[PATCH v2 2/2] arm: rk3568-evb1: add support for Rockchip SARADC

[Ahmad Fatoum]

On 23.06.21 09:52, Michael Riesch wrote:
> Signed-off-by: Michael Riesch <michael.riesch at wolfvision.net>
> ---
> v2:
> - add initial version
> 
>  arch/arm/dts/rk3568-evb1-v10.dts |  5 +++++
>  arch/arm/dts/rk3568.dtsi         | 12 ++++++++++++
>  2 files changed, 17 insertions(+)
> 
> diff --git a/arch/arm/dts/rk3568-evb1-v10.dts b/arch/arm/dts/rk3568-evb1-v10.dts
> index ca6f9c280..b8b4c85bf 100644
> --- a/arch/arm/dts/rk3568-evb1-v10.dts
> +++ b/arch/arm/dts/rk3568-evb1-v10.dts
> @@ -485,3 +485,8 @@
>  &uart2 {
>  	status = "okay";
>  };
> +
> +&saradc {
> +	vref-supply = <&vcca_1v8>;
> +	status = "okay";
> +};
> diff --git a/arch/arm/dts/rk3568.dtsi b/arch/arm/dts/rk3568.dtsi
> index 34d0b8a08..8a75a7e96 100644
> --- a/arch/arm/dts/rk3568.dtsi
> +++ b/arch/arm/dts/rk3568.dtsi
> @@ -817,6 +817,18 @@
>  		status = "disabled";
>  	};
> 
> +	saradc: saradc at fe720000 {
> +		compatible = "rockchip,rk3568-saradc";
> +		reg = <0x0 0xfe720000 0x0 0x100>;
> +		interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
> +		clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
> +		clock-names = "saradc", "apb_pclk";
> +		resets = <&cru SRST_P_SARADC>;
> +		reset-names = "saradc-apb";

Keep in mind the driver you added does _not_ trigger this reset.

> +		#io-channel-cells = <1>;
> +		status = "disabled";
> +	};
> +
>  	pinctrl: pinctrl {
>  		compatible = "rockchip,rk3568-pinctrl";
>  		rockchip,grf = <&grf>;
> --
> 2.20.1
> 
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