[PATCH v2 00/29] RISC-V: add BeagleV Beta board support
Ahmad Fatoum
a.fatoum at pengutronix.de
Fri Jun 18 21:50:26 PDT 2021
The changes allow barebox to run second stage (after ddrinit and second
boot) on the BeagleV beta board. It does everything necessary to support
Ethernet, MMC, GPIO, pinmux, pinconf, clock, reset, watchdog, HWRNG and
DMA between CPU and the cache-incoherent DMA masters.
The current vendor kernel doesn't care much for low-level
initialization, depending on pinmux, pinconf, clock and reset to happen
completely in the bootloader. This makes an initial bootloader port
much more complex, because you need not only care about the peripherals
you use yourself, but those that Linux may want to access to.
For this reason, there is a starfive-pwrseq driver that binds against
some nodes like the neural network accelerator, which we will probably
never support, but at least tickles it resets and enables its clocks.
Some peripherals require writing magic values into registers, which
this series doesn't do. If your boot hangs, consider checking out:
https://github.com/a3f/barebox/tree/beaglev
instead, which imports some vendor boot code to support more
peripherals. This series is sufficient to have barebox boot kernels that
do their own initialization though. Problem is there are no such kernels
yet ^^.
Candidates for further steps:
- Support more peripherals in starfive-pwrseq
- Get Designware i2c controller working, so we can use PMIC for reset
- Get Cadence QSPI working, so barebox can flash itself and use
environment on flash
- Figure out the ticket lottery stuff, so we can boot multi-core
- Replace ddrinit and secondboot with PBL, load from there opensbi
and then return to barebox proper
- Complete missing clock tree info when Documentation is available
I can use a hand impementing these, so patches are most certainly
welcome (Antony, I am looking at you ;-).
v1 was here:
https://lore.barebox.org/barebox/20210531073821.15257-1-a.fatoum@pengutronix.de/
v1 -> v2:
- Dropped untested PMIC and flash chip commits. i2c and qspi controller
drivers in tree don't yet work for BeagleV
- remove clocksource clutter from console
- import S-/M-Mode multi-image series, so we can build all images for
the same ISA in one go
- Drop barebox,provide-mac-address from OTP driver. This is now done
via nvmem-cells reference
- Replace coherent memory from SRAM allocator with non-1:1 mapping:
Give devices the cached <= 32 bit address, as they are
cache-incoherent anyway, and use the > 32 bit uncached address from
CPU side. Works beautifully
- Drop 64-bit-conversion for dw_mmc. Sascha did it for rk3568 and it
works for BeagleV too
- Check Designware ETH coherent memory allocation against mask
- Rebase on newest clock changes
- Disable clocks after resets (Sascha)
- Move repsonsibility of keeping reset-synchronous clocks needed
for normal operation enabled to drivers (Sascha, off-list)
- Handle fence.i trap in exception handler to support SoCs without
Zifencei ISA extension
- Add some static clock initialization to starfive-pwrseq driver
- Add pinctrl driver support
- Add GPIO driver support
- Add board support
Ahmad Fatoum (29):
clocksource: RISC-V: demote probe success messages to debug level
RISC-V: virt: select only one timer
RISC-V: extend multi-image to support both S- and M-Mode
RISC-V: cpuinfo: return some output for non-SBI systems as well
RISC-V: S-Mode: propagate Hart ID
RISC-V: erizo: make it easier to reuse ns16550 debug_ll
RISC-V: socs: add Kconfig entry for StarFive JH7100
nvmem: add StarFive OTP support
RISC-V: dma: support multiple dma_alloc_coherent backends
RISC-V: add exception support
RISC-V: support incoherent I-Cache
drivers: soc: sifive: add basic L2 cache controller driver
soc: starfive: add support for JH7100 incoherent interconnect
soc: sifive: l2_cache: enable maximum available cache ways
net: designware: fix non-1:1 mapped 64-bit systems
net: designware: add support for IP integrated into StarFive SoC
mci: allocate DMA-able memory
mci: allocate sector_buf on demand
dma: allocate 32-byte aligned buffers by default
mci: dw_mmc: add optional reset line
mci: dw_mmc: match against StarFive MMC compatibles
clk: add initial StarFive clock support
reset: add StarFive reset controller driver
watchdog: add StarFive watchdog driver
hw_random: add driver for RNG on StarFive SoC
reset: add device_reset_all helper
gpio: add support for StarFive GPIO controller
misc: add power sequencing driver for initializing StarFive
peripherals
RISC-V: StarFive: add board support for BeagleV Starlight
Documentation/boards/riscv.rst | 37 +
arch/riscv/Kconfig | 19 +-
arch/riscv/Kconfig.socs | 56 +-
arch/riscv/boards/Makefile | 1 +
arch/riscv/boards/beaglev/Makefile | 5 +
arch/riscv/boards/beaglev/board.c | 30 +
.../beaglev/defaultenv-beaglev/boot/buildroot | 13 +
.../beaglev/defaultenv-beaglev/boot/fedora | 16 +
.../defaultenv-beaglev/nv/boot.default | 1 +
arch/riscv/boards/beaglev/lowlevel.c | 18 +
arch/riscv/boards/erizo/lowlevel.c | 6 +-
arch/riscv/boards/hifive/lowlevel.c | 17 +-
arch/riscv/boot/board-dt-2nd.c | 4 +-
arch/riscv/boot/entry.c | 5 +-
arch/riscv/boot/entry.h | 6 +-
arch/riscv/boot/start.c | 15 +-
arch/riscv/boot/uncompress.c | 11 +-
arch/riscv/configs/starfive_defconfig | 131 +++
arch/riscv/cpu/Makefile | 4 +
arch/riscv/cpu/core.c | 40 +-
arch/riscv/cpu/dma.c | 74 ++
arch/riscv/cpu/interrupts.c | 139 +++
arch/riscv/cpu/mtrap.S | 30 +
arch/riscv/cpu/strap.S | 30 +
arch/riscv/dts/Makefile | 1 +
arch/riscv/dts/jh7100-beaglev-starlight.dts | 54 ++
arch/riscv/dts/jh7100-beaglev-starlight.dtsi | 369 ++++++++
arch/riscv/dts/jh7100.dtsi | 798 ++++++++++++++++++
arch/riscv/include/asm/asm-offsets.h | 1 +
arch/riscv/include/asm/barebox-riscv.h | 14 +-
arch/riscv/include/asm/barrier.h | 27 +
arch/riscv/include/asm/cacheflush.h | 16 +
arch/riscv/include/asm/debug_ll.h | 10 +-
arch/riscv/include/asm/dma.h | 48 +-
arch/riscv/include/asm/io.h | 10 +
arch/riscv/include/asm/irq.h | 107 +++
arch/riscv/include/asm/ptrace.h | 143 ++++
arch/riscv/include/asm/sbi.h | 8 +-
arch/riscv/include/asm/system.h | 61 ++
arch/riscv/include/asm/unwind.h | 9 +
arch/riscv/lib/asm-offsets.c | 46 +
arch/riscv/lib/bootm.c | 4 +-
arch/riscv/lib/cpuinfo.c | 56 +-
arch/riscv/lib/reloc.c | 8 +
arch/riscv/lib/sbi.c | 4 +
arch/riscv/lib/setupc.S | 2 +
commands/Kconfig | 4 +-
common/Kconfig | 11 +
common/globalvar.c | 21 +
common/oftree.c | 19 +-
drivers/Makefile | 2 +-
drivers/clk/Makefile | 1 +
drivers/clk/starfive/Makefile | 3 +
drivers/clk/starfive/clk.h | 64 ++
drivers/clk/starfive/jh7100-clkgen.c | 363 ++++++++
drivers/clocksource/timer-clint.c | 7 +-
drivers/clocksource/timer-riscv.c | 5 +-
drivers/gpio/Kconfig | 8 +
drivers/gpio/Makefile | 1 +
drivers/gpio/gpio-starfive-vic.c | 177 ++++
drivers/hw_random/Kconfig | 7 +
drivers/hw_random/Makefile | 1 +
drivers/hw_random/starfive-vic-rng.c | 208 +++++
drivers/mci/dw_mmc.c | 23 +-
drivers/mci/mci-core.c | 15 +-
drivers/misc/Kconfig | 10 +
drivers/misc/Makefile | 1 +
drivers/misc/starfive-pwrseq.c | 92 ++
drivers/net/Kconfig | 8 +
drivers/net/Makefile | 1 +
drivers/net/designware.c | 64 +-
drivers/net/designware.h | 29 +-
drivers/net/designware_starfive.c | 110 +++
drivers/nvmem/Kconfig | 8 +
drivers/nvmem/Makefile | 2 +
drivers/nvmem/starfive-otp.c | 201 +++++
drivers/pinctrl/pinctrl-single.c | 4 +-
drivers/reset/Kconfig | 6 +
drivers/reset/Makefile | 1 +
drivers/reset/core.c | 78 +-
drivers/reset/reset-starfive-vic.c | 234 +++++
drivers/soc/Makefile | 5 +
drivers/soc/sifive/Makefile | 1 +
drivers/soc/sifive/sifive_l2_cache.c | 136 +++
drivers/soc/starfive/Makefile | 1 +
drivers/soc/starfive/jh7100_dma.c | 55 ++
drivers/watchdog/Kconfig | 7 +
drivers/watchdog/Makefile | 1 +
drivers/watchdog/starfive_wdt.c | 106 +++
images/Makefile.riscv | 4 +
include/dma.h | 7 +-
include/dt-bindings/clock/starfive-jh7100.h | 203 +++++
.../reset-controller/starfive-jh7100.h | 126 +++
include/globalvar.h | 8 +
include/linux/reset.h | 7 +
include/pinctrl.h | 6 +
include/soc/sifive/l2_cache.h | 10 +
include/soc/starfive/rstgen.h | 41 +
include/soc/starfive/sysmain.h | 15 +
99 files changed, 4878 insertions(+), 154 deletions(-)
create mode 100644 arch/riscv/boards/beaglev/Makefile
create mode 100644 arch/riscv/boards/beaglev/board.c
create mode 100755 arch/riscv/boards/beaglev/defaultenv-beaglev/boot/buildroot
create mode 100755 arch/riscv/boards/beaglev/defaultenv-beaglev/boot/fedora
create mode 100644 arch/riscv/boards/beaglev/defaultenv-beaglev/nv/boot.default
create mode 100644 arch/riscv/boards/beaglev/lowlevel.c
create mode 100644 arch/riscv/configs/starfive_defconfig
create mode 100644 arch/riscv/cpu/dma.c
create mode 100644 arch/riscv/cpu/interrupts.c
create mode 100644 arch/riscv/cpu/mtrap.S
create mode 100644 arch/riscv/cpu/strap.S
create mode 100644 arch/riscv/dts/jh7100-beaglev-starlight.dts
create mode 100644 arch/riscv/dts/jh7100-beaglev-starlight.dtsi
create mode 100644 arch/riscv/dts/jh7100.dtsi
create mode 100644 arch/riscv/include/asm/asm-offsets.h
create mode 100644 arch/riscv/include/asm/barrier.h
create mode 100644 arch/riscv/include/asm/cacheflush.h
create mode 100644 arch/riscv/include/asm/irq.h
create mode 100644 arch/riscv/include/asm/ptrace.h
create mode 100644 arch/riscv/include/asm/system.h
create mode 100644 arch/riscv/include/asm/unwind.h
create mode 100644 drivers/clk/starfive/Makefile
create mode 100644 drivers/clk/starfive/clk.h
create mode 100644 drivers/clk/starfive/jh7100-clkgen.c
create mode 100644 drivers/gpio/gpio-starfive-vic.c
create mode 100644 drivers/hw_random/starfive-vic-rng.c
create mode 100644 drivers/misc/starfive-pwrseq.c
create mode 100644 drivers/net/designware_starfive.c
create mode 100644 drivers/nvmem/starfive-otp.c
create mode 100644 drivers/reset/reset-starfive-vic.c
create mode 100644 drivers/soc/Makefile
create mode 100644 drivers/soc/sifive/Makefile
create mode 100644 drivers/soc/sifive/sifive_l2_cache.c
create mode 100644 drivers/soc/starfive/Makefile
create mode 100644 drivers/soc/starfive/jh7100_dma.c
create mode 100644 drivers/watchdog/starfive_wdt.c
create mode 100644 include/dt-bindings/clock/starfive-jh7100.h
create mode 100644 include/dt-bindings/reset-controller/starfive-jh7100.h
create mode 100644 include/soc/sifive/l2_cache.h
create mode 100644 include/soc/starfive/rstgen.h
create mode 100644 include/soc/starfive/sysmain.h
--
2.29.2
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