[PATCH 2/2] ARM: i.MX: xload: consider ECC strength when reading page

[Sascha Hauer]

On Mon, Jun 14, 2021 at 03:14:22PM -0700, Trent Piepho wrote:
> On Tue, Jun 8, 2021 at 11:34 PM Andrej Picej <andrej.picej at norik.com> wrote:
> > On 8. 06. 21 14:38, Trent Piepho wrote:
> > > On Tue, Jun 8, 2021 at 12:23 AM Andrej Picej <andrej.picej at norik.com> wrote:
> > >> On 7. 06. 21 22:03, Trent Piepho wrote:
> > > Ok, so 4 ecc bits was used for testing, but your actual use case is
> > > for flash that uses 8 bits when NAND has 128 OOB bytes, which the
> > > current code uses a value different than 8?  My calculation is that
> > > 0x800+0x80 would use 18 bit ECC.
> >
> > Actually 8 ECC bits was used for testing. Maybe it was wrong that I
> > named EccBlockNEccType (from i.MX 6Dual/6Quad Applications Processor
> > Reference Manual) as ECC strength (in commit message) as it gets shifted
> > to the left for one bit to get ECC size in bits. So yes, we agree, 8 bit
> > ECC for 0x800+0x80 (4<<1 = 8) and 18 bit ECC for 0x800+0x80 (9<<1 = 18).
> 
> Ok, I see.  I discovered this too, as the kernel bug caused Linux to
> use 4 bit ECC instead of 8 bit. I instrumented Linux driver and found
> it was using 4 bit.  I inspected the FCB manually and it was 0x04, so
> 4 bit ECC is connect?  But I have all these NAND errors! I was sure it
> would be bad BCH config!  Maybe NAND timing?  Bad PCB?  Nope.  FCB ECC
> field is half the real ECC value and this is not documented in RM.  If
> the FCB is 0x04 that is called 8 bits in all BCH documentation in iMX
> RM and also Linux driver, dts properties, and so on.
> 
> > OK, I see. This is a valid point. Didn't really understand that updating
> > only 2nd stage barebox is a common practice. Do you know of any imx6
> > board that does that, because this xloader is imx6 specific?
> 
> I do not see any imx nand xloader users at all in mainlinux Barebox
> codebase.  Which is annoying, since I'm trying to boot barebox from
> NAND on iMX6ULL and there are no boards in barebox that do this.  So I
> have to do it from scratch, even though I know such boards exist and
> in fact you are using one.
> 
> Do I do not know of any specific imx6 boards that do this.  As there
> are apparently no imx boards booting barebox from nand....

There are several i.MX6 boards mainline that support booting from NAND,
one of them being the phyFLEX-i.MX6 board which I am using all day. It
doesn't use any xload mechanism, theres's only one stage in NAND. We
also have imx6_nand_start_image() which can be used when a xload
mechanism is desired for cases when the SDRAM shall be initialized in
code rather than using DCD data. This part indeed has no users in tree,
but there shouldn't be much to implement to get this working.

I wonder which parts are missing that make you think that booting from
NAND ist not supported?

> 
> I do know of a specific cyclone5 board that does this.
> 
> There is also plenty of documentation that calls for writing 2nd stage
> bootloader in Linux with nandwrite.  So I think it's reasonable
> someone would do this.  I think if I setup rauc to do a software
> update, I do not see support for FCB update, but there is a raw nand
> partition that can easily do 2nd stage bootloader.
> 
> But consider that even if barebox spl can support two different BCH
> configs on same nand device for booting, neither Barebox nor Linux
> support this concept at all.

At least the OMAP NAND driver in barebox supports different ECC configs
that are switchable during runtime. The ECC scheme once switched is used
for the whole device though, what's missing is indeed to attach an ECC
scheme to a partition rather than to the whole device. I have that dream
each time when hacking OMAP NAND...

Sascha

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