[PATCH 2/2] ARM: i.MX: nxp-imx8mm-evk: adjust DDR training order

[Lucas Stach]

This way we end up with the fastest DDR speed when training is finished
and don't need to rely on TF-A to switch into a higher DDR speed.

Signed-off-by: Lucas Stach <l.stach at pengutronix.de>
---
 arch/arm/boards/nxp-imx8mm-evk/lpddr4-timing.c | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/arch/arm/boards/nxp-imx8mm-evk/lpddr4-timing.c b/arch/arm/boards/nxp-imx8mm-evk/lpddr4-timing.c
index b164bdec07f1..33ef5542a364 100644
--- a/arch/arm/boards/nxp-imx8mm-evk/lpddr4-timing.c
+++ b/arch/arm/boards/nxp-imx8mm-evk/lpddr4-timing.c
@@ -118,7 +118,7 @@ static struct dram_cfg_param lpddr4_ddrc_cfg[] = {
 	{ DDRC_FREQ2_INIT7(0), 0x0006004a },
 
 	/* boot start point */
-	{ DDRC_MSTR2(0), 0x2 }, //DDRC_MSTR2
+	{ DDRC_MSTR2(0), 0x0 }, //DDRC_MSTR2
 };
 
 /* PHY Initialize Configuration */
@@ -1940,12 +1940,6 @@ static struct dram_fsp_msg lpddr4_dram_fsp_msg[] = {
 		.fw_type = FW_1D_IMAGE,
 		.fsp_cfg = lpddr4_fsp0_cfg,
 		.fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_cfg),
-	}, {
-		/* P0 3000mts 2D */
-		.drate = 3000,
-		.fw_type = FW_2D_IMAGE,
-		.fsp_cfg = lpddr4_fsp0_2d_cfg,
-		.fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_2d_cfg),
 	}, {
 		/* P1 400mts 1D */
 		.drate = 400,
@@ -1958,6 +1952,12 @@ static struct dram_fsp_msg lpddr4_dram_fsp_msg[] = {
 		.fw_type = FW_1D_IMAGE,
 		.fsp_cfg = lpddr4_fsp2_cfg,
 		.fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp2_cfg),
+	}, {
+		/* P0 3000mts 2D */
+		.drate = 3000,
+		.fw_type = FW_2D_IMAGE,
+		.fsp_cfg = lpddr4_fsp0_2d_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_2d_cfg),
 	},
 };
 
-- 
2.20.1