[PATCH v2] ARM: phytec-phycard-imx27: Add debug UART support

Florian Bäuerle florian.baeuerle at allegion.com
Mon Sep 10 01:05:12 PDT 2018


Signed-off-by: Florian Bäuerle <florian.baeuerle at allegion.com>
---
 arch/arm/boards/phytec-phycard-imx27/lowlevel.c | 16 ++++++++++++++++
 arch/arm/mach-imx/include/mach/debug_ll.h       | 13 +++++++++++++
 include/serial/imx-uart.h                       |  5 +++++
 3 files changed, 34 insertions(+)

diff --git a/arch/arm/boards/phytec-phycard-imx27/lowlevel.c b/arch/arm/boards/phytec-phycard-imx27/lowlevel.c
index e1132e0..a1f12e8 100644
--- a/arch/arm/boards/phytec-phycard-imx27/lowlevel.c
+++ b/arch/arm/boards/phytec-phycard-imx27/lowlevel.c
@@ -14,6 +14,8 @@
 #include <mach/imx-pll.h>
 #include <mach/esdctl.h>
 #include <mach/imx-nand.h>
+#include <mach/debug_ll.h>
+#include <serial/imx-uart.h>
 
 #define ESDCTL0_VAL (ESDCTL0_SDE | ESDCTL0_ROW13 | ESDCTL0_COL10)
 
@@ -58,6 +60,18 @@ static void sdram_init(void)
 			MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
 }
 
+static void setup_uart(void)
+{
+	/* Set PE[12-15] use, direction, function and pull-up */
+	writel(0xfffc0f27, MX27_GPIO5_BASE_ADDR + 0x20);
+	writel(0x00005000, MX27_GPIO5_BASE_ADDR);
+	writel(0x00000000, MX27_GPIO5_BASE_ADDR + 0x38);
+	writel(0xffff0fff, MX27_GPIO5_BASE_ADDR + 0x40);
+
+	imx27_ungate_all_peripherals();
+	imx27_uart_setup_ll();
+}
+
 void __bare_init __naked phytec_phycard_imx27_common_init(void *fdt)
 {
 	unsigned long r;
@@ -97,6 +111,8 @@ void __bare_init __naked phytec_phycard_imx27_common_init(void *fdt)
 		MX27_CSCR_MSHC_SEL, MX27_CCM_BASE_ADDR + MX27_CSCR);
 
 	sdram_init();
+	if (IS_ENABLED(CONFIG_DEBUG_LL))
+		setup_uart();
 
 	imx27_barebox_boot_nand_external(fdt);
 }
diff --git a/arch/arm/mach-imx/include/mach/debug_ll.h b/arch/arm/mach-imx/include/mach/debug_ll.h
index 1550e05..e045a1f 100644
--- a/arch/arm/mach-imx/include/mach/debug_ll.h
+++ b/arch/arm/mach-imx/include/mach/debug_ll.h
@@ -56,6 +56,12 @@
 #error "unknown i.MX debug uart soc type"
 #endif
 
+static inline void imx27_uart_setup_ll(void)  {
+	void *base = IOMEM(IMX_UART_BASE(IMX_DEBUG_SOC,
+				CONFIG_DEBUG_IMX_UART_PORT));
+	imx27_uart_setup(base);
+}
+
 static inline void imx50_uart_setup_ll(void)
 {
 	void *base = IOMEM(IMX_UART_BASE(IMX_DEBUG_SOC, CONFIG_DEBUG_IMX_UART_PORT));
@@ -121,6 +127,7 @@ static inline void PUTC_LL(int c)
 
 #else
 
+static inline void imx27_uart_setup_ll(void) {}
 static inline void imx50_uart_setup_ll(void) {}
 static inline void imx51_uart_setup_ll(void) {}
 static inline void imx53_uart_setup_ll(void) {}
@@ -138,6 +145,12 @@ static inline void imx_ungate_all_peripherals(void __iomem *ccmbase)
 		writel(0xffffffff, ccmbase + i);
 }
 
+static inline void imx27_ungate_all_peripherals(void)
+{
+	writel(0xfffffbff, IOMEM(MX27_CCM_BASE_ADDR) + MX27_PCCR0);
+	writel(0xfffffffc, IOMEM(MX27_CCM_BASE_ADDR) + MX27_PCCR1);
+}
+
 static inline void imx6_ungate_all_peripherals(void)
 {
 	imx_ungate_all_peripherals(IOMEM(MX6_CCM_BASE_ADDR));
diff --git a/include/serial/imx-uart.h b/include/serial/imx-uart.h
index c236065..0c033c2 100644
--- a/include/serial/imx-uart.h
+++ b/include/serial/imx-uart.h
@@ -155,6 +155,11 @@ static inline void imx_uart_set_dte(void __iomem *uartbase)
 	writel(ufcr, uartbase + UFCR);
 }
 
+static inline void imx27_uart_setup(void __iomem *uartbase)
+{
+	imx_uart_setup(uartbase, 66500000);
+}
+
 static inline void imx50_uart_setup(void __iomem *uartbase)
 {
 	imx_uart_setup(uartbase, 66666666);
-- 
1.8.3.1




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