[PATCH 76/78] ARM: create separate mmu_64.h file
Sascha Hauer
s.hauer at pengutronix.de
Fri Mar 16 05:53:52 PDT 2018
cpu/mmu.h has nothing in common for the 32bit and 64bit variant. Make it
two separate files.
Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
arch/arm/cpu/mmu.h | 47 -----------------------------------------------
arch/arm/cpu/mmu_64.c | 2 +-
arch/arm/cpu/mmu_64.h | 37 +++++++++++++++++++++++++++++++++++++
3 files changed, 38 insertions(+), 48 deletions(-)
create mode 100644 arch/arm/cpu/mmu_64.h
diff --git a/arch/arm/cpu/mmu.h b/arch/arm/cpu/mmu.h
index 5803cb6a83..79ebc80d7d 100644
--- a/arch/arm/cpu/mmu.h
+++ b/arch/arm/cpu/mmu.h
@@ -1,53 +1,6 @@
#ifndef __ARM_MMU_H
#define __ARM_MMU_H
-#ifdef CONFIG_CPU_64v8
-
-#ifndef __ASSEMBLY__
-
-static inline void set_ttbr_tcr_mair(int el, uint64_t table, uint64_t tcr, uint64_t attr)
-{
- asm volatile("dsb sy");
- if (el == 1) {
- asm volatile("msr ttbr0_el1, %0" : : "r" (table) : "memory");
- asm volatile("msr tcr_el1, %0" : : "r" (tcr) : "memory");
- asm volatile("msr mair_el1, %0" : : "r" (attr) : "memory");
- } else if (el == 2) {
- asm volatile("msr ttbr0_el2, %0" : : "r" (table) : "memory");
- asm volatile("msr tcr_el2, %0" : : "r" (tcr) : "memory");
- asm volatile("msr mair_el2, %0" : : "r" (attr) : "memory");
- } else if (el == 3) {
- asm volatile("msr ttbr0_el3, %0" : : "r" (table) : "memory");
- asm volatile("msr tcr_el3, %0" : : "r" (tcr) : "memory");
- asm volatile("msr mair_el3, %0" : : "r" (attr) : "memory");
- } else {
- hang();
- }
- asm volatile("isb");
-}
-
-static inline uint64_t get_ttbr(int el)
-{
- uint64_t val;
- if (el == 1) {
- asm volatile("mrs %0, ttbr0_el1" : "=r" (val));
- } else if (el == 2) {
- asm volatile("mrs %0, ttbr0_el2" : "=r" (val));
- } else if (el == 3) {
- asm volatile("mrs %0, ttbr0_el3" : "=r" (val));
- } else {
- hang();
- }
-
- return val;
-}
-
-void mmu_early_enable(uint64_t membase, uint64_t memsize, uint64_t _ttb);
-
-#endif
-
-#endif /* CONFIG_CPU_64v8 */
-
#ifdef CONFIG_MMU
void __mmu_cache_on(void);
void __mmu_cache_off(void);
diff --git a/arch/arm/cpu/mmu_64.c b/arch/arm/cpu/mmu_64.c
index 094bc0ac62..7f29ae7623 100644
--- a/arch/arm/cpu/mmu_64.c
+++ b/arch/arm/cpu/mmu_64.c
@@ -32,7 +32,7 @@
#include <memory.h>
#include <asm/system_info.h>
-#include "mmu.h"
+#include "mmu_64.h"
#define CACHED_MEM (PTE_BLOCK_MEMTYPE(MT_NORMAL) | \
PTE_BLOCK_OUTER_SHARE | \
diff --git a/arch/arm/cpu/mmu_64.h b/arch/arm/cpu/mmu_64.h
new file mode 100644
index 0000000000..cc01db0db9
--- /dev/null
+++ b/arch/arm/cpu/mmu_64.h
@@ -0,0 +1,37 @@
+
+static inline void set_ttbr_tcr_mair(int el, uint64_t table, uint64_t tcr, uint64_t attr)
+{
+ asm volatile("dsb sy");
+ if (el == 1) {
+ asm volatile("msr ttbr0_el1, %0" : : "r" (table) : "memory");
+ asm volatile("msr tcr_el1, %0" : : "r" (tcr) : "memory");
+ asm volatile("msr mair_el1, %0" : : "r" (attr) : "memory");
+ } else if (el == 2) {
+ asm volatile("msr ttbr0_el2, %0" : : "r" (table) : "memory");
+ asm volatile("msr tcr_el2, %0" : : "r" (tcr) : "memory");
+ asm volatile("msr mair_el2, %0" : : "r" (attr) : "memory");
+ } else if (el == 3) {
+ asm volatile("msr ttbr0_el3, %0" : : "r" (table) : "memory");
+ asm volatile("msr tcr_el3, %0" : : "r" (tcr) : "memory");
+ asm volatile("msr mair_el3, %0" : : "r" (attr) : "memory");
+ } else {
+ hang();
+ }
+ asm volatile("isb");
+}
+
+static inline uint64_t get_ttbr(int el)
+{
+ uint64_t val;
+ if (el == 1) {
+ asm volatile("mrs %0, ttbr0_el1" : "=r" (val));
+ } else if (el == 2) {
+ asm volatile("mrs %0, ttbr0_el2" : "=r" (val));
+ } else if (el == 3) {
+ asm volatile("mrs %0, ttbr0_el3" : "=r" (val));
+ } else {
+ hang();
+ }
+
+ return val;
+}
--
2.16.1
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