From s.hauer at pengutronix.de  Thu Mar  1 00:47:52 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Thu,  1 Mar 2018 09:47:52 +0100
Subject: [PATCH] ARM: dts: am33xx: do not delete no longer existing clocks
Message-ID: <20180301084752.12413-1-s.hauer@pengutronix.de>

Several clocks are removed from the am33xx dts files with v4.16-rc1.
Remove the corresponding /delete-node/ directives aswell to avoid
dtc breakage.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/dts/am33xx-clocks-strip.dtsi | 13 -------------
 1 file changed, 13 deletions(-)

diff --git a/arch/arm/dts/am33xx-clocks-strip.dtsi b/arch/arm/dts/am33xx-clocks-strip.dtsi
index 831f1630f9..92906deafe 100644
--- a/arch/arm/dts/am33xx-clocks-strip.dtsi
+++ b/arch/arm/dts/am33xx-clocks-strip.dtsi
@@ -34,10 +34,8 @@
 /delete-node/ &dpll_per_m2_ck;
 /delete-node/ &dpll_per_m2_div4_wkupdm_ck;
 /delete-node/ &dpll_per_m2_div4_ck;
-/delete-node/ &cefuse_fck;
 /delete-node/ &clk_24mhz;
 /delete-node/ &clkdiv32k_ck;
-/delete-node/ &clkdiv32k_ick;
 /delete-node/ &l3_gclk;
 /delete-node/ &pruss_ocp_gclk;
 /delete-node/ &mmu_fck;
@@ -59,21 +57,10 @@
 /delete-node/ &l4ls_gclk;
 /delete-node/ &sysclk_div_ck;
 /delete-node/ &gpio0_dbclk_mux_ck;
-/delete-node/ &gpio0_dbclk;
-/delete-node/ &gpio1_dbclk;
-/delete-node/ &gpio2_dbclk;
-/delete-node/ &gpio3_dbclk;
 /delete-node/ &lcd_gclk;
 /delete-node/ &mmc_clk;
 /delete-node/ &gfx_fclk_clksel_ck;
 /delete-node/ &gfx_fck_div_ck;
 /delete-node/ &sysclkout_pre_ck;
 /delete-node/ &clkout2_div_ck;
-/delete-node/ &dbg_sysclk_ck;
-/delete-node/ &dbg_clka_ck;
-/delete-node/ &stm_pmd_clock_mux_ck;
-/delete-node/ &trace_pmd_clk_mux_ck;
-/delete-node/ &stm_clk_div_ck;
-/delete-node/ &trace_clk_div_ck;
 /delete-node/ &clkout2_ck;
-/delete-node/ &clk_24mhz_clkdm;
-- 
2.16.1



From s.hauer at pengutronix.de  Thu Mar  1 00:48:21 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Thu, 1 Mar 2018 09:48:21 +0100
Subject: [PATCH v3 0/9] ratp: new generic RATP command support
In-Reply-To: <20180224150121.28309-1-aleksander@aleksander.es>
References: <20180224150121.28309-1-aleksander@aleksander.es>
Message-ID: <20180301084821.3aznzoovyik254uj@pengutronix.de>

On Sat, Feb 24, 2018 at 04:01:12PM +0100, Aleksander Morgado wrote:
> This v3 series includes new md, mw and reset operations in bbremote, using the new binary API interface. The actual commits including the new RATP commands include the bbremote changes as well.
> 
> An additional patch is also included to add a reference to the third-party libratp-barebox and ratp-barebox-cli tools.
> 
> Aleksander Morgado (9):
>   ratp: implement generic command support
>   ratp: moved logic to its own subdirectory
>   ratp: allow building without full console support
>   ratp: implement ping as a standard ratp command
>   ratp: implement getenv as a standard ratp command
>   ratp: use xstrndup() instead of a custom xmemdup_add_zero()
>   ratp: new md and mw commands
>   ratp: new reset command
>   docs: add reference to libratp-barebox in the remote-control docs

Applied, thanks

Sascha

> 
>  Documentation/user/remote-control.rst     |   7 ++
>  arch/arm/lib32/barebox.lds.S              |   4 +
>  arch/arm/lib64/barebox.lds.S              |   4 +
>  arch/blackfin/boards/ipe337/barebox.lds.S |   5 +-
>  arch/mips/lib/barebox.lds.S               |   4 +
>  arch/nios2/cpu/barebox.lds.S              |   5 +-
>  arch/openrisc/cpu/barebox.lds.S           |   4 +
>  arch/ppc/boards/pcm030/barebox.lds.S      |   4 +
>  arch/ppc/mach-mpc85xx/barebox.lds.S       |   4 +
>  arch/sandbox/board/barebox.lds.S          |   5 +
>  arch/x86/lib/barebox.lds.S                |   7 ++
>  arch/x86/mach-efi/elf_ia32_efi.lds.S      |   5 +
>  arch/x86/mach-efi/elf_x86_64_efi.lds.S    |   5 +
>  common/Kconfig                            |  13 +-
>  common/Makefile                           |   3 +-
>  common/module.lds.S                       |   2 +
>  common/ratp/Kconfig                       |  14 +++
>  common/ratp/Makefile                      |   6 +
>  common/ratp/getenv.c                      |  51 ++++++++
>  common/ratp/md.c                          | 202 ++++++++++++++++++++++++++++++
>  common/ratp/mw.c                          | 173 +++++++++++++++++++++++++
>  common/ratp/ping.c                        |  40 ++++++
>  common/{ => ratp}/ratp.c                  | 156 +++++++++++------------
>  common/ratp/reset.c                       |  55 ++++++++
>  fs/Kconfig                                |   2 +-
>  include/asm-generic/barebox.lds.h         |   2 +
>  include/ratp_bb.h                         |  52 ++++++++
>  lib/Kconfig                               |   2 +-
>  lib/readline.c                            |   2 +-
>  scripts/remote/controller.py              |  27 ++++
>  scripts/remote/main.py                    |  51 ++++++++
>  scripts/remote/messages.py                | 105 ++++++++++++++++
>  32 files changed, 918 insertions(+), 103 deletions(-)
>  create mode 100644 common/ratp/Kconfig
>  create mode 100644 common/ratp/Makefile
>  create mode 100644 common/ratp/getenv.c
>  create mode 100644 common/ratp/md.c
>  create mode 100644 common/ratp/mw.c
>  create mode 100644 common/ratp/ping.c
>  rename common/{ => ratp}/ratp.c (81%)
>  create mode 100644 common/ratp/reset.c
> 
> --
> 2.15.1
> 

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From s.hauer at pengutronix.de  Thu Mar  1 00:59:39 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Thu, 1 Mar 2018 09:59:39 +0100
Subject: [PATCH] mtd: spi-nor: add support for w25q16dw
In-Reply-To: <20180228093820.19423-1-m.grzeschik@pengutronix.de>
References: <20180228093820.19423-1-m.grzeschik@pengutronix.de>
Message-ID: <20180301085939.36ot5tfnxprvene4@pengutronix.de>

On Wed, Feb 28, 2018 at 10:38:20AM +0100, Michael Grzeschik wrote:
> Signed-off-by: Michael Grzeschik <m.grzeschik at pengutronix.de>
> ---
>  drivers/mtd/spi-nor/spi-nor.c | 1 +
>  1 file changed, 1 insertion(+)

Applied, although I would really prefer if we could start keeping the
table in barebox in sync with the one from the kernel.

Sascha

> 
> diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
> index 5cf650c0e2..057638ec5a 100644
> --- a/drivers/mtd/spi-nor/spi-nor.c
> +++ b/drivers/mtd/spi-nor/spi-nor.c
> @@ -641,6 +641,7 @@ static const struct spi_device_id spi_nor_ids[] = {
>  	{ "w25q20cl", INFO(0xef4012, 0, 64 * 1024,  4, SECT_4K) },
>  	{ "w25q20bw", INFO(0xef5012, 0, 64 * 1024,  4, SECT_4K) },
>  	{ "w25q20ew", INFO(0xef6012, 0, 64 * 1024,  4, SECT_4K) },
> +	{ "w25q16dw", INFO(0xef6015, 0, 64 * 1024, 32, SECT_4K) },
>  	{ "w25q32", INFO(0xef4016, 0, 64 * 1024,  64, SECT_4K) },
>  	{ "w25q32dw", INFO(0xef6016, 0, 64 * 1024,  64, SECT_4K) },
>  	{ "w25x64", INFO(0xef3017, 0, 64 * 1024, 128, SECT_4K) },
> -- 
> 2.16.1
> 
> 
> _______________________________________________
> barebox mailing list
> barebox at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/barebox
> 

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From s.hauer at pengutronix.de  Thu Mar  1 01:02:04 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Thu, 1 Mar 2018 10:02:04 +0100
Subject: [PATCH] ARM: dts: remove "delete" entry for deleted clocks
In-Reply-To: <20180228180121.31539-1-mail@schmidt-andreas.de>
References: <20180228180121.31539-1-mail@schmidt-andreas.de>
Message-ID: <20180301090204.6xcfru5d3prdhapn@pengutronix.de>

Hi Andreas,

On Wed, Feb 28, 2018 at 07:01:21PM +0100, Andreas Schmidt wrote:
> After updete to v4.16-rc1 some clocks ware deleted from src dts.
> This patch remove "delete" entry for this clocks from
> am33xx-clocks-strip.dtsi too.
> 
> Signed-off-by: Andreas Schmidt <mail at schmidt-andreas.de>

I should have read this mail *before* creating the same patch.

Sascha

> ---
>  arch/arm/dts/am33xx-clocks-strip.dtsi | 13 -------------
>  1 file changed, 13 deletions(-)
> 
> diff --git a/arch/arm/dts/am33xx-clocks-strip.dtsi b/arch/arm/dts/am33xx-clocks-strip.dtsi
> index 831f1630f..92906deaf 100644
> --- a/arch/arm/dts/am33xx-clocks-strip.dtsi
> +++ b/arch/arm/dts/am33xx-clocks-strip.dtsi
> @@ -34,10 +34,8 @@
>  /delete-node/ &dpll_per_m2_ck;
>  /delete-node/ &dpll_per_m2_div4_wkupdm_ck;
>  /delete-node/ &dpll_per_m2_div4_ck;
> -/delete-node/ &cefuse_fck;
>  /delete-node/ &clk_24mhz;
>  /delete-node/ &clkdiv32k_ck;
> -/delete-node/ &clkdiv32k_ick;
>  /delete-node/ &l3_gclk;
>  /delete-node/ &pruss_ocp_gclk;
>  /delete-node/ &mmu_fck;
> @@ -59,21 +57,10 @@
>  /delete-node/ &l4ls_gclk;
>  /delete-node/ &sysclk_div_ck;
>  /delete-node/ &gpio0_dbclk_mux_ck;
> -/delete-node/ &gpio0_dbclk;
> -/delete-node/ &gpio1_dbclk;
> -/delete-node/ &gpio2_dbclk;
> -/delete-node/ &gpio3_dbclk;
>  /delete-node/ &lcd_gclk;
>  /delete-node/ &mmc_clk;
>  /delete-node/ &gfx_fclk_clksel_ck;
>  /delete-node/ &gfx_fck_div_ck;
>  /delete-node/ &sysclkout_pre_ck;
>  /delete-node/ &clkout2_div_ck;
> -/delete-node/ &dbg_sysclk_ck;
> -/delete-node/ &dbg_clka_ck;
> -/delete-node/ &stm_pmd_clock_mux_ck;
> -/delete-node/ &trace_pmd_clk_mux_ck;
> -/delete-node/ &stm_clk_div_ck;
> -/delete-node/ &trace_clk_div_ck;
>  /delete-node/ &clkout2_ck;
> -/delete-node/ &clk_24mhz_clkdm;
> -- 
> 2.14.1
> 
> 
> _______________________________________________
> barebox mailing list
> barebox at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/barebox
> 

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From s.hauer at pengutronix.de  Thu Mar  1 01:03:32 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Thu, 1 Mar 2018 10:03:32 +0100
Subject: [PATCH v1 1/2] watchdog: ar9344-wdt: disable watchdog in probe
In-Reply-To: <20180228172206.12823-1-linux@rempel-privat.de>
References: <20180228172206.12823-1-linux@rempel-privat.de>
Message-ID: <20180301090332.g2nq3rzcxvtsmgx2@pengutronix.de>

On Wed, Feb 28, 2018 at 06:22:05PM +0100, Oleksij Rempel wrote:
> This should avoid of triggering reset if we boot barebox from
> barebox.
> 
> Signed-off-by: Oleksij Rempel <linux at rempel-privat.de>
> ---
>  drivers/watchdog/ar9344_wdt.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/watchdog/ar9344_wdt.c b/drivers/watchdog/ar9344_wdt.c
> index d570cb40f..b61786b1b 100644
> --- a/drivers/watchdog/ar9344_wdt.c
> +++ b/drivers/watchdog/ar9344_wdt.c
> @@ -101,6 +101,8 @@ static int ar9344_wdt_probe(struct device_d *dev)
>  	dev->priv = priv;
>  
>  	ar9344_watchdog_detect_reset_source(priv);
> +	/* disable watchdog on probe */
> +	iowrite32be(0, priv->base + AR9344_WD_REG_CTRL);

Do we really want this? I would assume that if the watchdog is enabled
here, then it is enabled on purpose and disabling it just bypasses this
purpose.

Sascha


-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From s.hauer at pengutronix.de  Thu Mar  1 01:04:02 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Thu, 1 Mar 2018 10:04:02 +0100
Subject: [PATCH v1 2/2] MIPS: dts: enable heartbeat led for
 ar9331-dptechnics-dpt-module
In-Reply-To: <20180228172206.12823-2-linux@rempel-privat.de>
References: <20180228172206.12823-1-linux@rempel-privat.de>
 <20180228172206.12823-2-linux@rempel-privat.de>
Message-ID: <20180301090402.rqoyjdlgoxkrzi2d@pengutronix.de>

On Wed, Feb 28, 2018 at 06:22:06PM +0100, Oleksij Rempel wrote:
> Signed-off-by: Oleksij Rempel <linux at rempel-privat.de>
> ---
>  arch/mips/dts/ar9331-dptechnics-dpt-module.dts | 6 ++++++
>  1 file changed, 6 insertions(+)
> 

Applied, thanks

Sascha

> diff --git a/arch/mips/dts/ar9331-dptechnics-dpt-module.dts b/arch/mips/dts/ar9331-dptechnics-dpt-module.dts
> index 39eb36600..2c38bbc09 100644
> --- a/arch/mips/dts/ar9331-dptechnics-dpt-module.dts
> +++ b/arch/mips/dts/ar9331-dptechnics-dpt-module.dts
> @@ -12,6 +12,12 @@
>  			device-path = &spiflash, "partname:barebox-environment";
>  		};
>  	};
> +
> +	leds {
> +		system {
> +			barebox,default-trigger = "heartbeat";
> +		};
> +	};
>  };
>  
>  &spiflash {
> -- 
> 2.14.1
> 
> 
> _______________________________________________
> barebox mailing list
> barebox at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/barebox
> 

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From s.hauer at pengutronix.de  Thu Mar  1 03:07:29 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Thu, 1 Mar 2018 12:07:29 +0100
Subject: MIPS parallel build breakage
Message-ID: <20180301110729.pvdxqjqul7klrjyr@pengutronix.de>

Hi Sam and Antony,

(Antony because you introduced this and Sam because you have intimate
knowledge with our build system ;)

I am trying to solve a problem that annoys me for some years now. The
problem is that the MIPS defconfigs regularly fail in my autobuilder.
I usually help myself with trying it again and most of the time it
then works, but doing this for years increases the pressure to do
something.

What happens is that the MIPS builds use include/generated/compile.h:

> arch/mips/include/asm/pbl_macros.h:28:#include <generated/compile.h>

This often ends in:

> In file included from arch/mips/boot/start.S:20:0: arch/mips/include/asm/pbl_macros.h:28:31:
> fatal error: generated/compile.h: No such file or directory
> compilation terminated.

include/generated/compile.h is generated in common/Makefile:

> include/generated/compile.h: FORCE
> 	@$($(quiet)chk_compile.h)
> 	$(Q)$(CONFIG_SHELL) $(srctree)/scripts/mkcompile_h $@ \
> 	"$(UTS_MACHINE)" "$(CC) $(KBUILD_CFLAGS)"

Other users of this file add an explicit dependency on it:

> # dependencies on generated files need to be listed explicitly
> $(obj)/version.o: include/generated/compile.h

This only seems to work though when the dependent file is in the same
directory, but not when the file is in arch/mips/boot/.

I tried doing the include/generated/compile.h in Makefile instead of
common/Makefile, but then the version counting gets confused and causes
unnecessary rebuilds.

Any ideas how to solve this?

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From s.hauer at pengutronix.de  Thu Mar  1 03:31:05 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Thu,  1 Mar 2018 12:31:05 +0100
Subject: [PATCH] ARM: am335x: beaglebone: Fix DDR register values
Message-ID: <20180301113105.18150-1-s.hauer@pengutronix.de>

For the DDR2 PHY register values there are tons of warnings that more
than 32bit are required to store the values. Looking at the reference
manual it seems only the lower ten bits have any meaning, so drop all
other values.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/boards/beaglebone/lowlevel.c | 26 ++++++--------------------
 1 file changed, 6 insertions(+), 20 deletions(-)

diff --git a/arch/arm/boards/beaglebone/lowlevel.c b/arch/arm/boards/beaglebone/lowlevel.c
index a56b4b6240..f2e1690b15 100644
--- a/arch/arm/boards/beaglebone/lowlevel.c
+++ b/arch/arm/boards/beaglebone/lowlevel.c
@@ -48,26 +48,12 @@ static const struct am33xx_emif_regs ddr2_regs = {
 };
 
 static const struct am33xx_ddr_data ddr2_data = {
-	.rd_slave_ratio0        = (DDR2_RD_DQS << 30) | (DDR2_RD_DQS << 20) |
-				(DDR2_RD_DQS << 10) | (DDR2_RD_DQS << 0),
-	.wr_dqs_slave_ratio0    = (DDR2_WR_DQS << 30) | (DDR2_WR_DQS << 20) |
-				(DDR2_WR_DQS << 10) | (DDR2_WR_DQS << 0),
-	.wrlvl_init_ratio0	= (DDR2_PHY_WRLVL << 30) |
-				(DDR2_PHY_WRLVL << 20) |
-				(DDR2_PHY_WRLVL << 10) |
-				(DDR2_PHY_WRLVL << 0),
-	.gatelvl_init_ratio0	= (DDR2_PHY_GATELVL << 30) |
-				(DDR2_PHY_GATELVL << 20) |
-				(DDR2_PHY_GATELVL << 10) |
-				(DDR2_PHY_GATELVL << 0),
-	.fifo_we_slave_ratio0	= (DDR2_PHY_FIFO_WE << 30) |
-				(DDR2_PHY_FIFO_WE << 20) |
-				(DDR2_PHY_FIFO_WE << 10) |
-				(DDR2_PHY_FIFO_WE << 0),
-	.wr_slave_ratio0        = (DDR2_PHY_WR_DATA << 30) |
-				(DDR2_PHY_WR_DATA << 20) |
-				(DDR2_PHY_WR_DATA << 10) |
-				(DDR2_PHY_WR_DATA << 0),
+	.rd_slave_ratio0        = DDR2_RD_DQS,
+	.wr_dqs_slave_ratio0    = DDR2_WR_DQS,
+	.wrlvl_init_ratio0	= DDR2_PHY_WRLVL,
+	.gatelvl_init_ratio0	= DDR2_PHY_GATELVL,
+	.fifo_we_slave_ratio0	= DDR2_PHY_FIFO_WE,
+	.wr_slave_ratio0        = DDR2_PHY_WR_DATA,
 	.use_rank0_delay	= 0x01,
 	.dll_lock_diff0		= 0x0,
 };
-- 
2.16.1



From giorgio.nicole at arcor.de  Thu Mar  1 06:23:33 2018
From: giorgio.nicole at arcor.de (Giorgio Dal Molin)
Date: Thu, 1 Mar 2018 15:23:33 +0100 (CET)
Subject: problems with am335x_sdram_size()
Message-ID: <377910125.70611.1519914213534@mail.vodafone.de>

Hi,

working with the TI AM335x Evaluation Module I noticed that the function
am335x_sdram_size() always returns 0 instead of the computed sdram size.

I could trace back the problem to the fact that the function does its 
computation based on the value of the register CM_EMIF_SDRAM_CONFIG
(addr. 0x44e10110), but this register is not written to by the function
am33xx_config_sdram() and just returns its initial value (0).
The datasheet says CM_EMIF_SDRAM_CONFIG should have the same value as
AM33XX_EMIF4_0_REG(SDRAM_CONFIG) (addr. 0x4c000008)

To conclude, to fix the problem with am335x_sdram_size() you can either
use AM33XX_EMIF4_0_REG(SDRAM_CONFIG) instead of CM_EMIF_SDRAM_CONFIG
in am335x_sdram_size()

 or

initialize CM_EMIF_SDRAM_CONFIG in am33xx_config_sdram() with the same value
as AM33XX_EMIF4_0_REG(SDRAM_CONFIG) (regs->sdram_config)

giorgio


From 548708880 at qq.com  Thu Mar  1 08:30:37 2018
From: 548708880 at qq.com (duhuanpeng)
Date: Fri, 2 Mar 2018 00:30:37 +0800
Subject: freescale-mx28-evk run from ram
Message-ID: <001601d3b17a$a176cbc0$e4646340$@qq.com>+C2394485D68CB85A

Dear all,

Happy Yuanxiao(Lantern) Festival!

I have a modified mx28-evk board, I want to run barebox on it, but I don?t want to make change to the flash.

In System.map
00000000 T __image_start
00000000 T start
00000000 T _stext
00000000 T _text
00000004 T __bare_init_start
00000004 T get_runtime_offset
00000014 t linkadr
00000018 T __ld_var_base
00000018 T __ld_var__text
00000020 t ___text
00000024 T __ld_var___rel_dyn_start
0000002c t ____rel_dyn_start
00000030 T __ld_var___rel_dyn_end
00000038 t ____rel_dyn_end
0000003c T __ld_var___dynsym_start
00000044 t ____dynsym_start
00000048 T __ld_var___dynsym_end
00000050 t ____dynsym_end
00000054 T __ld_var___bss_start
0000005c t ____bss_start
00000060 T __ld_var___bss_stop
00000068 t ____bss_stop

So, I load barebox.bin to address 0x00000000:

Hit any key to stop autoboot:  0 
MX28 U-Boot > tftpboot 0 barebox.bin
Using FEC0 device
TFTP from server 192.168.12.61; our IP address is 192.168.12.62
Filename 'barebox.bin'.
Load address: 0x0
Loading: T #############################
done
Bytes transferred = 424776 (67b48 hex)
MX28 U-Boot > go 0
## Starting application at 0x00000000 ...


I believe the sram is too small to load the binary.

So, I change the TEXT_BASE to 0x41600000 in menuconfig, build and update barebox.bin, it print funny characters:

MX28 U-Boot > <INTERRUPT>
MX28 U-Boot > <INTERRUPT>
MX28 U-Boot > tftpboot 0x41600000 barebox.bin
Using FEC0 device
TFTP from server 192.168.12.61; our IP address is 192.168.12.62
Filename 'barebox.bin'.
Load address: 0x41600000
Loading: T #############################
done
Bytes transferred = 424776 (67b48 hex)
MX28 U-Boot > go 0x41600000
## Starting application at 0x41600000 ...
?????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????

For imx283, How to run barebox from ram?

Thanks,
Du Huanpeng




From m.olbrich at pengutronix.de  Thu Mar  1 10:07:52 2018
From: m.olbrich at pengutronix.de (Michael Olbrich)
Date: Thu, 1 Mar 2018 19:07:52 +0100
Subject: MIPS parallel build breakage
In-Reply-To: <20180301110729.pvdxqjqul7klrjyr@pengutronix.de>
References: <20180301110729.pvdxqjqul7klrjyr@pengutronix.de>
Message-ID: <20180301180752.fccog5hv47wuwtou@pengutronix.de>

Hi,

On Thu, Mar 01, 2018 at 12:07:29PM +0100, Sascha Hauer wrote:
> (Antony because you introduced this and Sam because you have intimate
> knowledge with our build system ;)
> 
> I am trying to solve a problem that annoys me for some years now. The
> problem is that the MIPS defconfigs regularly fail in my autobuilder.
> I usually help myself with trying it again and most of the time it
> then works, but doing this for years increases the pressure to do
> something.
> 
> What happens is that the MIPS builds use include/generated/compile.h:
> 
> > arch/mips/include/asm/pbl_macros.h:28:#include <generated/compile.h>
> 
> This often ends in:
> 
> > In file included from arch/mips/boot/start.S:20:0: arch/mips/include/asm/pbl_macros.h:28:31:
> > fatal error: generated/compile.h: No such file or directory
> > compilation terminated.
> 
> include/generated/compile.h is generated in common/Makefile:
> 
> > include/generated/compile.h: FORCE
> > 	@$($(quiet)chk_compile.h)
> > 	$(Q)$(CONFIG_SHELL) $(srctree)/scripts/mkcompile_h $@ \
> > 	"$(UTS_MACHINE)" "$(CC) $(KBUILD_CFLAGS)"
> 
> Other users of this file add an explicit dependency on it:
> 
> > # dependencies on generated files need to be listed explicitly
> > $(obj)/version.o: include/generated/compile.h
> 
> This only seems to work though when the dependent file is in the same
> directory, but not when the file is in arch/mips/boot/.
> 
> I tried doing the include/generated/compile.h in Makefile instead of
> common/Makefile, but then the version counting gets confused and causes
> unnecessary rebuilds.
> 
> Any ideas how to solve this?

arch/mips/boot/: common/

in arch/mips/Makefile or something like that? These two are both targets of the
toplevel make call, so that should work. The same for $(BOARD), I think and
maybe others that include generated/compile.h.

Michael

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From list at schmidt-andreas.de  Thu Mar  1 10:19:13 2018
From: list at schmidt-andreas.de (Andreas Schmidt)
Date: Thu, 1 Mar 2018 19:19:13 +0100
Subject: [PATCH] ARM: dts: remove "delete" entry for deleted clocks
In-Reply-To: <20180301090204.6xcfru5d3prdhapn@pengutronix.de>
References: <20180228180121.31539-1-mail@schmidt-andreas.de>
 <20180301090204.6xcfru5d3prdhapn@pengutronix.de>
Message-ID: <72aec458-1f3d-8d10-9fcc-f6e276bf6d57@schmidt-andreas.de>

Hi Sascha,


On 01.03.2018 10:02, Sascha Hauer wrote:
> Hi Andreas,
>
> On Wed, Feb 28, 2018 at 07:01:21PM +0100, Andreas Schmidt wrote:
>> After updete to v4.16-rc1 some clocks ware deleted from src dts.
>> This patch remove "delete" entry for this clocks from
>> am33xx-clocks-strip.dtsi too.
>>
>> Signed-off-by: Andreas Schmidt <mail at schmidt-andreas.de>
> I should have read this mail *before* creating the same patch.
sorry for being late with the patch and that you did the same work.
But important is, that the bug is fixed :)

Have a nice day!

Regards,
Andreas
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From linux at rempel-privat.de  Thu Mar  1 10:39:24 2018
From: linux at rempel-privat.de (Oleksij Rempel)
Date: Thu,  1 Mar 2018 19:39:24 +0100
Subject: [PATCH] MIPS: ath79: fix different typos
Message-ID: <20180301183924.4126-1-linux@rempel-privat.de>

the CONFIG typos was not real issue.
The defconfig typo i detected only after clean compile.
I hope we can migrate barebox MIPS to multiimage soon.

Signed-off-by: Oleksij Rempel <linux at rempel-privat.de>
---
 arch/mips/Makefile                                | 4 ++--
 arch/mips/configs/dptechnics-dpt-module_defconfig | 2 +-
 arch/mips/mach-ath79/Kconfig                      | 4 ++--
 3 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index c53c3767b..3342e0eaf 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -79,8 +79,8 @@ machine-$(CONFIG_MACH_MIPS_AR231X)	:= ar231x
 board-$(CONFIG_BOARD_NETGEAR_WG102)	:= netgear-wg102
 
 machine-$(CONFIG_MACH_MIPS_ATH79)	:= ath79
-board-$(CONFIG_BOARC_8DEVICES_LIMA)	:= 8devices-lima
-board-$(CONFIG_BOARC_DPTECHNICS_DPT_MODULE)	:= dptechnics-dpt-module
+board-$(CONFIG_BOARD_8DEVICES_LIMA)	:= 8devices-lima
+board-$(CONFIG_BOARD_DPTECHNICS_DPT_MODULE)	:= dptechnics-dpt-module
 board-$(CONFIG_BOARD_TPLINK_MR3020)	:= tplink-mr3020
 board-$(CONFIG_BOARD_TPLINK_WDR4300)	:= tplink-wdr4300
 board-$(CONFIG_BOARD_BLACK_SWIFT)	:= black-swift
diff --git a/arch/mips/configs/dptechnics-dpt-module_defconfig b/arch/mips/configs/dptechnics-dpt-module_defconfig
index dbad08fe6..c01b22b98 100644
--- a/arch/mips/configs/dptechnics-dpt-module_defconfig
+++ b/arch/mips/configs/dptechnics-dpt-module_defconfig
@@ -1,7 +1,7 @@
 CONFIG_BUILTIN_DTB=y
 CONFIG_BUILTIN_DTB_NAME="ar9331-dptechnics-dpt-module"
 CONFIG_MACH_MIPS_ATH79=y
-CONFIG_BOARC_QCA_AR9331_GENERIC=y
+CONFIG_BOARD_DPTECHNICS_DPT_MODULE=y
 CONFIG_PBL_IMAGE=y
 CONFIG_IMAGE_COMPRESSION_XZKERN=y
 CONFIG_MMU=y
diff --git a/arch/mips/mach-ath79/Kconfig b/arch/mips/mach-ath79/Kconfig
index 3434e38ed..e4e10a2f6 100644
--- a/arch/mips/mach-ath79/Kconfig
+++ b/arch/mips/mach-ath79/Kconfig
@@ -13,7 +13,7 @@ config SOC_QCA_AR9344
 choice
 	prompt "Board type"
 
-config BOARC_8DEVICES_LIMA
+config BOARD_8DEVICES_LIMA
 	bool "8devices LIMA"
 	select SOC_QCA_QCA4531
 	select HAVE_PBL_IMAGE
@@ -21,7 +21,7 @@ config BOARC_8DEVICES_LIMA
 	select HAS_NMON
 	select HAS_NO_BOARD_HL_CODE
 
-config BOARC_DPTECHNICS_DPT_MODULE
+config BOARD_DPTECHNICS_DPT_MODULE
 	bool "DPTechnics DPT-Module"
 	select SOC_QCA_AR9331
 	select HAVE_PBL_IMAGE
-- 
2.14.1



From s.hauer at pengutronix.de  Thu Mar  1 23:26:06 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 2 Mar 2018 08:26:06 +0100
Subject: problems with am335x_sdram_size()
In-Reply-To: <377910125.70611.1519914213534@mail.vodafone.de>
References: <377910125.70611.1519914213534@mail.vodafone.de>
Message-ID: <20180302072606.nn5o4mj7zbe4pyna@pengutronix.de>

On Thu, Mar 01, 2018 at 03:23:33PM +0100, Giorgio Dal Molin wrote:
> Hi,
> 
> working with the TI AM335x Evaluation Module I noticed that the function
> am335x_sdram_size() always returns 0 instead of the computed sdram size.
> 
> I could trace back the problem to the fact that the function does its 
> computation based on the value of the register CM_EMIF_SDRAM_CONFIG
> (addr. 0x44e10110), but this register is not written to by the function
> am33xx_config_sdram() and just returns its initial value (0).
> The datasheet says CM_EMIF_SDRAM_CONFIG should have the same value as
> AM33XX_EMIF4_0_REG(SDRAM_CONFIG) (addr. 0x4c000008)

CM_EMIF_SDRAM_CONFIG is written when regs->zq_config is set and if it's
set then indeed the same value is written there as also written to
AM33XX_EMIF4_0_REG(SDRAM_CONFIG).

> 
> To conclude, to fix the problem with am335x_sdram_size() you can either
> use AM33XX_EMIF4_0_REG(SDRAM_CONFIG) instead of CM_EMIF_SDRAM_CONFIG
> in am335x_sdram_size().
> 
>  or
> 
> initialize CM_EMIF_SDRAM_CONFIG in am33xx_config_sdram() with the same value
> as AM33XX_EMIF4_0_REG(SDRAM_CONFIG) (regs->sdram_config)

I'm fine with either way. Maybe the datasheet gives us a hint which way
to choose? Why is CM_EMIF_SDRAM_CONFIG only written when regs->zq_config
is set? Is this correct?

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From s.hauer at pengutronix.de  Thu Mar  1 23:36:45 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 2 Mar 2018 08:36:45 +0100
Subject: freescale-mx28-evk run from ram
In-Reply-To: <001601d3b17a$a176cbc0$e4646340$@qq.com>
References: <001601d3b17a$a176cbc0$e4646340$@qq.com>
Message-ID: <20180302073645.az7o7zxeysrafxtw@pengutronix.de>

Hi Du Huanpeng,

On Fri, Mar 02, 2018 at 12:30:37AM +0800, duhuanpeng wrote:
> Dear all,
> 
> Happy Yuanxiao(Lantern) Festival!

Thanks, same to you. Just googled some pictures for the lantern
Festival, it must look amazing to stand under that many lanterns ;)

> In System.map
> 00000000 T __image_start
> 00000000 T start
> 00000000 T _stext
> 00000000 T _text
> 00000004 T __bare_init_start
> 00000004 T get_runtime_offset
> 00000014 t linkadr
> 00000018 T __ld_var_base
> 00000018 T __ld_var__text
> 00000020 t ___text
> 00000024 T __ld_var___rel_dyn_start
> 0000002c t ____rel_dyn_start
> 00000030 T __ld_var___rel_dyn_end
> 00000038 t ____rel_dyn_end
> 0000003c T __ld_var___dynsym_start
> 00000044 t ____dynsym_start
> 00000048 T __ld_var___dynsym_end
> 00000050 t ____dynsym_end
> 00000054 T __ld_var___bss_start
> 0000005c t ____bss_start
> 00000060 T __ld_var___bss_stop
> 00000068 t ____bss_stop
> 
> So, I load barebox.bin to address 0x00000000:

I assume you use freescale-mx28-evk_defconfig, right?
Which image do you start? It seems you are trying to start barebox.bin.
It should be images/barebox-freescale-mx28evk-2nd.img instead.

The image should be linked to 0x0, that is right. The code is position
independent though and the full barebox relocates itself to the end of
the available SDRAM automatically. TEXT_BASE is not relevant here.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From s.hauer at pengutronix.de  Thu Mar  1 23:38:21 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 2 Mar 2018 08:38:21 +0100
Subject: [PATCH] MIPS: ath79: fix different typos
In-Reply-To: <20180301183924.4126-1-linux@rempel-privat.de>
References: <20180301183924.4126-1-linux@rempel-privat.de>
Message-ID: <20180302073821.dk2ht676voz3ecv4@pengutronix.de>

On Thu, Mar 01, 2018 at 07:39:24PM +0100, Oleksij Rempel wrote:
> the CONFIG typos was not real issue.
> The defconfig typo i detected only after clean compile.
> I hope we can migrate barebox MIPS to multiimage soon.
> 
> Signed-off-by: Oleksij Rempel <linux at rempel-privat.de>
> ---

Applied, thanks

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From 548708880 at qq.com  Fri Mar  2 01:53:30 2018
From: 548708880 at qq.com (duhuanpeng)
Date: Fri, 2 Mar 2018 17:53:30 +0800
Subject: =?gb2312?B?tPC4tDogZnJlZXNjYWxlLW14MjgtZXZrIHJ1biBmcm9tIHJhbQ==?=
In-Reply-To: <20180302073645.az7o7zxeysrafxtw@pengutronix.de>
References: <001601d3b17a$a176cbc0$e4646340$@qq.com>
 <20180302073645.az7o7zxeysrafxtw@pengutronix.de>
Message-ID: <000f01d3b20c$524d84c0$f6e88e40$@qq.com>+C0D7D46BD8A415C1

Hi, this is the output for barebox-freescale-mx28evk-2nd.img

Load to address 0x00000000
- - -
Loading: *
Abort
MX28 U-Boot > tftpboot 0 barebox-freescale-mx28evk-2nd.img
Using FEC0 device
TFTP from server 192.168.12.61; our IP address is 192.168.12.62
Filename 'barebox-freescale-mx28evk-2nd.img'.
Load address: 0x0
Loading: T #################
done
Bytes transferred = 237766 (3a0c6 hex)
MX28 U-Boot > go 0
## Starting application at 0x00000000 ...

- - -

Load to address 0x41600000:
- - -
MX28 U-Boot > tftpboot barebox-freescale-mx28evk-2nd.img
Using FEC0 device
TFTP from server 192.168.12.61; our IP address is 192.168.12.62
Filename 'barebox-freescale-mx28evk-2nd.img'.
Load address: 0x41600000
Loading: T #################
done
Bytes transferred = 237766 (3a0c6 hex)
MX28 U-Boot > go 0x41600000
## Starting application at 0x41600000 ...

- - - -

This macro is on CONFIG_PBL_RELOCATABLE
#
# memory layout
#
CONFIG_HAVE_PBL_IMAGE=y
CONFIG_HAVE_PBL_MULTI_IMAGES=y
CONFIG_HAVE_IMAGE_COMPRESSION=y
CONFIG_PBL_IMAGE=y
CONFIG_PBL_MULTI_IMAGES=y
CONFIG_PBL_RELOCATABLE=y

-----????????-----
??????: Sascha Hauer [mailto:s.hauer at pengutronix.de] 
????????: 2018??3??2?? 15:37
??????: duhuanpeng
????: barebox at lists.infradead.org
????: Re: freescale-mx28-evk run from ram

Hi Du Huanpeng,

On Fri, Mar 02, 2018 at 12:30:37AM +0800, duhuanpeng wrote:
> Dear all,
> 
> Happy Yuanxiao(Lantern) Festival!

Thanks, same to you. Just googled some pictures for the lantern Festival, it
must look amazing to stand under that many lanterns ;)

> In System.map
> 00000000 T __image_start
> 00000000 T start
> 00000000 T _stext
> 00000000 T _text
> 00000004 T __bare_init_start
> 00000004 T get_runtime_offset
> 00000014 t linkadr
> 00000018 T __ld_var_base
> 00000018 T __ld_var__text
> 00000020 t ___text
> 00000024 T __ld_var___rel_dyn_start
> 0000002c t ____rel_dyn_start
> 00000030 T __ld_var___rel_dyn_end
> 00000038 t ____rel_dyn_end
> 0000003c T __ld_var___dynsym_start
> 00000044 t ____dynsym_start
> 00000048 T __ld_var___dynsym_end
> 00000050 t ____dynsym_end
> 00000054 T __ld_var___bss_start
> 0000005c t ____bss_start
> 00000060 T __ld_var___bss_stop
> 00000068 t ____bss_stop
> 
> So, I load barebox.bin to address 0x00000000:

> I assume you use freescale-mx28-evk_defconfig, right?
Yes.

Which image do you start? It seems you are trying to start barebox.bin.
> barebox.bin and barebox-freescale-mx28evk-2nd.img
It should be images/barebox-freescale-mx28evk-2nd.img instead.

The image should be linked to 0x0, that is right. The code is position
independent though and the full barebox relocates itself to the end of the
available SDRAM automatically. TEXT_BASE is not relevant here.
The start symbol is still 0x00000000 even I change TEXT_BASE in menuconfig.
my board have 64MiB ram. Modified board. 
Very cheap one, just 33?. :D
EasyARM-i.MX283A
http://www.zlg.cn/ipc/ipc/product/id/92.html
http://www.zlg.cn/ipc/down/down/id/92.html

This board has a LCD(480*800?), I want to test font support on this board.

The sch is here:
https://drive.google.com/open?id=1_3xW7nfQ6p9tnkjZEDK9vZiLlUnat25K

There are many pcf fonts here:
https://www.netsarang.com/download/main.html

and maybe use code from freetype? 
http://www.freetype.org/

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |






From 548708880 at qq.com  Fri Mar  2 02:01:12 2018
From: 548708880 at qq.com (duhuanpeng)
Date: Fri, 2 Mar 2018 18:01:12 +0800
Subject: my mx283 board sch
Message-ID: <001101d3b20d$65218190$2f6484b0$@qq.com>+8BBD1BA01F7704C8

Sorry, that link is broken.

Sch in google driver is here:
https://drive.google.com/file/d/1_3xW7nfQ6p9tnkjZEDK9vZiLlUnat25K/view?usp=s
haring





From s.hauer at pengutronix.de  Fri Mar  2 02:15:05 2018
From: s.hauer at pengutronix.de ('Sascha Hauer')
Date: Fri, 2 Mar 2018 11:15:05 +0100
Subject: =?utf-8?B?562U5aSN?= =?utf-8?Q?=3A?= freescale-mx28-evk run from
 ram
In-Reply-To: <000001d3b205$12bea160$383be420$@qq.com>
References: <001601d3b17a$a176cbc0$e4646340$@qq.com>
 <20180302073645.az7o7zxeysrafxtw@pengutronix.de>
 <000001d3b205$12bea160$383be420$@qq.com>
Message-ID: <20180302101505.iawtfiddffoswajt@pengutronix.de>

On Fri, Mar 02, 2018 at 05:01:37PM +0800, duhuanpeng wrote:
> > I assume you use freescale-mx28-evk_defconfig, right?
> Yes.
> 
> Which image do you start? It seems you are trying to start barebox.bin.
> > barebox.bin and barebox-freescale-mx28evk-2nd.img
> It should be images/barebox-freescale-mx28evk-2nd.img instead.
> 
> The image should be linked to 0x0, that is right. The code is position
> independent though and the full barebox relocates itself to the end of the
> available SDRAM automatically. TEXT_BASE is not relevant here.
> The start symbol is still 0x00000000 even I change TEXT_BASE in menuconfig.
> my board have 64MiB ram. Modified board. 
> Very cheap one, just 33?. :D
> EasyARM-i.MX283A

You are running on a board which actually is no mx28-evk, so it's no
wonder it doesn't work. Please mention that next time, because that
changes the question from "What is broken with the mx28-evk" to "What is
different on your board". This is a very important detail to answer
questions.

Anyway, you say your board only has 64MiB of RAM, so you must at least
change:

ENTRY_FUNCTION(start_barebox_freescale_mx28evk, r0, r1, r2)
{
        barebox_arm_entry(IMX_MEMORY_BASE, SZ_128M, NULL);
}

to SZ_64M. Other differences might include the pinmux and the UART port
number which is used for console output.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From 548708880 at qq.com  Fri Mar  2 02:55:26 2018
From: 548708880 at qq.com (duhuanpeng)
Date: Fri, 2 Mar 2018 18:55:26 +0800
Subject: =?gb2312?B?tPC4tDogtPC4tDogZnJlZXNjYWxlLW14MjgtZXZrIHJ1biBmcm9tIHJhbQ==?=
In-Reply-To: <20180302101505.iawtfiddffoswajt@pengutronix.de>
References: <001601d3b17a$a176cbc0$e4646340$@qq.com>
 <20180302073645.az7o7zxeysrafxtw@pengutronix.de>
 <000001d3b205$12bea160$383be420$@qq.com>
 <20180302101505.iawtfiddffoswajt@pengutronix.de>
Message-ID: <000001d3b214$f92d4520$eb87cf60$@qq.com>+497C8974AAC879C2

Hi, now it is running. Thanks. Now the lcd is dark. How to launch the gui?
- - -
diff --git a/arch/arm/boards/freescale-mx28-evk/lowlevel.c
b/arch/arm/boards/freescale-mx28-evk/lowlevel.c
index 4d45a03..10f7ef6 100644
--- a/arch/arm/boards/freescale-mx28-evk/lowlevel.c
+++ b/arch/arm/boards/freescale-mx28-evk/lowlevel.c
@@ -14,7 +14,7 @@
 
 ENTRY_FUNCTION(start_barebox_freescale_mx28evk, r0, r1, r2)
 {
-       barebox_arm_entry(IMX_MEMORY_BASE, SZ_128M, NULL);
+       barebox_arm_entry(IMX_MEMORY_BASE, SZ_64M, NULL);
 }
- - -

got MAC address from IIM: 00:04:f8:5d:d7:cf
FEC0
Warning: FEC0 MAC addresses don't match:
Address in SROM is         00:04:f8:5d:d7:cf
Address in environment is  02:00:92:b3:c4:a8

Hit any key to stop autoboot:  0
MX28 U-Boot > <INTERRUPT>
MX28 U-Boot > <INTERRUPT>
MX28 U-Boot > <INTERRUPT>
MX28 U-Boot > <INTERRUPT>
MX28 U-Boot > <INTERRUPT>
MX28 U-Boot > tftpboot barebox-freescale-mx28evk-2nd.img
Using FEC0 device
TFTP from server 192.168.12.61; our IP address is 192.168.12.62
Filename 'barebox-freescale-mx28evk-2nd.img'.
Load address: 0x41600000
Loading: T #################
done
Bytes transferred = 237783 (3a0d7 hex)
MX28 U-Boot > go 0x41600000
## Starting application at 0x41600000 ...
initcall-> globalvar_init+0x0/0x38
initcall-> platform_init+0x0/0xc
initcall-> mdio_bus_init+0x0/0xc
initcall-> spi_bus_init+0x0/0xc
initcall-> gpio_desc_alloc+0x0/0x20
initcall-> fs_bus_init+0x0/0xc
initcall-> mxs_gpio_add+0x0/0x18
initcall-> imx28_clocksource_init+0x0/0x54
initcall-> unwind_init+0x0/0x30
initcall-> imx28_ccm_init+0x0/0xc
initcall-> net_init+0x0/0x88
initcall-> init_fs+0x0/0x3c
initcall-> mxs_init+0x0/0xdc
detected i.MX28 revision 1.2
initcall-> imx28_devices_init+0x0/0x144
initcall-> imx28_init+0x0/0x2c
initcall-> stm_serial_driver_register+0x0/0xc
initcall-> auart_serial_driver_register+0x0/0xc
initcall-> mx28_evk_console_init+0x0/0x54
Switch to console [cs0]


barebox 2018.02.0-00077-g359966d-dirty #12 Fri Mar 2 18:37:29 CST 2018


Board: Freescale i.MX28 EVK
initcall-> globalvar_init+0x0/0x38
initcall-> platform_init+0x0/0xc 

-----????-----
???: 'Sascha Hauer' [mailto:s.hauer at pengutronix.de] 
????: 2018?3?2? 18:15
???: duhuanpeng
??: barebox at lists.infradead.org
??: Re: ??: freescale-mx28-evk run from ram

On Fri, Mar 02, 2018 at 05:01:37PM +0800, duhuanpeng wrote:
> > I assume you use freescale-mx28-evk_defconfig, right?
> Yes.
> 
> Which image do you start? It seems you are trying to start barebox.bin.
> > barebox.bin and barebox-freescale-mx28evk-2nd.img
> It should be images/barebox-freescale-mx28evk-2nd.img instead.
> 
> The image should be linked to 0x0, that is right. The code is position 
> independent though and the full barebox relocates itself to the end of 
> the available SDRAM automatically. TEXT_BASE is not relevant here.
> The start symbol is still 0x00000000 even I change TEXT_BASE in
menuconfig.
> my board have 64MiB ram. Modified board. 
> Very cheap one, just 33?. :D
> EasyARM-i.MX283A

You are running on a board which actually is no mx28-evk, so it's no wonder
it doesn't work. Please mention that next time, because that changes the
question from "What is broken with the mx28-evk" to "What is different on
your board". This is a very important detail to answer questions.

Anyway, you say your board only has 64MiB of RAM, so you must at least
change:

ENTRY_FUNCTION(start_barebox_freescale_mx28evk, r0, r1, r2) {
        barebox_arm_entry(IMX_MEMORY_BASE, SZ_128M, NULL); }

to SZ_64M. Other differences might include the pinmux and the UART port
number which is used for console output.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |



From 548708880 at qq.com  Fri Mar  2 02:56:26 2018
From: 548708880 at qq.com (duhuanpeng)
Date: Fri, 2 Mar 2018 18:56:26 +0800
Subject: =?gb2312?B?tPC4tDogtPC4tDogZnJlZXNjYWxlLW14MjgtZXZrIHJ1biBmcm9tIHJhbQ==?=
In-Reply-To: <20180302101505.iawtfiddffoswajt@pengutronix.de>
References: <001601d3b17a$a176cbc0$e4646340$@qq.com>
 <20180302073645.az7o7zxeysrafxtw@pengutronix.de>
 <000001d3b205$12bea160$383be420$@qq.com>
 <20180302101505.iawtfiddffoswajt@pengutronix.de>
Message-ID: <000101d3b215$1ce01060$56a03120$@qq.com>+AED5792B453695E6

Hi, now it is running. Thanks. Now the lcd is dark. How to launch the gui?
- - -
diff --git a/arch/arm/boards/freescale-mx28-evk/lowlevel.c
b/arch/arm/boards/freescale-mx28-evk/lowlevel.c
index 4d45a03..10f7ef6 100644
--- a/arch/arm/boards/freescale-mx28-evk/lowlevel.c
+++ b/arch/arm/boards/freescale-mx28-evk/lowlevel.c
@@ -14,7 +14,7 @@
 
 ENTRY_FUNCTION(start_barebox_freescale_mx28evk, r0, r1, r2)
 {
-       barebox_arm_entry(IMX_MEMORY_BASE, SZ_128M, NULL);
+       barebox_arm_entry(IMX_MEMORY_BASE, SZ_64M, NULL);
 }
- - -

got MAC address from IIM: 00:04:f8:5d:d7:cf
FEC0
Warning: FEC0 MAC addresses don't match:
Address in SROM is         00:04:f8:5d:d7:cf
Address in environment is  02:00:92:b3:c4:a8

Hit any key to stop autoboot:  0
MX28 U-Boot > <INTERRUPT>
MX28 U-Boot > <INTERRUPT>
MX28 U-Boot > <INTERRUPT>
MX28 U-Boot > <INTERRUPT>
MX28 U-Boot > <INTERRUPT>
MX28 U-Boot > tftpboot barebox-freescale-mx28evk-2nd.img
Using FEC0 device
TFTP from server 192.168.12.61; our IP address is 192.168.12.62
Filename 'barebox-freescale-mx28evk-2nd.img'.
Load address: 0x41600000
Loading: T #################
done
Bytes transferred = 237783 (3a0d7 hex)
MX28 U-Boot > go 0x41600000
## Starting application at 0x41600000 ...
initcall-> globalvar_init+0x0/0x38
initcall-> platform_init+0x0/0xc
initcall-> mdio_bus_init+0x0/0xc
initcall-> spi_bus_init+0x0/0xc
initcall-> gpio_desc_alloc+0x0/0x20
initcall-> fs_bus_init+0x0/0xc
initcall-> mxs_gpio_add+0x0/0x18
initcall-> imx28_clocksource_init+0x0/0x54
initcall-> unwind_init+0x0/0x30
initcall-> imx28_ccm_init+0x0/0xc
initcall-> net_init+0x0/0x88
initcall-> init_fs+0x0/0x3c
initcall-> mxs_init+0x0/0xdc
detected i.MX28 revision 1.2
initcall-> imx28_devices_init+0x0/0x144
initcall-> imx28_init+0x0/0x2c
initcall-> stm_serial_driver_register+0x0/0xc
initcall-> auart_serial_driver_register+0x0/0xc
initcall-> mx28_evk_console_init+0x0/0x54
Switch to console [cs0]


barebox 2018.02.0-00077-g359966d-dirty #12 Fri Mar 2 18:37:29 CST 2018


Board: Freescale i.MX28 EVK
initcall-> globalvar_init+0x0/0x38
initcall-> platform_init+0x0/0xc 

-----????-----
???: 'Sascha Hauer' [mailto:s.hauer at pengutronix.de] 
????: 2018?3?2? 18:15
???: duhuanpeng
??: barebox at lists.infradead.org
??: Re: ??: freescale-mx28-evk run from ram

On Fri, Mar 02, 2018 at 05:01:37PM +0800, duhuanpeng wrote:
> > I assume you use freescale-mx28-evk_defconfig, right?
> Yes.
> 
> Which image do you start? It seems you are trying to start barebox.bin.
> > barebox.bin and barebox-freescale-mx28evk-2nd.img
> It should be images/barebox-freescale-mx28evk-2nd.img instead.
> 
> The image should be linked to 0x0, that is right. The code is position 
> independent though and the full barebox relocates itself to the end of 
> the available SDRAM automatically. TEXT_BASE is not relevant here.
> The start symbol is still 0x00000000 even I change TEXT_BASE in
menuconfig.
> my board have 64MiB ram. Modified board. 
> Very cheap one, just 33?. :D
> EasyARM-i.MX283A

You are running on a board which actually is no mx28-evk, so it's no wonder
it doesn't work. Please mention that next time, because that changes the
question from "What is broken with the mx28-evk" to "What is different on
your board". This is a very important detail to answer questions.

Anyway, you say your board only has 64MiB of RAM, so you must at least
change:

ENTRY_FUNCTION(start_barebox_freescale_mx28evk, r0, r1, r2) {
        barebox_arm_entry(IMX_MEMORY_BASE, SZ_128M, NULL); }

to SZ_64M. Other differences might include the pinmux and the UART port
number which is used for console output.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |





From antonynpavlov at gmail.com  Fri Mar  2 04:17:35 2018
From: antonynpavlov at gmail.com (Antony Pavlov)
Date: Fri, 2 Mar 2018 15:17:35 +0300
Subject: MIPS parallel build breakage
In-Reply-To: <20180301110729.pvdxqjqul7klrjyr@pengutronix.de>
References: <20180301110729.pvdxqjqul7klrjyr@pengutronix.de>
Message-ID: <20180302151735.028ad4763bfd8ae7603a5fb9@gmail.com>

On Thu, 1 Mar 2018 12:07:29 +0100
Sascha Hauer <s.hauer at pengutronix.de> wrote:

> Hi Sam and Antony,
> 
> (Antony because you introduced this and Sam because you have intimate
> knowledge with our build system ;)
> 
> I am trying to solve a problem that annoys me for some years now. The
> problem is that the MIPS defconfigs regularly fail in my autobuilder.
> I usually help myself with trying it again and most of the time it
> then works, but doing this for years increases the pressure to do
> something.
> 
> What happens is that the MIPS builds use include/generated/compile.h:
> 
> > arch/mips/include/asm/pbl_macros.h:28:#include <generated/compile.h>
> 
> This often ends in:
> 
> > In file included from arch/mips/boot/start.S:20:0: arch/mips/include/asm/pbl_macros.h:28:31:
> > fatal error: generated/compile.h: No such file or directory
> > compilation terminated.
> 
> include/generated/compile.h is generated in common/Makefile:
> 
> > include/generated/compile.h: FORCE
> > 	@$($(quiet)chk_compile.h)
> > 	$(Q)$(CONFIG_SHELL) $(srctree)/scripts/mkcompile_h $@ \
> > 	"$(UTS_MACHINE)" "$(CC) $(KBUILD_CFLAGS)"
> 
> Other users of this file add an explicit dependency on it:
> 
> > # dependencies on generated files need to be listed explicitly
> > $(obj)/version.o: include/generated/compile.h
> 
> This only seems to work though when the dependent file is in the same
> directory, but not when the file is in arch/mips/boot/.
> 
> I tried doing the include/generated/compile.h in Makefile instead of
> common/Makefile, but then the version counting gets confused and causes
> unnecessary rebuilds.
> 
> Any ideas how to solve this?

I can't reproduce parallel build breakage. But I see another problem:
the version string inside mips pbl binary is differ from the version string
inside main barebox binary.

I suppose that the problem is that current build system handles mips asm files
(which are actually use generated compile.h) and c-files in a different way.

-- 
Best regards,
? Antony Pavlov


From s.hauer at pengutronix.de  Fri Mar  2 04:34:01 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 2 Mar 2018 13:34:01 +0100
Subject: MIPS parallel build breakage
In-Reply-To: <20180302151735.028ad4763bfd8ae7603a5fb9@gmail.com>
References: <20180301110729.pvdxqjqul7klrjyr@pengutronix.de>
 <20180302151735.028ad4763bfd8ae7603a5fb9@gmail.com>
Message-ID: <20180302123401.zb5ltrledrhdwbfj@pengutronix.de>

On Fri, Mar 02, 2018 at 03:17:35PM +0300, Antony Pavlov wrote:
> On Thu, 1 Mar 2018 12:07:29 +0100
> Sascha Hauer <s.hauer at pengutronix.de> wrote:
> 
> > Hi Sam and Antony,
> > 
> > (Antony because you introduced this and Sam because you have intimate
> > knowledge with our build system ;)
> > 
> > I am trying to solve a problem that annoys me for some years now. The
> > problem is that the MIPS defconfigs regularly fail in my autobuilder.
> > I usually help myself with trying it again and most of the time it
> > then works, but doing this for years increases the pressure to do
> > something.
> > 
> > What happens is that the MIPS builds use include/generated/compile.h:
> > 
> > > arch/mips/include/asm/pbl_macros.h:28:#include <generated/compile.h>
> > 
> > This often ends in:
> > 
> > > In file included from arch/mips/boot/start.S:20:0: arch/mips/include/asm/pbl_macros.h:28:31:
> > > fatal error: generated/compile.h: No such file or directory
> > > compilation terminated.
> > 
> > include/generated/compile.h is generated in common/Makefile:
> > 
> > > include/generated/compile.h: FORCE
> > > 	@$($(quiet)chk_compile.h)
> > > 	$(Q)$(CONFIG_SHELL) $(srctree)/scripts/mkcompile_h $@ \
> > > 	"$(UTS_MACHINE)" "$(CC) $(KBUILD_CFLAGS)"
> > 
> > Other users of this file add an explicit dependency on it:
> > 
> > > # dependencies on generated files need to be listed explicitly
> > > $(obj)/version.o: include/generated/compile.h
> > 
> > This only seems to work though when the dependent file is in the same
> > directory, but not when the file is in arch/mips/boot/.
> > 
> > I tried doing the include/generated/compile.h in Makefile instead of
> > common/Makefile, but then the version counting gets confused and causes
> > unnecessary rebuilds.
> > 
> > Any ideas how to solve this?
> 
> I can't reproduce parallel build breakage.

The failure starts here when using 6 threads or more and only when
compiling the black-swift_defconfig. After one successful build I can
reproduce this reliably here with:

rm -f include/generated/compile.h && make -j 6

> But I see another problem:
> the version string inside mips pbl binary is differ from the version string
> inside main barebox binary.
> 
> I suppose that the problem is that current build system handles mips asm files
> (which are actually use generated compile.h) and c-files in a different way.

Ups. How do the strings differ?

Another obvious way to fix the issue is to remove UTS_RELEASE and
UTS_VERSION from the pbl headers. Would that be an option?

Sascha


-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From antonynpavlov at gmail.com  Fri Mar  2 05:37:31 2018
From: antonynpavlov at gmail.com (Antony Pavlov)
Date: Fri, 2 Mar 2018 16:37:31 +0300
Subject: MIPS parallel build breakage
In-Reply-To: <20180302123401.zb5ltrledrhdwbfj@pengutronix.de>
References: <20180301110729.pvdxqjqul7klrjyr@pengutronix.de>
 <20180302151735.028ad4763bfd8ae7603a5fb9@gmail.com>
 <20180302123401.zb5ltrledrhdwbfj@pengutronix.de>
Message-ID: <20180302163731.a476bd3c03884101dafbaac1@gmail.com>

On Fri, 2 Mar 2018 13:34:01 +0100
Sascha Hauer <s.hauer at pengutronix.de> wrote:

> On Fri, Mar 02, 2018 at 03:17:35PM +0300, Antony Pavlov wrote:
> > On Thu, 1 Mar 2018 12:07:29 +0100
> > Sascha Hauer <s.hauer at pengutronix.de> wrote:
> > 
> > > Hi Sam and Antony,
> > > 
> > > (Antony because you introduced this and Sam because you have intimate
> > > knowledge with our build system ;)
> > > 
> > > I am trying to solve a problem that annoys me for some years now. The
> > > problem is that the MIPS defconfigs regularly fail in my autobuilder.
> > > I usually help myself with trying it again and most of the time it
> > > then works, but doing this for years increases the pressure to do
> > > something.
> > > 
> > > What happens is that the MIPS builds use include/generated/compile.h:
> > > 
> > > > arch/mips/include/asm/pbl_macros.h:28:#include <generated/compile.h>
> > > 
> > > This often ends in:
> > > 
> > > > In file included from arch/mips/boot/start.S:20:0: arch/mips/include/asm/pbl_macros.h:28:31:
> > > > fatal error: generated/compile.h: No such file or directory
> > > > compilation terminated.
> > > 
> > > include/generated/compile.h is generated in common/Makefile:
> > > 
> > > > include/generated/compile.h: FORCE
> > > > 	@$($(quiet)chk_compile.h)
> > > > 	$(Q)$(CONFIG_SHELL) $(srctree)/scripts/mkcompile_h $@ \
> > > > 	"$(UTS_MACHINE)" "$(CC) $(KBUILD_CFLAGS)"
> > > 
> > > Other users of this file add an explicit dependency on it:
> > > 
> > > > # dependencies on generated files need to be listed explicitly
> > > > $(obj)/version.o: include/generated/compile.h
> > > 
> > > This only seems to work though when the dependent file is in the same
> > > directory, but not when the file is in arch/mips/boot/.
> > > 
> > > I tried doing the include/generated/compile.h in Makefile instead of
> > > common/Makefile, but then the version counting gets confused and causes
> > > unnecessary rebuilds.
> > > 
> > > Any ideas how to solve this?
> > 
> > I can't reproduce parallel build breakage.
> 
> The failure starts here when using 6 threads or more and only when
> compiling the black-swift_defconfig. After one successful build I can
> reproduce this reliably here with:
> 
> rm -f include/generated/compile.h && make -j 6
> 
> > But I see another problem:
> > the version string inside mips pbl binary is differ from the version string
> > inside main barebox binary.
> > 
> > I suppose that the problem is that current build system handles mips asm files
> > (which are actually use generated compile.h) and c-files in a different way.
> 
> Ups. How do the strings differ?

insert generated version into pbl by using mips_barebox_10h:

barebox$ git diff
diff --git a/arch/mips/boards/qemu-malta/include/board/board_pbl_start.h b/arch/mips/boards/qemu-malta/include/board/board_pbl_start.h
index 5c1537262e..6e85a7009a 100644
--- a/arch/mips/boards/qemu-malta/include/board/board_pbl_start.h
+++ b/arch/mips/boards/qemu-malta/include/board/board_pbl_start.h
@@ -43,18 +43,8 @@
        .set    push
        .set    noreorder
 
-       b       __start
-        nop
+       mips_barebox_10h
 
-       /*
-          On MIPS Technologies boards
-          0x1fc00010 address is reserved for BoardID
-       */
-       .org    0x10
-       .word   0xffffffff
-       .word   0xffffffff
-
-__start:
        mips_disable_interrupts
 
        /* cpu specific setup ... */
barebox$ make mrproper
...
barebox$ export ARCH=mips
barebox$ export CROSS_COMPILE=mips-linux-gnu-
barebox$ make qemu-malta_defconfig
...
barebox$ make -j3 -s
...
barebox$ xxd barebox-flash-image | head -n 6
00000000: 1000 0017 0000 0000 0000 0000 0000 0000  ................
00000010: 6261 7265 626f 7820 3230 3138 2e30 322e  barebox 2018.02.
00000020: 302d 3030 3037 392d 6731 6564 6462 3064  0-00079-g1eddb0d
00000030: 3338 322d 6469 7274 7920 2330 2046 7269  382-dirty #0 Fri
                                                           ^^^^^^^
00000040: 204d 6172 2032 2031 363a 3032 3a32 3920   Mar 2 16:02:29 
00000050: 4d53 4b20 3230 3138 0000 0000 0000 0000  MSK 2018........

#0, 16:02:29 !!!!!!!!

barebox$ qemu-system-mips -nodefaults -M malta -m 256 \
>                          -nographic -serial stdio -monitor null \
>                          -bios barebox-flash-image


barebox 2018.02.0-00079-g1eddb0d382-dirty #1 Fri Mar 2 16:02:38 MSK 2018
                                        ^^^^^^^

#1, 16:02:38 !!!!!!!!

> Another obvious way to fix the issue is to remove UTS_RELEASE and
> UTS_VERSION from the pbl headers. Would that be an option?

It isn't a __good__ option.

-- 
Best regards,
? Antony Pavlov


From giorgio.nicole at arcor.de  Fri Mar  2 06:11:06 2018
From: giorgio.nicole at arcor.de (Giorgio Dal Molin)
Date: Fri, 2 Mar 2018 15:11:06 +0100 (CET)
Subject: problems with am335x_sdram_size()
In-Reply-To: <20180302072606.nn5o4mj7zbe4pyna@pengutronix.de>
References: <377910125.70611.1519914213534@mail.vodafone.de>
 <20180302072606.nn5o4mj7zbe4pyna@pengutronix.de>
Message-ID: <272060361.5564.1519999866645@mail.vodafone.de>

Hi,

> On March 2, 2018 at 8:26 AM Sascha Hauer <s.hauer at pengutronix.de> wrote:
> 
> 
> On Thu, Mar 01, 2018 at 03:23:33PM +0100, Giorgio Dal Molin wrote:
> > Hi,
> > 
> > working with the TI AM335x Evaluation Module I noticed that the function
> > am335x_sdram_size() always returns 0 instead of the computed sdram size.
> > 
> > I could trace back the problem to the fact that the function does its 
> > computation based on the value of the register CM_EMIF_SDRAM_CONFIG
> > (addr. 0x44e10110), but this register is not written to by the function
> > am33xx_config_sdram() and just returns its initial value (0).
> > The datasheet says CM_EMIF_SDRAM_CONFIG should have the same value as
> > AM33XX_EMIF4_0_REG(SDRAM_CONFIG) (addr. 0x4c000008)
> 
> CM_EMIF_SDRAM_CONFIG is written when regs->zq_config is set and if it's
> set then indeed the same value is written there as also written to
> AM33XX_EMIF4_0_REG(SDRAM_CONFIG).
> 

aaah, I'm blind !

I've added a line at the end of am33xx_config_sdram() that's
exactly the same as the one a couple of lines before.
I was so happy to have solved my problem that I've no more
double checked if the register was already configured somewhere else.

So, now I've also defined regs->zq_config in my lowlevel.c and everything works.

The datasheet says:

The CONTROL_EMIF_SDRAM_CONFIG register exports SDRAM configuration information
to the EMIF after resuming from low power scenarios.
This register should be loaded with the same value as SDRAM_CONFIG during DDR
initialization.

so I think we should initialize it unconditionally, not only if !regs->zq_config.
Doing this it should be the same which one we use in am335x_sdram_size() to
compute the sdram size even if I would prefer to use AM33XX_EMIF4_0_REG(SDRAM_CONFIG)
for clarity.

giorgio

> > 
> > To conclude, to fix the problem with am335x_sdram_size() you can either
> > use AM33XX_EMIF4_0_REG(SDRAM_CONFIG) instead of CM_EMIF_SDRAM_CONFIG
> > in am335x_sdram_size().
> > 
> >  or
> > 
> > initialize CM_EMIF_SDRAM_CONFIG in am33xx_config_sdram() with the same value
> > as AM33XX_EMIF4_0_REG(SDRAM_CONFIG) (regs->sdram_config)
> 
> I'm fine with either way. Maybe the datasheet gives us a hint which way
> to choose? Why is CM_EMIF_SDRAM_CONFIG only written when regs->zq_config
> is set? Is this correct?
> 
> Sascha
> 
> -- 
> Pengutronix e.K.                           |                             |
> Industrial Linux Solutions                 | http://www.pengutronix.de/  |
> Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
> Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |
> 
> _______________________________________________
> barebox mailing list
> barebox at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/barebox


From s.hauer at pengutronix.de  Fri Mar  2 06:54:02 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 2 Mar 2018 15:54:02 +0100
Subject: MIPS parallel build breakage
In-Reply-To: <20180302163731.a476bd3c03884101dafbaac1@gmail.com>
References: <20180301110729.pvdxqjqul7klrjyr@pengutronix.de>
 <20180302151735.028ad4763bfd8ae7603a5fb9@gmail.com>
 <20180302123401.zb5ltrledrhdwbfj@pengutronix.de>
 <20180302163731.a476bd3c03884101dafbaac1@gmail.com>
Message-ID: <20180302145402.oqssaqvsh4h6dupg@pengutronix.de>

On Fri, Mar 02, 2018 at 04:37:31PM +0300, Antony Pavlov wrote:
> On Fri, 2 Mar 2018 13:34:01 +0100
> Sascha Hauer <s.hauer at pengutronix.de> wrote:
> 
> > On Fri, Mar 02, 2018 at 03:17:35PM +0300, Antony Pavlov wrote:
> > > On Thu, 1 Mar 2018 12:07:29 +0100
> > > Sascha Hauer <s.hauer at pengutronix.de> wrote:
> > > 
> > > > Hi Sam and Antony,
> > > > 
> > > > (Antony because you introduced this and Sam because you have intimate
> > > > knowledge with our build system ;)
> > > > 
> > > > I am trying to solve a problem that annoys me for some years now. The
> > > > problem is that the MIPS defconfigs regularly fail in my autobuilder.
> > > > I usually help myself with trying it again and most of the time it
> > > > then works, but doing this for years increases the pressure to do
> > > > something.
> > > > 
> > > > What happens is that the MIPS builds use include/generated/compile.h:
> > > > 
> > > > > arch/mips/include/asm/pbl_macros.h:28:#include <generated/compile.h>
> > > > 
> > > > This often ends in:
> > > > 
> > > > > In file included from arch/mips/boot/start.S:20:0: arch/mips/include/asm/pbl_macros.h:28:31:
> > > > > fatal error: generated/compile.h: No such file or directory
> > > > > compilation terminated.
> > > > 
> > > > include/generated/compile.h is generated in common/Makefile:
> > > > 
> > > > > include/generated/compile.h: FORCE
> > > > > 	@$($(quiet)chk_compile.h)
> > > > > 	$(Q)$(CONFIG_SHELL) $(srctree)/scripts/mkcompile_h $@ \
> > > > > 	"$(UTS_MACHINE)" "$(CC) $(KBUILD_CFLAGS)"
> > > > 
> > > > Other users of this file add an explicit dependency on it:
> > > > 
> > > > > # dependencies on generated files need to be listed explicitly
> > > > > $(obj)/version.o: include/generated/compile.h
> > > > 
> > > > This only seems to work though when the dependent file is in the same
> > > > directory, but not when the file is in arch/mips/boot/.
> > > > 
> > > > I tried doing the include/generated/compile.h in Makefile instead of
> > > > common/Makefile, but then the version counting gets confused and causes
> > > > unnecessary rebuilds.
> > > > 
> > > > Any ideas how to solve this?
> > > 
> > > I can't reproduce parallel build breakage.
> > 
> > The failure starts here when using 6 threads or more and only when
> > compiling the black-swift_defconfig. After one successful build I can
> > reproduce this reliably here with:
> > 
> > rm -f include/generated/compile.h && make -j 6
> > 
> > > But I see another problem:
> > > the version string inside mips pbl binary is differ from the version string
> > > inside main barebox binary.
> > > 
> > > I suppose that the problem is that current build system handles mips asm files
> > > (which are actually use generated compile.h) and c-files in a different way.
> > 
> > Ups. How do the strings differ?
> 
> insert generated version into pbl by using mips_barebox_10h:
> 
> barebox$ git diff
> diff --git a/arch/mips/boards/qemu-malta/include/board/board_pbl_start.h b/arch/mips/boards/qemu-malta/include/board/board_pbl_start.h
> index 5c1537262e..6e85a7009a 100644
> --- a/arch/mips/boards/qemu-malta/include/board/board_pbl_start.h
> +++ b/arch/mips/boards/qemu-malta/include/board/board_pbl_start.h
> @@ -43,18 +43,8 @@
>         .set    push
>         .set    noreorder
>  
> -       b       __start
> -        nop
> +       mips_barebox_10h
>  
> -       /*
> -          On MIPS Technologies boards
> -          0x1fc00010 address is reserved for BoardID
> -       */
> -       .org    0x10
> -       .word   0xffffffff
> -       .word   0xffffffff
> -
> -__start:
>         mips_disable_interrupts
>  
>         /* cpu specific setup ... */
> barebox$ make mrproper
> ...
> barebox$ export ARCH=mips
> barebox$ export CROSS_COMPILE=mips-linux-gnu-
> barebox$ make qemu-malta_defconfig
> ...
> barebox$ make -j3 -s
> ...
> barebox$ xxd barebox-flash-image | head -n 6
> 00000000: 1000 0017 0000 0000 0000 0000 0000 0000  ................
> 00000010: 6261 7265 626f 7820 3230 3138 2e30 322e  barebox 2018.02.
> 00000020: 302d 3030 3037 392d 6731 6564 6462 3064  0-00079-g1eddb0d
> 00000030: 3338 322d 6469 7274 7920 2330 2046 7269  382-dirty #0 Fri
>                                                            ^^^^^^^
> 00000040: 204d 6172 2032 2031 363a 3032 3a32 3920   Mar 2 16:02:29 
> 00000050: 4d53 4b20 3230 3138 0000 0000 0000 0000  MSK 2018........
> 
> #0, 16:02:29 !!!!!!!!
> 
> barebox$ qemu-system-mips -nodefaults -M malta -m 256 \
> >                          -nographic -serial stdio -monitor null \
> >                          -bios barebox-flash-image
> 
> 
> barebox 2018.02.0-00079-g1eddb0d382-dirty #1 Fri Mar 2 16:02:38 MSK 2018
>                                         ^^^^^^^
> 
> #1, 16:02:38 !!!!!!!!

I can imagine this also goes down to the missing dependency. UTS_VERSION
contains the build number (the number behind the #) and the build date.

Now if the PBL macros lack the dependency and generated/compile.h is
included *before* it is re-generated whereas the files in common do have
the dependency and generated/compile.h is included after it has been
re-generated then you get the effect that you see above.

> 
> > Another obvious way to fix the issue is to remove UTS_RELEASE and
> > UTS_VERSION from the pbl headers. Would that be an option?
> 
> It isn't a __good__ option.

Why not? the IMD stuff was specifically designed to read the barebox
version from an image. What else do you need that makes the version
necessary at a fixed offset in the binary?

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From linux at rempel-privat.de  Sat Mar  3 01:03:28 2018
From: linux at rempel-privat.de (Oleksij Rempel)
Date: Sat,  3 Mar 2018 10:03:28 +0100
Subject: [PATCH] watchdog: add periodic watchdog ping
Message-ID: <20180303090328.10026-1-linux@rempel-privat.de>

This patch should cover at least this use cases:
- For production, for example automotive: cover as match as possible of SoC
life time with watchdog. Since some SoCs do not provide enough control over
watchdog timer it is not enough to enable it in PBL and retrigger in linux.
Barebox may need to retrigger it a few times as well.
- For remote development. If there is no way to power cycle the target except
of manually unplug it.

Signed-off-by: Oleksij Rempel <linux at rempel-privat.de>
---
 drivers/watchdog/wd_core.c | 57 ++++++++++++++++++++++++++++++++++++++++++++++
 include/watchdog.h         |  1 +
 2 files changed, 58 insertions(+)

diff --git a/drivers/watchdog/wd_core.c b/drivers/watchdog/wd_core.c
index 3a3f51964..e716a5f96 100644
--- a/drivers/watchdog/wd_core.c
+++ b/drivers/watchdog/wd_core.c
@@ -16,7 +16,11 @@
 #include <common.h>
 #include <command.h>
 #include <errno.h>
+#include <globalvar.h>
 #include <linux/ctype.h>
+#include <magicvar.h>
+#include <poller.h>
+#include <init.h>
 #include <watchdog.h>
 
 static LIST_HEAD(watchdog_list);
@@ -101,3 +105,56 @@ unsigned int of_get_watchdog_priority(struct device_node *node)
 
 	return priority;
 }
+
+static int watchdog_ping_enable;
+static unsigned int watchdog_ping_timeout;
+
+static void watchdog_ping_func(struct poller_struct *poller)
+{
+	struct watchdog *wd;
+	unsigned int timeout = watchdog_ping_timeout;
+
+	if (!watchdog_ping_enable)
+		return;
+
+	wd = watchdog_get_default();
+
+	if (!wd || wd->ping_next_event > get_time_ns())
+		return;
+
+	wd->ping_next_event = get_time_ns() + 500 * MSECOND;
+
+	pr_debug("setting timeout on %s to %ds\n", watchdog_name(wd), timeout);
+
+	wd->set_timeout(wd, timeout);
+}
+
+static struct poller_struct watchdog_poller = {
+	.func = watchdog_ping_func,
+};
+
+static int init_watchdog_ping_timeout(void)
+{
+	int err;
+
+	err = globalvar_add_simple_bool("watchdog.ping_enable",
+			&watchdog_ping_enable);
+	if (err)
+		return err;
+
+	err = globalvar_add_simple_int("watchdog.ping_timeout",
+			&watchdog_ping_timeout, "%u");
+	if (err)
+		return err;
+
+	return poller_register(&watchdog_poller);
+}
+late_initcall(init_watchdog_ping_timeout);
+
+BAREBOX_MAGICVAR_NAMED(global_watchdog_ping_enable,
+		       global.watchdog.ping_enable,
+		       "Enable periodic watchdog pings");
+
+BAREBOX_MAGICVAR_NAMED(global_watchdog_ping_timeout,
+		       global.watchdog.ping_timeout,
+		       "Periodic watchdog timeout in seconds");
diff --git a/include/watchdog.h b/include/watchdog.h
index 3e8a487a4..8966f0297 100644
--- a/include/watchdog.h
+++ b/include/watchdog.h
@@ -19,6 +19,7 @@ struct watchdog {
 	struct device_d *dev;
 	unsigned int priority;
 	struct list_head list;
+	uint64_t ping_next_event;
 };
 
 #ifdef CONFIG_WATCHDOG
-- 
2.14.1



From andrew.smirnov at gmail.com  Sat Mar  3 15:15:57 2018
From: andrew.smirnov at gmail.com (Andrey Smirnov)
Date: Sat, 3 Mar 2018 15:15:57 -0800
Subject: [PATCH] watchdog: add periodic watchdog ping
In-Reply-To: <20180303090328.10026-1-linux@rempel-privat.de>
References: <20180303090328.10026-1-linux@rempel-privat.de>
Message-ID: <CAHQ1cqFmfiGKnV6cuo_x-_v=097QQ16Qp-u2Z7S1wurCnb7H9A@mail.gmail.com>

On Sat, Mar 3, 2018 at 1:03 AM, Oleksij Rempel <linux at rempel-privat.de> wrote:
> This patch should cover at least this use cases:
> - For production, for example automotive: cover as match as possible of SoC
> life time with watchdog. Since some SoCs do not provide enough control over
> watchdog timer it is not enough to enable it in PBL and retrigger in linux.
> Barebox may need to retrigger it a few times as well.
> - For remote development. If there is no way to power cycle the target except
> of manually unplug it.
>
> Signed-off-by: Oleksij Rempel <linux at rempel-privat.de>
> ---
>  drivers/watchdog/wd_core.c | 57 ++++++++++++++++++++++++++++++++++++++++++++++
>  include/watchdog.h         |  1 +
>  2 files changed, 58 insertions(+)
>
> diff --git a/drivers/watchdog/wd_core.c b/drivers/watchdog/wd_core.c
> index 3a3f51964..e716a5f96 100644
> --- a/drivers/watchdog/wd_core.c
> +++ b/drivers/watchdog/wd_core.c
> @@ -16,7 +16,11 @@
>  #include <common.h>
>  #include <command.h>
>  #include <errno.h>
> +#include <globalvar.h>
>  #include <linux/ctype.h>
> +#include <magicvar.h>
> +#include <poller.h>
> +#include <init.h>
>  #include <watchdog.h>
>
>  static LIST_HEAD(watchdog_list);
> @@ -101,3 +105,56 @@ unsigned int of_get_watchdog_priority(struct device_node *node)
>
>         return priority;
>  }
> +
> +static int watchdog_ping_enable;
> +static unsigned int watchdog_ping_timeout;
> +
> +static void watchdog_ping_func(struct poller_struct *poller)
> +{
> +       struct watchdog *wd;
> +       unsigned int timeout = watchdog_ping_timeout;
> +
> +       if (!watchdog_ping_enable)
> +               return;
> +
> +       wd = watchdog_get_default();
> +
> +       if (!wd || wd->ping_next_event > get_time_ns())
> +               return;

What if for some bizarre reason (say legacy design that cannot be
changed) I have a system with more than one watchdog that needs to be
petted? I'd consider making pollers a per watchdog device thing and
also converting the code to use "struct poller_async" since it'll
already implement periodic execution.

> +
> +       wd->ping_next_event = get_time_ns() + 500 * MSECOND;
> +

I'd expect your petting frequency to be tied to watchdog timeout
period (say half the period), and not just fixed to 0.5 seconds. Is
this on purpose?

> +       pr_debug("setting timeout on %s to %ds\n", watchdog_name(wd), timeout);
> +
> +       wd->set_timeout(wd, timeout);

This changes the semantics of "set_timeout" callback, before, when
notion of "petting" a watchdog didn't exist, it only changed the
timeout setting, whereas with your patch it also becomes responsible
for petting as well. It depends on IP block's implementation, but it
is not that uncommon for one to have those functions -- petting and
changing the timeout -- to be implemented separately, oftentimes via
different registers. Just as a suggestion, it might be better to
introduce a separate "pet()"/"ping()" callback and have the framework
print a warning when used against a driver that was not explicitly
ported to support the notion of "petting".

> +}
> +
> +static struct poller_struct watchdog_poller = {
> +       .func = watchdog_ping_func,
> +};
> +
> +static int init_watchdog_ping_timeout(void)
> +{
> +       int err;
> +
> +       err = globalvar_add_simple_bool("watchdog.ping_enable",
> +                       &watchdog_ping_enable);
> +       if (err)
> +               return err;
> +
> +       err = globalvar_add_simple_int("watchdog.ping_timeout",
> +                       &watchdog_ping_timeout, "%u");
> +       if (err)
> +               return err;
> +
> +       return poller_register(&watchdog_poller);
> +}
> +late_initcall(init_watchdog_ping_timeout);
> +
> +BAREBOX_MAGICVAR_NAMED(global_watchdog_ping_enable,
> +                      global.watchdog.ping_enable,
> +                      "Enable periodic watchdog pings");
> +
> +BAREBOX_MAGICVAR_NAMED(global_watchdog_ping_timeout,
> +                      global.watchdog.ping_timeout,
> +                      "Periodic watchdog timeout in seconds");

As another suggestion, consider porting the notion of timeout
boundaries (max_timeout, min_timeout) similar to what exists in Linux
kernel to allow some bounds checking and avoiding setting bogus
timeout values.

Thanks,
Andrey Smrinov


From s.hauer at pengutronix.de  Sun Mar  4 23:48:01 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Mon, 5 Mar 2018 08:48:01 +0100
Subject: v2018.03.0
Message-ID: <20180305074801.mkoxhnki3n2cb2oc@pengutronix.de>


Hi All,

barebox-v2018.03.0 is out.

Some work has been done in the area if FIT images. We have now a greater
flexibility in which images can be opened, and when they are opened less
memory is used since we have to do one less copy of the image.
Another thing worth noting is that squashfs can now do zstd.

As usual, see below for a detailed list of patches.

Sascha

----------------------------------------------------------------
Aleksander Morgado (5):
      bbremote: rename command subparser variables
      ratp: rename global context variable
      ratp: move barebox-specific command to ratp_bb.h
      ratp: remove unused list pointer from ratp_bb_pkt
      ratp: remove unused context fields

Andrey Smirnov (1):
      at91sam9x5ek: Add appropriate compatibility guards to all initcalls

Antony Pavlov (5):
      sandbox: use 'poweroff' command for exit
      sandbox: avoid symbol conflict for {open,read,close}dir
      sandbox: add gpio support with libftdi1
      sandbox: add i2c and spi libftdi1 bit-bang example
      i2c: i2c_master_send(): don't leave flags uninitialized

Daniel Schultz (2):
      commands: ubi: ubiupdatevol: Reduce error code to 0 or 1
      ARM: configs: am335x_defconfig: Reorder configs

Lucas Stach (7):
      net: phy: scan PHYs referenced by phandle
      net/e1000: remove one level of indentation
      net/e1000: use correct bit for flash detection
      net/e1000: EEPROM isn't valid if only iNVM is available
      net/e1000: don't check EEPROM signature if populated from iNVM
      net/e1000: don't register EERPOM device if the content is invalid
      net: phy: fixed-link: read link parameters from devicetree

Michael Olbrich (1):
      scripts/compiler.h: inline functions in headers must be static

Philipp Zabel (7):
      fs/parseopt: Add parseopt_llu_suffix
      filetype: Add type detection at an offset
      fs: add support loop mount offset
      include linux/compiler.h in linux/unaligned/generic.h
      lib: Add xxhash module
      lib: Add zstd decompression module
      squashfs: Add zstd support

Sascha Hauer (51):
      startup: create /tmp
      fs: implement is_tftp_fs()
      libfile: implement make_temp
      libfile: implement a function to cache a file
      uimage: fix memory leak in error path
      uimage: Use is_tftp_fs() and cache_file() to ease TFTP workaround
      fs/uimagefs: Use is_tftp_fs() and cache_file() to ease TFTP workaround
      fs: remove now unused function can_lseek_backward()
      fs: Fix memory leak in mount()
      bootargs: Fix memory leak in linux_bootargs_get()
      imd: Make all pointers into image const
      bbu: imx-bbu-internal: Do not modify image
      bbu: imx-bbu-internal: make pointers to image const
      bbu: command: create temporary variable holding the pointer to the image
      bbu: Make pointer to image const
      usb: gadget: fastboot: allow data.image to be const
      ARM: am33xx: bbu: Make pointers to image const
      rsa: Add missing newline to pr_err messages
      pinctrl: do not dereference a device tree property directly
      libfile: Make write_file buffer const
      of: Allow for const properties
      of: fdt: add of_unflatten_dtb_const
      pstore: lower message priority
      state: refuse to set dirty parameter via setenv
      state: Add 'init_from_defaults' parameter
      startup: Load default environment earlier
      boot: Make independent of command support
      bootchooser: Drop SHELL_NONE conflict
      bootm: FIT: do not depend on FIT pre-opened images
      FIT: Do not pre-open images
      FIT: Let user specify the configuration to use
      FIT: store device_nodes in fit_handle
      FIT: move handle->verify check to fit_verify_hash()
      FIT: factor out some helper functions
      FIT: Implement opening images with no configuration
      FIT: Allow to open buffer as FIT image
      env: Add more context to error message
      Merge branch 'for-next/FIT'
      Merge branch 'for-next/at91'
      Merge branch 'for-next/constify'
      Merge branch 'for-next/e1000'
      Merge branch 'for-next/misc'
      Merge branch 'for-next/of'
      Merge branch 'for-next/ratp'
      Merge branch 'for-next/sandbox-libftdi'
      Merge branch 'for-next/tftp-workaround'
      Merge branch 'for-next/zstd'
      FIT: Use const dtb unflatten variant
      state: remove unused arguments from state_new_from_node()
      state: find backend node with its reproducible name
      Release v2018.03.0

Uwe Kleine-K?nig (1):
      i2c: read/write_reg: don't assume client->dev to be valid
-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From andrey.gusakov at cogentembedded.com  Mon Mar  5 06:19:53 2018
From: andrey.gusakov at cogentembedded.com (Andrey Gusakov)
Date: Mon,  5 Mar 2018 17:19:53 +0300
Subject: [PATCH] video: tc358767: register aux i2c bus after validating link
Message-ID: <1520259593-21311-1-git-send-email-andrey.gusakov@cogentembedded.com>

Register AUX i2c adapter only if AUX link is functional. This
should avoid possible hung during tc358767 probe when no display
connected.

Signed-off-by: Andrey Gusakov <andrey.gusakov at cogentembedded.com>
---
 drivers/video/tc358767.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/video/tc358767.c b/drivers/video/tc358767.c
index f9ca06c..5ad5cb4 100644
--- a/drivers/video/tc358767.c
+++ b/drivers/video/tc358767.c
@@ -1404,6 +1404,10 @@ static int tc_probe(struct device_d *dev)
 	if (ret)
 		goto err;
 
+	ret = tc_get_display_props(tc);
+	if (ret)
+		goto err;
+
 	/* Register DP AUX channel */
 	tc->adapter.master_xfer = tc_aux_i2c_xfer;
 	tc->adapter.nr = -1; /* any free */
@@ -1416,10 +1420,6 @@ static int tc_probe(struct device_d *dev)
 		goto err;
 	}
 
-	ret = tc_get_display_props(tc);
-	if (ret)
-		goto err;
-
 	/* add vlp */
 	tc->vpl.node = dev->device_node;
 	tc->vpl.ioctl = tc_ioctl;
-- 
1.9.1



From o.rempel at pengutronix.de  Thu Mar  8 03:05:10 2018
From: o.rempel at pengutronix.de (Oleksij Rempel)
Date: Thu,  8 Mar 2018 12:05:10 +0100
Subject: [PATCH v1 1/6] watchdog: rename dev to hwdev
Message-ID: <20180308110515.29574-1-o.rempel@pengutronix.de>

From: Sascha Hauer <s.hauer at pengutronix.de>

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 drivers/watchdog/ar9344_wdt.c  | 2 +-
 drivers/watchdog/davinci_wdt.c | 2 +-
 drivers/watchdog/dw_wdt.c      | 4 ++--
 drivers/watchdog/im28wd.c      | 2 +-
 drivers/watchdog/imxwd.c       | 2 +-
 drivers/watchdog/orion_wdt.c   | 2 +-
 drivers/watchdog/wd_core.c     | 4 ++--
 include/watchdog.h             | 2 +-
 8 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/drivers/watchdog/ar9344_wdt.c b/drivers/watchdog/ar9344_wdt.c
index d570cb40f..c1dfc994a 100644
--- a/drivers/watchdog/ar9344_wdt.c
+++ b/drivers/watchdog/ar9344_wdt.c
@@ -95,7 +95,7 @@ static int ar9344_wdt_probe(struct device_d *dev)
 
 	priv->base = IOMEM(iores->start);
 	priv->wd.set_timeout = ar9344_watchdog_set_timeout;
-	priv->wd.dev = dev;
+	priv->wd.hwdev = dev;
 	priv->dev = dev;
 
 	dev->priv = priv;
diff --git a/drivers/watchdog/davinci_wdt.c b/drivers/watchdog/davinci_wdt.c
index 03dc83408..2ac5f8b38 100644
--- a/drivers/watchdog/davinci_wdt.c
+++ b/drivers/watchdog/davinci_wdt.c
@@ -149,7 +149,7 @@ static int davinci_wdt_probe(struct device_d *dev)
 	clk_enable(davinci_wdt->clk);
 
 	davinci_wdt->wd.set_timeout = davinci_wdt_set_timeout;
-	davinci_wdt->wd.dev = dev;
+	davinci_wdt->wd.hwdev = dev;
 
 	ret = watchdog_register(&davinci_wdt->wd);
 	if (ret < 0)
diff --git a/drivers/watchdog/dw_wdt.c b/drivers/watchdog/dw_wdt.c
index 8fd8c81e6..85e810f24 100644
--- a/drivers/watchdog/dw_wdt.c
+++ b/drivers/watchdog/dw_wdt.c
@@ -73,7 +73,7 @@ static int dw_wdt_stop(struct watchdog *wdd)
 	struct dw_wdt *dw_wdt = to_dw_wdt(wdd);
 
 	if (IS_ERR(dw_wdt->rst)) {
-		dev_warn(dw_wdt->wdd.dev, "No reset line. Will not stop.\n");
+		dev_warn(dw_wdt->wdd.hwdev, "No reset line. Will not stop.\n");
 		return PTR_ERR(dw_wdt->rst);
 	}
 
@@ -157,7 +157,7 @@ static int dw_wdt_drv_probe(struct device_d *dev)
 
 	wdd = &dw_wdt->wdd;
 	wdd->name = "dw_wdt";
-	wdd->dev = dev;
+	wdd->hwdev = dev;
 	wdd->set_timeout = dw_wdt_set_timeout;
 
 	ret = watchdog_register(wdd);
diff --git a/drivers/watchdog/im28wd.c b/drivers/watchdog/im28wd.c
index 1956fdb73..43edea8d0 100644
--- a/drivers/watchdog/im28wd.c
+++ b/drivers/watchdog/im28wd.c
@@ -199,7 +199,7 @@ static int imx28_wd_probe(struct device_d *dev)
 		return PTR_ERR(iores);
 	priv->regs = IOMEM(iores->start);
 	priv->wd.set_timeout = imx28_watchdog_set_timeout;
-	priv->wd.dev = dev;
+	priv->wd.hwdev = dev;
 
 	if (!(readl(priv->regs + MXS_RTC_STAT) & MXS_RTC_STAT_WD_PRESENT)) {
 		rc = -ENODEV;
diff --git a/drivers/watchdog/imxwd.c b/drivers/watchdog/imxwd.c
index bd5e518bc..6b33834fe 100644
--- a/drivers/watchdog/imxwd.c
+++ b/drivers/watchdog/imxwd.c
@@ -218,7 +218,7 @@ static int imx_wd_probe(struct device_d *dev)
 	priv->base = IOMEM(iores->start);
 	priv->ops = ops;
 	priv->wd.set_timeout = imx_watchdog_set_timeout;
-	priv->wd.dev = dev;
+	priv->wd.hwdev = dev;
 	priv->dev = dev;
 
 	priv->ext_reset = of_property_read_bool(dev->device_node,
diff --git a/drivers/watchdog/orion_wdt.c b/drivers/watchdog/orion_wdt.c
index 2802033f7..4fe1ac1fd 100644
--- a/drivers/watchdog/orion_wdt.c
+++ b/drivers/watchdog/orion_wdt.c
@@ -88,7 +88,7 @@ static int orion_wdt_probe(struct device_d *dev)
 
 	ddata->wd.set_timeout = armada_xp_set_timeout;
 	ddata->wd.name = "orion_wdt";
-	ddata->wd.dev = dev;
+	ddata->wd.hwdev = dev;
 
 	res_timer = dev_request_mem_resource(dev, 0);
 	if (IS_ERR(res_timer)) {
diff --git a/drivers/watchdog/wd_core.c b/drivers/watchdog/wd_core.c
index 3a3f51964..56436e6f8 100644
--- a/drivers/watchdog/wd_core.c
+++ b/drivers/watchdog/wd_core.c
@@ -23,8 +23,8 @@ static LIST_HEAD(watchdog_list);
 
 static const char *watchdog_name(struct watchdog *wd)
 {
-	if (wd->dev)
-		return dev_name(wd->dev);
+	if (wd->hwdev)
+		return dev_name(wd->hwdev);
 	if (wd->name)
 		return wd->name;
 
diff --git a/include/watchdog.h b/include/watchdog.h
index 3e8a487a4..848981cc0 100644
--- a/include/watchdog.h
+++ b/include/watchdog.h
@@ -16,7 +16,7 @@
 struct watchdog {
 	int (*set_timeout)(struct watchdog *, unsigned);
 	const char *name;
-	struct device_d *dev;
+	struct device_d *hwdev;
 	unsigned int priority;
 	struct list_head list;
 };
-- 
2.16.1



From o.rempel at pengutronix.de  Thu Mar  8 03:05:11 2018
From: o.rempel at pengutronix.de (Oleksij Rempel)
Date: Thu,  8 Mar 2018 12:05:11 +0100
Subject: [PATCH v1 2/6] watchdog: move max timeout test in to wd_core
In-Reply-To: <20180308110515.29574-1-o.rempel@pengutronix.de>
References: <20180308110515.29574-1-o.rempel@pengutronix.de>
Message-ID: <20180308110515.29574-2-o.rempel@pengutronix.de>

From: Oleksij Rempel <linux at rempel-privat.de>

this also will be needed for watchdog poller as well

Signed-off-by: Oleksij Rempel <linux at rempel-privat.de>
---
 drivers/watchdog/ar9344_wdt.c | 15 ++++-----------
 drivers/watchdog/im28wd.c     |  4 +---
 drivers/watchdog/imxwd.c      | 10 ++++------
 drivers/watchdog/orion_wdt.c  |  4 +---
 drivers/watchdog/wd_core.c    |  6 ++++++
 include/watchdog.h            |  1 +
 6 files changed, 17 insertions(+), 23 deletions(-)

diff --git a/drivers/watchdog/ar9344_wdt.c b/drivers/watchdog/ar9344_wdt.c
index c1dfc994a..461528863 100644
--- a/drivers/watchdog/ar9344_wdt.c
+++ b/drivers/watchdog/ar9344_wdt.c
@@ -41,20 +41,11 @@ struct ar9344_wd {
 static int ar9344_watchdog_set_timeout(struct watchdog *wd, unsigned timeout)
 {
 	struct ar9344_wd *priv = to_ar9344_wd(wd);
-	u32 val, ctrl, rate, max_timout;
-
-	rate = clk_get_rate(priv->clk);
-	max_timout = U32_MAX / rate;
-
-	if (timeout > max_timout) {
-		dev_err(priv->dev, "timeout value out of range: %d > %d\n",
-			timeout, max_timout);
-		return -EINVAL;
-	}
+	u32 val, ctrl;
 
 	if (timeout) {
 		ctrl = AR9344_WD_CTRL_ACTION_FCR;
-		val = timeout * rate;
+		val = timeout * clk_get_rate(priv->clk);
 	} else {
 		ctrl = AR9344_WD_CTRL_ACTION_NONE;
 		val = U32_MAX;
@@ -111,6 +102,8 @@ static int ar9344_wdt_probe(struct device_d *dev)
 
 	clk_enable(priv->clk);
 
+	priv->wd.timeout_max = U32_MAX / clk_get_rate(priv->clk);
+
 	ret = watchdog_register(&priv->wd);
 	if (ret)
 		goto on_error;
diff --git a/drivers/watchdog/im28wd.c b/drivers/watchdog/im28wd.c
index 43edea8d0..2b233ede2 100644
--- a/drivers/watchdog/im28wd.c
+++ b/drivers/watchdog/im28wd.c
@@ -133,9 +133,6 @@ static int imx28_watchdog_set_timeout(struct watchdog *wd, unsigned timeout)
 	struct imx28_wd *pwd = (struct imx28_wd *)to_imx28_wd(wd);
 	void __iomem *base;
 
-	if (timeout > (ULONG_MAX / WDOG_TICK_RATE))
-		return -EINVAL;
-
 	if (timeout) {
 		writel(timeout * WDOG_TICK_RATE, pwd->regs + MXS_RTC_WATCHDOG);
 		base = pwd->regs + MXS_RTC_SET_ADDR;
@@ -199,6 +196,7 @@ static int imx28_wd_probe(struct device_d *dev)
 		return PTR_ERR(iores);
 	priv->regs = IOMEM(iores->start);
 	priv->wd.set_timeout = imx28_watchdog_set_timeout;
+	priv->wd.timeout_max = ULONG_MAX / WDOG_TICK_RATE;
 	priv->wd.hwdev = dev;
 
 	if (!(readl(priv->regs + MXS_RTC_STAT) & MXS_RTC_STAT_WD_PRESENT)) {
diff --git a/drivers/watchdog/imxwd.c b/drivers/watchdog/imxwd.c
index 6b33834fe..a66fae400 100644
--- a/drivers/watchdog/imxwd.c
+++ b/drivers/watchdog/imxwd.c
@@ -28,6 +28,7 @@ struct imx_wd_ops {
 	int (*set_timeout)(struct imx_wd *, unsigned);
 	void (*soc_reset)(struct imx_wd *);
 	int (*init)(struct imx_wd *);
+	unsigned int timeout_max;
 };
 
 struct imx_wd {
@@ -71,9 +72,6 @@ static int imx1_watchdog_set_timeout(struct imx_wd *priv, unsigned timeout)
 
 	dev_dbg(priv->dev, "%s: %d\n", __func__, timeout);
 
-	if (timeout > 64)
-		return -EINVAL;
-
 	if (!timeout) {
 		writew(IMX1_WDOG_WCR_WHALT, priv->base + IMX1_WDOG_WCR);
 		return 0;
@@ -102,9 +100,6 @@ static int imx21_watchdog_set_timeout(struct imx_wd *priv, unsigned timeout)
 
 	dev_dbg(priv->dev, "%s: %d\n", __func__, timeout);
 
-	if (timeout > 128)
-		return -EINVAL;
-
 	if (timeout == 0) /* bit 2 (WDE) cannot be set to 0 again */
 		return -ENOSYS;
 
@@ -218,6 +213,7 @@ static int imx_wd_probe(struct device_d *dev)
 	priv->base = IOMEM(iores->start);
 	priv->ops = ops;
 	priv->wd.set_timeout = imx_watchdog_set_timeout;
+	priv->wd.timeout_max = priv->ops->timeout_max;
 	priv->wd.hwdev = dev;
 	priv->dev = dev;
 
@@ -259,11 +255,13 @@ static const struct imx_wd_ops imx21_wd_ops = {
 	.set_timeout = imx21_watchdog_set_timeout,
 	.soc_reset = imx21_soc_reset,
 	.init = imx21_wd_init,
+	.timeout_max = 128,
 };
 
 static const struct imx_wd_ops imx1_wd_ops = {
 	.set_timeout = imx1_watchdog_set_timeout,
 	.soc_reset = imx1_soc_reset,
+	.timeout_max = 64,
 };
 
 static __maybe_unused struct of_device_id imx_wdt_dt_ids[] = {
diff --git a/drivers/watchdog/orion_wdt.c b/drivers/watchdog/orion_wdt.c
index 4fe1ac1fd..dd1fa3a04 100644
--- a/drivers/watchdog/orion_wdt.c
+++ b/drivers/watchdog/orion_wdt.c
@@ -49,9 +49,6 @@ static int armada_xp_set_timeout(struct watchdog *wd, unsigned timeout)
 		container_of(wd, struct orion_wdt_ddata, wd);
 	u32 ctrl;
 
-	if (0xffffffff / CLKRATE < timeout)
-		return -EINVAL;
-
 	ctrl = readl(ddata->timer_base + TIMER_CTRL);
 
 	if (timeout == 0) {
@@ -89,6 +86,7 @@ static int orion_wdt_probe(struct device_d *dev)
 	ddata->wd.set_timeout = armada_xp_set_timeout;
 	ddata->wd.name = "orion_wdt";
 	ddata->wd.hwdev = dev;
+	ddata->wd.timeout_max = U32_MAX / CLKRATE;
 
 	res_timer = dev_request_mem_resource(dev, 0);
 	if (IS_ERR(res_timer)) {
diff --git a/drivers/watchdog/wd_core.c b/drivers/watchdog/wd_core.c
index 56436e6f8..1d0f0de7d 100644
--- a/drivers/watchdog/wd_core.c
+++ b/drivers/watchdog/wd_core.c
@@ -36,6 +36,9 @@ int watchdog_register(struct watchdog *wd)
 	if (!wd->priority)
 		wd->priority = WATCHDOG_DEFAULT_PRIORITY;
 
+	dev_add_param_uint32_ro(&wd->dev, "timeout_max",
+			&wd->timeout_max, "%u");
+
 	list_add_tail(&wd->list, &watchdog_list);
 
 	pr_debug("registering watchdog %s with priority %d\n", watchdog_name(wd),
@@ -81,6 +84,9 @@ int watchdog_set_timeout(unsigned timeout)
 	if (!wd)
 		return -ENODEV;
 
+	if (timeout > wd->timeout_max)
+		return -EINVAL;
+
 	pr_debug("setting timeout on %s to %ds\n", watchdog_name(wd), timeout);
 
 	return wd->set_timeout(wd, timeout);
diff --git a/include/watchdog.h b/include/watchdog.h
index 848981cc0..1e06fbc3f 100644
--- a/include/watchdog.h
+++ b/include/watchdog.h
@@ -18,6 +18,7 @@ struct watchdog {
 	const char *name;
 	struct device_d *hwdev;
 	unsigned int priority;
+	unsigned int timeout_max;
 	struct list_head list;
 };
 
-- 
2.16.1



From o.rempel at pengutronix.de  Thu Mar  8 03:05:14 2018
From: o.rempel at pengutronix.de (Oleksij Rempel)
Date: Thu,  8 Mar 2018 12:05:14 +0100
Subject: [PATCH v1 5/6] watchdog: provide timeout_cur value
In-Reply-To: <20180308110515.29574-1-o.rempel@pengutronix.de>
References: <20180308110515.29574-1-o.rempel@pengutronix.de>
Message-ID: <20180308110515.29574-5-o.rempel@pengutronix.de>

timeout_cur will be used for watchdog poller.
Provided values should be good enough for most users
and still can be changed for separate projects and
fit to needed requirements.

Signed-off-by: Oleksij Rempel <o.rempel at pengutronix.de>
---
 drivers/watchdog/wd_core.c | 15 +++++++++++++++
 include/watchdog.h         |  1 +
 2 files changed, 16 insertions(+)

diff --git a/drivers/watchdog/wd_core.c b/drivers/watchdog/wd_core.c
index 66dbd790d..3162dd59c 100644
--- a/drivers/watchdog/wd_core.c
+++ b/drivers/watchdog/wd_core.c
@@ -31,6 +31,16 @@ static const char *watchdog_name(struct watchdog *wd)
 	return "unknown";
 }
 
+static int watchdog_set_cur(struct param_d *param, void *priv)
+{
+	struct watchdog *wd = priv;
+
+	if (wd->timeout_cur > wd->timeout_max)
+		return -EINVAL;
+
+	return 0;
+}
+
 int watchdog_register(struct watchdog *wd)
 {
 
@@ -45,8 +55,13 @@ int watchdog_register(struct watchdog *wd)
 	if (!wd->timeout_max)
 		wd->timeout_max = 60 * 4;
 
+	if (!wd->timeout_cur || wd->timeout_cur > wd->timeout_max)
+		wd->timeout_cur = wd->timeout_max;
+
 	dev_add_param_uint32_ro(&wd->dev, "timeout_max",
 			&wd->timeout_max, "%u");
+	dev_add_param_uint32(&wd->dev, "timeout_cur", watchdog_set_cur, NULL,
+			&wd->timeout_cur, "%u", wd);
 
 	list_add_tail(&wd->list, &watchdog_list);
 
diff --git a/include/watchdog.h b/include/watchdog.h
index a2459d255..2f1874c19 100644
--- a/include/watchdog.h
+++ b/include/watchdog.h
@@ -20,6 +20,7 @@ struct watchdog {
 	struct device_d dev;
 	unsigned int priority;
 	unsigned int timeout_max;
+	unsigned int timeout_cur;
 	struct list_head list;
 };
 
-- 
2.16.1



From o.rempel at pengutronix.de  Thu Mar  8 03:05:15 2018
From: o.rempel at pengutronix.de (Oleksij Rempel)
Date: Thu,  8 Mar 2018 12:05:15 +0100
Subject: [PATCH v1 6/6] watchdog: add watchdog poller
In-Reply-To: <20180308110515.29574-1-o.rempel@pengutronix.de>
References: <20180308110515.29574-1-o.rempel@pengutronix.de>
Message-ID: <20180308110515.29574-6-o.rempel@pengutronix.de>

In some cases it is practical to supervise as match as possible of
barebox execution with watchdog (or multiple watchdogs). This
patch provide async poller for watchdog core framework which can
be enabled by user and store this configuration to nv.

Signed-off-by: Oleksij Rempel <o.rempel at pengutronix.de>
---
 drivers/watchdog/wd_core.c | 54 ++++++++++++++++++++++++++++++++++++++++------
 include/watchdog.h         |  4 ++++
 2 files changed, 52 insertions(+), 6 deletions(-)

diff --git a/drivers/watchdog/wd_core.c b/drivers/watchdog/wd_core.c
index 3162dd59c..6f1cadaf8 100644
--- a/drivers/watchdog/wd_core.c
+++ b/drivers/watchdog/wd_core.c
@@ -31,6 +31,16 @@ static const char *watchdog_name(struct watchdog *wd)
 	return "unknown";
 }
 
+static int _watchdog_set_timeout(struct watchdog *wd, unsigned timeout)
+{
+	if (timeout > wd->timeout_max)
+		return -EINVAL;
+
+	pr_debug("setting timeout on %s to %ds\n", watchdog_name(wd), timeout);
+
+	return wd->set_timeout(wd, timeout);
+}
+
 static int watchdog_set_cur(struct param_d *param, void *priv)
 {
 	struct watchdog *wd = priv;
@@ -41,6 +51,37 @@ static int watchdog_set_cur(struct param_d *param, void *priv)
 	return 0;
 }
 
+static void watchdog_poller_cb(void *priv);
+
+static void watchdog_poller_start(struct watchdog *wd)
+{
+	_watchdog_set_timeout(wd, wd->timeout_cur);
+	poller_call_async(&wd->poller, 500 * MSECOND,
+			watchdog_poller_cb, wd);
+
+}
+
+static void watchdog_poller_cb(void *priv)
+{
+	struct watchdog *wd = priv;
+
+	if (wd->poller_enable)
+		watchdog_poller_start(wd);
+}
+
+static int watchdog_set_poller(struct param_d *param, void *priv)
+{
+	struct watchdog *wd = priv;
+
+
+	if (wd->poller_enable)
+		watchdog_poller_start(wd);
+	else
+		poller_async_cancel(&wd->poller);
+
+	return 0;
+}
+
 int watchdog_register(struct watchdog *wd)
 {
 
@@ -63,6 +104,10 @@ int watchdog_register(struct watchdog *wd)
 	dev_add_param_uint32(&wd->dev, "timeout_cur", watchdog_set_cur, NULL,
 			&wd->timeout_cur, "%u", wd);
 
+	poller_async_register(&wd->poller);
+	dev_add_param_bool(&wd->dev, "poller_enable", watchdog_set_poller, NULL,
+			&wd->poller_enable, wd);
+
 	list_add_tail(&wd->list, &watchdog_list);
 
 	pr_debug("registering watchdog %s with priority %d\n", watchdog_name(wd),
@@ -74,6 +119,8 @@ EXPORT_SYMBOL(watchdog_register);
 
 int watchdog_deregister(struct watchdog *wd)
 {
+	poller_async_cancel(&wd->poller);
+	poller_async_unregister(&wd->poller);
 	unregister_device(&wd->dev);
 	list_del(&wd->list);
 
@@ -109,12 +156,7 @@ int watchdog_set_timeout(unsigned timeout)
 	if (!wd)
 		return -ENODEV;
 
-	if (timeout > wd->timeout_max)
-		return -EINVAL;
-
-	pr_debug("setting timeout on %s to %ds\n", watchdog_name(wd), timeout);
-
-	return wd->set_timeout(wd, timeout);
+	return _watchdog_set_timeout(wd, timeout);
 }
 EXPORT_SYMBOL(watchdog_set_timeout);
 
diff --git a/include/watchdog.h b/include/watchdog.h
index 2f1874c19..0db4263a3 100644
--- a/include/watchdog.h
+++ b/include/watchdog.h
@@ -13,6 +13,8 @@
 #ifndef INCLUDE_WATCHDOG_H
 # define INCLUDE_WATCHDOG_H
 
+#include <poller.h>
+
 struct watchdog {
 	int (*set_timeout)(struct watchdog *, unsigned);
 	const char *name;
@@ -21,6 +23,8 @@ struct watchdog {
 	unsigned int priority;
 	unsigned int timeout_max;
 	unsigned int timeout_cur;
+	unsigned int poller_enable;
+	struct poller_async poller;
 	struct list_head list;
 };
 
-- 
2.16.1



From o.rempel at pengutronix.de  Thu Mar  8 03:05:13 2018
From: o.rempel at pengutronix.de (Oleksij Rempel)
Date: Thu,  8 Mar 2018 12:05:13 +0100
Subject: [PATCH v1 4/6] watchdog: set some reasonable timeout_max value if no
 other is available
In-Reply-To: <20180308110515.29574-1-o.rempel@pengutronix.de>
References: <20180308110515.29574-1-o.rempel@pengutronix.de>
Message-ID: <20180308110515.29574-4-o.rempel@pengutronix.de>

Some drivers do not provide timeout_max value.
Using some value is probbaly better then setting timeout_max to 0.

Signed-off-by: Oleksij Rempel <o.rempel at pengutronix.de>
---
 drivers/watchdog/wd_core.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/watchdog/wd_core.c b/drivers/watchdog/wd_core.c
index 97e2ab568..66dbd790d 100644
--- a/drivers/watchdog/wd_core.c
+++ b/drivers/watchdog/wd_core.c
@@ -41,6 +41,10 @@ int watchdog_register(struct watchdog *wd)
 	if (!wd->priority)
 		wd->priority = WATCHDOG_DEFAULT_PRIORITY;
 
+	/* set some default sane value */
+	if (!wd->timeout_max)
+		wd->timeout_max = 60 * 4;
+
 	dev_add_param_uint32_ro(&wd->dev, "timeout_max",
 			&wd->timeout_max, "%u");
 
-- 
2.16.1



From o.rempel at pengutronix.de  Thu Mar  8 03:05:12 2018
From: o.rempel at pengutronix.de (Oleksij Rempel)
Date: Thu,  8 Mar 2018 12:05:12 +0100
Subject: [PATCH v1 3/6] watchdog: register watchdog virtual device with short
 name wdog
In-Reply-To: <20180308110515.29574-1-o.rempel@pengutronix.de>
References: <20180308110515.29574-1-o.rempel@pengutronix.de>
Message-ID: <20180308110515.29574-3-o.rempel@pengutronix.de>

the watchdog hwdev is usually named with devicetree schema
which is not practical for CLI.

On device registration "wdog" will be extended with some index number
extracted from devicetree (if awailable) or automatically assigned
first available number. End result will be "wdog0" .. etc.

Signed-off-by: Oleksij Rempel <o.rempel at pengutronix.de>
---
 drivers/watchdog/wd_core.c | 6 ++++++
 include/watchdog.h         | 1 +
 2 files changed, 7 insertions(+)

diff --git a/drivers/watchdog/wd_core.c b/drivers/watchdog/wd_core.c
index 1d0f0de7d..97e2ab568 100644
--- a/drivers/watchdog/wd_core.c
+++ b/drivers/watchdog/wd_core.c
@@ -33,6 +33,11 @@ static const char *watchdog_name(struct watchdog *wd)
 
 int watchdog_register(struct watchdog *wd)
 {
+
+	strcpy(wd->dev.name, "wdog");
+	wd->dev.parent = wd->hwdev;
+	register_device(&wd->dev);
+
 	if (!wd->priority)
 		wd->priority = WATCHDOG_DEFAULT_PRIORITY;
 
@@ -50,6 +55,7 @@ EXPORT_SYMBOL(watchdog_register);
 
 int watchdog_deregister(struct watchdog *wd)
 {
+	unregister_device(&wd->dev);
 	list_del(&wd->list);
 
 	return 0;
diff --git a/include/watchdog.h b/include/watchdog.h
index 1e06fbc3f..a2459d255 100644
--- a/include/watchdog.h
+++ b/include/watchdog.h
@@ -17,6 +17,7 @@ struct watchdog {
 	int (*set_timeout)(struct watchdog *, unsigned);
 	const char *name;
 	struct device_d *hwdev;
+	struct device_d dev;
 	unsigned int priority;
 	unsigned int timeout_max;
 	struct list_head list;
-- 
2.16.1



From jlu at pengutronix.de  Thu Mar  8 05:49:29 2018
From: jlu at pengutronix.de (Jan =?ISO-8859-1?Q?L=FCbbe?=)
Date: Thu, 08 Mar 2018 14:49:29 +0100
Subject: [PATCH v1 6/6] watchdog: add watchdog poller
In-Reply-To: <20180308110515.29574-6-o.rempel@pengutronix.de>
References: <20180308110515.29574-1-o.rempel@pengutronix.de>
 <20180308110515.29574-6-o.rempel@pengutronix.de>
Message-ID: <1520516969.31759.115.camel@pengutronix.de>

Hi Oleksij,

On Thu, 2018-03-08 at 12:05 +0100, Oleksij Rempel wrote:
> In some cases it is practical to supervise as match as possible of
s/match/much/
> barebox execution with watchdog (or multiple watchdogs). This
 ^ the                  ^ a
> patch provide async poller for watchdog core framework which can
              ^-s an
> be enabled by user and store this configuration to nv.
               ^the           ^-s

Also, does this patch make the poller support required for using
watchdogs? It unconditionally calls the poller_* functions.

Also, it should be documented explicitly, that this will cause barebox
to keep triggering the watchdog, even when it drops to the shell after
a boot error. This makes it unsuitable for unattended use.

I'd prefer to make this optional at compile time.

> 
> Signed-off-by: Oleksij Rempel <o.rempel at pengutronix.de>
> ---
>  drivers/watchdog/wd_core.c | 54
> ++++++++++++++++++++++++++++++++++++++++------
>  include/watchdog.h         |  4 ++++
>  2 files changed, 52 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/watchdog/wd_core.c b/drivers/watchdog/wd_core.c
> index 3162dd59c..6f1cadaf8 100644
> --- a/drivers/watchdog/wd_core.c
> +++ b/drivers/watchdog/wd_core.c
> @@ -31,6 +31,16 @@ static const char *watchdog_name(struct watchdog
> *wd)
>  	return "unknown";
>  }
>  
> +static int _watchdog_set_timeout(struct watchdog *wd, unsigned
> timeout)
> +{
> +	if (timeout > wd->timeout_max)
> +		return -EINVAL;
> +
> +	pr_debug("setting timeout on %s to %ds\n",
> watchdog_name(wd), timeout);
> +
> +	return wd->set_timeout(wd, timeout);
> +}
> +
>  static int watchdog_set_cur(struct param_d *param, void *priv)
>  {
>  	struct watchdog *wd = priv;
> @@ -41,6 +51,37 @@ static int watchdog_set_cur(struct param_d *param,
> void *priv)
>  	return 0;
>  }
>  
> +static void watchdog_poller_cb(void *priv);
> +
> +static void watchdog_poller_start(struct watchdog *wd)
> +{
> +	_watchdog_set_timeout(wd, wd->timeout_cur);
> +	poller_call_async(&wd->poller, 500 * MSECOND,
> +			watchdog_poller_cb, wd);
> +
> +}
> +
> +static void watchdog_poller_cb(void *priv)
> +{
> +	struct watchdog *wd = priv;
> +
> +	if (wd->poller_enable)
> +		watchdog_poller_start(wd);
> +}
> +
> +static int watchdog_set_poller(struct param_d *param, void *priv)
> +{
> +	struct watchdog *wd = priv;
> +
> +
> +	if (wd->poller_enable)
> +		watchdog_poller_start(wd);
> +	else
> +		poller_async_cancel(&wd->poller);
> +
> +	return 0;
> +}
> +
>  int watchdog_register(struct watchdog *wd)
>  {
>  
> @@ -63,6 +104,10 @@ int watchdog_register(struct watchdog *wd)
>  	dev_add_param_uint32(&wd->dev, "timeout_cur",
> watchdog_set_cur, NULL,
>  			&wd->timeout_cur, "%u", wd);
>  
> +	poller_async_register(&wd->poller);
> +	dev_add_param_bool(&wd->dev, "poller_enable",
> watchdog_set_poller, NULL,
> +			&wd->poller_enable, wd);
Isn't the usage of the poller an implementation detail? Perhaps calls
this something like "auto_trigger"?

> +
>  	list_add_tail(&wd->list, &watchdog_list);
>  
>  	pr_debug("registering watchdog %s with priority %d\n",
> watchdog_name(wd),
> @@ -74,6 +119,8 @@ EXPORT_SYMBOL(watchdog_register);
>  
>  int watchdog_deregister(struct watchdog *wd)
>  {
> +	poller_async_cancel(&wd->poller);
> +	poller_async_unregister(&wd->poller);
>  	unregister_device(&wd->dev);
>  	list_del(&wd->list);
>  
> @@ -109,12 +156,7 @@ int watchdog_set_timeout(unsigned timeout)
>  	if (!wd)
>  		return -ENODEV;
>  
> -	if (timeout > wd->timeout_max)
> -		return -EINVAL;
> -
> -	pr_debug("setting timeout on %s to %ds\n",
> watchdog_name(wd), timeout);
> -
> -	return wd->set_timeout(wd, timeout);
> +	return _watchdog_set_timeout(wd, timeout);
>  }
>  EXPORT_SYMBOL(watchdog_set_timeout);
>  
> diff --git a/include/watchdog.h b/include/watchdog.h
> index 2f1874c19..0db4263a3 100644
> --- a/include/watchdog.h
> +++ b/include/watchdog.h
> @@ -13,6 +13,8 @@
>  #ifndef INCLUDE_WATCHDOG_H
>  # define INCLUDE_WATCHDOG_H
>  
> +#include <poller.h>
> +
>  struct watchdog {
>  	int (*set_timeout)(struct watchdog *, unsigned);
>  	const char *name;
> @@ -21,6 +23,8 @@ struct watchdog {
>  	unsigned int priority;
>  	unsigned int timeout_max;
>  	unsigned int timeout_cur;
> +	unsigned int poller_enable;
> +	struct poller_async poller;
>  	struct list_head list;
>  };
>  
-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From fishor at gmx.net  Thu Mar  8 06:16:19 2018
From: fishor at gmx.net (Oleksij Rempel)
Date: Thu, 8 Mar 2018 15:16:19 +0100
Subject: [PATCH v1 6/6] watchdog: add watchdog poller
In-Reply-To: <1520516969.31759.115.camel@pengutronix.de>
References: <20180308110515.29574-1-o.rempel@pengutronix.de>
 <20180308110515.29574-6-o.rempel@pengutronix.de>
 <1520516969.31759.115.camel@pengutronix.de>
Message-ID: <cd46083c-123e-8ec9-015b-cd121c87434b@gmx.net>

Hi,

thank you for review.

Am 08.03.2018 um 14:49 schrieb Jan L?bbe:
> Hi Oleksij,
> 
> On Thu, 2018-03-08 at 12:05 +0100, Oleksij Rempel wrote:
>> In some cases it is practical to supervise as match as possible of
> s/match/much/
>> barebox execution with watchdog (or multiple watchdogs). This
>  ^ the                  ^ a
>> patch provide async poller for watchdog core framework which can
>               ^-s an
>> be enabled by user and store this configuration to nv.
>                ^the           ^-s
> 
> Also, does this patch make the poller support required for using
> watchdogs? It unconditionally calls the poller_* functions.
> 
> Also, it should be documented explicitly, that this will cause barebox
> to keep triggering the watchdog, even when it drops to the shell after
> a boot error. This makes it unsuitable for unattended use.

I would prefer to use controlled reboot over uncontrolled watchdog reset.
For example it would be better to have boot and fail strategy. In case
of network boot, it would be better to retry download in some time and
not cause watchdog reset. If retry count exceeded then some thing should
be done. It can be power off, reboot, fall back to CLI.

The reason for controlled reboot is the fact that the reset impact (or
Reset Sensitivity) is different for every product and source of reset.

This example is take from MiniRISC EZ4021-FC documentation:
				Soft				TAP Ctrl
Module			Reset	Reset	PrRst	ERst	TRST	Reset
CPU			yes	yes	yes	no	no	no
CP0			yes	yes	yes	no	no	no
ICCi			yes	yes	yes	no	no	no
DCC			yes	yes	yes	no	no	no
BIU			yes	yes	yes	no	no	no
MMU			yes	no	no	no	no	no
MDU			yes	yes	yes	no	no	no
EJTAG iface:
- DMA/CPU Acc		yes	yes	yes	yes	yes	yes
  logic	
- Protocol engine	yes	no	no	yes	yes	yes
- Breakpoint		yes	no	no	yes	no	no
- PC trace yes no no yes no no


Most Atheros/QCA WiSoCs will not reset complete SoC even with watchdog
triggered reset.


> I'd prefer to make this optional at compile time.
> 
>>
>> Signed-off-by: Oleksij Rempel <o.rempel at pengutronix.de>
>> ---
>>  drivers/watchdog/wd_core.c | 54
>> ++++++++++++++++++++++++++++++++++++++++------
>>  include/watchdog.h         |  4 ++++
>>  2 files changed, 52 insertions(+), 6 deletions(-)
>>
>> diff --git a/drivers/watchdog/wd_core.c b/drivers/watchdog/wd_core.c
>> index 3162dd59c..6f1cadaf8 100644
>> --- a/drivers/watchdog/wd_core.c
>> +++ b/drivers/watchdog/wd_core.c
>> @@ -31,6 +31,16 @@ static const char *watchdog_name(struct watchdog
>> *wd)
>>  	return "unknown";
>>  }
>>  
>> +static int _watchdog_set_timeout(struct watchdog *wd, unsigned
>> timeout)
>> +{
>> +	if (timeout > wd->timeout_max)
>> +		return -EINVAL;
>> +
>> +	pr_debug("setting timeout on %s to %ds\n",
>> watchdog_name(wd), timeout);
>> +
>> +	return wd->set_timeout(wd, timeout);
>> +}
>> +
>>  static int watchdog_set_cur(struct param_d *param, void *priv)
>>  {
>>  	struct watchdog *wd = priv;
>> @@ -41,6 +51,37 @@ static int watchdog_set_cur(struct param_d *param,
>> void *priv)
>>  	return 0;
>>  }
>>  
>> +static void watchdog_poller_cb(void *priv);
>> +
>> +static void watchdog_poller_start(struct watchdog *wd)
>> +{
>> +	_watchdog_set_timeout(wd, wd->timeout_cur);
>> +	poller_call_async(&wd->poller, 500 * MSECOND,
>> +			watchdog_poller_cb, wd);
>> +
>> +}
>> +
>> +static void watchdog_poller_cb(void *priv)
>> +{
>> +	struct watchdog *wd = priv;
>> +
>> +	if (wd->poller_enable)
>> +		watchdog_poller_start(wd);
>> +}
>> +
>> +static int watchdog_set_poller(struct param_d *param, void *priv)
>> +{
>> +	struct watchdog *wd = priv;
>> +
>> +
>> +	if (wd->poller_enable)
>> +		watchdog_poller_start(wd);
>> +	else
>> +		poller_async_cancel(&wd->poller);
>> +
>> +	return 0;
>> +}
>> +
>>  int watchdog_register(struct watchdog *wd)
>>  {
>>  
>> @@ -63,6 +104,10 @@ int watchdog_register(struct watchdog *wd)
>>  	dev_add_param_uint32(&wd->dev, "timeout_cur",
>> watchdog_set_cur, NULL,
>>  			&wd->timeout_cur, "%u", wd);
>>  
>> +	poller_async_register(&wd->poller);
>> +	dev_add_param_bool(&wd->dev, "poller_enable",
>> watchdog_set_poller, NULL,
>> +			&wd->poller_enable, wd);
> Isn't the usage of the poller an implementation detail? Perhaps calls
> this something like "auto_trigger"?
> 
>> +
>>  	list_add_tail(&wd->list, &watchdog_list);
>>  
>>  	pr_debug("registering watchdog %s with priority %d\n",
>> watchdog_name(wd),
>> @@ -74,6 +119,8 @@ EXPORT_SYMBOL(watchdog_register);
>>  
>>  int watchdog_deregister(struct watchdog *wd)
>>  {
>> +	poller_async_cancel(&wd->poller);
>> +	poller_async_unregister(&wd->poller);
>>  	unregister_device(&wd->dev);
>>  	list_del(&wd->list);
>>  
>> @@ -109,12 +156,7 @@ int watchdog_set_timeout(unsigned timeout)
>>  	if (!wd)
>>  		return -ENODEV;
>>  
>> -	if (timeout > wd->timeout_max)
>> -		return -EINVAL;
>> -
>> -	pr_debug("setting timeout on %s to %ds\n",
>> watchdog_name(wd), timeout);
>> -
>> -	return wd->set_timeout(wd, timeout);
>> +	return _watchdog_set_timeout(wd, timeout);
>>  }
>>  EXPORT_SYMBOL(watchdog_set_timeout);
>>  
>> diff --git a/include/watchdog.h b/include/watchdog.h
>> index 2f1874c19..0db4263a3 100644
>> --- a/include/watchdog.h
>> +++ b/include/watchdog.h
>> @@ -13,6 +13,8 @@
>>  #ifndef INCLUDE_WATCHDOG_H
>>  # define INCLUDE_WATCHDOG_H
>>  
>> +#include <poller.h>
>> +
>>  struct watchdog {
>>  	int (*set_timeout)(struct watchdog *, unsigned);
>>  	const char *name;
>> @@ -21,6 +23,8 @@ struct watchdog {
>>  	unsigned int priority;
>>  	unsigned int timeout_max;
>>  	unsigned int timeout_cur;
>> +	unsigned int poller_enable;
>> +	struct poller_async poller;
>>  	struct list_head list;
>>  };
>>  


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From jlu at pengutronix.de  Thu Mar  8 07:33:39 2018
From: jlu at pengutronix.de (Jan =?ISO-8859-1?Q?L=FCbbe?=)
Date: Thu, 08 Mar 2018 16:33:39 +0100
Subject: [PATCH v1 6/6] watchdog: add watchdog poller
In-Reply-To: <cd46083c-123e-8ec9-015b-cd121c87434b@gmx.net>
References: <20180308110515.29574-1-o.rempel@pengutronix.de>
 <20180308110515.29574-6-o.rempel@pengutronix.de>
 <1520516969.31759.115.camel@pengutronix.de>
 <cd46083c-123e-8ec9-015b-cd121c87434b@gmx.net>
Message-ID: <1520523219.31759.140.camel@pengutronix.de>

Hi Oleksij,

On Thu, 2018-03-08 at 15:16 +0100, Oleksij Rempel wrote:
> > Also, it should be documented explicitly, that this will cause barebox
> > to keep triggering the watchdog, even when it drops to the shell after
> > a boot error. This makes it unsuitable for unattended use.
> 
> I would prefer to use controlled reboot over uncontrolled watchdog reset.
> For example it would be better to have boot and fail strategy. In case
> of network boot, it would be better to retry download in some time and
> not cause watchdog reset. If retry count exceeded then some thing should
> be done. It can be power off, reboot, fall back to CLI.

In my experience, the watchdog is used as a last resort to handle any
*unanticipated* problems. So, by definition, there isn't any code to
handle these problems. The way to do this is that the watchdog is only
triggered when the boot process has made actual progress towards a
running system. For example:
- once barebox probes the watchdog driver
- from the shell init scripts
- after loading the kernel, just before jumping to the kernel

This way, there is no possible way which could cause barebox to just
wait on the prompt: an idle or hung system will always be restarted via
the watchdog.

> The reason for controlled reboot is the fact that the reset impact (or
> Reset Sensitivity) is different for every product and source of reset.
> 
> This example is take from MiniRISC EZ4021-FC documentation:
> 				Soft				TAP Ctrl
> Module		Reset	Reset	PrRst	ERst	TRST	Reset
> CPU			yes	yes	yes	no	no	no
> CP0			yes	yes	yes	no	no	no
> ICCi			yes	yes	yes	no	no	no
> DCC			yes	yes	yes	no	no	no
> BIU			yes	yes	yes	no	no	no
> MMU			yes	no	no	no	no	no
> MDU			yes	yes	yes	no	no	no
> EJTAG iface:
> - DMA/CPU Acc		yes	yes	yes	yes	yes	yes
>   logic	
> - Protocol engine	yes	no	no	yes	yes	yes
> - Breakpoint		yes	no	no	yes	no	no
> - PC trace yes no no yes no no

It is not clear to me from this table which reset is triggered by the
hardware watchdog. I would expect that it is the first column, which
resets everything.

> Most Atheros/QCA WiSoCs will not reset complete SoC even with watchdog
> triggered reset.

If you can't be sure that the watchdog resets enough to recover from
any transient problem, you cannot rely on it at all (and should
possibly use an external watchdog).

Regards,
Jan
-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From s.hauer at pengutronix.de  Mon Mar 12 03:29:55 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Mon, 12 Mar 2018 11:29:55 +0100
Subject: [PATCH] video: tc358767: register aux i2c bus after validating
 link
In-Reply-To: <1520259593-21311-1-git-send-email-andrey.gusakov@cogentembedded.com>
References: <1520259593-21311-1-git-send-email-andrey.gusakov@cogentembedded.com>
Message-ID: <20180312102955.a55fq5ymrqcg452g@pengutronix.de>

On Mon, Mar 05, 2018 at 05:19:53PM +0300, Andrey Gusakov wrote:
> Register AUX i2c adapter only if AUX link is functional. This
> should avoid possible hung during tc358767 probe when no display
> connected.
> 
> Signed-off-by: Andrey Gusakov <andrey.gusakov at cogentembedded.com>
> ---
>  drivers/video/tc358767.c | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)

Applied, thanks

Sascha

> 
> diff --git a/drivers/video/tc358767.c b/drivers/video/tc358767.c
> index f9ca06c..5ad5cb4 100644
> --- a/drivers/video/tc358767.c
> +++ b/drivers/video/tc358767.c
> @@ -1404,6 +1404,10 @@ static int tc_probe(struct device_d *dev)
>  	if (ret)
>  		goto err;
>  
> +	ret = tc_get_display_props(tc);
> +	if (ret)
> +		goto err;
> +
>  	/* Register DP AUX channel */
>  	tc->adapter.master_xfer = tc_aux_i2c_xfer;
>  	tc->adapter.nr = -1; /* any free */
> @@ -1416,10 +1420,6 @@ static int tc_probe(struct device_d *dev)
>  		goto err;
>  	}
>  
> -	ret = tc_get_display_props(tc);
> -	if (ret)
> -		goto err;
> -
>  	/* add vlp */
>  	tc->vpl.node = dev->device_node;
>  	tc->vpl.ioctl = tc_ioctl;
> -- 
> 1.9.1
> 
> 

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From s.hauer at pengutronix.de  Mon Mar 12 03:35:26 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Mon, 12 Mar 2018 11:35:26 +0100
Subject: [PATCH v1 3/6] watchdog: register watchdog virtual device with
 short name wdog
In-Reply-To: <20180308110515.29574-3-o.rempel@pengutronix.de>
References: <20180308110515.29574-1-o.rempel@pengutronix.de>
 <20180308110515.29574-3-o.rempel@pengutronix.de>
Message-ID: <20180312103526.yoieryp6wlgxy6te@pengutronix.de>

Hi Oleksij,

On Thu, Mar 08, 2018 at 12:05:12PM +0100, Oleksij Rempel wrote:
> the watchdog hwdev is usually named with devicetree schema
> which is not practical for CLI.
> 
> On device registration "wdog" will be extended with some index number
> extracted from devicetree (if awailable) or automatically assigned
> first available number. End result will be "wdog0" .. etc.
> 
> Signed-off-by: Oleksij Rempel <o.rempel at pengutronix.de>
> ---
>  drivers/watchdog/wd_core.c | 6 ++++++
>  include/watchdog.h         | 1 +
>  2 files changed, 7 insertions(+)
> 
> diff --git a/drivers/watchdog/wd_core.c b/drivers/watchdog/wd_core.c
> index 1d0f0de7d..97e2ab568 100644
> --- a/drivers/watchdog/wd_core.c
> +++ b/drivers/watchdog/wd_core.c
> @@ -33,6 +33,11 @@ static const char *watchdog_name(struct watchdog *wd)
>  
>  int watchdog_register(struct watchdog *wd)
>  {
> +

Please drop that blank line.

> +	strcpy(wd->dev.name, "wdog");

I would prefer a of_alias_get() as first try and "wdog" only as
fallback.

For the hardcoded string wd->dev.id needs to be initialized with
DEVICE_ID_DYNAMIC, otherwise only a single watchdog can be successfully
registered.

> +	wd->dev.parent = wd->hwdev;
> +	register_device(&wd->dev);

Check return value.

Sascha


-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From s.hauer at pengutronix.de  Mon Mar 12 03:37:01 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Mon, 12 Mar 2018 11:37:01 +0100
Subject: [PATCH v1 4/6] watchdog: set some reasonable timeout_max value
 if no other is available
In-Reply-To: <20180308110515.29574-4-o.rempel@pengutronix.de>
References: <20180308110515.29574-1-o.rempel@pengutronix.de>
 <20180308110515.29574-4-o.rempel@pengutronix.de>
Message-ID: <20180312103701.mth5rujvayf323lw@pengutronix.de>

On Thu, Mar 08, 2018 at 12:05:13PM +0100, Oleksij Rempel wrote:
> Some drivers do not provide timeout_max value.
> Using some value is probbaly better then setting timeout_max to 0.
> 
> Signed-off-by: Oleksij Rempel <o.rempel at pengutronix.de>
> ---
>  drivers/watchdog/wd_core.c | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/drivers/watchdog/wd_core.c b/drivers/watchdog/wd_core.c
> index 97e2ab568..66dbd790d 100644
> --- a/drivers/watchdog/wd_core.c
> +++ b/drivers/watchdog/wd_core.c
> @@ -41,6 +41,10 @@ int watchdog_register(struct watchdog *wd)
>  	if (!wd->priority)
>  		wd->priority = WATCHDOG_DEFAULT_PRIORITY;
>  
> +	/* set some default sane value */
> +	if (!wd->timeout_max)
> +		wd->timeout_max = 60 * 4;

4 minutes? Why so low? I would expect something like a few hours.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From o.rempel at pengutronix.de  Tue Mar 13 01:33:27 2018
From: o.rempel at pengutronix.de (Oleksij Rempel)
Date: Tue, 13 Mar 2018 09:33:27 +0100
Subject: [PATCH v2 5/6] watchdog: provide timeout_cur value
In-Reply-To: <20180313083328.25705-1-o.rempel@pengutronix.de>
References: <20180313083328.25705-1-o.rempel@pengutronix.de>
Message-ID: <20180313083328.25705-5-o.rempel@pengutronix.de>

timeout_cur will be used for watchdog poller.
Provided values should be good enough for most users
and still can be changed for separate projects and
fit to needed requirements.

Signed-off-by: Oleksij Rempel <o.rempel at pengutronix.de>
---
 drivers/watchdog/wd_core.c | 18 ++++++++++++++++++
 include/watchdog.h         |  1 +
 2 files changed, 19 insertions(+)

diff --git a/drivers/watchdog/wd_core.c b/drivers/watchdog/wd_core.c
index 31a88a377..69663b39c 100644
--- a/drivers/watchdog/wd_core.c
+++ b/drivers/watchdog/wd_core.c
@@ -31,6 +31,16 @@ static const char *watchdog_name(struct watchdog *wd)
 	return "unknown";
 }
 
+static int watchdog_set_cur(struct param_d *param, void *priv)
+{
+	struct watchdog *wd = priv;
+
+	if (wd->timeout_cur > wd->timeout_max)
+		return -EINVAL;
+
+	return 0;
+}
+
 static int watchdog_register_dev(struct watchdog *wd, const char *name, int id)
 {
 	wd->dev.parent = wd->hwdev;
@@ -63,11 +73,19 @@ int watchdog_register(struct watchdog *wd)
 	if (!wd->timeout_max)
 		wd->timeout_max = 60 * 60 * 24;
 
+	if (!wd->timeout_cur || wd->timeout_cur > wd->timeout_max)
+		wd->timeout_cur = wd->timeout_max;
+
 	p = dev_add_param_uint32_ro(&wd->dev, "timeout_max",
 			&wd->timeout_max, "%u");
 	if (IS_ERR(p))
 		return PTR_ERR(p);
 
+	p = dev_add_param_uint32(&wd->dev, "timeout_cur", watchdog_set_cur, NULL,
+			&wd->timeout_cur, "%u", wd);
+	if (IS_ERR(p))
+		return PTR_ERR(p);
+
 	list_add_tail(&wd->list, &watchdog_list);
 
 	pr_debug("registering watchdog %s with priority %d\n", watchdog_name(wd),
diff --git a/include/watchdog.h b/include/watchdog.h
index a2459d255..2f1874c19 100644
--- a/include/watchdog.h
+++ b/include/watchdog.h
@@ -20,6 +20,7 @@ struct watchdog {
 	struct device_d dev;
 	unsigned int priority;
 	unsigned int timeout_max;
+	unsigned int timeout_cur;
 	struct list_head list;
 };
 
-- 
2.16.1



From o.rempel at pengutronix.de  Tue Mar 13 01:33:25 2018
From: o.rempel at pengutronix.de (Oleksij Rempel)
Date: Tue, 13 Mar 2018 09:33:25 +0100
Subject: [PATCH v2 3/6] watchdog: register watchdog virtual device with short
 name wdog
In-Reply-To: <20180313083328.25705-1-o.rempel@pengutronix.de>
References: <20180313083328.25705-1-o.rempel@pengutronix.de>
Message-ID: <20180313083328.25705-3-o.rempel@pengutronix.de>

the watchdog hwdev is usually named with devicetree schema
which is not practical for CLI.

On device registration "wdog" will be extended with some index number
extracted from devicetree (if awailable) or automatically assigned
first available number. End result will be "wdog0" .. etc.

Signed-off-by: Oleksij Rempel <o.rempel at pengutronix.de>
---
 drivers/watchdog/wd_core.c | 24 ++++++++++++++++++++++++
 include/watchdog.h         |  1 +
 2 files changed, 25 insertions(+)

diff --git a/drivers/watchdog/wd_core.c b/drivers/watchdog/wd_core.c
index 1d0f0de7d..0dc7aecf3 100644
--- a/drivers/watchdog/wd_core.c
+++ b/drivers/watchdog/wd_core.c
@@ -31,8 +31,31 @@ static const char *watchdog_name(struct watchdog *wd)
 	return "unknown";
 }
 
+static int watchdog_register_dev(struct watchdog *wd, const char *name, int id)
+{
+	wd->dev.parent = wd->hwdev;
+	wd->dev.id = id;
+	strncpy(wd->dev.name, name, MAX_DRIVER_NAME);
+
+	return register_device(&wd->dev);
+}
+
 int watchdog_register(struct watchdog *wd)
 {
+	struct param_d *p;
+	const char *alias;
+	int ret;
+
+	alias = of_alias_get(wd->hwdev->device_node);
+	if (alias)
+		ret = watchdog_register_dev(wd, alias, DEVICE_ID_SINGLE);
+
+	if (!alias || ret)
+		ret = watchdog_register_dev(wd, "wdog", DEVICE_ID_DYNAMIC);
+
+	if (ret)
+		return ret;
+
 	if (!wd->priority)
 		wd->priority = WATCHDOG_DEFAULT_PRIORITY;
 
@@ -50,6 +73,7 @@ EXPORT_SYMBOL(watchdog_register);
 
 int watchdog_deregister(struct watchdog *wd)
 {
+	unregister_device(&wd->dev);
 	list_del(&wd->list);
 
 	return 0;
diff --git a/include/watchdog.h b/include/watchdog.h
index 1e06fbc3f..a2459d255 100644
--- a/include/watchdog.h
+++ b/include/watchdog.h
@@ -17,6 +17,7 @@ struct watchdog {
 	int (*set_timeout)(struct watchdog *, unsigned);
 	const char *name;
 	struct device_d *hwdev;
+	struct device_d dev;
 	unsigned int priority;
 	unsigned int timeout_max;
 	struct list_head list;
-- 
2.16.1



From o.rempel at pengutronix.de  Tue Mar 13 01:33:26 2018
From: o.rempel at pengutronix.de (Oleksij Rempel)
Date: Tue, 13 Mar 2018 09:33:26 +0100
Subject: [PATCH v2 4/6] watchdog: set some reasonable timeout_max value if no
 other is available
In-Reply-To: <20180313083328.25705-1-o.rempel@pengutronix.de>
References: <20180313083328.25705-1-o.rempel@pengutronix.de>
Message-ID: <20180313083328.25705-4-o.rempel@pengutronix.de>

Some drivers do not provide timeout_max value.
Using some value is probably better then setting timeout_max to 0.

Signed-off-by: Oleksij Rempel <o.rempel at pengutronix.de>
---
 drivers/watchdog/wd_core.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/watchdog/wd_core.c b/drivers/watchdog/wd_core.c
index 0dc7aecf3..31a88a377 100644
--- a/drivers/watchdog/wd_core.c
+++ b/drivers/watchdog/wd_core.c
@@ -59,8 +59,14 @@ int watchdog_register(struct watchdog *wd)
 	if (!wd->priority)
 		wd->priority = WATCHDOG_DEFAULT_PRIORITY;
 
-	dev_add_param_uint32_ro(&wd->dev, "timeout_max",
+	/* set some default sane value */
+	if (!wd->timeout_max)
+		wd->timeout_max = 60 * 60 * 24;
+
+	p = dev_add_param_uint32_ro(&wd->dev, "timeout_max",
 			&wd->timeout_max, "%u");
+	if (IS_ERR(p))
+		return PTR_ERR(p);
 
 	list_add_tail(&wd->list, &watchdog_list);
 
-- 
2.16.1



From o.rempel at pengutronix.de  Tue Mar 13 01:33:28 2018
From: o.rempel at pengutronix.de (Oleksij Rempel)
Date: Tue, 13 Mar 2018 09:33:28 +0100
Subject: [PATCH v2 6/6] watchdog: add watchdog poller
In-Reply-To: <20180313083328.25705-1-o.rempel@pengutronix.de>
References: <20180313083328.25705-1-o.rempel@pengutronix.de>
Message-ID: <20180313083328.25705-6-o.rempel@pengutronix.de>

In some cases it is practical to supervise as much as possible of
the barebox execution with a watchdog (or multiple watchdogs). This
patch provides an async poller for watchdog core framework which can
be enabled by the user and stores this configuration to nv.

Signed-off-by: Oleksij Rempel <o.rempel at pengutronix.de>
---
 drivers/watchdog/Kconfig   |  6 ++++
 drivers/watchdog/wd_core.c | 74 ++++++++++++++++++++++++++++++++++++++++++----
 include/watchdog.h         |  4 +++
 3 files changed, 78 insertions(+), 6 deletions(-)

diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index 3defb9da6..375eb248b 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -10,6 +10,12 @@ menuconfig WATCHDOG
 
 if WATCHDOG
 
+menuconfig WATCHDOG_POLLER
+	bool "Watchdog poller support"
+	select POLLER
+	help
+	  Provides periodic ping support for watchdog framework.
+
 config WATCHDOG_AR9344
 	bool "QCA AR9344"
 	depends on SOC_QCA_AR9344 || SOC_QCA_AR9331
diff --git a/drivers/watchdog/wd_core.c b/drivers/watchdog/wd_core.c
index 69663b39c..77827eb50 100644
--- a/drivers/watchdog/wd_core.c
+++ b/drivers/watchdog/wd_core.c
@@ -31,6 +31,16 @@ static const char *watchdog_name(struct watchdog *wd)
 	return "unknown";
 }
 
+static int _watchdog_set_timeout(struct watchdog *wd, unsigned timeout)
+{
+	if (timeout > wd->timeout_max)
+		return -EINVAL;
+
+	pr_debug("setting timeout on %s to %ds\n", watchdog_name(wd), timeout);
+
+	return wd->set_timeout(wd, timeout);
+}
+
 static int watchdog_set_cur(struct param_d *param, void *priv)
 {
 	struct watchdog *wd = priv;
@@ -41,6 +51,55 @@ static int watchdog_set_cur(struct param_d *param, void *priv)
 	return 0;
 }
 
+static void watchdog_poller_cb(void *priv);
+
+static void watchdog_poller_start(struct watchdog *wd)
+{
+	_watchdog_set_timeout(wd, wd->timeout_cur);
+	poller_call_async(&wd->poller, 500 * MSECOND,
+			watchdog_poller_cb, wd);
+
+}
+
+static void watchdog_poller_cb(void *priv)
+{
+	struct watchdog *wd = priv;
+
+	if (wd->poller_enable)
+		watchdog_poller_start(wd);
+}
+
+static int watchdog_set_poller(struct param_d *param, void *priv)
+{
+	struct watchdog *wd = priv;
+
+
+	if (wd->poller_enable) {
+		dev_info(&wd->dev, "enable watchdog poller\n");
+		watchdog_poller_start(wd);
+	} else {
+		dev_info(&wd->dev, "disable watchdog poller\n");
+		poller_async_cancel(&wd->poller);
+	}
+
+	return 0;
+}
+
+static int watchdog_register_poller(struct watchdog *wd)
+{
+	struct param_d *p;
+	int ret;
+
+	ret = poller_async_register(&wd->poller);
+	if (ret)
+		return ret;
+
+	p = dev_add_param_bool(&wd->dev, "poller_enable", watchdog_set_poller,
+			NULL, &wd->poller_enable, wd);
+
+	return PTR_ERR_OR_ZERO(p);
+}
+
 static int watchdog_register_dev(struct watchdog *wd, const char *name, int id)
 {
 	wd->dev.parent = wd->hwdev;
@@ -86,6 +145,12 @@ int watchdog_register(struct watchdog *wd)
 	if (IS_ERR(p))
 		return PTR_ERR(p);
 
+	if (IS_ENABLED(CONFIG_WATCHDOG_POLLER)) {
+		ret = watchdog_register_poller(wd);
+		if (ret)
+			return ret;
+	}
+
 	list_add_tail(&wd->list, &watchdog_list);
 
 	pr_debug("registering watchdog %s with priority %d\n", watchdog_name(wd),
@@ -97,6 +162,8 @@ EXPORT_SYMBOL(watchdog_register);
 
 int watchdog_deregister(struct watchdog *wd)
 {
+	poller_async_cancel(&wd->poller);
+	poller_async_unregister(&wd->poller);
 	unregister_device(&wd->dev);
 	list_del(&wd->list);
 
@@ -132,12 +199,7 @@ int watchdog_set_timeout(unsigned timeout)
 	if (!wd)
 		return -ENODEV;
 
-	if (timeout > wd->timeout_max)
-		return -EINVAL;
-
-	pr_debug("setting timeout on %s to %ds\n", watchdog_name(wd), timeout);
-
-	return wd->set_timeout(wd, timeout);
+	return _watchdog_set_timeout(wd, timeout);
 }
 EXPORT_SYMBOL(watchdog_set_timeout);
 
diff --git a/include/watchdog.h b/include/watchdog.h
index 2f1874c19..0db4263a3 100644
--- a/include/watchdog.h
+++ b/include/watchdog.h
@@ -13,6 +13,8 @@
 #ifndef INCLUDE_WATCHDOG_H
 # define INCLUDE_WATCHDOG_H
 
+#include <poller.h>
+
 struct watchdog {
 	int (*set_timeout)(struct watchdog *, unsigned);
 	const char *name;
@@ -21,6 +23,8 @@ struct watchdog {
 	unsigned int priority;
 	unsigned int timeout_max;
 	unsigned int timeout_cur;
+	unsigned int poller_enable;
+	struct poller_async poller;
 	struct list_head list;
 };
 
-- 
2.16.1



From o.rempel at pengutronix.de  Tue Mar 13 01:33:23 2018
From: o.rempel at pengutronix.de (Oleksij Rempel)
Date: Tue, 13 Mar 2018 09:33:23 +0100
Subject: [PATCH v2 1/6] watchdog: rename dev to hwdev
Message-ID: <20180313083328.25705-1-o.rempel@pengutronix.de>

From: Sascha Hauer <s.hauer at pengutronix.de>

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 drivers/watchdog/ar9344_wdt.c  | 2 +-
 drivers/watchdog/davinci_wdt.c | 2 +-
 drivers/watchdog/dw_wdt.c      | 4 ++--
 drivers/watchdog/im28wd.c      | 2 +-
 drivers/watchdog/imxwd.c       | 2 +-
 drivers/watchdog/orion_wdt.c   | 2 +-
 drivers/watchdog/wd_core.c     | 4 ++--
 include/watchdog.h             | 2 +-
 8 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/drivers/watchdog/ar9344_wdt.c b/drivers/watchdog/ar9344_wdt.c
index d570cb40f..c1dfc994a 100644
--- a/drivers/watchdog/ar9344_wdt.c
+++ b/drivers/watchdog/ar9344_wdt.c
@@ -95,7 +95,7 @@ static int ar9344_wdt_probe(struct device_d *dev)
 
 	priv->base = IOMEM(iores->start);
 	priv->wd.set_timeout = ar9344_watchdog_set_timeout;
-	priv->wd.dev = dev;
+	priv->wd.hwdev = dev;
 	priv->dev = dev;
 
 	dev->priv = priv;
diff --git a/drivers/watchdog/davinci_wdt.c b/drivers/watchdog/davinci_wdt.c
index 03dc83408..2ac5f8b38 100644
--- a/drivers/watchdog/davinci_wdt.c
+++ b/drivers/watchdog/davinci_wdt.c
@@ -149,7 +149,7 @@ static int davinci_wdt_probe(struct device_d *dev)
 	clk_enable(davinci_wdt->clk);
 
 	davinci_wdt->wd.set_timeout = davinci_wdt_set_timeout;
-	davinci_wdt->wd.dev = dev;
+	davinci_wdt->wd.hwdev = dev;
 
 	ret = watchdog_register(&davinci_wdt->wd);
 	if (ret < 0)
diff --git a/drivers/watchdog/dw_wdt.c b/drivers/watchdog/dw_wdt.c
index 8fd8c81e6..85e810f24 100644
--- a/drivers/watchdog/dw_wdt.c
+++ b/drivers/watchdog/dw_wdt.c
@@ -73,7 +73,7 @@ static int dw_wdt_stop(struct watchdog *wdd)
 	struct dw_wdt *dw_wdt = to_dw_wdt(wdd);
 
 	if (IS_ERR(dw_wdt->rst)) {
-		dev_warn(dw_wdt->wdd.dev, "No reset line. Will not stop.\n");
+		dev_warn(dw_wdt->wdd.hwdev, "No reset line. Will not stop.\n");
 		return PTR_ERR(dw_wdt->rst);
 	}
 
@@ -157,7 +157,7 @@ static int dw_wdt_drv_probe(struct device_d *dev)
 
 	wdd = &dw_wdt->wdd;
 	wdd->name = "dw_wdt";
-	wdd->dev = dev;
+	wdd->hwdev = dev;
 	wdd->set_timeout = dw_wdt_set_timeout;
 
 	ret = watchdog_register(wdd);
diff --git a/drivers/watchdog/im28wd.c b/drivers/watchdog/im28wd.c
index 1956fdb73..43edea8d0 100644
--- a/drivers/watchdog/im28wd.c
+++ b/drivers/watchdog/im28wd.c
@@ -199,7 +199,7 @@ static int imx28_wd_probe(struct device_d *dev)
 		return PTR_ERR(iores);
 	priv->regs = IOMEM(iores->start);
 	priv->wd.set_timeout = imx28_watchdog_set_timeout;
-	priv->wd.dev = dev;
+	priv->wd.hwdev = dev;
 
 	if (!(readl(priv->regs + MXS_RTC_STAT) & MXS_RTC_STAT_WD_PRESENT)) {
 		rc = -ENODEV;
diff --git a/drivers/watchdog/imxwd.c b/drivers/watchdog/imxwd.c
index bd5e518bc..6b33834fe 100644
--- a/drivers/watchdog/imxwd.c
+++ b/drivers/watchdog/imxwd.c
@@ -218,7 +218,7 @@ static int imx_wd_probe(struct device_d *dev)
 	priv->base = IOMEM(iores->start);
 	priv->ops = ops;
 	priv->wd.set_timeout = imx_watchdog_set_timeout;
-	priv->wd.dev = dev;
+	priv->wd.hwdev = dev;
 	priv->dev = dev;
 
 	priv->ext_reset = of_property_read_bool(dev->device_node,
diff --git a/drivers/watchdog/orion_wdt.c b/drivers/watchdog/orion_wdt.c
index 2802033f7..4fe1ac1fd 100644
--- a/drivers/watchdog/orion_wdt.c
+++ b/drivers/watchdog/orion_wdt.c
@@ -88,7 +88,7 @@ static int orion_wdt_probe(struct device_d *dev)
 
 	ddata->wd.set_timeout = armada_xp_set_timeout;
 	ddata->wd.name = "orion_wdt";
-	ddata->wd.dev = dev;
+	ddata->wd.hwdev = dev;
 
 	res_timer = dev_request_mem_resource(dev, 0);
 	if (IS_ERR(res_timer)) {
diff --git a/drivers/watchdog/wd_core.c b/drivers/watchdog/wd_core.c
index 3a3f51964..56436e6f8 100644
--- a/drivers/watchdog/wd_core.c
+++ b/drivers/watchdog/wd_core.c
@@ -23,8 +23,8 @@ static LIST_HEAD(watchdog_list);
 
 static const char *watchdog_name(struct watchdog *wd)
 {
-	if (wd->dev)
-		return dev_name(wd->dev);
+	if (wd->hwdev)
+		return dev_name(wd->hwdev);
 	if (wd->name)
 		return wd->name;
 
diff --git a/include/watchdog.h b/include/watchdog.h
index 3e8a487a4..848981cc0 100644
--- a/include/watchdog.h
+++ b/include/watchdog.h
@@ -16,7 +16,7 @@
 struct watchdog {
 	int (*set_timeout)(struct watchdog *, unsigned);
 	const char *name;
-	struct device_d *dev;
+	struct device_d *hwdev;
 	unsigned int priority;
 	struct list_head list;
 };
-- 
2.16.1



From o.rempel at pengutronix.de  Tue Mar 13 01:33:24 2018
From: o.rempel at pengutronix.de (Oleksij Rempel)
Date: Tue, 13 Mar 2018 09:33:24 +0100
Subject: [PATCH v2 2/6] watchdog: move max timeout test in to wd_core
In-Reply-To: <20180313083328.25705-1-o.rempel@pengutronix.de>
References: <20180313083328.25705-1-o.rempel@pengutronix.de>
Message-ID: <20180313083328.25705-2-o.rempel@pengutronix.de>

From: Oleksij Rempel <linux at rempel-privat.de>

this also will be needed for watchdog poller as well

Signed-off-by: Oleksij Rempel <linux at rempel-privat.de>
---
 drivers/watchdog/ar9344_wdt.c | 15 ++++-----------
 drivers/watchdog/im28wd.c     |  4 +---
 drivers/watchdog/imxwd.c      | 10 ++++------
 drivers/watchdog/orion_wdt.c  |  4 +---
 drivers/watchdog/wd_core.c    |  6 ++++++
 include/watchdog.h            |  1 +
 6 files changed, 17 insertions(+), 23 deletions(-)

diff --git a/drivers/watchdog/ar9344_wdt.c b/drivers/watchdog/ar9344_wdt.c
index c1dfc994a..461528863 100644
--- a/drivers/watchdog/ar9344_wdt.c
+++ b/drivers/watchdog/ar9344_wdt.c
@@ -41,20 +41,11 @@ struct ar9344_wd {
 static int ar9344_watchdog_set_timeout(struct watchdog *wd, unsigned timeout)
 {
 	struct ar9344_wd *priv = to_ar9344_wd(wd);
-	u32 val, ctrl, rate, max_timout;
-
-	rate = clk_get_rate(priv->clk);
-	max_timout = U32_MAX / rate;
-
-	if (timeout > max_timout) {
-		dev_err(priv->dev, "timeout value out of range: %d > %d\n",
-			timeout, max_timout);
-		return -EINVAL;
-	}
+	u32 val, ctrl;
 
 	if (timeout) {
 		ctrl = AR9344_WD_CTRL_ACTION_FCR;
-		val = timeout * rate;
+		val = timeout * clk_get_rate(priv->clk);
 	} else {
 		ctrl = AR9344_WD_CTRL_ACTION_NONE;
 		val = U32_MAX;
@@ -111,6 +102,8 @@ static int ar9344_wdt_probe(struct device_d *dev)
 
 	clk_enable(priv->clk);
 
+	priv->wd.timeout_max = U32_MAX / clk_get_rate(priv->clk);
+
 	ret = watchdog_register(&priv->wd);
 	if (ret)
 		goto on_error;
diff --git a/drivers/watchdog/im28wd.c b/drivers/watchdog/im28wd.c
index 43edea8d0..2b233ede2 100644
--- a/drivers/watchdog/im28wd.c
+++ b/drivers/watchdog/im28wd.c
@@ -133,9 +133,6 @@ static int imx28_watchdog_set_timeout(struct watchdog *wd, unsigned timeout)
 	struct imx28_wd *pwd = (struct imx28_wd *)to_imx28_wd(wd);
 	void __iomem *base;
 
-	if (timeout > (ULONG_MAX / WDOG_TICK_RATE))
-		return -EINVAL;
-
 	if (timeout) {
 		writel(timeout * WDOG_TICK_RATE, pwd->regs + MXS_RTC_WATCHDOG);
 		base = pwd->regs + MXS_RTC_SET_ADDR;
@@ -199,6 +196,7 @@ static int imx28_wd_probe(struct device_d *dev)
 		return PTR_ERR(iores);
 	priv->regs = IOMEM(iores->start);
 	priv->wd.set_timeout = imx28_watchdog_set_timeout;
+	priv->wd.timeout_max = ULONG_MAX / WDOG_TICK_RATE;
 	priv->wd.hwdev = dev;
 
 	if (!(readl(priv->regs + MXS_RTC_STAT) & MXS_RTC_STAT_WD_PRESENT)) {
diff --git a/drivers/watchdog/imxwd.c b/drivers/watchdog/imxwd.c
index 6b33834fe..a66fae400 100644
--- a/drivers/watchdog/imxwd.c
+++ b/drivers/watchdog/imxwd.c
@@ -28,6 +28,7 @@ struct imx_wd_ops {
 	int (*set_timeout)(struct imx_wd *, unsigned);
 	void (*soc_reset)(struct imx_wd *);
 	int (*init)(struct imx_wd *);
+	unsigned int timeout_max;
 };
 
 struct imx_wd {
@@ -71,9 +72,6 @@ static int imx1_watchdog_set_timeout(struct imx_wd *priv, unsigned timeout)
 
 	dev_dbg(priv->dev, "%s: %d\n", __func__, timeout);
 
-	if (timeout > 64)
-		return -EINVAL;
-
 	if (!timeout) {
 		writew(IMX1_WDOG_WCR_WHALT, priv->base + IMX1_WDOG_WCR);
 		return 0;
@@ -102,9 +100,6 @@ static int imx21_watchdog_set_timeout(struct imx_wd *priv, unsigned timeout)
 
 	dev_dbg(priv->dev, "%s: %d\n", __func__, timeout);
 
-	if (timeout > 128)
-		return -EINVAL;
-
 	if (timeout == 0) /* bit 2 (WDE) cannot be set to 0 again */
 		return -ENOSYS;
 
@@ -218,6 +213,7 @@ static int imx_wd_probe(struct device_d *dev)
 	priv->base = IOMEM(iores->start);
 	priv->ops = ops;
 	priv->wd.set_timeout = imx_watchdog_set_timeout;
+	priv->wd.timeout_max = priv->ops->timeout_max;
 	priv->wd.hwdev = dev;
 	priv->dev = dev;
 
@@ -259,11 +255,13 @@ static const struct imx_wd_ops imx21_wd_ops = {
 	.set_timeout = imx21_watchdog_set_timeout,
 	.soc_reset = imx21_soc_reset,
 	.init = imx21_wd_init,
+	.timeout_max = 128,
 };
 
 static const struct imx_wd_ops imx1_wd_ops = {
 	.set_timeout = imx1_watchdog_set_timeout,
 	.soc_reset = imx1_soc_reset,
+	.timeout_max = 64,
 };
 
 static __maybe_unused struct of_device_id imx_wdt_dt_ids[] = {
diff --git a/drivers/watchdog/orion_wdt.c b/drivers/watchdog/orion_wdt.c
index 4fe1ac1fd..dd1fa3a04 100644
--- a/drivers/watchdog/orion_wdt.c
+++ b/drivers/watchdog/orion_wdt.c
@@ -49,9 +49,6 @@ static int armada_xp_set_timeout(struct watchdog *wd, unsigned timeout)
 		container_of(wd, struct orion_wdt_ddata, wd);
 	u32 ctrl;
 
-	if (0xffffffff / CLKRATE < timeout)
-		return -EINVAL;
-
 	ctrl = readl(ddata->timer_base + TIMER_CTRL);
 
 	if (timeout == 0) {
@@ -89,6 +86,7 @@ static int orion_wdt_probe(struct device_d *dev)
 	ddata->wd.set_timeout = armada_xp_set_timeout;
 	ddata->wd.name = "orion_wdt";
 	ddata->wd.hwdev = dev;
+	ddata->wd.timeout_max = U32_MAX / CLKRATE;
 
 	res_timer = dev_request_mem_resource(dev, 0);
 	if (IS_ERR(res_timer)) {
diff --git a/drivers/watchdog/wd_core.c b/drivers/watchdog/wd_core.c
index 56436e6f8..1d0f0de7d 100644
--- a/drivers/watchdog/wd_core.c
+++ b/drivers/watchdog/wd_core.c
@@ -36,6 +36,9 @@ int watchdog_register(struct watchdog *wd)
 	if (!wd->priority)
 		wd->priority = WATCHDOG_DEFAULT_PRIORITY;
 
+	dev_add_param_uint32_ro(&wd->dev, "timeout_max",
+			&wd->timeout_max, "%u");
+
 	list_add_tail(&wd->list, &watchdog_list);
 
 	pr_debug("registering watchdog %s with priority %d\n", watchdog_name(wd),
@@ -81,6 +84,9 @@ int watchdog_set_timeout(unsigned timeout)
 	if (!wd)
 		return -ENODEV;
 
+	if (timeout > wd->timeout_max)
+		return -EINVAL;
+
 	pr_debug("setting timeout on %s to %ds\n", watchdog_name(wd), timeout);
 
 	return wd->set_timeout(wd, timeout);
diff --git a/include/watchdog.h b/include/watchdog.h
index 848981cc0..1e06fbc3f 100644
--- a/include/watchdog.h
+++ b/include/watchdog.h
@@ -18,6 +18,7 @@ struct watchdog {
 	const char *name;
 	struct device_d *hwdev;
 	unsigned int priority;
+	unsigned int timeout_max;
 	struct list_head list;
 };
 
-- 
2.16.1



From s.hauer at pengutronix.de  Fri Mar 16 05:52:38 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 16 Mar 2018 13:52:38 +0100
Subject: [PATCH 02/78] ARM: Add 64bit compilation alternative
In-Reply-To: <20180316125354.23462-1-s.hauer@pengutronix.de>
References: <20180316125354.23462-1-s.hauer@pengutronix.de>
Message-ID: <20180316125354.23462-3-s.hauer@pengutronix.de>

Our 64bit file variants have the suffix "_64". This adds a make variable
that is either empty or contains "_64" which can be used to easily
alternatively compile the 32bit or 64bit variant.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/Makefile     |  1 +
 arch/arm/cpu/Makefile | 19 ++++++-------------
 2 files changed, 7 insertions(+), 13 deletions(-)

diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 620a3ccb0b..da307343c7 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -65,6 +65,7 @@ endif
 ifeq ($(CONFIG_CPU_V8), y)
 CPPFLAGS += $(CFLAGS_ABI) $(arch-y) $(tune-y)
 AFLAGS   += -include asm/unified.h
+export S64 = _64
 else
 CPPFLAGS += $(CFLAGS_ABI) $(arch-y) $(tune-y) -msoft-float $(CFLAGS_THUMB2)
 AFLAGS   += -include asm/unified.h -msoft-float $(AFLAGS_THUMB2)
diff --git a/arch/arm/cpu/Makefile b/arch/arm/cpu/Makefile
index 94f7d1bf45..ba729fb6e4 100644
--- a/arch/arm/cpu/Makefile
+++ b/arch/arm/cpu/Makefile
@@ -1,24 +1,17 @@
 obj-y += cpu.o
 
-ifeq ($(CONFIG_CPU_64v8), y)
-obj-$(CONFIG_ARM_EXCEPTIONS) += exceptions_64.o
-obj-$(CONFIG_MMU) += mmu_64.o
-lwl-y += lowlevel_64.o
-else
-obj-$(CONFIG_ARM_EXCEPTIONS) += exceptions.o
-obj-$(CONFIG_MMU) += mmu.o
+obj-$(CONFIG_ARM_EXCEPTIONS) += exceptions$(S64).o
+obj-$(CONFIG_MMU) += mmu$(S64).o
+lwl-y += lowlevel$(S64).o
+
+ifeq ($(CONFIG_CPU_32), y)
 obj-pbl-$(CONFIG_MMU) += mmu-early.o
-lwl-y += lowlevel.o
 endif
 
 obj-$(CONFIG_ARM_EXCEPTIONS) += interrupts.o
 obj-y += start.o entry.o
 
-ifeq ($(CONFIG_CPU_64v8), y)
-obj-pbl-y += setupc_64.o
-else
-obj-pbl-y += setupc.o
-endif
+obj-pbl-y += setupc$(S64).o
 
 #
 # Any variants can be called as start-armxyz.S
-- 
2.16.1



From s.hauer at pengutronix.de  Fri Mar 16 05:52:45 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 16 Mar 2018 13:52:45 +0100
Subject: [PATCH 09/78] ARM: android image: Fix compiler warning on aarch64
In-Reply-To: <20180316125354.23462-1-s.hauer@pengutronix.de>
References: <20180316125354.23462-1-s.hauer@pengutronix.de>
Message-ID: <20180316125354.23462-10-s.hauer@pengutronix.de>

The android image format has a u32 value which tells the loader
where to put the ATAG list. Casting this value to a pointer directly
causes a warning on aarch64. Silence it by casting it to unsigned
long first. The code is of no use on aarch64, so no need to fix anything
really.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/lib/bootm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c
index 25efb42541..9c6174adfe 100644
--- a/arch/arm/lib/bootm.c
+++ b/arch/arm/lib/bootm.c
@@ -522,7 +522,7 @@ static int do_bootm_aimage(struct image_data *data)
 		linux_bootargs_overwrite(header->cmdline);
 
 	if (!getenv("aimage_noverwrite_tags"))
-		armlinux_set_bootparams((void*)header->tags_addr);
+		armlinux_set_bootparams((void *)(unsigned long)header->tags_addr);
 
 	cmp = &header->second_stage;
 	if (cmp->size) {
-- 
2.16.1



From s.hauer at pengutronix.de  Fri Mar 16 05:52:37 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 16 Mar 2018 13:52:37 +0100
Subject: [PATCH 01/78] ARM: Use obj-pbl- where appropriate
In-Reply-To: <20180316125354.23462-1-s.hauer@pengutronix.de>
References: <20180316125354.23462-1-s.hauer@pengutronix.de>
Message-ID: <20180316125354.23462-2-s.hauer@pengutronix.de>

When sourcefiles are compiled for barebox and pbl we have obj-pbl-. Use
it where appropriate.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/cpu/Makefile | 28 ++++++++++------------------
 1 file changed, 10 insertions(+), 18 deletions(-)

diff --git a/arch/arm/cpu/Makefile b/arch/arm/cpu/Makefile
index 13fe12c31f..94f7d1bf45 100644
--- a/arch/arm/cpu/Makefile
+++ b/arch/arm/cpu/Makefile
@@ -6,8 +6,8 @@ obj-$(CONFIG_MMU) += mmu_64.o
 lwl-y += lowlevel_64.o
 else
 obj-$(CONFIG_ARM_EXCEPTIONS) += exceptions.o
-obj-$(CONFIG_MMU) += mmu.o mmu-early.o
-pbl-$(CONFIG_MMU) += mmu-early.o
+obj-$(CONFIG_MMU) += mmu.o
+obj-pbl-$(CONFIG_MMU) += mmu-early.o
 lwl-y += lowlevel.o
 endif
 
@@ -15,11 +15,9 @@ obj-$(CONFIG_ARM_EXCEPTIONS) += interrupts.o
 obj-y += start.o entry.o
 
 ifeq ($(CONFIG_CPU_64v8), y)
-obj-y += setupc_64.o
-pbl-y += setupc_64.o
+obj-pbl-y += setupc_64.o
 else
-obj-y += setupc.o
-pbl-y += setupc.o
+obj-pbl-y += setupc.o
 endif
 
 #
@@ -40,25 +38,19 @@ AFLAGS_smccc-call.o	:=-Wa,-march=armv7-a
 obj-$(CONFIG_ARM_SECURE_MONITOR) += sm.o sm_as.o
 AFLAGS_sm_as.o		:=-Wa,-march=armv7-a
 
-obj-$(CONFIG_CPU_32v4T) += cache-armv4.o
-pbl-$(CONFIG_CPU_32v4T) += cache-armv4.o
-obj-$(CONFIG_CPU_32v5) += cache-armv5.o
-pbl-$(CONFIG_CPU_32v5) += cache-armv5.o
-obj-$(CONFIG_CPU_32v6) += cache-armv6.o
-pbl-$(CONFIG_CPU_32v6) += cache-armv6.o
+obj-pbl-$(CONFIG_CPU_32v4T) += cache-armv4.o
+obj-pbl-$(CONFIG_CPU_32v5) += cache-armv5.o
+obj-pbl-$(CONFIG_CPU_32v6) += cache-armv6.o
 AFLAGS_cache-armv7.o       :=-Wa,-march=armv7-a
-obj-$(CONFIG_CPU_32v7) += cache-armv7.o
+obj-pbl-$(CONFIG_CPU_32v7) += cache-armv7.o
 AFLAGS_pbl-cache-armv7.o       :=-Wa,-march=armv7-a
-pbl-$(CONFIG_CPU_32v7) += cache-armv7.o
 obj-$(CONFIG_CACHE_L2X0) += cache-l2x0.o
 AFLAGS_cache-armv8.o       :=-Wa,-march=armv8-a
-obj-$(CONFIG_CPU_64v8) += cache-armv8.o
+obj-pbl-$(CONFIG_CPU_64v8) += cache-armv8.o
 AFLAGS_pbl-cache-armv8.o       :=-Wa,-march=armv8-a
-pbl-$(CONFIG_CPU_64v8) += cache-armv8.o
 
 pbl-y += entry.o
 pbl-$(CONFIG_PBL_SINGLE_IMAGE) += start-pbl.o
 pbl-$(CONFIG_PBL_MULTI_IMAGES) += uncompress.o
 
-obj-y += common.o cache.o
-pbl-y += common.o cache.o
+obj-pbl-y += common.o cache.o
-- 
2.16.1



From s.hauer at pengutronix.de  Fri Mar 16 05:52:42 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 16 Mar 2018 13:52:42 +0100
Subject: [PATCH 06/78] ARM: scroll past image end without ld_var
In-Reply-To: <20180316125354.23462-1-s.hauer@pengutronix.de>
References: <20180316125354.23462-1-s.hauer@pengutronix.de>
Message-ID: <20180316125354.23462-7-s.hauer@pengutronix.de>

ld_var is going to be removed, cope without it. In the PBL image
we want to get the location after the binary to the place where
the compressed image is located. To do this Put a variable at
the very end of the binary, get it's location and add an offset.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/cpu/uncompress.c | 17 +++++++++--------
 arch/arm/lib/pbl.lds.S    |  5 ++---
 2 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/arch/arm/cpu/uncompress.c b/arch/arm/cpu/uncompress.c
index 2588e84b66..b600c1e7ec 100644
--- a/arch/arm/cpu/uncompress.c
+++ b/arch/arm/cpu/uncompress.c
@@ -37,9 +37,8 @@
 unsigned long free_mem_ptr;
 unsigned long free_mem_end_ptr;
 
-static int __attribute__((__used__))
-	__attribute__((__section__(".image_end")))
-	__image_end_dummy = 0xdeadbeef;
+static int __attribute__((__section__(".image_end")))
+	image_end_marker = 0xdeadbeef;
 
 void __noreturn barebox_multi_pbl_start(unsigned long membase,
 		unsigned long memsize, void *boarddata)
@@ -52,7 +51,7 @@ void __noreturn barebox_multi_pbl_start(unsigned long membase,
 	void *pg_start;
 	unsigned long pc = get_pc();
 
-	image_end = (void *)ld_var(__image_end) + get_runtime_offset();
+	image_end = (void *)&image_end_marker + get_runtime_offset();
 
 	if (IS_ENABLED(CONFIG_PBL_RELOCATABLE)) {
 		/*
@@ -67,11 +66,13 @@ void __noreturn barebox_multi_pbl_start(unsigned long membase,
 	}
 
 	/*
-	 * image_end is the first location after the executable. It contains
-	 * the size of the appended compressed binary followed by the binary.
+	 * image_end is the image_end_marker defined above. It is the last location
+	 * in the executable. Right after the executable the build process adds
+	 * the size of the appended compressed binary followed by the compressed
+	 * binary itself.
 	 */
-	pg_start = image_end + 1;
-	pg_len = *(image_end);
+	pg_start = image_end + 2;
+	pg_len = *(image_end + 1);
 	uncompressed_len = get_unaligned((const u32 *)(pg_start + pg_len - 4));
 
 	if (IS_ENABLED(CONFIG_RELOCATABLE))
diff --git a/arch/arm/lib/pbl.lds.S b/arch/arm/lib/pbl.lds.S
index 73baff0ca5..7de7791b71 100644
--- a/arch/arm/lib/pbl.lds.S
+++ b/arch/arm/lib/pbl.lds.S
@@ -87,10 +87,9 @@ SECTIONS
 	__piggydata_end = .;
 
 	. = ALIGN(4);
-	.image_end : {
-		KEEP(*(.image_end))
-	}
+	.image_end : { *(.image_end) }
 	__image_end = .;
+
 	_barebox_image_size = __image_end - BASE;
 	_barebox_pbl_size = __bss_start - BASE;
 }
-- 
2.16.1



From s.hauer at pengutronix.de  Fri Mar 16 05:52:41 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 16 Mar 2018 13:52:41 +0100
Subject: [PATCH 05/78] ARM: For relocatable image force TEXT_BASE 0x0
In-Reply-To: <20180316125354.23462-1-s.hauer@pengutronix.de>
References: <20180316125354.23462-1-s.hauer@pengutronix.de>
Message-ID: <20180316125354.23462-6-s.hauer@pengutronix.de>

Nothing else should be used for the relocatable image case, so
force TEXT_BASE to 0x0 and do not show it in the menu.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/Kconfig | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index e7edc2ad44..563475205d 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -2,7 +2,7 @@ config ARM
 	bool
 	select HAS_KALLSYMS
 	select HAS_CACHE
-	select HAVE_CONFIGURABLE_TEXT_BASE
+	select HAVE_CONFIGURABLE_TEXT_BASE if !RELOCATABLE
 	select HAVE_IMAGE_COMPRESSION
 	default y
 
@@ -19,6 +19,10 @@ config ARM_USE_COMPRESSED_DTB
 	select UNCOMPRESS
 	select LZO_DECOMPRESS
 
+config TEXT_BASE
+	hex
+	default 0x0
+
 menu "System Type"
 
 config BUILTIN_DTB
-- 
2.16.1



From s.hauer at pengutronix.de  Fri Mar 16 05:52:43 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 16 Mar 2018 13:52:43 +0100
Subject: [PATCH 07/78] ARM: move away from ld_var
In-Reply-To: <20180316125354.23462-1-s.hauer@pengutronix.de>
References: <20180316125354.23462-1-s.hauer@pengutronix.de>
Message-ID: <20180316125354.23462-8-s.hauer@pengutronix.de>

The ld_var solves the issue that when compiled with -pie the linker
provided variables are all 0x0. This mechanism however refuses to
compile with aarch64 support.

This patch replaces the ld_var mechanism with a nice little trick
learned from U-Boot: Instead of using linker provided variables
directly with "__bss_start = ." we put a zero size array into
a separate section and use the address of that array instead of
the linker variable. This properly works before relocation.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/boards/friendlyarm-tiny210/lowlevel.c |  4 ++--
 arch/arm/cpu/Makefile                          |  2 +-
 arch/arm/cpu/common.c                          | 11 ++++-------
 arch/arm/cpu/sections.c                        | 11 +++++++++++
 arch/arm/cpu/setupc.S                          |  9 ++++-----
 arch/arm/include/asm/sections.h                |  5 +++++
 arch/arm/lib/pbl.lds.S                         | 22 +++++++++-------------
 arch/arm/lib32/barebox.lds.S                   | 23 ++++++++++-------------
 arch/arm/lib64/barebox.lds.S                   | 22 +++++++++-------------
 arch/arm/mach-imx/xload-common.c               |  4 ++--
 10 files changed, 57 insertions(+), 56 deletions(-)
 create mode 100644 arch/arm/cpu/sections.c

diff --git a/arch/arm/boards/friendlyarm-tiny210/lowlevel.c b/arch/arm/boards/friendlyarm-tiny210/lowlevel.c
index fea00ef503..4b9ba87d70 100644
--- a/arch/arm/boards/friendlyarm-tiny210/lowlevel.c
+++ b/arch/arm/boards/friendlyarm-tiny210/lowlevel.c
@@ -96,7 +96,7 @@ void __bare_init barebox_arm_reset_vector(void)
 
 	debug_led(1, 1);
 
-	if (! load_stage2((void*)(ld_var(_text) - 16),
+	if (! load_stage2((void*)(_text - 16),
 				barebox_image_size + 16)) {
 		debug_led(3, 1);
 		while (1) { } /* hang */
@@ -104,7 +104,7 @@ void __bare_init barebox_arm_reset_vector(void)
 
 	debug_led(2, 1);
 
-	jump_sdram(IRAM_CODE_BASE - ld_var(_text));
+	jump_sdram(IRAM_CODE_BASE - (unsigned long)_text);
 
 	debug_led(1, 0);
 
diff --git a/arch/arm/cpu/Makefile b/arch/arm/cpu/Makefile
index ba729fb6e4..b2fed2be51 100644
--- a/arch/arm/cpu/Makefile
+++ b/arch/arm/cpu/Makefile
@@ -46,4 +46,4 @@ pbl-y += entry.o
 pbl-$(CONFIG_PBL_SINGLE_IMAGE) += start-pbl.o
 pbl-$(CONFIG_PBL_MULTI_IMAGES) += uncompress.o
 
-obj-pbl-y += common.o cache.o
+obj-pbl-y += common.o cache.o sections.o
diff --git a/arch/arm/cpu/common.c b/arch/arm/cpu/common.c
index 3c9864c0db..7c07d00c1b 100644
--- a/arch/arm/cpu/common.c
+++ b/arch/arm/cpu/common.c
@@ -36,11 +36,11 @@ void relocate_to_current_adr(void)
 	/* Get offset between linked address and runtime address */
 	offset = get_runtime_offset();
 
-	dstart = (void *)(ld_var(__rel_dyn_start) + offset);
-	dend = (void *)(ld_var(__rel_dyn_end) + offset);
+	dstart = (void *)__rel_dyn_start + offset;
+	dend = (void *)__rel_dyn_end + offset;
 
-	dynsym = (void *)(ld_var(__dynsym_start) + offset);
-	dynend = (void *)(ld_var(__dynsym_end) + offset);
+	dynsym = (void *)__dynsym_start + offset;
+	dynend = (void *)__dynsym_end + offset;
 
 	while (dstart < dend) {
 		uint32_t *fixup = (uint32_t *)(*dstart + offset);
@@ -77,6 +77,3 @@ int __pure cpu_architecture(void)
 	return __cpu_architecture;
 }
 #endif
-
-char __image_start[0] __attribute__((section(".__image_start")));
-char __image_end[0] __attribute__((section(".__image_end")));
\ No newline at end of file
diff --git a/arch/arm/cpu/sections.c b/arch/arm/cpu/sections.c
new file mode 100644
index 0000000000..5874da2b82
--- /dev/null
+++ b/arch/arm/cpu/sections.c
@@ -0,0 +1,11 @@
+#include <asm/sections.h>
+
+char __rel_dyn_start[0] __attribute__((section(".__rel_dyn_start")));
+char __rel_dyn_end[0] __attribute__((section(".__rel_dyn_end")));
+char __dynsym_start[0] __attribute__((section(".__dynsym_start")));
+char __dynsym_end[0] __attribute__((section(".__dynsym_end")));
+char _text[0] __attribute__((section("._text")));
+char __bss_start[0] __attribute__((section(".__bss_start")));
+char __bss_stop[0] __attribute__((section(".__bss_stop")));
+char __image_start[0] __attribute__((section(".__image_start")));
+char __image_end[0] __attribute__((section(".__image_end")));
diff --git a/arch/arm/cpu/setupc.S b/arch/arm/cpu/setupc.S
index 30e88330e7..717500cfff 100644
--- a/arch/arm/cpu/setupc.S
+++ b/arch/arm/cpu/setupc.S
@@ -55,17 +55,16 @@ ENTRY(relocate_to_adr)
 
 	mov	r5, r0
 
-	ld_var	_text, r0, r4
-	mov	r8, r0
+	ldr	r8, =_text
 
-	add	r1, r0, r5		/* r1: from address */
+	add	r1, r8, r5		/* r1: from address */
 
 	cmp	r1, r6			/* already at correct address? */
 	beq	1f			/* yes, skip copy to new address */
 
-	ld_var	__bss_start, r2, r4
+	ldr	r2, =__bss_start
 
-	sub	r2, r2, r0		/* r2: size */
+	sub	r2, r2, r8		/* r2: size */
 	mov	r0, r6			/* r0: target */
 
 	/* adjust return address */
diff --git a/arch/arm/include/asm/sections.h b/arch/arm/include/asm/sections.h
index 8c7bc8cccc..087f63fb60 100644
--- a/arch/arm/include/asm/sections.h
+++ b/arch/arm/include/asm/sections.h
@@ -4,6 +4,11 @@
 #ifndef __ASSEMBLY__
 #include <asm-generic/sections.h>
 
+extern char __rel_dyn_start[];
+extern char __rel_dyn_end[];
+extern char __dynsym_start[];
+extern char __dynsym_end[];
+
 /*
  * Access a linker supplied variable. Use this if your code might not be running
  * at the address it is linked at.
diff --git a/arch/arm/lib/pbl.lds.S b/arch/arm/lib/pbl.lds.S
index 7de7791b71..be0a4a3b1a 100644
--- a/arch/arm/lib/pbl.lds.S
+++ b/arch/arm/lib/pbl.lds.S
@@ -34,10 +34,10 @@ SECTIONS
 	PRE_IMAGE
 
 	. = ALIGN(4);
+	._text : { *(._text) }
 	.text      :
 	{
 		_stext = .;
-		_text = .;
 		*(.text_head_entry*)
 		__bare_init_start = .;
 		*(.text_bare_init*)
@@ -61,22 +61,18 @@ SECTIONS
 	. = ALIGN(4);
 	.data : { *(.data*) }
 
-	.rel.dyn : {
-		__rel_dyn_start = .;
-		*(.rel*)
-		__rel_dyn_end = .;
-	}
+	.rel_dyn_start : { *(.__rel_dyn_start) }
+	.rel.dyn : { *(.rel*) }
+	.rel_dyn_end : { *(.__rel_dyn_end) }
 
-	.dynsym : {
-		__dynsym_start = .;
-		*(.dynsym)
-		__dynsym_end = .;
-	}
+	.__dynsym_start :  { *(.__dynsym_start) }
+	.dynsym : { *(.dynsym) }
+	.__dynsym_end : { *(.__dynsym_end) }
 
 	. = ALIGN(4);
-	__bss_start = .;
+	.__bss_start :  { *(.__bss_start) }
 	.bss : { *(.bss*) }
-	__bss_stop = .;
+	.__bss_stop :  { *(.__bss_stop) }
 	_end = .;
 
 	. = ALIGN(4);
diff --git a/arch/arm/lib32/barebox.lds.S b/arch/arm/lib32/barebox.lds.S
index 6fadc2a357..594bf56837 100644
--- a/arch/arm/lib32/barebox.lds.S
+++ b/arch/arm/lib32/barebox.lds.S
@@ -37,10 +37,11 @@ SECTIONS
 	PRE_IMAGE
 #endif
 	. = ALIGN(4);
+
+	._text : { *(._text) }
 	.text      :
 	{
 		_stext = .;
-		_text = .;
 		*(.text_entry*)
 		__bare_init_start = .;
 		*(.text_bare_init*)
@@ -109,25 +110,21 @@ SECTIONS
 
 	.dtb : { BAREBOX_DTB() }
 
-	.rel.dyn : {
-		__rel_dyn_start = .;
-		*(.rel*)
-		__rel_dyn_end = .;
-	}
+	.rel_dyn_start : { *(.__rel_dyn_start) }
+	.rel.dyn : { *(.rel*) }
+	.rel_dyn_end : { *(.__rel_dyn_end) }
 
-	.dynsym : {
-		__dynsym_start = .;
-		*(.dynsym)
-		__dynsym_end = .;
-	}
+	.__dynsym_start :  { *(.__dynsym_start) }
+	.dynsym : { *(.dynsym) }
+	.__dynsym_end : { *(.__dynsym_end) }
 
 	_edata = .;
 	.image_end : { *(.__image_end) }
 
 	. = ALIGN(4);
-	__bss_start = .;
+	.__bss_start :  { *(.__bss_start) }
 	.bss : { *(.bss*) }
-	__bss_stop = .;
+	.__bss_stop :  { *(.__bss_stop) }
 
 #ifdef CONFIG_ARM_SECURE_MONITOR
 	. = ALIGN(16);
diff --git a/arch/arm/lib64/barebox.lds.S b/arch/arm/lib64/barebox.lds.S
index a53b933bba..fa633e3699 100644
--- a/arch/arm/lib64/barebox.lds.S
+++ b/arch/arm/lib64/barebox.lds.S
@@ -35,10 +35,10 @@ SECTIONS
 	PRE_IMAGE
 #endif
 	. = ALIGN(4);
+	._text : { *(._text) }
 	.text      :
 	{
 		_stext = .;
-		_text = .;
 		*(.text_entry*)
 		__bare_init_start = .;
 		*(.text_bare_init*)
@@ -106,24 +106,20 @@ SECTIONS
 
 	.dtb : { BAREBOX_DTB() }
 
-	.rel.dyn : {
-		__rel_dyn_start = .;
-		*(.rel*)
-		__rel_dyn_end = .;
-	}
+	.rel_dyn_start : { *(.__rel_dyn_start) }
+	.rela.dyn : { *(.rela*) }
+	.rel_dyn_end : { *(.__rel_dyn_end) }
 
-	.dynsym : {
-		__dynsym_start = .;
-		*(.dynsym)
-		__dynsym_end = .;
-	}
+	.__dynsym_start :  { *(.__dynsym_start) }
+	.dynsym : { *(.dynsym) }
+	.__dynsym_end : { *(.__dynsym_end) }
 
 	_edata = .;
 
 	. = ALIGN(4);
-	__bss_start = .;
+	.__bss_start :  { *(.__bss_start) }
 	.bss : { *(.bss*) }
-	__bss_stop = .;
+	.__bss_stop :  { *(.__bss_stop) }
 	_end = .;
 	_barebox_image_size = __bss_start - TEXT_BASE;
 }
diff --git a/arch/arm/mach-imx/xload-common.c b/arch/arm/mach-imx/xload-common.c
index 2644438f40..13cd612d3c 100644
--- a/arch/arm/mach-imx/xload-common.c
+++ b/arch/arm/mach-imx/xload-common.c
@@ -5,7 +5,7 @@
 
 int imx_image_size(void)
 {
-	uint32_t *image_end = (void *)ld_var(__image_end);
+	uint32_t *image_end = (void *)__image_end;
 	uint32_t payload_len, pbl_len, imx_header_len, sizep;
 	void *pg_start;
 
@@ -15,7 +15,7 @@ int imx_image_size(void)
 	imx_header_len = SZ_4K;
 
 	/* The length of the PBL image */
-	pbl_len = ld_var(__image_end) - ld_var(_text);
+	pbl_len = __image_end - _text;
 
 	sizep = 4;
 
-- 
2.16.1



From s.hauer at pengutronix.de  Fri Mar 16 05:52:44 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 16 Mar 2018 13:52:44 +0100
Subject: [PATCH 08/78] ARM: remove ld_var support
In-Reply-To: <20180316125354.23462-1-s.hauer@pengutronix.de>
References: <20180316125354.23462-1-s.hauer@pengutronix.de>
Message-ID: <20180316125354.23462-9-s.hauer@pengutronix.de>

Now that ld_var is no longer used it can be removed.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/include/asm/sections.h | 25 -------------------------
 arch/arm/lib32/runtime-offset.S | 32 --------------------------------
 2 files changed, 57 deletions(-)

diff --git a/arch/arm/include/asm/sections.h b/arch/arm/include/asm/sections.h
index 087f63fb60..b3ada62ee8 100644
--- a/arch/arm/include/asm/sections.h
+++ b/arch/arm/include/asm/sections.h
@@ -9,31 +9,6 @@ extern char __rel_dyn_end[];
 extern char __dynsym_start[];
 extern char __dynsym_end[];
 
-/*
- * Access a linker supplied variable. Use this if your code might not be running
- * at the address it is linked at.
- */
-#define ld_var(name) ({ \
-	unsigned long __ld_var_##name(void); \
-	__ld_var_##name(); \
-})
-
-#else
-
-/*
- * Access a linker supplied variable, assembler macro version
- */
-.macro ld_var name, reg, scratch
-	1000:
-		ldr \reg, 1001f
-		ldr \scratch, =1000b
-		add \reg, \reg, \scratch
-		b 1002f
-	1001:
-		.word \name - 1000b
-	1002:
-.endm
-
 #endif
 
 #endif /* __ASM_SECTIONS_H */
diff --git a/arch/arm/lib32/runtime-offset.S b/arch/arm/lib32/runtime-offset.S
index 39b525b187..f86ca7865e 100644
--- a/arch/arm/lib32/runtime-offset.S
+++ b/arch/arm/lib32/runtime-offset.S
@@ -17,35 +17,3 @@ THUMB(	adds r0, r0, #1)
 linkadr:
 .word get_runtime_offset
 ENDPROC(get_runtime_offset)
-
-.globl __ld_var_base
-__ld_var_base:
-
-/*
- * Functions to calculate selected linker supplied variables during runtime.
- * This is needed for relocatable binaries when the linker variables are
- * needed before finxing up the relocations.
- */
-.macro ld_var_entry name
-	ENTRY(__ld_var_\name)
-		ldr r0, __\name
-		b 1f
-	__\name: .word \name - __ld_var_base
-	ENDPROC(__ld_var_\name)
-.endm
-
-ld_var_entry _text
-ld_var_entry __rel_dyn_start
-ld_var_entry __rel_dyn_end
-ld_var_entry __dynsym_start
-ld_var_entry __dynsym_end
-ld_var_entry __bss_start
-ld_var_entry __bss_stop
-#ifdef __PBL__
-ld_var_entry __image_end
-#endif
-
-1:
-	ldr r1, =__ld_var_base
-	adds r0, r0, r1
-	mov pc, lr
-- 
2.16.1



From s.hauer at pengutronix.de  Fri Mar 16 05:52:40 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 16 Mar 2018 13:52:40 +0100
Subject: [PATCH 04/78] ARM: mmu: include pgtable header from where it's needed
In-Reply-To: <20180316125354.23462-1-s.hauer@pengutronix.de>
References: <20180316125354.23462-1-s.hauer@pengutronix.de>
Message-ID: <20180316125354.23462-5-s.hauer@pengutronix.de>

Instead of #ifdefing the correct pgtable header file to include,
include it where it's needed. Also, move the memory type attributes
into there consumers, namely the mmu.c files.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/boards/qemu-virt64/init.c |  5 ++++-
 arch/arm/cpu/common.c              |  1 -
 arch/arm/cpu/mmu-early.c           |  1 +
 arch/arm/cpu/mmu.c                 |  4 ++++
 arch/arm/cpu/mmu_64.c              |  4 ++++
 arch/arm/cpu/start-pbl.c           |  1 -
 arch/arm/cpu/uncompress.c          |  1 -
 arch/arm/include/asm/mmu.h         | 15 ---------------
 8 files changed, 13 insertions(+), 19 deletions(-)

diff --git a/arch/arm/boards/qemu-virt64/init.c b/arch/arm/boards/qemu-virt64/init.c
index a85bd84db7..18831755df 100644
--- a/arch/arm/boards/qemu-virt64/init.c
+++ b/arch/arm/boards/qemu-virt64/init.c
@@ -8,6 +8,7 @@
 #include <init.h>
 #include <asm/armlinux.h>
 #include <asm/system_info.h>
+#include <asm/pgtable64.h>
 #include <mach/devices.h>
 #include <environment.h>
 #include <linux/sizes.h>
@@ -66,7 +67,9 @@ postcore_initcall(virt_core_init);
 static int virt_mmu_enable(void)
 {
 	/* Mapping all periph and flash range */
-	arch_remap_range((void *)0x00000000, 0x40000000, DEV_MEM);
+	arch_remap_range((void *)0x00000000, 0x40000000,
+			 PMD_ATTRINDX(MT_DEVICE_nGnRnE) | PMD_SECT_AF |
+			 PMD_TYPE_SECT);
 
 	mmu_enable();
 
diff --git a/arch/arm/cpu/common.c b/arch/arm/cpu/common.c
index 6670f4b9f8..3c9864c0db 100644
--- a/arch/arm/cpu/common.c
+++ b/arch/arm/cpu/common.c
@@ -23,7 +23,6 @@
 #include <asm/barebox-arm-head.h>
 #include <asm-generic/memory_layout.h>
 #include <asm/sections.h>
-#include <asm/pgtable.h>
 #include <asm/cache.h>
 
 /*
diff --git a/arch/arm/cpu/mmu-early.c b/arch/arm/cpu/mmu-early.c
index 2e4d316924..1549f08985 100644
--- a/arch/arm/cpu/mmu-early.c
+++ b/arch/arm/cpu/mmu-early.c
@@ -5,6 +5,7 @@
 #include <asm/memory.h>
 #include <asm/system.h>
 #include <asm/cache.h>
+#include <asm/pgtable.h>
 
 #include "mmu.h"
 
diff --git a/arch/arm/cpu/mmu.c b/arch/arm/cpu/mmu.c
index 459abe56ba..2c16579d79 100644
--- a/arch/arm/cpu/mmu.c
+++ b/arch/arm/cpu/mmu.c
@@ -27,11 +27,15 @@
 #include <asm/barebox-arm.h>
 #include <asm/system.h>
 #include <asm/cache.h>
+#include <asm/pgtable.h>
 #include <memory.h>
 #include <asm/system_info.h>
 
 #include "mmu.h"
 
+#define PMD_SECT_DEF_UNCACHED (PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | PMD_TYPE_SECT)
+#define PMD_SECT_DEF_CACHED (PMD_SECT_WB | PMD_SECT_DEF_UNCACHED)
+
 static unsigned long *ttb;
 
 static void create_sections(unsigned long virt, unsigned long phys, int size_m,
diff --git a/arch/arm/cpu/mmu_64.c b/arch/arm/cpu/mmu_64.c
index bfd80c0913..fd41435746 100644
--- a/arch/arm/cpu/mmu_64.c
+++ b/arch/arm/cpu/mmu_64.c
@@ -25,6 +25,7 @@
 #include <errno.h>
 #include <linux/sizes.h>
 #include <asm/memory.h>
+#include <asm/pgtable64.h>
 #include <asm/barebox-arm.h>
 #include <asm/system.h>
 #include <asm/cache.h>
@@ -33,6 +34,9 @@
 
 #include "mmu.h"
 
+#define CACHED_MEM      (PMD_ATTRINDX(MT_NORMAL) | PMD_SECT_S | PMD_SECT_AF | PMD_TYPE_SECT)
+#define UNCACHED_MEM    (PMD_ATTRINDX(MT_NORMAL_NC) | PMD_SECT_S | PMD_SECT_AF | PMD_TYPE_SECT)
+
 static uint64_t *ttb;
 static int free_idx;
 
diff --git a/arch/arm/cpu/start-pbl.c b/arch/arm/cpu/start-pbl.c
index 865aa1b1c4..68b2bbf6fb 100644
--- a/arch/arm/cpu/start-pbl.c
+++ b/arch/arm/cpu/start-pbl.c
@@ -26,7 +26,6 @@
 #include <asm/barebox-arm-head.h>
 #include <asm-generic/memory_layout.h>
 #include <asm/sections.h>
-#include <asm/pgtable.h>
 #include <asm/cache.h>
 #include <asm/unaligned.h>
 
diff --git a/arch/arm/cpu/uncompress.c b/arch/arm/cpu/uncompress.c
index 5530919118..2588e84b66 100644
--- a/arch/arm/cpu/uncompress.c
+++ b/arch/arm/cpu/uncompress.c
@@ -27,7 +27,6 @@
 #include <asm/barebox-arm-head.h>
 #include <asm-generic/memory_layout.h>
 #include <asm/sections.h>
-#include <asm/pgtable.h>
 #include <asm/cache.h>
 #include <asm/unaligned.h>
 
diff --git a/arch/arm/include/asm/mmu.h b/arch/arm/include/asm/mmu.h
index f68ab37143..2a1daeafe3 100644
--- a/arch/arm/include/asm/mmu.h
+++ b/arch/arm/include/asm/mmu.h
@@ -6,21 +6,6 @@
 #include <malloc.h>
 #include <xfuncs.h>
 
-#ifdef CONFIG_CPU_64v8
-#include <asm/pgtable64.h>
-
-#define DEV_MEM		(PMD_ATTRINDX(MT_DEVICE_nGnRnE) | PMD_SECT_AF | PMD_TYPE_SECT)
-#define CACHED_MEM	(PMD_ATTRINDX(MT_NORMAL) | PMD_SECT_S | PMD_SECT_AF | PMD_TYPE_SECT)
-#define UNCACHED_MEM	(PMD_ATTRINDX(MT_NORMAL_NC) | PMD_SECT_S | PMD_SECT_AF | PMD_TYPE_SECT)
-#else
-#include <asm/pgtable.h>
-
-#define PMD_SECT_DEF_UNCACHED (PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | PMD_TYPE_SECT)
-#define PMD_SECT_DEF_CACHED (PMD_SECT_WB | PMD_SECT_DEF_UNCACHED)
-#endif
-
-
-
 struct arm_memory;
 
 void mmu_enable(void);
-- 
2.16.1



From s.hauer at pengutronix.de  Fri Mar 16 05:52:46 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 16 Mar 2018 13:52:46 +0100
Subject: [PATCH 10/78] ARM: bootm: Fix wrong format specifier
In-Reply-To: <20180316125354.23462-1-s.hauer@pengutronix.de>
References: <20180316125354.23462-1-s.hauer@pengutronix.de>
Message-ID: <20180316125354.23462-11-s.hauer@pengutronix.de>

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/lib/bootm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c
index 9c6174adfe..c8bf72f0e0 100644
--- a/arch/arm/lib/bootm.c
+++ b/arch/arm/lib/bootm.c
@@ -362,7 +362,7 @@ static int do_bootz_linux(struct image_data *data)
 
 	data->os_res = request_sdram_region("zimage", load_address, image_size);
 	if (!data->os_res) {
-		pr_err("bootm/zImage: failed to request memory at 0x%lx to 0x%lx (%d).\n",
+		pr_err("bootm/zImage: failed to request memory at 0x%lx to 0x%lx (%zu).\n",
 		       load_address, load_address + image_size, image_size);
 		ret = -ENOMEM;
 		goto err_out;
-- 
2.16.1



From s.hauer at pengutronix.de  Fri Mar 16 05:52:57 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 16 Mar 2018 13:52:57 +0100
Subject: [PATCH 21/78] debug_ll: support 64bit longs
In-Reply-To: <20180316125354.23462-1-s.hauer@pengutronix.de>
References: <20180316125354.23462-1-s.hauer@pengutronix.de>
Message-ID: <20180316125354.23462-22-s.hauer@pengutronix.de>

puthex_ll outputs an unsigned long, so print all digits in case unsigned
long is 64bit.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 include/debug_ll.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/debug_ll.h b/include/debug_ll.h
index b0eb7cd7d9..5047516399 100644
--- a/include/debug_ll.h
+++ b/include/debug_ll.h
@@ -42,7 +42,7 @@ static inline void puthex_ll(unsigned long value)
 {
 	int i; unsigned char ch;
 
-	for (i = 8; i--; ) {
+	for (i = sizeof(unsigned long) * 2; i--; ) {
 		ch = ((value >> (i * 4)) & 0xf);
 		ch += (ch >= 10) ? 'a' - 10 : '0';
 		putc_ll(ch);
-- 
2.16.1



From s.hauer at pengutronix.de  Fri Mar 16 05:53:28 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 16 Mar 2018 13:53:28 +0100
Subject: [PATCH 52/78] ARM: aarch64: compile with strict alignment
In-Reply-To: <20180316125354.23462-1-s.hauer@pengutronix.de>
References: <20180316125354.23462-1-s.hauer@pengutronix.de>
Message-ID: <20180316125354.23462-53-s.hauer@pengutronix.de>

barebox runs with MMU disabled at least during startup. We need
-mstrict-alignment for these parts to avoid alignment aborts.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/Makefile | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index da307343c7..cf84a9a1c1 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -23,6 +23,8 @@ endif
 # accesses
 ifneq ($(CONFIG_CPU_V8),y)
 CFLAGS += -mno-unaligned-access
+else
+CFLAGS += -mstrict-align
 endif
 
 
-- 
2.16.1



From s.hauer at pengutronix.de  Fri Mar 16 05:52:47 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 16 Mar 2018 13:52:47 +0100
Subject: [PATCH 11/78] ARM: shutdown: Fix compiler warning
In-Reply-To: <20180316125354.23462-1-s.hauer@pengutronix.de>
References: <20180316125354.23462-1-s.hauer@pengutronix.de>
Message-ID: <20180316125354.23462-12-s.hauer@pengutronix.de>

On aarch64 we get a unused variable warning. Move the variable
declaration into the #ifdef where the variable is used.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/cpu/cpu.c | 28 +++++++++++++++++-----------
 1 file changed, 17 insertions(+), 11 deletions(-)

diff --git a/arch/arm/cpu/cpu.c b/arch/arm/cpu/cpu.c
index bf604fd60d..0e70a23260 100644
--- a/arch/arm/cpu/cpu.c
+++ b/arch/arm/cpu/cpu.c
@@ -89,6 +89,22 @@ void mmu_disable(void)
 }
 #endif
 
+static void disable_interrupts(void)
+{
+#if __LINUX_ARM_ARCH__ <= 7
+	uint32_t r;
+
+	/*
+	 * barebox normally does not use interrupts, but some functionalities
+	 * (eg. OMAP4_USBBOOT) require them enabled. So be sure interrupts are
+	 * disabled before exiting.
+	 */
+	__asm__ __volatile__("mrs %0, cpsr" : "=r"(r));
+	r |= PSR_I_BIT;
+	__asm__ __volatile__("msr cpsr, %0" : : "r"(r));
+#endif
+}
+
 /**
  * Disable MMU and D-cache, flush caches
  * @return 0 (always)
@@ -98,23 +114,13 @@ void mmu_disable(void)
  */
 static void arch_shutdown(void)
 {
-	uint32_t r;
 
 #ifdef CONFIG_MMU
 	mmu_disable();
 #endif
 	icache_invalidate();
 
-#if __LINUX_ARM_ARCH__ <= 7
-	/*
-	 * barebox normally does not use interrupts, but some functionalities
-	 * (eg. OMAP4_USBBOOT) require them enabled. So be sure interrupts are
-	 * disabled before exiting.
-	 */
-	__asm__ __volatile__("mrs %0, cpsr" : "=r"(r));
-	r |= PSR_I_BIT;
-	__asm__ __volatile__("msr cpsr, %0" : : "r"(r));
-#endif
+	disable_interrupts();
 }
 archshutdown_exitcall(arch_shutdown);
 
-- 
2.16.1



From s.hauer at pengutronix.de  Fri Mar 16 05:53:14 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 16 Mar 2018 13:53:14 +0100
Subject: [PATCH 38/78] ARM: aarch64: qemu board: remove unnecessary mapping
In-Reply-To: <20180316125354.23462-1-s.hauer@pengutronix.de>
References: <20180316125354.23462-1-s.hauer@pengutronix.de>
Message-ID: <20180316125354.23462-39-s.hauer@pengutronix.de>

Now that we do the initial flat mapping as device memory all addresses
that are not SDRAM are already mapped as device memory, so we can drop
the mapping from the board file.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/boards/qemu-virt64/init.c | 5 -----
 1 file changed, 5 deletions(-)

diff --git a/arch/arm/boards/qemu-virt64/init.c b/arch/arm/boards/qemu-virt64/init.c
index 18831755df..686231696e 100644
--- a/arch/arm/boards/qemu-virt64/init.c
+++ b/arch/arm/boards/qemu-virt64/init.c
@@ -66,11 +66,6 @@ postcore_initcall(virt_core_init);
 #ifdef CONFIG_MMU
 static int virt_mmu_enable(void)
 {
-	/* Mapping all periph and flash range */
-	arch_remap_range((void *)0x00000000, 0x40000000,
-			 PMD_ATTRINDX(MT_DEVICE_nGnRnE) | PMD_SECT_AF |
-			 PMD_TYPE_SECT);
-
 	mmu_enable();
 
 	return 0;
-- 
2.16.1



From s.hauer at pengutronix.de  Fri Mar 16 05:52:55 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 16 Mar 2018 13:52:55 +0100
Subject: [PATCH 19/78] ARM: aarch64: Do not use 32bit optimized fls
In-Reply-To: <20180316125354.23462-1-s.hauer@pengutronix.de>
References: <20180316125354.23462-1-s.hauer@pengutronix.de>
Message-ID: <20180316125354.23462-20-s.hauer@pengutronix.de>

The clz operation only works with 32bit values, so use the generic
fls() variants on aarch64. With this tlsf_malloc works as expected.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/include/asm/bitops.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/include/asm/bitops.h b/arch/arm/include/asm/bitops.h
index cd356c5e3d..348a76b2c1 100644
--- a/arch/arm/include/asm/bitops.h
+++ b/arch/arm/include/asm/bitops.h
@@ -115,7 +115,7 @@ extern int _find_next_bit_be(const unsigned long *p, int size, int offset);
 
 #endif		/* __ARMEB__ */
 
-#if defined(__LINUX_ARM_ARCH__) && (__LINUX_ARM_ARCH__ >= 5)
+#if defined (CONFIG_CPU_32) && defined(__LINUX_ARM_ARCH__) && (__LINUX_ARM_ARCH__ >= 5)
 static inline int constant_fls(int x)
 {
 	int r = 32;
-- 
2.16.1



From s.hauer at pengutronix.de  Fri Mar 16 05:53:01 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 16 Mar 2018 13:53:01 +0100
Subject: [PATCH 25/78] ARM: Add function to return offset to global variables
In-Reply-To: <20180316125354.23462-1-s.hauer@pengutronix.de>
References: <20180316125354.23462-1-s.hauer@pengutronix.de>
Message-ID: <20180316125354.23462-26-s.hauer@pengutronix.de>

ARM and aarch64 differ in the way global variables are addressed. This
adds a function which abstracts the differences.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/cpu/start-pbl.c           |  4 ++--
 arch/arm/cpu/uncompress.c          |  2 +-
 arch/arm/include/asm/barebox-arm.h | 14 ++++++++++++++
 3 files changed, 17 insertions(+), 3 deletions(-)

diff --git a/arch/arm/cpu/start-pbl.c b/arch/arm/cpu/start-pbl.c
index 68b2bbf6fb..73c27429da 100644
--- a/arch/arm/cpu/start-pbl.c
+++ b/arch/arm/cpu/start-pbl.c
@@ -60,8 +60,8 @@ __noreturn void barebox_single_pbl_start(unsigned long membase,
 	/* Get offset between linked address and runtime address */
 	offset = get_runtime_offset();
 
-	pg_start = (uint32_t)&input_data + offset;
-	pg_end = (uint32_t)&input_data_end + offset;
+	pg_start = (uint32_t)&input_data + global_variable_offset();
+	pg_end = (uint32_t)&input_data_end + global_variable_offset();
 	pg_len = pg_end - pg_start;
 	uncompressed_len = get_unaligned((const u32 *)(pg_start + pg_len - 4));
 
diff --git a/arch/arm/cpu/uncompress.c b/arch/arm/cpu/uncompress.c
index b600c1e7ec..37845b2259 100644
--- a/arch/arm/cpu/uncompress.c
+++ b/arch/arm/cpu/uncompress.c
@@ -51,7 +51,7 @@ void __noreturn barebox_multi_pbl_start(unsigned long membase,
 	void *pg_start;
 	unsigned long pc = get_pc();
 
-	image_end = (void *)&image_end_marker + get_runtime_offset();
+	image_end = (void *)&image_end_marker + global_variable_offset();
 
 	if (IS_ENABLED(CONFIG_PBL_RELOCATABLE)) {
 		/*
diff --git a/arch/arm/include/asm/barebox-arm.h b/arch/arm/include/asm/barebox-arm.h
index 1dccb8965e..9fc8afbe7d 100644
--- a/arch/arm/include/asm/barebox-arm.h
+++ b/arch/arm/include/asm/barebox-arm.h
@@ -44,6 +44,20 @@ extern char __exceptions_start[], __exceptions_stop[];
 void board_init_lowlevel(void);
 unsigned long get_runtime_offset(void);
 
+/* global_variable_offset() - Access global variables when not running at link address
+ *
+ * Get the offset of global variables when not running at the address we are
+ * linked at. ARM uses absolute addresses, so we must add the runtime offset
+ * whereas aarch64 uses PC relative addresses, so nothing must be done here.
+ */
+static inline unsigned long global_variable_offset(void)
+{
+	if (IS_ENABLED(CONFIG_CPU_32))
+		return get_runtime_offset();
+	else
+		return 0;
+}
+
 void setup_c(void);
 void relocate_to_current_adr(void);
 void relocate_to_adr(unsigned long target);
-- 
2.16.1



From s.hauer at pengutronix.de  Fri Mar 16 05:52:36 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 16 Mar 2018 13:52:36 +0100
Subject: [PATCH 00/78] ARM aarch64 updates
Message-ID: <20180316125354.23462-1-s.hauer@pengutronix.de>

Hi All,

Here is a massive update for the ARM aarch64 port. With the following
series the aarch64 port should be on par with the 32bit support.

With this aarch64 supports relocatable binaries, proper MMU support, DMA
cache maintenance operations, and finally starting a aarch64 Linux
image :)

This all has been developed on a i.MX8MQ EVK board. The i.MX8MQ patches
are currently evolving, but are not yet quite ready. DDR setup is still
very crude and pinmux is not yet working. NXP did a nice job with the
i.MX8MQ: It behaves very much like a i.MX6 with a different core, so
we already have most of the drivers and I could concentrate on the
aarch64 update. I hope I can send i.MX8 patches soon.

Sascha


Sascha Hauer (78):
  ARM: Use obj-pbl- where appropriate
  ARM: Add 64bit compilation alternative
  ARM: return positive offset in get_runtime_offset()
  ARM: mmu: include pgtable header from where it's needed
  ARM: For relocatable image force TEXT_BASE 0x0
  ARM: scroll past image end without ld_var
  ARM: move away from ld_var
  ARM: remove ld_var support
  ARM: android image: Fix compiler warning on aarch64
  ARM: bootm: Fix wrong format specifier
  ARM: shutdown: Fix compiler warning
  ARM: aarch64: silence compiler warning
  ARM: aarch64: Add dummy naked attribute
  ARM: get_runtime_offset() returns unsigned long
  ARM: aarch64: Add runtime-offset
  ARM: aarch64: implement get_pc()
  ARM: Use generic ffz()
  ARM: bitops: remove unnecessary #ifdef
  ARM: aarch64: Do not use 32bit optimized fls
  ARM: Move mmu_disable to mmu.c
  debug_ll: support 64bit longs
  ARM: aarch64: fix early cache flushing
  ARM: aarch64: cache: Add v8_inv_dcache_range
  ARM: aarch64: cache: no need to ifdef prototypes
  ARM: Add function to return offset to global variables
  ARM: remove function prototypes from the past
  ARM: move linker variable declarations to sections.h
  ARM: relocate_to_current_adr: Use unsigned long for variables
  clocksource: Add armv8 generic timer support
  ARM: aarch64: Add relocation support
  ARM: aarch64: fix pbl linker script for aarch64
  ARM: aarch64: mmu: Allocate page tables dynamically
  ARM: aarch64: mmu: create_sections() takes size in bytes
  ARM: aarch64: mmu: fix creation of flat mapping
  ARM: aarch64: mmu: remove unused map_io_sections()
  ARM: aarch64: mmu: by default map as device memory
  ARM: aarch64: mmu: Fix mair register setting
  ARM: aarch64: qemu board: remove unnecessary mapping
  ARM: aarch64: mmu: enable mmu in generic code
  ARM: aarch64: mmu: use PTE_* definitions from U-Boot
  ARM: aarch64: mmu: Fix adding additional page table levels
  ARM: aarch64: mmu: Fix PTE_TYPE_* flags
  ARM: aarch64: mmu: Fix TCR setting
  ARM: aarch64: mmu: No need to disable icache
  ARM: aarch64: mmu: drop ttb check when disabling the MMU
  ARM: aarch64: mmu: Fix disabling the MMU
  ARM: Make some variables 64bit aware
  dma: Use dma_addr_t as type for DMA addresses
  dma: Add prototypes for dma mapping functions
  ARM: implement dma mapping functions
  ARM: aarch64: implement dma operations
  ARM: aarch64: compile with strict alignment
  ARM: aarch64: move aarch64 exception support to separate file
  ARM: aarch64: fix exception level mixup
  ARM: aarch64: Setup exception vectors in initcall
  ARM: aarch64: lowlevel: Use switch_el
  ARM: aarch64: remove dead code in linker script
  ARM: aarch64: hide some config options
  ARM: aarch64: implement show_regs()
  ARM: aarch64: implement stacktraces
  ARM: aarch64: mmu: Make zero page faulting
  ARM: aarch64: Allow to leave exceptions
  ARM: aarch64: Add esr strings
  ARM: aarch64: print more information on sync exception
  ARM: aarch64: implement ignoring data aborts
  dt-bindings: Drop unused files
  ARM: aarch64: Add barebox head support
  filetype: Detect ARM aarch64 Linux images
  common: Add functions to find free RAM
  bootm: provide handlers the start of the OS image
  ARM: aarch64: disable 32bit boot commands
  ARM: aarch64: Add support to start kernel and barebox
  ARM: cache-armv4: Fix wrong section
  ARM: build: Remove duplicate file compilation
  ARM: Create own cache.c file for aarch64
  ARM: create separate mmu_64.h file
  ARM: change mmu_early_enable() prototype
  ARM: aarch64: Make early MMU support work

 arch/arm/Kconfig                                   |   9 +-
 arch/arm/Makefile                                  |   4 +-
 arch/arm/boards/afi-gf/lowlevel.c                  |   2 +-
 arch/arm/boards/altera-socdk/lowlevel.c            |   2 +-
 arch/arm/boards/at91sam9263ek/lowlevel_init.c      |   2 +-
 arch/arm/boards/at91sam9x5ek/lowlevel.c            |   2 +-
 arch/arm/boards/beaglebone/lowlevel.c              |   2 +-
 .../boards/boundarydevices-nitrogen6/lowlevel.c    |  10 +-
 arch/arm/boards/ccxmx53/lowlevel.c                 |   4 +-
 arch/arm/boards/datamodul-edm-qmx6/lowlevel.c      |   2 +-
 arch/arm/boards/dfi-fs700-m60/lowlevel.c           |   6 +-
 arch/arm/boards/duckbill/lowlevel.c                |   2 +-
 arch/arm/boards/ebv-socrates/lowlevel.c            |   2 +-
 arch/arm/boards/efika-mx-smartbook/lowlevel.c      |   2 +-
 arch/arm/boards/element14-warp7/lowlevel.c         |   2 +-
 arch/arm/boards/eltec-hipercam/lowlevel.c          |   2 +-
 arch/arm/boards/embedsky-e9/lowlevel.c             |   2 +-
 arch/arm/boards/embest-riotboard/lowlevel.c        |   2 +-
 arch/arm/boards/freescale-mx51-babbage/lowlevel.c  |   2 +-
 arch/arm/boards/freescale-mx53-qsb/lowlevel.c      |   4 +-
 arch/arm/boards/freescale-mx53-vmx53/lowlevel.c    |   2 +-
 arch/arm/boards/freescale-mx6-sabresd/lowlevel.c   |   2 +-
 .../arm/boards/freescale-mx6sx-sabresdb/lowlevel.c |   2 +-
 arch/arm/boards/freescale-mx7-sabresd/lowlevel.c   |   2 +-
 arch/arm/boards/freescale-vf610-twr/lowlevel.c     |   2 +-
 arch/arm/boards/friendlyarm-tiny210/lowlevel.c     |   4 +-
 arch/arm/boards/gateworks-ventana/lowlevel.c       |   2 +-
 arch/arm/boards/gk802/lowlevel.c                   |   2 +-
 arch/arm/boards/globalscale-guruplug/lowlevel.c    |   2 +-
 arch/arm/boards/globalscale-mirabox/lowlevel.c     |   2 +-
 arch/arm/boards/karo-tx25/lowlevel.c               |   2 +-
 arch/arm/boards/karo-tx6x/lowlevel.c               |   8 +-
 arch/arm/boards/kindle-mx50/lowlevel.c             |   6 +-
 arch/arm/boards/lenovo-ix4-300d/lowlevel.c         |   2 +-
 arch/arm/boards/marvell-armada-xp-gp/lowlevel.c    |   2 +-
 arch/arm/boards/netgear-rn104/lowlevel.c           |   2 +-
 arch/arm/boards/netgear-rn2120/lowlevel.c          |   2 +-
 arch/arm/boards/phytec-phycard-imx27/lowlevel.c    |   2 +-
 arch/arm/boards/phytec-phycore-imx27/lowlevel.c    |   2 +-
 arch/arm/boards/phytec-phycore-imx7/lowlevel.c     |   4 +-
 arch/arm/boards/phytec-som-am335x/lowlevel.c       |   6 +-
 arch/arm/boards/phytec-som-imx6/lowlevel.c         |   2 +-
 arch/arm/boards/phytec-som-rk3288/lowlevel.c       |   2 +-
 arch/arm/boards/plathome-openblocks-a6/lowlevel.c  |   2 +-
 arch/arm/boards/plathome-openblocks-ax3/lowlevel.c |   2 +-
 arch/arm/boards/qemu-virt64/init.c                 |  14 +-
 arch/arm/boards/radxa-rock/lowlevel.c              |   2 +-
 arch/arm/boards/raspberry-pi/lowlevel.c            |   4 +-
 arch/arm/boards/reflex-achilles/lowlevel.c         |   2 +-
 arch/arm/boards/solidrun-cubox/lowlevel.c          |   2 +-
 arch/arm/boards/solidrun-microsom/lowlevel.c       |  18 +-
 arch/arm/boards/technexion-pico-hobbit/lowlevel.c  |   2 +-
 arch/arm/boards/terasic-de0-nano-soc/lowlevel.c    |   2 +-
 arch/arm/boards/terasic-sockit/lowlevel.c          |   2 +-
 arch/arm/boards/tqma53/lowlevel.c                  |   4 +-
 arch/arm/boards/tqma6x/lowlevel.c                  |   4 +-
 arch/arm/boards/turris-omnia/lowlevel.c            |   2 +-
 arch/arm/boards/udoo/lowlevel.c                    |   2 +-
 arch/arm/boards/usi-topkick/lowlevel.c             |   2 +-
 arch/arm/boards/variscite-mx6/lowlevel.c           |   2 +-
 arch/arm/boards/vexpress/lowlevel.c                |   2 +-
 arch/arm/boards/vscom-baltos/lowlevel.c            |   2 +-
 arch/arm/boards/zii-imx6q-rdu2/lowlevel.c          |   4 +-
 arch/arm/boards/zii-vf610-dev/lowlevel.c           |   2 +-
 arch/arm/cpu/Makefile                              |  42 +---
 arch/arm/cpu/cache-armv4.S                         |   2 +-
 arch/arm/cpu/cache-armv8.S                         |  19 ++
 arch/arm/cpu/cache.c                               |  16 --
 arch/arm/cpu/cache_64.c                            |  35 +++
 arch/arm/cpu/common.c                              |  56 +++--
 arch/arm/cpu/cpu.c                                 |  37 ++-
 arch/arm/cpu/entry.c                               |   2 +-
 arch/arm/cpu/exceptions_64.S                       |  48 +++-
 arch/arm/cpu/interrupts.c                          |  48 +---
 arch/arm/cpu/interrupts_64.c                       | 198 +++++++++++++++
 arch/arm/cpu/lowlevel_64.S                         |  17 +-
 arch/arm/cpu/mmu-early.c                           |   4 +-
 arch/arm/cpu/mmu-early.h                           |   6 -
 arch/arm/cpu/mmu-early_64.c                        |  88 +++++++
 arch/arm/cpu/mmu.c                                 |  38 ++-
 arch/arm/cpu/mmu.h                                 |  54 -----
 arch/arm/cpu/mmu_64.c                              | 264 ++++++++++----------
 arch/arm/cpu/mmu_64.h                              | 121 ++++++++++
 arch/arm/cpu/no-mmu.c                              |   2 +-
 arch/arm/cpu/sections.c                            |  11 +
 arch/arm/cpu/setupc.S                              |  16 +-
 arch/arm/cpu/setupc_64.S                           |  58 +++++
 arch/arm/cpu/start-pbl.c                           |  14 +-
 arch/arm/cpu/start.c                               |   6 +-
 arch/arm/cpu/uncompress.c                          |  23 +-
 arch/arm/include/asm/assembler64.h                 |  21 ++
 arch/arm/include/asm/barebox-arm-head.h            |  13 +
 arch/arm/include/asm/barebox-arm.h                 |  41 +++-
 arch/arm/include/asm/barebox.h                     |   4 +-
 arch/arm/include/asm/bitops.h                      |  22 +-
 arch/arm/include/asm/cache.h                       |   9 +-
 arch/arm/include/asm/common.h                      |  10 +-
 arch/arm/include/asm/esr.h                         | 117 +++++++++
 arch/arm/include/asm/mmu.h                         |  19 +-
 arch/arm/include/asm/pgtable64.h                   |  77 +++---
 arch/arm/include/asm/ptrace.h                      |  19 ++
 arch/arm/include/asm/sections.h                    |  30 +--
 arch/arm/include/asm/stacktrace.h                  |   2 +
 arch/arm/lib/pbl.lds.S                             |  36 +--
 arch/arm/lib32/Makefile                            |   2 +
 arch/arm/lib32/barebox.lds.S                       |  23 +-
 arch/arm/{lib => lib32}/bootm.c                    |   4 +-
 arch/arm/{lib => lib32}/bootu.c                    |   0
 arch/arm/lib32/runtime-offset.S                    |  36 +--
 arch/arm/lib64/Makefile                            |   2 +
 arch/arm/lib64/armlinux.c                          | 120 ++++++++--
 arch/arm/lib64/barebox.lds.S                       |  38 +--
 arch/arm/lib64/runtime-offset.S                    |  19 ++
 arch/arm/lib64/stacktrace.c                        |  86 +++++++
 arch/arm/mach-imx/xload-common.c                   |   4 +-
 arch/arm/mach-mvebu/include/mach/common.h          |   4 +-
 arch/arm/mach-tegra/include/mach/lowlevel.h        |   2 +-
 arch/arm/mach-tegra/tegra_avp_init.c               |   2 +-
 arch/mips/lib/dma-default.c                        |   4 +-
 arch/openrisc/cpu/cpu.c                            |   5 -
 commands/Kconfig                                   |   4 +-
 common/Kconfig                                     |   2 +-
 common/bootm.c                                     |  10 +-
 common/filetype.c                                  |   3 +
 common/memory.c                                    |  51 ++++
 drivers/clocksource/Kconfig                        |   5 +
 drivers/clocksource/Makefile                       |   1 +
 drivers/clocksource/armv8-timer.c                  |  65 +++++
 include/bootm.h                                    |   7 +
 include/debug_ll.h                                 |   2 +-
 include/dma.h                                      |  16 +-
 include/dt-bindings/clock/tegra30-car.h            | 265 ---------------------
 include/dt-bindings/pinctrl/pinctrl-tegra.h        |  45 ----
 include/dt-bindings/pinctrl/rockchip.h             |  32 ---
 include/filetype.h                                 |   1 +
 include/memory.h                                   |   5 +
 136 files changed, 1611 insertions(+), 1106 deletions(-)
 create mode 100644 arch/arm/cpu/cache_64.c
 create mode 100644 arch/arm/cpu/interrupts_64.c
 delete mode 100644 arch/arm/cpu/mmu-early.h
 create mode 100644 arch/arm/cpu/mmu-early_64.c
 create mode 100644 arch/arm/cpu/mmu_64.h
 create mode 100644 arch/arm/cpu/sections.c
 create mode 100644 arch/arm/include/asm/assembler64.h
 create mode 100644 arch/arm/include/asm/esr.h
 rename arch/arm/{lib => lib32}/bootm.c (99%)
 rename arch/arm/{lib => lib32}/bootu.c (100%)
 create mode 100644 arch/arm/lib64/runtime-offset.S
 create mode 100644 arch/arm/lib64/stacktrace.c
 create mode 100644 drivers/clocksource/armv8-timer.c
 delete mode 100644 include/dt-bindings/clock/tegra30-car.h
 delete mode 100644 include/dt-bindings/pinctrl/pinctrl-tegra.h
 delete mode 100644 include/dt-bindings/pinctrl/rockchip.h

-- 
2.16.1



From s.hauer at pengutronix.de  Fri Mar 16 05:53:29 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 16 Mar 2018 13:53:29 +0100
Subject: [PATCH 53/78] ARM: aarch64: move aarch64 exception support to
 separate file
In-Reply-To: <20180316125354.23462-1-s.hauer@pengutronix.de>
References: <20180316125354.23462-1-s.hauer@pengutronix.de>
Message-ID: <20180316125354.23462-54-s.hauer@pengutronix.de>

The exception support for arm32 and aarch64 does not have much in
common. Move aarch64 exception support to a separate file to avoid
more ifdeffery.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/cpu/Makefile        |   3 +-
 arch/arm/cpu/interrupts.c    |  48 +-----------------
 arch/arm/cpu/interrupts_64.c | 116 +++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 118 insertions(+), 49 deletions(-)
 create mode 100644 arch/arm/cpu/interrupts_64.c

diff --git a/arch/arm/cpu/Makefile b/arch/arm/cpu/Makefile
index b2fed2be51..eb783481ea 100644
--- a/arch/arm/cpu/Makefile
+++ b/arch/arm/cpu/Makefile
@@ -1,6 +1,6 @@
 obj-y += cpu.o
 
-obj-$(CONFIG_ARM_EXCEPTIONS) += exceptions$(S64).o
+obj-$(CONFIG_ARM_EXCEPTIONS) += exceptions$(S64).o interrupts$(S64).o
 obj-$(CONFIG_MMU) += mmu$(S64).o
 lwl-y += lowlevel$(S64).o
 
@@ -8,7 +8,6 @@ ifeq ($(CONFIG_CPU_32), y)
 obj-pbl-$(CONFIG_MMU) += mmu-early.o
 endif
 
-obj-$(CONFIG_ARM_EXCEPTIONS) += interrupts.o
 obj-y += start.o entry.o
 
 obj-pbl-y += setupc$(S64).o
diff --git a/arch/arm/cpu/interrupts.c b/arch/arm/cpu/interrupts.c
index c34108a4f8..73f023bd71 100644
--- a/arch/arm/cpu/interrupts.c
+++ b/arch/arm/cpu/interrupts.c
@@ -26,9 +26,8 @@
 #include <abort.h>
 #include <asm/ptrace.h>
 #include <asm/unwind.h>
+#include <init.h>
 
-
-#if __LINUX_ARM_ARCH__ <= 7
 /**
  * Display current register set content
  * @param[in] regs Guess what
@@ -72,13 +71,10 @@ void show_regs (struct pt_regs *regs)
 	unwind_backtrace(regs);
 #endif
 }
-#endif
 
 static void __noreturn do_exception(struct pt_regs *pt_regs)
 {
-#if __LINUX_ARM_ARCH__ <= 7
 	show_regs(pt_regs);
-#endif
 
 	panic("");
 }
@@ -126,8 +122,6 @@ void do_prefetch_abort (struct pt_regs *pt_regs)
  */
 void do_data_abort (struct pt_regs *pt_regs)
 {
-
-#if __LINUX_ARM_ARCH__ <= 7
 	u32 far;
 
 	asm volatile ("mrc     p15, 0, %0, c6, c0, 0" : "=r" (far) : : "cc");
@@ -135,7 +129,6 @@ void do_data_abort (struct pt_regs *pt_regs)
 	printf("unable to handle %s at address 0x%08x\n",
 			far < PAGE_SIZE ? "NULL pointer dereference" :
 			"paging request", far);
-#endif
 
 	do_exception(pt_regs);
 }
@@ -164,45 +157,6 @@ void do_irq (struct pt_regs *pt_regs)
 	do_exception(pt_regs);
 }
 
-#ifdef CONFIG_CPU_64v8
-void do_bad_sync(struct pt_regs *pt_regs)
-{
-	printf("bad sync\n");
-	do_exception(pt_regs);
-}
-
-void do_bad_irq(struct pt_regs *pt_regs)
-{
-	printf("bad irq\n");
-	do_exception(pt_regs);
-}
-
-void do_bad_fiq(struct pt_regs *pt_regs)
-{
-	printf("bad fiq\n");
-	do_exception(pt_regs);
-}
-
-void do_bad_error(struct pt_regs *pt_regs)
-{
-	printf("bad error\n");
-	do_exception(pt_regs);
-}
-
-void do_sync(struct pt_regs *pt_regs)
-{
-	printf("sync exception\n");
-	do_exception(pt_regs);
-}
-
-
-void do_error(struct pt_regs *pt_regs)
-{
-	printf("error exception\n");
-	do_exception(pt_regs);
-}
-#endif
-
 extern volatile int arm_ignore_data_abort;
 extern volatile int arm_data_abort_occurred;
 
diff --git a/arch/arm/cpu/interrupts_64.c b/arch/arm/cpu/interrupts_64.c
new file mode 100644
index 0000000000..81fd941cfa
--- /dev/null
+++ b/arch/arm/cpu/interrupts_64.c
@@ -0,0 +1,116 @@
+/*
+ * interrupts_64.c - Interrupt Support Routines
+ *
+ * Copyright (c) 2018 Sascha Hauer <s.hauer at pengutronix.de>, Pengutronix
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <common.h>
+#include <abort.h>
+#include <asm/ptrace.h>
+#include <asm/unwind.h>
+#include <init.h>
+
+/**
+ * Display current register set content
+ * @param[in] regs Guess what
+ */
+void show_regs(struct pt_regs *regs)
+{
+}
+
+static void __noreturn do_exception(struct pt_regs *pt_regs)
+{
+	show_regs(pt_regs);
+
+	panic("");
+}
+
+/**
+ * The CPU catches a fast interrupt request.
+ * @param[in] pt_regs Register set content when the interrupt happens
+ *
+ * We never enable FIQs, so this should not happen
+ */
+void do_fiq(struct pt_regs *pt_regs)
+{
+	printf ("fast interrupt request\n");
+	do_exception(pt_regs);
+}
+
+/**
+ * The CPU catches a regular interrupt.
+ * @param[in] pt_regs Register set content when the interrupt happens
+ *
+ * We never enable interrupts, so this should not happen
+ */
+void do_irq(struct pt_regs *pt_regs)
+{
+	printf ("interrupt request\n");
+	do_exception(pt_regs);
+}
+
+void do_bad_sync(struct pt_regs *pt_regs)
+{
+	printf("bad sync\n");
+	do_exception(pt_regs);
+}
+
+void do_bad_irq(struct pt_regs *pt_regs)
+{
+	printf("bad irq\n");
+	do_exception(pt_regs);
+}
+
+void do_bad_fiq(struct pt_regs *pt_regs)
+{
+	printf("bad fiq\n");
+	do_exception(pt_regs);
+}
+
+void do_bad_error(struct pt_regs *pt_regs)
+{
+	printf("bad error\n");
+	do_exception(pt_regs);
+}
+
+void do_sync(struct pt_regs *pt_regs)
+{
+	printf("sync exception\n");
+	do_exception(pt_regs);
+}
+
+
+void do_error(struct pt_regs *pt_regs)
+{
+	printf("error exception\n");
+	do_exception(pt_regs);
+}
+
+extern volatile int arm_ignore_data_abort;
+extern volatile int arm_data_abort_occurred;
+
+void data_abort_mask(void)
+{
+	arm_data_abort_occurred = 0;
+	arm_ignore_data_abort = 1;
+}
+
+int data_abort_unmask(void)
+{
+	arm_ignore_data_abort = 0;
+
+	return arm_data_abort_occurred != 0;
+}
-- 
2.16.1



From s.hauer at pengutronix.de  Fri Mar 16 05:53:13 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 16 Mar 2018 13:53:13 +0100
Subject: [PATCH 37/78] ARM: aarch64: mmu: Fix mair register setting
In-Reply-To: <20180316125354.23462-1-s.hauer@pengutronix.de>
References: <20180316125354.23462-1-s.hauer@pengutronix.de>
Message-ID: <20180316125354.23462-38-s.hauer@pengutronix.de>

The memory attributes register contains the memory attribute settings
for the corresponding to the possible AttrIndx values in the page
table entries. Passing UNCACHED_MEM makes no sense here, pass the
desired attributes instead.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/cpu/mmu_64.c            | 5 +++--
 arch/arm/include/asm/pgtable64.h | 7 +++++++
 2 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/arch/arm/cpu/mmu_64.c b/arch/arm/cpu/mmu_64.c
index 27b5acd6a7..639aa6d189 100644
--- a/arch/arm/cpu/mmu_64.c
+++ b/arch/arm/cpu/mmu_64.c
@@ -243,7 +243,8 @@ static int mmu_init(void)
 
 		memset(ttb, 0, GRANULE_SIZE);
 
-		set_ttbr_tcr_mair(current_el(), (uint64_t)ttb, TCR_FLAGS, UNCACHED_MEM);
+		set_ttbr_tcr_mair(current_el(), (uint64_t)ttb, TCR_FLAGS,
+				  MEMORY_ATTRIBUTES);
 	}
 
 	pr_debug("ttb: 0x%p\n", ttb);
@@ -298,7 +299,7 @@ void mmu_early_enable(uint64_t membase, uint64_t memsize, uint64_t _ttb)
 
 	memset(ttb, 0, GRANULE_SIZE);
 
-	set_ttbr_tcr_mair(current_el(), (uint64_t)ttb, TCR_FLAGS, UNCACHED_MEM);
+	set_ttbr_tcr_mair(current_el(), (uint64_t)ttb, TCR_FLAGS, MEMORY_ATTRIBUTES);
 
 	create_sections(0, 0, 1UL << (BITS_PER_VA - 1), UNCACHED_MEM);
 
diff --git a/arch/arm/include/asm/pgtable64.h b/arch/arm/include/asm/pgtable64.h
index 20bea5b28a..7f7efa10ca 100644
--- a/arch/arm/include/asm/pgtable64.h
+++ b/arch/arm/include/asm/pgtable64.h
@@ -109,6 +109,13 @@
 #define MT_NORMAL		4
 #define MT_NORMAL_WT		5
 
+#define MEMORY_ATTRIBUTES ((0x00 << (MT_DEVICE_nGnRnE * 8))	| \
+			  (0x04 << (MT_DEVICE_nGnRE * 8)) 	| \
+			  (0x0c << (MT_DEVICE_GRE * 8)) 	| \
+			  (0x44 << (MT_NORMAL_NC * 8))		| \
+			  (UL(0xff) << (MT_NORMAL * 8))		| \
+			  (UL(0xbb) << (MT_NORMAL_WT * 8)))
+
 /*
  * TCR flags.
  */
-- 
2.16.1



From s.hauer at pengutronix.de  Fri Mar 16 05:53:38 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 16 Mar 2018 13:53:38 +0100
Subject: [PATCH 62/78] ARM: aarch64: Allow to leave exceptions
In-Reply-To: <20180316125354.23462-1-s.hauer@pengutronix.de>
References: <20180316125354.23462-1-s.hauer@pengutronix.de>
Message-ID: <20180316125354.23462-63-s.hauer@pengutronix.de>

So far exceptions can only be entered but never left. Add code to leave
exceptions based on U-Boot commit 4c2cc7c4e (arm64: Allow exceptions to return).
This will be useful to implement ignoring data aborts on a 'md' command.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/cpu/exceptions_64.S | 34 ++++++++++++++++++++++++++++++++++
 1 file changed, 34 insertions(+)

diff --git a/arch/arm/cpu/exceptions_64.S b/arch/arm/cpu/exceptions_64.S
index a7069a8475..58ca50b709 100644
--- a/arch/arm/cpu/exceptions_64.S
+++ b/arch/arm/cpu/exceptions_64.S
@@ -80,34 +80,68 @@ vectors:
 _do_bad_sync:
 	exception_entry
 	bl	do_bad_sync
+	b	exception_exit
 
 _do_bad_irq:
 	exception_entry
 	bl	do_bad_irq
+	b	exception_exit
 
 _do_bad_fiq:
 	exception_entry
 	bl	do_bad_fiq
+	b	exception_exit
 
 _do_bad_error:
 	exception_entry
 	bl	do_bad_error
+	b	exception_exit
 
 _do_sync:
 	exception_entry
 	bl	do_sync
+	b	exception_exit
 
 _do_irq:
 	exception_entry
 	bl	do_irq
+	b	exception_exit
 
 _do_fiq:
 	exception_entry
 	bl	do_fiq
+	b	exception_exit
 
 _do_error:
 	exception_entry
 	bl	do_error
+	b	exception_exit
+
+exception_exit:
+	ldp	x2, x0, [sp],#16
+	switch_el x11, 3f, 2f, 1f
+3:     	msr	elr_el3, x2
+	b	0f
+2:     	msr	elr_el2, x2
+	b	0f
+1:     	msr	elr_el1, x2
+0:
+	ldp	x1, x2, [sp],#16
+	ldp	x3, x4, [sp],#16
+	ldp	x5, x6, [sp],#16
+	ldp	x7, x8, [sp],#16
+	ldp	x9, x10, [sp],#16
+	ldp	x11, x12, [sp],#16
+	ldp	x13, x14, [sp],#16
+	ldp	x15, x16, [sp],#16
+	ldp	x17, x18, [sp],#16
+	ldp	x19, x20, [sp],#16
+	ldp	x21, x22, [sp],#16
+	ldp	x23, x24, [sp],#16
+	ldp	x25, x26, [sp],#16
+	ldp	x27, x28, [sp],#16
+	ldp	x29, x30, [sp],#16
+	eret
 
 .section .data
 .align 4
-- 
2.16.1



From s.hauer at pengutronix.de  Fri Mar 16 05:53:32 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 16 Mar 2018 13:53:32 +0100
Subject: [PATCH 56/78] ARM: aarch64: lowlevel: Use switch_el
In-Reply-To: <20180316125354.23462-1-s.hauer@pengutronix.de>
References: <20180316125354.23462-1-s.hauer@pengutronix.de>
Message-ID: <20180316125354.23462-57-s.hauer@pengutronix.de>

Use switch_el macro rather than open coded version. While at it rename the
labels so that the name matches the exception level.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/cpu/lowlevel_64.S | 13 ++++---------
 1 file changed, 4 insertions(+), 9 deletions(-)

diff --git a/arch/arm/cpu/lowlevel_64.S b/arch/arm/cpu/lowlevel_64.S
index a66556f1ad..af1cd8b5bc 100644
--- a/arch/arm/cpu/lowlevel_64.S
+++ b/arch/arm/cpu/lowlevel_64.S
@@ -1,18 +1,13 @@
 #include <linux/linkage.h>
 #include <init.h>
 #include <asm/system.h>
+#include <asm/assembler64.h>
 
 .section ".text_bare_init_","ax"
 ENTRY(arm_cpu_lowlevel_init)
-	mrs	x1, CurrentEL
-	cmp	x1, #0xC		/* Check EL3 state */
-	b.eq	1f
-	cmp	x1, #0x8		/* Check EL2 state */
-	b.eq	2f
-	cmp	x1, #0x4		/* Check EL1 state */
-	b.eq	3f
+	switch_el x1, 3f, 2f, 1f
 
-1:
+3:
 	mov	x0, #1			/* Non-Secure EL0/1 */
 	orr	x0, x0, #(1 << 10)	/* 64-bit EL2 */
 	msr	scr_el3, x0
@@ -25,7 +20,7 @@ ENTRY(arm_cpu_lowlevel_init)
 	b	done
 
 
-3:
+1:
 	mov	x0, #(3 << 20)		/* Enable FP/SIMD */
 	msr	cpacr_el1, x0
 	b	done
-- 
2.16.1



From s.hauer at pengutronix.de  Fri Mar 16 05:53:05 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 16 Mar 2018 13:53:05 +0100
Subject: [PATCH 29/78] clocksource: Add armv8 generic timer support
In-Reply-To: <20180316125354.23462-1-s.hauer@pengutronix.de>
References: <20180316125354.23462-1-s.hauer@pengutronix.de>
Message-ID: <20180316125354.23462-30-s.hauer@pengutronix.de>

armv8 has a generic time used in many SoCs. Add support for it.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 drivers/clocksource/Kconfig       |  5 +++
 drivers/clocksource/Makefile      |  1 +
 drivers/clocksource/armv8-timer.c | 65 +++++++++++++++++++++++++++++++++++++++
 3 files changed, 71 insertions(+)
 create mode 100644 drivers/clocksource/armv8-timer.c

diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index 23ad20afcf..3d63f7ff16 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -65,3 +65,8 @@ config CLOCKSOURCE_ROCKCHIP
 config CLOCKSOURCE_ATMEL_PIT
        bool
        depends on SOC_AT91SAM9 || SOC_SAMA5
+
+config CLOCKSOURCE_ARMV8_TIMER
+	bool
+	default y
+	depends on ARM && CPU_64v8
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index f774edee46..ea33fff502 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -11,3 +11,4 @@ obj-$(CONFIG_CLOCKSOURCE_ORION)   += orion.o
 obj-$(CONFIG_CLOCKSOURCE_UEMD)    += uemd.o
 obj-$(CONFIG_CLOCKSOURCE_ROCKCHIP)+= rk_timer.o
 obj-$(CONFIG_CLOCKSOURCE_ATMEL_PIT) += timer-atmel-pit.o
+obj-$(CONFIG_CLOCKSOURCE_ARMV8_TIMER) += armv8-timer.o
diff --git a/drivers/clocksource/armv8-timer.c b/drivers/clocksource/armv8-timer.c
new file mode 100644
index 0000000000..57b0b694c7
--- /dev/null
+++ b/drivers/clocksource/armv8-timer.c
@@ -0,0 +1,65 @@
+/*
+ * Copyright (C) 2018 Sascha Hauer <s.hauer at pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <common.h>
+#include <init.h>
+#include <clock.h>
+#include <linux/clk.h>
+#include <io.h>
+#include <asm/system.h>
+
+uint64_t armv8_clocksource_read(void)
+{
+	unsigned long cntpct;
+
+	isb();
+	asm volatile("mrs %0, cntpct_el0" : "=r" (cntpct));
+
+	return cntpct;
+}
+
+static struct clocksource cs = {
+	.read	= armv8_clocksource_read,
+	.mask	= CLOCKSOURCE_MASK(64),
+	.shift	= 0,
+};
+
+static int armv8_timer_probe(struct device_d *dev)
+{
+	unsigned long cntfrq;
+
+	asm volatile("mrs %0, cntfrq_el0" : "=r" (cntfrq));
+
+	cs.mult = clocksource_hz2mult(cntfrq, cs.shift);
+
+	return init_clock(&cs);
+}
+
+static struct of_device_id armv8_timer_dt_ids[] = {
+	{ .compatible = "arm,armv8-timer", },
+	{ }
+};
+
+static struct driver_d armv8_timer_driver = {
+	.name = "armv8-timer",
+	.probe = armv8_timer_probe,
+	.of_compatible = DRV_OF_COMPAT(armv8_timer_dt_ids),
+};
+
+static int armv8_timer_init(void)
+{
+	return platform_driver_register(&armv8_timer_driver);
+}
+postcore_initcall(armv8_timer_init);
-- 
2.16.1



From s.hauer at pengutronix.de  Fri Mar 16 05:53:30 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 16 Mar 2018 13:53:30 +0100
Subject: [PATCH 54/78] ARM: aarch64: fix exception level mixup
In-Reply-To: <20180316125354.23462-1-s.hauer@pengutronix.de>
References: <20180316125354.23462-1-s.hauer@pengutronix.de>
Message-ID: <20180316125354.23462-55-s.hauer@pengutronix.de>

When entering an exception the we currently jump to the code handling
EL1 when we are actually at EL3 and the other way round. Fix this by
introducing and using the switch_el macro from U-Boot.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/cpu/exceptions_64.S       | 10 ++--------
 arch/arm/include/asm/assembler64.h | 21 +++++++++++++++++++++
 2 files changed, 23 insertions(+), 8 deletions(-)
 create mode 100644 arch/arm/include/asm/assembler64.h

diff --git a/arch/arm/cpu/exceptions_64.S b/arch/arm/cpu/exceptions_64.S
index 58120253a1..a7069a8475 100644
--- a/arch/arm/cpu/exceptions_64.S
+++ b/arch/arm/cpu/exceptions_64.S
@@ -7,6 +7,7 @@
 
 #include <config.h>
 #include <asm/ptrace.h>
+#include <asm/assembler64.h>
 #include <linux/linkage.h>
 
 /*
@@ -31,14 +32,7 @@
 	stp	x3, x4, [sp, #-16]!
 	stp	x1, x2, [sp, #-16]!
 
-	/* Could be running at EL3/EL2/EL1 */
-	mrs	x11, CurrentEL
-	cmp	x11, #0xC		/* Check EL3 state */
-	b.eq	1f
-	cmp	x11, #0x8		/* Check EL2 state */
-	b.eq	2f
-	cmp	x11, #0x4		/* Check EL1 state */
-	b.eq	3f
+	switch_el x11, 3f, 2f, 1f
 3:	mrs	x1, esr_el3
 	mrs	x2, elr_el3
 	b	0f
diff --git a/arch/arm/include/asm/assembler64.h b/arch/arm/include/asm/assembler64.h
new file mode 100644
index 0000000000..26182aa5f6
--- /dev/null
+++ b/arch/arm/include/asm/assembler64.h
@@ -0,0 +1,21 @@
+#ifndef __ASM_ARCH_ASSEMBLY_H
+#define __ASM_ARCH_ASSEMBLY_H
+
+#ifndef __ASSEMBLY__
+#error "Only include this from assembly code"
+#endif
+
+/*
+ * Branch according to exception level
+ */
+.macro  switch_el, xreg, el3_label, el2_label, el1_label
+	mrs	\xreg, CurrentEL
+	cmp	\xreg, 0xc
+	b.eq	\el3_label
+	cmp	\xreg, 0x8
+	b.eq	\el2_label
+	cmp	\xreg, 0x4
+	b.eq	\el1_label
+.endm
+
+#endif /* __ASM_ARCH_ASSEMBLY_H */
\ No newline at end of file
-- 
2.16.1



From s.hauer at pengutronix.de  Fri Mar 16 05:52:49 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 16 Mar 2018 13:52:49 +0100
Subject: [PATCH 13/78] ARM: aarch64: Add dummy naked attribute
In-Reply-To: <20180316125354.23462-1-s.hauer@pengutronix.de>
References: <20180316125354.23462-1-s.hauer@pengutronix.de>
Message-ID: <20180316125354.23462-14-s.hauer@pengutronix.de>

The naked attribute is not supported on aarch64. To silence the compiler
warning add a dummy naked attribute.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/cpu/entry.c               |  2 +-
 arch/arm/cpu/start.c               |  4 ++--
 arch/arm/include/asm/barebox-arm.h | 17 +++++++++++++++--
 3 files changed, 18 insertions(+), 5 deletions(-)

diff --git a/arch/arm/cpu/entry.c b/arch/arm/cpu/entry.c
index 33b1429d4a..b48c1ca11d 100644
--- a/arch/arm/cpu/entry.c
+++ b/arch/arm/cpu/entry.c
@@ -24,7 +24,7 @@
  * be fine.
  */
 
-void __naked __noreturn barebox_arm_entry(unsigned long membase,
+void NAKED __noreturn barebox_arm_entry(unsigned long membase,
 					  unsigned long memsize, void *boarddata)
 {
 	arm_setup_stack(arm_mem_stack_top(membase, membase + memsize) - 16);
diff --git a/arch/arm/cpu/start.c b/arch/arm/cpu/start.c
index 171e6ad0eb..9f4213bfb9 100644
--- a/arch/arm/cpu/start.c
+++ b/arch/arm/cpu/start.c
@@ -229,7 +229,7 @@ __noreturn void barebox_non_pbl_start(unsigned long membase,
 
 #ifndef CONFIG_PBL_IMAGE
 
-void __naked __section(.text_entry) start(void)
+void NAKED __section(.text_entry) start(void)
 {
 	barebox_arm_head();
 }
@@ -239,7 +239,7 @@ void __naked __section(.text_entry) start(void)
  * First function in the uncompressed image. We get here from
  * the pbl. The stack already has been set up by the pbl.
  */
-void __naked __section(.text_entry) start(unsigned long membase,
+void NAKED __section(.text_entry) start(unsigned long membase,
 		unsigned long memsize, void *boarddata)
 {
 	barebox_non_pbl_start(membase, memsize, boarddata);
diff --git a/arch/arm/include/asm/barebox-arm.h b/arch/arm/include/asm/barebox-arm.h
index 3aea2e070e..170839aaad 100644
--- a/arch/arm/include/asm/barebox-arm.h
+++ b/arch/arm/include/asm/barebox-arm.h
@@ -161,13 +161,13 @@ static inline unsigned long arm_mem_barebox_image(unsigned long membase,
 #define ENTRY_FUNCTION(name, arg0, arg1, arg2)				\
 	static void __##name(uint32_t, uint32_t, uint32_t);		\
 									\
-	void __naked __section(.text_head_entry_##name)	name		\
+	void NAKED __section(.text_head_entry_##name)	name		\
 				(uint32_t r0, uint32_t r1, uint32_t r2)	\
 		{							\
 			__barebox_arm_head();				\
 			__##name(r0, r1, r2);				\
 		}							\
-		static void __naked noinline __##name			\
+		static void NAKED noinline __##name			\
 			(uint32_t arg0, uint32_t arg1, uint32_t arg2)
 
 /*
@@ -181,4 +181,17 @@ static inline unsigned long arm_mem_barebox_image(unsigned long membase,
 
 #define barebox_image_size (__image_end - __image_start)
 
+#ifdef CONFIG_CPU_32
+#define NAKED __naked
+#else
+/*
+ * There is no naked support for aarch64, so do not rely on it.
+ * This basically means we must have a stack configured when a
+ * function with the naked attribute is entered. On nowadays hardware
+ * the ROM should have some basic stack already. If not, set one
+ * up before jumping into the barebox entry functions.
+ */
+#define NAKED
+#endif
+
 #endif	/* _BAREBOX_ARM_H_ */
-- 
2.16.1



From s.hauer at pengutronix.de  Fri Mar 16 05:53:26 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 16 Mar 2018 13:53:26 +0100
Subject: [PATCH 50/78] ARM: implement dma mapping functions
In-Reply-To: <20180316125354.23462-1-s.hauer@pengutronix.de>
References: <20180316125354.23462-1-s.hauer@pengutronix.de>
Message-ID: <20180316125354.23462-51-s.hauer@pengutronix.de>

Implement basic dma mapping functions. For now just assume every address
is valid for dma mapping.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/cpu/mmu.c | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/arch/arm/cpu/mmu.c b/arch/arm/cpu/mmu.c
index fc71cf03cd..6ccd5893b4 100644
--- a/arch/arm/cpu/mmu.c
+++ b/arch/arm/cpu/mmu.c
@@ -598,3 +598,19 @@ void dma_sync_single_for_device(dma_addr_t address, size_t size,
 			outer_cache.clean_range(address, address + size);
 	}
 }
+
+dma_addr_t dma_map_single(struct device_d *dev, void *ptr, size_t size,
+			  enum dma_data_direction dir)
+{
+	unsigned long addr = (unsigned long)ptr;
+
+	dma_sync_single_for_device(addr, size, dir);
+
+	return addr;
+}
+
+void dma_unmap_single(struct device_d *dev, dma_addr_t addr, size_t size,
+		      enum dma_data_direction dir)
+{
+	dma_sync_single_for_cpu(addr, size, dir);
+}
-- 
2.16.1



From s.hauer at pengutronix.de  Fri Mar 16 05:53:27 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 16 Mar 2018 13:53:27 +0100
Subject: [PATCH 51/78] ARM: aarch64: implement dma operations
In-Reply-To: <20180316125354.23462-1-s.hauer@pengutronix.de>
References: <20180316125354.23462-1-s.hauer@pengutronix.de>
Message-ID: <20180316125354.23462-52-s.hauer@pengutronix.de>

For proper DMA support dma_alloc_coherent and DMA sync operations are
needed. Implement them.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/cpu/mmu_64.c | 55 +++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 55 insertions(+)

diff --git a/arch/arm/cpu/mmu_64.c b/arch/arm/cpu/mmu_64.c
index 6606405b21..20f6c387f3 100644
--- a/arch/arm/cpu/mmu_64.c
+++ b/arch/arm/cpu/mmu_64.c
@@ -365,3 +365,58 @@ void *phys_to_virt(unsigned long phys)
 {
 	return (void *)phys;
 }
+
+void *dma_alloc_coherent(size_t size, dma_addr_t *dma_handle)
+{
+	void *ret;
+
+	size = PAGE_ALIGN(size);
+	ret = xmemalign(PAGE_SIZE, size);
+	if (dma_handle)
+		*dma_handle = (dma_addr_t)ret;
+
+	map_region((unsigned long)ret, (unsigned long)ret, size, UNCACHED_MEM);
+	tlb_invalidate();
+
+	return ret;
+}
+
+void dma_free_coherent(void *mem, dma_addr_t dma_handle, size_t size)
+{
+	size = PAGE_ALIGN(size);
+
+	map_region((unsigned long)mem, (unsigned long)mem, size, CACHED_MEM);
+
+	free(mem);
+}
+
+void dma_sync_single_for_cpu(dma_addr_t address, size_t size,
+                             enum dma_data_direction dir)
+{
+	if (dir != DMA_TO_DEVICE)
+		v8_inv_dcache_range(address, address + size - 1);
+}
+
+void dma_sync_single_for_device(dma_addr_t address, size_t size,
+                                enum dma_data_direction dir)
+{
+	if (dir == DMA_FROM_DEVICE)
+		v8_inv_dcache_range(address, address + size - 1);
+	v8_flush_dcache_range(address, address + size - 1);
+}
+
+dma_addr_t dma_map_single(struct device_d *dev, void *ptr, size_t size,
+			  enum dma_data_direction dir)
+{
+	unsigned long addr = (unsigned long)ptr;
+
+	dma_sync_single_for_device(addr, size, dir);
+
+	return addr;
+}
+
+void dma_unmap_single(struct device_d *dev, dma_addr_t addr, size_t size,
+		      enum dma_data_direction dir)
+{
+	dma_sync_single_for_cpu(addr, size, dir);
+}
-- 
2.16.1



From s.hauer at pengutronix.de  Fri Mar 16 05:52:56 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 16 Mar 2018 13:52:56 +0100
Subject: [PATCH 20/78] ARM: Move mmu_disable to mmu.c
In-Reply-To: <20180316125354.23462-1-s.hauer@pengutronix.de>
References: <20180316125354.23462-1-s.hauer@pengutronix.de>
Message-ID: <20180316125354.23462-21-s.hauer@pengutronix.de>

mmu_64 has mmu_disable() in mmu_64.c. Move to mmu.c for the 32bit
case aswell to be consistent.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/cpu/cpu.c | 15 ---------------
 arch/arm/cpu/mmu.c | 13 +++++++++++++
 2 files changed, 13 insertions(+), 15 deletions(-)

diff --git a/arch/arm/cpu/cpu.c b/arch/arm/cpu/cpu.c
index 0e70a23260..c5daf6c60e 100644
--- a/arch/arm/cpu/cpu.c
+++ b/arch/arm/cpu/cpu.c
@@ -68,27 +68,12 @@ int icache_status(void)
 	return (get_cr () & CR_I) != 0;
 }
 
-#if __LINUX_ARM_ARCH__ <= 7
 /*
  * SoC like the ux500 have the l2x0 always enable
  * with or without MMU enable
  */
 struct outer_cache_fns outer_cache;
 
-/*
- * Clean and invalide caches, disable MMU
- */
-void mmu_disable(void)
-{
-	__mmu_cache_flush();
-	if (outer_cache.disable) {
-		outer_cache.flush_all();
-		outer_cache.disable();
-	}
-	__mmu_cache_off();
-}
-#endif
-
 static void disable_interrupts(void)
 {
 #if __LINUX_ARM_ARCH__ <= 7
diff --git a/arch/arm/cpu/mmu.c b/arch/arm/cpu/mmu.c
index 2c16579d79..27d994d452 100644
--- a/arch/arm/cpu/mmu.c
+++ b/arch/arm/cpu/mmu.c
@@ -511,6 +511,19 @@ static int mmu_init(void)
 }
 mmu_initcall(mmu_init);
 
+/*
+ * Clean and invalide caches, disable MMU
+ */
+void mmu_disable(void)
+{
+	__mmu_cache_flush();
+	if (outer_cache.disable) {
+		outer_cache.flush_all();
+		outer_cache.disable();
+	}
+	__mmu_cache_off();
+}
+
 void *dma_alloc_coherent(size_t size, dma_addr_t *dma_handle)
 {
 	void *ret;
-- 
2.16.1



From s.hauer at pengutronix.de  Fri Mar 16 05:53:43 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 16 Mar 2018 13:53:43 +0100
Subject: [PATCH 67/78] ARM: aarch64: Add barebox head support
In-Reply-To: <20180316125354.23462-1-s.hauer@pengutronix.de>
References: <20180316125354.23462-1-s.hauer@pengutronix.de>
Message-ID: <20180316125354.23462-68-s.hauer@pengutronix.de>

Allow aarch64 images to use the same image header as arm32 images.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/include/asm/barebox-arm-head.h | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/arm/include/asm/barebox-arm-head.h b/arch/arm/include/asm/barebox-arm-head.h
index bd9c9b1c4f..4d0da6c491 100644
--- a/arch/arm/include/asm/barebox-arm-head.h
+++ b/arch/arm/include/asm/barebox-arm-head.h
@@ -21,6 +21,7 @@ void cortex_a7_lowlevel_init(void);
 static inline void __barebox_arm_head(void)
 {
 	__asm__ __volatile__ (
+#ifdef CONFIG_CPU_32
 #ifdef CONFIG_THUMB2_BAREBOX
 		".arm\n"
 		"adr r9, 1f + 1\n"
@@ -40,11 +41,23 @@ static inline void __barebox_arm_head(void)
 		"1: b 1b\n"
 		"1: b 1b\n"
 		"1: b 1b\n"
+#endif
+#else
+		"b 2f\n"
+		"nop\n"
+		"nop\n"
+		"nop\n"
+		"nop\n"
+		"nop\n"
 #endif
 		".asciz \"barebox\"\n"
+#ifdef CONFIG_CPU_32
 		".word _text\n"				/* text base. If copied there,
 							 * barebox can skip relocation
 							 */
+#else
+		".word 0xffffffff\n"
+#endif
 		".word _barebox_image_size\n"		/* image size to copy */
 		".rept 8\n"
 		".word 0x55555555\n"
-- 
2.16.1



From s.hauer at pengutronix.de  Fri Mar 16 05:52:58 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 16 Mar 2018 13:52:58 +0100
Subject: [PATCH 22/78] ARM: aarch64: fix early cache flushing
In-Reply-To: <20180316125354.23462-1-s.hauer@pengutronix.de>
References: <20180316125354.23462-1-s.hauer@pengutronix.de>
Message-ID: <20180316125354.23462-23-s.hauer@pengutronix.de>

v8_dcache_all() should not be used directly, but only called from
v8_flush_dcache_all() and v8_invalidate_dcache_all() which set
pass the type of operation in x0. While at it add the missing prototype
for v8_invalidate_dcache_all().

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/cpu/cache.c         | 2 +-
 arch/arm/include/asm/cache.h | 3 ++-
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/arch/arm/cpu/cache.c b/arch/arm/cpu/cache.c
index 929c385df5..1a8f49d301 100644
--- a/arch/arm/cpu/cache.c
+++ b/arch/arm/cpu/cache.c
@@ -146,7 +146,7 @@ void arm_early_mmu_cache_flush(void)
 #endif
 #ifdef CONFIG_CPU_64v8
 	case CPU_ARCH_ARMv8:
-		v8_dcache_all();
+		v8_flush_dcache_all();
 		return;
 #endif
 	}
diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h
index b5460a7876..406a9d5d99 100644
--- a/arch/arm/include/asm/cache.h
+++ b/arch/arm/include/asm/cache.h
@@ -3,7 +3,8 @@
 
 #ifdef CONFIG_CPU_64v8
 extern void v8_invalidate_icache_all(void);
-extern void v8_dcache_all(void);
+void v8_flush_dcache_all(void);
+void v8_invalidate_dcache_all(void);
 #endif
 
 static inline void icache_invalidate(void)
-- 
2.16.1



From s.hauer at pengutronix.de  Fri Mar 16 05:53:34 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 16 Mar 2018 13:53:34 +0100
Subject: [PATCH 58/78] ARM: aarch64: hide some config options
In-Reply-To: <20180316125354.23462-1-s.hauer@pengutronix.de>
References: <20180316125354.23462-1-s.hauer@pengutronix.de>
Message-ID: <20180316125354.23462-59-s.hauer@pengutronix.de>

EABI and ATAGS have no meaning on aarch64, so hide the options from the
user.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/Kconfig | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 563475205d..37cde0c0c5 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -286,6 +286,7 @@ config ARM_ASM_UNIFIED
 
 config AEABI
 	bool "Use the ARM EABI to compile barebox"
+	depends on !CPU_V8
 	help
 	  This option allows for barebox to be compiled using the latest
 	  ARM ABI (aka EABI).
@@ -308,7 +309,7 @@ config THUMB2_BAREBOX
 
 config ARM_BOARD_APPEND_ATAG
 	bool "Let board specific code to add ATAGs to be passed to the kernel"
-	depends on ARM_LINUX
+	depends on ARM_LINUX && !CPU_V8
 	help
 	  This option is purely to start some vendor provided kernels.
 	  ** DO NOT USE FOR YOUR OWN DESIGNS! **
-- 
2.16.1



From s.hauer at pengutronix.de  Fri Mar 16 05:53:36 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 16 Mar 2018 13:53:36 +0100
Subject: [PATCH 60/78] ARM: aarch64: implement stacktraces
In-Reply-To: <20180316125354.23462-1-s.hauer@pengutronix.de>
References: <20180316125354.23462-1-s.hauer@pengutronix.de>
Message-ID: <20180316125354.23462-61-s.hauer@pengutronix.de>

Implement stacktraces as a great debugging aid. On aarch64 this is cheap
enough to be enabled unconditionally. Unwinding code is taken from the
Kernel.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/cpu/interrupts_64.c      |  4 +-
 arch/arm/include/asm/barebox.h    |  4 +-
 arch/arm/include/asm/stacktrace.h |  2 +
 arch/arm/lib64/Makefile           |  1 +
 arch/arm/lib64/stacktrace.c       | 86 +++++++++++++++++++++++++++++++++++++++
 5 files changed, 95 insertions(+), 2 deletions(-)
 create mode 100644 arch/arm/lib64/stacktrace.c

diff --git a/arch/arm/cpu/interrupts_64.c b/arch/arm/cpu/interrupts_64.c
index ffdb87af94..9ed6ed9761 100644
--- a/arch/arm/cpu/interrupts_64.c
+++ b/arch/arm/cpu/interrupts_64.c
@@ -44,7 +44,9 @@ static void __noreturn do_exception(struct pt_regs *pt_regs)
 {
 	show_regs(pt_regs);
 
-	panic("");
+	unwind_backtrace(pt_regs);
+
+	panic("panic: unhandled exception");
 }
 
 /**
diff --git a/arch/arm/include/asm/barebox.h b/arch/arm/include/asm/barebox.h
index 5a6622235b..4e89466593 100644
--- a/arch/arm/include/asm/barebox.h
+++ b/arch/arm/include/asm/barebox.h
@@ -2,9 +2,11 @@
 #define _BAREBOX_H_	1
 
 #ifdef CONFIG_ARM_UNWIND
-#ifndef CONFIG_CPU_V8
 #define ARCH_HAS_STACK_DUMP
 #endif
+
+#ifdef CONFIG_CPU_V8
+#define ARCH_HAS_STACK_DUMP
 #endif
 
 #ifdef CONFIG_ARM_EXCEPTIONS
diff --git a/arch/arm/include/asm/stacktrace.h b/arch/arm/include/asm/stacktrace.h
index 10f70e1675..602e79ced4 100644
--- a/arch/arm/include/asm/stacktrace.h
+++ b/arch/arm/include/asm/stacktrace.h
@@ -4,7 +4,9 @@
 struct stackframe {
 	unsigned long fp;
 	unsigned long sp;
+#ifdef CONFIG_CPU_32
 	unsigned long lr;
+#endif
 	unsigned long pc;
 };
 
diff --git a/arch/arm/lib64/Makefile b/arch/arm/lib64/Makefile
index 679ca556e5..77647128a5 100644
--- a/arch/arm/lib64/Makefile
+++ b/arch/arm/lib64/Makefile
@@ -1,3 +1,4 @@
+obj-y += stacktrace.o
 obj-$(CONFIG_ARM_LINUX)	+= armlinux.o
 obj-y	+= div0.o
 obj-$(CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS)	+= memcpy.o
diff --git a/arch/arm/lib64/stacktrace.c b/arch/arm/lib64/stacktrace.c
new file mode 100644
index 0000000000..b8352c1454
--- /dev/null
+++ b/arch/arm/lib64/stacktrace.c
@@ -0,0 +1,86 @@
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ */
+
+#include <common.h>
+#include <asm/stacktrace.h>
+
+#define THREAD_SIZE 16384
+
+/*
+ * AArch64 PCS assigns the frame pointer to x29.
+ *
+ * A simple function prologue looks like this:
+ * 	sub	sp, sp, #0x10
+ *   	stp	x29, x30, [sp]
+ *	mov	x29, sp
+ *
+ * A simple function epilogue looks like this:
+ *	mov	sp, x29
+ *	ldp	x29, x30, [sp]
+ *	add	sp, sp, #0x10
+ */
+int unwind_frame(struct stackframe *frame)
+{
+	unsigned long high, low;
+	unsigned long fp = frame->fp;
+
+	low  = frame->sp;
+	high = ALIGN(low, THREAD_SIZE);
+
+	if (fp < low || fp > high - 0x18 || fp & 0xf)
+		return -EINVAL;
+
+	frame->sp = fp + 0x10;
+	frame->fp = *(unsigned long *)(fp);
+	frame->pc = *(unsigned long *)(fp + 8);
+
+	return 0;
+}
+
+void dump_backtrace_entry(unsigned long where, unsigned long from)
+{
+#ifdef CONFIG_KALLSYMS
+	printf("[<%08lx>] (%pS) from [<%08lx>] (%pS)\n", where, (void *)where, from, (void *)from);
+#else
+	printf("Function entered at [<%08lx>] from [<%08lx>]\n", where, from);
+#endif
+}
+
+void unwind_backtrace(struct pt_regs *regs)
+{
+        struct stackframe frame = {};
+	register unsigned long current_sp asm ("sp");
+
+	if (regs) {
+		frame.fp = regs->regs[29];
+		frame.pc = regs->elr;
+	} else {
+		frame.fp = (unsigned long)__builtin_frame_address(0);
+		frame.sp = current_sp;
+		frame.pc = (unsigned long)unwind_backtrace;
+	}
+
+	printf("Call trace:\n");
+	while (1) {
+		unsigned long where = frame.pc;
+		int ret;
+
+		ret = unwind_frame(&frame);
+		if (ret < 0)
+			break;
+		dump_backtrace_entry(where, frame.pc);
+	}
+}
+
+void dump_stack(void)
+{
+	unwind_backtrace(NULL);
+}
-- 
2.16.1



From s.hauer at pengutronix.de  Fri Mar 16 05:53:02 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 16 Mar 2018 13:53:02 +0100
Subject: [PATCH 26/78] ARM: remove function prototypes from the past
In-Reply-To: <20180316125354.23462-1-s.hauer@pengutronix.de>
References: <20180316125354.23462-1-s.hauer@pengutronix.de>
Message-ID: <20180316125354.23462-27-s.hauer@pengutronix.de>

Several functions do not exist anymore for a long time now. Remove their
prototypes.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/include/asm/barebox-arm.h | 8 --------
 arch/openrisc/cpu/cpu.c            | 5 -----
 2 files changed, 13 deletions(-)

diff --git a/arch/arm/include/asm/barebox-arm.h b/arch/arm/include/asm/barebox-arm.h
index 9fc8afbe7d..6c7507a9c7 100644
--- a/arch/arm/include/asm/barebox-arm.h
+++ b/arch/arm/include/asm/barebox-arm.h
@@ -32,16 +32,8 @@
 #include <linux/compiler.h>
 #include <asm/barebox-arm-head.h>
 
-/* cpu/.../cpu.c */
-int	cleanup_before_linux(void);
-
-/* arch/<arch>board(s)/.../... */
-int	board_init(void);
-int	dram_init (void);
-
 extern char __exceptions_start[], __exceptions_stop[];
 
-void board_init_lowlevel(void);
 unsigned long get_runtime_offset(void);
 
 /* global_variable_offset() - Access global variables when not running at link address
diff --git a/arch/openrisc/cpu/cpu.c b/arch/openrisc/cpu/cpu.c
index e7f944555e..cae42d41b8 100644
--- a/arch/openrisc/cpu/cpu.c
+++ b/arch/openrisc/cpu/cpu.c
@@ -23,11 +23,6 @@
 #include <asm/system.h>
 #include <asm/openrisc_exc.h>
 
-int cleanup_before_linux(void)
-{
-	return 0;
-}
-
 extern void __reset(void);
 
 static void __noreturn openrisc_restart_cpu(struct restart_handler *rst)
-- 
2.16.1



From s.hauer at pengutronix.de  Fri Mar 16 05:53:53 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 16 Mar 2018 13:53:53 +0100
Subject: [PATCH 77/78] ARM: change mmu_early_enable() prototype
In-Reply-To: <20180316125354.23462-1-s.hauer@pengutronix.de>
References: <20180316125354.23462-1-s.hauer@pengutronix.de>
Message-ID: <20180316125354.23462-78-s.hauer@pengutronix.de>

Change the arguements to type unsigned long which is suitable for both
arm32 and arm64. While at it move the prototype to arch/arm/include/.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/cpu/mmu-early.c   | 3 ++-
 arch/arm/cpu/mmu-early.h   | 6 ------
 arch/arm/cpu/mmu_64.c      | 3 ++-
 arch/arm/cpu/start-pbl.c   | 3 +--
 arch/arm/cpu/start.c       | 2 +-
 arch/arm/cpu/uncompress.c  | 3 +--
 arch/arm/include/asm/mmu.h | 3 +++
 7 files changed, 10 insertions(+), 13 deletions(-)
 delete mode 100644 arch/arm/cpu/mmu-early.h

diff --git a/arch/arm/cpu/mmu-early.c b/arch/arm/cpu/mmu-early.c
index 1549f08985..70cb5fe31b 100644
--- a/arch/arm/cpu/mmu-early.c
+++ b/arch/arm/cpu/mmu-early.c
@@ -30,7 +30,8 @@ static void map_cachable(unsigned long start, unsigned long size)
 			PMD_SECT_AP_READ | PMD_TYPE_SECT | PMD_SECT_WB);
 }
 
-void mmu_early_enable(uint32_t membase, uint32_t memsize, uint32_t _ttb)
+void mmu_early_enable(unsigned long membase, unsigned long memsize,
+		      unsigned long _ttb)
 {
 	int i;
 
diff --git a/arch/arm/cpu/mmu-early.h b/arch/arm/cpu/mmu-early.h
deleted file mode 100644
index af21f52131..0000000000
--- a/arch/arm/cpu/mmu-early.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __ARM_CPU_MMU_EARLY_H
-#define __ARM_CPU_MMU_EARLY_H
-
-void mmu_early_enable(uint32_t membase, uint32_t memsize, uint32_t ttb);
-
-#endif /* __ARM_CPU_MMU_EARLY_H */
diff --git a/arch/arm/cpu/mmu_64.c b/arch/arm/cpu/mmu_64.c
index 7f29ae7623..31658de910 100644
--- a/arch/arm/cpu/mmu_64.c
+++ b/arch/arm/cpu/mmu_64.c
@@ -339,7 +339,8 @@ void mmu_disable(void)
 	isb();
 }
 
-void mmu_early_enable(uint64_t membase, uint64_t memsize, uint64_t _ttb)
+void mmu_early_enable(unsigned long membase, unsigned long memsize,
+		      unsigned long _ttb)
 {
 	int el;
 
diff --git a/arch/arm/cpu/start-pbl.c b/arch/arm/cpu/start-pbl.c
index 25f91b02f3..16159d7f9d 100644
--- a/arch/arm/cpu/start-pbl.c
+++ b/arch/arm/cpu/start-pbl.c
@@ -27,10 +27,9 @@
 #include <asm-generic/memory_layout.h>
 #include <asm/sections.h>
 #include <asm/cache.h>
+#include <asm/mmu.h>
 #include <asm/unaligned.h>
 
-#include "mmu-early.h"
-
 unsigned long free_mem_ptr;
 unsigned long free_mem_end_ptr;
 
diff --git a/arch/arm/cpu/start.c b/arch/arm/cpu/start.c
index 9f4213bfb9..68fff892e8 100644
--- a/arch/arm/cpu/start.c
+++ b/arch/arm/cpu/start.c
@@ -26,12 +26,12 @@
 #include <asm/sections.h>
 #include <asm/unaligned.h>
 #include <asm/cache.h>
+#include <asm/mmu.h>
 #include <memory.h>
 #include <uncompress.h>
 #include <malloc.h>
 
 #include <debug_ll.h>
-#include "mmu-early.h"
 
 unsigned long arm_stack_top;
 static unsigned long arm_barebox_size;
diff --git a/arch/arm/cpu/uncompress.c b/arch/arm/cpu/uncompress.c
index c721eef0ad..b07087e4cf 100644
--- a/arch/arm/cpu/uncompress.c
+++ b/arch/arm/cpu/uncompress.c
@@ -28,12 +28,11 @@
 #include <asm-generic/memory_layout.h>
 #include <asm/sections.h>
 #include <asm/cache.h>
+#include <asm/mmu.h>
 #include <asm/unaligned.h>
 
 #include <debug_ll.h>
 
-#include "mmu-early.h"
-
 unsigned long free_mem_ptr;
 unsigned long free_mem_end_ptr;
 
diff --git a/arch/arm/include/asm/mmu.h b/arch/arm/include/asm/mmu.h
index 840851858f..99833ac5b4 100644
--- a/arch/arm/include/asm/mmu.h
+++ b/arch/arm/include/asm/mmu.h
@@ -54,4 +54,7 @@ void __dma_clean_range(unsigned long, unsigned long);
 void __dma_flush_range(unsigned long, unsigned long);
 void __dma_inv_range(unsigned long, unsigned long);
 
+void mmu_early_enable(unsigned long membase, unsigned long memsize,
+		      unsigned long ttb);
+
 #endif /* __ASM_MMU_H */
-- 
2.16.1



From s.hauer at pengutronix.de  Fri Mar 16 05:52:48 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 16 Mar 2018 13:52:48 +0100
Subject: [PATCH 12/78] ARM: aarch64: silence compiler warning
In-Reply-To: <20180316125354.23462-1-s.hauer@pengutronix.de>
References: <20180316125354.23462-1-s.hauer@pengutronix.de>
Message-ID: <20180316125354.23462-13-s.hauer@pengutronix.de>

find_pte is currently unused, nevertheless it's useful for debugging
purposes. Add a __maybe_unused to silence the compiler warning.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/cpu/mmu_64.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/cpu/mmu_64.c b/arch/arm/cpu/mmu_64.c
index fd41435746..4803a85e4c 100644
--- a/arch/arm/cpu/mmu_64.c
+++ b/arch/arm/cpu/mmu_64.c
@@ -130,7 +130,7 @@ static uint64_t *get_level_table(uint64_t *pte)
 	return table;
 }
 
-static uint64_t *find_pte(uint64_t addr)
+static __maybe_unused uint64_t *find_pte(uint64_t addr)
 {
 	uint64_t *pte;
 	uint64_t block_shift;
-- 
2.16.1



From s.hauer at pengutronix.de  Fri Mar 16 05:53:25 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 16 Mar 2018 13:53:25 +0100
Subject: [PATCH 49/78] dma: Add prototypes for dma mapping functions
In-Reply-To: <20180316125354.23462-1-s.hauer@pengutronix.de>
References: <20180316125354.23462-1-s.hauer@pengutronix.de>
Message-ID: <20180316125354.23462-50-s.hauer@pengutronix.de>

Right now we only have the dma_sync_single_* functions, but no functions
for actually mapping a pointer. The mapping functions become necessary
when casting a pointer to unsigned long to get a dma address is not
enough. (I'm not even going so far that we'll add IOMMU support, but on
some architectures we need a place where we can check if a pointer is
DMA mappable at all)

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 include/dma.h | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/include/dma.h b/include/dma.h
index 29d94c0a52..5fdcb1733c 100644
--- a/include/dma.h
+++ b/include/dma.h
@@ -30,6 +30,18 @@ static inline void dma_free(void *mem)
 }
 #endif
 
+dma_addr_t dma_map_single(struct device_d *dev, void *ptr, size_t size,
+			  enum dma_data_direction dir);
+void dma_unmap_single(struct device_d *dev, dma_addr_t addr, size_t size,
+		      enum dma_data_direction dir);
+
+#define DMA_ERROR_CODE  (~(dma_addr_t)0)
+
+static inline int dma_mapping_error(struct device_d *dev, dma_addr_t dma_addr)
+{
+	return dma_addr == DMA_ERROR_CODE;
+}
+
 /* streaming DMA - implement the below calls to support HAS_DMA */
 void dma_sync_single_for_cpu(dma_addr_t address, size_t size,
 			     enum dma_data_direction dir);
-- 
2.16.1



From s.hauer at pengutronix.de  Fri Mar 16 05:53:54 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 16 Mar 2018 13:53:54 +0100
Subject: [PATCH 78/78] ARM: aarch64: Make early MMU support work
In-Reply-To: <20180316125354.23462-1-s.hauer@pengutronix.de>
References: <20180316125354.23462-1-s.hauer@pengutronix.de>
Message-ID: <20180316125354.23462-79-s.hauer@pengutronix.de>

Until now it was not possible to enable the MMU in PBL because
create_section needs memory allocations which are not available. With
this patch we move the early MMU support to a separate file and all
necessary aux functions to mmu_64.h. create_sections is reimplmented
for the early case to only create 1st level pagetables.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/cpu/Makefile       |   5 +-
 arch/arm/cpu/mmu-early_64.c |  88 +++++++++++++++++++++++++++++
 arch/arm/cpu/mmu_64.c       | 134 +++-----------------------------------------
 arch/arm/cpu/mmu_64.h       |  84 +++++++++++++++++++++++++++
 4 files changed, 182 insertions(+), 129 deletions(-)
 create mode 100644 arch/arm/cpu/mmu-early_64.c

diff --git a/arch/arm/cpu/Makefile b/arch/arm/cpu/Makefile
index f79cedd085..0316d251c0 100644
--- a/arch/arm/cpu/Makefile
+++ b/arch/arm/cpu/Makefile
@@ -3,10 +3,7 @@ obj-y += cpu.o
 obj-$(CONFIG_ARM_EXCEPTIONS) += exceptions$(S64).o interrupts$(S64).o
 obj-$(CONFIG_MMU) += mmu$(S64).o
 lwl-y += lowlevel$(S64).o
-
-ifeq ($(CONFIG_CPU_32), y)
-obj-pbl-$(CONFIG_MMU) += mmu-early.o
-endif
+obj-pbl-$(CONFIG_MMU) += mmu-early$(S64).o
 
 obj-y += start.o entry.o
 
diff --git a/arch/arm/cpu/mmu-early_64.c b/arch/arm/cpu/mmu-early_64.c
new file mode 100644
index 0000000000..f07d107e0d
--- /dev/null
+++ b/arch/arm/cpu/mmu-early_64.c
@@ -0,0 +1,88 @@
+#include <common.h>
+#include <dma-dir.h>
+#include <init.h>
+#include <mmu.h>
+#include <errno.h>
+#include <linux/sizes.h>
+#include <asm/memory.h>
+#include <asm/pgtable64.h>
+#include <asm/barebox-arm.h>
+#include <asm/system.h>
+#include <asm/cache.h>
+#include <memory.h>
+#include <asm/system_info.h>
+
+#include "mmu_64.h"
+
+static void create_sections(void *ttb, uint64_t virt, uint64_t phys,
+			    uint64_t size, uint64_t attr)
+{
+	uint64_t block_size;
+	uint64_t block_shift;
+	uint64_t *pte;
+	uint64_t idx;
+	uint64_t addr;
+	uint64_t *table;
+
+	addr = virt;
+
+	attr &= ~PTE_TYPE_MASK;
+
+	table = ttb;
+
+	while (1) {
+		block_shift = level2shift(1);
+		idx = (addr & level2mask(1)) >> block_shift;
+		block_size = (1ULL << block_shift);
+
+		pte = table + idx;
+
+		*pte = phys | attr | PTE_TYPE_BLOCK;
+
+		if (size < block_size)
+			break;
+
+		addr += block_size;
+		phys += block_size;
+		size -= block_size;
+	}
+}
+
+void mmu_early_enable(unsigned long membase, unsigned long memsize,
+		      unsigned long ttb)
+{
+	int el;
+
+	/*
+	 * For the early code we only create level 1 pagetables which only
+	 * allow for a 1GiB granularity. If our membase is not aligned to that
+	 * bail out without enabling the MMU.
+	 */
+	if (membase & ((1ULL << level2shift(1)) - 1))
+		return;
+
+	memset((void *)ttb, 0, GRANULE_SIZE);
+
+	el = current_el();
+	set_ttbr_tcr_mair(el, ttb, calc_tcr(el), MEMORY_ATTRIBUTES);
+	create_sections((void *)ttb, 0, 0, 1UL << (BITS_PER_VA - 1), UNCACHED_MEM);
+	create_sections((void *)ttb, membase, membase, memsize, CACHED_MEM);
+	tlb_invalidate();
+	isb();
+	set_cr(get_cr() | CR_M);
+}
+
+void mmu_early_disable(void)
+{
+	unsigned int cr;
+
+	cr = get_cr();
+	cr &= ~(CR_M | CR_C);
+
+	set_cr(cr);
+	v8_flush_dcache_all();
+	tlb_invalidate();
+
+	dsb();
+	isb();
+}
\ No newline at end of file
diff --git a/arch/arm/cpu/mmu_64.c b/arch/arm/cpu/mmu_64.c
index 31658de910..8355a4c6e8 100644
--- a/arch/arm/cpu/mmu_64.c
+++ b/arch/arm/cpu/mmu_64.c
@@ -34,13 +34,6 @@
 
 #include "mmu_64.h"
 
-#define CACHED_MEM      (PTE_BLOCK_MEMTYPE(MT_NORMAL) | \
-			 PTE_BLOCK_OUTER_SHARE | \
-			 PTE_BLOCK_AF)
-#define UNCACHED_MEM    (PTE_BLOCK_MEMTYPE(MT_DEVICE_nGnRnE) | \
-			 PTE_BLOCK_OUTER_SHARE | \
-			 PTE_BLOCK_AF)
-
 static uint64_t *ttb;
 
 static void arm_mmu_not_initialized_error(void)
@@ -54,74 +47,6 @@ static void arm_mmu_not_initialized_error(void)
 	panic("MMU not initialized\n");
 }
 
-static uint64_t calc_tcr(int el)
-{
-	u64 ips, va_bits;
-	u64 tcr;
-
-	ips = 2;
-	va_bits = BITS_PER_VA;
-
-	if (el == 1)
-		tcr = (ips << 32) | TCR_EPD1_DISABLE;
-	else if (el == 2)
-		tcr = (ips << 16);
-	else
-		tcr = (ips << 16);
-
-	/* PTWs cacheable, inner/outer WBWA and inner shareable */
-	tcr |= TCR_TG0_4K | TCR_SHARED_INNER | TCR_ORGN_WBWA | TCR_IRGN_WBWA;
-	tcr |= TCR_T0SZ(va_bits);
-
-	return tcr;
-}
-
-/*
- * Do it the simple way for now and invalidate the entire
- * tlb
- */
-static inline void tlb_invalidate(void)
-{
-	unsigned int el = current_el();
-
-	dsb();
-
-	if (el == 1)
-		__asm__ __volatile__("tlbi vmalle1\n\t" : : : "memory");
-	else if (el == 2)
-		__asm__ __volatile__("tlbi alle2\n\t" : : : "memory");
-	else if (el == 3)
-		__asm__ __volatile__("tlbi alle3\n\t" : : : "memory");
-
-	dsb();
-	isb();
-}
-
-static int level2shift(int level)
-{
-	/* Page is 12 bits wide, every level translates 9 bits */
-	return (12 + 9 * (3 - level));
-}
-
-static uint64_t level2mask(int level)
-{
-	uint64_t mask = -EINVAL;
-
-	if (level == 1)
-		mask = L1_ADDR_MASK;
-	else if (level == 2)
-		mask = L2_ADDR_MASK;
-	else if (level == 3)
-		mask = L3_ADDR_MASK;
-
-	return mask;
-}
-
-static int pte_type(uint64_t *pte)
-{
-	return *pte & PTE_TYPE_MASK;
-}
-
 static void set_table(uint64_t *pt, uint64_t *table_addr)
 {
 	uint64_t val;
@@ -140,16 +65,6 @@ static uint64_t *create_table(void)
 	return new_table;
 }
 
-static uint64_t *get_level_table(uint64_t *pte)
-{
-	uint64_t *table = (uint64_t *)(*pte & XLAT_ADDR_MASK);
-
-	if (pte_type(pte) != PTE_TYPE_TABLE)
-		BUG();
-
-	return table;
-}
-
 static __maybe_unused uint64_t *find_pte(uint64_t addr)
 {
 	uint64_t *pte;
@@ -286,26 +201,15 @@ static int mmu_init(void)
 		 */
 		panic("MMU: No memory bank found! Cannot continue\n");
 
-	if (get_cr() & CR_M) {
-		ttb = (uint64_t *)get_ttbr(current_el());
-		if (!request_sdram_region("ttb", (unsigned long)ttb, SZ_16K))
-			/*
-			* This can mean that:
-			* - the early MMU code has put the ttb into a place
-			*   which we don't have inside our available memory
-			* - Somebody else has occupied the ttb region which means
-			*   the ttb will get corrupted.
-			*/
-			pr_crit("Critical Error: Can't request SDRAM region for ttb at %p\n",
-				ttb);
-	} else {
-		ttb = xmemalign(GRANULE_SIZE, GRANULE_SIZE);
-
-		memset(ttb, 0, GRANULE_SIZE);
-
-		el = current_el();
-		set_ttbr_tcr_mair(el, (uint64_t)ttb, calc_tcr(el), MEMORY_ATTRIBUTES);
-	}
+	if (get_cr() & CR_M)
+		mmu_disable();
+
+	ttb = xmemalign(GRANULE_SIZE, GRANULE_SIZE);
+
+	memset(ttb, 0, GRANULE_SIZE);
+
+	el = current_el();
+	set_ttbr_tcr_mair(el, (uint64_t)ttb, calc_tcr(el), MEMORY_ATTRIBUTES);
 
 	pr_debug("ttb: 0x%p\n", ttb);
 
@@ -339,26 +243,6 @@ void mmu_disable(void)
 	isb();
 }
 
-void mmu_early_enable(unsigned long membase, unsigned long memsize,
-		      unsigned long _ttb)
-{
-	int el;
-
-	ttb = (uint64_t *)_ttb;
-
-	memset(ttb, 0, GRANULE_SIZE);
-
-	el = current_el();
-	set_ttbr_tcr_mair(el, (uint64_t)ttb, calc_tcr(el), MEMORY_ATTRIBUTES);
-
-	create_sections(0, 0, 1UL << (BITS_PER_VA - 1), UNCACHED_MEM);
-
-	create_sections(membase, membase, memsize, CACHED_MEM);
-
-	isb();
-	set_cr(get_cr() | CR_M);
-}
-
 unsigned long virt_to_phys(volatile void *virt)
 {
 	return (unsigned long)virt;
diff --git a/arch/arm/cpu/mmu_64.h b/arch/arm/cpu/mmu_64.h
index cc01db0db9..c280d2ced2 100644
--- a/arch/arm/cpu/mmu_64.h
+++ b/arch/arm/cpu/mmu_64.h
@@ -1,4 +1,31 @@
 
+#define CACHED_MEM      (PTE_BLOCK_MEMTYPE(MT_NORMAL) | \
+			 PTE_BLOCK_OUTER_SHARE | \
+			 PTE_BLOCK_AF)
+#define UNCACHED_MEM    (PTE_BLOCK_MEMTYPE(MT_DEVICE_nGnRnE) | \
+			 PTE_BLOCK_OUTER_SHARE | \
+			 PTE_BLOCK_AF)
+
+/*
+ * Do it the simple way for now and invalidate the entire tlb
+ */
+static inline void tlb_invalidate(void)
+{
+	unsigned int el = current_el();
+
+	dsb();
+
+	if (el == 1)
+		__asm__ __volatile__("tlbi vmalle1\n\t" : : : "memory");
+	else if (el == 2)
+		__asm__ __volatile__("tlbi alle2\n\t" : : : "memory");
+	else if (el == 3)
+		__asm__ __volatile__("tlbi alle3\n\t" : : : "memory");
+
+	dsb();
+	isb();
+}
+
 static inline void set_ttbr_tcr_mair(int el, uint64_t table, uint64_t tcr, uint64_t attr)
 {
 	asm volatile("dsb sy");
@@ -35,3 +62,60 @@ static inline uint64_t get_ttbr(int el)
 
 	return val;
 }
+
+static inline int level2shift(int level)
+{
+	/* Page is 12 bits wide, every level translates 9 bits */
+	return (12 + 9 * (3 - level));
+}
+
+static inline uint64_t level2mask(int level)
+{
+	uint64_t mask = -EINVAL;
+
+	if (level == 1)
+		mask = L1_ADDR_MASK;
+	else if (level == 2)
+		mask = L2_ADDR_MASK;
+	else if (level == 3)
+		mask = L3_ADDR_MASK;
+
+	return mask;
+}
+
+static inline uint64_t calc_tcr(int el)
+{
+	u64 ips, va_bits;
+	u64 tcr;
+
+	ips = 2;
+	va_bits = BITS_PER_VA;
+
+	if (el == 1)
+		tcr = (ips << 32) | TCR_EPD1_DISABLE;
+	else if (el == 2)
+		tcr = (ips << 16);
+	else
+		tcr = (ips << 16);
+
+	/* PTWs cacheable, inner/outer WBWA and inner shareable */
+	tcr |= TCR_TG0_4K | TCR_SHARED_INNER | TCR_ORGN_WBWA | TCR_IRGN_WBWA;
+	tcr |= TCR_T0SZ(va_bits);
+
+	return tcr;
+}
+
+static inline int pte_type(uint64_t *pte)
+{
+	return *pte & PTE_TYPE_MASK;
+}
+
+static inline uint64_t *get_level_table(uint64_t *pte)
+{
+	uint64_t *table = (uint64_t *)(*pte & XLAT_ADDR_MASK);
+
+	if (pte_type(pte) != PTE_TYPE_TABLE)
+		BUG();
+
+	return table;
+}
-- 
2.16.1



From s.hauer at pengutronix.de  Fri Mar 16 05:53:45 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 16 Mar 2018 13:53:45 +0100
Subject: [PATCH 69/78] common: Add functions to find free RAM
In-Reply-To: <20180316125354.23462-1-s.hauer@pengutronix.de>
References: <20180316125354.23462-1-s.hauer@pengutronix.de>
Message-ID: <20180316125354.23462-70-s.hauer@pengutronix.de>

The bootm code needs to put the Kernel image and initrd into free
RAM. Add some functions to find free RAM chunks to help this code.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 common/memory.c  | 51 +++++++++++++++++++++++++++++++++++++++++++++++++++
 include/memory.h |  5 +++++
 2 files changed, 56 insertions(+)

diff --git a/common/memory.c b/common/memory.c
index ff5bdc14e2..00fa7c50ff 100644
--- a/common/memory.c
+++ b/common/memory.c
@@ -171,6 +171,57 @@ int release_sdram_region(struct resource *res)
 	return release_region(res);
 }
 
+void memory_bank_find_space(struct memory_bank *bank, resource_size_t *retstart,
+			   resource_size_t *retend)
+{
+	resource_size_t freeptr, size, maxfree = 0;
+	struct resource *last, *child;
+
+	if (list_empty(&bank->res->children)) {
+		/* No children - return the whole bank */
+		*retstart = bank->res->start;
+		*retend = bank->res->end;
+		return;
+	}
+
+	freeptr = bank->res->start;
+
+	list_for_each_entry(child, &bank->res->children, sibling) {
+		/* Check gaps between child resources */
+		size = child->start - freeptr;
+		if (size > maxfree) {
+			*retstart = freeptr;
+			*retend = child->start - 1;
+			maxfree = size;
+		}
+		freeptr = child->start + resource_size(child);
+	}
+
+	last = list_last_entry(&bank->res->children, struct resource, sibling);
+
+	/* Check gap between last child and end of memory bank */
+	freeptr = last->start + resource_size(last);
+	size = bank->res->start + resource_size(bank->res) - freeptr;
+
+	if (size > maxfree) {
+		*retstart = freeptr;
+		*retend = bank->res->end;
+	}
+}
+
+int memory_bank_first_find_space(resource_size_t *retstart,
+				 resource_size_t *retend)
+{
+	struct memory_bank *bank;
+
+	for_each_memory_bank(bank) {
+		memory_bank_find_space(bank, retstart, retend);
+		return 0;
+	}
+
+	return -ENOENT;
+}
+
 #ifdef CONFIG_OFTREE
 
 static int of_memory_fixup(struct device_node *node, void *unused)
diff --git a/include/memory.h b/include/memory.h
index 165d2dc52a..56d16d20c8 100644
--- a/include/memory.h
+++ b/include/memory.h
@@ -27,4 +27,9 @@ struct resource *request_sdram_region(const char *name, resource_size_t start,
 		resource_size_t size);
 int release_sdram_region(struct resource *res);
 
+void memory_bank_find_space(struct memory_bank *bank, resource_size_t *retstart,
+			    resource_size_t *retend);
+int memory_bank_first_find_space(resource_size_t *retstart,
+				 resource_size_t *retend);
+
 #endif
-- 
2.16.1



From s.hauer at pengutronix.de  Fri Mar 16 05:53:11 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 16 Mar 2018 13:53:11 +0100
Subject: [PATCH 35/78] ARM: aarch64: mmu: remove unused map_io_sections()
In-Reply-To: <20180316125354.23462-1-s.hauer@pengutronix.de>
References: <20180316125354.23462-1-s.hauer@pengutronix.de>
Message-ID: <20180316125354.23462-36-s.hauer@pengutronix.de>

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/cpu/mmu_64.c | 10 ----------
 1 file changed, 10 deletions(-)

diff --git a/arch/arm/cpu/mmu_64.c b/arch/arm/cpu/mmu_64.c
index fe1e5410f7..357e244042 100644
--- a/arch/arm/cpu/mmu_64.c
+++ b/arch/arm/cpu/mmu_64.c
@@ -202,16 +202,6 @@ static void create_sections(uint64_t virt, uint64_t phys, uint64_t size, uint64_
 	tlb_invalidate();
 }
 
-void *map_io_sections(unsigned long phys, void *_start, size_t size)
-{
-
-	map_region((uint64_t)_start, phys, (uint64_t)size, UNCACHED_MEM);
-
-	tlb_invalidate();
-	return _start;
-}
-
-
 int arch_remap_range(void *_start, size_t size, unsigned flags)
 {
 	map_region((uint64_t)_start, (uint64_t)_start, (uint64_t)size, flags);
-- 
2.16.1



From s.hauer at pengutronix.de  Fri Mar 16 05:53:12 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 16 Mar 2018 13:53:12 +0100
Subject: [PATCH 36/78] ARM: aarch64: mmu: by default map as device memory
In-Reply-To: <20180316125354.23462-1-s.hauer@pengutronix.de>
References: <20180316125354.23462-1-s.hauer@pengutronix.de>
Message-ID: <20180316125354.23462-37-s.hauer@pengutronix.de>

By default map the whole address space as unshared device memory
as this is what barebox drivers normally expect.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/cpu/mmu_64.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/cpu/mmu_64.c b/arch/arm/cpu/mmu_64.c
index 357e244042..27b5acd6a7 100644
--- a/arch/arm/cpu/mmu_64.c
+++ b/arch/arm/cpu/mmu_64.c
@@ -35,7 +35,7 @@
 #include "mmu.h"
 
 #define CACHED_MEM      (PMD_ATTRINDX(MT_NORMAL) | PMD_SECT_S | PMD_SECT_AF | PMD_TYPE_SECT)
-#define UNCACHED_MEM    (PMD_ATTRINDX(MT_NORMAL_NC) | PMD_SECT_S | PMD_SECT_AF | PMD_TYPE_SECT)
+#define UNCACHED_MEM    (PMD_ATTRINDX(MT_DEVICE_nGnRnE) | PMD_SECT_AF)
 
 static uint64_t *ttb;
 
-- 
2.16.1



From s.hauer at pengutronix.de  Fri Mar 16 05:53:52 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 16 Mar 2018 13:53:52 +0100
Subject: [PATCH 76/78] ARM: create separate mmu_64.h file
In-Reply-To: <20180316125354.23462-1-s.hauer@pengutronix.de>
References: <20180316125354.23462-1-s.hauer@pengutronix.de>
Message-ID: <20180316125354.23462-77-s.hauer@pengutronix.de>

cpu/mmu.h has nothing in common for the 32bit and 64bit variant. Make it
two separate files.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/cpu/mmu.h    | 47 -----------------------------------------------
 arch/arm/cpu/mmu_64.c |  2 +-
 arch/arm/cpu/mmu_64.h | 37 +++++++++++++++++++++++++++++++++++++
 3 files changed, 38 insertions(+), 48 deletions(-)
 create mode 100644 arch/arm/cpu/mmu_64.h

diff --git a/arch/arm/cpu/mmu.h b/arch/arm/cpu/mmu.h
index 5803cb6a83..79ebc80d7d 100644
--- a/arch/arm/cpu/mmu.h
+++ b/arch/arm/cpu/mmu.h
@@ -1,53 +1,6 @@
 #ifndef __ARM_MMU_H
 #define __ARM_MMU_H
 
-#ifdef CONFIG_CPU_64v8
-
-#ifndef __ASSEMBLY__
-
-static inline void set_ttbr_tcr_mair(int el, uint64_t table, uint64_t tcr, uint64_t attr)
-{
-	asm volatile("dsb sy");
-	if (el == 1) {
-		asm volatile("msr ttbr0_el1, %0" : : "r" (table) : "memory");
-		asm volatile("msr tcr_el1, %0" : : "r" (tcr) : "memory");
-		asm volatile("msr mair_el1, %0" : : "r" (attr) : "memory");
-	} else if (el == 2) {
-		asm volatile("msr ttbr0_el2, %0" : : "r" (table) : "memory");
-		asm volatile("msr tcr_el2, %0" : : "r" (tcr) : "memory");
-		asm volatile("msr mair_el2, %0" : : "r" (attr) : "memory");
-	} else if (el == 3) {
-		asm volatile("msr ttbr0_el3, %0" : : "r" (table) : "memory");
-		asm volatile("msr tcr_el3, %0" : : "r" (tcr) : "memory");
-		asm volatile("msr mair_el3, %0" : : "r" (attr) : "memory");
-	} else {
-		hang();
-	}
-	asm volatile("isb");
-}
-
-static inline uint64_t get_ttbr(int el)
-{
-	uint64_t val;
-	if (el == 1) {
-		asm volatile("mrs %0, ttbr0_el1" : "=r" (val));
-	} else if (el == 2) {
-		asm volatile("mrs %0, ttbr0_el2" : "=r" (val));
-	} else if (el == 3) {
-		asm volatile("mrs %0, ttbr0_el3" : "=r" (val));
-	} else {
-		hang();
-	}
-
-	return val;
-}
-
-void mmu_early_enable(uint64_t membase, uint64_t memsize, uint64_t _ttb);
-
-#endif
-
-#endif /* CONFIG_CPU_64v8 */
-
 #ifdef CONFIG_MMU
 void __mmu_cache_on(void);
 void __mmu_cache_off(void);
diff --git a/arch/arm/cpu/mmu_64.c b/arch/arm/cpu/mmu_64.c
index 094bc0ac62..7f29ae7623 100644
--- a/arch/arm/cpu/mmu_64.c
+++ b/arch/arm/cpu/mmu_64.c
@@ -32,7 +32,7 @@
 #include <memory.h>
 #include <asm/system_info.h>
 
-#include "mmu.h"
+#include "mmu_64.h"
 
 #define CACHED_MEM      (PTE_BLOCK_MEMTYPE(MT_NORMAL) | \
 			 PTE_BLOCK_OUTER_SHARE | \
diff --git a/arch/arm/cpu/mmu_64.h b/arch/arm/cpu/mmu_64.h
new file mode 100644
index 0000000000..cc01db0db9
--- /dev/null
+++ b/arch/arm/cpu/mmu_64.h
@@ -0,0 +1,37 @@
+
+static inline void set_ttbr_tcr_mair(int el, uint64_t table, uint64_t tcr, uint64_t attr)
+{
+	asm volatile("dsb sy");
+	if (el == 1) {
+		asm volatile("msr ttbr0_el1, %0" : : "r" (table) : "memory");
+		asm volatile("msr tcr_el1, %0" : : "r" (tcr) : "memory");
+		asm volatile("msr mair_el1, %0" : : "r" (attr) : "memory");
+	} else if (el == 2) {
+		asm volatile("msr ttbr0_el2, %0" : : "r" (table) : "memory");
+		asm volatile("msr tcr_el2, %0" : : "r" (tcr) : "memory");
+		asm volatile("msr mair_el2, %0" : : "r" (attr) : "memory");
+	} else if (el == 3) {
+		asm volatile("msr ttbr0_el3, %0" : : "r" (table) : "memory");
+		asm volatile("msr tcr_el3, %0" : : "r" (tcr) : "memory");
+		asm volatile("msr mair_el3, %0" : : "r" (attr) : "memory");
+	} else {
+		hang();
+	}
+	asm volatile("isb");
+}
+
+static inline uint64_t get_ttbr(int el)
+{
+	uint64_t val;
+	if (el == 1) {
+		asm volatile("mrs %0, ttbr0_el1" : "=r" (val));
+	} else if (el == 2) {
+		asm volatile("mrs %0, ttbr0_el2" : "=r" (val));
+	} else if (el == 3) {
+		asm volatile("mrs %0, ttbr0_el3" : "=r" (val));
+	} else {
+		hang();
+	}
+
+	return val;
+}
-- 
2.16.1



From s.hauer at pengutronix.de  Fri Mar 16 05:53:17 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 16 Mar 2018 13:53:17 +0100
Subject: [PATCH 41/78] ARM: aarch64: mmu: Fix adding additional page table
 levels
In-Reply-To: <20180316125354.23462-1-s.hauer@pengutronix.de>
References: <20180316125354.23462-1-s.hauer@pengutronix.de>
Message-ID: <20180316125354.23462-42-s.hauer@pengutronix.de>

When we create a higher level page table we have to initialize it
with the settings from the previous lower level page table so that
we do not modify unrelated mappings. split_block() is taken from
U-Boot code and does this job.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/cpu/mmu_64.c | 39 ++++++++++++++++++++++++++++++++++-----
 1 file changed, 34 insertions(+), 5 deletions(-)

diff --git a/arch/arm/cpu/mmu_64.c b/arch/arm/cpu/mmu_64.c
index baa443f9e2..2934ad12cd 100644
--- a/arch/arm/cpu/mmu_64.c
+++ b/arch/arm/cpu/mmu_64.c
@@ -123,10 +123,8 @@ static uint64_t *get_level_table(uint64_t *pte)
 {
 	uint64_t *table = (uint64_t *)(*pte & XLAT_ADDR_MASK);
 
-	if (pte_type(pte) != PTE_TYPE_TABLE) {
-		table = create_table();
-		set_table(pte, table);
-	}
+	if (pte_type(pte) != PTE_TYPE_TABLE)
+		BUG();
 
 	return table;
 }
@@ -154,6 +152,36 @@ static __maybe_unused uint64_t *find_pte(uint64_t addr)
 	return pte;
 }
 
+#define MAX_PTE_ENTRIES 512
+
+/* Splits a block PTE into table with subpages spanning the old block */
+static void split_block(uint64_t *pte, int level)
+{
+	uint64_t old_pte = *pte;
+	uint64_t *new_table;
+	uint64_t i = 0;
+	int levelshift;
+
+	if ((*pte & PTE_TYPE_MASK) == PTE_TYPE_TABLE)
+		return;
+
+	/* level describes the parent level, we need the child ones */
+	levelshift = level2shift(level + 1);
+
+	new_table = create_table();
+
+	for (i = 0; i < MAX_PTE_ENTRIES; i++) {
+		new_table[i] = old_pte | (i << levelshift);
+
+		/* Level 3 block PTEs have the table type */
+		if ((level + 1) == 3)
+			new_table[i] |= PTE_TYPE_TABLE;
+	}
+
+	/* Set the new table into effect */
+	set_table(pte, new_table);
+}
+
 static void map_region(uint64_t virt, uint64_t phys, uint64_t size, uint64_t attr)
 {
 	uint64_t block_size;
@@ -191,7 +219,8 @@ static void map_region(uint64_t virt, uint64_t phys, uint64_t size, uint64_t att
 				phys += block_size;
 				size -= block_size;
 				break;
-
+			} else {
+				split_block(pte, level);
 			}
 
 			table = get_level_table(pte);
-- 
2.16.1



From s.hauer at pengutronix.de  Fri Mar 16 05:53:16 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 16 Mar 2018 13:53:16 +0100
Subject: [PATCH 40/78] ARM: aarch64: mmu: use PTE_* definitions from U-Boot
In-Reply-To: <20180316125354.23462-1-s.hauer@pengutronix.de>
References: <20180316125354.23462-1-s.hauer@pengutronix.de>
Message-ID: <20180316125354.23462-41-s.hauer@pengutronix.de>

'PMD' (Page Middle Directory) is a Linuxism that is not really
helpful in the barebox MMU code. Use the U-Boot definitions
which only use PTE_* and seem to be more consistent for our
usecase.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/cpu/mmu_64.c            | 22 +++++++------
 arch/arm/include/asm/pgtable64.h | 67 +++++++++++++---------------------------
 2 files changed, 35 insertions(+), 54 deletions(-)

diff --git a/arch/arm/cpu/mmu_64.c b/arch/arm/cpu/mmu_64.c
index 695a73262d..baa443f9e2 100644
--- a/arch/arm/cpu/mmu_64.c
+++ b/arch/arm/cpu/mmu_64.c
@@ -34,8 +34,12 @@
 
 #include "mmu.h"
 
-#define CACHED_MEM      (PMD_ATTRINDX(MT_NORMAL) | PMD_SECT_S | PMD_SECT_AF | PMD_TYPE_SECT)
-#define UNCACHED_MEM    (PMD_ATTRINDX(MT_DEVICE_nGnRnE) | PMD_SECT_AF)
+#define CACHED_MEM      (PTE_BLOCK_MEMTYPE(MT_NORMAL) | \
+			 PTE_BLOCK_OUTER_SHARE | \
+			 PTE_BLOCK_AF)
+#define UNCACHED_MEM    (PTE_BLOCK_MEMTYPE(MT_DEVICE_nGnRnE) | \
+			 PTE_BLOCK_OUTER_SHARE | \
+			 PTE_BLOCK_AF)
 
 static uint64_t *ttb;
 
@@ -94,14 +98,14 @@ static uint64_t level2mask(int level)
 
 static int pte_type(uint64_t *pte)
 {
-	return *pte & PMD_TYPE_MASK;
+	return *pte & PTE_TYPE_MASK;
 }
 
 static void set_table(uint64_t *pt, uint64_t *table_addr)
 {
 	uint64_t val;
 
-	val = PMD_TYPE_TABLE | (uint64_t)table_addr;
+	val = PTE_TYPE_TABLE | (uint64_t)table_addr;
 	*pt = val;
 }
 
@@ -119,7 +123,7 @@ static uint64_t *get_level_table(uint64_t *pte)
 {
 	uint64_t *table = (uint64_t *)(*pte & XLAT_ADDR_MASK);
 
-	if (pte_type(pte) != PMD_TYPE_TABLE) {
+	if (pte_type(pte) != PTE_TYPE_TABLE) {
 		table = create_table();
 		set_table(pte, table);
 	}
@@ -141,7 +145,7 @@ static __maybe_unused uint64_t *find_pte(uint64_t addr)
 		idx = (addr & level2mask(i)) >> block_shift;
 		pte += idx;
 
-		if ((pte_type(pte) != PMD_TYPE_TABLE) || (block_shift <= GRANULE_SIZE_SHIFT))
+		if ((pte_type(pte) != PTE_TYPE_TABLE) || (block_shift <= GRANULE_SIZE_SHIFT))
 			break;
 		else
 			pte = (uint64_t *)(*pte & XLAT_ADDR_MASK);
@@ -165,21 +169,21 @@ static void map_region(uint64_t virt, uint64_t phys, uint64_t size, uint64_t att
 
 	addr = virt;
 
-	attr &= ~(PMD_TYPE_SECT);
+	attr &= ~PTE_TYPE_MASK;
 
 	while (size) {
 		table = ttb;
 		for (level = 1; level < 4; level++) {
 			block_shift = level2shift(level);
 			idx = (addr & level2mask(level)) >> block_shift;
-			block_size = (1 << block_shift);
+			block_size = (1ULL << block_shift);
 
 			pte = table + idx;
 
 			if (level == 3)
 				attr |= PTE_TYPE_PAGE;
 			else
-				attr |= PMD_TYPE_SECT;
+				attr |= PTE_TYPE_BLOCK;
 
 			if (size >= block_size && IS_ALIGNED(addr, block_size)) {
 				*pte = phys | attr;
diff --git a/arch/arm/include/asm/pgtable64.h b/arch/arm/include/asm/pgtable64.h
index 7f7efa10ca..f2888c3ccd 100644
--- a/arch/arm/include/asm/pgtable64.h
+++ b/arch/arm/include/asm/pgtable64.h
@@ -47,51 +47,28 @@
 
 #define GRANULE_MASK	GRANULE_SIZE
 
-
-/*
- * Level 2 descriptor (PMD).
- */
-#define PMD_TYPE_MASK		(3 << 0)
-#define PMD_TYPE_FAULT		(0 << 0)
-#define PMD_TYPE_TABLE		(3 << 0)
-#define PMD_TYPE_SECT		(1 << 0)
-#define PMD_TABLE_BIT		(1 << 1)
-
-/*
- * Section
- */
-#define PMD_SECT_VALID		(1 << 0)
-#define PMD_SECT_USER		(1 << 6)		/* AP[1] */
-#define PMD_SECT_RDONLY		(1 << 7)		/* AP[2] */
-#define PMD_SECT_S		(3 << 8)
-#define PMD_SECT_AF		(1 << 10)
-#define PMD_SECT_NG		(1 << 11)
-#define PMD_SECT_CONT		(1 << 52)
-#define PMD_SECT_PXN		(1 << 53)
-#define PMD_SECT_UXN		(1 << 54)
-
-/*
- * AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers).
- */
-#define PMD_ATTRINDX(t)		((t) << 2)
-#define PMD_ATTRINDX_MASK	(7 << 2)
-
-/*
- * Level 3 descriptor (PTE).
- */
-#define PTE_TYPE_MASK		(3 << 0)
-#define PTE_TYPE_FAULT		(0 << 0)
-#define PTE_TYPE_PAGE		(3 << 0)
-#define PTE_TABLE_BIT		(1 << 1)
-#define PTE_USER		(1 << 6)		/* AP[1] */
-#define PTE_RDONLY		(1 << 7)		/* AP[2] */
-#define PTE_SHARED		(3 << 8)		/* SH[1:0], inner shareable */
-#define PTE_AF			(1 << 10)	/* Access Flag */
-#define PTE_NG			(1 << 11)	/* nG */
-#define PTE_DBM			(1 << 51)	/* Dirty Bit Management */
-#define PTE_CONT		(1 << 52)	/* Contiguous range */
-#define PTE_PXN			(1 << 53)	/* Privileged XN */
-#define PTE_UXN			(1 << 54)	/* User XN */
+/* Hardware page table definitions */
+#define PTE_TYPE_MASK           (3 << 0)
+#define PTE_TYPE_FAULT          (0 << 0)
+#define PTE_TYPE_TABLE          (3 << 0)
+#define PTE_TYPE_PAGE           (3 << 0)
+#define PTE_TYPE_BLOCK          (1 << 0)
+
+#define PTE_TABLE_PXN           (1UL << 59)
+#define PTE_TABLE_XN            (1UL << 60)
+#define PTE_TABLE_AP            (1UL << 61)
+#define PTE_TABLE_NS            (1UL << 63)
+
+/* Block */
+#define PTE_BLOCK_MEMTYPE(x)    ((x) << 2)
+#define PTE_BLOCK_NS            (1 << 5)
+#define PTE_BLOCK_NON_SHARE     (0 << 8)
+#define PTE_BLOCK_OUTER_SHARE   (2 << 8)
+#define PTE_BLOCK_INNER_SHARE   (3 << 8)
+#define PTE_BLOCK_AF            (1 << 10)
+#define PTE_BLOCK_NG            (1 << 11)
+#define PTE_BLOCK_PXN           (UL(1) << 53)
+#define PTE_BLOCK_UXN           (UL(1) << 54)
 
 /*
  * AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers).
-- 
2.16.1



From s.hauer at pengutronix.de  Fri Mar 16 05:53:39 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 16 Mar 2018 13:53:39 +0100
Subject: [PATCH 63/78] ARM: aarch64: Add esr strings
In-Reply-To: <20180316125354.23462-1-s.hauer@pengutronix.de>
References: <20180316125354.23462-1-s.hauer@pengutronix.de>
Message-ID: <20180316125354.23462-64-s.hauer@pengutronix.de>

The Exception Syndrome Register (ESR) holds information over an
exception. This adds the strings necessary to dispatch this information.
Based on Linux code.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/cpu/interrupts_64.c |  46 +++++++++++++++++
 arch/arm/include/asm/esr.h   | 117 +++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 163 insertions(+)
 create mode 100644 arch/arm/include/asm/esr.h

diff --git a/arch/arm/cpu/interrupts_64.c b/arch/arm/cpu/interrupts_64.c
index 9ed6ed9761..c32cd4f051 100644
--- a/arch/arm/cpu/interrupts_64.c
+++ b/arch/arm/cpu/interrupts_64.c
@@ -23,6 +23,52 @@
 #include <asm/unwind.h>
 #include <init.h>
 #include <asm/system.h>
+#include <asm/esr.h>
+
+static const char *esr_class_str[] = {
+	[0 ... ESR_ELx_EC_MAX]		= "UNRECOGNIZED EC",
+	[ESR_ELx_EC_UNKNOWN]		= "Unknown/Uncategorized",
+	[ESR_ELx_EC_WFx]		= "WFI/WFE",
+	[ESR_ELx_EC_CP15_32]		= "CP15 MCR/MRC",
+	[ESR_ELx_EC_CP15_64]		= "CP15 MCRR/MRRC",
+	[ESR_ELx_EC_CP14_MR]		= "CP14 MCR/MRC",
+	[ESR_ELx_EC_CP14_LS]		= "CP14 LDC/STC",
+	[ESR_ELx_EC_FP_ASIMD]		= "ASIMD",
+	[ESR_ELx_EC_CP10_ID]		= "CP10 MRC/VMRS",
+	[ESR_ELx_EC_CP14_64]		= "CP14 MCRR/MRRC",
+	[ESR_ELx_EC_ILL]		= "PSTATE.IL",
+	[ESR_ELx_EC_SVC32]		= "SVC (AArch32)",
+	[ESR_ELx_EC_HVC32]		= "HVC (AArch32)",
+	[ESR_ELx_EC_SMC32]		= "SMC (AArch32)",
+	[ESR_ELx_EC_SVC64]		= "SVC (AArch64)",
+	[ESR_ELx_EC_HVC64]		= "HVC (AArch64)",
+	[ESR_ELx_EC_SMC64]		= "SMC (AArch64)",
+	[ESR_ELx_EC_SYS64]		= "MSR/MRS (AArch64)",
+	[ESR_ELx_EC_IMP_DEF]		= "EL3 IMP DEF",
+	[ESR_ELx_EC_IABT_LOW]		= "IABT (lower EL)",
+	[ESR_ELx_EC_IABT_CUR]		= "IABT (current EL)",
+	[ESR_ELx_EC_PC_ALIGN]		= "PC Alignment",
+	[ESR_ELx_EC_DABT_LOW]		= "DABT (lower EL)",
+	[ESR_ELx_EC_DABT_CUR]		= "DABT (current EL)",
+	[ESR_ELx_EC_SP_ALIGN]		= "SP Alignment",
+	[ESR_ELx_EC_FP_EXC32]		= "FP (AArch32)",
+	[ESR_ELx_EC_FP_EXC64]		= "FP (AArch64)",
+	[ESR_ELx_EC_SERROR]		= "SError",
+	[ESR_ELx_EC_BREAKPT_LOW]	= "Breakpoint (lower EL)",
+	[ESR_ELx_EC_BREAKPT_CUR]	= "Breakpoint (current EL)",
+	[ESR_ELx_EC_SOFTSTP_LOW]	= "Software Step (lower EL)",
+	[ESR_ELx_EC_SOFTSTP_CUR]	= "Software Step (current EL)",
+	[ESR_ELx_EC_WATCHPT_LOW]	= "Watchpoint (lower EL)",
+	[ESR_ELx_EC_WATCHPT_CUR]	= "Watchpoint (current EL)",
+	[ESR_ELx_EC_BKPT32]		= "BKPT (AArch32)",
+	[ESR_ELx_EC_VECTOR32]		= "Vector catch (AArch32)",
+	[ESR_ELx_EC_BRK64]		= "BRK (AArch64)",
+};
+
+const char *esr_get_class_string(u32 esr)
+{
+	return esr_class_str[esr >> ESR_ELx_EC_SHIFT];
+}
 
 /**
  * Display current register set content
diff --git a/arch/arm/include/asm/esr.h b/arch/arm/include/asm/esr.h
new file mode 100644
index 0000000000..77eeb2cc64
--- /dev/null
+++ b/arch/arm/include/asm/esr.h
@@ -0,0 +1,117 @@
+/*
+ * Copyright (C) 2013 - ARM Ltd
+ * Author: Marc Zyngier <marc.zyngier at arm.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __ASM_ESR_H
+#define __ASM_ESR_H
+
+#include <asm/memory.h>
+
+#define ESR_ELx_EC_UNKNOWN	(0x00)
+#define ESR_ELx_EC_WFx		(0x01)
+/* Unallocated EC: 0x02 */
+#define ESR_ELx_EC_CP15_32	(0x03)
+#define ESR_ELx_EC_CP15_64	(0x04)
+#define ESR_ELx_EC_CP14_MR	(0x05)
+#define ESR_ELx_EC_CP14_LS	(0x06)
+#define ESR_ELx_EC_FP_ASIMD	(0x07)
+#define ESR_ELx_EC_CP10_ID	(0x08)
+/* Unallocated EC: 0x09 - 0x0B */
+#define ESR_ELx_EC_CP14_64	(0x0C)
+/* Unallocated EC: 0x0d */
+#define ESR_ELx_EC_ILL		(0x0E)
+/* Unallocated EC: 0x0F - 0x10 */
+#define ESR_ELx_EC_SVC32	(0x11)
+#define ESR_ELx_EC_HVC32	(0x12)
+#define ESR_ELx_EC_SMC32	(0x13)
+/* Unallocated EC: 0x14 */
+#define ESR_ELx_EC_SVC64	(0x15)
+#define ESR_ELx_EC_HVC64	(0x16)
+#define ESR_ELx_EC_SMC64	(0x17)
+#define ESR_ELx_EC_SYS64	(0x18)
+/* Unallocated EC: 0x19 - 0x1E */
+#define ESR_ELx_EC_IMP_DEF	(0x1f)
+#define ESR_ELx_EC_IABT_LOW	(0x20)
+#define ESR_ELx_EC_IABT_CUR	(0x21)
+#define ESR_ELx_EC_PC_ALIGN	(0x22)
+/* Unallocated EC: 0x23 */
+#define ESR_ELx_EC_DABT_LOW	(0x24)
+#define ESR_ELx_EC_DABT_CUR	(0x25)
+#define ESR_ELx_EC_SP_ALIGN	(0x26)
+/* Unallocated EC: 0x27 */
+#define ESR_ELx_EC_FP_EXC32	(0x28)
+/* Unallocated EC: 0x29 - 0x2B */
+#define ESR_ELx_EC_FP_EXC64	(0x2C)
+/* Unallocated EC: 0x2D - 0x2E */
+#define ESR_ELx_EC_SERROR	(0x2F)
+#define ESR_ELx_EC_BREAKPT_LOW	(0x30)
+#define ESR_ELx_EC_BREAKPT_CUR	(0x31)
+#define ESR_ELx_EC_SOFTSTP_LOW	(0x32)
+#define ESR_ELx_EC_SOFTSTP_CUR	(0x33)
+#define ESR_ELx_EC_WATCHPT_LOW	(0x34)
+#define ESR_ELx_EC_WATCHPT_CUR	(0x35)
+/* Unallocated EC: 0x36 - 0x37 */
+#define ESR_ELx_EC_BKPT32	(0x38)
+/* Unallocated EC: 0x39 */
+#define ESR_ELx_EC_VECTOR32	(0x3A)
+/* Unallocted EC: 0x3B */
+#define ESR_ELx_EC_BRK64	(0x3C)
+/* Unallocated EC: 0x3D - 0x3F */
+#define ESR_ELx_EC_MAX		(0x3F)
+
+#define ESR_ELx_EC_SHIFT	(26)
+#define ESR_ELx_EC_MASK		(UL(0x3F) << ESR_ELx_EC_SHIFT)
+
+#define ESR_ELx_IL		(UL(1) << 25)
+#define ESR_ELx_ISS_MASK	(ESR_ELx_IL - 1)
+#define ESR_ELx_ISV		(UL(1) << 24)
+#define ESR_ELx_SAS_SHIFT	(22)
+#define ESR_ELx_SAS		(UL(3) << ESR_ELx_SAS_SHIFT)
+#define ESR_ELx_SSE		(UL(1) << 21)
+#define ESR_ELx_SRT_SHIFT	(16)
+#define ESR_ELx_SRT_MASK	(UL(0x1F) << ESR_ELx_SRT_SHIFT)
+#define ESR_ELx_SF 		(UL(1) << 15)
+#define ESR_ELx_AR 		(UL(1) << 14)
+#define ESR_ELx_EA 		(UL(1) << 9)
+#define ESR_ELx_CM 		(UL(1) << 8)
+#define ESR_ELx_S1PTW 		(UL(1) << 7)
+#define ESR_ELx_WNR		(UL(1) << 6)
+#define ESR_ELx_FSC		(0x3F)
+#define ESR_ELx_FSC_TYPE	(0x3C)
+#define ESR_ELx_FSC_EXTABT	(0x10)
+#define ESR_ELx_FSC_ACCESS	(0x08)
+#define ESR_ELx_FSC_FAULT	(0x04)
+#define ESR_ELx_FSC_PERM	(0x0C)
+#define ESR_ELx_CV		(UL(1) << 24)
+#define ESR_ELx_COND_SHIFT	(20)
+#define ESR_ELx_COND_MASK	(UL(0xF) << ESR_ELx_COND_SHIFT)
+#define ESR_ELx_WFx_ISS_WFE	(UL(1) << 0)
+#define ESR_ELx_xVC_IMM_MASK	((1UL << 16) - 1)
+
+/* ESR value templates for specific events */
+
+/* BRK instruction trap from AArch64 state */
+#define ESR_ELx_VAL_BRK64(imm)					\
+	((ESR_ELx_EC_BRK64 << ESR_ELx_EC_SHIFT) | ESR_ELx_IL |	\
+	 ((imm) & 0xffff))
+
+#ifndef __ASSEMBLY__
+#include <asm/types.h>
+
+const char *esr_get_class_string(u32 esr);
+#endif /* __ASSEMBLY */
+
+#endif /* __ASM_ESR_H */
-- 
2.16.1



From s.hauer at pengutronix.de  Fri Mar 16 05:53:15 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 16 Mar 2018 13:53:15 +0100
Subject: [PATCH 39/78] ARM: aarch64: mmu: enable mmu in generic code
In-Reply-To: <20180316125354.23462-1-s.hauer@pengutronix.de>
References: <20180316125354.23462-1-s.hauer@pengutronix.de>
Message-ID: <20180316125354.23462-40-s.hauer@pengutronix.de>

Using board code to enable the MMU is not nice. Do it in generic
code. Since mmu_enable() is now done in mmu_64.c we no longer have
to export it.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/boards/qemu-virt64/init.c | 10 ----------
 arch/arm/cpu/mmu_64.c              | 20 ++++++++------------
 arch/arm/include/asm/mmu.h         |  1 -
 3 files changed, 8 insertions(+), 23 deletions(-)

diff --git a/arch/arm/boards/qemu-virt64/init.c b/arch/arm/boards/qemu-virt64/init.c
index 686231696e..19cfcae1f0 100644
--- a/arch/arm/boards/qemu-virt64/init.c
+++ b/arch/arm/boards/qemu-virt64/init.c
@@ -62,13 +62,3 @@ static int virt_core_init(void)
 	return 0;
 }
 postcore_initcall(virt_core_init);
-
-#ifdef CONFIG_MMU
-static int virt_mmu_enable(void)
-{
-	mmu_enable();
-
-	return 0;
-}
-postmmu_initcall(virt_mmu_enable);
-#endif
diff --git a/arch/arm/cpu/mmu_64.c b/arch/arm/cpu/mmu_64.c
index 639aa6d189..695a73262d 100644
--- a/arch/arm/cpu/mmu_64.c
+++ b/arch/arm/cpu/mmu_64.c
@@ -210,6 +210,12 @@ int arch_remap_range(void *_start, size_t size, unsigned flags)
 	return 0;
 }
 
+static void mmu_enable(void)
+{
+	isb();
+	set_cr(get_cr() | CR_M | CR_C | CR_I);
+}
+
 /*
  * Prepare MMU for usage enable it.
  */
@@ -256,22 +262,12 @@ static int mmu_init(void)
 	for_each_memory_bank(bank)
 		create_sections(bank->start, bank->start, bank->size, CACHED_MEM);
 
+	mmu_enable();
+
 	return 0;
 }
 mmu_initcall(mmu_init);
 
-void mmu_enable(void)
-{
-	if (!ttb)
-		arm_mmu_not_initialized_error();
-
-	if (!(get_cr() & CR_M)) {
-
-		isb();
-		set_cr(get_cr() | CR_M | CR_C | CR_I);
-	}
-}
-
 void mmu_disable(void)
 {
 	unsigned int cr;
diff --git a/arch/arm/include/asm/mmu.h b/arch/arm/include/asm/mmu.h
index 2a1daeafe3..840851858f 100644
--- a/arch/arm/include/asm/mmu.h
+++ b/arch/arm/include/asm/mmu.h
@@ -8,7 +8,6 @@
 
 struct arm_memory;
 
-void mmu_enable(void);
 void mmu_disable(void);
 static inline void arm_create_section(unsigned long virt, unsigned long phys, int size_m,
 		unsigned int flags)
-- 
2.16.1



From s.hauer at pengutronix.de  Fri Mar 16 05:53:35 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 16 Mar 2018 13:53:35 +0100
Subject: [PATCH 59/78] ARM: aarch64: implement show_regs()
In-Reply-To: <20180316125354.23462-1-s.hauer@pengutronix.de>
References: <20180316125354.23462-1-s.hauer@pengutronix.de>
Message-ID: <20180316125354.23462-60-s.hauer@pengutronix.de>

Do something useful in an exception and at least print the current
register contents.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/cpu/interrupts_64.c  |  8 ++++++++
 arch/arm/include/asm/ptrace.h | 19 +++++++++++++++++++
 2 files changed, 27 insertions(+)

diff --git a/arch/arm/cpu/interrupts_64.c b/arch/arm/cpu/interrupts_64.c
index b3bd0aa5a4..ffdb87af94 100644
--- a/arch/arm/cpu/interrupts_64.c
+++ b/arch/arm/cpu/interrupts_64.c
@@ -30,6 +30,14 @@
  */
 void show_regs(struct pt_regs *regs)
 {
+	int i;
+
+	printf("elr: %016lx lr : %016lx\n", regs->elr, regs->regs[30]);
+
+	for (i = 0; i < 29; i += 2)
+		printf("x%-2d: %016lx x%-2d: %016lx\n",
+			i, regs->regs[i], i + 1, regs->regs[i + 1]);
+	printf("\n");
 }
 
 static void __noreturn do_exception(struct pt_regs *pt_regs)
diff --git a/arch/arm/include/asm/ptrace.h b/arch/arm/include/asm/ptrace.h
index 6520a0a73a..7fbd8d9b6f 100644
--- a/arch/arm/include/asm/ptrace.h
+++ b/arch/arm/include/asm/ptrace.h
@@ -10,6 +10,23 @@
 #ifndef __ASM_ARM_PTRACE_H
 #define __ASM_ARM_PTRACE_H
 
+#ifdef CONFIG_CPU_64
+
+#ifndef __ASSEMBLY__
+
+/*
+ * This struct defines the way the registers are stored
+ * on the stack during an exception.
+ */
+struct pt_regs {
+	unsigned long elr;
+	unsigned long regs[31];
+};
+
+#endif  /* __ASSEMBLY__ */
+
+#else   /* CONFIG_CPU_64 */
+
 #define PTRACE_GETREGS		12
 #define PTRACE_SETREGS		13
 #define PTRACE_GETFPREGS	14
@@ -141,4 +158,6 @@ extern void show_regs(struct pt_regs *);
 
 #endif /* __ASSEMBLY__ */
 
+#endif /* CONFIG_CPU_64 */
+
 #endif
-- 
2.16.1



From s.hauer at pengutronix.de  Fri Mar 16 05:53:23 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 16 Mar 2018 13:53:23 +0100
Subject: [PATCH 47/78] ARM: Make some variables 64bit aware
In-Reply-To: <20180316125354.23462-1-s.hauer@pengutronix.de>
References: <20180316125354.23462-1-s.hauer@pengutronix.de>
Message-ID: <20180316125354.23462-48-s.hauer@pengutronix.de>

Use unsigned long as type for variables that are used as addresses.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/cpu/start-pbl.c  | 10 +++++-----
 arch/arm/cpu/uncompress.c |  2 +-
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/arch/arm/cpu/start-pbl.c b/arch/arm/cpu/start-pbl.c
index 73c27429da..25f91b02f3 100644
--- a/arch/arm/cpu/start-pbl.c
+++ b/arch/arm/cpu/start-pbl.c
@@ -48,10 +48,10 @@ extern void *input_data_end;
 __noreturn void barebox_single_pbl_start(unsigned long membase,
 		unsigned long memsize, void *boarddata)
 {
-	uint32_t offset;
-	uint32_t pg_start, pg_end, pg_len, uncompressed_len;
+	unsigned long offset;
+	unsigned long pg_start, pg_end, pg_len, uncompressed_len;
 	void __noreturn (*barebox)(unsigned long, unsigned long, void *);
-	uint32_t endmem = membase + memsize;
+	unsigned long endmem = membase + memsize;
 	unsigned long barebox_base;
 
 	if (IS_ENABLED(CONFIG_PBL_RELOCATABLE))
@@ -60,8 +60,8 @@ __noreturn void barebox_single_pbl_start(unsigned long membase,
 	/* Get offset between linked address and runtime address */
 	offset = get_runtime_offset();
 
-	pg_start = (uint32_t)&input_data + global_variable_offset();
-	pg_end = (uint32_t)&input_data_end + global_variable_offset();
+	pg_start = (unsigned long)&input_data + global_variable_offset();
+	pg_end = (unsigned long)&input_data_end + global_variable_offset();
 	pg_len = pg_end - pg_start;
 	uncompressed_len = get_unaligned((const u32 *)(pg_start + pg_len - 4));
 
diff --git a/arch/arm/cpu/uncompress.c b/arch/arm/cpu/uncompress.c
index 37845b2259..c721eef0ad 100644
--- a/arch/arm/cpu/uncompress.c
+++ b/arch/arm/cpu/uncompress.c
@@ -45,7 +45,7 @@ void __noreturn barebox_multi_pbl_start(unsigned long membase,
 {
 	uint32_t pg_len, uncompressed_len;
 	void __noreturn (*barebox)(unsigned long, unsigned long, void *);
-	uint32_t endmem = membase + memsize;
+	unsigned long endmem = membase + memsize;
 	unsigned long barebox_base;
 	uint32_t *image_end;
 	void *pg_start;
-- 
2.16.1



From s.hauer at pengutronix.de  Fri Mar 16 05:53:04 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 16 Mar 2018 13:53:04 +0100
Subject: [PATCH 28/78] ARM: relocate_to_current_adr: Use unsigned long for
 variables
In-Reply-To: <20180316125354.23462-1-s.hauer@pengutronix.de>
References: <20180316125354.23462-1-s.hauer@pengutronix.de>
Message-ID: <20180316125354.23462-29-s.hauer@pengutronix.de>

relocate_to_current_adr() fixes up pointers in the binary, so unsigned
long is a better match as it works on aarch64 aswell.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/cpu/common.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/arch/arm/cpu/common.c b/arch/arm/cpu/common.c
index 7c07d00c1b..3766116d97 100644
--- a/arch/arm/cpu/common.c
+++ b/arch/arm/cpu/common.c
@@ -30,8 +30,8 @@
  */
 void relocate_to_current_adr(void)
 {
-	uint32_t offset;
-	uint32_t *dstart, *dend, *dynsym, *dynend;
+	unsigned long offset;
+	unsigned long *dstart, *dend, *dynsym, *dynend;
 
 	/* Get offset between linked address and runtime address */
 	offset = get_runtime_offset();
@@ -43,14 +43,14 @@ void relocate_to_current_adr(void)
 	dynend = (void *)__dynsym_end + offset;
 
 	while (dstart < dend) {
-		uint32_t *fixup = (uint32_t *)(*dstart + offset);
-		uint32_t type = *(dstart + 1);
+		unsigned long *fixup = (unsigned long *)(*dstart + offset);
+		unsigned long type = *(dstart + 1);
 
 		if ((type & 0xff) == 0x17) {
 			*fixup = *fixup + offset;
 		} else {
 			int index = type >> 8;
-			uint32_t r = dynsym[index * 4 + 1];
+			unsigned long r = dynsym[index * 4 + 1];
 
 			*fixup = *fixup + r + offset;
 		}
-- 
2.16.1



From s.hauer at pengutronix.de  Fri Mar 16 05:53:21 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 16 Mar 2018 13:53:21 +0100
Subject: [PATCH 45/78] ARM: aarch64: mmu: drop ttb check when disabling the MMU
In-Reply-To: <20180316125354.23462-1-s.hauer@pengutronix.de>
References: <20180316125354.23462-1-s.hauer@pengutronix.de>
Message-ID: <20180316125354.23462-46-s.hauer@pengutronix.de>

If the MMU is enabled then we should be able to disable it, no
matter if we initialized it in barebox or not. This change is not
really needed but helps when we are starting second stage from U-Boot
with the 'go' command which leaves the MMU enabled.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/cpu/mmu_64.c | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/arch/arm/cpu/mmu_64.c b/arch/arm/cpu/mmu_64.c
index c8c3c9d84f..165ff5bac6 100644
--- a/arch/arm/cpu/mmu_64.c
+++ b/arch/arm/cpu/mmu_64.c
@@ -326,9 +326,6 @@ void mmu_disable(void)
 {
 	unsigned int cr;
 
-	if (!ttb)
-		arm_mmu_not_initialized_error();
-
 	cr = get_cr();
 	cr &= ~(CR_M | CR_C);
 
-- 
2.16.1



From s.hauer at pengutronix.de  Fri Mar 16 05:53:40 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 16 Mar 2018 13:53:40 +0100
Subject: [PATCH 64/78] ARM: aarch64: print more information on sync exception
In-Reply-To: <20180316125354.23462-1-s.hauer@pengutronix.de>
References: <20180316125354.23462-1-s.hauer@pengutronix.de>
Message-ID: <20180316125354.23462-65-s.hauer@pengutronix.de>

On a sync exception more useful information can be printed than we
currently do. Pass the ESR and FAR value to do_sync and print the
reason for the exception along with the address that actually faulted.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/cpu/exceptions_64.S | 4 ++++
 arch/arm/cpu/interrupts_64.c | 4 ++--
 2 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/arch/arm/cpu/exceptions_64.S b/arch/arm/cpu/exceptions_64.S
index 58ca50b709..22034eaef9 100644
--- a/arch/arm/cpu/exceptions_64.S
+++ b/arch/arm/cpu/exceptions_64.S
@@ -35,12 +35,15 @@
 	switch_el x11, 3f, 2f, 1f
 3:	mrs	x1, esr_el3
 	mrs	x2, elr_el3
+	mrs     x3, far_el3
 	b	0f
 2:	mrs	x1, esr_el2
 	mrs	x2, elr_el2
+	mrs     x3, far_el2
 	b	0f
 1:	mrs	x1, esr_el1
 	mrs	x2, elr_el1
+	mrs     x3, far_el1
 0:
 	stp	x2, x0, [sp, #-16]!
 	mov	x0, sp
@@ -99,6 +102,7 @@ _do_bad_error:
 
 _do_sync:
 	exception_entry
+	mov	x2, x3
 	bl	do_sync
 	b	exception_exit
 
diff --git a/arch/arm/cpu/interrupts_64.c b/arch/arm/cpu/interrupts_64.c
index c32cd4f051..ee3dc3380b 100644
--- a/arch/arm/cpu/interrupts_64.c
+++ b/arch/arm/cpu/interrupts_64.c
@@ -143,9 +143,9 @@ void do_bad_error(struct pt_regs *pt_regs)
 	do_exception(pt_regs);
 }
 
-void do_sync(struct pt_regs *pt_regs)
+void do_sync(struct pt_regs *pt_regs, unsigned int esr, unsigned long far)
 {
-	printf("sync exception\n");
+	printf("%s exception at 0x%016lx\n", esr_get_class_string(esr), far);
 	do_exception(pt_regs);
 }
 
-- 
2.16.1



From s.hauer at pengutronix.de  Fri Mar 16 05:53:19 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 16 Mar 2018 13:53:19 +0100
Subject: [PATCH 43/78] ARM: aarch64: mmu: Fix TCR setting
In-Reply-To: <20180316125354.23462-1-s.hauer@pengutronix.de>
References: <20180316125354.23462-1-s.hauer@pengutronix.de>
Message-ID: <20180316125354.23462-44-s.hauer@pengutronix.de>

A BITS_PER_VA value of 33 is a little small. Increase it to 39 which is
the maximum size we can do with 3 level page tables. The TCR value
depends on the current exception level, so we have to calculate the
value during runtime. To do this use a function derived from U-Boots
get_tcr function.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/cpu/mmu.h               |  7 -------
 arch/arm/cpu/mmu_64.c            | 31 ++++++++++++++++++++++++++++---
 arch/arm/include/asm/pgtable64.h |  3 ++-
 3 files changed, 30 insertions(+), 11 deletions(-)

diff --git a/arch/arm/cpu/mmu.h b/arch/arm/cpu/mmu.h
index 186d408ead..5803cb6a83 100644
--- a/arch/arm/cpu/mmu.h
+++ b/arch/arm/cpu/mmu.h
@@ -3,13 +3,6 @@
 
 #ifdef CONFIG_CPU_64v8
 
-#define TCR_FLAGS		(TCR_TG0_4K | \
-		TCR_SHARED_OUTER | \
-		TCR_SHARED_INNER | \
-		TCR_IRGN_WBWA | \
-		TCR_ORGN_WBWA | \
-		TCR_T0SZ(BITS_PER_VA))
-
 #ifndef __ASSEMBLY__
 
 static inline void set_ttbr_tcr_mair(int el, uint64_t table, uint64_t tcr, uint64_t attr)
diff --git a/arch/arm/cpu/mmu_64.c b/arch/arm/cpu/mmu_64.c
index c7590fa33c..7932185885 100644
--- a/arch/arm/cpu/mmu_64.c
+++ b/arch/arm/cpu/mmu_64.c
@@ -54,6 +54,27 @@ static void arm_mmu_not_initialized_error(void)
 	panic("MMU not initialized\n");
 }
 
+static uint64_t calc_tcr(int el)
+{
+	u64 ips, va_bits;
+	u64 tcr;
+
+	ips = 2;
+	va_bits = BITS_PER_VA;
+
+	if (el == 1)
+		tcr = (ips << 32) | TCR_EPD1_DISABLE;
+	else if (el == 2)
+		tcr = (ips << 16);
+	else
+		tcr = (ips << 16);
+
+	/* PTWs cacheable, inner/outer WBWA and inner shareable */
+	tcr |= TCR_TG0_4K | TCR_SHARED_INNER | TCR_ORGN_WBWA | TCR_IRGN_WBWA;
+	tcr |= TCR_T0SZ(va_bits);
+
+	return tcr;
+}
 
 /*
  * Do it the simple way for now and invalidate the entire
@@ -254,6 +275,7 @@ static void mmu_enable(void)
 static int mmu_init(void)
 {
 	struct memory_bank *bank;
+	unsigned int el;
 
 	if (list_empty(&memory_banks))
 		/*
@@ -281,8 +303,8 @@ static int mmu_init(void)
 
 		memset(ttb, 0, GRANULE_SIZE);
 
-		set_ttbr_tcr_mair(current_el(), (uint64_t)ttb, TCR_FLAGS,
-				  MEMORY_ATTRIBUTES);
+		el = current_el();
+		set_ttbr_tcr_mair(el, (uint64_t)ttb, calc_tcr(el), MEMORY_ATTRIBUTES);
 	}
 
 	pr_debug("ttb: 0x%p\n", ttb);
@@ -323,11 +345,14 @@ void mmu_disable(void)
 
 void mmu_early_enable(uint64_t membase, uint64_t memsize, uint64_t _ttb)
 {
+	int el;
+
 	ttb = (uint64_t *)_ttb;
 
 	memset(ttb, 0, GRANULE_SIZE);
 
-	set_ttbr_tcr_mair(current_el(), (uint64_t)ttb, TCR_FLAGS, MEMORY_ATTRIBUTES);
+	el = current_el();
+	set_ttbr_tcr_mair(el, (uint64_t)ttb, calc_tcr(el), MEMORY_ATTRIBUTES);
 
 	create_sections(0, 0, 1UL << (BITS_PER_VA - 1), UNCACHED_MEM);
 
diff --git a/arch/arm/include/asm/pgtable64.h b/arch/arm/include/asm/pgtable64.h
index f2888c3ccd..d8382505d0 100644
--- a/arch/arm/include/asm/pgtable64.h
+++ b/arch/arm/include/asm/pgtable64.h
@@ -21,7 +21,7 @@
 #define UNUSED_DESC                0x6EbAAD0BBADbA6E0
 
 #define VA_START                   0x0
-#define BITS_PER_VA                33
+#define BITS_PER_VA                39
 
 /* Granule size of 4KB is being used */
 #define GRANULE_SIZE_SHIFT         12
@@ -116,6 +116,7 @@
 #define TCR_EL1_IPS_BITS	(UL(3) << 32)	/* 42 bits physical address */
 #define TCR_EL2_IPS_BITS	(3 << 16)	/* 42 bits physical address */
 #define TCR_EL3_IPS_BITS	(3 << 16)	/* 42 bits physical address */
+#define TCR_EPD1_DISABLE	(1 << 23)
 
 #define TCR_EL1_RSVD		(1 << 31)
 #define TCR_EL2_RSVD		(1 << 31 | 1 << 23)
-- 
2.16.1



From s.hauer at pengutronix.de  Fri Mar 16 05:53:47 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 16 Mar 2018 13:53:47 +0100
Subject: [PATCH 71/78] ARM: aarch64: disable 32bit boot commands
In-Reply-To: <20180316125354.23462-1-s.hauer@pengutronix.de>
References: <20180316125354.23462-1-s.hauer@pengutronix.de>
Message-ID: <20180316125354.23462-72-s.hauer@pengutronix.de>

The 32bit boot support is full of legacy cruft. While it should be
possible to merge the aarch64 support there, a fresh start looks more
promising.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/Makefile               | 1 -
 arch/arm/lib32/Makefile         | 2 ++
 arch/arm/{lib => lib32}/bootm.c | 0
 arch/arm/{lib => lib32}/bootu.c | 0
 commands/Kconfig                | 4 ++--
 5 files changed, 4 insertions(+), 3 deletions(-)
 rename arch/arm/{lib => lib32}/bootm.c (100%)
 rename arch/arm/{lib => lib32}/bootu.c (100%)

diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index cf84a9a1c1..ac97de1e83 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -298,7 +298,6 @@ endif
 
 common-y += $(BOARD) arch/arm/boards/ $(MACH)
 common-y += arch/arm/cpu/
-common-y += arch/arm/lib/
 
 ifeq ($(CONFIG_CPU_V8), y)
 common-y += arch/arm/lib64/
diff --git a/arch/arm/lib32/Makefile b/arch/arm/lib32/Makefile
index cdd07322cf..3c02a0bf96 100644
--- a/arch/arm/lib32/Makefile
+++ b/arch/arm/lib32/Makefile
@@ -1,5 +1,7 @@
 obj-$(CONFIG_ARM_LINUX)	+= armlinux.o
 obj-$(CONFIG_CMD_BOOTZ)	+= bootz.o
+obj-$(CONFIG_BOOTM)     += bootm.o
+obj-$(CONFIG_CMD_BOOTU) += bootu.o
 obj-y	+= div0.o
 obj-y	+= findbit.o
 obj-y	+= io.o
diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib32/bootm.c
similarity index 100%
rename from arch/arm/lib/bootm.c
rename to arch/arm/lib32/bootm.c
diff --git a/arch/arm/lib/bootu.c b/arch/arm/lib32/bootu.c
similarity index 100%
rename from arch/arm/lib/bootu.c
rename to arch/arm/lib32/bootu.c
diff --git a/commands/Kconfig b/commands/Kconfig
index 17bbe0f27a..951a86963e 100644
--- a/commands/Kconfig
+++ b/commands/Kconfig
@@ -348,7 +348,7 @@ config CMD_BOOTM
 config CMD_BOOTU
 	tristate
 	default y
-	depends on ARM
+	depends on ARM && !CPU_64v8
 	prompt "bootu"
 	help
 	  Boot into already loaded Linux kernel, which must be raw (uncompressed).
@@ -357,7 +357,7 @@ config CMD_BOOTU
 
 config CMD_BOOTZ
 	tristate
-	depends on ARM
+	depends on ARM && !CPU_64v8
 	prompt "bootz"
 	help
 	  Boot Linux zImage
-- 
2.16.1



From s.hauer at pengutronix.de  Fri Mar 16 05:53:09 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 16 Mar 2018 13:53:09 +0100
Subject: [PATCH 33/78] ARM: aarch64: mmu: create_sections() takes size in bytes
In-Reply-To: <20180316125354.23462-1-s.hauer@pengutronix.de>
References: <20180316125354.23462-1-s.hauer@pengutronix.de>
Message-ID: <20180316125354.23462-34-s.hauer@pengutronix.de>

create_sections() takes size in bytes, not in megabytes, so
drop the _m prefix from the size argument.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/cpu/mmu_64.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/arch/arm/cpu/mmu_64.c b/arch/arm/cpu/mmu_64.c
index eb54097514..6e22da9a26 100644
--- a/arch/arm/cpu/mmu_64.c
+++ b/arch/arm/cpu/mmu_64.c
@@ -196,10 +196,9 @@ static void map_region(uint64_t virt, uint64_t phys, uint64_t size, uint64_t att
 	}
 }
 
-static void create_sections(uint64_t virt, uint64_t phys, uint64_t size_m, uint64_t flags)
+static void create_sections(uint64_t virt, uint64_t phys, uint64_t size, uint64_t flags)
 {
-
-	map_region(virt, phys, size_m, flags);
+	map_region(virt, phys, size, flags);
 	tlb_invalidate();
 }
 
-- 
2.16.1



From s.hauer at pengutronix.de  Fri Mar 16 05:53:03 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 16 Mar 2018 13:53:03 +0100
Subject: [PATCH 27/78] ARM: move linker variable declarations to sections.h
In-Reply-To: <20180316125354.23462-1-s.hauer@pengutronix.de>
References: <20180316125354.23462-1-s.hauer@pengutronix.de>
Message-ID: <20180316125354.23462-28-s.hauer@pengutronix.de>

We collected most linker variable declarations in asm/sections.h, so
move __exceptions_start/__exceptions_stop there aswell.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/cpu/mmu.c                 | 1 +
 arch/arm/cpu/no-mmu.c              | 2 +-
 arch/arm/include/asm/barebox-arm.h | 2 --
 arch/arm/include/asm/sections.h    | 2 ++
 4 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/arch/arm/cpu/mmu.c b/arch/arm/cpu/mmu.c
index 27d994d452..de0b631981 100644
--- a/arch/arm/cpu/mmu.c
+++ b/arch/arm/cpu/mmu.c
@@ -30,6 +30,7 @@
 #include <asm/pgtable.h>
 #include <memory.h>
 #include <asm/system_info.h>
+#include <asm/sections.h>
 
 #include "mmu.h"
 
diff --git a/arch/arm/cpu/no-mmu.c b/arch/arm/cpu/no-mmu.c
index e227b457a1..7268fa9b9d 100644
--- a/arch/arm/cpu/no-mmu.c
+++ b/arch/arm/cpu/no-mmu.c
@@ -28,7 +28,7 @@
 #include <memory.h>
 #include <asm/system_info.h>
 #include <debug_ll.h>
-
+#include <asm/sections.h>
 
 #define __exceptions_size (__exceptions_stop - __exceptions_start)
 
diff --git a/arch/arm/include/asm/barebox-arm.h b/arch/arm/include/asm/barebox-arm.h
index 6c7507a9c7..fa673a63a7 100644
--- a/arch/arm/include/asm/barebox-arm.h
+++ b/arch/arm/include/asm/barebox-arm.h
@@ -32,8 +32,6 @@
 #include <linux/compiler.h>
 #include <asm/barebox-arm-head.h>
 
-extern char __exceptions_start[], __exceptions_stop[];
-
 unsigned long get_runtime_offset(void);
 
 /* global_variable_offset() - Access global variables when not running at link address
diff --git a/arch/arm/include/asm/sections.h b/arch/arm/include/asm/sections.h
index b3ada62ee8..6933c7032d 100644
--- a/arch/arm/include/asm/sections.h
+++ b/arch/arm/include/asm/sections.h
@@ -8,6 +8,8 @@ extern char __rel_dyn_start[];
 extern char __rel_dyn_end[];
 extern char __dynsym_start[];
 extern char __dynsym_end[];
+extern char __exceptions_start[];
+extern char __exceptions_stop[];
 
 #endif
 
-- 
2.16.1



From s.hauer at pengutronix.de  Fri Mar 16 05:53:37 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 16 Mar 2018 13:53:37 +0100
Subject: [PATCH 61/78] ARM: aarch64: mmu: Make zero page faulting
In-Reply-To: <20180316125354.23462-1-s.hauer@pengutronix.de>
References: <20180316125354.23462-1-s.hauer@pengutronix.de>
Message-ID: <20180316125354.23462-62-s.hauer@pengutronix.de>

Make zero page faulting which allows us to catch NULL pointer derefs.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/cpu/mmu_64.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/cpu/mmu_64.c b/arch/arm/cpu/mmu_64.c
index 20f6c387f3..094bc0ac62 100644
--- a/arch/arm/cpu/mmu_64.c
+++ b/arch/arm/cpu/mmu_64.c
@@ -316,6 +316,8 @@ static int mmu_init(void)
 	for_each_memory_bank(bank)
 		create_sections(bank->start, bank->start, bank->size, CACHED_MEM);
 
+	create_sections(0x0, 0x0, 0x1000, 0x0);
+
 	mmu_enable();
 
 	return 0;
-- 
2.16.1



From s.hauer at pengutronix.de  Fri Mar 16 05:53:06 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 16 Mar 2018 13:53:06 +0100
Subject: [PATCH 30/78] ARM: aarch64: Add relocation support
In-Reply-To: <20180316125354.23462-1-s.hauer@pengutronix.de>
References: <20180316125354.23462-1-s.hauer@pengutronix.de>
Message-ID: <20180316125354.23462-31-s.hauer@pengutronix.de>

This adds aarch64 support for relocating binaries linked with -pie.

Support is integrated into the already exisiting
relocate_to_current_adr() function which is now used for both arm32
and aarch64.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/cpu/common.c    | 38 ++++++++++++++++++++++++-------
 arch/arm/cpu/setupc_64.S | 58 ++++++++++++++++++++++++++++++++++++++++++++++++
 common/Kconfig           |  2 +-
 3 files changed, 89 insertions(+), 9 deletions(-)

diff --git a/arch/arm/cpu/common.c b/arch/arm/cpu/common.c
index 3766116d97..c317e502d0 100644
--- a/arch/arm/cpu/common.c
+++ b/arch/arm/cpu/common.c
@@ -24,39 +24,61 @@
 #include <asm-generic/memory_layout.h>
 #include <asm/sections.h>
 #include <asm/cache.h>
+#include <debug_ll.h>
+
+#define R_ARM_RELATIVE 23
+#define R_AARCH64_RELATIVE 1027
 
 /*
  * relocate binary to the currently running address
  */
 void relocate_to_current_adr(void)
 {
-	unsigned long offset;
+	unsigned long offset, offset_var;
 	unsigned long *dstart, *dend, *dynsym, *dynend;
 
 	/* Get offset between linked address and runtime address */
 	offset = get_runtime_offset();
+	offset_var = global_variable_offset();
 
-	dstart = (void *)__rel_dyn_start + offset;
-	dend = (void *)__rel_dyn_end + offset;
+	dstart = (void *)__rel_dyn_start + offset_var;
+	dend = (void *)__rel_dyn_end + offset_var;
 
-	dynsym = (void *)__dynsym_start + offset;
-	dynend = (void *)__dynsym_end + offset;
+	dynsym = (void *)__dynsym_start + offset_var;
+	dynend = (void *)__dynsym_end + offset_var;
 
 	while (dstart < dend) {
 		unsigned long *fixup = (unsigned long *)(*dstart + offset);
 		unsigned long type = *(dstart + 1);
+		int add;
+
+		if (ELF64_R_TYPE(type) == R_AARCH64_RELATIVE) {
+			unsigned long addend = *(dstart + 2);
 
-		if ((type & 0xff) == 0x17) {
+			*fixup = addend + offset;
+
+			add = 3;
+		} else if (ELF32_R_TYPE(type) == R_ARM_RELATIVE) {
 			*fixup = *fixup + offset;
-		} else {
+
+			add = 2;
+		} else if (ELF32_R_TYPE(type) == R_ARM_ABS32) {
 			int index = type >> 8;
 			unsigned long r = dynsym[index * 4 + 1];
 
 			*fixup = *fixup + r + offset;
+
+			add = 2;
+		} else {
+			putc_ll('>');
+			puthex_ll(type);
+			putc_ll('\n');
+			/* We're doomed */
+			panic(NULL);
 		}
 
 		*dstart += offset;
-		dstart += 2;
+		dstart += add;
 	}
 
 	memset(dynsym, 0, (unsigned long)dynend - (unsigned long)dynsym);
diff --git a/arch/arm/cpu/setupc_64.S b/arch/arm/cpu/setupc_64.S
index 3515854784..88c7899205 100644
--- a/arch/arm/cpu/setupc_64.S
+++ b/arch/arm/cpu/setupc_64.S
@@ -16,3 +16,61 @@ ENTRY(setup_c)
 	mov	x30, x15
 	ret
 ENDPROC(setup_c)
+
+/*
+ * void relocate_to_adr(unsigned long targetadr)
+ *
+ * Copy binary to targetadr, relocate code and continue
+ * executing at new address.
+ */
+.section .text.relocate_to_adr
+ENTRY(relocate_to_adr)
+					/* x0: target address */
+
+	stp	x19, x20, [sp, #-16]!
+
+	mov	x19, lr
+
+	mov	x6, x0
+
+	bl	get_runtime_offset
+	mov	x5, x0
+
+	ldr	x0, =_text
+	mov	x8, x0
+
+	add	x1, x0, x5		/* x1: from address */
+
+	cmp	x1, x6			/* already at correct address? */
+	beq	1f			/* yes, skip copy to new address */
+
+	ldr	x2, =__bss_start
+
+	sub	x2, x2, x0		/* x2: size */
+	mov	x0, x6			/* x0: target */
+
+	/* adjust return address */
+	sub	x19, x19, x1		/* sub address where we are actually running */
+	add	x19, x19, x0		/* add address where we are going to run */
+
+	bl	memcpy			/* copy binary */
+
+#ifdef CONFIG_MMU
+	bl	arm_early_mmu_cache_flush
+#endif
+	mov	x0,#0
+	ic	ivau, x0	/* flush icache */
+
+	ldr	x0,=1f
+	sub	x0, x0, x8
+	add	x0, x0, x6
+	br	x0			/* jump to relocated address */
+1:
+	bl	relocate_to_current_adr	/* relocate binary */
+
+	mov	lr, x19
+
+	ldp	x19, x20, [sp], #16
+	ret
+
+ENDPROC(relocate_to_adr)
diff --git a/common/Kconfig b/common/Kconfig
index af71d6888a..b7000c4d73 100644
--- a/common/Kconfig
+++ b/common/Kconfig
@@ -344,7 +344,7 @@ config KALLSYMS
 	  This is useful to print a nice backtrace when an exception occurs.
 
 config RELOCATABLE
-	depends on PPC || (ARM && !CPU_V8)
+	depends on PPC || ARM
 	bool "generate relocatable barebox binary"
 	help
 	  A non relocatable barebox binary will run at it's compiled in
-- 
2.16.1



From s.hauer at pengutronix.de  Fri Mar 16 05:53:07 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 16 Mar 2018 13:53:07 +0100
Subject: [PATCH 31/78] ARM: aarch64: fix pbl linker script for aarch64
In-Reply-To: <20180316125354.23462-1-s.hauer@pengutronix.de>
References: <20180316125354.23462-1-s.hauer@pengutronix.de>
Message-ID: <20180316125354.23462-32-s.hauer@pengutronix.de>

Fix output format for aarch64. Also, relocation fixup symbols are in
rela section rather than rel section.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/lib/pbl.lds.S | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/arm/lib/pbl.lds.S b/arch/arm/lib/pbl.lds.S
index be0a4a3b1a..9df1800543 100644
--- a/arch/arm/lib/pbl.lds.S
+++ b/arch/arm/lib/pbl.lds.S
@@ -25,8 +25,13 @@
 #define BASE	(TEXT_BASE - SZ_2M)
 #endif
 
+#ifdef CONFIG_CPU_32
 OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
 OUTPUT_ARCH(arm)
+#else
+OUTPUT_FORMAT("elf64-littleaarch64", "elf64-littleaarch64", "elf64-littleaarch64")
+OUTPUT_ARCH(aarch64)
+#endif
 SECTIONS
 {
 	. = BASE;
@@ -62,7 +67,11 @@ SECTIONS
 	.data : { *(.data*) }
 
 	.rel_dyn_start : { *(.__rel_dyn_start) }
+#ifdef CONFIG_CPU_32
 	.rel.dyn : { *(.rel*) }
+#else
+	.rela.dyn : { *(.rela*) }
+#endif
 	.rel_dyn_end : { *(.__rel_dyn_end) }
 
 	.__dynsym_start :  { *(.__dynsym_start) }
-- 
2.16.1



From s.hauer at pengutronix.de  Fri Mar 16 05:52:51 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 16 Mar 2018 13:52:51 +0100
Subject: [PATCH 15/78] ARM: aarch64: Add runtime-offset
In-Reply-To: <20180316125354.23462-1-s.hauer@pengutronix.de>
References: <20180316125354.23462-1-s.hauer@pengutronix.de>
Message-ID: <20180316125354.23462-16-s.hauer@pengutronix.de>

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/lib64/Makefile         |  1 +
 arch/arm/lib64/runtime-offset.S | 19 +++++++++++++++++++
 2 files changed, 20 insertions(+)
 create mode 100644 arch/arm/lib64/runtime-offset.S

diff --git a/arch/arm/lib64/Makefile b/arch/arm/lib64/Makefile
index 4b7b7e3cc5..679ca556e5 100644
--- a/arch/arm/lib64/Makefile
+++ b/arch/arm/lib64/Makefile
@@ -3,5 +3,6 @@ obj-y	+= div0.o
 obj-$(CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS)	+= memcpy.o
 obj-$(CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS)	+= memset.o
 extra-y += barebox.lds
+obj-pbl-y   += runtime-offset.o
 
 pbl-y	+= div0.o
diff --git a/arch/arm/lib64/runtime-offset.S b/arch/arm/lib64/runtime-offset.S
new file mode 100644
index 0000000000..177ca64784
--- /dev/null
+++ b/arch/arm/lib64/runtime-offset.S
@@ -0,0 +1,19 @@
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+
+.section ".text_bare_init","ax"
+
+/*
+ * Get the offset between the link address and the address
+ * we are currently running at.
+ */
+ENTRY(get_runtime_offset)
+1:	adr x0, 1b
+	ldr x1, linkadr
+	subs x0, x0, x1
+	ret
+
+.align 3
+linkadr:
+.quad get_runtime_offset
+ENDPROC(get_runtime_offset)
-- 
2.16.1



From s.hauer at pengutronix.de  Fri Mar 16 05:53:22 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 16 Mar 2018 13:53:22 +0100
Subject: [PATCH 46/78] ARM: aarch64: mmu: Fix disabling the MMU
In-Reply-To: <20180316125354.23462-1-s.hauer@pengutronix.de>
References: <20180316125354.23462-1-s.hauer@pengutronix.de>
Message-ID: <20180316125354.23462-47-s.hauer@pengutronix.de>

Do it as U-Boot: Disable MMU first, then flush caches and finally
invalidate tlbs. I wish I could reference some document instead of
U-Boot code, but I haven't found anything.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/cpu/mmu_64.c | 7 ++-----
 1 file changed, 2 insertions(+), 5 deletions(-)

diff --git a/arch/arm/cpu/mmu_64.c b/arch/arm/cpu/mmu_64.c
index 165ff5bac6..6606405b21 100644
--- a/arch/arm/cpu/mmu_64.c
+++ b/arch/arm/cpu/mmu_64.c
@@ -329,12 +329,9 @@ void mmu_disable(void)
 	cr = get_cr();
 	cr &= ~(CR_M | CR_C);
 
-	tlb_invalidate();
-
-	dsb();
-	isb();
-
 	set_cr(cr);
+	v8_flush_dcache_all();
+	tlb_invalidate();
 
 	dsb();
 	isb();
-- 
2.16.1



From s.hauer at pengutronix.de  Fri Mar 16 05:53:24 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 16 Mar 2018 13:53:24 +0100
Subject: [PATCH 48/78] dma: Use dma_addr_t as type for DMA addresses
In-Reply-To: <20180316125354.23462-1-s.hauer@pengutronix.de>
References: <20180316125354.23462-1-s.hauer@pengutronix.de>
Message-ID: <20180316125354.23462-49-s.hauer@pengutronix.de>

DMA addresses are not necessarily the same as unsigned long. Fix
the type for the dma_sync_single_* operations.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/cpu/mmu.c          | 4 ++--
 arch/mips/lib/dma-default.c | 4 ++--
 include/dma.h               | 4 ++--
 3 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/arch/arm/cpu/mmu.c b/arch/arm/cpu/mmu.c
index de0b631981..fc71cf03cd 100644
--- a/arch/arm/cpu/mmu.c
+++ b/arch/arm/cpu/mmu.c
@@ -575,7 +575,7 @@ void dma_free_coherent(void *mem, dma_addr_t dma_handle, size_t size)
 	free(mem);
 }
 
-void dma_sync_single_for_cpu(unsigned long address, size_t size,
+void dma_sync_single_for_cpu(dma_addr_t address, size_t size,
 			     enum dma_data_direction dir)
 {
 	if (dir != DMA_TO_DEVICE) {
@@ -585,7 +585,7 @@ void dma_sync_single_for_cpu(unsigned long address, size_t size,
 	}
 }
 
-void dma_sync_single_for_device(unsigned long address, size_t size,
+void dma_sync_single_for_device(dma_addr_t address, size_t size,
 				enum dma_data_direction dir)
 {
 	if (dir == DMA_FROM_DEVICE) {
diff --git a/arch/mips/lib/dma-default.c b/arch/mips/lib/dma-default.c
index 9b2fe7d410..71c1e423b7 100644
--- a/arch/mips/lib/dma-default.c
+++ b/arch/mips/lib/dma-default.c
@@ -44,13 +44,13 @@ static inline void __dma_sync_mips(void *addr, size_t size,
 }
 #endif
 
-void dma_sync_single_for_cpu(unsigned long address, size_t size,
+void dma_sync_single_for_cpu(dma_addr_t address, size_t size,
 			     enum dma_data_direction dir)
 {
 	__dma_sync_mips(address, size, dir);
 }
 
-void dma_sync_single_for_device(unsigned long address, size_t size,
+void dma_sync_single_for_device(dma_addr_t address, size_t size,
 				enum dma_data_direction dir)
 {
 	__dma_sync_mips(address, size, dir);
diff --git a/include/dma.h b/include/dma.h
index 4d31797968..29d94c0a52 100644
--- a/include/dma.h
+++ b/include/dma.h
@@ -31,10 +31,10 @@ static inline void dma_free(void *mem)
 #endif
 
 /* streaming DMA - implement the below calls to support HAS_DMA */
-void dma_sync_single_for_cpu(unsigned long address, size_t size,
+void dma_sync_single_for_cpu(dma_addr_t address, size_t size,
 			     enum dma_data_direction dir);
 
-void dma_sync_single_for_device(unsigned long address, size_t size,
+void dma_sync_single_for_device(dma_addr_t address, size_t size,
 				enum dma_data_direction dir);
 
 void *dma_alloc_coherent(size_t size, dma_addr_t *dma_handle);
-- 
2.16.1



From s.hauer at pengutronix.de  Fri Mar 16 05:53:46 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 16 Mar 2018 13:53:46 +0100
Subject: [PATCH 70/78] bootm: provide handlers the start of the OS image
In-Reply-To: <20180316125354.23462-1-s.hauer@pengutronix.de>
References: <20180316125354.23462-1-s.hauer@pengutronix.de>
Message-ID: <20180316125354.23462-71-s.hauer@pengutronix.de>

The bootm code needs to read the beginning of the OS image in order to
determine the filetype. If it does so already, then we can provide the
handlers the buffer. This can help the handlers to find some image
metadata before loading the full image.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 common/bootm.c  | 10 +++++++++-
 include/bootm.h |  7 +++++++
 2 files changed, 16 insertions(+), 1 deletion(-)

diff --git a/common/bootm.c b/common/bootm.c
index 3e48ca1d88..5ff6683fe7 100644
--- a/common/bootm.c
+++ b/common/bootm.c
@@ -529,6 +529,7 @@ int bootm_boot(struct bootm_data *bootm_data)
 	struct image_handler *handler;
 	int ret;
 	enum filetype os_type;
+	size_t size;
 
 	if (!bootm_data->os_file) {
 		printf("no image given\n");
@@ -548,7 +549,13 @@ int bootm_boot(struct bootm_data *bootm_data)
 	data->os_address = bootm_data->os_address;
 	data->os_entry = bootm_data->os_entry;
 
-	os_type = file_name_detect_type(data->os_file);
+	ret = read_file_2(data->os_file, &size, &data->os_header, PAGE_SIZE);
+	if (ret < 0 && ret != -EFBIG)
+		goto err_out;
+	if (size < PAGE_SIZE)
+		goto err_out;
+
+	os_type = file_detect_type(data->os_header, PAGE_SIZE);
 	if ((int)os_type < 0) {
 		printf("could not open %s: %s\n", data->os_file,
 				strerror(-os_type));
@@ -674,6 +681,7 @@ err_out:
 		of_delete_node(data->of_root_node);
 
 	globalvar_remove("linux.bootargs.bootm.appendroot");
+	free(data->os_header);
 	free(data->os_file);
 	free(data->oftree_file);
 	free(data->initrd_file);
diff --git a/include/bootm.h b/include/bootm.h
index 35c18dc276..62951d6058 100644
--- a/include/bootm.h
+++ b/include/bootm.h
@@ -81,6 +81,13 @@ struct image_data {
 	struct fdt_header *oftree;
 	struct resource *oftree_res;
 
+	/*
+	 * The first PAGE_SIZE bytes of the OS image. Can be used by the image
+	 * handlers to analyze the OS image before actually loading the bulk of
+	 * it.
+	 */
+	void *os_header;
+
 	enum bootm_verify verify;
 	int verbose;
 	int force;
-- 
2.16.1



From s.hauer at pengutronix.de  Fri Mar 16 05:52:50 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 16 Mar 2018 13:52:50 +0100
Subject: [PATCH 14/78] ARM: get_runtime_offset() returns unsigned long
In-Reply-To: <20180316125354.23462-1-s.hauer@pengutronix.de>
References: <20180316125354.23462-1-s.hauer@pengutronix.de>
Message-ID: <20180316125354.23462-15-s.hauer@pengutronix.de>

Change return type from uint32_t to unsigned long which is suitable for
aarch64 aswell.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/include/asm/barebox-arm.h        | 2 +-
 arch/arm/mach-mvebu/include/mach/common.h | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/include/asm/barebox-arm.h b/arch/arm/include/asm/barebox-arm.h
index 170839aaad..1dccb8965e 100644
--- a/arch/arm/include/asm/barebox-arm.h
+++ b/arch/arm/include/asm/barebox-arm.h
@@ -42,7 +42,7 @@ int	dram_init (void);
 extern char __exceptions_start[], __exceptions_stop[];
 
 void board_init_lowlevel(void);
-uint32_t get_runtime_offset(void);
+unsigned long get_runtime_offset(void);
 
 void setup_c(void);
 void relocate_to_current_adr(void);
diff --git a/arch/arm/mach-mvebu/include/mach/common.h b/arch/arm/mach-mvebu/include/mach/common.h
index aa4babcfa7..8e15723fbe 100644
--- a/arch/arm/mach-mvebu/include/mach/common.h
+++ b/arch/arm/mach-mvebu/include/mach/common.h
@@ -25,7 +25,7 @@
 #define MVEBU_REMAP_INT_REG_BASE	0xf1000000
 
 /* #including <asm/barebox-arm.h> yields a circle, so we need a forward decl */
-uint32_t get_runtime_offset(void);
+unsigned long get_runtime_offset(void);
 
 static inline void __iomem *mvebu_get_initial_int_reg_base(void)
 {
-- 
2.16.1



From s.hauer at pengutronix.de  Fri Mar 16 05:53:31 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 16 Mar 2018 13:53:31 +0100
Subject: [PATCH 55/78] ARM: aarch64: Setup exception vectors in initcall
In-Reply-To: <20180316125354.23462-1-s.hauer@pengutronix.de>
References: <20180316125354.23462-1-s.hauer@pengutronix.de>
Message-ID: <20180316125354.23462-56-s.hauer@pengutronix.de>

The vectors are currently configured in arm_cpu_lowlevel_init(). This
shall be callable from PBL, but here the vectors are not available so
calling it from PBL will result in a linker error.
Move the vector setup to an initcall.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/cpu/interrupts_64.c | 19 +++++++++++++++++++
 arch/arm/cpu/lowlevel_64.S   |  4 ----
 2 files changed, 19 insertions(+), 4 deletions(-)

diff --git a/arch/arm/cpu/interrupts_64.c b/arch/arm/cpu/interrupts_64.c
index 81fd941cfa..b3bd0aa5a4 100644
--- a/arch/arm/cpu/interrupts_64.c
+++ b/arch/arm/cpu/interrupts_64.c
@@ -22,6 +22,7 @@
 #include <asm/ptrace.h>
 #include <asm/unwind.h>
 #include <init.h>
+#include <asm/system.h>
 
 /**
  * Display current register set content
@@ -114,3 +115,21 @@ int data_abort_unmask(void)
 
 	return arm_data_abort_occurred != 0;
 }
+
+extern unsigned long vectors;
+
+static int aarch64_init_vectors(void)
+{
+        unsigned int el;
+
+        el = current_el();
+        if (el == 1)
+                asm volatile("msr vbar_el1, %0" : : "r" (&vectors) : "cc");
+        else if (el == 2)
+                asm volatile("msr vbar_el2, %0" : : "r" (&vectors) : "cc");
+        else
+                asm volatile("msr vbar_el3, %0" : : "r" (&vectors) : "cc");
+
+	return 0;
+}
+pure_initcall(aarch64_init_vectors);
diff --git a/arch/arm/cpu/lowlevel_64.S b/arch/arm/cpu/lowlevel_64.S
index 4850895169..a66556f1ad 100644
--- a/arch/arm/cpu/lowlevel_64.S
+++ b/arch/arm/cpu/lowlevel_64.S
@@ -4,7 +4,6 @@
 
 .section ".text_bare_init_","ax"
 ENTRY(arm_cpu_lowlevel_init)
-	adr	x0, vectors
 	mrs	x1, CurrentEL
 	cmp	x1, #0xC		/* Check EL3 state */
 	b.eq	1f
@@ -14,7 +13,6 @@ ENTRY(arm_cpu_lowlevel_init)
 	b.eq	3f
 
 1:
-	msr	vbar_el3, x0
 	mov	x0, #1			/* Non-Secure EL0/1 */
 	orr	x0, x0, #(1 << 10)	/* 64-bit EL2 */
 	msr	scr_el3, x0
@@ -22,14 +20,12 @@ ENTRY(arm_cpu_lowlevel_init)
 	b	done
 
 2:
-	msr	vbar_el2, x0
 	mov	x0, #0x33ff		/* Enable FP/SIMD */
 	msr	cptr_el2, x0
 	b	done
 
 
 3:
-	msr	vbar_el1, x0
 	mov	x0, #(3 << 20)		/* Enable FP/SIMD */
 	msr	cpacr_el1, x0
 	b	done
-- 
2.16.1



From s.hauer at pengutronix.de  Fri Mar 16 05:53:20 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 16 Mar 2018 13:53:20 +0100
Subject: [PATCH 44/78] ARM: aarch64: mmu: No need to disable icache
In-Reply-To: <20180316125354.23462-1-s.hauer@pengutronix.de>
References: <20180316125354.23462-1-s.hauer@pengutronix.de>
Message-ID: <20180316125354.23462-45-s.hauer@pengutronix.de>

When the MMU is disabled there is no need to disable the icache. Leave
it enabled.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/cpu/mmu_64.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/cpu/mmu_64.c b/arch/arm/cpu/mmu_64.c
index 7932185885..c8c3c9d84f 100644
--- a/arch/arm/cpu/mmu_64.c
+++ b/arch/arm/cpu/mmu_64.c
@@ -330,7 +330,7 @@ void mmu_disable(void)
 		arm_mmu_not_initialized_error();
 
 	cr = get_cr();
-	cr &= ~(CR_M | CR_C | CR_I);
+	cr &= ~(CR_M | CR_C);
 
 	tlb_invalidate();
 
-- 
2.16.1



From s.hauer at pengutronix.de  Fri Mar 16 05:53:00 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 16 Mar 2018 13:53:00 +0100
Subject: [PATCH 24/78] ARM: aarch64: cache: no need to ifdef prototypes
In-Reply-To: <20180316125354.23462-1-s.hauer@pengutronix.de>
References: <20180316125354.23462-1-s.hauer@pengutronix.de>
Message-ID: <20180316125354.23462-25-s.hauer@pengutronix.de>

There's no need to ifdef function prototypes, so remove the
ifdefs. While there also remove unnecessary "export" for functions.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/include/asm/cache.h | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h
index 503bf8a0f7..0822cb78c3 100644
--- a/arch/arm/include/asm/cache.h
+++ b/arch/arm/include/asm/cache.h
@@ -1,13 +1,11 @@
 #ifndef __ASM_CACHE_H
 #define __ASM_CACHE_H
 
-#ifdef CONFIG_CPU_64v8
-extern void v8_invalidate_icache_all(void);
+void v8_invalidate_icache_all(void);
 void v8_flush_dcache_all(void);
 void v8_invalidate_dcache_all(void);
 void v8_flush_dcache_range(unsigned long start, unsigned long end);
 void v8_inv_dcache_range(unsigned long start, unsigned long end);
-#endif
 
 static inline void icache_invalidate(void)
 {
-- 
2.16.1



From s.hauer at pengutronix.de  Fri Mar 16 05:52:59 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 16 Mar 2018 13:52:59 +0100
Subject: [PATCH 23/78] ARM: aarch64: cache: Add v8_inv_dcache_range
In-Reply-To: <20180316125354.23462-1-s.hauer@pengutronix.de>
References: <20180316125354.23462-1-s.hauer@pengutronix.de>
Message-ID: <20180316125354.23462-24-s.hauer@pengutronix.de>

implement v8_flush_dcache_range based on v8_inv_dcache_range. While
at it add a prototype for v8_inv_dcache_range.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/cpu/cache-armv8.S   | 19 +++++++++++++++++++
 arch/arm/include/asm/cache.h |  2 ++
 2 files changed, 21 insertions(+)

diff --git a/arch/arm/cpu/cache-armv8.S b/arch/arm/cpu/cache-armv8.S
index 82b2f81778..3e21b35913 100644
--- a/arch/arm/cpu/cache-armv8.S
+++ b/arch/arm/cpu/cache-armv8.S
@@ -148,6 +148,25 @@ ENTRY(v8_flush_dcache_range)
 	ret
 ENDPROC(v8_flush_dcache_range)
 
+.section .text.v8_inv_dcache_range
+ENTRY(v8_inv_dcache_range)
+	mrs	x3, ctr_el0
+	lsr	x3, x3, #16
+	and	x3, x3, #0xf
+	mov	x2, #4
+	lsl	x2, x2, x3		/* cache line size */
+
+	/* x2 <- minimal cache line size in cache system */
+	sub	x3, x2, #1
+	bic	x0, x0, x3
+1:	dc	ivac, x0	/* invalidate data or unified cache */
+	add	x0, x0, x2
+	cmp	x0, x1
+	b.lo	1b
+	dsb	sy
+	ret
+ENDPROC(v8_inv_dcache_range)
+
 /*
  * void v8_invalidate_icache_all(void)
  *
diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h
index 406a9d5d99..503bf8a0f7 100644
--- a/arch/arm/include/asm/cache.h
+++ b/arch/arm/include/asm/cache.h
@@ -5,6 +5,8 @@
 extern void v8_invalidate_icache_all(void);
 void v8_flush_dcache_all(void);
 void v8_invalidate_dcache_all(void);
+void v8_flush_dcache_range(unsigned long start, unsigned long end);
+void v8_inv_dcache_range(unsigned long start, unsigned long end);
 #endif
 
 static inline void icache_invalidate(void)
-- 
2.16.1



From s.hauer at pengutronix.de  Fri Mar 16 05:52:54 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 16 Mar 2018 13:52:54 +0100
Subject: [PATCH 18/78] ARM: bitops: remove unnecessary #ifdef
In-Reply-To: <20180316125354.23462-1-s.hauer@pengutronix.de>
References: <20180316125354.23462-1-s.hauer@pengutronix.de>
Message-ID: <20180316125354.23462-19-s.hauer@pengutronix.de>

__fls() must always be provided, not only for aarch64, so remove
unnecessary #ifdef. This didn't show up because nobody directly uses
__fls() in barebox. Only aarch64 indirectly uses __fls() for
implementing fls64().

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/include/asm/bitops.h | 2 --
 1 file changed, 2 deletions(-)

diff --git a/arch/arm/include/asm/bitops.h b/arch/arm/include/asm/bitops.h
index 344e288bae..cd356c5e3d 100644
--- a/arch/arm/include/asm/bitops.h
+++ b/arch/arm/include/asm/bitops.h
@@ -162,9 +162,7 @@ static inline int constant_fls(int x)
 #include <asm-generic/bitops/fls.h>
 #endif		/* __ARM__USE_GENERIC_FF */
 
-#if __LINUX_ARM_ARCH__ == 8
 #include <asm-generic/bitops/__fls.h>
-#endif
 
 #include <asm-generic/bitops/fls64.h>
 
-- 
2.16.1



From s.hauer at pengutronix.de  Fri Mar 16 05:52:52 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 16 Mar 2018 13:52:52 +0100
Subject: [PATCH 16/78] ARM: aarch64: implement get_pc()
In-Reply-To: <20180316125354.23462-1-s.hauer@pengutronix.de>
References: <20180316125354.23462-1-s.hauer@pengutronix.de>
Message-ID: <20180316125354.23462-17-s.hauer@pengutronix.de>

The arm32 version can't be used on aarch64, implement an aarch64
specific version.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/include/asm/common.h | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/arch/arm/include/asm/common.h b/arch/arm/include/asm/common.h
index 07ae619cea..97bfdc43f5 100644
--- a/arch/arm/include/asm/common.h
+++ b/arch/arm/include/asm/common.h
@@ -4,13 +4,19 @@
 static inline unsigned long get_pc(void)
 {
 	unsigned long pc;
-
+#ifdef CONFIG_CPU_32
 	__asm__ __volatile__(
                 "mov    %0, pc\n"
                 : "=r" (pc)
                 :
                 : "memory");
-
+#else
+	__asm__ __volatile__(
+                "adr    %0, .\n"
+                : "=r" (pc)
+                :
+                : "memory");
+#endif
 	return pc;
 }
 
-- 
2.16.1



From s.hauer at pengutronix.de  Fri Mar 16 05:53:18 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 16 Mar 2018 13:53:18 +0100
Subject: [PATCH 42/78] ARM: aarch64: mmu: Fix PTE_TYPE_* flags
In-Reply-To: <20180316125354.23462-1-s.hauer@pengutronix.de>
References: <20180316125354.23462-1-s.hauer@pengutronix.de>
Message-ID: <20180316125354.23462-43-s.hauer@pengutronix.de>

When we reach level 3 page tables we set the PTE_TYPE_PAGE bit in attr.
This is wrong since in the outer loop we can fall back to a lower level
in which case the PTE_TYPE_PAGE may not be set.
Fix this by not modifying attr and instead compose the *pte value when
needed.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/cpu/mmu_64.c | 11 +++++------
 1 file changed, 5 insertions(+), 6 deletions(-)

diff --git a/arch/arm/cpu/mmu_64.c b/arch/arm/cpu/mmu_64.c
index 2934ad12cd..c7590fa33c 100644
--- a/arch/arm/cpu/mmu_64.c
+++ b/arch/arm/cpu/mmu_64.c
@@ -208,13 +208,12 @@ static void map_region(uint64_t virt, uint64_t phys, uint64_t size, uint64_t att
 
 			pte = table + idx;
 
-			if (level == 3)
-				attr |= PTE_TYPE_PAGE;
-			else
-				attr |= PTE_TYPE_BLOCK;
-
 			if (size >= block_size && IS_ALIGNED(addr, block_size)) {
-				*pte = phys | attr;
+				if (level == 3)
+					*pte = phys | attr | PTE_TYPE_PAGE;
+				else
+					*pte = phys | attr | PTE_TYPE_BLOCK;
+
 				addr += block_size;
 				phys += block_size;
 				size -= block_size;
-- 
2.16.1



From s.hauer at pengutronix.de  Fri Mar 16 05:53:10 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 16 Mar 2018 13:53:10 +0100
Subject: [PATCH 34/78] ARM: aarch64: mmu: fix creation of flat mapping
In-Reply-To: <20180316125354.23462-1-s.hauer@pengutronix.de>
References: <20180316125354.23462-1-s.hauer@pengutronix.de>
Message-ID: <20180316125354.23462-35-s.hauer@pengutronix.de>

During initialization of the page tables we want to create a flat
uncached mapping for the whole address space. create_sections() takes
the size in bytes, not in MiB as assumed by the callees. Fix this.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/cpu/mmu_64.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/cpu/mmu_64.c b/arch/arm/cpu/mmu_64.c
index 6e22da9a26..fe1e5410f7 100644
--- a/arch/arm/cpu/mmu_64.c
+++ b/arch/arm/cpu/mmu_64.c
@@ -258,8 +258,8 @@ static int mmu_init(void)
 
 	pr_debug("ttb: 0x%p\n", ttb);
 
-	/* create a flat mapping using 1MiB sections */
-	create_sections(0, 0, GRANULE_SIZE, UNCACHED_MEM);
+	/* create a flat mapping */
+	create_sections(0, 0, 1UL << (BITS_PER_VA - 1), UNCACHED_MEM);
 
 	/* Map sdram cached. */
 	for_each_memory_bank(bank)
@@ -310,7 +310,7 @@ void mmu_early_enable(uint64_t membase, uint64_t memsize, uint64_t _ttb)
 
 	set_ttbr_tcr_mair(current_el(), (uint64_t)ttb, TCR_FLAGS, UNCACHED_MEM);
 
-	create_sections(0, 0, 4096, UNCACHED_MEM);
+	create_sections(0, 0, 1UL << (BITS_PER_VA - 1), UNCACHED_MEM);
 
 	create_sections(membase, membase, memsize, CACHED_MEM);
 
-- 
2.16.1



From s.hauer at pengutronix.de  Fri Mar 16 05:53:44 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 16 Mar 2018 13:53:44 +0100
Subject: [PATCH 68/78] filetype: Detect ARM aarch64 Linux images
In-Reply-To: <20180316125354.23462-1-s.hauer@pengutronix.de>
References: <20180316125354.23462-1-s.hauer@pengutronix.de>
Message-ID: <20180316125354.23462-69-s.hauer@pengutronix.de>

ARM aarch64 Linux image have a special type. Allow to detect them.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 common/filetype.c  | 3 +++
 include/filetype.h | 1 +
 2 files changed, 4 insertions(+)

diff --git a/common/filetype.c b/common/filetype.c
index 71691fd813..444ec14cc4 100644
--- a/common/filetype.c
+++ b/common/filetype.c
@@ -67,6 +67,7 @@ static const struct filetype_str filetype_str[] = {
 	[filetype_socfpga_xload] = { "SoCFPGA prebootloader image", "socfpga-xload" },
 	[filetype_kwbimage_v1] = { "MVEBU kwbimage (v1)", "kwb" },
 	[filetype_android_sparse] = { "Android sparse image", "sparse" },
+	[filetype_arm64_linux_image] = { "ARM aarch64 Linux image", "aarch64-linux" },
 };
 
 const char *file_type_to_string(enum filetype f)
@@ -296,6 +297,8 @@ enum filetype file_detect_type(const void *_buf, size_t bufsize)
 		return filetype_mips_barebox;
 	if (buf[0] == be32_to_cpu(0x534F4659))
 		return filetype_bpk;
+	if (le32_to_cpu(buf[14]) == 0x644d5241)
+		return filetype_arm64_linux_image;
 	if ((buf8[0] == 0x5a || buf8[0] == 0x69 || buf8[0] == 0x78 ||
 	     buf8[0] == 0x8b || buf8[0] == 0x9c) &&
 	    buf8[0x1] == 0 && buf8[0x2] == 0 && buf8[0x3] == 0 &&
diff --git a/include/filetype.h b/include/filetype.h
index ec5aea2635..9986938ddb 100644
--- a/include/filetype.h
+++ b/include/filetype.h
@@ -40,6 +40,7 @@ enum filetype {
 	filetype_socfpga_xload,
 	filetype_kwbimage_v1,
 	filetype_android_sparse,
+	filetype_arm64_linux_image,
 	filetype_max,
 };
 
-- 
2.16.1



From s.hauer at pengutronix.de  Fri Mar 16 05:53:08 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 16 Mar 2018 13:53:08 +0100
Subject: [PATCH 32/78] ARM: aarch64: mmu: Allocate page tables dynamically
In-Reply-To: <20180316125354.23462-1-s.hauer@pengutronix.de>
References: <20180316125354.23462-1-s.hauer@pengutronix.de>
Message-ID: <20180316125354.23462-33-s.hauer@pengutronix.de>

Current code allocates 16KiB for page tables. Whenever a new
table is needed an index is increased, but the bounds of this
index are never checked. Allocate the page tables dynamically
to solve this.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/cpu/mmu_64.c | 9 ++-------
 1 file changed, 2 insertions(+), 7 deletions(-)

diff --git a/arch/arm/cpu/mmu_64.c b/arch/arm/cpu/mmu_64.c
index 4803a85e4c..eb54097514 100644
--- a/arch/arm/cpu/mmu_64.c
+++ b/arch/arm/cpu/mmu_64.c
@@ -38,7 +38,6 @@
 #define UNCACHED_MEM    (PMD_ATTRINDX(MT_NORMAL_NC) | PMD_SECT_S | PMD_SECT_AF | PMD_TYPE_SECT)
 
 static uint64_t *ttb;
-static int free_idx;
 
 static void arm_mmu_not_initialized_error(void)
 {
@@ -108,13 +107,11 @@ static void set_table(uint64_t *pt, uint64_t *table_addr)
 
 static uint64_t *create_table(void)
 {
-	uint64_t *new_table = ttb + free_idx * GRANULE_SIZE;
+	uint64_t *new_table = xmemalign(GRANULE_SIZE, GRANULE_SIZE);
 
 	/* Mark all entries as invalid */
 	memset(new_table, 0, GRANULE_SIZE);
 
-	free_idx++;
-
 	return new_table;
 }
 
@@ -253,8 +250,7 @@ static int mmu_init(void)
 			pr_crit("Critical Error: Can't request SDRAM region for ttb at %p\n",
 				ttb);
 	} else {
-		ttb = memalign(GRANULE_SIZE, SZ_16K);
-		free_idx = 1;
+		ttb = xmemalign(GRANULE_SIZE, GRANULE_SIZE);
 
 		memset(ttb, 0, GRANULE_SIZE);
 
@@ -312,7 +308,6 @@ void mmu_early_enable(uint64_t membase, uint64_t memsize, uint64_t _ttb)
 	ttb = (uint64_t *)_ttb;
 
 	memset(ttb, 0, GRANULE_SIZE);
-	free_idx = 1;
 
 	set_ttbr_tcr_mair(current_el(), (uint64_t)ttb, TCR_FLAGS, UNCACHED_MEM);
 
-- 
2.16.1



From s.hauer at pengutronix.de  Fri Mar 16 05:53:49 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 16 Mar 2018 13:53:49 +0100
Subject: [PATCH 73/78] ARM: cache-armv4: Fix wrong section
In-Reply-To: <20180316125354.23462-1-s.hauer@pengutronix.de>
References: <20180316125354.23462-1-s.hauer@pengutronix.de>
Message-ID: <20180316125354.23462-74-s.hauer@pengutronix.de>

The v4_mmu_cache_on function should be in a section with the same name.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/cpu/cache-armv4.S | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/cpu/cache-armv4.S b/arch/arm/cpu/cache-armv4.S
index 1d1a1e32bf..db87de17e9 100644
--- a/arch/arm/cpu/cache-armv4.S
+++ b/arch/arm/cpu/cache-armv4.S
@@ -3,7 +3,7 @@
 
 #define CACHE_DLINESIZE 32
 
-.section .text.__mmu_cache_on
+.section .text.v4_mmu_cache_on
 ENTRY(v4_mmu_cache_on)
 		mov	r12, lr
 #ifdef CONFIG_MMU
-- 
2.16.1



From s.hauer at pengutronix.de  Fri Mar 16 05:52:53 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 16 Mar 2018 13:52:53 +0100
Subject: [PATCH 17/78] ARM: Use generic ffz()
In-Reply-To: <20180316125354.23462-1-s.hauer@pengutronix.de>
References: <20180316125354.23462-1-s.hauer@pengutronix.de>
Message-ID: <20180316125354.23462-18-s.hauer@pengutronix.de>

The generic ffz() from <asm-generic/bitops/ffz.h> works like our
ARM specific variant except that the generic variant has 64bit word size
support. Use the generic variant to fix ffz() for aarch64.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/include/asm/bitops.h | 18 +-----------------
 1 file changed, 1 insertion(+), 17 deletions(-)

diff --git a/arch/arm/include/asm/bitops.h b/arch/arm/include/asm/bitops.h
index b51225efe5..344e288bae 100644
--- a/arch/arm/include/asm/bitops.h
+++ b/arch/arm/include/asm/bitops.h
@@ -156,23 +156,7 @@ static inline int constant_fls(int x)
 #define __ffs(x) (ffs(x) - 1)
 #define ffz(x) __ffs(~(x))
 #else		/* ! __ARM__USE_GENERIC_FF */
-/*
- * ffz = Find First Zero in word. Undefined if no zero exists,
- * so code should check against ~0UL first..
- */
-static inline unsigned long ffz(unsigned long word)
-{
-	int k;
-
-	word = ~word;
-	k = 31;
-	if (word & 0x0000ffff) { k -= 16; word <<= 16; }
-	if (word & 0x00ff0000) { k -= 8;  word <<= 8;  }
-	if (word & 0x0f000000) { k -= 4;  word <<= 4;  }
-	if (word & 0x30000000) { k -= 2;  word <<= 2;  }
-	if (word & 0x40000000) { k -= 1; }
-	return k;
-}
+#include <asm-generic/bitops/ffz.h>
 #include <asm-generic/bitops/__ffs.h>
 #include <asm-generic/bitops/ffs.h>
 #include <asm-generic/bitops/fls.h>
-- 
2.16.1



From s.hauer at pengutronix.de  Fri Mar 16 05:53:50 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 16 Mar 2018 13:53:50 +0100
Subject: [PATCH 74/78] ARM: build: Remove duplicate file compilation
In-Reply-To: <20180316125354.23462-1-s.hauer@pengutronix.de>
References: <20180316125354.23462-1-s.hauer@pengutronix.de>
Message-ID: <20180316125354.23462-75-s.hauer@pengutronix.de>

cache.o is already obj-y, drop unnecessary obj-$(CONFIG_MMU)

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/cpu/Makefile | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/arm/cpu/Makefile b/arch/arm/cpu/Makefile
index eb783481ea..edd4a290ca 100644
--- a/arch/arm/cpu/Makefile
+++ b/arch/arm/cpu/Makefile
@@ -18,7 +18,6 @@ obj-pbl-y += setupc$(S64).o
 obj-$(CONFIG_CMD_ARM_CPUINFO) += cpuinfo.o
 obj-$(CONFIG_CMD_ARM_MMUINFO) += mmuinfo.o
 obj-$(CONFIG_OFDEVICE) += dtb.o
-obj-$(CONFIG_MMU) += cache.o
 
 ifeq ($(CONFIG_MMU),)
 obj-y += no-mmu.o
-- 
2.16.1



From s.hauer at pengutronix.de  Fri Mar 16 05:53:41 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 16 Mar 2018 13:53:41 +0100
Subject: [PATCH 65/78] ARM: aarch64: implement ignoring data aborts
In-Reply-To: <20180316125354.23462-1-s.hauer@pengutronix.de>
References: <20180316125354.23462-1-s.hauer@pengutronix.de>
Message-ID: <20180316125354.23462-66-s.hauer@pengutronix.de>

Data aborts can be masked using the data_abort_mask() function.
Add the missing pieces for functionality on aarch64 so that the
'md' command is safe to call even with faulting addresses.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/cpu/interrupts_64.c | 13 ++++++++++---
 1 file changed, 10 insertions(+), 3 deletions(-)

diff --git a/arch/arm/cpu/interrupts_64.c b/arch/arm/cpu/interrupts_64.c
index ee3dc3380b..32c8dfcb2d 100644
--- a/arch/arm/cpu/interrupts_64.c
+++ b/arch/arm/cpu/interrupts_64.c
@@ -143,8 +143,18 @@ void do_bad_error(struct pt_regs *pt_regs)
 	do_exception(pt_regs);
 }
 
+extern volatile int arm_ignore_data_abort;
+extern volatile int arm_data_abort_occurred;
+
 void do_sync(struct pt_regs *pt_regs, unsigned int esr, unsigned long far)
 {
+	if ((esr >> ESR_ELx_EC_SHIFT) == ESR_ELx_EC_DABT_CUR &&
+			arm_ignore_data_abort) {
+		arm_data_abort_occurred = 1;
+		pt_regs->elr += 4;
+		return;
+	}
+
 	printf("%s exception at 0x%016lx\n", esr_get_class_string(esr), far);
 	do_exception(pt_regs);
 }
@@ -156,9 +166,6 @@ void do_error(struct pt_regs *pt_regs)
 	do_exception(pt_regs);
 }
 
-extern volatile int arm_ignore_data_abort;
-extern volatile int arm_data_abort_occurred;
-
 void data_abort_mask(void)
 {
 	arm_data_abort_occurred = 0;
-- 
2.16.1



From s.hauer at pengutronix.de  Fri Mar 16 05:53:33 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 16 Mar 2018 13:53:33 +0100
Subject: [PATCH 57/78] ARM: aarch64: remove dead code in linker script
In-Reply-To: <20180316125354.23462-1-s.hauer@pengutronix.de>
References: <20180316125354.23462-1-s.hauer@pengutronix.de>
Message-ID: <20180316125354.23462-58-s.hauer@pengutronix.de>

CONFIG_ARM_UNWIND does not exist for aarch64. Remove the dead code.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/lib64/barebox.lds.S | 16 ----------------
 1 file changed, 16 deletions(-)

diff --git a/arch/arm/lib64/barebox.lds.S b/arch/arm/lib64/barebox.lds.S
index fa633e3699..08adc44e86 100644
--- a/arch/arm/lib64/barebox.lds.S
+++ b/arch/arm/lib64/barebox.lds.S
@@ -53,22 +53,6 @@ SECTIONS
 	. = ALIGN(4);
 	.rodata : { *(.rodata*) }
 
-#ifdef CONFIG_ARM_UNWIND
-	/*
-	 * Stack unwinding tables
-	 */
-	. = ALIGN(8);
-	.ARM.unwind_idx : {
-		__start_unwind_idx = .;
-		*(.ARM.exidx*)
-		__stop_unwind_idx = .;
-	}
-	.ARM.unwind_tab : {
-		__start_unwind_tab = .;
-		*(.ARM.extab*)
-		__stop_unwind_tab = .;
-	}
-#endif
 	_etext = .;			/* End of text and rodata section */
 	_sdata = .;
 
-- 
2.16.1



From s.hauer at pengutronix.de  Fri Mar 16 05:53:51 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 16 Mar 2018 13:53:51 +0100
Subject: [PATCH 75/78] ARM: Create own cache.c file for aarch64
In-Reply-To: <20180316125354.23462-1-s.hauer@pengutronix.de>
References: <20180316125354.23462-1-s.hauer@pengutronix.de>
Message-ID: <20180316125354.23462-76-s.hauer@pengutronix.de>

cache.c does not work properly for aarch64. We create a struct cache_fns
using C preprocessor foo which assumes the existence of cache
maintenance operations with a certain name. These functions have other
names on aarch64. While we could fix this we do not need the automatic
cache function selection on aarch64 since here we only have one function
set.
Create a separate file and be done with this issue.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/cpu/Makefile   |  4 ++--
 arch/arm/cpu/cache.c    | 16 ----------------
 arch/arm/cpu/cache_64.c | 35 +++++++++++++++++++++++++++++++++++
 3 files changed, 37 insertions(+), 18 deletions(-)
 create mode 100644 arch/arm/cpu/cache_64.c

diff --git a/arch/arm/cpu/Makefile b/arch/arm/cpu/Makefile
index edd4a290ca..f79cedd085 100644
--- a/arch/arm/cpu/Makefile
+++ b/arch/arm/cpu/Makefile
@@ -10,7 +10,7 @@ endif
 
 obj-y += start.o entry.o
 
-obj-pbl-y += setupc$(S64).o
+obj-pbl-y += setupc$(S64).o cache$(S64).o
 
 #
 # Any variants can be called as start-armxyz.S
@@ -44,4 +44,4 @@ pbl-y += entry.o
 pbl-$(CONFIG_PBL_SINGLE_IMAGE) += start-pbl.o
 pbl-$(CONFIG_PBL_MULTI_IMAGES) += uncompress.o
 
-obj-pbl-y += common.o cache.o sections.o
+obj-pbl-y += common.o sections.o
diff --git a/arch/arm/cpu/cache.c b/arch/arm/cpu/cache.c
index 1a8f49d301..7047470f0c 100644
--- a/arch/arm/cpu/cache.c
+++ b/arch/arm/cpu/cache.c
@@ -101,11 +101,6 @@ int arm_set_cache_functions(void)
 	case CPU_ARCH_ARMv7:
 		cache_fns = &cache_fns_armv7;
 		break;
-#endif
-#ifdef CONFIG_CPU_64v8
-	case CPU_ARCH_ARMv8:
-		cache_fns = &cache_fns_armv8;
-		break;
 #endif
 	default:
 		while(1);
@@ -143,11 +138,6 @@ void arm_early_mmu_cache_flush(void)
 	case CPU_ARCH_ARMv7:
 		v7_mmu_cache_flush();
 		return;
-#endif
-#ifdef CONFIG_CPU_64v8
-	case CPU_ARCH_ARMv8:
-		v8_flush_dcache_all();
-		return;
 #endif
 	}
 }
@@ -171,12 +161,6 @@ void arm_early_mmu_cache_invalidate(void)
 		v7_mmu_cache_invalidate();
 		return;
 #endif
-#else
-#ifdef CONFIG_CPU_64v8
-	case CPU_ARCH_ARMv8:
-		v8_invalidate_icache_all();
-		return;
-#endif
 #endif
 	}
 }
diff --git a/arch/arm/cpu/cache_64.c b/arch/arm/cpu/cache_64.c
new file mode 100644
index 0000000000..45f01e8dc9
--- /dev/null
+++ b/arch/arm/cpu/cache_64.c
@@ -0,0 +1,35 @@
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ */
+
+#include <common.h>
+#include <init.h>
+#include <asm/mmu.h>
+#include <asm/cache.h>
+#include <asm/system_info.h>
+
+int arm_set_cache_functions(void)
+{
+	return 0;
+}
+
+/*
+ * Early function to flush the caches. This is for use when the
+ * C environment is not yet fully initialized.
+ */
+void arm_early_mmu_cache_flush(void)
+{
+	v8_flush_dcache_all();
+}
+
+void arm_early_mmu_cache_invalidate(void)
+{
+	v8_invalidate_icache_all();
+}
-- 
2.16.1



From s.hauer at pengutronix.de  Fri Mar 16 05:53:48 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 16 Mar 2018 13:53:48 +0100
Subject: [PATCH 72/78] ARM: aarch64: Add support to start kernel and barebox
In-Reply-To: <20180316125354.23462-1-s.hauer@pengutronix.de>
References: <20180316125354.23462-1-s.hauer@pengutronix.de>
Message-ID: <20180316125354.23462-73-s.hauer@pengutronix.de>

aarch64 has its own image format. Add a bootm handler to handle this
format. Also add a barebox handler.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/lib64/armlinux.c | 120 +++++++++++++++++++++++++++++++++++++---------
 1 file changed, 98 insertions(+), 22 deletions(-)

diff --git a/arch/arm/lib64/armlinux.c b/arch/arm/lib64/armlinux.c
index 54ce6ca046..238e8b67a4 100644
--- a/arch/arm/lib64/armlinux.c
+++ b/arch/arm/lib64/armlinux.c
@@ -1,51 +1,127 @@
 /*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger at sysgo.de>
+ * Copyright (C) 2018 Sascha Hauer <s.hauer at pengutronix.de>
  *
- * Copyright (C) 2001  Erik Mouw (J.A.K.Mouw at its.tudelft.nl)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
  */
 
 #include <boot.h>
 #include <common.h>
-#include <command.h>
-#include <driver.h>
 #include <environment.h>
 #include <image.h>
-#include <init.h>
 #include <fs.h>
-#include <linux/list.h>
 #include <xfuncs.h>
 #include <malloc.h>
 #include <fcntl.h>
 #include <errno.h>
 #include <memory.h>
 #include <of.h>
-#include <magicvar.h>
-
+#include <init.h>
+#include <bootm.h>
+#include <linux/list.h>
 #include <asm/byteorder.h>
 #include <asm/setup.h>
 #include <asm/barebox-arm.h>
 #include <asm/armlinux.h>
 #include <asm/system.h>
 
-void start_linux(void *adr, int swap, unsigned long initrd_address,
-		 unsigned long initrd_size, void *oftree,
-		 enum arm_security_state bootm_secure_state)
+static int do_bootm_linux(struct image_data *data)
 {
-	void (*kernel)(void *dtb) = adr;
+	void (*fn)(unsigned long dtb, unsigned long x1, unsigned long x2,
+		       unsigned long x3);
+	resource_size_t start, end;
+	unsigned long text_offset, image_size, devicetree, kernel;
+	int ret;
+
+	text_offset = le64_to_cpup(data->os_header + 8);
+	image_size = le64_to_cpup(data->os_header + 16);
+
+	ret = memory_bank_first_find_space(&start, &end);
+	if (ret)
+		goto out;
+
+	kernel = ALIGN(start, SZ_2M) + text_offset;
+
+	ret = bootm_load_os(data, kernel);
+	if (ret)
+		goto out;
+
+	devicetree = ALIGN(kernel + image_size, PAGE_SIZE);
+
+	ret = bootm_load_devicetree(data, devicetree);
+	if (ret)
+		goto out;
+
+	printf("Loaded kernel to 0x%08lx, devicetree at 0x%08lx\n",
+	       kernel, devicetree);
 
 	shutdown_barebox();
 
-	kernel(oftree);
+	fn = (void *)kernel;
+
+	fn(devicetree, 0, 0, 0);
+
+	ret = -EINVAL;
+
+out:
+	return ret;
+}
+
+static struct image_handler aarch64_linux_handler = {
+        .name = "ARM aarch64 Linux image",
+        .bootm = do_bootm_linux,
+        .filetype = filetype_arm64_linux_image,
+};
+
+static int do_bootm_barebox(struct image_data *data)
+{
+	void (*fn)(unsigned long x0, unsigned long x1, unsigned long x2,
+		       unsigned long x3);
+	resource_size_t start, end;
+	unsigned long barebox;
+	int ret;
+
+	ret = memory_bank_first_find_space(&start, &end);
+	if (ret)
+		goto out;
+
+	barebox = start;
+
+	ret = bootm_load_os(data, barebox);
+	if (ret)
+		goto out;
+
+	printf("Loaded barebox image to 0x%08lx\n", barebox);
+
+	shutdown_barebox();
+
+	fn = (void *)barebox;
+
+	fn(0, 0, 0, 0);
+
+	ret = -EINVAL;
+
+out:
+	return ret;
+}
+
+static struct image_handler aarch64_barebox_handler = {
+        .name = "ARM aarch64 barebox image",
+        .bootm = do_bootm_barebox,
+        .filetype = filetype_arm_barebox,
+};
+
+static int aarch64_register_image_handler(void)
+{
+	register_image_handler(&aarch64_linux_handler);
+	register_image_handler(&aarch64_barebox_handler);
+
+	return 0;
 }
+late_initcall(aarch64_register_image_handler);
-- 
2.16.1



From s.hauer at pengutronix.de  Fri Mar 16 05:52:39 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 16 Mar 2018 13:52:39 +0100
Subject: [PATCH 03/78] ARM: return positive offset in get_runtime_offset()
In-Reply-To: <20180316125354.23462-1-s.hauer@pengutronix.de>
References: <20180316125354.23462-1-s.hauer@pengutronix.de>
Message-ID: <20180316125354.23462-4-s.hauer@pengutronix.de>

When we are linked at 0x0 and running at 0x01000000 then
get_runtime_offset() should return 0x01000000 and not 0xff000000. This
makes get_runtime_offset() more consistent and better understandable.

This was tested on a Freescale i.MX53 Quickstart board. Additionally
relocate_to_adr() was tested since that is normally not called.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/boards/afi-gf/lowlevel.c                    |  2 +-
 arch/arm/boards/altera-socdk/lowlevel.c              |  2 +-
 arch/arm/boards/at91sam9263ek/lowlevel_init.c        |  2 +-
 arch/arm/boards/at91sam9x5ek/lowlevel.c              |  2 +-
 arch/arm/boards/beaglebone/lowlevel.c                |  2 +-
 arch/arm/boards/boundarydevices-nitrogen6/lowlevel.c | 10 +++++-----
 arch/arm/boards/ccxmx53/lowlevel.c                   |  4 ++--
 arch/arm/boards/datamodul-edm-qmx6/lowlevel.c        |  2 +-
 arch/arm/boards/dfi-fs700-m60/lowlevel.c             |  6 +++---
 arch/arm/boards/duckbill/lowlevel.c                  |  2 +-
 arch/arm/boards/ebv-socrates/lowlevel.c              |  2 +-
 arch/arm/boards/efika-mx-smartbook/lowlevel.c        |  2 +-
 arch/arm/boards/element14-warp7/lowlevel.c           |  2 +-
 arch/arm/boards/eltec-hipercam/lowlevel.c            |  2 +-
 arch/arm/boards/embedsky-e9/lowlevel.c               |  2 +-
 arch/arm/boards/embest-riotboard/lowlevel.c          |  2 +-
 arch/arm/boards/freescale-mx51-babbage/lowlevel.c    |  2 +-
 arch/arm/boards/freescale-mx53-qsb/lowlevel.c        |  4 ++--
 arch/arm/boards/freescale-mx53-vmx53/lowlevel.c      |  2 +-
 arch/arm/boards/freescale-mx6-sabresd/lowlevel.c     |  2 +-
 arch/arm/boards/freescale-mx6sx-sabresdb/lowlevel.c  |  2 +-
 arch/arm/boards/freescale-mx7-sabresd/lowlevel.c     |  2 +-
 arch/arm/boards/freescale-vf610-twr/lowlevel.c       |  2 +-
 arch/arm/boards/gateworks-ventana/lowlevel.c         |  2 +-
 arch/arm/boards/gk802/lowlevel.c                     |  2 +-
 arch/arm/boards/globalscale-guruplug/lowlevel.c      |  2 +-
 arch/arm/boards/globalscale-mirabox/lowlevel.c       |  2 +-
 arch/arm/boards/karo-tx25/lowlevel.c                 |  2 +-
 arch/arm/boards/karo-tx6x/lowlevel.c                 |  8 ++++----
 arch/arm/boards/kindle-mx50/lowlevel.c               |  6 +++---
 arch/arm/boards/lenovo-ix4-300d/lowlevel.c           |  2 +-
 arch/arm/boards/marvell-armada-xp-gp/lowlevel.c      |  2 +-
 arch/arm/boards/netgear-rn104/lowlevel.c             |  2 +-
 arch/arm/boards/netgear-rn2120/lowlevel.c            |  2 +-
 arch/arm/boards/phytec-phycard-imx27/lowlevel.c      |  2 +-
 arch/arm/boards/phytec-phycore-imx27/lowlevel.c      |  2 +-
 arch/arm/boards/phytec-phycore-imx7/lowlevel.c       |  4 ++--
 arch/arm/boards/phytec-som-am335x/lowlevel.c         |  6 +++---
 arch/arm/boards/phytec-som-imx6/lowlevel.c           |  2 +-
 arch/arm/boards/phytec-som-rk3288/lowlevel.c         |  2 +-
 arch/arm/boards/plathome-openblocks-a6/lowlevel.c    |  2 +-
 arch/arm/boards/plathome-openblocks-ax3/lowlevel.c   |  2 +-
 arch/arm/boards/radxa-rock/lowlevel.c                |  2 +-
 arch/arm/boards/raspberry-pi/lowlevel.c              |  4 ++--
 arch/arm/boards/reflex-achilles/lowlevel.c           |  2 +-
 arch/arm/boards/solidrun-cubox/lowlevel.c            |  2 +-
 arch/arm/boards/solidrun-microsom/lowlevel.c         | 18 +++++++++---------
 arch/arm/boards/technexion-pico-hobbit/lowlevel.c    |  2 +-
 arch/arm/boards/terasic-de0-nano-soc/lowlevel.c      |  2 +-
 arch/arm/boards/terasic-sockit/lowlevel.c            |  2 +-
 arch/arm/boards/tqma53/lowlevel.c                    |  4 ++--
 arch/arm/boards/tqma6x/lowlevel.c                    |  4 ++--
 arch/arm/boards/turris-omnia/lowlevel.c              |  2 +-
 arch/arm/boards/udoo/lowlevel.c                      |  2 +-
 arch/arm/boards/usi-topkick/lowlevel.c               |  2 +-
 arch/arm/boards/variscite-mx6/lowlevel.c             |  2 +-
 arch/arm/boards/vexpress/lowlevel.c                  |  2 +-
 arch/arm/boards/vscom-baltos/lowlevel.c              |  2 +-
 arch/arm/boards/zii-imx6q-rdu2/lowlevel.c            |  4 ++--
 arch/arm/boards/zii-vf610-dev/lowlevel.c             |  2 +-
 arch/arm/cpu/common.c                                | 16 ++++++++--------
 arch/arm/cpu/setupc.S                                |  9 +++++----
 arch/arm/cpu/start-pbl.c                             |  4 ++--
 arch/arm/cpu/uncompress.c                            |  2 +-
 arch/arm/lib32/runtime-offset.S                      |  4 ++--
 arch/arm/mach-mvebu/include/mach/common.h            |  2 +-
 arch/arm/mach-tegra/include/mach/lowlevel.h          |  2 +-
 arch/arm/mach-tegra/tegra_avp_init.c                 |  2 +-
 68 files changed, 109 insertions(+), 108 deletions(-)

diff --git a/arch/arm/boards/afi-gf/lowlevel.c b/arch/arm/boards/afi-gf/lowlevel.c
index 91b4b68c6d..1afc96571b 100644
--- a/arch/arm/boards/afi-gf/lowlevel.c
+++ b/arch/arm/boards/afi-gf/lowlevel.c
@@ -258,7 +258,7 @@ ENTRY_FUNCTION(start_am33xx_afi_gf_sdram, r0, r1, r2)
 {
 	void *fdt;
 
-	fdt = __dtb_z_am335x_afi_gf_start - get_runtime_offset();
+	fdt = __dtb_z_am335x_afi_gf_start + get_runtime_offset();
 
 	putc_ll('>');
 
diff --git a/arch/arm/boards/altera-socdk/lowlevel.c b/arch/arm/boards/altera-socdk/lowlevel.c
index 8cfe839159..08e70a0fc6 100644
--- a/arch/arm/boards/altera-socdk/lowlevel.c
+++ b/arch/arm/boards/altera-socdk/lowlevel.c
@@ -26,7 +26,7 @@ ENTRY_FUNCTION(start_socfpga_socdk, r0, r1, r2)
 
 	arm_cpu_lowlevel_init();
 
-	fdt = __dtb_socfpga_cyclone5_socdk_start - get_runtime_offset();
+	fdt = __dtb_socfpga_cyclone5_socdk_start + get_runtime_offset();
 
 	barebox_arm_entry(0x0, SZ_1G, fdt);
 }
diff --git a/arch/arm/boards/at91sam9263ek/lowlevel_init.c b/arch/arm/boards/at91sam9263ek/lowlevel_init.c
index 2004d70cbe..30c14089d1 100644
--- a/arch/arm/boards/at91sam9263ek/lowlevel_init.c
+++ b/arch/arm/boards/at91sam9263ek/lowlevel_init.c
@@ -126,7 +126,7 @@ ENTRY_FUNCTION(start_at91sam9263ek, r0, r1, r2)
 	arm_setup_stack(AT91SAM9263_SRAM0_BASE + AT91SAM9263_SRAM0_SIZE - 16);
 
 	if (IS_ENABLED(CONFIG_MACH_AT91SAM9263EK_DT))
-		fdt = __dtb_at91sam9263ek_start - get_runtime_offset();
+		fdt = __dtb_at91sam9263ek_start + get_runtime_offset();
 	else
 		fdt = NULL;
 
diff --git a/arch/arm/boards/at91sam9x5ek/lowlevel.c b/arch/arm/boards/at91sam9x5ek/lowlevel.c
index acf80d7955..9aa0e8ba9b 100644
--- a/arch/arm/boards/at91sam9x5ek/lowlevel.c
+++ b/arch/arm/boards/at91sam9x5ek/lowlevel.c
@@ -15,7 +15,7 @@ ENTRY_FUNCTION(start_at91sam9x5ek, r0, r1, r2)
 	arm_cpu_lowlevel_init();
 	arm_setup_stack(AT91SAM9X5_SRAM_BASE + AT91SAM9X5_SRAM_SIZE - 16);
 
-	fdt = __dtb_at91sam9x5ek_start - get_runtime_offset();
+	fdt = __dtb_at91sam9x5ek_start + get_runtime_offset();
 
 	barebox_arm_entry(AT91_CHIPSELECT_1, at91sam9x5_get_ddram_size(), fdt);
 }
diff --git a/arch/arm/boards/beaglebone/lowlevel.c b/arch/arm/boards/beaglebone/lowlevel.c
index a56b4b6240..a1ba1d32f9 100644
--- a/arch/arm/boards/beaglebone/lowlevel.c
+++ b/arch/arm/boards/beaglebone/lowlevel.c
@@ -184,7 +184,7 @@ ENTRY_FUNCTION(start_am33xx_beaglebone_sdram, r0, r1, r2)
 		fdt = __dtb_z_am335x_bone_start;
 	}
 
-	fdt -= get_runtime_offset();
+	fdt += get_runtime_offset();
 
 	barebox_arm_entry(0x80000000, sdram_size, fdt);
 }
diff --git a/arch/arm/boards/boundarydevices-nitrogen6/lowlevel.c b/arch/arm/boards/boundarydevices-nitrogen6/lowlevel.c
index bee70a5af4..74ff71fc24 100644
--- a/arch/arm/boards/boundarydevices-nitrogen6/lowlevel.c
+++ b/arch/arm/boards/boundarydevices-nitrogen6/lowlevel.c
@@ -11,7 +11,7 @@ ENTRY_FUNCTION(start_imx6q_nitrogen6x_1g, r0, r1, r2)
 
 	imx6_cpu_lowlevel_init();
 
-	fdt = __dtb_imx6q_nitrogen6x_start - get_runtime_offset();
+	fdt = __dtb_imx6q_nitrogen6x_start + get_runtime_offset();
 
 	imx6q_barebox_entry(fdt);
 }
@@ -22,7 +22,7 @@ ENTRY_FUNCTION(start_imx6q_nitrogen6x_2g, r0, r1, r2)
 
 	imx6_cpu_lowlevel_init();
 
-	fdt = __dtb_imx6q_nitrogen6x_start - get_runtime_offset();
+	fdt = __dtb_imx6q_nitrogen6x_start + get_runtime_offset();
 
 	imx6q_barebox_entry(fdt);
 }
@@ -35,7 +35,7 @@ ENTRY_FUNCTION(start_imx6dl_nitrogen6x_1g, r0, r1, r2)
 
 	imx6_cpu_lowlevel_init();
 
-	fdt = __dtb_imx6dl_nitrogen6x_start - get_runtime_offset();
+	fdt = __dtb_imx6dl_nitrogen6x_start + get_runtime_offset();
 
 	imx6q_barebox_entry(fdt);
 }
@@ -46,7 +46,7 @@ ENTRY_FUNCTION(start_imx6dl_nitrogen6x_2g, r0, r1, r2)
 
 	imx6_cpu_lowlevel_init();
 
-	fdt = __dtb_imx6dl_nitrogen6x_start - get_runtime_offset();
+	fdt = __dtb_imx6dl_nitrogen6x_start + get_runtime_offset();
 
 	imx6q_barebox_entry(fdt);
 }
@@ -59,7 +59,7 @@ ENTRY_FUNCTION(start_imx6qp_nitrogen6_max, r0, r1, r2)
 
 	imx6_cpu_lowlevel_init();
 
-	fdt = __dtb_imx6qp_nitrogen6_max_start - get_runtime_offset();
+	fdt = __dtb_imx6qp_nitrogen6_max_start + get_runtime_offset();
 
 	imx6q_barebox_entry(fdt);
 }
diff --git a/arch/arm/boards/ccxmx53/lowlevel.c b/arch/arm/boards/ccxmx53/lowlevel.c
index 22492140d8..c27e33098c 100644
--- a/arch/arm/boards/ccxmx53/lowlevel.c
+++ b/arch/arm/boards/ccxmx53/lowlevel.c
@@ -41,7 +41,7 @@ ENTRY_FUNCTION(start_ccxmx53_512mb, r0, r1, r2)
 
 	IMD_USED(ccxmx53_memsize_SZ_512M);
 
-	fdt = __dtb_imx53_ccxmx53_start - get_runtime_offset();
+	fdt = __dtb_imx53_ccxmx53_start + get_runtime_offset();
 
 	imx53_barebox_entry(fdt);
 }
@@ -55,7 +55,7 @@ ENTRY_FUNCTION(start_ccxmx53_1gib, r0, r1, r2)
 
 	IMD_USED(ccxmx53_memsize_SZ_1G);
 
-	fdt = __dtb_imx53_ccxmx53_start - get_runtime_offset();
+	fdt = __dtb_imx53_ccxmx53_start + get_runtime_offset();
 
 	imx53_barebox_entry(fdt);
 }
diff --git a/arch/arm/boards/datamodul-edm-qmx6/lowlevel.c b/arch/arm/boards/datamodul-edm-qmx6/lowlevel.c
index 28b4aa280d..3ecdb66bc5 100644
--- a/arch/arm/boards/datamodul-edm-qmx6/lowlevel.c
+++ b/arch/arm/boards/datamodul-edm-qmx6/lowlevel.c
@@ -147,7 +147,7 @@ ENTRY_FUNCTION(start_imx6_realq7, r0, r1, r2)
 
 	arm_setup_stack(0x00940000 - 8);
 
-	fdt = __dtb_imx6q_dmo_edmqmx6_start - get_runtime_offset();
+	fdt = __dtb_imx6q_dmo_edmqmx6_start + get_runtime_offset();
 
 	if (get_pc() < 0x10000000) {
 		sdram_init();
diff --git a/arch/arm/boards/dfi-fs700-m60/lowlevel.c b/arch/arm/boards/dfi-fs700-m60/lowlevel.c
index a22f66a11b..b419228505 100644
--- a/arch/arm/boards/dfi-fs700-m60/lowlevel.c
+++ b/arch/arm/boards/dfi-fs700-m60/lowlevel.c
@@ -115,7 +115,7 @@ ENTRY_FUNCTION(start_imx6q_dfi_fs700_m60_6q_nanya, r0, r1, r2)
 
 	early_uart_init_6q();
 
-	fdt = __dtb_imx6q_dfi_fs700_m60_6q_start - get_runtime_offset();
+	fdt = __dtb_imx6q_dfi_fs700_m60_6q_start + get_runtime_offset();
 
 	barebox_arm_entry(0x10000000, memsize_1G_2G(), fdt);
 }
@@ -134,7 +134,7 @@ ENTRY_FUNCTION(start_imx6q_dfi_fs700_m60_6q_micron, r0, r1, r2)
 
 	early_uart_init_6q();
 
-	fdt = __dtb_imx6q_dfi_fs700_m60_6q_start - get_runtime_offset();
+	fdt = __dtb_imx6q_dfi_fs700_m60_6q_start + get_runtime_offset();
 
 	*(uint32_t *)0x10000000 = SZ_1G;
 
@@ -157,7 +157,7 @@ ENTRY_FUNCTION(start_imx6dl_dfi_fs700_m60_6s, r0, r1, r2)
 
 	early_uart_init_6s();
 
-	fdt = __dtb_imx6dl_dfi_fs700_m60_6s_start - get_runtime_offset();
+	fdt = __dtb_imx6dl_dfi_fs700_m60_6s_start + get_runtime_offset();
 
 	barebox_arm_entry(0x10000000, memsize_512M_1G(), fdt);
 }
diff --git a/arch/arm/boards/duckbill/lowlevel.c b/arch/arm/boards/duckbill/lowlevel.c
index c00a9a0b04..2922e40f2a 100644
--- a/arch/arm/boards/duckbill/lowlevel.c
+++ b/arch/arm/boards/duckbill/lowlevel.c
@@ -20,7 +20,7 @@ ENTRY_FUNCTION(start_barebox_duckbill, r0, r1, r2)
 
 	pr_debug("here we are!\n");
 
-	fdt = __dtb_imx28_duckbill_start - get_runtime_offset();
+	fdt = __dtb_imx28_duckbill_start + get_runtime_offset();
 
 	barebox_arm_entry(IMX_MEMORY_BASE, SZ_128M, fdt);
 }
diff --git a/arch/arm/boards/ebv-socrates/lowlevel.c b/arch/arm/boards/ebv-socrates/lowlevel.c
index 9643269f8e..ef9f4535f6 100644
--- a/arch/arm/boards/ebv-socrates/lowlevel.c
+++ b/arch/arm/boards/ebv-socrates/lowlevel.c
@@ -52,7 +52,7 @@ ENTRY_FUNCTION(start_socfpga_socrates, r0, r1, r2)
 
 	arm_cpu_lowlevel_init();
 
-	fdt = __dtb_socfpga_cyclone5_socrates_start - get_runtime_offset();
+	fdt = __dtb_socfpga_cyclone5_socrates_start + get_runtime_offset();
 
 	barebox_arm_entry(0x0, SZ_1G, fdt);
 }
diff --git a/arch/arm/boards/efika-mx-smartbook/lowlevel.c b/arch/arm/boards/efika-mx-smartbook/lowlevel.c
index 52454c7d50..6da5bfaf55 100644
--- a/arch/arm/boards/efika-mx-smartbook/lowlevel.c
+++ b/arch/arm/boards/efika-mx-smartbook/lowlevel.c
@@ -15,7 +15,7 @@ ENTRY_FUNCTION(start_imx51_genesi_efikasb, r0, r1, r2)
 	arm_setup_stack(0x20000000 - 16);
 	imx51_init_lowlevel(800);
 
-	fdt = __dtb_imx51_genesi_efika_sb_start - get_runtime_offset();
+	fdt = __dtb_imx51_genesi_efika_sb_start + get_runtime_offset();
 
 	imx51_barebox_entry(fdt);
 }
diff --git a/arch/arm/boards/element14-warp7/lowlevel.c b/arch/arm/boards/element14-warp7/lowlevel.c
index 89a77d2f88..6ca733a0be 100644
--- a/arch/arm/boards/element14-warp7/lowlevel.c
+++ b/arch/arm/boards/element14-warp7/lowlevel.c
@@ -35,7 +35,7 @@ static noinline void warp7_start(void)
 
 	pr_debug("Element14 i.MX7 Warp\n");
 
-	fdt = __dtb_imx7s_warp_start - get_runtime_offset();
+	fdt = __dtb_imx7s_warp_start + get_runtime_offset();
 
 	barebox_arm_entry(0x80000000, SZ_512M, fdt);
 }
diff --git a/arch/arm/boards/eltec-hipercam/lowlevel.c b/arch/arm/boards/eltec-hipercam/lowlevel.c
index 21542e49e9..b0d3155023 100644
--- a/arch/arm/boards/eltec-hipercam/lowlevel.c
+++ b/arch/arm/boards/eltec-hipercam/lowlevel.c
@@ -44,7 +44,7 @@ ENTRY_FUNCTION(start_imx6dl_eltec_hipercam, r0, r1, r2)
 	if (IS_ENABLED(CONFIG_DEBUG_LL))
 		setup_uart();
 
-	fdt = __dtb_imx6dl_eltec_hipercam_start - get_runtime_offset();
+	fdt = __dtb_imx6dl_eltec_hipercam_start + get_runtime_offset();
 
 	barebox_arm_entry(0x10000000, SZ_256M, fdt);
 }
diff --git a/arch/arm/boards/embedsky-e9/lowlevel.c b/arch/arm/boards/embedsky-e9/lowlevel.c
index fb1ba5f64a..845c4ec90c 100644
--- a/arch/arm/boards/embedsky-e9/lowlevel.c
+++ b/arch/arm/boards/embedsky-e9/lowlevel.c
@@ -12,7 +12,7 @@ ENTRY_FUNCTION(start_imx6q_embedsky_e9, r0, r1, r2)
 
 	imx6_cpu_lowlevel_init();
 
-	fdt = __dtb_imx6q_embedsky_e9_start - get_runtime_offset();
+	fdt = __dtb_imx6q_embedsky_e9_start + get_runtime_offset();
 
 	barebox_arm_entry(0x10000000, SZ_2G, fdt);
 }
diff --git a/arch/arm/boards/embest-riotboard/lowlevel.c b/arch/arm/boards/embest-riotboard/lowlevel.c
index d26bc98bbb..07f669fc03 100644
--- a/arch/arm/boards/embest-riotboard/lowlevel.c
+++ b/arch/arm/boards/embest-riotboard/lowlevel.c
@@ -23,6 +23,6 @@ ENTRY_FUNCTION(start_imx6s_riotboard, r0, r1, r2)
 		putc_ll('a');
 	}
 
-	fdt = __dtb_imx6s_riotboard_start - get_runtime_offset();
+	fdt = __dtb_imx6s_riotboard_start + get_runtime_offset();
 	barebox_arm_entry(0x10000000, SZ_1G, fdt);
 }
diff --git a/arch/arm/boards/freescale-mx51-babbage/lowlevel.c b/arch/arm/boards/freescale-mx51-babbage/lowlevel.c
index af40f4405e..1c20b6a7ae 100644
--- a/arch/arm/boards/freescale-mx51-babbage/lowlevel.c
+++ b/arch/arm/boards/freescale-mx51-babbage/lowlevel.c
@@ -50,7 +50,7 @@ ENTRY_FUNCTION(start_imx51_babbage, r0, r1, r2)
 
 	arm_setup_stack(0x20000000 - 16);
 
-	fdt = __dtb_imx51_babbage_start - get_runtime_offset();
+	fdt = __dtb_imx51_babbage_start + get_runtime_offset();
 
 	imx51_barebox_entry(fdt);
 }
diff --git a/arch/arm/boards/freescale-mx53-qsb/lowlevel.c b/arch/arm/boards/freescale-mx53-qsb/lowlevel.c
index bed886357c..cfe01f7807 100644
--- a/arch/arm/boards/freescale-mx53-qsb/lowlevel.c
+++ b/arch/arm/boards/freescale-mx53-qsb/lowlevel.c
@@ -15,7 +15,7 @@ ENTRY_FUNCTION(start_imx53_loco, r0, r1, r2)
 	imx5_cpu_lowlevel_init();
 	arm_setup_stack(MX53_IRAM_BASE_ADDR + MX53_IRAM_SIZE - 8);
 
-	fdt = __dtb_imx53_qsb_start - get_runtime_offset();
+	fdt = __dtb_imx53_qsb_start + get_runtime_offset();
 
 	imx53_barebox_entry(fdt);
 }
@@ -29,7 +29,7 @@ ENTRY_FUNCTION(start_imx53_loco_r, r0, r1, r2)
 	imx5_cpu_lowlevel_init();
 	arm_setup_stack(MX53_IRAM_BASE_ADDR + MX53_IRAM_SIZE - 8);
 
-	fdt = __dtb_imx53_qsrb_start - get_runtime_offset();
+	fdt = __dtb_imx53_qsrb_start + get_runtime_offset();
 
 	imx53_barebox_entry(fdt);
 }
diff --git a/arch/arm/boards/freescale-mx53-vmx53/lowlevel.c b/arch/arm/boards/freescale-mx53-vmx53/lowlevel.c
index 3545a1c352..aac784ca6e 100644
--- a/arch/arm/boards/freescale-mx53-vmx53/lowlevel.c
+++ b/arch/arm/boards/freescale-mx53-vmx53/lowlevel.c
@@ -13,7 +13,7 @@ ENTRY_FUNCTION(start_imx53_vmx53, r0, r1, r2)
 	imx5_cpu_lowlevel_init();
 	arm_setup_stack(0xf8020000 - 8);
 
-	fdt = __dtb_imx53_voipac_bsb_start - get_runtime_offset();
+	fdt = __dtb_imx53_voipac_bsb_start + get_runtime_offset();
 
 	imx53_barebox_entry(fdt);
 }
diff --git a/arch/arm/boards/freescale-mx6-sabresd/lowlevel.c b/arch/arm/boards/freescale-mx6-sabresd/lowlevel.c
index 5743dbcf30..ae847feaa6 100644
--- a/arch/arm/boards/freescale-mx6-sabresd/lowlevel.c
+++ b/arch/arm/boards/freescale-mx6-sabresd/lowlevel.c
@@ -31,7 +31,7 @@ ENTRY_FUNCTION(start_imx6q_sabresd, r0, r1, r2)
 	if (IS_ENABLED(CONFIG_DEBUG_LL))
 		setup_uart();
 
-	fdt = __dtb_imx6q_sabresd_start - get_runtime_offset();
+	fdt = __dtb_imx6q_sabresd_start + get_runtime_offset();
 
 	barebox_arm_entry(0x10000000, SZ_1G, fdt);
 }
diff --git a/arch/arm/boards/freescale-mx6sx-sabresdb/lowlevel.c b/arch/arm/boards/freescale-mx6sx-sabresdb/lowlevel.c
index af26557e90..6a6e27bf44 100644
--- a/arch/arm/boards/freescale-mx6sx-sabresdb/lowlevel.c
+++ b/arch/arm/boards/freescale-mx6sx-sabresdb/lowlevel.c
@@ -46,7 +46,7 @@ ENTRY_FUNCTION(start_imx6sx_sabresdb, r0, r1, r2)
 	if (IS_ENABLED(CONFIG_DEBUG_LL))
 		setup_uart();
 
-	fdt = __dtb_imx6sx_sdb_start - get_runtime_offset();
+	fdt = __dtb_imx6sx_sdb_start + get_runtime_offset();
 
 	barebox_arm_entry(0x80000000, SZ_1G, fdt);
 }
diff --git a/arch/arm/boards/freescale-mx7-sabresd/lowlevel.c b/arch/arm/boards/freescale-mx7-sabresd/lowlevel.c
index 96ccbbfeb8..43aa610759 100644
--- a/arch/arm/boards/freescale-mx7-sabresd/lowlevel.c
+++ b/arch/arm/boards/freescale-mx7-sabresd/lowlevel.c
@@ -40,7 +40,7 @@ ENTRY_FUNCTION(start_imx7d_sabresd, r0, r1, r2)
 	if (IS_ENABLED(CONFIG_DEBUG_LL))
 		setup_uart();
 
-	fdt = __dtb_imx7d_sdb_start - get_runtime_offset();
+	fdt = __dtb_imx7d_sdb_start + get_runtime_offset();
 
 	barebox_arm_entry(0x80000000, SZ_1G, fdt);
 }
diff --git a/arch/arm/boards/freescale-vf610-twr/lowlevel.c b/arch/arm/boards/freescale-vf610-twr/lowlevel.c
index 53c7b3af6b..deabe4e371 100644
--- a/arch/arm/boards/freescale-vf610-twr/lowlevel.c
+++ b/arch/arm/boards/freescale-vf610-twr/lowlevel.c
@@ -34,6 +34,6 @@ ENTRY_FUNCTION(start_vf610_twr, r0, r1, r2)
 	if (IS_ENABLED(CONFIG_DEBUG_LL))
 		setup_uart();
 
-	fdt = __dtb_vf610_twr_start - get_runtime_offset();
+	fdt = __dtb_vf610_twr_start + get_runtime_offset();
 	barebox_arm_entry(0x80000000, SZ_128M, fdt);
 }
diff --git a/arch/arm/boards/gateworks-ventana/lowlevel.c b/arch/arm/boards/gateworks-ventana/lowlevel.c
index 746beb87e5..0a79d82049 100644
--- a/arch/arm/boards/gateworks-ventana/lowlevel.c
+++ b/arch/arm/boards/gateworks-ventana/lowlevel.c
@@ -12,7 +12,7 @@ ENTRY_FUNCTION(start_imx6q_gw54xx_1gx64, r0, r1, r2)
 
 	imx6_cpu_lowlevel_init();
 
-	fdt = __dtb_imx6q_gw54xx_start - get_runtime_offset();
+	fdt = __dtb_imx6q_gw54xx_start + get_runtime_offset();
 
 	barebox_arm_entry(0x10000000, SZ_1G, fdt);
 }
diff --git a/arch/arm/boards/gk802/lowlevel.c b/arch/arm/boards/gk802/lowlevel.c
index b571969884..a41b711e36 100644
--- a/arch/arm/boards/gk802/lowlevel.c
+++ b/arch/arm/boards/gk802/lowlevel.c
@@ -12,6 +12,6 @@ ENTRY_FUNCTION(start_imx6_gk802, r0, r1, r2)
 
 	imx6_cpu_lowlevel_init();
 
-	fdt = __dtb_imx6q_gk802_start - get_runtime_offset();
+	fdt = __dtb_imx6q_gk802_start + get_runtime_offset();
 	barebox_arm_entry(0x10000000, SZ_1G, fdt);
 }
diff --git a/arch/arm/boards/globalscale-guruplug/lowlevel.c b/arch/arm/boards/globalscale-guruplug/lowlevel.c
index 67c3b23f2c..92424cbd6b 100644
--- a/arch/arm/boards/globalscale-guruplug/lowlevel.c
+++ b/arch/arm/boards/globalscale-guruplug/lowlevel.c
@@ -28,7 +28,7 @@ ENTRY_FUNCTION(start_globalscale_guruplug, r0, r1, r2)
 
 	arm_cpu_lowlevel_init();
 
-	fdt = __dtb_kirkwood_guruplug_server_plus_bb_start -
+	fdt = __dtb_kirkwood_guruplug_server_plus_bb_start +
 		get_runtime_offset();
 
 	kirkwood_barebox_entry(fdt);
diff --git a/arch/arm/boards/globalscale-mirabox/lowlevel.c b/arch/arm/boards/globalscale-mirabox/lowlevel.c
index 7b070d70b1..69786c88fb 100644
--- a/arch/arm/boards/globalscale-mirabox/lowlevel.c
+++ b/arch/arm/boards/globalscale-mirabox/lowlevel.c
@@ -28,7 +28,7 @@ ENTRY_FUNCTION(start_globalscale_mirabox, r0, r1, r2)
 
 	arm_cpu_lowlevel_init();
 
-	fdt = __dtb_armada_370_mirabox_bb_start -
+	fdt = __dtb_armada_370_mirabox_bb_start +
 		get_runtime_offset();
 
 	armada_370_xp_barebox_entry(fdt);
diff --git a/arch/arm/boards/karo-tx25/lowlevel.c b/arch/arm/boards/karo-tx25/lowlevel.c
index b7ff2d44c6..78e6f4d823 100644
--- a/arch/arm/boards/karo-tx25/lowlevel.c
+++ b/arch/arm/boards/karo-tx25/lowlevel.c
@@ -171,7 +171,7 @@ ENTRY_FUNCTION(start_imx25_karo_tx25, r0, r1, r2)
 
 	arm_setup_stack(MX25_IRAM_BASE_ADDR + MX25_IRAM_SIZE - 8);
 
-	fdt = __dtb_imx25_karo_tx25_start - get_runtime_offset();
+	fdt = __dtb_imx25_karo_tx25_start + get_runtime_offset();
 
 	karo_tx25_common_init(fdt);
 }
diff --git a/arch/arm/boards/karo-tx6x/lowlevel.c b/arch/arm/boards/karo-tx6x/lowlevel.c
index f2643efb05..7b58a496ef 100644
--- a/arch/arm/boards/karo-tx6x/lowlevel.c
+++ b/arch/arm/boards/karo-tx6x/lowlevel.c
@@ -53,7 +53,7 @@ ENTRY_FUNCTION(start_imx6dl_tx6x_512m, r0, r1, r2)
 	if (IS_ENABLED(CONFIG_DEBUG_LL))
 		setup_uart();
 
-	fdt = __dtb_imx6dl_tx6u_start - get_runtime_offset();
+	fdt = __dtb_imx6dl_tx6u_start + get_runtime_offset();
 
 	barebox_arm_entry(0x10000000, SZ_512M, fdt);
 }
@@ -73,7 +73,7 @@ ENTRY_FUNCTION(start_imx6dl_tx6x_1g, r0, r1, r2)
 	if (IS_ENABLED(CONFIG_DEBUG_LL))
 		setup_uart();
 
-	fdt = __dtb_imx6dl_tx6u_start - get_runtime_offset();
+	fdt = __dtb_imx6dl_tx6u_start + get_runtime_offset();
 
 	barebox_arm_entry(0x10000000, SZ_1G, fdt);
 }
@@ -93,7 +93,7 @@ ENTRY_FUNCTION(start_imx6q_tx6x_1g, r0, r1, r2)
 	if (IS_ENABLED(CONFIG_DEBUG_LL))
 		setup_uart();
 
-	fdt = __dtb_imx6q_tx6q_start - get_runtime_offset();
+	fdt = __dtb_imx6q_tx6q_start + get_runtime_offset();
 
 	imx6q_barebox_entry(fdt);
 }
@@ -113,7 +113,7 @@ ENTRY_FUNCTION(start_imx6q_tx6x_2g, r0, r1, r2)
 	if (IS_ENABLED(CONFIG_DEBUG_LL))
 		setup_uart();
 
-	fdt = __dtb_imx6q_tx6q_start - get_runtime_offset();
+	fdt = __dtb_imx6q_tx6q_start + get_runtime_offset();
 
 	imx6q_barebox_entry(fdt);
 }
diff --git a/arch/arm/boards/kindle-mx50/lowlevel.c b/arch/arm/boards/kindle-mx50/lowlevel.c
index dc321b533b..20f86c8fcb 100644
--- a/arch/arm/boards/kindle-mx50/lowlevel.c
+++ b/arch/arm/boards/kindle-mx50/lowlevel.c
@@ -20,7 +20,7 @@ ENTRY_FUNCTION(start_imx50_kindle_d01100, r0, r1, r2)
 	imx5_cpu_lowlevel_init();
 	arm_setup_stack(MX50_IRAM_BASE_ADDR + MX50_IRAM_SIZE - 8);
 
-	fdt = __dtb_imx50_kindle_d01100_start - get_runtime_offset();
+	fdt = __dtb_imx50_kindle_d01100_start + get_runtime_offset();
 
 	barebox_arm_entry(MX50_CSD0_BASE_ADDR, SZ_256M, fdt);
 }
@@ -32,7 +32,7 @@ ENTRY_FUNCTION(start_imx50_kindle_d01200, r0, r1, r2)
 	imx5_cpu_lowlevel_init();
 	arm_setup_stack(MX50_IRAM_BASE_ADDR + MX50_IRAM_SIZE - 8);
 
-	fdt = __dtb_imx50_kindle_d01200_start - get_runtime_offset();
+	fdt = __dtb_imx50_kindle_d01200_start + get_runtime_offset();
 
 	barebox_arm_entry(MX50_CSD0_BASE_ADDR, SZ_256M, fdt);
 }
@@ -44,7 +44,7 @@ ENTRY_FUNCTION(start_imx50_kindle_ey21, r0, r1, r2)
 	imx5_cpu_lowlevel_init();
 	arm_setup_stack(MX50_IRAM_BASE_ADDR + MX50_IRAM_SIZE - 8);
 
-	fdt = __dtb_imx50_kindle_ey21_start - get_runtime_offset();
+	fdt = __dtb_imx50_kindle_ey21_start + get_runtime_offset();
 
 	barebox_arm_entry(MX50_CSD0_BASE_ADDR, SZ_256M, fdt);
 }
diff --git a/arch/arm/boards/lenovo-ix4-300d/lowlevel.c b/arch/arm/boards/lenovo-ix4-300d/lowlevel.c
index f8313cd210..40145b5cef 100644
--- a/arch/arm/boards/lenovo-ix4-300d/lowlevel.c
+++ b/arch/arm/boards/lenovo-ix4-300d/lowlevel.c
@@ -28,7 +28,7 @@ ENTRY_FUNCTION(start_lenovo_ix4_300d, r0, r1, r2)
 
 	arm_cpu_lowlevel_init();
 
-	fdt = __dtb_armada_xp_lenovo_ix4_300d_bb_start -
+	fdt = __dtb_armada_xp_lenovo_ix4_300d_bb_start +
 		get_runtime_offset();
 
 	armada_370_xp_barebox_entry(fdt);
diff --git a/arch/arm/boards/marvell-armada-xp-gp/lowlevel.c b/arch/arm/boards/marvell-armada-xp-gp/lowlevel.c
index da6d4aaf4e..e62627c324 100644
--- a/arch/arm/boards/marvell-armada-xp-gp/lowlevel.c
+++ b/arch/arm/boards/marvell-armada-xp-gp/lowlevel.c
@@ -28,7 +28,7 @@ ENTRY_FUNCTION(start_marvell_armada_xp_gp, r0, r1, r2)
 
 	arm_cpu_lowlevel_init();
 
-	fdt = __dtb_armada_xp_gp_bb_start - get_runtime_offset();
+	fdt = __dtb_armada_xp_gp_bb_start + get_runtime_offset();
 
 	armada_370_xp_barebox_entry(fdt);
 }
diff --git a/arch/arm/boards/netgear-rn104/lowlevel.c b/arch/arm/boards/netgear-rn104/lowlevel.c
index 97590d8a6f..8a53615018 100644
--- a/arch/arm/boards/netgear-rn104/lowlevel.c
+++ b/arch/arm/boards/netgear-rn104/lowlevel.c
@@ -15,7 +15,7 @@ ENTRY_FUNCTION(start_netgear_rn104, r0, r1, r2)
 
 	arm_cpu_lowlevel_init();
 
-	fdt = __dtb_armada_370_rn104_bb_start -
+	fdt = __dtb_armada_370_rn104_bb_start +
 		get_runtime_offset();
 
 	armada_370_xp_barebox_entry(fdt);
diff --git a/arch/arm/boards/netgear-rn2120/lowlevel.c b/arch/arm/boards/netgear-rn2120/lowlevel.c
index 59b9985ca9..e05f2f4c17 100644
--- a/arch/arm/boards/netgear-rn2120/lowlevel.c
+++ b/arch/arm/boards/netgear-rn2120/lowlevel.c
@@ -51,7 +51,7 @@ ENTRY_FUNCTION(start_netgear_rn2120, r0, r1, r2)
 	/* Win 0 Control Register: size=0x4000000, wincs=0, en=1 */
 	writel(0x3fffffe1, base + 0x20184);
 
-	fdt = __dtb_armada_xp_rn2120_bb_start -
+	fdt = __dtb_armada_xp_rn2120_bb_start +
 		get_runtime_offset();
 
 	armada_370_xp_barebox_entry(fdt);
diff --git a/arch/arm/boards/phytec-phycard-imx27/lowlevel.c b/arch/arm/boards/phytec-phycard-imx27/lowlevel.c
index 7e4a9f02f0..e1132e0b54 100644
--- a/arch/arm/boards/phytec-phycard-imx27/lowlevel.c
+++ b/arch/arm/boards/phytec-phycard-imx27/lowlevel.c
@@ -109,7 +109,7 @@ ENTRY_FUNCTION(start_phytec_phycard_imx27, r0, r1, r2)
 
 	arm_setup_stack(MX27_IRAM_BASE_ADDR + MX27_IRAM_SIZE - 12);
 
-	fdt = __dtb_imx27_phytec_phycard_s_rdk_bb_start - get_runtime_offset();
+	fdt = __dtb_imx27_phytec_phycard_s_rdk_bb_start + get_runtime_offset();
 
 	phytec_phycard_imx27_common_init(fdt);
 }
diff --git a/arch/arm/boards/phytec-phycore-imx27/lowlevel.c b/arch/arm/boards/phytec-phycore-imx27/lowlevel.c
index b9b2ab5935..b858ff348b 100644
--- a/arch/arm/boards/phytec-phycore-imx27/lowlevel.c
+++ b/arch/arm/boards/phytec-phycore-imx27/lowlevel.c
@@ -108,7 +108,7 @@ ENTRY_FUNCTION(start_phytec_phycore_imx27, r0, r1, r2)
 
 	arm_setup_stack(MX27_IRAM_BASE_ADDR + MX27_IRAM_SIZE - 12);
 
-	fdt = __dtb_imx27_phytec_phycore_rdk_start - get_runtime_offset();
+	fdt = __dtb_imx27_phytec_phycore_rdk_start + get_runtime_offset();
 
 	phytec_phycorce_imx27_common_init(fdt);
 }
diff --git a/arch/arm/boards/phytec-phycore-imx7/lowlevel.c b/arch/arm/boards/phytec-phycore-imx7/lowlevel.c
index ee2d7ae553..3d2038e4a8 100644
--- a/arch/arm/boards/phytec-phycore-imx7/lowlevel.c
+++ b/arch/arm/boards/phytec-phycore-imx7/lowlevel.c
@@ -29,7 +29,7 @@ static noinline void phytec_phycore_imx7_start(void)
 
 	pr_debug("Phytec phyCORE i.MX7\n");
 
-	fdt = __dtb_imx7d_phyboard_zeta_start - get_runtime_offset();
+	fdt = __dtb_imx7d_phyboard_zeta_start + get_runtime_offset();
 
 	barebox_arm_entry(0x80000000, SZ_512M, fdt);
 }
@@ -45,4 +45,4 @@ ENTRY_FUNCTION(start_phytec_phycore_imx7, r0, r1, r2)
 	barrier();
 
 	phytec_phycore_imx7_start();
-}
\ No newline at end of file
+}
diff --git a/arch/arm/boards/phytec-som-am335x/lowlevel.c b/arch/arm/boards/phytec-som-am335x/lowlevel.c
index 338d13a391..a028449fc0 100644
--- a/arch/arm/boards/phytec-som-am335x/lowlevel.c
+++ b/arch/arm/boards/phytec-som-am335x/lowlevel.c
@@ -210,7 +210,7 @@ static noinline void physom_board_entry(unsigned long bootinfo, int sdram,
 	ENTRY_FUNCTION(name, bootinfo, r1, r2)				\
 	{								\
 		extern char __dtb_z_##fdt_name##_start[];		\
-		void *fdt = __dtb_z_##fdt_name##_start -		\
+		void *fdt = __dtb_z_##fdt_name##_start +		\
 			get_runtime_offset();				\
 		physom_board_entry(bootinfo, 0, fdt, module_family);	\
 	}
@@ -219,7 +219,7 @@ static noinline void physom_board_entry(unsigned long bootinfo, int sdram,
 	ENTRY_FUNCTION(name, bootinfo, r1, r2)				\
 	{								\
 		extern char __dtb_z_##fdt_name##_start[];		\
-		void *fdt = __dtb_z_##fdt_name##_start -		\
+		void *fdt = __dtb_z_##fdt_name##_start +		\
 			get_runtime_offset();				\
 		physom_board_entry(bootinfo, sdram, fdt, NONE);		\
 	}
@@ -228,7 +228,7 @@ static noinline void physom_board_entry(unsigned long bootinfo, int sdram,
 	ENTRY_FUNCTION(name, r0, r1, r2)				\
 	{								\
 		extern char __dtb_z_##fdt_name##_start[];		\
-		void *fdt = __dtb_z_##fdt_name##_start -		\
+		void *fdt = __dtb_z_##fdt_name##_start +		\
 			get_runtime_offset();				\
 		am335x_barebox_entry(fdt);				\
 	}
diff --git a/arch/arm/boards/phytec-som-imx6/lowlevel.c b/arch/arm/boards/phytec-som-imx6/lowlevel.c
index 29811d34ef..12c3cfa642 100644
--- a/arch/arm/boards/phytec-som-imx6/lowlevel.c
+++ b/arch/arm/boards/phytec-som-imx6/lowlevel.c
@@ -68,7 +68,7 @@ static void __noreturn start_imx6_phytec_common(uint32_t size,
 	if (do_early_uart_config && IS_ENABLED(CONFIG_DEBUG_LL))
 		setup_uart();
 
-	fdt = fdt_blob_fixed_offset - get_runtime_offset();
+	fdt = fdt_blob_fixed_offset + get_runtime_offset();
 
 	if (cpu_type == IMX6_CPUTYPE_IMX6UL
 	    || cpu_type == IMX6_CPUTYPE_IMX6ULL)
diff --git a/arch/arm/boards/phytec-som-rk3288/lowlevel.c b/arch/arm/boards/phytec-som-rk3288/lowlevel.c
index 7649ef864a..9def80ddb8 100644
--- a/arch/arm/boards/phytec-som-rk3288/lowlevel.c
+++ b/arch/arm/boards/phytec-som-rk3288/lowlevel.c
@@ -37,7 +37,7 @@ ENTRY_FUNCTION(start_rk3288_phycore_som, r0, r1, r2)
 			     GPIO7C6_UART2DBG_SIN << GPIO7C6_SHIFT);
 		INIT_LL();
 	}
-	fdt = __dtb_rk3288_phycore_som_start - get_runtime_offset();
+	fdt = __dtb_rk3288_phycore_som_start + get_runtime_offset();
 
 	barebox_arm_entry(0x0, SZ_1G, fdt);
 }
diff --git a/arch/arm/boards/plathome-openblocks-a6/lowlevel.c b/arch/arm/boards/plathome-openblocks-a6/lowlevel.c
index 785ec210dc..31a28c8916 100644
--- a/arch/arm/boards/plathome-openblocks-a6/lowlevel.c
+++ b/arch/arm/boards/plathome-openblocks-a6/lowlevel.c
@@ -25,7 +25,7 @@ ENTRY_FUNCTION(start_plathome_openblocks_a6, r0, r1, r2)
 
 	arm_cpu_lowlevel_init();
 
-	fdt = __dtb_kirkwood_openblocks_a6_bb_start -
+	fdt = __dtb_kirkwood_openblocks_a6_bb_start +
 		get_runtime_offset();
 
 	kirkwood_barebox_entry(fdt);
diff --git a/arch/arm/boards/plathome-openblocks-ax3/lowlevel.c b/arch/arm/boards/plathome-openblocks-ax3/lowlevel.c
index ae3664defc..f029bd1ba6 100644
--- a/arch/arm/boards/plathome-openblocks-ax3/lowlevel.c
+++ b/arch/arm/boards/plathome-openblocks-ax3/lowlevel.c
@@ -28,7 +28,7 @@ ENTRY_FUNCTION(start_plathome_openblocks_ax3, r0, r1, r2)
 
 	arm_cpu_lowlevel_init();
 
-	fdt = __dtb_armada_xp_openblocks_ax3_4_bb_start -
+	fdt = __dtb_armada_xp_openblocks_ax3_4_bb_start +
 		get_runtime_offset();
 
 	armada_370_xp_barebox_entry(fdt);
diff --git a/arch/arm/boards/radxa-rock/lowlevel.c b/arch/arm/boards/radxa-rock/lowlevel.c
index 1c07bc3377..611dc938cf 100644
--- a/arch/arm/boards/radxa-rock/lowlevel.c
+++ b/arch/arm/boards/radxa-rock/lowlevel.c
@@ -24,7 +24,7 @@ ENTRY_FUNCTION(start_radxa_rock, r0, r1, r2)
 
 	arm_cpu_lowlevel_init();
 
-	fdt = __dtb_rk3188_radxarock_start - get_runtime_offset();
+	fdt = __dtb_rk3188_radxarock_start + get_runtime_offset();
 
 	barebox_arm_entry(0x60000000, SZ_2G, fdt);
 }
diff --git a/arch/arm/boards/raspberry-pi/lowlevel.c b/arch/arm/boards/raspberry-pi/lowlevel.c
index 4e71e29e0c..cbc6caa4b9 100644
--- a/arch/arm/boards/raspberry-pi/lowlevel.c
+++ b/arch/arm/boards/raspberry-pi/lowlevel.c
@@ -7,7 +7,7 @@
 extern char __dtb_bcm2835_rpi_start[];
 ENTRY_FUNCTION(start_raspberry_pi1, r0, r1, r2)
 {
-	void *fdt = __dtb_bcm2835_rpi_start - get_runtime_offset();
+	void *fdt = __dtb_bcm2835_rpi_start + get_runtime_offset();
 
 	arm_cpu_lowlevel_init();
 
@@ -17,7 +17,7 @@ ENTRY_FUNCTION(start_raspberry_pi1, r0, r1, r2)
 extern char __dtb_bcm2836_rpi_2_start[];
 ENTRY_FUNCTION(start_raspberry_pi2, r0, r1, r2)
 {
-	void *fdt = __dtb_bcm2836_rpi_2_start - get_runtime_offset();
+	void *fdt = __dtb_bcm2836_rpi_2_start + get_runtime_offset();
 
 	arm_cpu_lowlevel_init();
 
diff --git a/arch/arm/boards/reflex-achilles/lowlevel.c b/arch/arm/boards/reflex-achilles/lowlevel.c
index 12994177cc..25e7ad0f1c 100644
--- a/arch/arm/boards/reflex-achilles/lowlevel.c
+++ b/arch/arm/boards/reflex-achilles/lowlevel.c
@@ -33,7 +33,7 @@ static noinline void achilles_entry(void)
 
 	puts_ll("SDRAM setup done\n");
 
-	fdt = __dtb_socfpga_arria10_achilles_start - get_runtime_offset();
+	fdt = __dtb_socfpga_arria10_achilles_start + get_runtime_offset();
 
 	barebox_arm_entry(0x0, SZ_2G + SZ_1G, fdt);
 }
diff --git a/arch/arm/boards/solidrun-cubox/lowlevel.c b/arch/arm/boards/solidrun-cubox/lowlevel.c
index 071309ee3d..ec63986b38 100644
--- a/arch/arm/boards/solidrun-cubox/lowlevel.c
+++ b/arch/arm/boards/solidrun-cubox/lowlevel.c
@@ -29,7 +29,7 @@ ENTRY_FUNCTION(start_solidrun_cubox, r0, r1, r2)
 
 	arm_cpu_lowlevel_init();
 
-	fdt = __dtb_dove_cubox_bb_start - get_runtime_offset();
+	fdt = __dtb_dove_cubox_bb_start + get_runtime_offset();
 
 	dove_barebox_entry(fdt);
 }
diff --git a/arch/arm/boards/solidrun-microsom/lowlevel.c b/arch/arm/boards/solidrun-microsom/lowlevel.c
index cc15958d64..ea204e15f3 100644
--- a/arch/arm/boards/solidrun-microsom/lowlevel.c
+++ b/arch/arm/boards/solidrun-microsom/lowlevel.c
@@ -15,7 +15,7 @@ ENTRY_FUNCTION(start_hummingboard_microsom_i1, r0, r1, r2)
 
 	imx6_cpu_lowlevel_init();
 
-	fdt = __dtb_imx6dl_hummingboard_start - get_runtime_offset();
+	fdt = __dtb_imx6dl_hummingboard_start + get_runtime_offset();
 	imx6q_barebox_entry(fdt);
 }
 
@@ -25,7 +25,7 @@ ENTRY_FUNCTION(start_hummingboard_microsom_i2, r0, r1, r2)
 
 	imx6_cpu_lowlevel_init();
 
-	fdt = __dtb_imx6dl_hummingboard_start - get_runtime_offset();
+	fdt = __dtb_imx6dl_hummingboard_start + get_runtime_offset();
 	imx6q_barebox_entry(fdt);
 }
 
@@ -35,7 +35,7 @@ ENTRY_FUNCTION(start_hummingboard_microsom_i2ex, r0, r1, r2)
 
 	imx6_cpu_lowlevel_init();
 
-	fdt = __dtb_imx6q_hummingboard_start - get_runtime_offset();
+	fdt = __dtb_imx6q_hummingboard_start + get_runtime_offset();
 	imx6q_barebox_entry(fdt);
 }
 
@@ -45,7 +45,7 @@ ENTRY_FUNCTION(start_hummingboard_microsom_i4, r0, r1, r2)
 
 	imx6_cpu_lowlevel_init();
 
-	fdt = __dtb_imx6q_hummingboard_start - get_runtime_offset();
+	fdt = __dtb_imx6q_hummingboard_start + get_runtime_offset();
 	imx6q_barebox_entry(fdt);
 }
 
@@ -55,7 +55,7 @@ ENTRY_FUNCTION(start_hummingboard2_microsom_i1, r0, r1, r2)
 
 	imx6_cpu_lowlevel_init();
 
-	fdt = __dtb_imx6dl_hummingboard2_start - get_runtime_offset();
+	fdt = __dtb_imx6dl_hummingboard2_start + get_runtime_offset();
 	imx6q_barebox_entry(fdt);
 }
 
@@ -65,7 +65,7 @@ ENTRY_FUNCTION(start_hummingboard2_microsom_i2, r0, r1, r2)
 
 	imx6_cpu_lowlevel_init();
 
-	fdt = __dtb_imx6dl_hummingboard2_start - get_runtime_offset();
+	fdt = __dtb_imx6dl_hummingboard2_start + get_runtime_offset();
 	imx6q_barebox_entry(fdt);
 }
 
@@ -75,7 +75,7 @@ ENTRY_FUNCTION(start_hummingboard2_microsom_i2ex, r0, r1, r2)
 
 	imx6_cpu_lowlevel_init();
 
-	fdt = __dtb_imx6q_hummingboard2_start - get_runtime_offset();
+	fdt = __dtb_imx6q_hummingboard2_start + get_runtime_offset();
 	imx6q_barebox_entry(fdt);
 }
 
@@ -85,7 +85,7 @@ ENTRY_FUNCTION(start_hummingboard2_microsom_i4, r0, r1, r2)
 
 	imx6_cpu_lowlevel_init();
 
-	fdt = __dtb_imx6q_hummingboard2_start - get_runtime_offset();
+	fdt = __dtb_imx6q_hummingboard2_start + get_runtime_offset();
 	imx6q_barebox_entry(fdt);
 }
 
@@ -95,6 +95,6 @@ ENTRY_FUNCTION(start_h100_microsom_i2ex, r0, r1, r2)
 
 	imx6_cpu_lowlevel_init();
 
-	fdt = __dtb_imx6q_h100_start - get_runtime_offset();
+	fdt = __dtb_imx6q_h100_start + get_runtime_offset();
 	imx6q_barebox_entry(fdt);
 }
diff --git a/arch/arm/boards/technexion-pico-hobbit/lowlevel.c b/arch/arm/boards/technexion-pico-hobbit/lowlevel.c
index f351e67dd7..77f48043da 100644
--- a/arch/arm/boards/technexion-pico-hobbit/lowlevel.c
+++ b/arch/arm/boards/technexion-pico-hobbit/lowlevel.c
@@ -55,7 +55,7 @@ static void __noreturn start_imx6_pico_hobbit_common(uint32_t size,
 	writew(0x0, 0x020c0008);
 	writew(0x0, 0x021e4008);
 
-	fdt = fdt_blob_fixed_offset - get_runtime_offset();
+	fdt = fdt_blob_fixed_offset + get_runtime_offset();
 
 	imx6ul_barebox_entry(fdt);
 }
diff --git a/arch/arm/boards/terasic-de0-nano-soc/lowlevel.c b/arch/arm/boards/terasic-de0-nano-soc/lowlevel.c
index 1d5ea6b12a..dfb8271724 100644
--- a/arch/arm/boards/terasic-de0-nano-soc/lowlevel.c
+++ b/arch/arm/boards/terasic-de0-nano-soc/lowlevel.c
@@ -26,7 +26,7 @@ ENTRY_FUNCTION(start_socfpga_de0_nano_soc, r0, r1, r2)
 
 	arm_cpu_lowlevel_init();
 
-	fdt = __dtb_socfpga_cyclone5_de0_nano_soc_start - get_runtime_offset();
+	fdt = __dtb_socfpga_cyclone5_de0_nano_soc_start + get_runtime_offset();
 
 	barebox_arm_entry(0x0, SZ_1G, fdt);
 }
diff --git a/arch/arm/boards/terasic-sockit/lowlevel.c b/arch/arm/boards/terasic-sockit/lowlevel.c
index 0a6eb21365..05b7d800a2 100644
--- a/arch/arm/boards/terasic-sockit/lowlevel.c
+++ b/arch/arm/boards/terasic-sockit/lowlevel.c
@@ -52,7 +52,7 @@ ENTRY_FUNCTION(start_socfpga_sockit, r0, r1, r2)
 
 	arm_cpu_lowlevel_init();
 
-	fdt = __dtb_socfpga_cyclone5_sockit_start - get_runtime_offset();
+	fdt = __dtb_socfpga_cyclone5_sockit_start + get_runtime_offset();
 
 	barebox_arm_entry(0x0, SZ_1G, fdt);
 }
diff --git a/arch/arm/boards/tqma53/lowlevel.c b/arch/arm/boards/tqma53/lowlevel.c
index 0cb5952608..0d0b16846c 100644
--- a/arch/arm/boards/tqma53/lowlevel.c
+++ b/arch/arm/boards/tqma53/lowlevel.c
@@ -51,7 +51,7 @@ ENTRY_FUNCTION(start_imx53_mba53_512mib, r0, r1, r2)
 
 	imx53_init_lowlevel_early(800);
 
-	fdt = __dtb_imx53_mba53_start - get_runtime_offset();
+	fdt = __dtb_imx53_mba53_start + get_runtime_offset();
 
 	start_imx53_tqma53_common(fdt);
 }
@@ -70,7 +70,7 @@ ENTRY_FUNCTION(start_imx53_mba53_1gib, r0, r1, r2)
 
 	imx53_init_lowlevel_early(800);
 
-	fdt = __dtb_imx53_mba53_start - get_runtime_offset();
+	fdt = __dtb_imx53_mba53_start + get_runtime_offset();
 
 	start_imx53_tqma53_common(fdt);
 }
diff --git a/arch/arm/boards/tqma6x/lowlevel.c b/arch/arm/boards/tqma6x/lowlevel.c
index 52afee4b75..a90cd4007f 100644
--- a/arch/arm/boards/tqma6x/lowlevel.c
+++ b/arch/arm/boards/tqma6x/lowlevel.c
@@ -42,7 +42,7 @@ ENTRY_FUNCTION(start_imx6q_mba6x, r0, r1, r2)
 
 	arm_early_mmu_cache_invalidate();
 
-	fdt = __dtb_imx6q_mba6x_start - get_runtime_offset();
+	fdt = __dtb_imx6q_mba6x_start + get_runtime_offset();
 
 	barebox_arm_entry(0x10000000, SZ_1G, fdt);
 }
@@ -63,7 +63,7 @@ ENTRY_FUNCTION(start_imx6dl_mba6x, r0, r1, r2)
 
 	arm_early_mmu_cache_invalidate();
 
-	fdt = __dtb_imx6dl_mba6x_start - get_runtime_offset();
+	fdt = __dtb_imx6dl_mba6x_start + get_runtime_offset();
 
 	barebox_arm_entry(0x10000000, SZ_512M, fdt);
 }
diff --git a/arch/arm/boards/turris-omnia/lowlevel.c b/arch/arm/boards/turris-omnia/lowlevel.c
index 3f20908ff7..7236211c40 100644
--- a/arch/arm/boards/turris-omnia/lowlevel.c
+++ b/arch/arm/boards/turris-omnia/lowlevel.c
@@ -26,7 +26,7 @@ ENTRY_FUNCTION(start_turris_omnia, r0, r1, r2)
 
 	arm_cpu_lowlevel_init();
 
-	fdt = __dtb_armada_385_turris_omnia_bb_start -
+	fdt = __dtb_armada_385_turris_omnia_bb_start +
 		get_runtime_offset();
 
 	armada_370_xp_barebox_entry(fdt);
diff --git a/arch/arm/boards/udoo/lowlevel.c b/arch/arm/boards/udoo/lowlevel.c
index 785ab16678..1f06f7e37f 100644
--- a/arch/arm/boards/udoo/lowlevel.c
+++ b/arch/arm/boards/udoo/lowlevel.c
@@ -12,7 +12,7 @@ ENTRY_FUNCTION(start_imx6_udoo, r0, r1, r2)
 
 	imx6_cpu_lowlevel_init();
 
-	fdt = __dtb_imx6q_udoo_start - get_runtime_offset();
+	fdt = __dtb_imx6q_udoo_start + get_runtime_offset();
 
 	barebox_arm_entry(0x10000000, SZ_1G, fdt);
 }
diff --git a/arch/arm/boards/usi-topkick/lowlevel.c b/arch/arm/boards/usi-topkick/lowlevel.c
index 4c731e5621..4202138986 100644
--- a/arch/arm/boards/usi-topkick/lowlevel.c
+++ b/arch/arm/boards/usi-topkick/lowlevel.c
@@ -28,7 +28,7 @@ ENTRY_FUNCTION(start_usi_topkick, r0, r1, r2)
 
 	arm_cpu_lowlevel_init();
 
-	fdt = __dtb_kirkwood_topkick_bb_start - get_runtime_offset();
+	fdt = __dtb_kirkwood_topkick_bb_start + get_runtime_offset();
 
 	kirkwood_barebox_entry(fdt);
 }
diff --git a/arch/arm/boards/variscite-mx6/lowlevel.c b/arch/arm/boards/variscite-mx6/lowlevel.c
index 5cb738acb2..337bc58c8d 100644
--- a/arch/arm/boards/variscite-mx6/lowlevel.c
+++ b/arch/arm/boards/variscite-mx6/lowlevel.c
@@ -50,7 +50,7 @@ ENTRY_FUNCTION(start_variscite_custom, r0, r1, r2)
 	if (IS_ENABLED(CONFIG_DEBUG_LL))
 	    setup_uart();
 
-	fdt = __dtb_imx6q_var_custom_start - get_runtime_offset();
+	fdt = __dtb_imx6q_var_custom_start + get_runtime_offset();
 
 	barebox_arm_entry(0x10000000, SZ_1G, fdt);
 }
diff --git a/arch/arm/boards/vexpress/lowlevel.c b/arch/arm/boards/vexpress/lowlevel.c
index 9fe7c836b7..ac27fbd7c6 100644
--- a/arch/arm/boards/vexpress/lowlevel.c
+++ b/arch/arm/boards/vexpress/lowlevel.c
@@ -14,7 +14,7 @@
 
 static inline void start_vexpress_common(void *internal_dt)
 {
-	void *fdt = internal_dt - get_runtime_offset();
+	void *fdt = internal_dt + get_runtime_offset();
 	unsigned long membase, memsize = SZ_512M;
 
 	arm_cpu_lowlevel_init();
diff --git a/arch/arm/boards/vscom-baltos/lowlevel.c b/arch/arm/boards/vscom-baltos/lowlevel.c
index c4e234196e..98bbbaae16 100644
--- a/arch/arm/boards/vscom-baltos/lowlevel.c
+++ b/arch/arm/boards/vscom-baltos/lowlevel.c
@@ -134,7 +134,7 @@ ENTRY_FUNCTION(start_am33xx_baltos_sdram, r0, r1, r2)
 
 	fdt = __dtb_am335x_baltos_minimal_start;
 
-	fdt -= get_runtime_offset();
+	fdt += get_runtime_offset();
 
 	am335x_barebox_entry(fdt);
 }
diff --git a/arch/arm/boards/zii-imx6q-rdu2/lowlevel.c b/arch/arm/boards/zii-imx6q-rdu2/lowlevel.c
index fb5e961e09..22ffdf85ea 100644
--- a/arch/arm/boards/zii-imx6q-rdu2/lowlevel.c
+++ b/arch/arm/boards/zii-imx6q-rdu2/lowlevel.c
@@ -308,9 +308,9 @@ ENTRY_FUNCTION(start_imx6_zii_rdu2, r0, r1, r2)
 		rdu2_sram_setup();
 
 	if (__imx6_cpu_revision() == IMX_CHIP_REV_2_0)
-		imx6q_barebox_entry(__dtb_imx6qp_zii_rdu2_start -
+		imx6q_barebox_entry(__dtb_imx6qp_zii_rdu2_start +
 				    get_runtime_offset());
 	else
-		imx6q_barebox_entry(__dtb_imx6q_zii_rdu2_start -
+		imx6q_barebox_entry(__dtb_imx6q_zii_rdu2_start +
 				    get_runtime_offset());
 }
diff --git a/arch/arm/boards/zii-vf610-dev/lowlevel.c b/arch/arm/boards/zii-vf610-dev/lowlevel.c
index 95b68d5dce..c6663c1415 100644
--- a/arch/arm/boards/zii-vf610-dev/lowlevel.c
+++ b/arch/arm/boards/zii-vf610-dev/lowlevel.c
@@ -133,5 +133,5 @@ ENTRY_FUNCTION(start_zii_vf610_dev, r0, r1, r2)
 		break;
 	}
 
-	barebox_arm_entry(0x80000000, SZ_512M, fdt - get_runtime_offset());
+	barebox_arm_entry(0x80000000, SZ_512M, fdt + get_runtime_offset());
 }
diff --git a/arch/arm/cpu/common.c b/arch/arm/cpu/common.c
index 7d749967e1..6670f4b9f8 100644
--- a/arch/arm/cpu/common.c
+++ b/arch/arm/cpu/common.c
@@ -37,26 +37,26 @@ void relocate_to_current_adr(void)
 	/* Get offset between linked address and runtime address */
 	offset = get_runtime_offset();
 
-	dstart = (void *)(ld_var(__rel_dyn_start) - offset);
-	dend = (void *)(ld_var(__rel_dyn_end) - offset);
+	dstart = (void *)(ld_var(__rel_dyn_start) + offset);
+	dend = (void *)(ld_var(__rel_dyn_end) + offset);
 
-	dynsym = (void *)(ld_var(__dynsym_start) - offset);
-	dynend = (void *)(ld_var(__dynsym_end) - offset);
+	dynsym = (void *)(ld_var(__dynsym_start) + offset);
+	dynend = (void *)(ld_var(__dynsym_end) + offset);
 
 	while (dstart < dend) {
-		uint32_t *fixup = (uint32_t *)(*dstart - offset);
+		uint32_t *fixup = (uint32_t *)(*dstart + offset);
 		uint32_t type = *(dstart + 1);
 
 		if ((type & 0xff) == 0x17) {
-			*fixup = *fixup - offset;
+			*fixup = *fixup + offset;
 		} else {
 			int index = type >> 8;
 			uint32_t r = dynsym[index * 4 + 1];
 
-			*fixup = *fixup + r - offset;
+			*fixup = *fixup + r + offset;
 		}
 
-		*dstart -= offset;
+		*dstart += offset;
 		dstart += 2;
 	}
 
diff --git a/arch/arm/cpu/setupc.S b/arch/arm/cpu/setupc.S
index c232b08d3b..30e88330e7 100644
--- a/arch/arm/cpu/setupc.S
+++ b/arch/arm/cpu/setupc.S
@@ -15,7 +15,7 @@ ENTRY(setup_c)
 	push	{r4, r5}
 	mov	r5, lr
 	bl	get_runtime_offset
-	subs	r4, r0, #0
+	adds	r4, r0, #0
 	beq	1f			/* skip memcpy if already at correct address */
 	ldr	r0,=_text
 	ldr	r2,=__bss_start
@@ -58,7 +58,7 @@ ENTRY(relocate_to_adr)
 	ld_var	_text, r0, r4
 	mov	r8, r0
 
-	sub	r1, r0, r5		/* r1: from address */
+	add	r1, r0, r5		/* r1: from address */
 
 	cmp	r1, r6			/* already at correct address? */
 	beq	1f			/* yes, skip copy to new address */
@@ -68,8 +68,9 @@ ENTRY(relocate_to_adr)
 	sub	r2, r2, r0		/* r2: size */
 	mov	r0, r6			/* r0: target */
 
-	add	r7, r7, r0		/* adjust return address */
-	sub	r7, r7, r1		/* lr += offset */
+	/* adjust return address */
+	sub	r7, r7, r1		/* sub address where we are actually running */
+	add	r7, r7, r0		/* add address where we are going to run */
 
 	bl	memcpy			/* copy binary */
 
diff --git a/arch/arm/cpu/start-pbl.c b/arch/arm/cpu/start-pbl.c
index e851b4a2da..865aa1b1c4 100644
--- a/arch/arm/cpu/start-pbl.c
+++ b/arch/arm/cpu/start-pbl.c
@@ -61,8 +61,8 @@ __noreturn void barebox_single_pbl_start(unsigned long membase,
 	/* Get offset between linked address and runtime address */
 	offset = get_runtime_offset();
 
-	pg_start = (uint32_t)&input_data - offset;
-	pg_end = (uint32_t)&input_data_end - offset;
+	pg_start = (uint32_t)&input_data + offset;
+	pg_end = (uint32_t)&input_data_end + offset;
 	pg_len = pg_end - pg_start;
 	uncompressed_len = get_unaligned((const u32 *)(pg_start + pg_len - 4));
 
diff --git a/arch/arm/cpu/uncompress.c b/arch/arm/cpu/uncompress.c
index 9d7fe0e921..5530919118 100644
--- a/arch/arm/cpu/uncompress.c
+++ b/arch/arm/cpu/uncompress.c
@@ -53,7 +53,7 @@ void __noreturn barebox_multi_pbl_start(unsigned long membase,
 	void *pg_start;
 	unsigned long pc = get_pc();
 
-	image_end = (void *)ld_var(__image_end) - get_runtime_offset();
+	image_end = (void *)ld_var(__image_end) + get_runtime_offset();
 
 	if (IS_ENABLED(CONFIG_PBL_RELOCATABLE)) {
 		/*
diff --git a/arch/arm/lib32/runtime-offset.S b/arch/arm/lib32/runtime-offset.S
index 7375cb961b..39b525b187 100644
--- a/arch/arm/lib32/runtime-offset.S
+++ b/arch/arm/lib32/runtime-offset.S
@@ -10,8 +10,8 @@
 ENTRY(get_runtime_offset)
 1:	adr r0, 1b
 	ldr r1, linkadr
-	subs r0, r1, r0
-THUMB(	subs r0, r0, #1)
+	subs r0, r0, r1
+THUMB(	adds r0, r0, #1)
 	mov pc, lr
 
 linkadr:
diff --git a/arch/arm/mach-mvebu/include/mach/common.h b/arch/arm/mach-mvebu/include/mach/common.h
index 529eb61cfd..aa4babcfa7 100644
--- a/arch/arm/mach-mvebu/include/mach/common.h
+++ b/arch/arm/mach-mvebu/include/mach/common.h
@@ -30,7 +30,7 @@ uint32_t get_runtime_offset(void);
 static inline void __iomem *mvebu_get_initial_int_reg_base(void)
 {
 #ifdef __PBL__
-	u32 base = __get_unaligned_le32(_text - get_runtime_offset() + 0x30);
+	u32 base = __get_unaligned_le32(_text + get_runtime_offset() + 0x30);
 	return (void __force __iomem *)base;
 #else
 	return (void __force __iomem *)MVEBU_REMAP_INT_REG_BASE;
diff --git a/arch/arm/mach-tegra/include/mach/lowlevel.h b/arch/arm/mach-tegra/include/mach/lowlevel.h
index e9ba5ee393..c862778fc4 100644
--- a/arch/arm/mach-tegra/include/mach/lowlevel.h
+++ b/arch/arm/mach-tegra/include/mach/lowlevel.h
@@ -264,7 +264,7 @@ void tegra_cpu_lowlevel_setup(char *fdt)
 	arm_setup_stack(TEGRA_IRAM_BASE + SZ_256K - 8);
 
 	if (tegra_cpu_is_maincomplex())
-		tegra_maincomplex_entry(fdt - get_runtime_offset());
+		tegra_maincomplex_entry(fdt + get_runtime_offset());
 
 	tegra_ll_delay_setup();
 }
diff --git a/arch/arm/mach-tegra/tegra_avp_init.c b/arch/arm/mach-tegra/tegra_avp_init.c
index 16dc65be07..8a11e06c53 100644
--- a/arch/arm/mach-tegra/tegra_avp_init.c
+++ b/arch/arm/mach-tegra/tegra_avp_init.c
@@ -140,7 +140,7 @@ static void init_pllx(void)
 
 	conf = &pllx_config_table[chiptype][osc_freq];
 	/* we are not relocated yet - globals are a bit more tricky here */
-	conf = (struct pll_config *)((char *)conf - get_runtime_offset());
+	conf = (struct pll_config *)((char *)conf + get_runtime_offset());
 
 	/* set PLL bypass and frequency parameters */
 	reg = CRC_PLLX_BASE_BYPASS;
-- 
2.16.1



From s.hauer at pengutronix.de  Fri Mar 16 05:53:42 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 16 Mar 2018 13:53:42 +0100
Subject: [PATCH 66/78] dt-bindings: Drop unused files
In-Reply-To: <20180316125354.23462-1-s.hauer@pengutronix.de>
References: <20180316125354.23462-1-s.hauer@pengutronix.de>
Message-ID: <20180316125354.23462-67-s.hauer@pengutronix.de>

include/dt-bindings is not included in device tree builds anymore since
2014. Since then this directory is unused, so remove the files in it.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 include/dt-bindings/clock/tegra30-car.h     | 265 ----------------------------
 include/dt-bindings/pinctrl/pinctrl-tegra.h |  45 -----
 include/dt-bindings/pinctrl/rockchip.h      |  32 ----
 3 files changed, 342 deletions(-)
 delete mode 100644 include/dt-bindings/clock/tegra30-car.h
 delete mode 100644 include/dt-bindings/pinctrl/pinctrl-tegra.h
 delete mode 100644 include/dt-bindings/pinctrl/rockchip.h

diff --git a/include/dt-bindings/clock/tegra30-car.h b/include/dt-bindings/clock/tegra30-car.h
deleted file mode 100644
index e40fae8f9a..0000000000
--- a/include/dt-bindings/clock/tegra30-car.h
+++ /dev/null
@@ -1,265 +0,0 @@
-/*
- * This header provides constants for binding nvidia,tegra30-car.
- *
- * The first 130 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
- * registers. These IDs often match those in the CAR's RST_DEVICES registers,
- * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
- * this case, those clocks are assigned IDs above 160 in order to highlight
- * this issue. Implementations that interpret these clock IDs as bit values
- * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
- * explicitly handle these special cases.
- *
- * The balance of the clocks controlled by the CAR are assigned IDs of 160 and
- * above.
- */
-
-#ifndef _DT_BINDINGS_CLOCK_TEGRA30_CAR_H
-#define _DT_BINDINGS_CLOCK_TEGRA30_CAR_H
-
-#define TEGRA30_CLK_CPU 0
-/* 1 */
-/* 2 */
-/* 3 */
-#define TEGRA30_CLK_RTC 4
-#define TEGRA30_CLK_TIMER 5
-#define TEGRA30_CLK_UARTA 6
-/* 7 (register bit affects uartb and vfir) */
-#define TEGRA30_CLK_GPIO 8
-#define TEGRA30_CLK_SDMMC2 9
-/* 10 (register bit affects spdif_in and spdif_out) */
-#define TEGRA30_CLK_I2S1 11
-#define TEGRA30_CLK_I2C1 12
-#define TEGRA30_CLK_NDFLASH 13
-#define TEGRA30_CLK_SDMMC1 14
-#define TEGRA30_CLK_SDMMC4 15
-/* 16 */
-#define TEGRA30_CLK_PWM 17
-#define TEGRA30_CLK_I2S2 18
-#define TEGRA30_CLK_EPP 19
-/* 20 (register bit affects vi and vi_sensor) */
-#define TEGRA30_CLK_GR2D 21
-#define TEGRA30_CLK_USBD 22
-#define TEGRA30_CLK_ISP 23
-#define TEGRA30_CLK_GR3D 24
-/* 25 */
-#define TEGRA30_CLK_DISP2 26
-#define TEGRA30_CLK_DISP1 27
-#define TEGRA30_CLK_HOST1X 28
-#define TEGRA30_CLK_VCP 29
-#define TEGRA30_CLK_I2S0 30
-#define TEGRA30_CLK_COP_CACHE 31
-
-#define TEGRA30_CLK_MC 32
-#define TEGRA30_CLK_AHBDMA 33
-#define TEGRA30_CLK_APBDMA 34
-/* 35 */
-#define TEGRA30_CLK_KBC 36
-#define TEGRA30_CLK_STATMON 37
-#define TEGRA30_CLK_PMC 38
-/* 39 (register bit affects fuse and fuse_burn) */
-#define TEGRA30_CLK_KFUSE 40
-#define TEGRA30_CLK_SBC1 41
-#define TEGRA30_CLK_NOR 42
-/* 43 */
-#define TEGRA30_CLK_SBC2 44
-/* 45 */
-#define TEGRA30_CLK_SBC3 46
-#define TEGRA30_CLK_I2C5 47
-#define TEGRA30_CLK_DSIA 48
-/* 49 (register bit affects cve and tvo) */
-#define TEGRA30_CLK_MIPI 50
-#define TEGRA30_CLK_HDMI 51
-#define TEGRA30_CLK_CSI 52
-#define TEGRA30_CLK_TVDAC 53
-#define TEGRA30_CLK_I2C2 54
-#define TEGRA30_CLK_UARTC 55
-/* 56 */
-#define TEGRA30_CLK_EMC 57
-#define TEGRA30_CLK_USB2 58
-#define TEGRA30_CLK_USB3 59
-#define TEGRA30_CLK_MPE 60
-#define TEGRA30_CLK_VDE 61
-#define TEGRA30_CLK_BSEA 62
-#define TEGRA30_CLK_BSEV 63
-
-#define TEGRA30_CLK_SPEEDO 64
-#define TEGRA30_CLK_UARTD 65
-#define TEGRA30_CLK_UARTE 66
-#define TEGRA30_CLK_I2C3 67
-#define TEGRA30_CLK_SBC4 68
-#define TEGRA30_CLK_SDMMC3 69
-#define TEGRA30_CLK_PCIE 70
-#define TEGRA30_CLK_OWR 71
-#define TEGRA30_CLK_AFI 72
-#define TEGRA30_CLK_CSITE 73
-#define TEGRA30_CLK_PCIEX 74
-#define TEGRA30_CLK_AVPUCQ 75
-#define TEGRA30_CLK_LA 76
-/* 77 */
-/* 78 */
-#define TEGRA30_CLK_DTV 79
-#define TEGRA30_CLK_NDSPEED 80
-#define TEGRA30_CLK_I2CSLOW 81
-#define TEGRA30_CLK_DSIB 82
-/* 83 */
-#define TEGRA30_CLK_IRAMA 84
-#define TEGRA30_CLK_IRAMB 85
-#define TEGRA30_CLK_IRAMC 86
-#define TEGRA30_CLK_IRAMD 87
-#define TEGRA30_CLK_CRAM2 88
-/* 89 */
-#define TEGRA30_CLK_AUDIO_2X 90 /* a/k/a audio_2x_sync_clk */
-/* 91 */
-#define TEGRA30_CLK_CSUS 92
-#define TEGRA30_CLK_CDEV2 93
-#define TEGRA30_CLK_CDEV1 94
-/* 95 */
-
-#define TEGRA30_CLK_CPU_G 96
-#define TEGRA30_CLK_CPU_LP 97
-#define TEGRA30_CLK_GR3D2 98
-#define TEGRA30_CLK_MSELECT 99
-#define TEGRA30_CLK_TSENSOR 100
-#define TEGRA30_CLK_I2S3 101
-#define TEGRA30_CLK_I2S4 102
-#define TEGRA30_CLK_I2C4 103
-#define TEGRA30_CLK_SBC5 104
-#define TEGRA30_CLK_SBC6 105
-#define TEGRA30_CLK_D_AUDIO 106
-#define TEGRA30_CLK_APBIF 107
-#define TEGRA30_CLK_DAM0 108
-#define TEGRA30_CLK_DAM1 109
-#define TEGRA30_CLK_DAM2 110
-#define TEGRA30_CLK_HDA2CODEC_2X 111
-#define TEGRA30_CLK_ATOMICS 112
-#define TEGRA30_CLK_AUDIO0_2X 113
-#define TEGRA30_CLK_AUDIO1_2X 114
-#define TEGRA30_CLK_AUDIO2_2X 115
-#define TEGRA30_CLK_AUDIO3_2X 116
-#define TEGRA30_CLK_AUDIO4_2X 117
-#define TEGRA30_CLK_SPDIF_2X 118
-#define TEGRA30_CLK_ACTMON 119
-#define TEGRA30_CLK_EXTERN1 120
-#define TEGRA30_CLK_EXTERN2 121
-#define TEGRA30_CLK_EXTERN3 122
-#define TEGRA30_CLK_SATA_OOB 123
-#define TEGRA30_CLK_SATA 124
-#define TEGRA30_CLK_HDA 125
-/* 126 */
-#define TEGRA30_CLK_SE 127
-
-#define TEGRA30_CLK_HDA2HDMI 128
-#define TEGRA30_CLK_SATA_COLD 129
-/* 130 */
-/* 131 */
-/* 132 */
-/* 133 */
-/* 134 */
-/* 135 */
-/* 136 */
-/* 137 */
-/* 138 */
-/* 139 */
-/* 140 */
-/* 141 */
-/* 142 */
-/* 143 */
-/* 144 */
-/* 145 */
-/* 146 */
-/* 147 */
-/* 148 */
-/* 149 */
-/* 150 */
-/* 151 */
-/* 152 */
-/* 153 */
-/* 154 */
-/* 155 */
-/* 156 */
-/* 157 */
-/* 158 */
-/* 159 */
-
-#define TEGRA30_CLK_UARTB 160
-#define TEGRA30_CLK_VFIR 161
-#define TEGRA30_CLK_SPDIF_IN 162
-#define TEGRA30_CLK_SPDIF_OUT 163
-#define TEGRA30_CLK_VI 164
-#define TEGRA30_CLK_VI_SENSOR 165
-#define TEGRA30_CLK_FUSE 166
-#define TEGRA30_CLK_FUSE_BURN 167
-#define TEGRA30_CLK_CVE 168
-#define TEGRA30_CLK_TVO 169
-#define TEGRA30_CLK_CLK_32K 170
-#define TEGRA30_CLK_CLK_M 171
-#define TEGRA30_CLK_CLK_M_DIV2 172
-#define TEGRA30_CLK_CLK_M_DIV4 173
-#define TEGRA30_CLK_PLL_REF 174
-#define TEGRA30_CLK_PLL_C 175
-#define TEGRA30_CLK_PLL_C_OUT1 176
-#define TEGRA30_CLK_PLL_M 177
-#define TEGRA30_CLK_PLL_M_OUT1 178
-#define TEGRA30_CLK_PLL_P 179
-#define TEGRA30_CLK_PLL_P_OUT1 180
-#define TEGRA30_CLK_PLL_P_OUT2 181
-#define TEGRA30_CLK_PLL_P_OUT3 182
-#define TEGRA30_CLK_PLL_P_OUT4 183
-#define TEGRA30_CLK_PLL_A 184
-#define TEGRA30_CLK_PLL_A_OUT0 185
-#define TEGRA30_CLK_PLL_D 186
-#define TEGRA30_CLK_PLL_D_OUT0 187
-#define TEGRA30_CLK_PLL_D2 188
-#define TEGRA30_CLK_PLL_D2_OUT0 189
-#define TEGRA30_CLK_PLL_U 190
-#define TEGRA30_CLK_PLL_X 191
-
-#define TEGRA30_CLK_PLL_X_OUT0 192
-#define TEGRA30_CLK_PLL_E 193
-#define TEGRA30_CLK_SPDIF_IN_SYNC 194
-#define TEGRA30_CLK_I2S0_SYNC 195
-#define TEGRA30_CLK_I2S1_SYNC 196
-#define TEGRA30_CLK_I2S2_SYNC 197
-#define TEGRA30_CLK_I2S3_SYNC 198
-#define TEGRA30_CLK_I2S4_SYNC 199
-#define TEGRA30_CLK_VIMCLK_SYNC 200
-#define TEGRA30_CLK_AUDIO0 201
-#define TEGRA30_CLK_AUDIO1 202
-#define TEGRA30_CLK_AUDIO2 203
-#define TEGRA30_CLK_AUDIO3 204
-#define TEGRA30_CLK_AUDIO4 205
-#define TEGRA30_CLK_SPDIF 206
-#define TEGRA30_CLK_CLK_OUT_1 207 /* (extern1) */
-#define TEGRA30_CLK_CLK_OUT_2 208 /* (extern2) */
-#define TEGRA30_CLK_CLK_OUT_3 209 /* (extern3) */
-#define TEGRA30_CLK_SCLK 210
-#define TEGRA30_CLK_BLINK 211
-#define TEGRA30_CLK_CCLK_G 212
-#define TEGRA30_CLK_CCLK_LP 213
-#define TEGRA30_CLK_TWD 214
-#define TEGRA30_CLK_CML0 215
-#define TEGRA30_CLK_CML1 216
-#define TEGRA30_CLK_HCLK 217
-#define TEGRA30_CLK_PCLK 218
-/* 219 */
-/* 220 */
-/* 221 */
-/* 222 */
-/* 223 */
-
-/* 288 */
-/* 289 */
-/* 290 */
-/* 291 */
-/* 292 */
-/* 293 */
-/* 294 */
-/* 295 */
-/* 296 */
-/* 297 */
-/* 298 */
-/* 299 */
-#define TEGRA30_CLK_CLK_OUT_1_MUX 300
-#define TEGRA30_CLK_CLK_MAX 301
-
-#endif	/* _DT_BINDINGS_CLOCK_TEGRA30_CAR_H */
diff --git a/include/dt-bindings/pinctrl/pinctrl-tegra.h b/include/dt-bindings/pinctrl/pinctrl-tegra.h
deleted file mode 100644
index ebafa498be..0000000000
--- a/include/dt-bindings/pinctrl/pinctrl-tegra.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * This header provides constants for Tegra pinctrl bindings.
- *
- * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
- *
- * Author: Laxman Dewangan <ldewangan at nvidia.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- */
-
-#ifndef _DT_BINDINGS_PINCTRL_TEGRA_H
-#define _DT_BINDINGS_PINCTRL_TEGRA_H
-
-/*
- * Enable/disable for diffeent dt properties. This is applicable for
- * properties nvidia,enable-input, nvidia,tristate, nvidia,open-drain,
- * nvidia,lock, nvidia,rcv-sel, nvidia,high-speed-mode, nvidia,schmitt.
- */
-#define TEGRA_PIN_DISABLE				0
-#define TEGRA_PIN_ENABLE				1
-
-#define TEGRA_PIN_PULL_NONE				0
-#define TEGRA_PIN_PULL_DOWN				1
-#define TEGRA_PIN_PULL_UP				2
-
-/* Low power mode driver */
-#define TEGRA_PIN_LP_DRIVE_DIV_8			0
-#define TEGRA_PIN_LP_DRIVE_DIV_4			1
-#define TEGRA_PIN_LP_DRIVE_DIV_2			2
-#define TEGRA_PIN_LP_DRIVE_DIV_1			3
-
-/* Rising/Falling slew rate */
-#define TEGRA_PIN_SLEW_RATE_FASTEST			0
-#define TEGRA_PIN_SLEW_RATE_FAST			1
-#define TEGRA_PIN_SLEW_RATE_SLOW			2
-#define TEGRA_PIN_SLEW_RATE_SLOWEST			3
-
-#endif
diff --git a/include/dt-bindings/pinctrl/rockchip.h b/include/dt-bindings/pinctrl/rockchip.h
deleted file mode 100644
index cd5788be82..0000000000
--- a/include/dt-bindings/pinctrl/rockchip.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * Header providing constants for Rockchip pinctrl bindings.
- *
- * Copyright (c) 2013 MundoReader S.L.
- * Author: Heiko Stuebner <heiko at sntech.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef __DT_BINDINGS_ROCKCHIP_PINCTRL_H__
-#define __DT_BINDINGS_ROCKCHIP_PINCTRL_H__
-
-#define RK_GPIO0	0
-#define RK_GPIO1	1
-#define RK_GPIO2	2
-#define RK_GPIO3	3
-#define RK_GPIO4	4
-#define RK_GPIO6	6
-
-#define RK_FUNC_GPIO	0
-#define RK_FUNC_1	1
-#define RK_FUNC_2	2
-
-#endif
-- 
2.16.1



From l.stach at pengutronix.de  Fri Mar 16 07:56:58 2018
From: l.stach at pengutronix.de (Lucas Stach)
Date: Fri, 16 Mar 2018 15:56:58 +0100
Subject: [PATCH] of: demote "no ranges" message to debug level
Message-ID: <20180316145658.14996-1-l.stach@pengutronix.de>

There are valid cases where there is no way to translate a OF node to
a MMIO address via ranges, so do the same as the Linux kernel and don't
print an error message in that case, but make it available as a debug
message.

Signed-off-by: Lucas Stach <l.stach at pengutronix.de>
---
 drivers/of/address.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/of/address.c b/drivers/of/address.c
index 8018d78bcbd8..14db08041725 100644
--- a/drivers/of/address.c
+++ b/drivers/of/address.c
@@ -314,7 +314,7 @@ static int of_translate_one(struct device_node *parent, struct of_bus *bus,
 	ranges = of_get_property(parent, rprop, &rlen);
 #if !defined(CONFIG_PPC)
 	if (ranges == NULL) {
-		pr_err("OF: no ranges; cannot translate\n");
+		pr_debug("OF: no ranges; cannot translate\n");
 		return 1;
 	}
 #endif /* !defined(CONFIG_PPC) */
-- 
2.16.1



From andrew.smirnov at gmail.com  Fri Mar 16 14:51:19 2018
From: andrew.smirnov at gmail.com (Andrey Smirnov)
Date: Fri, 16 Mar 2018 14:51:19 -0700
Subject: [PATCH 30/78] ARM: aarch64: Add relocation support
In-Reply-To: <20180316125354.23462-31-s.hauer@pengutronix.de>
References: <20180316125354.23462-1-s.hauer@pengutronix.de>
 <20180316125354.23462-31-s.hauer@pengutronix.de>
Message-ID: <CAHQ1cqGbkHN+Csi7-Bb=_iTea4zXK3-mmK8EK0x-UW9niHNCQg@mail.gmail.com>

On Fri, Mar 16, 2018 at 5:53 AM, Sascha Hauer <s.hauer at pengutronix.de> wrote:
> This adds aarch64 support for relocating binaries linked with -pie.
>
> Support is integrated into the already exisiting
> relocate_to_current_adr() function which is now used for both arm32
> and aarch64.
>
> Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>


Sascha:

Two small suggestions w.r.t. this patch:

 - I'd consider changing the code of relocate_to_current_adr() such
that AARCH64 specific codepaths are not taken on ARM32 (via IS_ENABLED
check or something similar)

 - I've always wanted to fix the original code to use Elf32_rel type
instead of magic hard-coded offsets, so depending on your
willingness/time-budget, maybe now would be a good time to do that as
well as use Elf64_rela for AARCH64?

Thanks,
Andrey Smirnov

> ---
>  arch/arm/cpu/common.c    | 38 ++++++++++++++++++++++++-------
>  arch/arm/cpu/setupc_64.S | 58 ++++++++++++++++++++++++++++++++++++++++++++++++
>  common/Kconfig           |  2 +-
>  3 files changed, 89 insertions(+), 9 deletions(-)
>
> diff --git a/arch/arm/cpu/common.c b/arch/arm/cpu/common.c
> index 3766116d97..c317e502d0 100644
> --- a/arch/arm/cpu/common.c
> +++ b/arch/arm/cpu/common.c
> @@ -24,39 +24,61 @@
>  #include <asm-generic/memory_layout.h>
>  #include <asm/sections.h>
>  #include <asm/cache.h>
> +#include <debug_ll.h>
> +
> +#define R_ARM_RELATIVE 23
> +#define R_AARCH64_RELATIVE 1027
>
>  /*
>   * relocate binary to the currently running address
>   */
>  void relocate_to_current_adr(void)
>  {
> -       unsigned long offset;
> +       unsigned long offset, offset_var;
>         unsigned long *dstart, *dend, *dynsym, *dynend;
>
>         /* Get offset between linked address and runtime address */
>         offset = get_runtime_offset();
> +       offset_var = global_variable_offset();
>
> -       dstart = (void *)__rel_dyn_start + offset;
> -       dend = (void *)__rel_dyn_end + offset;
> +       dstart = (void *)__rel_dyn_start + offset_var;
> +       dend = (void *)__rel_dyn_end + offset_var;
>
> -       dynsym = (void *)__dynsym_start + offset;
> -       dynend = (void *)__dynsym_end + offset;
> +       dynsym = (void *)__dynsym_start + offset_var;
> +       dynend = (void *)__dynsym_end + offset_var;
>
>         while (dstart < dend) {
>                 unsigned long *fixup = (unsigned long *)(*dstart + offset);
>                 unsigned long type = *(dstart + 1);
> +               int add;
> +
> +               if (ELF64_R_TYPE(type) == R_AARCH64_RELATIVE) {
> +                       unsigned long addend = *(dstart + 2);
>
> -               if ((type & 0xff) == 0x17) {
> +                       *fixup = addend + offset;
> +
> +                       add = 3;
> +               } else if (ELF32_R_TYPE(type) == R_ARM_RELATIVE) {
>                         *fixup = *fixup + offset;
> -               } else {
> +
> +                       add = 2;
> +               } else if (ELF32_R_TYPE(type) == R_ARM_ABS32) {
>                         int index = type >> 8;
>                         unsigned long r = dynsym[index * 4 + 1];
>
>                         *fixup = *fixup + r + offset;
> +
> +                       add = 2;
> +               } else {
> +                       putc_ll('>');
> +                       puthex_ll(type);
> +                       putc_ll('\n');
> +                       /* We're doomed */
> +                       panic(NULL);
>                 }
>
>                 *dstart += offset;
> -               dstart += 2;
> +               dstart += add;
>         }
>
>         memset(dynsym, 0, (unsigned long)dynend - (unsigned long)dynsym);
> diff --git a/arch/arm/cpu/setupc_64.S b/arch/arm/cpu/setupc_64.S
> index 3515854784..88c7899205 100644
> --- a/arch/arm/cpu/setupc_64.S
> +++ b/arch/arm/cpu/setupc_64.S
> @@ -16,3 +16,61 @@ ENTRY(setup_c)
>         mov     x30, x15
>         ret
>  ENDPROC(setup_c)
> +
> +/*
> + * void relocate_to_adr(unsigned long targetadr)
> + *
> + * Copy binary to targetadr, relocate code and continue
> + * executing at new address.
> + */
> +.section .text.relocate_to_adr
> +ENTRY(relocate_to_adr)
> +                                       /* x0: target address */
> +
> +       stp     x19, x20, [sp, #-16]!
> +
> +       mov     x19, lr
> +
> +       mov     x6, x0
> +
> +       bl      get_runtime_offset
> +       mov     x5, x0
> +
> +       ldr     x0, =_text
> +       mov     x8, x0
> +
> +       add     x1, x0, x5              /* x1: from address */
> +
> +       cmp     x1, x6                  /* already at correct address? */
> +       beq     1f                      /* yes, skip copy to new address */
> +
> +       ldr     x2, =__bss_start
> +
> +       sub     x2, x2, x0              /* x2: size */
> +       mov     x0, x6                  /* x0: target */
> +
> +       /* adjust return address */
> +       sub     x19, x19, x1            /* sub address where we are actually running */
> +       add     x19, x19, x0            /* add address where we are going to run */
> +
> +       bl      memcpy                  /* copy binary */
> +
> +#ifdef CONFIG_MMU
> +       bl      arm_early_mmu_cache_flush
> +#endif
> +       mov     x0,#0
> +       ic      ivau, x0        /* flush icache */
> +
> +       ldr     x0,=1f
> +       sub     x0, x0, x8
> +       add     x0, x0, x6
> +       br      x0                      /* jump to relocated address */
> +1:
> +       bl      relocate_to_current_adr /* relocate binary */
> +
> +       mov     lr, x19
> +
> +       ldp     x19, x20, [sp], #16
> +       ret
> +
> +ENDPROC(relocate_to_adr)
> diff --git a/common/Kconfig b/common/Kconfig
> index af71d6888a..b7000c4d73 100644
> --- a/common/Kconfig
> +++ b/common/Kconfig
> @@ -344,7 +344,7 @@ config KALLSYMS
>           This is useful to print a nice backtrace when an exception occurs.
>
>  config RELOCATABLE
> -       depends on PPC || (ARM && !CPU_V8)
> +       depends on PPC || ARM
>         bool "generate relocatable barebox binary"
>         help
>           A non relocatable barebox binary will run at it's compiled in
> --
> 2.16.1
>
>
> _______________________________________________
> barebox mailing list
> barebox at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/barebox


From akurz at blala.de  Sun Mar 18 14:10:46 2018
From: akurz at blala.de (Alexander Kurz)
Date: Sun, 18 Mar 2018 21:10:46 +0000
Subject: [PATCH] ARM: i.MX50: Amazon Kindle: fix setup of board specific
 environment
Message-ID: <20180318211046.14239-1-akurz@blala.de>

With patch 5b92cfceff38 ("startup: Load default environment earlier")
loading of the default environment moved from environment_initcall
four initcalls up to fs_initcall. At this time, most of the board specific
environment patches inserted via defaultenv_append_directory() have not
been processed yet (mostly done in device_initcall) and will not appear
in the environment.
Fix this problem for the mx50 kindles by moving defaultenv_append_directory()
one initcall in front of fs_initcall.
Similar patches may be necessary for all other board implementations and the
efi implementation using defaultenv_append_directory() in device_initcall.

Signed-off-by: Alexander Kurz <akurz at blala.de>
---
 arch/arm/boards/kindle-mx50/board.c | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boards/kindle-mx50/board.c b/arch/arm/boards/kindle-mx50/board.c
index 089dd8ebb..86cf54a46 100644
--- a/arch/arm/boards/kindle-mx50/board.c
+++ b/arch/arm/boards/kindle-mx50/board.c
@@ -127,6 +127,13 @@ static int is_mx50_kindle(void)
 		of_machine_is_compatible("amazon,kindle-ey21");
 }
 
+static int kindle_mx50_coredev_init(void)
+{
+	defaultenv_append_directory(defaultenv_kindle_mx50);
+	return 0;
+}
+coredevice_initcall(kindle_mx50_coredev_init);
+
 static int kindle_mx50_late_init(void)
 {
 	if (!is_mx50_kindle())
@@ -164,8 +171,6 @@ static int kindle_mx50_devices_init(void)
 	if (dev)
 		dev_set_param(dev, "probe", "1");
 
-	defaultenv_append_directory(defaultenv_kindle_mx50);
-
 	return 0;
 }
 device_initcall(kindle_mx50_devices_init);
-- 
2.11.0



From gael.portay at savoirfairelinux.com  Sun Mar 18 15:22:36 2018
From: gael.portay at savoirfairelinux.com (=?UTF-8?q?Ga=C3=ABl=20PORTAY?=)
Date: Sun, 18 Mar 2018 18:22:36 -0400
Subject: [PATCH] fs: check pointer returned by get_fsdevice_by_path before
 dereferencing
Message-ID: <20180318222236.28296-1-gael.portay@savoirfairelinux.com>

In __canonicalize_path() we dereference the pointer returned by
get_fsdevice_by_path() without checking if the pointer is NULL or not.
When the pointer is NULL it leads to an Ooops.

	Ooops, address error on load or ifetch!

	$ 0   : 00000000 00000001 a0000026 a0811c10
	$ 4   : a0402e60 a0402e48 a0811c00 a0402e58
	$ 8   : 00000001 00000000 0000005a 00000023
	$12   : 00000000 00000002 00601021 00000000
	$16   : a0402e60 a0402e50 a0402e39 a0810000
	$20   : a0402e38 a0811420 a0811424 00000000
	$24   : 00000000 a080de10
	$28   : 87f87d40 a03ffa68 a0810000 a080ce30
	Hi    : 00000002
	Lo    : 00000000
	epc   : a080ce34
	ra    : a080ce30
	Status: 00000006
	Cause : 40008010
	Config: 80040483

	### ERROR ### Please RESET the board ###

Fixes: d79a81736 fs: Don't bother filesystems without link support with additional stat() calls

Signed-off-by: Ga?l PORTAY <gael.portay at savoirfairelinux.com>
---
 fs/fs.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/fs/fs.c b/fs/fs.c
index 88f0b1478..5135112c8 100644
--- a/fs/fs.c
+++ b/fs/fs.c
@@ -191,7 +191,7 @@ static char *__canonicalize_path(const char *_pathname, int level)
 		 * with an additional stat() call.
 		 */
 		fsdev = get_fsdevice_by_path(outpath);
-		if (!fsdev->driver->readlink)
+		if (!fsdev || !fsdev->driver->readlink)
 			continue;
 
 		ret = __lstat(outpath, &s);
-- 
2.16.1



From s.hauer at pengutronix.de  Mon Mar 19 00:54:20 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Mon, 19 Mar 2018 08:54:20 +0100
Subject: [PATCH] ARM: AM335x: Fix invalid register access
Message-ID: <20180319075420.2919-1-s.hauer@pengutronix.de>

Several DDR3 phy registers are written with the pattern x<<30 | x<<20 | x<<10 | x.
The x<<30 doesn't fit into 32bit which causes a compiler warning.
Looking at the reference manual only the lower 10bit of the registers
have any meaning, so drop the other bogus values. This affects the
registers:

AM33XX_DATA0_RD_DQS_SLAVE_RATIO_0
AM33XX_DATA0_WR_DQS_SLAVE_RATIO_0
AM33XX_DATA0_WR_DQS_SLAVE_RATIO_1
AM33XX_DATA0_WRLVL_INIT_RATIO_0
AM33XX_DATA0_GATELVL_INIT_RATIO_0
AM33XX_DATA0_GATELVL_INIT_RATIO_1
AM33XX_DATA0_FIFO_WE_SLAVE_RATIO_0
AM33XX_DATA0_WR_DATA_SLAVE_RATIO_0

(AM33XX_DATA0_WR_DQS_SLAVE_RATIO_1 and AM33XX_DATA0_GATELVL_INIT_RATIO_1
do not even exist according to the reference manual, but that's another
story.)

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/boards/afi-gf/lowlevel.c     | 18 ++++++------------
 arch/arm/boards/beaglebone/lowlevel.c | 26 ++++++--------------------
 2 files changed, 12 insertions(+), 32 deletions(-)

diff --git a/arch/arm/boards/afi-gf/lowlevel.c b/arch/arm/boards/afi-gf/lowlevel.c
index 91b4b68c6d..dfa202dda3 100644
--- a/arch/arm/boards/afi-gf/lowlevel.c
+++ b/arch/arm/boards/afi-gf/lowlevel.c
@@ -64,33 +64,27 @@ static void board_data_macro_config(int dataMacroNum)
 	if (dataMacroNum == 1)
 		BaseAddrOffset = 0xA4;
 
-	__raw_writel(((DDR2_RD_DQS<<30)|(DDR2_RD_DQS<<20)
-		|(DDR2_RD_DQS<<10)|(DDR2_RD_DQS<<0)),
+	__raw_writel(DDR2_RD_DQS,
 		(AM33XX_DATA0_RD_DQS_SLAVE_RATIO_0 + BaseAddrOffset));
 	__raw_writel(DDR2_RD_DQS>>2,
 		(AM33XX_DATA0_RD_DQS_SLAVE_RATIO_1 + BaseAddrOffset));
-	__raw_writel(((DDR2_WR_DQS<<30)|(DDR2_WR_DQS<<20)
-		|(DDR2_WR_DQS<<10)|(DDR2_WR_DQS<<0)),
+	__raw_writel(DDR2_WR_DQS,
 		(AM33XX_DATA0_WR_DQS_SLAVE_RATIO_0 + BaseAddrOffset));
 	__raw_writel(DDR2_WR_DQS>>2,
 		(AM33XX_DATA0_WR_DQS_SLAVE_RATIO_1 + BaseAddrOffset));
-	__raw_writel(((DDR2_PHY_WRLVL<<30)|(DDR2_PHY_WRLVL<<20)
-		|(DDR2_PHY_WRLVL<<10)|(DDR2_PHY_WRLVL<<0)),
+	__raw_writel(DDR2_PHY_WRLVL,
 		(AM33XX_DATA0_WRLVL_INIT_RATIO_0 + BaseAddrOffset));
 	__raw_writel(DDR2_PHY_WRLVL>>2,
 		(AM33XX_DATA0_WRLVL_INIT_RATIO_1 + BaseAddrOffset));
-	__raw_writel(((DDR2_PHY_GATELVL<<30)|(DDR2_PHY_GATELVL<<20)
-		|(DDR2_PHY_GATELVL<<10)|(DDR2_PHY_GATELVL<<0)),
+	__raw_writel(DDR2_PHY_GATELVL,
 		(AM33XX_DATA0_GATELVL_INIT_RATIO_0 + BaseAddrOffset));
 	__raw_writel(DDR2_PHY_GATELVL>>2,
 		(AM33XX_DATA0_GATELVL_INIT_RATIO_1 + BaseAddrOffset));
-	__raw_writel(((DDR2_PHY_FIFO_WE<<30)|(DDR2_PHY_FIFO_WE<<20)
-		|(DDR2_PHY_FIFO_WE<<10)|(DDR2_PHY_FIFO_WE<<0)),
+	__raw_writel(DDR2_PHY_FIFO_WE,
 		(AM33XX_DATA0_FIFO_WE_SLAVE_RATIO_0 + BaseAddrOffset));
 	__raw_writel(DDR2_PHY_FIFO_WE>>2,
 		(AM33XX_DATA0_FIFO_WE_SLAVE_RATIO_1 + BaseAddrOffset));
-	__raw_writel(((DDR2_PHY_WR_DATA<<30)|(DDR2_PHY_WR_DATA<<20)
-		|(DDR2_PHY_WR_DATA<<10)|(DDR2_PHY_WR_DATA<<0)),
+	__raw_writel(DDR2_PHY_WR_DATA,
 		(AM33XX_DATA0_WR_DATA_SLAVE_RATIO_0 + BaseAddrOffset));
 	__raw_writel(DDR2_PHY_WR_DATA>>2,
 		(AM33XX_DATA0_WR_DATA_SLAVE_RATIO_1 + BaseAddrOffset));
diff --git a/arch/arm/boards/beaglebone/lowlevel.c b/arch/arm/boards/beaglebone/lowlevel.c
index a56b4b6240..f2e1690b15 100644
--- a/arch/arm/boards/beaglebone/lowlevel.c
+++ b/arch/arm/boards/beaglebone/lowlevel.c
@@ -48,26 +48,12 @@ static const struct am33xx_emif_regs ddr2_regs = {
 };
 
 static const struct am33xx_ddr_data ddr2_data = {
-	.rd_slave_ratio0        = (DDR2_RD_DQS << 30) | (DDR2_RD_DQS << 20) |
-				(DDR2_RD_DQS << 10) | (DDR2_RD_DQS << 0),
-	.wr_dqs_slave_ratio0    = (DDR2_WR_DQS << 30) | (DDR2_WR_DQS << 20) |
-				(DDR2_WR_DQS << 10) | (DDR2_WR_DQS << 0),
-	.wrlvl_init_ratio0	= (DDR2_PHY_WRLVL << 30) |
-				(DDR2_PHY_WRLVL << 20) |
-				(DDR2_PHY_WRLVL << 10) |
-				(DDR2_PHY_WRLVL << 0),
-	.gatelvl_init_ratio0	= (DDR2_PHY_GATELVL << 30) |
-				(DDR2_PHY_GATELVL << 20) |
-				(DDR2_PHY_GATELVL << 10) |
-				(DDR2_PHY_GATELVL << 0),
-	.fifo_we_slave_ratio0	= (DDR2_PHY_FIFO_WE << 30) |
-				(DDR2_PHY_FIFO_WE << 20) |
-				(DDR2_PHY_FIFO_WE << 10) |
-				(DDR2_PHY_FIFO_WE << 0),
-	.wr_slave_ratio0        = (DDR2_PHY_WR_DATA << 30) |
-				(DDR2_PHY_WR_DATA << 20) |
-				(DDR2_PHY_WR_DATA << 10) |
-				(DDR2_PHY_WR_DATA << 0),
+	.rd_slave_ratio0        = DDR2_RD_DQS,
+	.wr_dqs_slave_ratio0    = DDR2_WR_DQS,
+	.wrlvl_init_ratio0	= DDR2_PHY_WRLVL,
+	.gatelvl_init_ratio0	= DDR2_PHY_GATELVL,
+	.fifo_we_slave_ratio0	= DDR2_PHY_FIFO_WE,
+	.wr_slave_ratio0        = DDR2_PHY_WR_DATA,
 	.use_rank0_delay	= 0x01,
 	.dll_lock_diff0		= 0x0,
 };
-- 
2.16.1



From s.hauer at pengutronix.de  Mon Mar 19 01:01:37 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Mon, 19 Mar 2018 09:01:37 +0100
Subject: [PATCH v2 6/6] watchdog: add watchdog poller
In-Reply-To: <20180313083328.25705-6-o.rempel@pengutronix.de>
References: <20180313083328.25705-1-o.rempel@pengutronix.de>
 <20180313083328.25705-6-o.rempel@pengutronix.de>
Message-ID: <20180319080137.wqucsld7iumv6ivo@pengutronix.de>

On Tue, Mar 13, 2018 at 09:33:28AM +0100, Oleksij Rempel wrote:
> In some cases it is practical to supervise as much as possible of
> the barebox execution with a watchdog (or multiple watchdogs). This
> patch provides an async poller for watchdog core framework which can
> be enabled by the user and stores this configuration to nv.
> 
> +static int watchdog_register_poller(struct watchdog *wd)
> +{
> +	struct param_d *p;
> +	int ret;
> +
> +	ret = poller_async_register(&wd->poller);
> +	if (ret)
> +		return ret;
> +
> +	p = dev_add_param_bool(&wd->dev, "poller_enable", watchdog_set_poller,
> +			NULL, &wd->poller_enable, wd);

The series looks mostly good and I applied 1-5. However, as Jan
mentioned we should find a better name for the variable. "poller_enable"
describes how it's internally implemented, not what this variable is
good for.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From s.hauer at pengutronix.de  Mon Mar 19 01:05:51 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Mon, 19 Mar 2018 09:05:51 +0100
Subject: [PATCH] of: demote "no ranges" message to debug level
In-Reply-To: <20180316145658.14996-1-l.stach@pengutronix.de>
References: <20180316145658.14996-1-l.stach@pengutronix.de>
Message-ID: <20180319080551.ar7bwo67di7zajg5@pengutronix.de>

On Fri, Mar 16, 2018 at 03:56:58PM +0100, Lucas Stach wrote:
> There are valid cases where there is no way to translate a OF node to
> a MMIO address via ranges, so do the same as the Linux kernel and don't
> print an error message in that case, but make it available as a debug
> message.
> 
> Signed-off-by: Lucas Stach <l.stach at pengutronix.de>
> ---
>  drivers/of/address.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)

Applied, thanks

Sascha

> 
> diff --git a/drivers/of/address.c b/drivers/of/address.c
> index 8018d78bcbd8..14db08041725 100644
> --- a/drivers/of/address.c
> +++ b/drivers/of/address.c
> @@ -314,7 +314,7 @@ static int of_translate_one(struct device_node *parent, struct of_bus *bus,
>  	ranges = of_get_property(parent, rprop, &rlen);
>  #if !defined(CONFIG_PPC)
>  	if (ranges == NULL) {
> -		pr_err("OF: no ranges; cannot translate\n");
> +		pr_debug("OF: no ranges; cannot translate\n");
>  		return 1;
>  	}
>  #endif /* !defined(CONFIG_PPC) */
> -- 
> 2.16.1
> 
> 
> _______________________________________________
> barebox mailing list
> barebox at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/barebox
> 

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From s.hauer at pengutronix.de  Mon Mar 19 01:29:03 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Mon, 19 Mar 2018 09:29:03 +0100
Subject: [PATCH] Revert "startup: Load default environment earlier"
Message-ID: <20180319082903.30756-1-s.hauer@pengutronix.de>

Several boards use defaultenv_append_directory() to append a board
specific envfs snippet during runtime. This only works when
defaultenv_append_directory() is called before defaultenv_load() is
exectuted. Since that was executed at the end of the start process
every initcall level could be used to append a env directory. With this
patch only initcall levels earlier than fsdevice_initcall work and
most boards do not cope with this.

Revert this patch until a better solution is found.

Reported-by: Alexander Kurz <akurz at blala.de>

This reverts commit 5b92cfceff38f3a6462a21cf6b69159ad0ae9744.
---
 common/startup.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/common/startup.c b/common/startup.c
index 8940674528..8553849cb3 100644
--- a/common/startup.c
+++ b/common/startup.c
@@ -67,9 +67,6 @@ static int mount_root(void)
 		mount("none", "pstore", "/pstore", NULL);
 	}
 
-	if (IS_ENABLED(CONFIG_DEFAULT_ENVIRONMENT))
-		defaultenv_load("/env", 0);
-
 	return 0;
 }
 fs_initcall(mount_root);
@@ -82,6 +79,9 @@ static int load_environment(void)
 
 	default_environment_path = default_environment_path_get();
 
+	if (IS_ENABLED(CONFIG_DEFAULT_ENVIRONMENT))
+		defaultenv_load("/env", 0);
+
 	envfs_load(default_environment_path, "/env", 0);
 	nvvar_load();
 
-- 
2.16.1



From s.hauer at pengutronix.de  Mon Mar 19 01:28:57 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Mon, 19 Mar 2018 09:28:57 +0100
Subject: [PATCH] ARM: i.MX50: Amazon Kindle: fix setup of board specific
 environment
In-Reply-To: <20180318211046.14239-1-akurz@blala.de>
References: <20180318211046.14239-1-akurz@blala.de>
Message-ID: <20180319082857.2kxpkffblycc2tl4@pengutronix.de>

Hi Alexander,

On Sun, Mar 18, 2018 at 09:10:46PM +0000, Alexander Kurz wrote:
> With patch 5b92cfceff38 ("startup: Load default environment earlier")
> loading of the default environment moved from environment_initcall
> four initcalls up to fs_initcall. At this time, most of the board specific
> environment patches inserted via defaultenv_append_directory() have not
> been processed yet (mostly done in device_initcall) and will not appear
> in the environment.
> Fix this problem for the mx50 kindles by moving defaultenv_append_directory()
> one initcall in front of fs_initcall.
> Similar patches may be necessary for all other board implementations and the
> efi implementation using defaultenv_append_directory() in device_initcall.

You are right. Most boards do not cope with this change. Let's just
revert the original patch instead of reworking all boards.

It should be also possible to call defaultenv_load_one() instead of
putting it to the defaultenv_list list when we have already loaded the
environment, but for now I prefer the easy way out without possible
regressions.

Sascha


-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From s.hauer at pengutronix.de  Mon Mar 19 01:36:29 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Mon, 19 Mar 2018 09:36:29 +0100
Subject: [PATCH] fs: check pointer returned by get_fsdevice_by_path
 before dereferencing
In-Reply-To: <20180318222236.28296-1-gael.portay@savoirfairelinux.com>
References: <20180318222236.28296-1-gael.portay@savoirfairelinux.com>
Message-ID: <20180319083629.kxjdc4jnd35prif2@pengutronix.de>

Hi Ga?l,

On Sun, Mar 18, 2018 at 06:22:36PM -0400, Ga?l PORTAY wrote:
> In __canonicalize_path() we dereference the pointer returned by
> get_fsdevice_by_path() without checking if the pointer is NULL or not.
> When the pointer is NULL it leads to an Ooops.
> 
> 	Ooops, address error on load or ifetch!
> 
> 	$ 0   : 00000000 00000001 a0000026 a0811c10
> 	$ 4   : a0402e60 a0402e48 a0811c00 a0402e58
> 	$ 8   : 00000001 00000000 0000005a 00000023
> 	$12   : 00000000 00000002 00601021 00000000
> 	$16   : a0402e60 a0402e50 a0402e39 a0810000
> 	$20   : a0402e38 a0811420 a0811424 00000000
> 	$24   : 00000000 a080de10
> 	$28   : 87f87d40 a03ffa68 a0810000 a080ce30
> 	Hi    : 00000002
> 	Lo    : 00000000
> 	epc   : a080ce34
> 	ra    : a080ce30
> 	Status: 00000006
> 	Cause : 40008010
> 	Config: 80040483
> 
> 	### ERROR ### Please RESET the board ###
> 
> Fixes: d79a81736 fs: Don't bother filesystems without link support with additional stat() calls
> 
> Signed-off-by: Ga?l PORTAY <gael.portay at savoirfairelinux.com>
> ---
>  fs/fs.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)

Applied, thanks.

I wonder though what calls into the filesystem layer before / is
mounted in your case.

Sascha


-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From s.hauer at pengutronix.de  Mon Mar 19 01:50:19 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Mon, 19 Mar 2018 09:50:19 +0100
Subject: [PATCH 30/78] ARM: aarch64: Add relocation support
In-Reply-To: <CAHQ1cqGbkHN+Csi7-Bb=_iTea4zXK3-mmK8EK0x-UW9niHNCQg@mail.gmail.com>
References: <20180316125354.23462-1-s.hauer@pengutronix.de>
 <20180316125354.23462-31-s.hauer@pengutronix.de>
 <CAHQ1cqGbkHN+Csi7-Bb=_iTea4zXK3-mmK8EK0x-UW9niHNCQg@mail.gmail.com>
Message-ID: <20180319085019.qbcgurw2aspsmxcr@pengutronix.de>

Hi Andrey,

On Fri, Mar 16, 2018 at 02:51:19PM -0700, Andrey Smirnov wrote:
> On Fri, Mar 16, 2018 at 5:53 AM, Sascha Hauer <s.hauer at pengutronix.de> wrote:
> > This adds aarch64 support for relocating binaries linked with -pie.
> >
> > Support is integrated into the already exisiting
> > relocate_to_current_adr() function which is now used for both arm32
> > and aarch64.
> >
> > Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
> 
> 
> Sascha:
> 
> Two small suggestions w.r.t. this patch:
> 
>  - I'd consider changing the code of relocate_to_current_adr() such
> that AARCH64 specific codepaths are not taken on ARM32 (via IS_ENABLED
> check or something similar)

Why? Do you want to make the code more clear or do you fear that we
apply fixups for a foreign architecture?

> 
>  - I've always wanted to fix the original code to use Elf32_rel type
> instead of magic hard-coded offsets, so depending on your
> willingness/time-budget, maybe now would be a good time to do that as
> well as use Elf64_rela for AARCH64?

You mean using 

> struct elf32_rel {
>	Elf32_Addr    r_offset;
>	Elf32_Word    r_info;
> } Elf32_Rel;

and:

> struct elf64_rela {
> 	Elf64_Addr r_offset;  /* Location at which to apply the action */
> 	Elf64_Xword r_info;   /* index and type of relocation */
>	Elf64_Sxword r_addend;        /* Constant addend used to compute value */
> } Elf64_Rela;

?

Yes, I can change that. I wonder though which type is behind R_ARM_ABS32

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
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From gael.portay at savoirfairelinux.com  Mon Mar 19 02:06:17 2018
From: gael.portay at savoirfairelinux.com (=?iso-8859-1?Q?Ga=EBl?= PORTAY)
Date: Mon, 19 Mar 2018 05:06:17 -0400
Subject: [PATCH] fs: check pointer returned by get_fsdevice_by_path
 before dereferencing
In-Reply-To: <20180319083629.kxjdc4jnd35prif2@pengutronix.de>
References: <20180318222236.28296-1-gael.portay@savoirfairelinux.com>
 <20180319083629.kxjdc4jnd35prif2@pengutronix.de>
Message-ID: <20180319090616.vmmb2dky3syrmuwm@archlinux.local>

Hi Sascha,

On Mon, Mar 19, 2018 at 09:36:29AM +0100, Sascha Hauer wrote:
> ...
> I wonder though what calls into the filesystem layer before / is
> mounted in your case.
>

The issue is trigger by function stat() in start_barebox(), right before
I expect to have a shell.

Here.

	if (IS_ENABLED(CONFIG_COMMAND_SUPPORT)) {
		pr_info("running /env/bin/init...\n");

		if (!stat("/env/bin/init", &s))
			run_command("source /env/bin/init");
		else
			pr_err("/env/bin/init not found\n");
	}

My configuration is very minimal for now. I do not have (yet) any FS
selected (excepted devfs) and I do not have any root device mounted
either in this configuration.

I guess this is why fs_dev_root is NULL and why get_fsdevice_by_path()
returns fs_dev_root (because there is nothing to iterate in list
fs_device_list).

Gael


From s.hauer at pengutronix.de  Mon Mar 19 02:11:46 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Mon, 19 Mar 2018 10:11:46 +0100
Subject: [PATCH 14/14] ARM: i.MX: ocotp: Add i.MX8MQ support
In-Reply-To: <20180319091146.4112-1-s.hauer@pengutronix.de>
References: <20180319091146.4112-1-s.hauer@pengutronix.de>
Message-ID: <20180319091146.4112-15-s.hauer@pengutronix.de>

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/mach-imx/Kconfig |  2 +-
 arch/arm/mach-imx/ocotp.c | 10 ++++++++++
 2 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 5b430b19d6..b49bef3f27 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -744,7 +744,7 @@ config IMX_IIM_FUSE_BLOW
 
 config IMX_OCOTP
 	tristate "i.MX6 On Chip OTP controller"
-	depends on ARCH_IMX6 || ARCH_VF610
+	depends on ARCH_IMX6 || ARCH_VF610 || ARCH_IMX8MQ
 	depends on OFDEVICE
 	help
 	  This adds support for the i.MX6 On-Chip OTP controller. Currently the
diff --git a/arch/arm/mach-imx/ocotp.c b/arch/arm/mach-imx/ocotp.c
index 99b365aad8..09f8cf4ff6 100644
--- a/arch/arm/mach-imx/ocotp.c
+++ b/arch/arm/mach-imx/ocotp.c
@@ -584,6 +584,13 @@ static struct imx_ocotp_data vf610_ocotp_data = {
 	.mac_offsets = { MAC_OFFSET_0, MAC_OFFSET_1 },
 };
 
+static struct imx_ocotp_data imx8mq_ocotp_data = {
+	.num_regs = 2048,
+	.addr_to_offset = imx6sl_addr_to_offset,
+	.mac_offsets_num = 1,
+	.mac_offsets = { 0x90 },
+};
+
 static __maybe_unused struct of_device_id imx_ocotp_dt_ids[] = {
 	{
 		.compatible = "fsl,imx6q-ocotp",
@@ -597,6 +604,9 @@ static __maybe_unused struct of_device_id imx_ocotp_dt_ids[] = {
 	}, {
 		.compatible = "fsl,imx6ul-ocotp",
 		.data = &imx6q_ocotp_data,
+	}, {
+		.compatible = "fsl,imx8mq-ocotp",
+		.data = &imx8mq_ocotp_data,
 	}, {
 		.compatible = "fsl,vf610-ocotp",
 		.data = &vf610_ocotp_data,
-- 
2.16.1



From s.hauer at pengutronix.de  Mon Mar 19 02:11:33 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Mon, 19 Mar 2018 10:11:33 +0100
Subject: [PATCH 01/14] ARM: i.MX: xload: Fix compiler warning
In-Reply-To: <20180319091146.4112-1-s.hauer@pengutronix.de>
References: <20180319091146.4112-1-s.hauer@pengutronix.de>
Message-ID: <20180319091146.4112-2-s.hauer@pengutronix.de>

the ESDHC controller is a 32bit device, so can do DMA only on the
lower 32bit. Fix the compiler warning about casting a pointer to integer
of different size on aarch64 by casting to unsigned long first. Error
out if the destination does not fit into 32bit though.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/mach-imx/xload-esdhc.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-imx/xload-esdhc.c b/arch/arm/mach-imx/xload-esdhc.c
index e774e4e68c..bd58bdc644 100644
--- a/arch/arm/mach-imx/xload-esdhc.c
+++ b/arch/arm/mach-imx/xload-esdhc.c
@@ -109,8 +109,13 @@ esdhc_send_cmd(struct esdhc *esdhc, struct mci_cmd *cmd, struct mci_data *data)
 	__udelay(1);
 
 	if (data) {
+		unsigned long dest = (unsigned long)data->dest;
+
+		if (dest > 0xffffffff)
+			return -EINVAL;
+
 		/* Set up for a data transfer if we have one */
-		esdhc_write32(regs + SDHCI_DMA_ADDRESS, (u32)data->dest);
+		esdhc_write32(regs + SDHCI_DMA_ADDRESS, (u32)dest);
 		esdhc_write32(regs + SDHCI_BLOCK_SIZE__BLOCK_COUNT, data->blocks << 16 | SECTOR_SIZE);
 	}
 
-- 
2.16.1



From s.hauer at pengutronix.de  Mon Mar 19 02:11:32 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Mon, 19 Mar 2018 10:11:32 +0100
Subject: [PATCH 00/14] ARM: i.MX8MQ and EVK support
Message-ID: <20180319091146.4112-1-s.hauer@pengutronix.de>

This series adds support for the i.MX8MQ SoC and the EVK board from NXP.
Currently only 2nd stage after U-Boot is supported, 1st stage support
will still need some time. Besides of the missing first stage support
the EVK support should be fairly complete already, as the i.MX8MQ is
very similar to the i.MX6 and only the core has been changed.

This series is likely not the final one as the clock driver and the
device tree are derived from mailing list patches and not from the
final versions (which do not exist yet).

Sascha

Sascha Hauer (14):
  ARM: i.MX: xload: Fix compiler warning
  ARM: i.MX: compile arm32 specific errata only for CPU32
  ARM: Add i.MX8 support
  aarch64: Add i.MX8 debug UART support
  Include our own include/dt-bindings
  ARM: i.MX8: Add i.MX8mq EVK support
  mci: imx-esdhc: use dma mapping functions
  net: fec_imx: remove unnecessary DMA sync ops
  net: fec_imx: Use dma mapping functions
  clock: Add i.MX8MQ clock driver
  serial: i.MX: Add i.MX8 support
  mmc: i.MX esdhc: Add i.MX8 support
  gpio: i.MX: Add i.MX8mq support
  ARM: i.MX: ocotp: Add i.MX8MQ support

 arch/arm/boards/Makefile                       |   1 +
 arch/arm/boards/nxp-imx8mq-evk/Makefile        |   2 +
 arch/arm/boards/nxp-imx8mq-evk/board.c         |  44 ++
 arch/arm/boards/nxp-imx8mq-evk/lowlevel.c      |  43 ++
 arch/arm/dts/Makefile                          |   1 +
 arch/arm/dts/imx8mq-evk.dts                    | 446 ++++++++++++++++++
 arch/arm/dts/imx8mq-pinfunc.h                  | 623 ++++++++++++++++++++++++
 arch/arm/dts/imx8mq.dtsi                       | 624 ++++++++++++++++++++++++
 arch/arm/mach-imx/Kconfig                      |  15 +-
 arch/arm/mach-imx/Makefile                     |   1 +
 arch/arm/mach-imx/cpu_init.c                   |   2 +
 arch/arm/mach-imx/imx.c                        |   4 +
 arch/arm/mach-imx/imx8mq.c                     |  66 +++
 arch/arm/mach-imx/include/mach/debug_ll.h      |   3 +
 arch/arm/mach-imx/include/mach/generic.h       |  13 +
 arch/arm/mach-imx/include/mach/imx8mq-regs.h   | 121 +++++
 arch/arm/mach-imx/include/mach/imx_cpu_types.h |   1 +
 arch/arm/mach-imx/ocotp.c                      |  10 +
 arch/arm/mach-imx/xload-esdhc.c                |   7 +-
 arch/mips/dts/include/dt-bindings              |   1 -
 common/Kconfig                                 |   8 +
 drivers/clk/imx/Makefile                       |   3 +
 drivers/clk/imx/clk-frac-pll.c                 | 226 +++++++++
 drivers/clk/imx/clk-imx8mq.c                   | 580 +++++++++++++++++++++++
 drivers/clk/imx/clk-sccg-pll.c                 | 242 ++++++++++
 drivers/clk/imx/clk.h                          |  27 ++
 drivers/gpio/gpio-imx.c                        |   3 +
 drivers/mci/imx-esdhc.c                        |  54 +--
 drivers/net/fec_imx.c                          |  19 +-
 drivers/net/fec_imx.h                          |   1 +
 drivers/serial/serial_imx.c                    |   5 +-
 images/Makefile.imx                            |   6 +
 include/dt-bindings/clock/imx8mq-clock.h       | 629 +++++++++++++++++++++++++
 include/serial/imx-uart.h                      |   5 +
 scripts/Makefile.lib                           |   1 +
 35 files changed, 3796 insertions(+), 41 deletions(-)
 create mode 100644 arch/arm/boards/nxp-imx8mq-evk/Makefile
 create mode 100644 arch/arm/boards/nxp-imx8mq-evk/board.c
 create mode 100644 arch/arm/boards/nxp-imx8mq-evk/lowlevel.c
 create mode 100644 arch/arm/dts/imx8mq-evk.dts
 create mode 100644 arch/arm/dts/imx8mq-pinfunc.h
 create mode 100644 arch/arm/dts/imx8mq.dtsi
 create mode 100644 arch/arm/mach-imx/imx8mq.c
 create mode 100644 arch/arm/mach-imx/include/mach/imx8mq-regs.h
 delete mode 120000 arch/mips/dts/include/dt-bindings
 create mode 100644 drivers/clk/imx/clk-frac-pll.c
 create mode 100644 drivers/clk/imx/clk-imx8mq.c
 create mode 100644 drivers/clk/imx/clk-sccg-pll.c
 create mode 100644 include/dt-bindings/clock/imx8mq-clock.h

-- 
2.16.1



From s.hauer at pengutronix.de  Mon Mar 19 02:11:36 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Mon, 19 Mar 2018 10:11:36 +0100
Subject: [PATCH 04/14] aarch64: Add i.MX8 debug UART support
In-Reply-To: <20180319091146.4112-1-s.hauer@pengutronix.de>
References: <20180319091146.4112-1-s.hauer@pengutronix.de>
Message-ID: <20180319091146.4112-5-s.hauer@pengutronix.de>

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/mach-imx/include/mach/debug_ll.h | 3 +++
 common/Kconfig                            | 8 ++++++++
 2 files changed, 11 insertions(+)

diff --git a/arch/arm/mach-imx/include/mach/debug_ll.h b/arch/arm/mach-imx/include/mach/debug_ll.h
index d54d601db0..7212443ba4 100644
--- a/arch/arm/mach-imx/include/mach/debug_ll.h
+++ b/arch/arm/mach-imx/include/mach/debug_ll.h
@@ -15,6 +15,7 @@
 #include <mach/imx53-regs.h>
 #include <mach/imx6-regs.h>
 #include <mach/imx7-regs.h>
+#include <mach/imx8mq-regs.h>
 #include <mach/vf610-regs.h>
 
 #include <serial/imx-uart.h>
@@ -47,6 +48,8 @@
 #define IMX_DEBUG_SOC MX6
 #elif defined CONFIG_DEBUG_IMX7D_UART
 #define IMX_DEBUG_SOC MX7
+#elif defined CONFIG_DEBUG_IMX8MQ_UART
+#define IMX_DEBUG_SOC MX8MQ
 #elif defined CONFIG_DEBUG_VF610_UART
 #define IMX_DEBUG_SOC VF610
 #else
diff --git a/common/Kconfig b/common/Kconfig
index b7000c4d73..75aea460a3 100644
--- a/common/Kconfig
+++ b/common/Kconfig
@@ -1099,6 +1099,13 @@ config DEBUG_IMX7D_UART
 	  Say Y here if you want barebox low-level debugging support
 	  on i.MX7D.
 
+config DEBUG_IMX8MQ_UART
+	bool "i.MX8MQ Debug UART"
+	depends on ARCH_IMX8MQ
+	help
+	  Say Y here if you want barebox low-level debugging support
+	  on i.MX8MQ.
+
 config DEBUG_VF610_UART
 	bool "VF610 Debug UART"
 	depends on ARCH_VF610
@@ -1163,6 +1170,7 @@ config DEBUG_IMX_UART_PORT
 						DEBUG_IMX6Q_UART || \
 						DEBUG_IMX6SL_UART || \
 						DEBUG_IMX7D_UART || \
+						DEBUG_IMX8MQ_UART || \
 						DEBUG_VF610_UART
 	default 1
 	depends on ARCH_IMX
-- 
2.16.1



From s.hauer at pengutronix.de  Mon Mar 19 02:11:37 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Mon, 19 Mar 2018 10:11:37 +0100
Subject: [PATCH 05/14] Include our own include/dt-bindings
In-Reply-To: <20180319091146.4112-1-s.hauer@pengutronix.de>
References: <20180319091146.4112-1-s.hauer@pengutronix.de>
Message-ID: <20180319091146.4112-6-s.hauer@pengutronix.de>

Allow to use dt-bindings files that are not yet upstreamed. They can
be put into include/dt-bindings.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/mips/dts/include/dt-bindings | 1 -
 scripts/Makefile.lib              | 1 +
 2 files changed, 1 insertion(+), 1 deletion(-)
 delete mode 120000 arch/mips/dts/include/dt-bindings

diff --git a/arch/mips/dts/include/dt-bindings b/arch/mips/dts/include/dt-bindings
deleted file mode 120000
index 0cecb3d080..0000000000
--- a/arch/mips/dts/include/dt-bindings
+++ /dev/null
@@ -1 +0,0 @@
-../../../../include/dt-bindings
\ No newline at end of file
diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib
index 272b5981e9..3024b068ee 100644
--- a/scripts/Makefile.lib
+++ b/scripts/Makefile.lib
@@ -154,6 +154,7 @@ ld_flags       = $(LDFLAGS) $(EXTRA_LDFLAGS)
 dtc_cpp_flags  = -Wp,-MD,$(depfile).pre -nostdinc                        \
 		 -I$(srctree)/arch/$(SRCARCH)/dts/include		 \
 		 -I$(srctree)/dts/include                                \
+		 -I$(srctree)/include                                    \
 		 -I$(srctree)/dts/src/                                   \
 		 -undef -D__DTS__
 
-- 
2.16.1



From s.hauer at pengutronix.de  Mon Mar 19 02:11:44 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Mon, 19 Mar 2018 10:11:44 +0100
Subject: [PATCH 12/14] mmc: i.MX esdhc: Add i.MX8 support
In-Reply-To: <20180319091146.4112-1-s.hauer@pengutronix.de>
References: <20180319091146.4112-1-s.hauer@pengutronix.de>
Message-ID: <20180319091146.4112-13-s.hauer@pengutronix.de>

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 drivers/mci/imx-esdhc.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/mci/imx-esdhc.c b/drivers/mci/imx-esdhc.c
index 8929901d4b..c4daa9d121 100644
--- a/drivers/mci/imx-esdhc.c
+++ b/drivers/mci/imx-esdhc.c
@@ -728,6 +728,7 @@ static __maybe_unused struct of_device_id fsl_esdhc_compatible[] = {
 	{ .compatible = "fsl,imx6q-usdhc",  .data = &usdhc_imx6q_data  },
 	{ .compatible = "fsl,imx6sl-usdhc", .data = &usdhc_imx6sl_data },
 	{ .compatible = "fsl,imx6sx-usdhc", .data = &usdhc_imx6sx_data },
+	{ .compatible = "fsl,imx8mq-usdhc", .data = &usdhc_imx6sx_data },
 	{ /* sentinel */ }
 };
 
-- 
2.16.1



From s.hauer at pengutronix.de  Mon Mar 19 02:11:39 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Mon, 19 Mar 2018 10:11:39 +0100
Subject: [PATCH 07/14] mci: imx-esdhc: use dma mapping functions
In-Reply-To: <20180319091146.4112-1-s.hauer@pengutronix.de>
References: <20180319091146.4112-1-s.hauer@pengutronix.de>
Message-ID: <20180319091146.4112-8-s.hauer@pengutronix.de>

Rather than relying on the fact that addresses can be just casted
into DMA addresses use proper DMA mapping functions.

This fixes compiler warnings when we do DMA on this 32bit only device
on aarch64 SoCs.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 drivers/mci/imx-esdhc.c | 53 ++++++++++++++++++++++++-------------------------
 1 file changed, 26 insertions(+), 27 deletions(-)

diff --git a/drivers/mci/imx-esdhc.c b/drivers/mci/imx-esdhc.c
index b91f94b99c..8929901d4b 100644
--- a/drivers/mci/imx-esdhc.c
+++ b/drivers/mci/imx-esdhc.c
@@ -211,18 +211,14 @@ esdhc_pio_read_write(struct mci_host *mci, struct mci_data *data)
 	return 0;
 }
 
-static int esdhc_setup_data(struct mci_host *mci, struct mci_data *data)
+static int esdhc_setup_data(struct mci_host *mci, struct mci_data *data,
+			    dma_addr_t dma)
 {
 	struct fsl_esdhc_host *host = to_fsl_esdhc(mci);
 	void __iomem *regs = host->regs;
 	u32 wml_value;
 
-	if (IS_ENABLED(CONFIG_MCI_IMX_ESDHC_PIO)) {
-		if (!(data->flags & MMC_DATA_READ))
-			esdhc_write32(regs + SDHCI_DMA_ADDRESS, (u32)data->src);
-		else
-			esdhc_write32(regs + SDHCI_DMA_ADDRESS, (u32)data->dest);
-	} else {
+	if (!IS_ENABLED(CONFIG_MCI_IMX_ESDHC_PIO)) {
 		wml_value = data->blocksize/4;
 
 		if (data->flags & MMC_DATA_READ) {
@@ -230,15 +226,14 @@ static int esdhc_setup_data(struct mci_host *mci, struct mci_data *data)
 				wml_value = 0x10;
 
 			esdhc_clrsetbits32(regs + IMX_SDHCI_WML, WML_RD_WML_MASK, wml_value);
-			esdhc_write32(regs + SDHCI_DMA_ADDRESS, (u32)data->dest);
 		} else {
 			if (wml_value > 0x80)
 				wml_value = 0x80;
 
 			esdhc_clrsetbits32(regs + IMX_SDHCI_WML, WML_WR_WML_MASK,
 						wml_value << 16);
-			esdhc_write32(regs + SDHCI_DMA_ADDRESS, (u32)data->src);
 		}
+		esdhc_write32(regs + SDHCI_DMA_ADDRESS, dma);
 	}
 
 	esdhc_write32(regs + SDHCI_BLOCK_SIZE__BLOCK_COUNT, data->blocks << 16 | data->blocksize);
@@ -250,7 +245,6 @@ static int esdhc_do_data(struct mci_host *mci, struct mci_data *data)
 {
 	struct fsl_esdhc_host *host = to_fsl_esdhc(mci);
 	void __iomem *regs = host->regs;
-	unsigned int num_bytes = data->blocks * data->blocksize;
 	u32 irqstat;
 
 	if (IS_ENABLED(CONFIG_MCI_IMX_ESDHC_PIO))
@@ -267,13 +261,6 @@ static int esdhc_do_data(struct mci_host *mci, struct mci_data *data)
 	} while (!(irqstat & IRQSTAT_TC) &&
 		(esdhc_read32(regs + SDHCI_PRESENT_STATE) & PRSSTAT_DLA));
 
-	if (data->flags & MMC_DATA_WRITE)
-		dma_sync_single_for_cpu((unsigned long)data->src,
-					num_bytes, DMA_TO_DEVICE);
-	else
-		dma_sync_single_for_cpu((unsigned long)data->dest,
-					num_bytes, DMA_FROM_DEVICE);
-
 	return 0;
 }
 
@@ -290,6 +277,9 @@ esdhc_send_cmd(struct mci_host *mci, struct mci_cmd *cmd, struct mci_data *data)
 	void __iomem *regs = host->regs;
 	unsigned int num_bytes = 0;
 	int ret;
+	void *ptr;
+	enum dma_data_direction dir = 0;
+	dma_addr_t dma = 0;
 
 	esdhc_write32(regs + SDHCI_INT_STATUS, -1);
 
@@ -300,19 +290,25 @@ esdhc_send_cmd(struct mci_host *mci, struct mci_cmd *cmd, struct mci_data *data)
 	if (data) {
 		int err;
 
-		err = esdhc_setup_data(mci, data);
-		if(err)
-			return err;
+		if (!IS_ENABLED(CONFIG_MCI_IMX_ESDHC_PIO)) {
+			num_bytes = data->blocks * data->blocksize;
 
-		num_bytes = data->blocks * data->blocksize;
+			if (data->flags & MMC_DATA_WRITE) {
+				ptr = (void *)data->src;
+				dir = DMA_TO_DEVICE;
+			} else {
+				ptr = data->dest;
+				dir = DMA_FROM_DEVICE;
+			}
 
-		if (data->flags & MMC_DATA_WRITE)
-			dma_sync_single_for_device((unsigned long)data->src,
-						   num_bytes, DMA_TO_DEVICE);
-		else
-			dma_sync_single_for_device((unsigned long)data->dest,
-						   num_bytes, DMA_FROM_DEVICE);
+			dma = dma_map_single(host->dev, ptr, num_bytes, dir);
+			if (dma_mapping_error(host->dev, dma))
+				return -EIO;
+		}
 
+		err = esdhc_setup_data(mci, data, dma);
+		if(err)
+			return err;
 	}
 
 	/* Figure out the transfer arguments */
@@ -383,6 +379,9 @@ esdhc_send_cmd(struct mci_host *mci, struct mci_cmd *cmd, struct mci_data *data)
 		ret = esdhc_do_data(mci, data);
 		if (ret)
 			return ret;
+
+		if (!IS_ENABLED(CONFIG_MCI_IMX_ESDHC_PIO))
+			dma_unmap_single(host->dev, dma, num_bytes, dir);
 	}
 
 	esdhc_write32(regs + SDHCI_INT_STATUS, -1);
-- 
2.16.1



From s.hauer at pengutronix.de  Mon Mar 19 02:11:43 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Mon, 19 Mar 2018 10:11:43 +0100
Subject: [PATCH 11/14] serial: i.MX: Add i.MX8 support
In-Reply-To: <20180319091146.4112-1-s.hauer@pengutronix.de>
References: <20180319091146.4112-1-s.hauer@pengutronix.de>
Message-ID: <20180319091146.4112-12-s.hauer@pengutronix.de>

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 drivers/serial/serial_imx.c | 5 ++++-
 include/serial/imx-uart.h   | 5 +++++
 2 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/serial/serial_imx.c b/drivers/serial/serial_imx.c
index e8c3836a66..49fb5e8340 100644
--- a/drivers/serial/serial_imx.c
+++ b/drivers/serial/serial_imx.c
@@ -290,9 +290,12 @@ static __maybe_unused struct of_device_id imx_serial_dt_ids[] = {
 	}, {
 		.compatible = "fsl,imx6ul-uart",
 		.data = &imx21_data,
-	},  {
+	}, {
 		.compatible = "fsl,imx7d-uart",
 		.data = &imx21_data,
+	}, {
+		.compatible = "fsl,imx8mq-uart",
+		.data = &imx21_data,
 	}, {
 		/* sentinel */
 	}
diff --git a/include/serial/imx-uart.h b/include/serial/imx-uart.h
index 9cab32f359..c23606569d 100644
--- a/include/serial/imx-uart.h
+++ b/include/serial/imx-uart.h
@@ -180,6 +180,11 @@ static inline void imx7_uart_setup(void __iomem *uartbase)
 	imx_uart_setup(uartbase, 24000000);
 }
 
+static inline void imx8mq_uart_setup(void __iomem *uartbase)
+{
+	imx_uart_setup(uartbase, 25000000);
+}
+
 static inline void imx_uart_putc(void *base, int c)
 {
 	if (!(readl(base + UCR1) & UCR1_UARTEN))
-- 
2.16.1



From s.hauer at pengutronix.de  Mon Mar 19 02:11:34 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Mon, 19 Mar 2018 10:11:34 +0100
Subject: [PATCH 02/14] ARM: i.MX: compile arm32 specific errata only for CPU32
In-Reply-To: <20180319091146.4112-1-s.hauer@pengutronix.de>
References: <20180319091146.4112-1-s.hauer@pengutronix.de>
Message-ID: <20180319091146.4112-3-s.hauer@pengutronix.de>

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/mach-imx/cpu_init.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/mach-imx/cpu_init.c b/arch/arm/mach-imx/cpu_init.c
index 6a6c4c5210..5b93d12da9 100644
--- a/arch/arm/mach-imx/cpu_init.c
+++ b/arch/arm/mach-imx/cpu_init.c
@@ -16,6 +16,7 @@
 #include <asm/errata.h>
 #include <linux/types.h>
 
+#ifdef CONFIG_CPU_32
 void imx5_cpu_lowlevel_init(void)
 {
 	arm_cpu_lowlevel_init();
@@ -50,3 +51,4 @@ void vf610_cpu_lowlevel_init(void)
 {
 	arm_cpu_lowlevel_init();
 }
+#endif
\ No newline at end of file
-- 
2.16.1



From s.hauer at pengutronix.de  Mon Mar 19 02:11:38 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Mon, 19 Mar 2018 10:11:38 +0100
Subject: [PATCH 06/14] ARM: i.MX8: Add i.MX8mq EVK support
In-Reply-To: <20180319091146.4112-1-s.hauer@pengutronix.de>
References: <20180319091146.4112-1-s.hauer@pengutronix.de>
Message-ID: <20180319091146.4112-7-s.hauer@pengutronix.de>

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/boards/Makefile                  |   1 +
 arch/arm/boards/nxp-imx8mq-evk/Makefile   |   2 +
 arch/arm/boards/nxp-imx8mq-evk/board.c    |  44 +++
 arch/arm/boards/nxp-imx8mq-evk/lowlevel.c |  43 +++
 arch/arm/dts/Makefile                     |   1 +
 arch/arm/dts/imx8mq-evk.dts               | 446 ++++++++++++++++++++++++++++++
 arch/arm/mach-imx/Kconfig                 |   4 +
 images/Makefile.imx                       |   6 +
 8 files changed, 547 insertions(+)
 create mode 100644 arch/arm/boards/nxp-imx8mq-evk/Makefile
 create mode 100644 arch/arm/boards/nxp-imx8mq-evk/board.c
 create mode 100644 arch/arm/boards/nxp-imx8mq-evk/lowlevel.c
 create mode 100644 arch/arm/dts/imx8mq-evk.dts

diff --git a/arch/arm/boards/Makefile b/arch/arm/boards/Makefile
index ca187ccb89..8a14383ce6 100644
--- a/arch/arm/boards/Makefile
+++ b/arch/arm/boards/Makefile
@@ -78,6 +78,7 @@ obj-$(CONFIG_MACH_NVIDIA_BEAVER)		+= nvidia-beaver/
 obj-$(CONFIG_MACH_NVIDIA_JETSON)		+= nvidia-jetson-tk1/
 obj-$(CONFIG_MACH_NXDB500)			+= netx/
 obj-$(CONFIG_MACH_NXP_IMX6ULL_EVK)		+= nxp-imx6ull-evk/
+obj-$(CONFIG_MACH_NXP_IMX8MQ_EVK)		+= nxp-imx8mq-evk/
 obj-$(CONFIG_MACH_OMAP343xSDP)			+= omap343xdsp/
 obj-$(CONFIG_MACH_OMAP3EVM)			+= omap3evm/
 obj-$(CONFIG_MACH_PANDA)			+= panda/
diff --git a/arch/arm/boards/nxp-imx8mq-evk/Makefile b/arch/arm/boards/nxp-imx8mq-evk/Makefile
new file mode 100644
index 0000000000..01c7a259e9
--- /dev/null
+++ b/arch/arm/boards/nxp-imx8mq-evk/Makefile
@@ -0,0 +1,2 @@
+obj-y += board.o
+lwl-y += lowlevel.o
diff --git a/arch/arm/boards/nxp-imx8mq-evk/board.c b/arch/arm/boards/nxp-imx8mq-evk/board.c
new file mode 100644
index 0000000000..d93e21da17
--- /dev/null
+++ b/arch/arm/boards/nxp-imx8mq-evk/board.c
@@ -0,0 +1,44 @@
+/*
+ * Copyright (C) 2018 Sascha Hauer, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation.
+ *
+ */
+
+#include <common.h>
+#include <init.h>
+#include <asm/memory.h>
+#include <linux/sizes.h>
+
+static int imx8mq_evk_mem_init(void)
+{
+	arm_add_mem_device("ram0", 0x40000000, SZ_2G);
+
+	request_sdram_region("ATF", 0x40000000, SZ_128K);
+
+	return 0;
+}
+mem_initcall(imx8mq_evk_mem_init);
+
+static int nxp_imx8mq_evk_init(void)
+{
+	if (!of_machine_is_compatible("fsl,imx8mq-evk"))
+		return 0;
+
+	barebox_set_hostname("imx8mq-evk");
+
+	return 0;
+}
+device_initcall(nxp_imx8mq_evk_init);
diff --git a/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c b/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c
new file mode 100644
index 0000000000..98198b3297
--- /dev/null
+++ b/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c
@@ -0,0 +1,43 @@
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ */
+
+#include <common.h>
+#include <linux/sizes.h>
+#include <mach/generic.h>
+#include <asm/barebox-arm-head.h>
+#include <asm/barebox-arm.h>
+#include <mach/imx6-regs.h>
+#include <io.h>
+#include <debug_ll.h>
+#include <asm/cache.h>
+#include <asm/sections.h>
+#include <asm/mmu.h>
+
+extern char __dtb_imx8mq_evk_start[];
+
+static noinline void nxp_imx8mq_evk(void)
+{
+	pbl_set_putc(imx_uart_putc, IOMEM(0x30860000));
+
+	printf("i.MX8MQ EVK\n");
+
+	barebox_arm_entry(0x40000000, 0xc0000000, __dtb_imx8mq_evk_start);
+}
+
+ENTRY_FUNCTION(start_nxp_imx8mq_evk, r0, r1, r2)
+{
+	arm_cpu_lowlevel_init();
+
+	relocate_to_current_adr();
+	setup_c();
+
+	nxp_imx8mq_evk();
+}
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 0526a6f407..75d29bf85d 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -81,6 +81,7 @@ pbl-dtb-$(CONFIG_MACH_SOLIDRUN_MICROSOM) += imx6dl-hummingboard.dtb.o imx6q-humm
 pbl-dtb-$(CONFIG_MACH_TECHNEXION_WANDBOARD) += imx6q-wandboard.dtb.o imx6dl-wandboard.dtb.o
 pbl-dtb-$(CONFIG_MACH_TECHNEXION_PICO_HOBBIT) += imx6ul-pico-hobbit.dtb.o
 pbl-dtb-$(CONFIG_MACH_NXP_IMX6ULL_EVK) += imx6ull-14x14-evk.dtb.o
+pbl-dtb-$(CONFIG_MACH_NXP_IMX8MQ_EVK) += imx8mq-evk.dtb.o
 pbl-dtb-$(CONFIG_MACH_TORADEX_COLIBRI_T20) += tegra20-colibri-iris.dtb.o
 pbl-dtb-$(CONFIG_MACH_TOSHIBA_AC100) += tegra20-paz00.dtb.o
 pbl-dtb-$(CONFIG_MACH_TQMA53) += imx53-mba53.dtb.o
diff --git a/arch/arm/dts/imx8mq-evk.dts b/arch/arm/dts/imx8mq-evk.dts
new file mode 100644
index 0000000000..fd9f780b65
--- /dev/null
+++ b/arch/arm/dts/imx8mq-evk.dts
@@ -0,0 +1,446 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2017 NXP
+ * Copyright (C) 2017 Pengutronix, Lucas Stach <kernel at pengutronix.de>
+ */
+
+/dts-v1/;
+
+#include "imx8mq.dtsi"
+
+/ {
+	model = "NXP i.MX8MQ EVK";
+	compatible = "fsl,imx8mq-evk", "fsl,imx8mq";
+
+	chosen {
+		bootargs = "console=ttymxc0,115200 ip=dhcp root=/dev/nfs nfsroot=/home/lst/nfsroot/mx8,v3,tcp";
+		//bootargs = "console=ttymxc0,115200 root=/dev/mmcblk0p2 rootwait rw";
+		stdout-path = &uart1;
+	};
+
+	memory at 40000000 {
+		device_type = "memory";
+		reg = <0x00000000 0x40000000 0 0xc0000000>;
+	};
+
+	reg_usdhc2_vmmc: regulator-vsd-3v3 {
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_reg_usdhc2>;
+		compatible = "regulator-fixed";
+		regulator-name = "VSD_3V3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+};
+
+&dcss {
+	status = "okay";
+};
+
+&fec1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_fec1_mdc>, <&pinctrl_fec1_mdio>,
+	            <&pinctrl_fec1_data_tx>, <&pinctrl_fec1_data_rx>,
+	            <&pinctrl_fec1_phy_reset>;
+	phy-mode = "rgmii-id";
+	status = "okay";
+};
+
+&hdmi {
+	status ="okay";
+};
+
+&i2c1 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c1>;
+	status = "okay";
+
+	pmic at 8 {
+		compatible = "fsl,pfuze100";
+		reg = <0x8>;
+
+		regulators {
+			sw1a_reg: sw1ab {
+				regulator-min-microvolt = <825000>;
+				regulator-max-microvolt = <1100000>;
+			};
+
+			sw1c_reg: sw1c {
+				regulator-min-microvolt = <825000>;
+				regulator-max-microvolt = <1100000>;
+			};
+
+			sw2_reg: sw2 {
+				regulator-min-microvolt = <1100000>;
+				regulator-max-microvolt = <1100000>;
+				regulator-always-on;
+			};
+
+			sw3a_reg: sw3ab {
+				regulator-min-microvolt = <825000>;
+				regulator-max-microvolt = <1100000>;
+				regulator-always-on;
+			};
+
+			sw4_reg: sw4 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-always-on;
+			};
+
+			swbst_reg: swbst {
+				regulator-min-microvolt = <5000000>;
+				regulator-max-microvolt = <5150000>;
+			};
+
+			snvs_reg: vsnvs {
+				regulator-min-microvolt = <1000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-always-on;
+			};
+
+			vref_reg: vrefddr {
+				regulator-always-on;
+			};
+
+			vgen1_reg: vgen1 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1550000>;
+			};
+
+			vgen2_reg: vgen2 {
+				regulator-min-microvolt = <850000>;
+				regulator-max-microvolt = <975000>;
+				regulator-always-on;
+			};
+
+			vgen3_reg: vgen3 {
+				regulator-min-microvolt = <1675000>;
+				regulator-max-microvolt = <1975000>;
+				regulator-always-on;
+			};
+
+			vgen4_reg: vgen4 {
+				regulator-min-microvolt = <1625000>;
+				regulator-max-microvolt = <1875000>;
+				regulator-always-on;
+			};
+
+			vgen5_reg: vgen5 {
+				regulator-min-microvolt = <3075000>;
+				regulator-max-microvolt = <3625000>;
+				regulator-always-on;
+			};
+
+			vgen6_reg: vgen6 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+			};
+		};
+	};
+};
+
+&ocotp {
+	barebox,provide-mac-address = <&fec1 0x640>;
+};
+
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart1>;
+	status = "okay";
+};
+
+&usb3_phy1 {
+	status = "okay";
+};
+
+&usb3_1 {
+	status = "okay";
+};
+
+&usb_dwc3_1 {
+	status = "okay";
+	dr_mode = "host";
+};
+
+&usdhc1 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc1_cd_reset>, <&pinctrl_usdhc1_clk_strobe>,
+	            <&pinctrl_usdhc1_data>;
+	pinctrl-1 = <&pinctrl_usdhc1_cd_reset>,
+	            <&pinctrl_usdhc1_clk_strobe_100mhz>,
+	            <&pinctrl_usdhc1_data_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc1_cd_reset>,
+	            <&pinctrl_usdhc1_clk_strobe_200mhz>,
+	            <&pinctrl_usdhc1_data_200mhz>;
+	vqmmc-supply = <&sw4_reg>;
+	bus-width = <8>;
+	non-removable;
+	no-sd;
+	no-sdio;
+	status = "okay";
+};
+
+&usdhc2 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc2_vselect>, <&pinctrl_usdhc2_clk>,
+	            <&pinctrl_usdhc2_data>;
+	pinctrl-1 = <&pinctrl_usdhc2_vselect>, <&pinctrl_usdhc2_clk_100mhz>,
+	            <&pinctrl_usdhc2_data_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc2_vselect>, <&pinctrl_usdhc2_clk_200mhz>,
+	            <&pinctrl_usdhc2_data_200mhz>;
+	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
+	vmmc-supply = <&reg_usdhc2_vmmc>;
+	status = "okay";
+};
+
+&wdog1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_wdog>;
+	fsl,ext-reset-output;
+	status = "okay";
+};
+
+&iomuxc {
+	pinctrl_fec1_mdc: fec1mdcgrp {
+		pinmux = <MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC>;
+		drive-strength = <3>;
+		slew-rate = <0>;
+	};
+
+	pinctrl_fec1_mdio: fec1mdiogrp {
+		pinmux = <MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO>;
+		drive-strength = <3>;
+		slew-rate = <0>;
+		drive-open-drain;
+	};
+
+	pinctrl_fec1_phy_reset: fec1phyresetgrp {
+		pinmux = <MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9>;
+		drive-strength = <1>;
+		slew-rate = <0>;
+	};
+
+	pinctrl_fec1_data_tx: fec1datatxgrp {
+		pinmux = <
+			MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3
+			MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2
+			MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1
+			MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0
+			MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC
+			MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL
+		>;
+		drive-strength = <7>;
+		slew-rate = <3>;
+	};
+
+	pinctrl_fec1_data_rx: fec1datarxgrp {
+		pinmux = <
+			MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3
+			MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2
+			MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1
+			MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0
+			MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC
+			MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL
+		>;
+		drive-strength = <1>;
+		slew-rate = <2>;
+		input-schmitt-enable;
+	};
+
+	pinctrl_i2c1: i2c1grp {
+		pinmux = <
+			MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL
+			MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA
+		>;
+		drive-strength = <7>;
+		slew-rate = <0>;
+		drive-open-drain;
+		input-enable;
+	};
+
+	pinctrl_reg_usdhc2: regusdhc2grpgpio {
+		pinmux = <MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19>;
+		drive-strength = <1>;
+		slew-rate = <0>;
+		bias-pull-up;
+	};
+
+	pinctrl_uart1: uart1grp {
+		pinmux = <
+			MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX
+			MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX
+		>;
+		drive-strength = <1>;
+		slew-rate = <0>;
+		bias-pull-up;
+	};
+
+	pinctrl_usdhc1_cd_reset: usdhc1cdgrp {
+		pinmux = <
+			MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12
+			MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B
+			>;
+		drive-strength = <1>;
+		slew-rate = <0>;
+		bias-pull-up;
+	};
+
+	pinctrl_usdhc1_clk_strobe: usdhc1clkgrp {
+		pinmux = <
+			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK
+			MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE
+			>;
+		drive-strength = <3>;
+		slew-rate = <0>;
+	};
+
+	pinctrl_usdhc1_data: usdhc1datagrp {
+		pinmux = <
+			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD
+			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0
+			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1
+			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2
+			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3
+			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4
+			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5
+			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6
+			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7
+			>;
+		drive-strength = <3>;
+		slew-rate = <0>;
+		bias-pull-up;
+		input-schmitt-enable;
+	};
+
+	pinctrl_usdhc1_clk_strobe_100mhz: usdhc1clk100grp {
+		pinmux = <
+			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK
+			MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE
+			>;
+		drive-strength = <3>;
+		slew-rate = <0>;
+	};
+
+	pinctrl_usdhc1_data_100mhz: usdhc1data100grp {
+		pinmux = <
+			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD
+			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0
+			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1
+			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2
+			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3
+			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4
+			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5
+			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6
+			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7
+			>;
+		drive-strength = <5>;
+		slew-rate = <1>;
+		bias-pull-up;
+		input-schmitt-enable;
+	};
+
+	pinctrl_usdhc1_clk_strobe_200mhz: usdhc1clk200grp {
+		pinmux = <
+			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK
+			MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE
+			>;
+		drive-strength = <7>;
+		slew-rate = <3>;
+	};
+
+	pinctrl_usdhc1_data_200mhz: usdhc1data200grp {
+		pinmux = <
+			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD
+			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0
+			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1
+			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2
+			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3
+			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4
+			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5
+			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6
+			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7
+			>;
+		drive-strength = <7>;
+		slew-rate = <3>;
+		bias-pull-up;
+		input-schmitt-enable;
+	};
+
+	pinctrl_usdhc2_vselect: usdhc2vselectgrp {
+		pinmux = <MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT>;
+		drive-strength = <1>;
+		slew-rate = <0>;
+		bias-pull-up;
+	};
+
+	pinctrl_usdhc2_clk: usdhc2clkgrp {
+		pinmux = <MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK>;
+		drive-strength = <3>;
+		slew-rate = <0>;
+	};
+
+	pinctrl_usdhc2_data: usdhc2datagrp {
+		pinmux = <
+			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD
+			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0
+			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1
+			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2
+			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3
+			>;
+		drive-strength = <3>;
+		slew-rate = <0>;
+		bias-pull-up;
+		input-schmitt-enable;
+	};
+
+	pinctrl_usdhc2_clk_100mhz: usdhc2clk100grp {
+		pinmux = <MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK>;
+		drive-strength = <5>;
+		slew-rate = <1>;
+	};
+
+	pinctrl_usdhc2_data_100mhz: usdhc2data100grp {
+		pinmux = <
+			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD
+			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0
+			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1
+			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2
+			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3
+			>;
+		drive-strength = <5>;
+		slew-rate = <1>;
+		bias-pull-up;
+		input-schmitt-enable;
+	};
+
+	pinctrl_usdhc2_clk_200mhz: usdhc2clk200grp {
+		pinmux = <MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK>;
+		drive-strength = <7>;
+		slew-rate = <3>;
+	};
+
+	pinctrl_usdhc2_data_200mhz: usdhc2data200grp {
+		pinmux = <
+			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD
+			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0
+			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1
+			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2
+			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3
+			>;
+		drive-strength = <7>;
+		slew-rate = <3>;
+		bias-pull-up;
+		input-schmitt-enable;
+	};
+
+	pinctrl_wdog: wdoggrp {
+		pinmux = <MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B>;
+		drive-strength = <6>;
+		slew-rate = <0>;
+		bias-pull-up;
+	};
+};
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 54078cc65b..5b430b19d6 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -429,6 +429,10 @@ config MACH_NXP_IMX6ULL_EVK
 	bool "NXP i.MX6ull EVK Board"
 	select ARCH_IMX6UL
 
+config MACH_NXP_IMX8MQ_EVK
+	bool "NXP i.MX8MQ EVK Board"
+	select ARCH_IMX8MQ
+
 endif
 
 # ----------------------------------------------------------
diff --git a/images/Makefile.imx b/images/Makefile.imx
index 5e0043f1f0..b2325553bc 100644
--- a/images/Makefile.imx
+++ b/images/Makefile.imx
@@ -490,7 +490,13 @@ CFG_start_zii_vf610_dev.pblx.imximg = $(board)/zii-vf610-dev/flash-header-zii-vf
 FILE_barebox-zii-vf610-dev.img = start_zii_vf610_dev.pblx.imximg
 image-$(CONFIG_MACH_ZII_VF610_DEV) += barebox-zii-vf610-dev.img
 
+# ----------------------- i.MX7 based boards ---------------------------
 pblx-$(CONFIG_MACH_FREESCALE_MX7_SABRESD) += start_imx7d_sabresd
 CFG_start_imx7d_sabresd.pblx.imximg = $(board)/freescale-mx7-sabresd/flash-header-mx7-sabresd.imxcfg
 FILE_barebox-freescale-mx7-sabresd.img = start_imx7d_sabresd.pblx.imximg
 image-$(CONFIG_MACH_FREESCALE_MX7_SABRESD) += barebox-freescale-mx7-sabresd.img
+
+# ----------------------- i.MX8mq based boards --------------------------
+pblx-$(CONFIG_MACH_NXP_IMX8MQ_EVK) += start_nxp_imx8mq_evk
+FILE_barebox-nxp-imx8mq-evk.img = start_nxp_imx8mq_evk.pblx
+image-$(CONFIG_MACH_NXP_IMX8MQ_EVK) += barebox-nxp-imx8mq-evk.img
-- 
2.16.1



From s.hauer at pengutronix.de  Mon Mar 19 02:11:40 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Mon, 19 Mar 2018 10:11:40 +0100
Subject: [PATCH 08/14] net: fec_imx: remove unnecessary DMA sync ops
In-Reply-To: <20180319091146.4112-1-s.hauer@pengutronix.de>
References: <20180319091146.4112-1-s.hauer@pengutronix.de>
Message-ID: <20180319091146.4112-9-s.hauer@pengutronix.de>

The fec receive buffers are coherently mapped, no need to dma_sync on
them.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 drivers/net/fec_imx.c | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/drivers/net/fec_imx.c b/drivers/net/fec_imx.c
index d506fd64f1..33599dd826 100644
--- a/drivers/net/fec_imx.c
+++ b/drivers/net/fec_imx.c
@@ -580,11 +580,7 @@ static int fec_recv(struct eth_device *dev)
 			 */
 			frame = phys_to_virt(readl(&rbd->data_pointer));
 			frame_length = readw(&rbd->data_length) - 4;
-			dma_sync_single_for_cpu((unsigned long)frame->data,
-						frame_length, DMA_FROM_DEVICE);
 			net_receive(dev, frame->data, frame_length);
-			dma_sync_single_for_device((unsigned long)frame->data,
-						   frame_length, DMA_FROM_DEVICE);
 			len = frame_length;
 		} else {
 			if (bd_status & FEC_RBD_ERR) {
-- 
2.16.1



From s.hauer at pengutronix.de  Mon Mar 19 02:11:45 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Mon, 19 Mar 2018 10:11:45 +0100
Subject: [PATCH 13/14] gpio: i.MX: Add i.MX8mq support
In-Reply-To: <20180319091146.4112-1-s.hauer@pengutronix.de>
References: <20180319091146.4112-1-s.hauer@pengutronix.de>
Message-ID: <20180319091146.4112-14-s.hauer@pengutronix.de>

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 drivers/gpio/gpio-imx.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpio/gpio-imx.c b/drivers/gpio/gpio-imx.c
index d8bcea2234..d618e60119 100644
--- a/drivers/gpio/gpio-imx.c
+++ b/drivers/gpio/gpio-imx.c
@@ -190,6 +190,9 @@ static __maybe_unused struct of_device_id imx_gpio_dt_ids[] = {
 	}, {
 		.compatible = "fsl,imx6q-gpio",
 		.data = &regs_imx31,
+	},  {
+		.compatible = "fsl,imx8mq-gpio",
+		.data = &regs_imx31,
 	}, {
 		/* sentinel */
 	}
-- 
2.16.1



From s.hauer at pengutronix.de  Mon Mar 19 02:11:41 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Mon, 19 Mar 2018 10:11:41 +0100
Subject: [PATCH 09/14] net: fec_imx: Use dma mapping functions
In-Reply-To: <20180319091146.4112-1-s.hauer@pengutronix.de>
References: <20180319091146.4112-1-s.hauer@pengutronix.de>
Message-ID: <20180319091146.4112-10-s.hauer@pengutronix.de>

Rather than doing DMA on the input buffer address get a proper DMA
address from the mapping functions.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 drivers/net/fec_imx.c | 15 +++++++++------
 drivers/net/fec_imx.h |  1 +
 2 files changed, 10 insertions(+), 6 deletions(-)

diff --git a/drivers/net/fec_imx.c b/drivers/net/fec_imx.c
index 33599dd826..0ca5940821 100644
--- a/drivers/net/fec_imx.c
+++ b/drivers/net/fec_imx.c
@@ -453,6 +453,7 @@ static int fec_send(struct eth_device *dev, void *eth_data, int data_length)
 {
 	unsigned int status;
 	uint64_t tmo;
+	dma_addr_t dma;
 
 	/*
 	 * This routine transmits one frame.  This routine only accepts
@@ -466,7 +467,7 @@ static int fec_send(struct eth_device *dev, void *eth_data, int data_length)
 		return -1;
 	}
 
-	if ((uint32_t)eth_data & (DB_DATA_ALIGNMENT-1))
+	if ((unsigned long)eth_data & (DB_DATA_ALIGNMENT - 1))
 		dev_warn(&dev->dev, "Transmit data not aligned: %p!\n", eth_data);
 
 	/*
@@ -479,10 +480,12 @@ static int fec_send(struct eth_device *dev, void *eth_data, int data_length)
 
 	writew(data_length, &fec->tbd_base[fec->tbd_index].data_length);
 
-	writel((uint32_t)(eth_data), &fec->tbd_base[fec->tbd_index].data_pointer);
+	dma = dma_map_single(fec->dev, eth_data, data_length, DMA_TO_DEVICE);
+	if (dma_mapping_error(fec->dev, dma))
+		return -EIO;
+
+	writel((uint32_t)(dma), &fec->tbd_base[fec->tbd_index].data_pointer);
 
-	dma_sync_single_for_device((unsigned long)eth_data, data_length,
-				   DMA_TO_DEVICE);
 	/*
 	 * update BD's status now
 	 * This block:
@@ -505,8 +508,7 @@ static int fec_send(struct eth_device *dev, void *eth_data, int data_length)
 			break;
 		}
 	}
-	dma_sync_single_for_cpu((unsigned long)eth_data, data_length,
-				DMA_TO_DEVICE);
+	dma_unmap_single(fec->dev, dma, data_length, DMA_TO_DEVICE);
 
 	/* for next transmission use the other buffer */
 	if (fec->tbd_index)
@@ -748,6 +750,7 @@ static int fec_probe(struct device_d *dev)
 
 	fec = xzalloc(sizeof(*fec));
 	fec->type = type;
+	fec->dev = dev;
 	edev = &fec->edev;
 	dev->priv = fec;
 	edev->priv = fec;
diff --git a/drivers/net/fec_imx.h b/drivers/net/fec_imx.h
index 561de0890b..e3f60dd66a 100644
--- a/drivers/net/fec_imx.h
+++ b/drivers/net/fec_imx.h
@@ -149,6 +149,7 @@ enum fec_opt_clock {
  */
 struct fec_priv {
 	struct eth_device edev;
+	struct device_d *dev;
 	void __iomem *regs;
 	struct buffer_descriptor __iomem *rbd_base;	/* RBD ring                  */
 	int rbd_index;				/* next receive BD to read   */
-- 
2.16.1



From s.hauer at pengutronix.de  Mon Mar 19 02:11:42 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Mon, 19 Mar 2018 10:11:42 +0100
Subject: [PATCH 10/14] clock: Add i.MX8MQ clock driver
In-Reply-To: <20180319091146.4112-1-s.hauer@pengutronix.de>
References: <20180319091146.4112-1-s.hauer@pengutronix.de>
Message-ID: <20180319091146.4112-11-s.hauer@pengutronix.de>

This is based on Lucas' patch sent as "[PATCH v2 4/4] clk: imx: add
clock driver for i.MX8MQ CCM" to the mailing list.

It will likely need some rework before it is finally merged, so apply
the reworks here before merging into barebox.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 drivers/clk/imx/Makefile       |   3 +
 drivers/clk/imx/clk-frac-pll.c | 226 ++++++++++++++++
 drivers/clk/imx/clk-imx8mq.c   | 580 +++++++++++++++++++++++++++++++++++++++++
 drivers/clk/imx/clk-sccg-pll.c | 242 +++++++++++++++++
 drivers/clk/imx/clk.h          |  27 ++
 5 files changed, 1078 insertions(+)
 create mode 100644 drivers/clk/imx/clk-frac-pll.c
 create mode 100644 drivers/clk/imx/clk-imx8mq.c
 create mode 100644 drivers/clk/imx/clk-sccg-pll.c

diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
index b864b4f321..8f441a97e7 100644
--- a/drivers/clk/imx/Makefile
+++ b/drivers/clk/imx/Makefile
@@ -6,6 +6,8 @@ obj-$(CONFIG_COMMON_CLK) +=	\
 	clk-gate2.o		\
 	clk-gate-exclusive.o	\
 	clk-cpu.o		\
+	clk-frac-pll.o		\
+	clk-sccg-pll.o		\
 	clk.o
 
 obj-$(CONFIG_ARCH_IMX1)   += clk-imx1.o
@@ -22,4 +24,5 @@ obj-$(CONFIG_ARCH_IMX6SX) += clk-imx6sx.o
 obj-$(CONFIG_ARCH_IMX6SL) += clk-imx6sl.o
 obj-$(CONFIG_ARCH_IMX6UL) += clk-imx6ul.o
 obj-$(CONFIG_ARCH_IMX7) += clk-imx7.o
+obj-$(CONFIG_ARCH_IMX8MQ) += clk-imx8mq.o
 obj-$(CONFIG_ARCH_VF610)  += clk-vf610.o
diff --git a/drivers/clk/imx/clk-frac-pll.c b/drivers/clk/imx/clk-frac-pll.c
new file mode 100644
index 0000000000..def870e244
--- /dev/null
+++ b/drivers/clk/imx/clk-frac-pll.c
@@ -0,0 +1,226 @@
+/*
+ * Copyright 2017 NXP.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <common.h>
+#include <io.h>
+#include <malloc.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <asm-generic/div64.h>
+
+#include "clk.h"
+
+#define PLL_CFG0 	0x0
+#define PLL_CFG1	0x4
+
+#define PLL_LOCK_STATUS	(0x1 << 31)
+#define PLL_CLKE	21
+#define PLL_PD		19
+#define PLL_BYPASS	14
+#define PLL_NEWDIV_VAL		(1 << 12)
+#define PLL_NEWDIV_ACK		(1 << 11)
+#define PLL_FRAC_DIV_MASK	0xffffff
+#define PLL_INT_DIV_MASK	0x7f
+#define PLL_FRAC_DENOM		0x1000000
+
+struct clk_frac_pll {
+	struct clk	clk;
+	void __iomem	*base;
+	const char *parent;
+};
+
+#define to_clk_frac_pll(_clk) container_of(_clk, struct clk_frac_pll, clk)
+
+static int clk_wait_lock(struct clk_frac_pll *pll)
+{
+	unsigned long timeout = 100000;
+
+	/* Wait for PLL to lock */
+	while (timeout--) {
+		if (readl(pll->base) & PLL_LOCK_STATUS)
+			break;
+	}
+
+	return readl(pll->base) & PLL_LOCK_STATUS ? 0 : -ETIMEDOUT;
+}
+
+static int clk_wait_ack(struct clk_frac_pll *pll)
+{
+	unsigned long timeout = 100000;
+
+	/* return directly if the pll is in powerdown or in bypass */
+	if (readl(pll->base) & ((1 << PLL_PD) | (1 << PLL_BYPASS)))
+		return 0;
+
+	/* Wait for the pll's divfi and divff to be reloaded */
+	while (timeout--) {
+		if (readl(pll->base) & PLL_NEWDIV_ACK)
+			break;
+	}
+
+	return readl(pll->base) & PLL_NEWDIV_ACK ? 0 : ETIMEDOUT;
+}
+
+static int clk_pll_enable(struct clk *clk)
+{
+	struct clk_frac_pll *pll = to_clk_frac_pll(clk);
+	u32 val;
+
+	val = readl(pll->base + PLL_CFG0);
+	val &= ~(1 << PLL_PD);
+	writel(val, pll->base + PLL_CFG0);
+
+	return clk_wait_lock(pll);
+}
+
+static void clk_pll_disable(struct clk *clk)
+{
+	struct clk_frac_pll *pll = to_clk_frac_pll(clk);
+	u32 val;
+
+	val = readl(pll->base + PLL_CFG0);
+	val |= (1 << PLL_PD);
+	writel(val, pll->base + PLL_CFG0);
+}
+
+static int clk_pll_is_enabled(struct clk *clk)
+{
+	struct clk_frac_pll *pll = to_clk_frac_pll(clk);
+	u32 val;
+
+	val = readl(pll->base + PLL_CFG0);
+	return (val & (1 << PLL_PD)) ? 0 : 1;
+}
+
+static unsigned long clk_pll_recalc_rate(struct clk *clk,
+					 unsigned long parent_rate)
+{
+	struct clk_frac_pll *pll = to_clk_frac_pll(clk);
+	u32 val, divff, divfi, divq;
+	u64 temp64;
+
+	val = readl(pll->base + PLL_CFG0);
+	divq = ((val & 0x1f) + 1) * 2;
+	val = readl(pll->base + PLL_CFG1);
+	divff = (val >> 7) & PLL_FRAC_DIV_MASK;
+	divfi = (val & PLL_INT_DIV_MASK);
+
+	temp64 = (u64)parent_rate * 8;
+	temp64 *= divff;
+	do_div(temp64, PLL_FRAC_DENOM);
+	temp64 /= divq;
+
+	return parent_rate * 8 * (divfi + 1) / divq + (unsigned long)temp64;
+}
+
+static long clk_pll_round_rate(struct clk *clk, unsigned long rate,
+			       unsigned long *prate)
+{
+	u32 divff, divfi;
+	u64 temp64;
+	unsigned long parent_rate = *prate;
+
+	parent_rate *= 8;
+	rate *= 2;
+	divfi = rate / parent_rate;
+	temp64 = (u64)(rate - divfi * parent_rate);
+	temp64 *= PLL_FRAC_DENOM;
+	do_div(temp64, parent_rate);
+	divff = temp64;
+
+	temp64 = (u64)parent_rate;
+	temp64 *= divff;
+	do_div(temp64, PLL_FRAC_DENOM);
+
+	return (parent_rate * divfi + (unsigned long)temp64) / 2;
+}
+
+/*
+ * To simplify the clock calculation, we can keep the 'PLL_OUTPUT_VAL' at zero
+ * (means the PLL output will be divided by 2). So the PLL output can use
+ * the below formula:
+ * pllout = parent_rate * 8 / 2 * DIVF_VAL;
+ * where DIVF_VAL = 1 + DIVFI + DIVFF / 2^24.
+ */
+static int clk_pll_set_rate(struct clk *clk, unsigned long rate,
+			    unsigned long parent_rate)
+{
+	struct clk_frac_pll *pll = to_clk_frac_pll(clk);
+	u32 val, divfi, divff;
+	u64 temp64;
+	int ret;
+
+	parent_rate *= 8;
+	rate *= 2;
+	divfi = rate / parent_rate;
+	temp64 = (u64) (rate - divfi * parent_rate);
+	temp64 *= PLL_FRAC_DENOM;
+	do_div(temp64, parent_rate);
+	divff = temp64;
+
+	val = readl(pll->base + PLL_CFG1);
+	val &= ~((PLL_FRAC_DIV_MASK << 7) | (PLL_INT_DIV_MASK));
+	val |= ((divff << 7) | (divfi - 1));
+	writel(val, pll->base + PLL_CFG1);
+
+	val = readl(pll->base + PLL_CFG0);
+	val &= ~0x1f;
+	writel(val, pll->base + PLL_CFG0);
+
+	/* Set the NEV_DIV_VAL to reload the DIVFI and DIVFF */
+	val = readl(pll->base + PLL_CFG0);
+	val |= PLL_NEWDIV_VAL;
+	writel(val, pll->base + PLL_CFG0);
+
+	ret = clk_wait_ack(pll);
+
+	/* clear the NEV_DIV_VAL */
+	val = readl(pll->base + PLL_CFG0);
+	val &= ~PLL_NEWDIV_VAL;
+	writel(val, pll->base + PLL_CFG0);
+
+	return ret;
+}
+
+static const struct clk_ops clk_frac_pll_ops = {
+	.enable		= clk_pll_enable,
+	.disable	= clk_pll_disable,
+	.is_enabled	= clk_pll_is_enabled,
+	.recalc_rate	= clk_pll_recalc_rate,
+	.round_rate	= clk_pll_round_rate,
+	.set_rate	= clk_pll_set_rate,
+};
+
+struct clk *imx_clk_frac_pll(const char *name, const char *parent,
+			     void __iomem *base)
+{
+	struct clk_frac_pll *pll;
+	int ret;
+
+	pll = kzalloc(sizeof(*pll), GFP_KERNEL);
+	if (!pll)
+		return ERR_PTR(-ENOMEM);
+
+	pll->base = base;
+	pll->parent = parent;
+	pll->clk.ops = &clk_frac_pll_ops;
+	pll->clk.name = name;
+	pll->clk.parent_names = &pll->parent;
+	pll->clk.num_parents = 1;
+
+	ret = clk_register(&pll->clk);
+	if (ret) {
+		free(pll);
+		return ERR_PTR(ret);
+	}
+
+	return &pll->clk;
+}
diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c
new file mode 100644
index 0000000000..21d88dd10d
--- /dev/null
+++ b/drivers/clk/imx/clk-imx8mq.c
@@ -0,0 +1,580 @@
+/*
+ * Copyright 2017 NXP.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <common.h>
+#include <init.h>
+#include <driver.h>
+#include <linux/clk.h>
+#include <io.h>
+#include <of.h>
+#include <of_address.h>
+#include <linux/clkdev.h>
+#include <linux/err.h>
+#include <mach/revision.h>
+#include <dt-bindings/clock/imx8mq-clock.h>
+
+#include "clk.h"
+
+static struct clk *clks[IMX8MQ_CLK_END];
+
+static const char *pll_ref_sels[] = { "osc_25m", "osc_27m", "dummy", "dummy", };
+static const char *arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", };
+static const char *gpu_pll_bypass_sels[] = {"gpu_pll", "gpu_pll_ref_sel", };
+static const char *vpu_pll_bypass_sels[] = {"vpu_pll", "vpu_pll_ref_sel", };
+static const char *audio_pll1_bypass_sels[] = {"audio_pll1", "audio_pll1_ref_sel", };
+static const char *audio_pll2_bypass_sels[] = {"audio_pll2", "audio_pll2_ref_sel", };
+static const char *video_pll1_bypass_sels[] = {"video_pll1", "video_pll1_ref_sel", };
+
+static const char *sys1_pll1_out_sels[] = {"sys1_pll1", "sys1_pll1_ref_sel", };
+static const char *sys2_pll1_out_sels[] = {"sys2_pll1", "sys1_pll1_ref_sel", };
+static const char *sys3_pll1_out_sels[] = {"sys3_pll1", "sys3_pll1_ref_sel", };
+static const char *dram_pll1_out_sels[] = {"dram_pll1", "dram_pll1_ref_sel", };
+static const char *video2_pll1_out_sels[] = {"video2_pll1", "video2_pll1_ref_sel", };
+
+static const char *sys1_pll2_out_sels[] = {"sys1_pll2_div", "sys1_pll1_ref_sel", };
+static const char *sys2_pll2_out_sels[] = {"sys2_pll2_div", "sys2_pll1_ref_sel", };
+static const char *sys3_pll2_out_sels[] = {"sys3_pll2_div", "sys2_pll1_ref_sel", };
+static const char *dram_pll2_out_sels[] = {"dram_pll2_div", "dram_pll1_ref_sel", };
+static const char *video2_pll2_out_sels[] = {"video2_pll2_div", "video2_pll1_ref_sel", };
+
+/* CCM ROOT */
+static const char *imx8mq_a53_sels[] = {"osc_25m", "arm_pll_out", "sys2_pll_500m", "sys2_pll_1000m",
+					"sys1_pll_800m", "sys1_pll_400m", "audio_pll1_out", "sys3_pll2_out", };
+
+static const char *imx8mq_main_axi_sels[] = {"osc_25m", "sys2_pll_333m", "sys1_pll_800m", "sys2_pll_250m",
+					     "sys2_pll_1000m", "audio_pll1_out", "video_pll1_out", "sys1_pll_100m",};
+
+static const char *imx8mq_enet_axi_sels[] = {"osc_25m", "sys1_pll_266m", "sys1_pll_800m", "sys2_pll_250m",
+					     "sys2_pll_200m", "audio_pll1_out", "video_pll1_out", "sys3_pll2_out", };
+
+static const char *imx8mq_nand_usdhc_sels[] = {"osc_25m", "sys1_pll_266m", "sys1_pll_800m", "sys2_pll_200m",
+					       "sys1_pll_133m", "sys3_pll2_out", "sys2_pll_250m", "audio_pll1_out", };
+
+static const char *imx8mq_usb_bus_sels[] = {"osc_25m", "sys2_pll_500m", "sys1_pll_800m", "sys2_pll_100m",
+					    "sys2_pll_200m", "clk_ext2", "clk_ext4", "audio_pll2_out", };
+
+static const char *imx8mq_noc_sels[] = {"osc_25m", "sys1_pll_800m", "sys3_pll2_out", "sys2_pll_1000m", "sys2_pll_500m",
+					"audio_pll1_out", "video_pll1_out", "audio_pll2_out", };
+
+static const char *imx8mq_noc_apb_sels[] = {"osc_25m", "sys1_pll_400m", "sys3_pll2_out", "sys2_pll_333m", "sys2_pll_200m",
+					    "sys1_pll_800m", "audio_pll1_out", "video_pll1_out", };
+
+static const char *imx8mq_ahb_sels[] = {"osc_25m", "sys1_pll_133m", "sys1_pll_800m", "sys1_pll_400m",
+					"sys2_pll_125m", "sys3_pll2_out", "audio_pll1_out", "video_pll1_out", };
+
+static const char *imx8mq_dram_alt_sels[] = {"osc_25m", "sys1_pll_800m", "sys1_pll_100m", "sys2_pll_500m",
+					     "sys2_pll_250m", "sys1_pll_400m", "audio_pll1_out", "sys1_pll_266m", };
+
+static const char *imx8mq_dram_apb_sels[] = {"osc_25m", "sys2_pll_200m", "sys1_pll_40m", "sys1_pll_160m",
+					     "sys1_pll_800m", "sys3_pll2_out", "sys2_pll_250m", "audio_pll2_out", };
+
+static const char *imx8mq_pcie1_ctrl_sels[] = {"osc_25m", "sys2_pll_250m", "sys2_pll_200m", "sys1_pll_266m",
+					       "sys1_pll_800m", "sys2_pll_500m", "sys2_pll_250m", "sys3_pll2_out", };
+
+static const char *imx8mq_pcie1_phy_sels[] = {"osc_25m", "sys2_pll_100m", "sys2_pll_500m", "clk_ext1", "clk_ext2",
+					      "clk_ext3", "clk_ext4", };
+
+static const char *imx8mq_pcie1_aux_sels[] = {"osc_25m", "sys2_pll_200m", "sys2_pll_500m", "sys3_pll2_out",
+					      "sys2_pll_100m", "sys1_pll_80m", "sys1_pll_160m", "sys1_pll_200m", };
+
+static const char *imx8mq_dc_pixel_sels[] = {"osc_25m", "video_pll1_out", "audio_pll2_out", "audio_pll1_out", "sys1_pll_800m", "sys2_pll_1000m", "sys3_pll2_out", "clk_ext4", };
+
+static const char *imx8mq_lcdif_pixel_sels[] = {"osc_25m", "video_pll1_out", "audio_pll2_out", "audio_pll1_out", "sys1_pll_800m", "sys2_pll_1000m", "sys3_pll2_out", "clk_ext4", };
+
+static const char *imx8mq_enet_ref_sels[] = {"osc_25m", "sys2_pll_125m", "sys2_pll_500m", "sys2_pll_100m",
+					     "sys1_pll_160m", "audio_pll1_out", "video_pll1_out", "clk_ext4", };
+
+static const char *imx8mq_enet_timer_sels[] = {"osc_25m", "sys2_pll_100m", "audio_pll1_out", "clk_ext1", "clk_ext2",
+					       "clk_ext3", "clk_ext4", "video_pll1_out", };
+
+static const char *imx8mq_enet_phy_sels[] = {"osc_25m", "sys2_pll_50m", "sys2_pll_125m", "sys2_pll_500m",
+					     "audio_pll1_out", "video_pll1_out", "audio_pll2_out", };
+
+static const char *imx8mq_nand_sels[] = {"osc_25m", "sys2_pll_500m", "audio_pll1_out", "sys1_pll_400m",
+					 "audio_pll2_out", "sys3_pll2_out", "sys2_pll_250m", "video_pll1_out", };
+
+static const char *imx8mq_qspi_sels[] = {"osc_25m", "sys1_pll_400m", "sys1_pll_800m", "sys2_pll_500m",
+					 "audio_pll2_out", "sys1_pll_266m", "sys3_pll2_out", "sys1_pll_100m", };
+
+static const char *imx8mq_usdhc1_sels[] = {"osc_25m", "sys1_pll_400m", "sys1_pll_800m", "sys2_pll_500m",
+					 "audio_pll2_out", "sys1_pll_266m", "sys3_pll2_out", "sys1_pll_100m", };
+
+static const char *imx8mq_usdhc2_sels[] = {"osc_25m", "sys1_pll_400m", "sys1_pll_800m", "sys2_pll_500m",
+					 "audio_pll2_out", "sys1_pll_266m", "sys3_pll2_out", "sys1_pll_100m", };
+
+static const char *imx8mq_i2c1_sels[] = {"osc_25m", "sys1_pll_160m", "sys2_pll_50m", "sys3_pll2_out", "audio_pll1_out",
+					 "video_pll1_out", "audio_pll2_out", "sys1_pll_133m", };
+
+static const char *imx8mq_i2c2_sels[] = {"osc_25m", "sys1_pll_160m", "sys2_pll_50m", "sys3_pll2_out", "audio_pll1_out",
+					 "video_pll1_out", "audio_pll2_out", "sys1_pll_133m", };
+
+static const char *imx8mq_i2c3_sels[] = {"osc_25m", "sys1_pll_160m", "sys2_pll_50m", "sys3_pll2_out", "audio_pll1_out",
+					 "video_pll1_out", "audio_pll2_out", "sys1_pll_133m", };
+
+static const char *imx8mq_i2c4_sels[] = {"osc_25m", "sys1_pll_160m", "sys2_pll_50m", "sys3_pll2_out", "audio_pll1_out",
+					 "video_pll1_out", "audio_pll2_out", "sys1_pll_133m", };
+
+static const char *imx8mq_uart1_sels[] = {"osc_25m", "sys1_pll_80m", "sys2_pll_200m", "sys2_pll_100m",
+					  "sys3_pll2_out", "clk_ext2", "clk_ext4", "audio_pll2_out", };
+
+static const char *imx8mq_uart2_sels[] = {"osc_25m", "sys1_pll_80m", "sys2_pll_200m", "sys2_pll_100m",
+					  "sys3_pll2_out", "clk_ext2", "clk_ext3", "audio_pll2_out", };
+
+static const char *imx8mq_uart3_sels[] = {"osc_25m", "sys1_pll_80m", "sys2_pll_200m", "sys2_pll_100m",
+					  "sys3_pll2_out", "clk_ext2", "clk_ext4", "audio_pll2_out", };
+
+static const char *imx8mq_uart4_sels[] = {"osc_25m", "sys1_pll_80m", "sys2_pll_200m", "sys2_pll_100m",
+					  "sys3_pll2_out", "clk_ext2", "clk_ext3", "audio_pll2_out", };
+
+static const char *imx8mq_usb_core_sels[] = {"osc_25m", "sys1_pll_100m", "sys1_pll_40m", "sys2_pll_100m",
+					     "sys2_pll_200m", "clk_ext2", "clk_ext3", "audio_pll2_out", };
+
+static const char *imx8mq_usb_phy_sels[] = {"osc_25m", "sys1_pll_100m", "sys1_pll_40m", "sys2_pll_100m",
+					     "sys2_pll_200m", "clk_ext2", "clk_ext3", "audio_pll2_out", };
+
+static const char *imx8mq_ecspi1_sels[] = {"osc_25m", "sys2_pll_200m", "sys1_pll_40m", "sys1_pll_160m",
+					   "sys1_pll_800m", "sys3_pll2_out", "sys2_pll_250m", "audio_pll2_out", };
+
+static const char *imx8mq_ecspi2_sels[] = {"osc_25m", "sys2_pll_200m", "sys1_pll_40m", "sys1_pll_160m",
+					   "sys1_pll_800m", "sys3_pll2_out", "sys2_pll_250m", "audio_pll2_out", };
+
+static const char *imx8mq_pwm1_sels[] = {"osc_25m", "sys2_pll_100m", "sys1_pll_160m", "sys1_pll_40m",
+					 "sys3_pll2_out", "clk_ext1", "sys1_pll_80m", "video_pll1_out", };
+
+static const char *imx8mq_pwm2_sels[] = {"osc_25m", "sys2_pll_100m", "sys1_pll_160m", "sys1_pll_40m",
+					 "sys3_pll2_out", "clk_ext1", "sys1_pll_80m", "video_pll1_out", };
+
+static const char *imx8mq_pwm3_sels[] = {"osc_25m", "sys2_pll_100m", "sys1_pll_160m", "sys1_pll_40m",
+					 "sys3_pll2_out", "clk_ext2", "sys1_pll_80m", "video_pll1_out", };
+
+static const char *imx8mq_pwm4_sels[] = {"osc_25m", "sys2_pll_100m", "sys1_pll_160m", "sys1_pll_40m",
+					 "sys3_pll2_out", "clk_ext2", "sys1_pll_80m", "video_pll1_out", };
+
+static const char *imx8mq_gpt1_sels[] = {"osc_25m", "sys2_pll_100m", "sys1_pll_400m", "sys1_pll_40m",
+					 "sys1_pll_80m", "audio_pll1_out", "clk_ext1", };
+
+static const char *imx8mq_wdog_sels[] = {"osc_25m", "sys1_pll_133m", "sys1_pll_160m", "vpu_pll_out",
+					 "sys2_pll_125m", "sys3_pll2_out", "sys1_pll_80m", "sys2_pll_166m", };
+
+static const char *imx8mq_wrclk_sels[] = {"osc_25m", "sys1_pll_40m", "vpu_pll_out", "sys3_pll2_out", "sys2_pll_200m",
+					  "sys1_pll_266m", "sys2_pll_500m", "sys1_pll_100m", };
+
+static const char *imx8mq_pcie2_ctrl_sels[] = {"osc_25m", "sys2_pll_250m", "sys2_pll_200m", "sys1_pll_266m",
+					       "sys1_pll_800m", "sys2_pll_500m", "sys2_pll_333m", "sys3_pll2_out", };
+
+static const char *imx8mq_pcie2_phy_sels[] = {"osc_25m", "sys2_pll_100m", "sys2_pll_500m", "clk_ext1",
+					      "clk_ext2", "clk_ext3", "clk_ext4", "sys1_pll_400m", };
+
+static const char *imx8mq_pcie2_aux_sels[] = {"osc_25m", "sys2_pll_200m", "sys2_pll_50m", "sys3_pll2_out",
+					      "sys2_pll_100m", "sys1_pll_80m", "sys1_pll_160m", "sys1_pll_200m", };
+
+static const char *imx8mq_ecspi3_sels[] = {"osc_25m", "sys2_pll_200m", "sys1_pll_40m", "sys1_pll_160m",
+					   "sys1_pll_800m", "sys3_pll2_out", "sys2_pll_250m", "audio_pll2_out", };
+static const char *imx8mq_dram_core_sels[] = {"dram_pll_out", "dram_alt_root", };
+
+static const char *imx8mq_clko2_sels[] = {"osc_25m", "sys2_pll_200m", "sys1_pll_400m", "sys2_pll_166m", "audio_pll1_out",
+					 "video_pll1_out", "ckil", };
+
+static struct clk_onecell_data clk_data;
+
+static void __init imx8mq_clocks_init(struct device_node *ccm_node)
+{
+	struct device_node *np;
+	void __iomem *base;
+	int i;
+
+	clks[IMX8MQ_CLK_DUMMY] = clk_fixed("dummy", 0);
+	clks[IMX8MQ_CLK_32K] = of_clk_get_by_name(ccm_node, "ckil");
+	clks[IMX8MQ_CLK_25M] = of_clk_get_by_name(ccm_node, "osc_25m");
+	clks[IMX8MQ_CLK_27M] = of_clk_get_by_name(ccm_node, "osc_27m");
+	clks[IMX8MQ_CLK_EXT1] = of_clk_get_by_name(ccm_node, "clk_ext1");
+	clks[IMX8MQ_CLK_EXT2] = of_clk_get_by_name(ccm_node, "clk_ext2");
+	clks[IMX8MQ_CLK_EXT3] = of_clk_get_by_name(ccm_node, "clk_ext3");
+	clks[IMX8MQ_CLK_EXT4] = of_clk_get_by_name(ccm_node, "clk_ext4");
+
+	np = of_find_compatible_node(NULL, NULL, "fsl,imx8mq-anatop");
+	base = of_iomap(np, 0);
+	WARN_ON(!base);
+
+	clks[IMX8MQ_ARM_PLL_REF_SEL] = imx_clk_mux("arm_pll_ref_sel", base + 0x28, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
+	clks[IMX8MQ_GPU_PLL_REF_SEL] = imx_clk_mux("gpu_pll_ref_sel", base + 0x18, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
+	clks[IMX8MQ_VPU_PLL_REF_SEL] = imx_clk_mux("vpu_pll_ref_sel", base + 0x20, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
+	clks[IMX8MQ_AUDIO_PLL1_REF_SEL] = imx_clk_mux("audio_pll1_ref_sel", base + 0x0, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
+	clks[IMX8MQ_AUDIO_PLL2_REF_SEL] = imx_clk_mux("audio_pll2_ref_sel", base + 0x8, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
+	clks[IMX8MQ_VIDEO_PLL1_REF_SEL] = imx_clk_mux("video_pll1_ref_sel", base + 0x10, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
+	clks[IMX8MQ_SYS1_PLL1_REF_SEL]	= imx_clk_mux("sys1_pll1_ref_sel", base + 0x30, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
+	clks[IMX8MQ_SYS2_PLL1_REF_SEL]	= imx_clk_mux("sys2_pll1_ref_sel", base + 0x3c, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
+	clks[IMX8MQ_SYS3_PLL1_REF_SEL]	= imx_clk_mux("sys3_pll1_ref_sel", base + 0x48, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
+	clks[IMX8MQ_DRAM_PLL1_REF_SEL]	= imx_clk_mux("dram_pll1_ref_sel", base + 0x60, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
+	clks[IMX8MQ_VIDEO2_PLL1_REF_SEL] = imx_clk_mux("video2_pll1_ref_sel", base + 0x54, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
+
+	clks[IMX8MQ_ARM_PLL_REF_DIV]	= imx_clk_divider("arm_pll_ref_div", "arm_pll_ref_sel", base + 0x28, 5, 6);
+	clks[IMX8MQ_GPU_PLL_REF_DIV]	= imx_clk_divider("gpu_pll_ref_div", "gpu_pll_ref_sel", base + 0x18, 5, 6);
+	clks[IMX8MQ_VPU_PLL_REF_DIV]	= imx_clk_divider("vpu_pll_ref_div", "vpu_pll_ref_sel", base + 0x20, 5, 6);
+	clks[IMX8MQ_AUDIO_PLL1_REF_DIV] = imx_clk_divider("audio_pll1_ref_div", "audio_pll1_ref_sel", base + 0x0, 5, 6);
+	clks[IMX8MQ_AUDIO_PLL2_REF_DIV] = imx_clk_divider("audio_pll2_ref_div", "audio_pll2_ref_sel", base + 0x8, 5, 6);
+	clks[IMX8MQ_VIDEO_PLL1_REF_DIV] = imx_clk_divider("video_pll1_ref_div", "video_pll1_ref_sel", base + 0x10, 5, 6);
+	clks[IMX8MQ_SYS1_PLL1_REF_DIV]	= imx_clk_divider("sys1_pll1_ref_div", "sys1_pll1_ref_sel", base + 0x38, 25, 3);
+	clks[IMX8MQ_SYS2_PLL1_REF_DIV]	= imx_clk_divider("sys2_pll1_ref_div", "sys2_pll1_ref_sel", base + 0x44, 25, 3);
+	clks[IMX8MQ_SYS3_PLL1_REF_DIV]	= imx_clk_divider("sys3_pll1_ref_div", "sys3_pll1_ref_sel", base + 0x50, 25, 3);
+	clks[IMX8MQ_DRAM_PLL1_REF_DIV]	= imx_clk_divider("dram_pll1_ref_div", "dram_pll1_ref_sel", base + 0x68, 25, 3);
+	clks[IMX8MQ_VIDEO2_PLL1_REF_DIV]  = imx_clk_divider("video2_pll1_ref_div", "video2_pll1_ref_sel", base + 0x5c, 25, 3);
+
+	clks[IMX8MQ_ARM_PLL] = imx_clk_frac_pll("arm_pll", "arm_pll_ref_div", base + 0x28);
+	clks[IMX8MQ_GPU_PLL] = imx_clk_frac_pll("gpu_pll", "gpu_pll_ref_div", base + 0x18);
+	clks[IMX8MQ_VPU_PLL] = imx_clk_frac_pll("vpu_pll", "vpu_pll_ref_div", base + 0x20);
+	clks[IMX8MQ_AUDIO_PLL1] = imx_clk_frac_pll("audio_pll1", "audio_pll1_ref_div", base + 0x0);
+	clks[IMX8MQ_AUDIO_PLL2] = imx_clk_frac_pll("audio_pll2", "audio_pll2_ref_div", base + 0x8);
+	clks[IMX8MQ_VIDEO_PLL1] = imx_clk_frac_pll("video_pll1", "video_pll1_ref_div", base + 0x10);
+	clks[IMX8MQ_SYS1_PLL1] = imx_clk_sccg_pll("sys1_pll1", "sys1_pll1_ref_div", base + 0x30, SCCG_PLL1);
+	clks[IMX8MQ_SYS2_PLL1] = imx_clk_sccg_pll("sys2_pll1", "sys2_pll1_ref_div", base + 0x3c, SCCG_PLL1);
+	clks[IMX8MQ_SYS3_PLL1] = imx_clk_sccg_pll("sys3_pll1", "sys3_pll1_ref_div", base + 0x48, SCCG_PLL1);
+	clks[IMX8MQ_DRAM_PLL1] = imx_clk_sccg_pll("dram_pll1", "dram_pll1_ref_div", base + 0x60, SCCG_PLL1);
+	clks[IMX8MQ_VIDEO2_PLL1] = imx_clk_sccg_pll("video2_pll1", "video2_pll1_ref_div", base + 0x5c, 3);
+
+	clks[IMX8MQ_SYS1_PLL2] = imx_clk_sccg_pll("sys1_pll2", "sys1_pll1_out_div", base + 0x30, SCCG_PLL2);
+	clks[IMX8MQ_SYS2_PLL2] = imx_clk_sccg_pll("sys2_pll2", "sys2_pll1_out_div", base + 0x3c, SCCG_PLL2);
+	clks[IMX8MQ_SYS3_PLL2] = imx_clk_sccg_pll("sys3_pll2", "sys3_pll1_out_div", base + 0x48, SCCG_PLL2);
+	clks[IMX8MQ_DRAM_PLL2] = imx_clk_sccg_pll("dram_pll2", "dram_pll1_out_div", base + 0x60, SCCG_PLL2);
+	clks[IMX8MQ_VIDEO2_PLL2] = imx_clk_sccg_pll("video2_pll2", "video2_pll1_out_div", base + 0x54, SCCG_PLL2);
+
+	/* PLL divs */
+	clks[IMX8MQ_SYS1_PLL1_OUT_DIV] = imx_clk_divider("sys1_pll1_out_div", "sys1_pll1_out", base + 0x38, 19, 6);
+	clks[IMX8MQ_SYS2_PLL1_OUT_DIV] = imx_clk_divider("sys2_pll1_out_div", "sys2_pll1_out", base + 0x44, 19, 6);
+	clks[IMX8MQ_SYS3_PLL1_OUT_DIV] = imx_clk_divider("sys3_pll1_out_div", "sys3_pll1_out", base + 0x50, 19, 6);
+	clks[IMX8MQ_DRAM_PLL1_OUT_DIV] = imx_clk_divider("dram_pll1_out_div", "dram_pll1_out", base + 0x68, 19, 6);
+	clks[IMX8MQ_VIDEO2_PLL1_OUT_DIV] = imx_clk_divider("video2_pll1_out_div", "video2_pll1_out", base + 0x5c, 19, 6);
+	clks[IMX8MQ_SYS1_PLL2_DIV] = imx_clk_divider("sys1_pll2_div", "sys1_pll2", base + 0x38, 1, 6);
+	clks[IMX8MQ_SYS2_PLL2_DIV] = imx_clk_divider("sys2_pll2_div", "sys2_pll2", base + 0x44, 1, 6);
+	clks[IMX8MQ_SYS3_PLL2_DIV] = imx_clk_divider("sys3_pll2_div", "sys3_pll2", base + 0x50, 1, 6);
+	clks[IMX8MQ_DRAM_PLL2_DIV] = imx_clk_divider("dram_pll2_div", "dram_pll2", base + 0x68, 1, 6);
+	clks[IMX8MQ_VIDEO2_PLL2_DIV] = imx_clk_divider("video2_pll2_div", "video2_pll2", base + 0x5c, 1, 6);
+
+	/* PLL bypass out */
+	clks[IMX8MQ_ARM_PLL_BYPASS] = imx_clk_mux("arm_pll_bypass", base + 0x28, 14, 1, arm_pll_bypass_sels, ARRAY_SIZE(arm_pll_bypass_sels));
+	clks[IMX8MQ_GPU_PLL_BYPASS] = imx_clk_mux("gpu_pll_bypass", base + 0x18, 14, 1, gpu_pll_bypass_sels, ARRAY_SIZE(gpu_pll_bypass_sels));
+	clks[IMX8MQ_VPU_PLL_BYPASS] = imx_clk_mux("vpu_pll_bypass", base + 0x20, 14, 1, vpu_pll_bypass_sels, ARRAY_SIZE(vpu_pll_bypass_sels));
+	clks[IMX8MQ_AUDIO_PLL1_BYPASS] = imx_clk_mux("audio_pll1_bypass", base + 0x0, 14, 1, audio_pll1_bypass_sels, ARRAY_SIZE(audio_pll1_bypass_sels));
+	clks[IMX8MQ_AUDIO_PLL2_BYPASS] = imx_clk_mux("audio_pll2_bypass", base + 0x8, 14, 1, audio_pll2_bypass_sels, ARRAY_SIZE(audio_pll2_bypass_sels));
+	clks[IMX8MQ_VIDEO_PLL1_BYPASS] = imx_clk_mux("video_pll1_bypass", base + 0x10, 14, 1, video_pll1_bypass_sels, ARRAY_SIZE(video_pll1_bypass_sels));
+
+	clks[IMX8MQ_SYS1_PLL1_OUT] = imx_clk_mux("sys1_pll1_out", base + 0x30, 5, 1, sys1_pll1_out_sels, ARRAY_SIZE(sys1_pll1_out_sels));
+	clks[IMX8MQ_SYS2_PLL1_OUT] = imx_clk_mux("sys2_pll1_out", base + 0x3c, 5, 1, sys2_pll1_out_sels, ARRAY_SIZE(sys2_pll1_out_sels));
+	clks[IMX8MQ_SYS3_PLL1_OUT] = imx_clk_mux("sys3_pll1_out", base + 0x48, 5, 1, sys3_pll1_out_sels, ARRAY_SIZE(sys3_pll1_out_sels));
+	clks[IMX8MQ_DRAM_PLL1_OUT] = imx_clk_mux("dram_pll1_out", base + 0x60, 5, 1, dram_pll1_out_sels, ARRAY_SIZE(dram_pll1_out_sels));
+	clks[IMX8MQ_VIDEO2_PLL1_OUT] = imx_clk_mux("video2_pll1_out", base + 0x54, 5, 1, video2_pll1_out_sels, ARRAY_SIZE(video2_pll1_out_sels));
+	clks[IMX8MQ_SYS1_PLL2_OUT] = imx_clk_mux("sys1_pll2_out", base + 0x30, 4, 1, sys1_pll2_out_sels, ARRAY_SIZE(sys1_pll2_out_sels));
+	clks[IMX8MQ_SYS2_PLL2_OUT] = imx_clk_mux("sys2_pll2_out", base + 0x3c, 4, 1, sys2_pll2_out_sels, ARRAY_SIZE(sys2_pll2_out_sels));
+	clks[IMX8MQ_SYS3_PLL2_OUT] = imx_clk_mux("sys3_pll2_out", base + 0x48, 4, 1, sys3_pll2_out_sels, ARRAY_SIZE(sys3_pll2_out_sels));
+	clks[IMX8MQ_DRAM_PLL2_OUT] = imx_clk_mux("dram_pll2_out", base + 0x60, 4, 1, dram_pll2_out_sels, ARRAY_SIZE(dram_pll2_out_sels));
+	clks[IMX8MQ_VIDEO2_PLL2_OUT] = imx_clk_mux("video2_pll2_out", base + 0x54, 4, 1, video2_pll2_out_sels, ARRAY_SIZE(video2_pll2_out_sels));
+
+	/* unbypass all the plls */
+	clk_set_parent(clks[IMX8MQ_GPU_PLL_BYPASS], clks[IMX8MQ_GPU_PLL]);
+	clk_set_parent(clks[IMX8MQ_VPU_PLL_BYPASS], clks[IMX8MQ_VPU_PLL]);
+	clk_set_parent(clks[IMX8MQ_AUDIO_PLL1_BYPASS], clks[IMX8MQ_AUDIO_PLL1]);
+	clk_set_parent(clks[IMX8MQ_AUDIO_PLL2_BYPASS], clks[IMX8MQ_AUDIO_PLL2]);
+	clk_set_parent(clks[IMX8MQ_VIDEO_PLL1_BYPASS], clks[IMX8MQ_VIDEO_PLL1]);
+	clk_set_parent(clks[IMX8MQ_SYS3_PLL1_OUT], clks[IMX8MQ_SYS3_PLL1]);
+	clk_set_parent(clks[IMX8MQ_SYS3_PLL2_OUT], clks[IMX8MQ_SYS3_PLL2_DIV]);
+
+	/* PLL OUT GATE */
+	clks[IMX8MQ_ARM_PLL_OUT] = imx_clk_gate("arm_pll_out", "arm_pll_bypass", base + 0x28, 21);
+	clks[IMX8MQ_GPU_PLL_OUT] = imx_clk_gate("gpu_pll_out", "gpu_pll_bypass", base + 0x18, 21);
+	clks[IMX8MQ_VPU_PLL_OUT] = imx_clk_gate("vpu_pll_out", "vpu_pll_bypass", base + 0x20, 21);
+	clks[IMX8MQ_AUDIO_PLL1_OUT] = imx_clk_gate("audio_pll1_out", "audio_pll1_bypass", base + 0x0, 21);
+	clks[IMX8MQ_AUDIO_PLL2_OUT] = imx_clk_gate("audio_pll2_out", "audio_pll2_bypass", base + 0x8, 21);
+	clks[IMX8MQ_VIDEO_PLL1_OUT] = imx_clk_gate("video_pll1_out", "video_pll1_bypass", base + 0x10, 21);
+	clks[IMX8MQ_SYS1_PLL_OUT] = imx_clk_gate("sys1_pll_out", "sys1_pll2_out", base + 0x30, 9);
+	clks[IMX8MQ_SYS2_PLL_OUT] = imx_clk_gate("sys2_pll_out", "sys2_pll2_out", base + 0x3c, 9);
+	clks[IMX8MQ_SYS3_PLL_OUT] = imx_clk_gate("sys3_pll_out", "sys3_pll2_out", base + 0x48, 9);
+	clks[IMX8MQ_DRAM_PLL_OUT] = imx_clk_gate("dram_pll_out", "dram_pll2_out", base + 0x60, 9);
+	clks[IMX8MQ_VIDEO2_PLL_OUT] = imx_clk_gate("video2_pll_out", "video2_pll2_out", base + 0x54, 9);
+
+	/* SYS PLL fixed output */
+	clks[IMX8MQ_SYS1_PLL_40M] = imx_clk_fixed_factor("sys1_pll_40m", "sys1_pll_out", 1, 20);
+	clks[IMX8MQ_SYS1_PLL_80M] = imx_clk_fixed_factor("sys1_pll_80m", "sys1_pll_out", 1, 10);
+	clks[IMX8MQ_SYS1_PLL_100M] = imx_clk_fixed_factor("sys1_pll_100m", "sys1_pll_out", 1, 8);
+	clks[IMX8MQ_SYS1_PLL_133M] = imx_clk_fixed_factor("sys1_pll_133m", "sys1_pll_out", 1, 6);
+	clks[IMX8MQ_SYS1_PLL_160M] = imx_clk_fixed_factor("sys1_pll_160m", "sys1_pll_out", 1, 5);
+	clks[IMX8MQ_SYS1_PLL_200M] = imx_clk_fixed_factor("sys1_pll_200m", "sys1_pll_out", 1, 4);
+	clks[IMX8MQ_SYS1_PLL_266M] = imx_clk_fixed_factor("sys1_pll_266m", "sys1_pll_out", 1, 3);
+	clks[IMX8MQ_SYS1_PLL_400M] = imx_clk_fixed_factor("sys1_pll_400m", "sys1_pll_out", 1, 2);
+	clks[IMX8MQ_SYS1_PLL_800M] = imx_clk_fixed_factor("sys1_pll_800m", "sys1_pll_out", 1, 1);
+
+	clks[IMX8MQ_SYS2_PLL_50M] = imx_clk_fixed_factor("sys2_pll_50m", "sys2_pll_out", 1, 20);
+	clks[IMX8MQ_SYS2_PLL_100M] = imx_clk_fixed_factor("sys2_pll_100m", "sys2_pll_out", 1, 10);
+	clks[IMX8MQ_SYS2_PLL_125M] = imx_clk_fixed_factor("sys2_pll_125m", "sys2_pll_out", 1, 8);
+	clks[IMX8MQ_SYS2_PLL_166M] = imx_clk_fixed_factor("sys2_pll_166m", "sys2_pll_out", 1, 6);
+	clks[IMX8MQ_SYS2_PLL_200M] = imx_clk_fixed_factor("sys2_pll_200m", "sys2_pll_out", 1, 5);
+	clks[IMX8MQ_SYS2_PLL_250M] = imx_clk_fixed_factor("sys2_pll_250m", "sys2_pll_out", 1, 4);
+	clks[IMX8MQ_SYS2_PLL_333M] = imx_clk_fixed_factor("sys2_pll_333m", "sys2_pll_out", 1, 3);
+	clks[IMX8MQ_SYS2_PLL_500M] = imx_clk_fixed_factor("sys2_pll_500m", "sys2_pll_out", 1, 2);
+	clks[IMX8MQ_SYS2_PLL_1000M] = imx_clk_fixed_factor("sys2_pll_1000m", "sys2_pll_out", 1, 1);
+
+	np = ccm_node;
+	base = of_iomap(np, 0);
+	WARN_ON(!base);
+	/* CORE */
+	clks[IMX8MQ_CLK_A53_SRC] = imx_clk_mux2("arm_a53_src", base + 0x8000, 24, 3, imx8mq_a53_sels, ARRAY_SIZE(imx8mq_a53_sels));
+	clks[IMX8MQ_CLK_A53_CG] = imx_clk_gate3("arm_a53_cg", "arm_a53_src", base + 0x8000, 28);
+	clks[IMX8MQ_CLK_A53_DIV] = imx_clk_divider2("arm_a53_div", "arm_a53_cg", base + 0x8000, 0, 3);
+
+	/* BUS */
+	clks[IMX8MQ_CLK_MAIN_AXI_SRC] = imx_clk_mux2("main_axi_src", base + 0x8800, 24, 3, imx8mq_main_axi_sels, ARRAY_SIZE(imx8mq_main_axi_sels));
+	clks[IMX8MQ_CLK_ENET_AXI_SRC] = imx_clk_mux2("enet_axi_src", base + 0x8880, 24, 3, imx8mq_enet_axi_sels, ARRAY_SIZE(imx8mq_enet_axi_sels));
+	clks[IMX8MQ_CLK_NAND_USDHC_BUS_SRC] = imx_clk_mux2("nand_usdhc_bus_src", base + 0x8900, 24, 3, imx8mq_nand_usdhc_sels, ARRAY_SIZE(imx8mq_nand_usdhc_sels));
+	clks[IMX8MQ_CLK_USB_BUS_SRC] = imx_clk_mux2("usb_bus_src", base + 0x8b80, 24, 3, imx8mq_usb_bus_sels, ARRAY_SIZE(imx8mq_usb_bus_sels));
+	clks[IMX8MQ_CLK_NOC_SRC] = imx_clk_mux2("noc_src", base + 0x8d00, 24, 3, imx8mq_noc_sels, ARRAY_SIZE(imx8mq_noc_sels));
+	clks[IMX8MQ_CLK_NOC_APB_SRC] = imx_clk_mux2("noc_apb_src", base + 0x8d80, 24, 3, imx8mq_noc_apb_sels, ARRAY_SIZE(imx8mq_noc_apb_sels));
+
+	clks[IMX8MQ_CLK_MAIN_AXI_CG] = imx_clk_gate3("main_axi_cg", "main_axi_src", base + 0x8800, 28);
+	clks[IMX8MQ_CLK_ENET_AXI_CG] = imx_clk_gate3("enet_axi_cg", "enet_axi_src", base + 0x8880, 28);
+	clks[IMX8MQ_CLK_NAND_USDHC_BUS_CG] = imx_clk_gate3("nand_usdhc_bus_cg", "nand_usdhc_bus_src", base + 0x8900, 28);
+	clks[IMX8MQ_CLK_USB_BUS_CG] = imx_clk_gate3("usb_bus_cg", "usb_bus_src", base + 0x8b80, 28);
+	clks[IMX8MQ_CLK_NOC_CG] = imx_clk_gate3("noc_cg", "noc_src", base + 0x8d00, 28);
+	clks[IMX8MQ_CLK_NOC_APB_CG] = imx_clk_gate3("noc_apb_cg", "noc_apb_src", base + 0x8d80, 28);
+
+	clks[IMX8MQ_CLK_MAIN_AXI_PRE_DIV] = imx_clk_divider2("main_axi_pre_div", "main_axi_cg", base + 0x8800, 16, 3);
+	clks[IMX8MQ_CLK_ENET_AXI_PRE_DIV] = imx_clk_divider2("enet_axi_pre_div", "enet_axi_cg", base + 0x8880, 16, 3);
+	clks[IMX8MQ_CLK_NAND_USDHC_BUS_PRE_DIV] = imx_clk_divider2("nand_usdhc_bus_pre_div", "nand_usdhc_bus_cg", base + 0x8900, 16, 3);
+	clks[IMX8MQ_CLK_DISP_AXI_PRE_DIV] = imx_clk_divider2("disp_axi_pre_div", "disp_axi_cg", base + 0x8a00, 16, 3);
+	clks[IMX8MQ_CLK_DISP_APB_PRE_DIV] = imx_clk_divider2("disp_apb_pre_div", "disp_apb_cg", base + 0x8a80, 16, 3);
+	clks[IMX8MQ_CLK_DISP_RTRM_PRE_DIV] = imx_clk_divider2("disp_rtrm_pre_div", "disp_rtrm_cg", base + 0x8b00, 16, 3);
+	clks[IMX8MQ_CLK_USB_BUS_PRE_DIV] = imx_clk_divider2("usb_bus_pre_div", "usb_bus_cg", base + 0x8b80, 16, 3);
+	clks[IMX8MQ_CLK_GPU_AXI_PRE_DIV] = imx_clk_divider2("gpu_axi_pre_div", "gpu_axi_cg", base + 0x8c00, 16, 3);
+	clks[IMX8MQ_CLK_GPU_AHB_PRE_DIV] = imx_clk_divider2("gpu_ahb_pre_div", "gpu_ahb_cg", base + 0x8c80, 16, 3);
+	clks[IMX8MQ_CLK_NOC_PRE_DIV] = imx_clk_divider2("noc_pre_div", "noc_cg", base + 0x8d00, 16, 3);
+	clks[IMX8MQ_CLK_NOC_APB_PRE_DIV] = imx_clk_divider2("noc_apb_pre_div", "noc_apb_cg", base + 0x8d80, 16, 3);
+
+	clks[IMX8MQ_CLK_MAIN_AXI_DIV] = imx_clk_divider2("main_axi_div", "main_axi_pre_div", base + 0x8800, 0, 6);
+	clks[IMX8MQ_CLK_ENET_AXI_DIV] = imx_clk_divider2("enet_axi_div", "enet_axi_pre_div", base + 0x8880, 0, 6);
+	clks[IMX8MQ_CLK_NAND_USDHC_BUS_DIV] = imx_clk_divider2("nand_usdhc_bus_div", "nand_usdhc_bus_pre_div", base + 0x8900, 0, 6);
+	clks[IMX8MQ_CLK_USB_BUS_DIV] = imx_clk_divider2("usb_bus_div", "usb_bus_pre_div", base + 0x8b80, 0, 6);
+	clks[IMX8MQ_CLK_NOC_DIV] = imx_clk_divider2("noc_div", "noc_pre_div", base + 0x8d00, 0, 6);
+	clks[IMX8MQ_CLK_NOC_APB_DIV] = imx_clk_divider2("noc_apb_div", "noc_apb_pre_div", base + 0x8d80, 0, 6);
+
+	/* AHB */
+	clks[IMX8MQ_CLK_AHB_SRC] = imx_clk_mux2("ahb_src", base + 0x9000, 24, 3, imx8mq_ahb_sels, ARRAY_SIZE(imx8mq_ahb_sels));
+	clks[IMX8MQ_CLK_AHB_CG] = imx_clk_gate3("ahb_cg", "ahb_src", base + 0x9000, 28);
+	clks[IMX8MQ_CLK_AHB_PRE_DIV] = imx_clk_divider2("ahb_pre_div", "ahb_cg", base + 0x9000, 16, 3);
+	clks[IMX8MQ_CLK_AHB_DIV] = imx_clk_divider_flags("ahb_div", "ahb_pre_div", base + 0x9000, 0, 6, CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE);
+
+	/* IPG */
+	clks[IMX8MQ_CLK_IPG_ROOT] = imx_clk_divider2("ipg_root", "ahb_div", base + 0x9080, 0, 1);
+
+	/* IP */
+	clks[IMX8MQ_CLK_DRAM_ALT_SRC] = imx_clk_mux2("dram_alt_src", base + 0xa000, 24, 3, imx8mq_dram_alt_sels, ARRAY_SIZE(imx8mq_dram_alt_sels));
+	clks[IMX8MQ_CLK_DRAM_CORE] = imx_clk_mux2("dram_core_clk", base + 0x9800, 24, 1, imx8mq_dram_core_sels, ARRAY_SIZE(imx8mq_dram_core_sels));
+	clks[IMX8MQ_CLK_DRAM_APB_SRC] = imx_clk_mux2("dram_apb_src", base + 0xa080, 24, 3, imx8mq_dram_apb_sels, ARRAY_SIZE(imx8mq_dram_apb_sels));
+	clks[IMX8MQ_CLK_PCIE1_CTRL_SRC] = imx_clk_mux2("pcie1_ctrl_src", base + 0xa300, 24, 3, imx8mq_pcie1_ctrl_sels, ARRAY_SIZE(imx8mq_pcie1_ctrl_sels));
+	clks[IMX8MQ_CLK_PCIE1_PHY_SRC] = imx_clk_mux2("pcie1_phy_src", base + 0xa380, 24, 3, imx8mq_pcie1_phy_sels, ARRAY_SIZE(imx8mq_pcie1_phy_sels));
+	clks[IMX8MQ_CLK_PCIE1_AUX_SRC] = imx_clk_mux2("pcie1_aux_src", base + 0xa400, 24, 3, imx8mq_pcie1_aux_sels, ARRAY_SIZE(imx8mq_pcie1_aux_sels));
+	clks[IMX8MQ_CLK_DC_PIXEL_SRC] = imx_clk_mux2("dc_pixel_src", base + 0xa480, 24, 3, imx8mq_dc_pixel_sels, ARRAY_SIZE(imx8mq_dc_pixel_sels));
+	clks[IMX8MQ_CLK_LCDIF_PIXEL_SRC] = imx_clk_mux2("lcdif_pixel_src", base + 0xa500, 24, 3, imx8mq_lcdif_pixel_sels, ARRAY_SIZE(imx8mq_lcdif_pixel_sels));
+	clks[IMX8MQ_CLK_ENET_REF_SRC] = imx_clk_mux2("enet_ref_src", base + 0xa980, 24, 3, imx8mq_enet_ref_sels, ARRAY_SIZE(imx8mq_enet_ref_sels));
+	clks[IMX8MQ_CLK_ENET_TIMER_SRC] = imx_clk_mux2("enet_timer_src", base + 0xaa00, 24, 3, imx8mq_enet_timer_sels, ARRAY_SIZE(imx8mq_enet_timer_sels));
+	clks[IMX8MQ_CLK_ENET_PHY_REF_SRC] = imx_clk_mux2("enet_phy_src", base + 0xaa80, 24, 3, imx8mq_enet_phy_sels, ARRAY_SIZE(imx8mq_enet_phy_sels));
+	clks[IMX8MQ_CLK_NAND_SRC] = imx_clk_mux2("nand_src", base + 0xab00, 24, 3, imx8mq_nand_sels, ARRAY_SIZE(imx8mq_nand_sels));
+	clks[IMX8MQ_CLK_QSPI_SRC] = imx_clk_mux2("qspi_src", base + 0xab80, 24, 3, imx8mq_qspi_sels, ARRAY_SIZE(imx8mq_qspi_sels));
+	clks[IMX8MQ_CLK_USDHC1_SRC] = imx_clk_mux2("usdhc1_src", base + 0xac00, 24, 3, imx8mq_usdhc1_sels, ARRAY_SIZE(imx8mq_usdhc1_sels));
+	clks[IMX8MQ_CLK_USDHC2_SRC] = imx_clk_mux2("usdhc2_src", base + 0xac80, 24, 3, imx8mq_usdhc2_sels, ARRAY_SIZE(imx8mq_usdhc2_sels));
+	clks[IMX8MQ_CLK_I2C1_SRC] = imx_clk_mux2("i2c1_src", base + 0xad00, 24, 3, imx8mq_i2c1_sels, ARRAY_SIZE(imx8mq_i2c1_sels));
+	clks[IMX8MQ_CLK_I2C2_SRC] = imx_clk_mux2("i2c2_src", base + 0xad80, 24, 3, imx8mq_i2c2_sels, ARRAY_SIZE(imx8mq_i2c2_sels));
+	clks[IMX8MQ_CLK_I2C3_SRC] = imx_clk_mux2("i2c3_src", base + 0xae00, 24, 3, imx8mq_i2c3_sels, ARRAY_SIZE(imx8mq_i2c3_sels));
+	clks[IMX8MQ_CLK_I2C4_SRC] = imx_clk_mux2("i2c4_src", base + 0xae80, 24, 3, imx8mq_i2c4_sels, ARRAY_SIZE(imx8mq_i2c4_sels));
+	clks[IMX8MQ_CLK_UART1_SRC] = imx_clk_mux2("uart1_src", base + 0xaf00, 24, 3, imx8mq_uart1_sels, ARRAY_SIZE(imx8mq_uart1_sels));
+	clks[IMX8MQ_CLK_UART2_SRC] = imx_clk_mux2("uart2_src", base + 0xaf80, 24, 3, imx8mq_uart2_sels, ARRAY_SIZE(imx8mq_uart2_sels));
+	clks[IMX8MQ_CLK_UART3_SRC] = imx_clk_mux2("uart3_src", base + 0xb000, 24, 3, imx8mq_uart3_sels, ARRAY_SIZE(imx8mq_uart3_sels));
+	clks[IMX8MQ_CLK_UART4_SRC] = imx_clk_mux2("uart4_src", base + 0xb080, 24, 3, imx8mq_uart4_sels, ARRAY_SIZE(imx8mq_uart4_sels));
+	clks[IMX8MQ_CLK_USB_CORE_REF_SRC] = imx_clk_mux2("usb_core_ref_src", base + 0xb100, 24, 3, imx8mq_usb_core_sels, ARRAY_SIZE(imx8mq_usb_core_sels));
+	clks[IMX8MQ_CLK_USB_PHY_REF_SRC] = imx_clk_mux2("usb_phy_ref_src", base + 0xb180, 24, 3, imx8mq_usb_phy_sels, ARRAY_SIZE(imx8mq_usb_phy_sels));
+	clks[IMX8MQ_CLK_ECSPI1_SRC] = imx_clk_mux2("ecspi1_src", base + 0xb280, 24, 3, imx8mq_ecspi1_sels, ARRAY_SIZE(imx8mq_ecspi1_sels));
+	clks[IMX8MQ_CLK_ECSPI2_SRC] = imx_clk_mux2("ecspi2_src", base + 0xb300, 24, 3, imx8mq_ecspi2_sels, ARRAY_SIZE(imx8mq_ecspi2_sels));
+	clks[IMX8MQ_CLK_PWM1_SRC] = imx_clk_mux2("pwm1_src", base + 0xb380, 24, 3, imx8mq_pwm1_sels, ARRAY_SIZE(imx8mq_pwm1_sels));
+	clks[IMX8MQ_CLK_PWM2_SRC] = imx_clk_mux2("pwm2_src", base + 0xb400, 24, 3, imx8mq_pwm2_sels, ARRAY_SIZE(imx8mq_pwm2_sels));
+	clks[IMX8MQ_CLK_PWM3_SRC] = imx_clk_mux2("pwm3_src", base + 0xb480, 24, 3, imx8mq_pwm3_sels, ARRAY_SIZE(imx8mq_pwm3_sels));
+	clks[IMX8MQ_CLK_PWM4_SRC] = imx_clk_mux2("pwm4_src", base + 0xb500, 24, 3, imx8mq_pwm4_sels, ARRAY_SIZE(imx8mq_pwm4_sels));
+	clks[IMX8MQ_CLK_GPT1_SRC] = imx_clk_mux2("gpt1_src", base + 0xb580, 24, 3, imx8mq_gpt1_sels, ARRAY_SIZE(imx8mq_gpt1_sels));
+	clks[IMX8MQ_CLK_WDOG_SRC] = imx_clk_mux2("wdog_src", base + 0xb900, 24, 3, imx8mq_wdog_sels, ARRAY_SIZE(imx8mq_wdog_sels));
+	clks[IMX8MQ_CLK_WRCLK_SRC] = imx_clk_mux2("wrclk_src", base + 0xb980, 24, 3, imx8mq_wrclk_sels, ARRAY_SIZE(imx8mq_wrclk_sels));
+	clks[IMX8MQ_CLK_CLKO2_SRC] = imx_clk_mux2("clko2_src", base + 0xba80, 24, 3, imx8mq_clko2_sels, ARRAY_SIZE(imx8mq_clko2_sels));
+	clks[IMX8MQ_CLK_PCIE2_CTRL_SRC] = imx_clk_mux2("pcie2_ctrl_src", base + 0xc000, 24, 3, imx8mq_pcie2_ctrl_sels, ARRAY_SIZE(imx8mq_pcie2_ctrl_sels));
+	clks[IMX8MQ_CLK_PCIE2_PHY_SRC] = imx_clk_mux2("pcie2_phy_src", base + 0xc080, 24, 3, imx8mq_pcie2_phy_sels, ARRAY_SIZE(imx8mq_pcie2_phy_sels));
+	clks[IMX8MQ_CLK_PCIE2_AUX_SRC] = imx_clk_mux2("pcie2_aux_src", base + 0xc100, 24, 3, imx8mq_pcie2_aux_sels, ARRAY_SIZE(imx8mq_pcie2_aux_sels));
+	clks[IMX8MQ_CLK_ECSPI3_SRC] = imx_clk_mux2("ecspi3_src", base + 0xc180, 24, 3, imx8mq_ecspi3_sels, ARRAY_SIZE(imx8mq_ecspi3_sels));
+
+	clks[IMX8MQ_CLK_DRAM_ALT_CG] = imx_clk_gate3("dram_alt_cg", "dram_alt_src", base + 0xa000, 28);
+	clks[IMX8MQ_CLK_DRAM_APB_CG] = imx_clk_gate3("dram_apb_cg", "dram_apb_src", base + 0xa080, 28);
+	clks[IMX8MQ_CLK_PCIE1_CTRL_CG] = imx_clk_gate3("pcie1_ctrl_cg", "pcie1_ctrl_src", base + 0xa300, 28);
+	clks[IMX8MQ_CLK_PCIE1_PHY_CG] = imx_clk_gate3("pcie1_phy_cg", "pcie1_phy_src", base + 0xa380, 28);
+	clks[IMX8MQ_CLK_PCIE1_AUX_CG] = imx_clk_gate3("pcie1_aux_cg", "pcie1_aux_src", base + 0xa400, 28);
+	clks[IMX8MQ_CLK_ENET_REF_CG] = imx_clk_gate3("enet_ref_cg", "enet_ref_src", base + 0xa980, 28);
+	clks[IMX8MQ_CLK_ENET_TIMER_CG] = imx_clk_gate3("enet_timer_cg", "enet_timer_src", base + 0xaa00, 28);
+	clks[IMX8MQ_CLK_ENET_PHY_REF_CG] = imx_clk_gate3("enet_phy_cg", "enet_phy_src", base + 0xaa80, 28);
+	clks[IMX8MQ_CLK_NAND_CG] = imx_clk_gate3("nand_cg", "nand_src", base + 0xab00, 28);
+	clks[IMX8MQ_CLK_QSPI_CG] = imx_clk_gate3("qspi_cg", "qspi_src", base + 0xab80, 28);
+	clks[IMX8MQ_CLK_USDHC1_CG] = imx_clk_gate3("usdhc1_cg", "usdhc1_src", base + 0xac00, 28);
+	clks[IMX8MQ_CLK_USDHC2_CG] = imx_clk_gate3("usdhc2_cg", "usdhc2_src", base + 0xac80, 28);
+	clks[IMX8MQ_CLK_I2C1_CG] = imx_clk_gate3("i2c1_cg", "i2c1_src", base + 0xad00, 28);
+	clks[IMX8MQ_CLK_I2C2_CG] = imx_clk_gate3("i2c2_cg", "i2c2_src", base + 0xad80, 28);
+	clks[IMX8MQ_CLK_I2C3_CG] = imx_clk_gate3("i2c3_cg", "i2c3_src", base + 0xae00, 28);
+	clks[IMX8MQ_CLK_I2C4_CG] = imx_clk_gate3("i2c4_cg", "i2c4_src", base + 0xae80, 28);
+	clks[IMX8MQ_CLK_UART1_CG] = imx_clk_gate3("uart1_cg", "uart1_src", base + 0xaf00, 28);
+	clks[IMX8MQ_CLK_UART2_CG] = imx_clk_gate3("uart2_cg", "uart2_src", base + 0xaf80, 28);
+	clks[IMX8MQ_CLK_UART3_CG] = imx_clk_gate3("uart3_cg", "uart3_src", base + 0xb000, 28);
+	clks[IMX8MQ_CLK_UART4_CG] = imx_clk_gate3("uart4_cg", "uart4_src", base + 0xb080, 28);
+	clks[IMX8MQ_CLK_USB_CORE_REF_CG] = imx_clk_gate3("usb_core_ref_cg", "usb_core_ref_src", base + 0xb100, 28);
+	clks[IMX8MQ_CLK_USB_PHY_REF_CG] = imx_clk_gate3("usb_phy_ref_cg", "usb_phy_ref_src", base + 0xb180, 28);
+	clks[IMX8MQ_CLK_ECSPI1_CG] = imx_clk_gate3("ecspi1_cg", "ecspi1_src",  base + 0xb280, 28);
+	clks[IMX8MQ_CLK_ECSPI2_CG] = imx_clk_gate3("ecspi2_cg", "ecspi2_src", base + 0xb300, 28);
+	clks[IMX8MQ_CLK_PWM1_CG] = imx_clk_gate3("pwm1_cg", "pwm1_src", base + 0xb380, 28);
+	clks[IMX8MQ_CLK_PWM2_CG] = imx_clk_gate3("pwm2_cg", "pwm2_src", base + 0xb400, 28);
+	clks[IMX8MQ_CLK_PWM3_CG] = imx_clk_gate3("pwm3_cg", "pwm3_src", base + 0xb480, 28);
+	clks[IMX8MQ_CLK_PWM4_CG] = imx_clk_gate3("pwm4_cg", "pwm4_src", base + 0xb500, 28);
+	clks[IMX8MQ_CLK_GPT1_CG] = imx_clk_gate3("gpt1_cg", "gpt1_src", base + 0xb580, 28);
+	clks[IMX8MQ_CLK_WDOG_CG] = imx_clk_gate3("wdog_cg", "wdog_src", base + 0xb900, 28);
+	clks[IMX8MQ_CLK_WRCLK_CG] = imx_clk_gate3("wrclk_cg", "wrclk_src", base + 0xb980, 28);
+	clks[IMX8MQ_CLK_CLKO2_CG] = imx_clk_gate3("clko2_cg", "clko2_src", base + 0xba80, 28);
+	clks[IMX8MQ_CLK_PCIE2_CTRL_CG] = imx_clk_gate3("pcie2_ctrl_cg", "pcie2_ctrl_src", base + 0xc000, 28);
+	clks[IMX8MQ_CLK_PCIE2_PHY_CG] = imx_clk_gate3("pcie2_phy_cg", "pcie2_phy_src", base + 0xc080, 28);
+	clks[IMX8MQ_CLK_PCIE2_AUX_CG] = imx_clk_gate3("pcie2_aux_cg", "pcie2_aux_src", base + 0xc100, 28);
+	clks[IMX8MQ_CLK_ECSPI3_CG] = imx_clk_gate3("ecspi3_cg", "ecspi3_src", base + 0xc180, 28);
+
+	clks[IMX8MQ_CLK_DRAM_ALT_PRE_DIV] = imx_clk_divider2("dram_alt_pre_div", "dram_alt_cg", base + 0xa000, 16, 3);
+	clks[IMX8MQ_CLK_DRAM_APB_PRE_DIV] = imx_clk_divider_flags("dram_apb_pre_div", "dram_apb_cg", base + 0xa080, 16, 3, CLK_OPS_PARENT_ENABLE);
+	clks[IMX8MQ_CLK_PCIE1_CTRL_PRE_DIV] = imx_clk_divider2("pcie1_ctrl_pre_div", "pcie1_ctrl_cg", base + 0xa300, 16, 3);
+	clks[IMX8MQ_CLK_PCIE1_PHY_PRE_DIV] = imx_clk_divider2("pcie1_phy_pre_div", "pcie1_phy_cg", base + 0xa380, 16, 3);
+	clks[IMX8MQ_CLK_PCIE1_AUX_PRE_DIV] = imx_clk_divider2("pcie1_aux_pre_div", "pcie1_aux_cg", base + 0xa400, 16, 3);
+	clks[IMX8MQ_CLK_DC_PIXEL_PRE_DIV] = imx_clk_divider2("dc_pixel_pre_div", "dc_pixel_cg", base + 0xa480, 16, 3);
+	clks[IMX8MQ_CLK_LCDIF_PIXEL_PRE_DIV] = imx_clk_divider2("lcdif_pixel_pre_div", "lcdif_pixel_cg", base + 0xa500, 16, 3);
+	clks[IMX8MQ_CLK_SPDIF1_PRE_DIV] = imx_clk_divider2("spdif1_pre_div", "spdif1_cg", base + 0xa880, 16, 3);
+	clks[IMX8MQ_CLK_SPDIF2_PRE_DIV] = imx_clk_divider2("spdif2_pre_div", "spdif2_cg", base + 0xa900, 16, 3);
+	clks[IMX8MQ_CLK_ENET_REF_PRE_DIV] = imx_clk_divider2("enet_ref_pre_div", "enet_ref_cg", base + 0xa980, 16, 3);
+	clks[IMX8MQ_CLK_ENET_TIMER_PRE_DIV] = imx_clk_divider2("enet_timer_pre_div", "enet_timer_cg", base + 0xaa00, 16, 3);
+	clks[IMX8MQ_CLK_ENET_PHY_REF_PRE_DIV] = imx_clk_divider2("enet_phy_pre_div", "enet_phy_cg", base + 0xaa80, 16, 3);
+	clks[IMX8MQ_CLK_NAND_PRE_DIV] = imx_clk_divider2("nand_pre_div", "nand_cg", base + 0xab00, 16, 3);
+	clks[IMX8MQ_CLK_QSPI_PRE_DIV] = imx_clk_divider2("qspi_pre_div", "qspi_cg", base + 0xab80, 16, 3);
+	clks[IMX8MQ_CLK_USDHC1_PRE_DIV] = imx_clk_divider2("usdhc1_pre_div", "usdhc1_cg", base + 0xac00, 16, 3);
+	clks[IMX8MQ_CLK_USDHC2_PRE_DIV] = imx_clk_divider2("usdhc2_pre_div", "usdhc2_cg", base + 0xac80, 16, 3);
+	clks[IMX8MQ_CLK_I2C1_PRE_DIV] = imx_clk_divider2("i2c1_pre_div", "i2c1_cg", base + 0xad00, 16, 3);
+	clks[IMX8MQ_CLK_I2C2_PRE_DIV] = imx_clk_divider2("i2c2_pre_div", "i2c2_cg", base + 0xad80, 16, 3);
+	clks[IMX8MQ_CLK_I2C3_PRE_DIV] = imx_clk_divider2("i2c3_pre_div", "i2c3_cg", base + 0xae00, 16, 3);
+	clks[IMX8MQ_CLK_I2C4_PRE_DIV] = imx_clk_divider2("i2c4_pre_div", "i2c4_cg", base + 0xae80, 16, 3);
+	clks[IMX8MQ_CLK_UART1_PRE_DIV] = imx_clk_divider2("uart1_pre_div", "uart1_cg", base + 0xaf00, 16, 3);
+	clks[IMX8MQ_CLK_UART2_PRE_DIV] = imx_clk_divider2("uart2_pre_div", "uart2_cg", base + 0xaf80, 16, 3);
+	clks[IMX8MQ_CLK_UART3_PRE_DIV] = imx_clk_divider2("uart3_pre_div", "uart3_cg", base + 0xb000, 16, 3);
+	clks[IMX8MQ_CLK_UART4_PRE_DIV] = imx_clk_divider2("uart4_pre_div", "uart4_cg", base + 0xb080, 16, 3);
+	clks[IMX8MQ_CLK_USB_CORE_REF_PRE_DIV] = imx_clk_divider2("usb_core_ref_pre_div", "usb_core_ref_cg", base + 0xb100, 16, 3);
+	clks[IMX8MQ_CLK_USB_PHY_REF_PRE_DIV] = imx_clk_divider2("usb_phy_ref_pre_div", "usb_phy_ref_cg", base + 0xb180, 16, 3);
+	clks[IMX8MQ_CLK_ECSPI1_PRE_DIV] = imx_clk_divider2("ecspi1_pre_div", "ecspi1_cg", base + 0xb280, 16, 3);
+	clks[IMX8MQ_CLK_ECSPI2_PRE_DIV] = imx_clk_divider2("ecspi2_pre_div", "ecspi2_cg", base + 0xb300, 16, 3);
+	clks[IMX8MQ_CLK_PWM1_PRE_DIV] = imx_clk_divider2("pwm1_pre_div", "pwm1_cg", base + 0xb380, 16, 3);
+	clks[IMX8MQ_CLK_PWM2_PRE_DIV] = imx_clk_divider2("pwm2_pre_div", "pwm2_cg", base + 0xb400, 16, 3);
+	clks[IMX8MQ_CLK_PWM3_PRE_DIV] = imx_clk_divider2("pwm3_pre_div", "pwm3_cg", base + 0xb480, 16, 3);
+	clks[IMX8MQ_CLK_PWM4_PRE_DIV] = imx_clk_divider2("pwm4_pre_div", "pwm4_cg", base + 0xb500, 16, 3);
+	clks[IMX8MQ_CLK_GPT1_PRE_DIV] = imx_clk_divider2("gpt1_pre_div", "gpt1_cg", base + 0xb580, 16, 3);
+	clks[IMX8MQ_CLK_WDOG_PRE_DIV] = imx_clk_divider2("wdog_pre_div", "wdog_cg", base + 0xb900, 16, 3);
+	clks[IMX8MQ_CLK_WRCLK_PRE_DIV] = imx_clk_divider2("wrclk_pre_div", "wrclk_cg", base + 0xb980, 16, 3);
+	clks[IMX8MQ_CLK_CLKO2_PRE_DIV] = imx_clk_divider2("clko2_pre_div", "clko2_cg", base + 0xba80, 16, 3);
+	clks[IMX8MQ_CLK_PCIE2_CTRL_PRE_DIV] = imx_clk_divider2("pcie2_ctrl_pre_div", "pcie2_ctrl_cg", base + 0xc000, 16, 3);
+	clks[IMX8MQ_CLK_PCIE2_PHY_PRE_DIV] = imx_clk_divider2("pcie2_phy_pre_div", "pcie2_phy_cg", base + 0xc080, 16, 3);
+	clks[IMX8MQ_CLK_PCIE2_AUX_PRE_DIV] = imx_clk_divider2("pcie2_aux_pre_div", "pcie2_aux_cg", base + 0xc100, 16, 3);
+	clks[IMX8MQ_CLK_ECSPI3_PRE_DIV] = imx_clk_divider2("ecspi3_pre_div", "ecspi3_cg", base + 0xc180, 16, 3);
+
+	clks[IMX8MQ_CLK_DRAM_ALT_DIV] = imx_clk_divider2("dram_alt_div", "dram_alt_pre_div", base + 0xa000, 0, 6);
+	clks[IMX8MQ_CLK_DRAM_APB_DIV] = imx_clk_divider2("dram_apb_div", "dram_apb_pre_div", base + 0xa080, 0, 6);
+	clks[IMX8MQ_CLK_PCIE1_CTRL_DIV] = imx_clk_divider2("pcie1_ctrl_div", "pcie1_ctrl_pre_div", base + 0xa300, 0, 6);
+	clks[IMX8MQ_CLK_PCIE1_PHY_DIV] = imx_clk_divider2("pcie1_phy_div", "pcie1_phy_pre_div", base + 0xa380, 0, 6);
+	clks[IMX8MQ_CLK_PCIE1_AUX_DIV] = imx_clk_divider2("pcie1_aux_div", "pcie1_aux_pre_div", base + 0xa400, 0, 6);
+	clks[IMX8MQ_CLK_DC_PIXEL_DIV] = imx_clk_divider2("dc_pixel_div", "dc_pixel_pre_div", base + 0xa480, 0, 6);
+	clks[IMX8MQ_CLK_LCDIF_PIXEL_DIV] = imx_clk_divider2("lcdif_pixel_div", "lcdif_pixel_pre_div", base + 0xa500, 0, 6);
+	clks[IMX8MQ_CLK_ENET_REF_DIV] = imx_clk_divider2("enet_ref_div", "enet_ref_pre_div", base + 0xa980, 0, 6);
+	clks[IMX8MQ_CLK_ENET_TIMER_DIV] = imx_clk_divider2("enet_timer_div", "enet_timer_pre_div", base + 0xaa00, 0, 6);
+	clks[IMX8MQ_CLK_ENET_PHY_REF_DIV] = imx_clk_divider2("enet_phy_div", "enet_phy_pre_div", base + 0xaa80, 0, 6);
+	clks[IMX8MQ_CLK_NAND_DIV] = imx_clk_divider2("nand_div", "nand_pre_div", base + 0xab00, 0, 6);
+	clks[IMX8MQ_CLK_QSPI_DIV] = imx_clk_divider2("qspi_div", "qspi_pre_div", base + 0xab80, 0, 6);
+	clks[IMX8MQ_CLK_USDHC1_DIV] = imx_clk_divider2("usdhc1_div", "usdhc1_pre_div", base + 0xac00, 0, 6);
+	clks[IMX8MQ_CLK_USDHC2_DIV] = imx_clk_divider2("usdhc2_div", "usdhc2_pre_div", base + 0xac80, 0, 6);
+	clks[IMX8MQ_CLK_I2C1_DIV] = imx_clk_divider2("i2c1_div", "i2c1_pre_div", base + 0xad00, 0, 6);
+	clks[IMX8MQ_CLK_I2C2_DIV] = imx_clk_divider2("i2c2_div", "i2c2_pre_div", base + 0xad80, 0, 6);
+	clks[IMX8MQ_CLK_I2C3_DIV] = imx_clk_divider2("i2c3_div", "i2c3_pre_div", base + 0xae00, 0, 6);
+	clks[IMX8MQ_CLK_I2C4_DIV] = imx_clk_divider2("i2c4_div", "i2c4_pre_div", base + 0xae80, 0, 6);
+	clks[IMX8MQ_CLK_UART1_DIV] = imx_clk_divider2("uart1_div", "uart1_pre_div", base + 0xaf00, 0, 6);
+	clks[IMX8MQ_CLK_UART2_DIV] = imx_clk_divider2("uart2_div", "uart2_pre_div", base + 0xaf80, 0, 6);
+	clks[IMX8MQ_CLK_UART3_DIV] = imx_clk_divider2("uart3_div", "uart3_pre_div", base + 0xb000, 0, 6);
+	clks[IMX8MQ_CLK_UART4_DIV] = imx_clk_divider2("uart4_div", "uart4_pre_div", base + 0xb080, 0, 6);
+	clks[IMX8MQ_CLK_USB_CORE_REF_DIV] = imx_clk_divider2("usb_core_ref_div", "usb_core_ref_pre_div", base + 0xb100, 0, 6);
+	clks[IMX8MQ_CLK_USB_PHY_REF_DIV] = imx_clk_divider2("usb_phy_ref_div", "usb_phy_ref_pre_div", base + 0xb180, 0, 6);
+	clks[IMX8MQ_CLK_ECSPI1_DIV] = imx_clk_divider2("ecspi1_div", "ecspi1_pre_div", base + 0xb280, 0, 6);
+	clks[IMX8MQ_CLK_ECSPI2_DIV] = imx_clk_divider2("ecspi2_div", "ecspi2_pre_div", base + 0xb300, 0, 6);
+	clks[IMX8MQ_CLK_PWM1_DIV] = imx_clk_divider2("pwm1_div", "pwm1_pre_div", base + 0xb380, 0, 6);
+	clks[IMX8MQ_CLK_PWM2_DIV] = imx_clk_divider2("pwm2_div", "pwm2_pre_div", base + 0xb400, 0, 6);
+	clks[IMX8MQ_CLK_PWM3_DIV] = imx_clk_divider2("pwm3_div", "pwm3_pre_div", base + 0xb480, 0, 6);
+	clks[IMX8MQ_CLK_PWM4_DIV] = imx_clk_divider2("pwm4_div", "pwm4_pre_div", base + 0xb500, 0, 6);
+	clks[IMX8MQ_CLK_GPT1_DIV] = imx_clk_divider2("gpt1_div", "gpt1_pre_div", base + 0xb580, 0, 6);
+	clks[IMX8MQ_CLK_WDOG_DIV] = imx_clk_divider2("wdog_div", "wdog_pre_div", base + 0xb900, 0, 6);
+	clks[IMX8MQ_CLK_WRCLK_DIV] = imx_clk_divider2("wrclk_div", "wrclk_pre_div", base + 0xb980, 0, 6);
+	clks[IMX8MQ_CLK_CLKO2_DIV] = imx_clk_divider2("clko2_div", "clko2_pre_div", base + 0xba80, 0, 6);
+	clks[IMX8MQ_CLK_PCIE2_CTRL_DIV] = imx_clk_divider2("pcie2_ctrl_div", "pcie2_ctrl_pre_div", base + 0xc000, 0, 6);
+	clks[IMX8MQ_CLK_PCIE2_PHY_DIV] = imx_clk_divider2("pcie2_phy_div", "pcie2_phy_pre_div", base + 0xc080, 0, 6);
+	clks[IMX8MQ_CLK_PCIE2_AUX_DIV] = imx_clk_divider2("pcie2_aux_div", "pcie2_aux_pre_div", base + 0xc100, 0, 6);
+	clks[IMX8MQ_CLK_ECSPI3_DIV] = imx_clk_divider2("ecspi3_div", "ecspi3_pre_div", base + 0xc180, 0, 6);
+
+	/*FIXME, the doc is not ready now */
+	clks[IMX8MQ_CLK_ECSPI1_ROOT] = imx_clk_gate4("ecspi1_root_clk", "ecspi1_div", base + 0x4070, 0);
+	clks[IMX8MQ_CLK_ECSPI2_ROOT] = imx_clk_gate4("ecspi2_root_clk", "ecspi2_div", base + 0x4080, 0);
+	clks[IMX8MQ_CLK_ECSPI3_ROOT] = imx_clk_gate4("ecspi3_root_clk", "ecspi3_div", base + 0x4090, 0);
+	clks[IMX8MQ_CLK_ENET1_ROOT] = imx_clk_gate4("enet1_root_clk", "enet_axi_div", base + 0x40a0, 0);
+	clks[IMX8MQ_CLK_GPT1_ROOT] = imx_clk_gate4("gpt1_root_clk", "gpt1_div", base + 0x4100, 0);
+	clks[IMX8MQ_CLK_I2C1_ROOT] = imx_clk_gate4("i2c1_root_clk", "i2c1_div", base + 0x4170, 0);
+	clks[IMX8MQ_CLK_I2C2_ROOT] = imx_clk_gate4("i2c2_root_clk", "i2c2_div", base + 0x4180, 0);
+	clks[IMX8MQ_CLK_I2C3_ROOT] = imx_clk_gate4("i2c3_root_clk", "i2c3_div", base + 0x4190, 0);
+	clks[IMX8MQ_CLK_I2C4_ROOT] = imx_clk_gate4("i2c4_root_clk", "i2c4_div", base + 0x41a0, 0);
+	clks[IMX8MQ_CLK_MU_ROOT] = imx_clk_gate4("mu_root_clk", "ipg_root", base + 0x4210, 0);
+	clks[IMX8MQ_CLK_OCOTP_ROOT] = imx_clk_gate4("ocotp_root_clk", "ipg_root", base + 0x4220, 0);
+	clks[IMX8MQ_CLK_PCIE1_ROOT] = imx_clk_gate4("pcie1_root_clk", "pcie1_ctrl_div", base + 0x4250, 0);
+	clks[IMX8MQ_CLK_PCIE2_ROOT] = imx_clk_gate4("pcie2_root_clk", "pcie2_ctrl_div", base + 0x4640, 0);
+	clks[IMX8MQ_CLK_PWM1_ROOT] = imx_clk_gate4("pwm1_root_clk", "pwm1_div", base + 0x4280, 0);
+	clks[IMX8MQ_CLK_PWM2_ROOT] = imx_clk_gate4("pwm2_root_clk", "pwm2_div", base + 0x4290, 0);
+	clks[IMX8MQ_CLK_PWM3_ROOT] = imx_clk_gate4("pwm3_root_clk", "pwm3_div", base + 0x42a0, 0);
+	clks[IMX8MQ_CLK_PWM4_ROOT] = imx_clk_gate4("pwm4_root_clk", "pwm4_div", base + 0x42b0, 0);
+	clks[IMX8MQ_CLK_QSPI_ROOT] = imx_clk_gate4("qspi_root_clk", "qspi_div", base + 0x42f0, 0);
+	clks[IMX8MQ_CLK_RAWNAND_ROOT] = imx_clk_gate4("nand_root_clk", "nand_div", base + 0x4300, 0);
+	clks[IMX8MQ_CLK_NAND_USDHC_BUS_RAWNAND_CLK] = imx_clk_gate_shared("nand_usdhc_rawnand_clk", "nand_usdhc_bus_div", "nand_root_clk");
+	clks[IMX8MQ_CLK_UART1_ROOT] = imx_clk_gate4("uart1_root_clk", "uart1_div", base + 0x4490, 0);
+	clks[IMX8MQ_CLK_UART2_ROOT] = imx_clk_gate4("uart2_root_clk", "uart2_div", base + 0x44a0, 0);
+	clks[IMX8MQ_CLK_UART3_ROOT] = imx_clk_gate4("uart3_root_clk", "uart3_div", base + 0x44b0, 0);
+	clks[IMX8MQ_CLK_UART4_ROOT] = imx_clk_gate4("uart4_root_clk", "uart4_div", base + 0x44c0, 0);
+	clks[IMX8MQ_CLK_USB1_CTRL_ROOT] = imx_clk_gate4("usb1_ctrl_root_clk", "usb_core_ref_div", base + 0x44d0, 0);
+	clks[IMX8MQ_CLK_USB2_CTRL_ROOT] = imx_clk_gate4("usb2_ctrl_root_clk", "usb_core_ref_div", base + 0x44e0, 0);
+	clks[IMX8MQ_CLK_USB1_PHY_ROOT] = imx_clk_gate4("usb1_phy_root_clk", "usb_phy_ref_div", base + 0x44f0, 0);
+	clks[IMX8MQ_CLK_USB2_PHY_ROOT] = imx_clk_gate4("usb2_phy_root_clk", "usb_phy_ref_div", base + 0x4500, 0);
+	clks[IMX8MQ_CLK_USDHC1_ROOT] = imx_clk_gate4("usdhc1_root_clk", "usdhc1_div", base + 0x4510, 0);
+	clks[IMX8MQ_CLK_USDHC2_ROOT] = imx_clk_gate4("usdhc2_root_clk", "usdhc2_div", base + 0x4520, 0);
+	clks[IMX8MQ_CLK_WDOG1_ROOT] = imx_clk_gate4("wdog1_root_clk", "wdog_div", base + 0x4530, 0);
+	clks[IMX8MQ_CLK_WDOG2_ROOT] = imx_clk_gate4("wdog2_root_clk", "wdog_div", base + 0x4540, 0);
+	clks[IMX8MQ_CLK_WDOG3_ROOT] = imx_clk_gate4("wdog3_root_clk", "wdog_div", base + 0x4550, 0);
+
+	clks[IMX8MQ_GPT_3M_CLK] = imx_clk_fixed_factor("gpt_3m", "osc_25m", 1, 8);
+	clks[IMX8MQ_CLK_DRAM_ALT_ROOT] = imx_clk_fixed_factor("dram_alt_root", "dram_alt_div", 1, 4);
+
+	for (i = 0; i < IMX8MQ_CLK_END; i++)
+		if (IS_ERR(clks[i]))
+			pr_err("i.MX8mq clk %u register failed with %ld\n",
+			       i, PTR_ERR(clks[i]));
+
+	clk_data.clks = clks;
+	clk_data.clk_num = ARRAY_SIZE(clks);
+	of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
+}
+
+CLK_OF_DECLARE(imx8mq, "fsl,imx8mq-ccm", imx8mq_clocks_init);
diff --git a/drivers/clk/imx/clk-sccg-pll.c b/drivers/clk/imx/clk-sccg-pll.c
new file mode 100644
index 0000000000..951234367b
--- /dev/null
+++ b/drivers/clk/imx/clk-sccg-pll.c
@@ -0,0 +1,242 @@
+/*
+ * Copyright 2017 NXP.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <common.h>
+#include <init.h>
+#include <driver.h>
+#include <linux/clk.h>
+#include <io.h>
+#include <linux/clkdev.h>
+#include <linux/err.h>
+#include <malloc.h>
+#include <clock.h>
+#include <asm-generic/div64.h>
+
+#include "clk.h"
+
+/* PLL CFGs */
+#define PLL_CFG0	0x0
+#define PLL_CFG1	0x4
+#define PLL_CFG2	0x8
+
+#define PLL_DIVF1_SHIFT	13
+#define PLL_DIVF2_SHIFT	7
+#define PLL_DIVF_MASK	0x3f
+
+#define PLL_DIVR1_SHIFT	25
+#define PLL_DIVR2_SHIFT	19
+#define PLL_DIVR1_MASK	0x3
+#define PLL_DIVR2_MASK	0x3f
+#define PLL_REF_SHIFT	0
+#define PLL_REF_MASK	0x3
+
+#define PLL_LOCK	31
+#define PLL_PD		7
+
+#define OSC_25M		25000000
+#define OSC_27M		27000000
+
+struct clk_sccg_pll {
+	struct clk	clk;
+	void __iomem	*base;
+	const char	*parent;
+};
+
+#define to_clk_sccg_pll(_clk) container_of(_clk, struct clk_sccg_pll, clk)
+
+static int clk_pll1_is_prepared(struct clk *clk)
+{
+	struct clk_sccg_pll *pll = to_clk_sccg_pll(clk);
+	u32 val;
+
+	val = readl(pll->base + PLL_CFG0);
+	return (val & (1 << PLL_PD)) ? 0 : 1;
+}
+
+static unsigned long clk_pll1_recalc_rate(struct clk *clk,
+					 unsigned long parent_rate)
+{
+	struct clk_sccg_pll *pll = to_clk_sccg_pll(clk);
+	u32 val, divf;
+
+	val = readl(pll->base + PLL_CFG2);
+	divf = (val >> PLL_DIVF1_SHIFT) & PLL_DIVF_MASK;
+
+	return parent_rate * 2 * (divf + 1);
+}
+
+static long clk_pll1_round_rate(struct clk *clk, unsigned long rate,
+			       unsigned long *prate)
+{
+	unsigned long parent_rate = *prate;
+	u32 div;
+
+	div = rate / (parent_rate * 2);
+
+	return parent_rate * div * 2;
+}
+
+static int clk_pll1_set_rate(struct clk *clk, unsigned long rate,
+			    unsigned long parent_rate)
+{
+	struct clk_sccg_pll *pll = to_clk_sccg_pll(clk);
+	u32 val;
+	u32 divf;
+
+	divf = rate / (parent_rate * 2);
+
+	val = readl(pll->base + PLL_CFG2);
+	val &= ~(PLL_DIVF_MASK << PLL_DIVF1_SHIFT);
+	val |= (divf - 1) << PLL_DIVF1_SHIFT;
+	writel(val, pll->base + PLL_CFG2);
+
+	/* FIXME: PLL lock check */
+
+	return 0;
+}
+
+static int clk_pll1_prepare(struct clk *clk)
+{
+	struct clk_sccg_pll *pll = to_clk_sccg_pll(clk);
+	u32 val;
+
+	val = readl(pll->base);
+	val &= ~(1 << PLL_PD);
+	writel(val, pll->base);
+
+	/* FIXME: PLL lock check */
+
+	return 0;
+}
+
+static void clk_pll1_unprepare(struct clk *clk)
+{
+	struct clk_sccg_pll *pll = to_clk_sccg_pll(clk);
+	u32 val;
+printf("%s %p\n", __func__, pll);
+	val = readl(pll->base);
+	val |= (1 << PLL_PD);
+	writel(val, pll->base);
+printf("fuschi\n");
+}
+
+static unsigned long clk_pll2_recalc_rate(struct clk *clk,
+					 unsigned long parent_rate)
+{
+	struct clk_sccg_pll *pll = to_clk_sccg_pll(clk);
+	u32 val, ref, divr1, divf1, divr2, divf2;
+	u64 temp64;
+
+	val = readl(pll->base + PLL_CFG0);
+	switch ((val >> PLL_REF_SHIFT) & PLL_REF_MASK) {
+	case 0:
+		ref = OSC_25M;
+		break;
+	case 1:
+		ref = OSC_27M;
+		break;
+	default:
+		ref = OSC_25M;
+		break;
+	}
+
+	val = readl(pll->base + PLL_CFG2);
+	divr1 = (val >> PLL_DIVR1_SHIFT) & PLL_DIVR1_MASK;
+	divr2 = (val >> PLL_DIVR2_SHIFT) & PLL_DIVR2_MASK;
+	divf1 = (val >> PLL_DIVF1_SHIFT) & PLL_DIVF_MASK;
+	divf2 = (val >> PLL_DIVF2_SHIFT) & PLL_DIVF_MASK;
+
+	temp64 = ref * 2;
+	temp64 *= (divf1 + 1) * (divf2 + 1);
+
+	do_div(temp64, (divr1 + 1) * (divr2 + 1));
+
+	return (unsigned long)temp64;
+}
+
+static long clk_pll2_round_rate(struct clk *clk, unsigned long rate,
+			       unsigned long *prate)
+{
+	u32 div;
+	unsigned long parent_rate = *prate;
+
+	div = rate / (parent_rate);
+
+	return parent_rate * div;
+}
+
+static int clk_pll2_set_rate(struct clk *clk, unsigned long rate,
+			    unsigned long parent_rate)
+{
+	u32 val;
+	u32 divf;
+	struct clk_sccg_pll *pll = to_clk_sccg_pll(clk);
+
+	divf = rate / (parent_rate);
+
+	val = readl(pll->base + PLL_CFG2);
+	val &= ~(PLL_DIVF_MASK << PLL_DIVF2_SHIFT);
+	val |= (divf - 1) << PLL_DIVF2_SHIFT;
+	writel(val, pll->base + PLL_CFG2);
+
+	/* FIXME: PLL lock check */
+
+	return 0;
+}
+
+static const struct clk_ops clk_sccg_pll1_ops = {
+	.is_enabled	= clk_pll1_is_prepared,
+	.recalc_rate	= clk_pll1_recalc_rate,
+	.round_rate	= clk_pll1_round_rate,
+	.set_rate	= clk_pll1_set_rate,
+};
+
+static const struct clk_ops clk_sccg_pll2_ops = {
+	.enable		= clk_pll1_prepare,
+	.disable	= clk_pll1_unprepare,
+	.recalc_rate	= clk_pll2_recalc_rate,
+	.round_rate	= clk_pll2_round_rate,
+	.set_rate	= clk_pll2_set_rate,
+};
+
+struct clk *imx_clk_sccg_pll(const char *name, const char *parent_name,
+			     void __iomem *base, enum imx_sccg_pll_type pll_type)
+{
+	struct clk_sccg_pll *pll;
+	int ret;
+
+	pll = kzalloc(sizeof(*pll), GFP_KERNEL);
+	if (!pll)
+		return ERR_PTR(-ENOMEM);
+
+	pll->base = base;
+	pll->clk.name = name;
+	switch (pll_type) {
+	case SCCG_PLL1:
+		pll->clk.ops = &clk_sccg_pll1_ops;
+		break;
+	case SCCG_PLL2:
+		pll->clk.ops = &clk_sccg_pll2_ops;
+		break;
+	}
+
+	pll->parent = parent_name;
+        pll->clk.parent_names = &pll->parent;
+        pll->clk.num_parents = 1;
+
+	ret = clk_register(&pll->clk);
+	if (ret) {
+		free(pll);
+		return ERR_PTR(ret);
+	}
+
+	return &pll->clk;
+}
diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h
index c46c2614d9..589e2d091a 100644
--- a/drivers/clk/imx/clk.h
+++ b/drivers/clk/imx/clk.h
@@ -10,6 +10,13 @@ static inline struct clk *imx_clk_divider(const char *name, const char *parent,
 	return clk_divider(name, parent, reg, shift, width, CLK_SET_RATE_PARENT);
 }
 
+static inline struct clk *imx_clk_divider_flags(const char *name,
+                const char *parent, void __iomem *reg, u8 shift, u8 width,
+                unsigned long flags)
+{
+	return clk_divider(name, parent, reg, shift, width, flags);
+}
+
 static inline struct clk *imx_clk_divider_np(const char *name, const char *parent,
 		void __iomem *reg, u8 shift, u8 width)
 {
@@ -44,6 +51,14 @@ static inline struct clk *imx_clk_mux_flags(const char *name, void __iomem *reg,
 	return clk_mux(name, reg, shift, width, parents, num_parents, flags);
 }
 
+static inline struct clk *imx_clk_mux2_flags(const char *name,
+		void __iomem *reg, u8 shift, u8 width, const char **parents,
+		int num_parents, unsigned long flags)
+{
+	return clk_mux(name, reg, shift, width, parents, num_parents,
+		       flags | CLK_OPS_PARENT_ENABLE);
+}
+
 static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg,
 		u8 shift, u8 width, const char **parents, u8 num_parents)
 {
@@ -126,6 +141,18 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
 			  const char *parent, void __iomem *base,
 			  u32 div_mask);
 
+struct clk *imx_clk_frac_pll(const char *name, const char *parent_name,
+			     void __iomem *base);
+
+enum imx_sccg_pll_type {
+	SCCG_PLL1,
+	SCCG_PLL2,
+};
+
+struct clk *imx_clk_sccg_pll(const char *name, const char *parent_name,
+			     void __iomem *base,
+			     enum imx_sccg_pll_type pll_type);
+
 struct clk *imx_clk_pfd(const char *name, const char *parent,
 			void __iomem *reg, u8 idx);
 
-- 
2.16.1



From s.hauer at pengutronix.de  Mon Mar 19 02:11:35 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Mon, 19 Mar 2018 10:11:35 +0100
Subject: [PATCH 03/14] ARM: Add i.MX8 support
In-Reply-To: <20180319091146.4112-1-s.hauer@pengutronix.de>
References: <20180319091146.4112-1-s.hauer@pengutronix.de>
Message-ID: <20180319091146.4112-4-s.hauer@pengutronix.de>

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/dts/imx8mq-pinfunc.h                  | 623 ++++++++++++++++++++++++
 arch/arm/dts/imx8mq.dtsi                       | 624 ++++++++++++++++++++++++
 arch/arm/mach-imx/Kconfig                      |   9 +
 arch/arm/mach-imx/Makefile                     |   1 +
 arch/arm/mach-imx/imx.c                        |   4 +
 arch/arm/mach-imx/imx8mq.c                     |  66 +++
 arch/arm/mach-imx/include/mach/generic.h       |  13 +
 arch/arm/mach-imx/include/mach/imx8mq-regs.h   | 121 +++++
 arch/arm/mach-imx/include/mach/imx_cpu_types.h |   1 +
 include/dt-bindings/clock/imx8mq-clock.h       | 629 +++++++++++++++++++++++++
 10 files changed, 2091 insertions(+)
 create mode 100644 arch/arm/dts/imx8mq-pinfunc.h
 create mode 100644 arch/arm/dts/imx8mq.dtsi
 create mode 100644 arch/arm/mach-imx/imx8mq.c
 create mode 100644 arch/arm/mach-imx/include/mach/imx8mq-regs.h
 create mode 100644 include/dt-bindings/clock/imx8mq-clock.h

diff --git a/arch/arm/dts/imx8mq-pinfunc.h b/arch/arm/dts/imx8mq-pinfunc.h
new file mode 100644
index 0000000000..b94b02080a
--- /dev/null
+++ b/arch/arm/dts/imx8mq-pinfunc.h
@@ -0,0 +1,623 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ */
+
+#ifndef __DTS_IMX8MQ_PINFUNC_H
+#define __DTS_IMX8MQ_PINFUNC_H
+
+/*
+ * The pin function ID is a tuple of
+ * <mux_reg conf_reg input_reg mux_mode input_val>
+ */
+
+#define MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX_PMIC_STBY_REQ               0x014 0x27C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX_PMIC_ON_REQ                        0x018 0x280 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_ONOFF_SNVSMIX_ONOFF                                    0x01C 0x284 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_POR_B_SNVSMIX_POR_B                                    0x020 0x288 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX_RTC_RESET_B                        0x024 0x28C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0                                   0x028 0x290 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT          0x028 0x290 0x4C0 0x1 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K                          0x028 0x290 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1                       0x028 0x290 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO00_SJC_FAIL                                    0x028 0x290 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO01_GPIO1_IO1                                   0x02C 0x294 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO01_PWM1_OUT                                    0x02C 0x294 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M                          0x02C 0x294 0x4BC 0x5 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2                       0x02C 0x294 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO01_SJC_ACTIVE                                  0x02C 0x294 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO02_GPIO1_IO2                                   0x030 0x298 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B                                0x030 0x298 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY                              0x030 0x298 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO02_SJC_DE_B                                    0x030 0x298 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3                                   0x034 0x29C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO03_USDHC1_VSELECT                              0x034 0x29C 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0                            0x034 0x29C 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO03_ANAMIX_XTAL_OK                              0x034 0x29C 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO03_SJC_DONE                                    0x034 0x29C 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO04_GPIO1_IO4                                   0x038 0x2A0 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT                              0x038 0x2A0 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1                            0x038 0x2A0 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO04_ANAMIX_XTAL_OK_LV                           0x038 0x2A0 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO04_USDHC1_TEST_TRIG                            0x038 0x2A0 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5                                   0x03C 0x2A4 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO05_M4_NMI                                      0x03C 0x2A4 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO05_CCMSRCGPCMIX_PMIC_READY                     0x03C 0x2A4 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO05_CCMSRCGPCMIX_INT_BOOT                       0x03C 0x2A4 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO05_USDHC2_TEST_TRIG                            0x03C 0x2A4 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6                                   0x040 0x2A8 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO06_ENET1_MDC                                   0x040 0x2A8 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO06_USDHC1_CD_B                                 0x040 0x2A8 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO06_CCMSRCGPCMIX_EXT_CLK3                       0x040 0x2A8 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO06_ECSPI1_TEST_TRIG                            0x040 0x2A8 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO07_GPIO1_IO7                                   0x044 0x2AC 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO07_ENET1_MDIO                                  0x044 0x2AC 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO07_USDHC1_WP                                   0x044 0x2AC 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO07_CCMSRCGPCMIX_EXT_CLK4                       0x044 0x2AC 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO07_ECSPI2_TEST_TRIG                            0x044 0x2AC 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8                                   0x048 0x2B0 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN                        0x048 0x2B0 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO08_USDHC2_RESET_B                              0x048 0x2B0 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO08_CCMSRCGPCMIX_WAIT                           0x048 0x2B0 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO08_QSPI_TEST_TRIG                              0x048 0x2B0 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9                                   0x04C 0x2B4 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT                       0x04C 0x2B4 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0                            0x04C 0x2B4 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO09_CCMSRCGPCMIX_STOP                           0x04C 0x2B4 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO09_RAWNAND_TEST_TRIG                           0x04C 0x2B4 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO10_GPIO1_IO10                                  0x050 0x2B8 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO10_USB1_OTG_ID                                 0x050 0x2B8 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO10_OCOTP_CTRL_WRAPPER_FUSE_LATCHED             0x050 0x2B8 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11                                  0x054 0x2BC 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO11_USB2_OTG_ID                                 0x054 0x2BC 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO11_CCMSRCGPCMIX_PMIC_READY                     0x054 0x2BC 0x4BC 0x5 0x1
+#define MX8MQ_IOMUXC_GPIO1_IO11_CCMSRCGPCMIX_OUT0                           0x054 0x2BC 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO11_CAAM_WRAPPER_RNG_OSC_OBS                    0x054 0x2BC 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12                                  0x058 0x2C0 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO12_USB1_OTG_PWR                                0x058 0x2C0 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1                            0x058 0x2C0 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO12_CCMSRCGPCMIX_OUT1                           0x058 0x2C0 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO12_CSU_CSU_ALARM_AUT0                          0x058 0x2C0 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13                                  0x05C 0x2C4 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO13_USB1_OTG_OC                                 0x05C 0x2C4 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO13_PWM2_OUT                                    0x05C 0x2C4 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO13_CCMSRCGPCMIX_OUT2                           0x05C 0x2C4 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO13_CSU_CSU_ALARM_AUT1                          0x05C 0x2C4 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO14_GPIO1_IO14                                  0x060 0x2C8 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO14_USB2_OTG_PWR                                0x060 0x2C8 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO14_PWM3_OUT                                    0x060 0x2C8 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1                          0x060 0x2C8 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO14_CSU_CSU_ALARM_AUT2                          0x060 0x2C8 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO15_GPIO1_IO15                                  0x064 0x2CC 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO15_USB2_OTG_OC                                 0x064 0x2CC 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO15_PWM4_OUT                                    0x064 0x2CC 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2                          0x064 0x2CC 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO15_CSU_CSU_INT_DEB                             0x064 0x2CC 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC                                     0x068 0x2D0 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_ENET_MDC_GPIO1_IO16                                    0x068 0x2D0 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO                                   0x06C 0x2D4 0x4C0 0x0 0x1
+#define MX8MQ_IOMUXC_ENET_MDIO_GPIO1_IO17                                   0x06C 0x2D4 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3                               0x070 0x2D8 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_ENET_TD3_GPIO1_IO18                                    0x070 0x2D8 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2                               0x074 0x2DC 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_ENET_TD2_ENET1_TX_CLK                                  0x074 0x2DC 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_ENET_TD2_GPIO1_IO19                                    0x074 0x2DC 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1                               0x078 0x2E0 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_ENET_TD1_GPIO1_IO20                                    0x078 0x2E0 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0                               0x07C 0x2E4 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_ENET_TD0_GPIO1_IO21                                    0x07C 0x2E4 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL                         0x080 0x2E8 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_ENET_TX_CTL_GPIO1_IO22                                 0x080 0x2E8 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC                               0x084 0x2EC 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_ENET_TXC_ENET1_TX_ER                                   0x084 0x2EC 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_ENET_TXC_GPIO1_IO23                                    0x084 0x2EC 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL                         0x088 0x2F0 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_ENET_RX_CTL_GPIO1_IO24                                 0x088 0x2F0 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC                               0x08C 0x2F4 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_ENET_RXC_ENET1_RX_ER                                   0x08C 0x2F4 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_ENET_RXC_GPIO1_IO25                                    0x08C 0x2F4 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0                               0x090 0x2F8 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_ENET_RD0_GPIO1_IO26                                    0x090 0x2F8 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1                               0x094 0x2FC 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_ENET_RD1_GPIO1_IO27                                    0x094 0x2FC 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2                               0x098 0x300 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_ENET_RD2_GPIO1_IO28                                    0x098 0x300 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3                               0x09C 0x304 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_ENET_RD3_GPIO1_IO29                                    0x09C 0x304 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK                                     0x0A0 0x308 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SD1_CLK_GPIO2_IO0                                      0x0A0 0x308 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD                                     0x0A4 0x30C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SD1_CMD_GPIO2_IO1                                      0x0A4 0x30C 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0                                 0x0A8 0x310 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SD1_DATA0_GPIO2_IO2                                    0x0A8 0x31  0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1                                 0x0AC 0x314 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SD1_DATA1_GPIO2_IO3                                    0x0AC 0x314 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2                                 0x0B0 0x318 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SD1_DATA2_GPIO2_IO4                                    0x0B0 0x318 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3                                 0x0B4 0x31C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SD1_DATA3_GPIO2_IO5                                    0x0B4 0x31C 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4                                 0x0B8 0x320 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SD1_DATA4_GPIO2_IO6                                    0x0B8 0x320 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5                                 0x0BC 0x324 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SD1_DATA5_GPIO2_IO7                                    0x0BC 0x324 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6                                 0x0C0 0x328 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SD1_DATA6_GPIO2_IO8                                    0x0C0 0x328 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7                                 0x0C4 0x32C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SD1_DATA7_GPIO2_IO9                                    0x0C4 0x32C 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B                             0x0C8 0x330 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SD1_RESET_B_GPIO2_IO10                                 0x0C8 0x330 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE                               0x0CC 0x334 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SD1_STROBE_GPIO2_IO11                                  0x0CC 0x334 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SD2_CD_B_USDHC2_CD_B                                   0x0D0 0x338 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12                                    0x0D0 0x338 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK                                     0x0D4 0x33C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SD2_CLK_GPIO2_IO13                                     0x0D4 0x33C 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SD2_CLK_CCMSRCGPCMIX_OBSERVE0                          0x0D4 0x33C 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SD2_CLK_OBSERVE_MUX_OUT0                               0x0D4 0x33C 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD                                     0x0D8 0x340 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SD2_CMD_GPIO2_IO14                                     0x0D8 0x340 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SD2_CMD_CCMSRCGPCMIX_OBSERVE1                          0x0D8 0x340 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SD2_CMD_OBSERVE_MUX_OUT1                               0x0D8 0x340 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0                                 0x0DC 0x344 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SD2_DATA0_GPIO2_IO15                                   0x0DC 0x344 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SD2_DATA0_CCMSRCGPCMIX_OBSERVE2                        0x0DC 0x344 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SD2_DATA0_OBSERVE_MUX_OUT2                             0x0DC 0x344 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1                                 0x0E0 0x348 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SD2_DATA1_GPIO2_IO16                                   0x0E0 0x348 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SD2_DATA1_CCMSRCGPCMIX_WAIT                            0x0E0 0x348 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SD2_DATA1_OBSERVE_MUX_OUT3                             0x0E0 0x348 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2                                 0x0E4 0x34C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SD2_DATA2_GPIO2_IO17                                   0x0E4 0x34C 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SD2_DATA2_CCMSRCGPCMIX_STOP                            0x0E4 0x34C 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SD2_DATA2_OBSERVE_MUX_OUT4                             0x0E4 0x34C 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3                                 0x0E8 0x350 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SD2_DATA3_GPIO2_IO18                                   0x0E8 0x350 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SD2_DATA3_CCMSRCGPCMIX_EARLY_RESET                     0x0E8 0x350 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SD2_RESET_B_USDHC2_RESET_B                             0x0EC 0x354 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19                                 0x0EC 0x354 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SD2_RESET_B_CCMSRCGPCMIX_SYSTEM_RESET                  0x0EC 0x354 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SD2_WP_USDHC2_WP                                       0x0F0 0x358 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20                                      0x0F0 0x358 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SD2_WP_SIM_M_HMASTLOCK                                 0x0F0 0x358 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_NAND_ALE_RAWNAND_ALE                                   0x0F4 0x35C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK                                   0x0F4 0x35C 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_NAND_ALE_GPIO3_IO0                                     0x0F4 0x35C 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_NAND_ALE_SIM_M_HPROT0                                  0x0F4 0x35C 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_NAND_CE0_B_RAWNAND_CE0_B                               0x0F8 0x360 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B                                0x0F8 0x360 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_NAND_CE0_B_GPIO3_IO1                                   0x0F8 0x360 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_NAND_CE0_B_SIM_M_HPROT1                                0x0F8 0x360 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_NAND_CE1_B_RAWNAND_CE1_B                               0x0FC 0x364 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B                                0x0FC 0x364 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_NAND_CE1_B_GPIO3_IO2                                   0x0FC 0x364 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_NAND_CE1_B_SIM_M_HPROT2                                0x0FC 0x364 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_NAND_CE2_B_RAWNAND_CE2_B                               0x100 0x368 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_NAND_CE2_B_QSPI_B_SS0_B                                0x100 0x368 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_NAND_CE2_B_GPIO3_IO3                                   0x100 0x368 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_NAND_CE2_B_SIM_M_HPROT3                                0x100 0x368 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_NAND_CE3_B_RAWNAND_CE3_B                               0x104 0x36C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_NAND_CE3_B_QSPI_B_SS1_B                                0x104 0x36C 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4                                   0x104 0x36C 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_NAND_CE3_B_SIM_M_HADDR0                                0x104 0x36C 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_NAND_CLE_RAWNAND_CLE                                   0x108 0x370 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_NAND_CLE_QSPI_B_SCLK                                   0x108 0x370 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5                                     0x108 0x370 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_NAND_CLE_SIM_M_HADDR1                                  0x108 0x370 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_NAND_DATA00_RAWNAND_DATA00                             0x10C 0x374 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0                               0x10C 0x374 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_NAND_DATA00_GPIO3_IO6                                  0x10C 0x374 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_NAND_DATA00_SIM_M_HADDR2                               0x10C 0x374 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_NAND_DATA01_RAWNAND_DATA01                             0x110 0x378 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1                               0x110 0x378 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_NAND_DATA01_GPIO3_IO7                                  0x110 0x378 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_NAND_DATA01_SIM_M_HADDR3                               0x110 0x378 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_NAND_DATA02_RAWNAND_DATA02                             0x114 0x37C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2                               0x114 0x37C 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_NAND_DATA02_GPIO3_IO8                                  0x114 0x37C 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_NAND_DATA02_SIM_M_HADDR4                               0x114 0x37C 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_NAND_DATA03_RAWNAND_DATA03                             0x118 0x380 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3                               0x118 0x380 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_NAND_DATA03_GPIO3_IO9                                  0x118 0x380 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_NAND_DATA03_SIM_M_HADDR5                               0x118 0x380 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_NAND_DATA04_RAWNAND_DATA04                             0x11C 0x384 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_NAND_DATA04_QSPI_B_DATA0                               0x11C 0x384 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10                                 0x11C 0x384 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_NAND_DATA04_SIM_M_HADDR6                               0x11C 0x384 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_NAND_DATA05_RAWNAND_DATA05                             0x120 0x388 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_NAND_DATA05_QSPI_B_DATA1                               0x120 0x388 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11                                 0x120 0x388 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_NAND_DATA05_SIM_M_HADDR7                               0x120 0x388 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_NAND_DATA06_RAWNAND_DATA06                             0x124 0x38C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_NAND_DATA06_QSPI_B_DATA2                               0x124 0x38C 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12                                 0x124 0x38C 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_NAND_DATA06_SIM_M_HADDR8                               0x124 0x38C 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_NAND_DATA07_RAWNAND_DATA07                             0x128 0x390 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_NAND_DATA07_QSPI_B_DATA3                               0x128 0x390 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_NAND_DATA07_GPIO3_IO13                                 0x128 0x390 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_NAND_DATA07_SIM_M_HADDR9                               0x128 0x390 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_NAND_DQS_RAWNAND_DQS                                   0x12C 0x394 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_NAND_DQS_QSPI_A_DQS                                    0x12C 0x394 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_NAND_DQS_GPIO3_IO14                                    0x12C 0x394 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_NAND_DQS_SIM_M_HADDR10                                 0x12C 0x394 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_NAND_RE_B_RAWNAND_RE_B                                 0x130 0x398 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_NAND_RE_B_QSPI_B_DQS                                   0x130 0x398 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15                                   0x130 0x398 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_NAND_RE_B_SIM_M_HADDR11                                0x130 0x398 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_NAND_READY_B_RAWNAND_READY_B                           0x134 0x39C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_NAND_READY_B_GPIO3_IO16                                0x134 0x39C 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_NAND_READY_B_SIM_M_HADDR12                             0x134 0x39C 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_NAND_WE_B_RAWNAND_WE_B                                 0x138 0x3A0 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_NAND_WE_B_GPIO3_IO17                                   0x138 0x3A0 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_NAND_WE_B_SIM_M_HADDR13                                0x138 0x3A0 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_NAND_WP_B_RAWNAND_WP_B                                 0x13C 0x3A4 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_NAND_WP_B_GPIO3_IO18                                   0x13C 0x3A4 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_NAND_WP_B_SIM_M_HADDR14                                0x13C 0x3A4 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC                                 0x140 0x3A8 0x4E4 0x0 0x0
+#define MX8MQ_IOMUXC_SAI5_RXFS_SAI1_TX_DATA0                                0x140 0x3A8 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI5_RXFS_GPIO3_IO19                                   0x140 0x3A8 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI5_RXC_SAI5_RX_BCLK                                  0x144 0x3AC 0x4D0 0x0 0x0
+#define MX8MQ_IOMUXC_SAI5_RXC_SAI1_TX_DATA1                                 0x144 0x3AC 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20                                    0x144 0x3AC 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0                                0x148 0x3B0 0x4D4 0x0 0x0
+#define MX8MQ_IOMUXC_SAI5_RXD0_SAI1_TX_DATA2                                0x148 0x3B0 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI5_RXD0_GPIO3_IO21                                   0x148 0x3B0 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI5_RXD1_SAI5_RX_DATA1                                0x14C 0x3B4 0x4D8 0x0 0x0
+#define MX8MQ_IOMUXC_SAI5_RXD1_SAI1_TX_DATA3                                0x14C 0x3B4 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI5_RXD1_SAI1_TX_SYNC                                 0x14C 0x3B4 0x4CC 0x2 0x0
+#define MX8MQ_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC                                 0x14C 0x3B4 0x4EC 0x3 0x0
+#define MX8MQ_IOMUXC_SAI5_RXD1_GPIO3_IO22                                   0x14C 0x3B4 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI5_RXD2_SAI5_RX_DATA2                                0x150 0x3B8 0x4DC 0x0 0x0
+#define MX8MQ_IOMUXC_SAI5_RXD2_SAI1_TX_DATA4                                0x150 0x3B8 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI5_RXD2_SAI1_TX_SYNC                                 0x150 0x3B8 0x4CC 0x2 0x1
+#define MX8MQ_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK                                 0x150 0x3B8 0x4E8 0x3 0x0
+#define MX8MQ_IOMUXC_SAI5_RXD2_GPIO3_IO23                                   0x150 0x3B8 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI5_RXD3_SAI5_RX_DATA3                                0x154 0x3BC 0x4E0 0x0 0x0
+#define MX8MQ_IOMUXC_SAI5_RXD3_SAI1_TX_DATA5                                0x154 0x3BC 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI5_RXD3_SAI1_TX_SYNC                                 0x154 0x3BC 0x4CC 0x2 0x2
+#define MX8MQ_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0                                0x154 0x3BC 0x000 0x3 0x0
+#define MX8MQ_IOMUXC_SAI5_RXD3_GPIO3_IO24                                   0x154 0x3BC 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI5_MCLK_SAI5_MCLK                                    0x158 0x3C0 0x52C 0x0 0x0
+#define MX8MQ_IOMUXC_SAI5_MCLK_SAI1_TX_BCLK                                 0x158 0x3C0 0x4C8 0x1 0x0
+#define MX8MQ_IOMUXC_SAI5_MCLK_SAI4_MCLK                                    0x158 0x3C0 0x000 0x2 0x0
+#define MX8MQ_IOMUXC_SAI5_MCLK_GPIO3_IO25                                   0x158 0x3C0 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI5_MCLK_CCMSRCGPCMIX_TESTER_ACK                      0x158 0x3C0 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SAI1_RXFS_SAI1_RX_SYNC                                 0x15C 0x3C4 0x4C4 0x0 0x0
+#define MX8MQ_IOMUXC_SAI1_RXFS_SAI5_RX_SYNC                                 0x15C 0x3C4 0x4E4 0x1 0x1
+#define MX8MQ_IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK                          0x15C 0x3C4 0x000 0x4 0x0
+#define MX8MQ_IOMUXC_SAI1_RXFS_GPIO4_IO0                                    0x15C 0x3C4 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI1_RXFS_SIM_M_HADDR15                                0x15C 0x3C4 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI1_RXC_SAI1_RX_BCLK                                  0x160 0x3C8 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI1_RXC_SAI5_RX_BCLK                                  0x160 0x3C8 0x4D0 0x1 0x1
+#define MX8MQ_IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL                           0x160 0x3C8 0x000 0x4 0x0
+#define MX8MQ_IOMUXC_SAI1_RXC_GPIO4_IO1                                     0x160 0x3C8 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI1_RXC_SIM_M_HADDR16                                 0x160 0x3C8 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD0_SAI1_RX_DATA0                                0x164 0x3CC 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD0_SAI5_RX_DATA0                                0x164 0x3CC 0x4D4 0x1 0x1
+#define MX8MQ_IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0                             0x164 0x3CC 0x000 0x4 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD0_GPIO4_IO2                                    0x164 0x3CC 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD0_CCMSRCGPCMIX_BOOT_CFG0                       0x164 0x3CC 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD0_SIM_M_HADDR17                                0x164 0x3CC 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD1_SAI1_RX_DATA1                                0x168 0x3D0 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD1_SAI5_RX_DATA1                                0x168 0x3D0 0x4D8 0x1 0x1
+#define MX8MQ_IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1                             0x168 0x3D0 0x000 0x4 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD1_GPIO4_IO3                                    0x168 0x3D0 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD1_CCMSRCGPCMIX_BOOT_CFG1                       0x168 0x3D0 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD1_SIM_M_HADDR18                                0x168 0x3D0 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD2_SAI1_RX_DATA2                                0x16C 0x3D4 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD2_SAI5_RX_DATA2                                0x16C 0x3D4 0x4DC 0x1 0x1
+#define MX8MQ_IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2                             0x16C 0x3D4 0x000 0x4 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD2_GPIO4_IO4                                    0x16C 0x3D4 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD2_CCMSRCGPCMIX_BOOT_CFG2                       0x16C 0x3D4 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD2_SIM_M_HADDR19                                0x16C 0x3D4 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD3_SAI1_RX_DATA3                                0x170 0x3D8 0x4E0 0x0 0x1
+#define MX8MQ_IOMUXC_SAI1_RXD3_SAI5_RX_DATA3                                0x170 0x3D8 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3                             0x170 0x3D8 0x000 0x4 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD3_GPIO4_IO5                                    0x170 0x3D8 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD3_CCMSRCGPCMIX_BOOT_CFG3                       0x170 0x3D8 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD3_SIM_M_HADDR20                                0x170 0x3D8 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD4_SAI1_RX_DATA4                                0x174 0x3DC 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD4_SAI6_TX_BCLK                                 0x174 0x3DC 0x51C 0x1 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD4_SAI6_RX_BCLK                                 0x174 0x3DC 0x510 0x2 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4                             0x174 0x3DC 0x000 0x4 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD4_GPIO4_IO6                                    0x174 0x3DC 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD4_CCMSRCGPCMIX_BOOT_CFG4                       0x174 0x3DC 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD4_SIM_M_HADDR21                                0x174 0x3DC 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD5_SAI1_RX_DATA5                                0x178 0x3E0 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD5_SAI6_TX_DATA0                                0x178 0x3E0 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD5_SAI6_RX_DATA0                                0x178 0x3E0 0x514 0x2 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD5_SAI1_RX_SYNC                                 0x178 0x3E0 0x4C4 0x3 0x1
+#define MX8MQ_IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5                             0x178 0x3E0 0x000 0x4 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD5_GPIO4_IO7                                    0x178 0x3E0 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD5_CCMSRCGPCMIX_BOOT_CFG5                       0x178 0x3E0 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD5_SIM_M_HADDR22                                0x178 0x3E0 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD6_SAI1_RX_DATA6                                0x17C 0x3E4 0x520 0x0 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD6_SAI6_TX_SYNC                                 0x17C 0x3E4 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD6_SAI6_RX_SYNC                                 0x17C 0x3E4 0x518 0x2 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6                             0x17C 0x3E4 0x000 0x4 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD6_GPIO4_IO8                                    0x17C 0x3E4 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD6_CCMSRCGPCMIX_BOOT_CFG6                       0x17C 0x3E4 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD6_SIM_M_HADDR23                                0x17C 0x3E4 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD7_SAI1_RX_DATA7                                0x180 0x3E8 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD7_SAI6_MCLK                                    0x180 0x3E8 0x530 0x1 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD7_SAI1_TX_SYNC                                 0x180 0x3E8 0x4CC 0x2 0x4
+#define MX8MQ_IOMUXC_SAI1_RXD7_SAI1_TX_DATA4                                0x180 0x3E8 0x000 0x3 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7                             0x180 0x3E8 0x000 0x4 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD7_GPIO4_IO9                                    0x180 0x3E8 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD7_CCMSRCGPCMIX_BOOT_CFG7                       0x180 0x3E8 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD7_SIM_M_HADDR24                                0x180 0x3E8 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC                                 0x184 0x3EC 0x4CC 0x0 0x3
+#define MX8MQ_IOMUXC_SAI1_TXFS_SAI5_TX_SYNC                                 0x184 0x3EC 0x4EC 0x1 0x1
+#define MX8MQ_IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO                             0x184 0x3EC 0x000 0x4 0x0
+#define MX8MQ_IOMUXC_SAI1_TXFS_GPIO4_IO10                                   0x184 0x3EC 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI1_TXFS_SIM_M_HADDR25                                0x184 0x3EC 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI1_TXC_SAI1_TX_BCLK                                  0x188 0x3F0 0x4C8 0x0 0x1
+#define MX8MQ_IOMUXC_SAI1_TXC_SAI5_TX_BCLK                                  0x188 0x3F0 0x4E8 0x1 0x1
+#define MX8MQ_IOMUXC_SAI1_TXC_CORESIGHT_EVENTI                              0x188 0x3F0 0x000 0x4 0x0
+#define MX8MQ_IOMUXC_SAI1_TXC_GPIO4_IO11                                    0x188 0x3F0 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI1_TXC_SIM_M_HADDR26                                 0x188 0x3F0 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0                                0x18C 0x3F4 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD0_SAI5_TX_DATA0                                0x18C 0x3F4 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8                             0x18C 0x3F4 0x000 0x4 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD0_GPIO4_IO12                                   0x18C 0x3F4 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD0_CCMSRCGPCMIX_BOOT_CFG8                       0x18C 0x3F4 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD0_SIM_M_HADDR27                                0x18C 0x3F4 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1                                0x190 0x3F8 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD1_SAI5_TX_DATA1                                0x190 0x3F8 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9                             0x190 0x3F8 0x000 0x4 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD1_GPIO4_IO13                                   0x190 0x3F8 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD1_CCMSRCGPCMIX_BOOT_CFG9                       0x190 0x3F8 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD1_SIM_M_HADDR28                                0x190 0x3F8 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2                                0x194 0x3FC 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD2_SAI5_TX_DATA2                                0x194 0x3FC 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10                            0x194 0x3FC 0x000 0x4 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD2_GPIO4_IO14                                   0x194 0x3FC 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD2_CCMSRCGPCMIX_BOOT_CFG10                      0x194 0x3FC 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD2_SIM_M_HADDR29                                0x194 0x3FC 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3                                0x198 0x400 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD3_SAI5_TX_DATA3                                0x198 0x400 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11                            0x198 0x400 0x000 0x4 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD3_GPIO4_IO15                                   0x198 0x400 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD3_CCMSRCGPCMIX_BOOT_CFG11                      0x198 0x400 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD3_SIM_M_HADDR30                                0x198 0x400 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4                                0x19C 0x404 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD4_SAI6_RX_BCLK                                 0x19C 0x404 0x510 0x1 0x1
+#define MX8MQ_IOMUXC_SAI1_TXD4_SAI6_TX_BCLK                                 0x19C 0x404 0x51C 0x2 0x1
+#define MX8MQ_IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12                            0x19C 0x404 0x000 0x4 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD4_GPIO4_IO16                                   0x19C 0x404 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD4_CCMSRCGPCMIX_BOOT_CFG12                      0x19C 0x404 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD4_SIM_M_HADDR31                                0x19C 0x404 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5                                0x1A0 0x408 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD5_SAI6_RX_DATA0                                0x1A0 0x408 0x514 0x1 0x1
+#define MX8MQ_IOMUXC_SAI1_TXD5_SAI6_TX_DATA0                                0x1A0 0x408 0x000 0x2 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13                            0x1A0 0x408 0x000 0x4 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD5_GPIO4_IO17                                   0x1A0 0x408 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD5_CCMSRCGPCMIX_BOOT_CFG13                      0x1A0 0x408 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD5_SIM_M_HBURST0                                0x1A0 0x408 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6                                0x1A4 0x40C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD6_SAI6_RX_SYNC                                 0x1A4 0x40C 0x518 0x1 0x1
+#define MX8MQ_IOMUXC_SAI1_TXD6_SAI6_TX_SYNC                                 0x1A4 0x40C 0x520 0x2 0x1
+#define MX8MQ_IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14                            0x1A4 0x40C 0x000 0x4 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD6_GPIO4_IO18                                   0x1A4 0x40C 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD6_CCMSRCGPCMIX_BOOT_CFG14                      0x1A4 0x40C 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD6_SIM_M_HBURST1                                0x1A4 0x40C 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7                                0x1A8 0x410 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD7_SAI6_MCLK                                    0x1A8 0x410 0x530 0x1 0x1
+#define MX8MQ_IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15                            0x1A8 0x410 0x000 0x4 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD7_GPIO4_IO19                                   0x1A8 0x410 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD7_CCMSRCGPCMIX_BOOT_CFG15                      0x1A8 0x410 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD7_SIM_M_HBURST2                                0x1A8 0x410 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI1_MCLK_SAI1_MCLK                                    0x1AC 0x414 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI1_MCLK_SAI5_MCLK                                    0x1AC 0x414 0x52C 0x1 0x1
+#define MX8MQ_IOMUXC_SAI1_MCLK_SAI1_TX_BCLK                                 0x1AC 0x414 0x4C8 0x2 0x2
+#define MX8MQ_IOMUXC_SAI1_MCLK_GPIO4_IO20                                   0x1AC 0x414 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI1_MCLK_SIM_M_HRESP                                  0x1AC 0x414 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI2_RXFS_SAI2_RX_SYNC                                 0x1B0 0x418 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI2_RXFS_SAI5_TX_SYNC                                 0x1B0 0x418 0x4EC 0x1 0x2
+#define MX8MQ_IOMUXC_SAI2_RXFS_GPIO4_IO21                                   0x1B0 0x418 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI2_RXFS_SIM_M_HSIZE0                                 0x1B0 0x418 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI2_RXC_SAI2_RX_BCLK                                  0x1B4 0x41C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI2_RXC_SAI5_TX_BCLK                                  0x1B4 0x41C 0x4E8 0x1 0x2
+#define MX8MQ_IOMUXC_SAI2_RXC_GPIO4_IO22                                    0x1B4 0x41C 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI2_RXC_SIM_M_HSIZE1                                  0x1B4 0x41C 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0                                0x1B8 0x420 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI2_RXD0_SAI5_TX_DATA0                                0x1B8 0x420 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI2_RXD0_GPIO4_IO23                                   0x1B8 0x420 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI2_RXD0_SIM_M_HSIZE2                                 0x1B8 0x420 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC                                 0x1BC 0x424 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI2_TXFS_SAI5_TX_DATA1                                0x1BC 0x424 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI2_TXFS_GPIO4_IO24                                   0x1BC 0x424 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI2_TXFS_SIM_M_HWRITE                                 0x1BC 0x424 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK                                  0x1C0 0x428 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI2_TXC_SAI5_TX_DATA2                                 0x1C0 0x428 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI2_TXC_GPIO4_IO25                                    0x1C0 0x428 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI2_TXC_SIM_M_HREADYOUT                               0x1C0 0x428 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0                                0x1C4 0x42C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI2_TXD0_SAI5_TX_DATA3                                0x1C4 0x42C 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI2_TXD0_GPIO4_IO26                                   0x1C4 0x42C 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI2_TXD0_TPSMP_CLK                                    0x1C4 0x42C 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK                                    0x1C8 0x430 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI2_MCLK_SAI5_MCLK                                    0x1C8 0x430 0x52C 0x1 0x2
+#define MX8MQ_IOMUXC_SAI2_MCLK_GPIO4_IO27                                   0x1C8 0x430 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI2_MCLK_TPSMP_HDATA_DIR                              0x1C8 0x430 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI3_RXFS_SAI3_RX_SYNC                                 0x1CC 0x434 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI3_RXFS_GPT1_CAPTURE1                                0x1CC 0x434 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI3_RXFS_SAI5_RX_SYNC                                 0x1CC 0x434 0x4E4 0x2 0x2
+#define MX8MQ_IOMUXC_SAI3_RXFS_GPIO4_IO28                                   0x1CC 0x434 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI3_RXFS_TPSMP_HTRANS0                                0x1CC 0x434 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI3_RXC_SAI3_RX_BCLK                                  0x1D0 0x438 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI3_RXC_GPT1_CAPTURE2                                 0x1D0 0x438 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI3_RXC_SAI5_RX_BCLK                                  0x1D0 0x438 0x4D0 0x2 0x2
+#define MX8MQ_IOMUXC_SAI3_RXC_GPIO4_IO29                                    0x1D0 0x438 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI3_RXC_TPSMP_HTRANS1                                 0x1D0 0x438 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI3_RXD_SAI3_RX_DATA0                                 0x1D4 0x43C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI3_RXD_GPT1_COMPARE1                                 0x1D4 0x43C 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI3_RXD_SAI5_RX_DATA0                                 0x1D4 0x43C 0x4D4 0x2 0x2
+#define MX8MQ_IOMUXC_SAI3_RXD_GPIO4_IO30                                    0x1D4 0x43C 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI3_RXD_TPSMP_HDATA0                                  0x1D4 0x43C 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC                                 0x1D8 0x440 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI3_TXFS_GPT1_CLK                                     0x1D8 0x440 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI3_TXFS_SAI5_RX_DATA1                                0x1D8 0x440 0x4D8 0x2 0x2
+#define MX8MQ_IOMUXC_SAI3_TXFS_GPIO4_IO31                                   0x1D8 0x440 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI3_TXFS_TPSMP_HDATA1                                 0x1D8 0x440 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI3_TXC_SAI3_TX_BCLK                                  0x1DC 0x444 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI3_TXC_GPT1_COMPARE2                                 0x1DC 0x444 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI3_TXC_SAI5_RX_DATA2                                 0x1DC 0x444 0x4DC 0x2 0x2
+#define MX8MQ_IOMUXC_SAI3_TXC_GPIO5_IO0                                     0x1DC 0x444 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI3_TXC_TPSMP_HDATA2                                  0x1DC 0x444 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI3_TXD_SAI3_TX_DATA0                                 0x1E0 0x448 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI3_TXD_GPT1_COMPARE3                                 0x1E0 0x448 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI3_TXD_SAI5_RX_DATA3                                 0x1E0 0x448 0x4E0 0x2 0x2
+#define MX8MQ_IOMUXC_SAI3_TXD_GPIO5_IO1                                     0x1E0 0x448 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI3_TXD_TPSMP_HDATA3                                  0x1E0 0x448 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI3_MCLK_SAI3_MCLK                                    0x1E4 0x44C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI3_MCLK_PWM4_OUT                                     0x1E4 0x44C 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI3_MCLK_SAI5_MCLK                                    0x1E4 0x44C 0x52C 0x2 0x3
+#define MX8MQ_IOMUXC_SAI3_MCLK_GPIO5_IO2                                    0x1E4 0x44C 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI3_MCLK_TPSMP_HDATA4                                 0x1E4 0x44C 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SPDIF_TX_SPDIF1_OUT                                    0x1E8 0x450 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SPDIF_TX_PWM3_OUT                                      0x1E8 0x450 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SPDIF_TX_GPIO5_IO3                                     0x1E8 0x450 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SPDIF_TX_TPSMP_HDATA5                                  0x1E8 0x450 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SPDIF_RX_SPDIF1_IN                                     0x1EC 0x454 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SPDIF_RX_PWM2_OUT                                      0x1EC 0x454 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SPDIF_RX_GPIO5_IO4                                     0x1EC 0x454 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SPDIF_RX_TPSMP_HDATA6                                  0x1EC 0x454 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK                           0x1F0 0x458 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT                                 0x1F0 0x458 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5                                0x1F0 0x458 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SPDIF_EXT_CLK_TPSMP_HDATA7                             0x1F0 0x458 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK                                0x1F4 0x45C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX                               0x1F4 0x45C 0x504 0x1 0x0
+#define MX8MQ_IOMUXC_ECSPI1_SCLK_UART3_DTE_TX                               0x1F4 0x45C 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_ECSPI1_SCLK_GPIO5_IO6                                  0x1F4 0x45C 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_ECSPI1_SCLK_TPSMP_HDATA8                               0x1F4 0x45C 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI                                0x1F8 0x460 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX                               0x1F8 0x460 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_ECSPI1_MOSI_UART3_DTE_RX                               0x1F8 0x460 0x504 0x1 0x1
+#define MX8MQ_IOMUXC_ECSPI1_MOSI_GPIO5_IO7                                  0x1F8 0x460 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_ECSPI1_MOSI_TPSMP_HDATA9                               0x1F8 0x460 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_ECSPI1_MISO_ECSPI1_MISO                                0x1FC 0x464 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B                            0x1FC 0x464 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DTE_RTS_B                            0x1FC 0x464 0x500 0x1 0x0
+#define MX8MQ_IOMUXC_ECSPI1_MISO_GPIO5_IO8                                  0x1FC 0x464 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_ECSPI1_MISO_TPSMP_HDATA10                              0x1FC 0x464 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_ECSPI1_SS0_ECSPI1_SS0                                  0x200 0x468 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B                             0x200 0x468 0x500 0x1 0x1
+#define MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DTE_CTS_B                             0x200 0x468 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_ECSPI1_SS0_GPIO5_IO9                                   0x200 0x468 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_ECSPI1_SS0_TPSMP_HDATA11                               0x200 0x468 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK                                0x204 0x46C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX                               0x204 0x46C 0x50C 0x1 0x0
+#define MX8MQ_IOMUXC_ECSPI2_SCLK_UART4_DTE_TX                               0x204 0x46C 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_ECSPI2_SCLK_GPIO5_IO10                                 0x204 0x46C 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_ECSPI2_SCLK_TPSMP_HDATA12                              0x204 0x46C 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI                                0x208 0x470 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX                               0x208 0x470 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_ECSPI2_MOSI_UART4_DTE_RX                               0x208 0x470 0x50C 0x1 0x1
+#define MX8MQ_IOMUXC_ECSPI2_MOSI_GPIO5_IO11                                 0x208 0x470 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_ECSPI2_MOSI_TPSMP_HDATA13                              0x208 0x470 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_ECSPI2_MISO_ECSPI2_MISO                                0x20C 0x474 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B                            0x20C 0x474 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_ECSPI2_MISO_UART4_DTE_RTS_B                            0x20C 0x474 0x508 0x1 0x0
+#define MX8MQ_IOMUXC_ECSPI2_MISO_GPIO5_IO12                                 0x20C 0x474 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_ECSPI2_MISO_TPSMP_HDATA14                              0x20C 0x474 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_ECSPI2_SS0_ECSPI2_SS0                                  0x210 0x478 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B                             0x210 0x478 0x508 0x1 0x1
+#define MX8MQ_IOMUXC_ECSPI2_SS0_UART4_DTE_CTS_B                             0x210 0x478 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_ECSPI2_SS0_GPIO5_IO13                                  0x210 0x478 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_ECSPI2_SS0_TPSMP_HDATA15                               0x210 0x478 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL                                      0x214 0x47C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_I2C1_SCL_ENET1_MDC                                     0x214 0x47C 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_I2C1_SCL_GPIO5_IO14                                    0x214 0x47C 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_I2C1_SCL_TPSMP_HDATA16                                 0x214 0x47C 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA                                      0x218 0x480 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_I2C1_SDA_ENET1_MDIO                                    0x218 0x480 0x4C0 0x1 0x2
+#define MX8MQ_IOMUXC_I2C1_SDA_GPIO5_IO15                                    0x218 0x480 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_I2C1_SDA_TPSMP_HDATA17                                 0x218 0x480 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL                                      0x21C 0x484 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN                          0x21C 0x484 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_I2C2_SCL_GPIO5_IO16                                    0x21C 0x484 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_I2C2_SCL_TPSMP_HDATA18                                 0x21C 0x484 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA                                      0x220 0x488 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT                         0x220 0x488 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_I2C2_SDA_GPIO5_IO17                                    0x220 0x488 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_I2C2_SDA_TPSMP_HDATA19                                 0x220 0x488 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL                                      0x224 0x48C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_I2C3_SCL_PWM4_OUT                                      0x224 0x48C 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_I2C3_SCL_GPT2_CLK                                      0x224 0x48C 0x000 0x2 0x0
+#define MX8MQ_IOMUXC_I2C3_SCL_GPIO5_IO18                                    0x224 0x48C 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_I2C3_SCL_TPSMP_HDATA20                                 0x224 0x48C 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA                                      0x228 0x490 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_I2C3_SDA_PWM3_OUT                                      0x228 0x490 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_I2C3_SDA_GPT3_CLK                                      0x228 0x490 0x000 0x2 0x0
+#define MX8MQ_IOMUXC_I2C3_SDA_GPIO5_IO19                                    0x228 0x490 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_I2C3_SDA_TPSMP_HDATA21                                 0x228 0x490 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL                                      0x22C 0x494 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_I2C4_SCL_PWM2_OUT                                      0x22C 0x494 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B                                0x22C 0x494 0x524 0x2 0x0
+#define MX8MQ_IOMUXC_I2C4_SCL_GPIO5_IO20                                    0x22C 0x494 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_I2C4_SCL_TPSMP_HDATA22                                 0x22C 0x494 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA                                      0x230 0x498 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_I2C4_SDA_PWM1_OUT                                      0x230 0x498 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B                                0x230 0x498 0x528 0x2 0x0
+#define MX8MQ_IOMUXC_I2C4_SDA_GPIO5_IO21                                    0x230 0x498 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_I2C4_SDA_TPSMP_HDATA23                                 0x230 0x498 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX                                 0x234 0x49C 0x4F4 0x0 0x0
+#define MX8MQ_IOMUXC_UART1_RXD_UART1_DTE_TX                                 0x234 0x49C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_UART1_RXD_ECSPI3_SCLK                                  0x234 0x49C 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_UART1_RXD_GPIO5_IO22                                   0x234 0x49C 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_UART1_RXD_TPSMP_HDATA24                                0x234 0x49C 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX                                 0x238 0x4A0 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_UART1_TXD_UART1_DTE_RX                                 0x238 0x4A0 0x4F4 0x0 0x0
+#define MX8MQ_IOMUXC_UART1_TXD_ECSPI3_MOSI                                  0x238 0x4A0 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_UART1_TXD_GPIO5_IO23                                   0x238 0x4A0 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_UART1_TXD_TPSMP_HDATA25                                0x238 0x4A0 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX                                 0x23C 0x4A4 0x4FC 0x0 0x0
+#define MX8MQ_IOMUXC_UART2_RXD_UART2_DTE_TX                                 0x23C 0x4A4 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_UART2_RXD_ECSPI3_MISO                                  0x23C 0x4A4 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_UART2_RXD_GPIO5_IO24                                   0x23C 0x4A4 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_UART2_RXD_TPSMP_HDATA26                                0x23C 0x4A4 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX                                 0x240 0x4A8 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_UART2_TXD_UART2_DTE_RX                                 0x240 0x4A8 0x4FC 0x0 0x1
+#define MX8MQ_IOMUXC_UART2_TXD_ECSPI3_SS0                                   0x240 0x4A8 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_UART2_TXD_GPIO5_IO25                                   0x240 0x4A8 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_UART2_TXD_TPSMP_HDATA27                                0x240 0x4A8 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX                                 0x244 0x4AC 0x504 0x0 0x2
+#define MX8MQ_IOMUXC_UART3_RXD_UART3_DTE_TX                                 0x244 0x4AC 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_UART3_RXD_UART1_DCE_CTS_B                              0x244 0x4AC 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_UART3_RXD_UART1_DTE_RTS_B                              0x244 0x4AC 0x4F0 0x1 0x0
+#define MX8MQ_IOMUXC_UART3_RXD_GPIO5_IO26                                   0x244 0x4AC 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_UART3_RXD_TPSMP_HDATA28                                0x244 0x4AC 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX                                 0x248 0x4B0 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_UART3_TXD_UART3_DTE_RX                                 0x248 0x4B0 0x504 0x0 0x3
+#define MX8MQ_IOMUXC_UART3_TXD_UART1_DCE_RTS_B                              0x248 0x4B0 0x4F0 0x1 0x1
+#define MX8MQ_IOMUXC_UART3_TXD_UART1_DTE_CTS_B                              0x248 0x4B0 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_UART3_TXD_GPIO5_IO27                                   0x248 0x4B0 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_UART3_TXD_TPSMP_HDATA29                                0x248 0x4B0 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_UART4_RXD_UART4_DCE_RX                                 0x24C 0x4B4 0x50C 0x0 0x2
+#define MX8MQ_IOMUXC_UART4_RXD_UART4_DTE_TX                                 0x24C 0x4B4 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_UART4_RXD_UART2_DCE_CTS_B                              0x24C 0x4B4 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_UART4_RXD_UART2_DTE_RTS_B                              0x24C 0x4B4 0x4F8 0x1 0x0
+#define MX8MQ_IOMUXC_UART4_RXD_PCIE1_CLKREQ_B                               0x24C 0x4B4 0x524 0x2 0x1
+#define MX8MQ_IOMUXC_UART4_RXD_GPIO5_IO28                                   0x24C 0x4B4 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_UART4_RXD_TPSMP_HDATA30                                0x24C 0x4B4 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_UART4_TXD_UART4_DCE_TX                                 0x250 0x4B8 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_UART4_TXD_UART4_DTE_RX                                 0x250 0x4B8 0x50C 0x0 0x3
+#define MX8MQ_IOMUXC_UART4_TXD_UART2_DCE_RTS_B                              0x250 0x4B8 0x4F8 0x1 0x1
+#define MX8MQ_IOMUXC_UART4_TXD_UART2_DTE_CTS_B                              0x250 0x4B8 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_UART4_TXD_PCIE2_CLKREQ_B                               0x250 0x4B8 0x528 0x2 0x1
+#define MX8MQ_IOMUXC_UART4_TXD_GPIO5_IO29                                   0x250 0x4B8 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_UART4_TXD_TPSMP_HDATA31                                0x250 0x4B8 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_TEST_MODE                                              0x000 0x254 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_BOOT_MODE0                                             0x000 0x258 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_BOOT_MODE1                                             0x000 0x25C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_JTAG_MOD                                               0x000 0x260 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_JTAG_TRST_B                                            0x000 0x264 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_JTAG_TDI                                               0x000 0x268 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_JTAG_TMS                                               0x000 0x26C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_JTAG_TCK                                               0x000 0x270 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_JTAG_TDO                                               0x000 0x274 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_RTC                                                    0x000 0x278 0x000 0x0 0x0
+
+#endif /* __DTS_IMX8MQ_PINFUNC_H */
diff --git a/arch/arm/dts/imx8mq.dtsi b/arch/arm/dts/imx8mq.dtsi
new file mode 100644
index 0000000000..c67438a48e
--- /dev/null
+++ b/arch/arm/dts/imx8mq.dtsi
@@ -0,0 +1,624 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2017 NXP
+ * Copyright (C) 2017 Pengutronix, Lucas Stach <kernel at pengutronix.de>
+ */
+
+#include <dt-bindings/clock/imx8mq-clock.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "imx8mq-pinfunc.h"
+
+/* first 128 KiB of memory are owned by ATF */
+/memreserve/ 0x40000000 0x00020000;
+
+/ {
+	/* This should really be the GPC, but we need a driver for this first */
+	interrupt-parent = <&gic>;
+
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	aliases {
+		i2c0 = &i2c1;
+		i2c1 = &i2c2;
+		i2c2 = &i2c3;
+		i2c3 = &i2c4;
+		serial0 = &uart1;
+		serial1 = &uart2;
+		serial2 = &uart3;
+		serial3 = &uart4;
+		gpio0 = &gpio1;
+		gpio1 = &gpio2;
+		gpio2 = &gpio3;
+		gpio3 = &gpio4;
+		gpio4 = &gpio5;
+		mmc0 = &usdhc1;
+		mmc1 = &usdhc2;
+	};
+
+	ckil: clk-ckil {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <32768>;
+		clock-output-names = "ckil";
+	};
+
+	osc_25m: clk-osc-25m {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <25000000>;
+		clock-output-names = "osc_25m";
+	};
+
+	osc_27m: clk-osc-27m {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <27000000>;
+		clock-output-names = "osc_27m";
+	};
+
+	clk_ext1: clk-ext1 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <133000000>;
+		clock-output-names = "clk_ext1";
+	};
+
+	clk_ext2: clk-ext2 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <133000000>;
+		clock-output-names = "clk_ext2";
+	};
+
+	clk_ext3: clk-ext3 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <133000000>;
+		clock-output-names = "clk_ext3";
+	};
+
+	clk_ext4: clk-ext4 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency= <133000000>;
+		clock-output-names = "clk_ext4";
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		A53_0: cpu at 0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x0>;
+			enable-method = "psci";
+			next-level-cache = <&A53_L2>;
+		};
+
+		A53_1: cpu at 1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x1>;
+			enable-method = "psci";
+			next-level-cache = <&A53_L2>;
+		};
+
+		A53_2: cpu at 2 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x2>;
+			enable-method = "psci";
+			next-level-cache = <&A53_L2>;
+		};
+
+		A53_3: cpu at 3 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x3>;
+			enable-method = "psci";
+			next-level-cache = <&A53_L2>;
+		};
+
+		A53_L2: l2-cache0 {
+			compatible = "cache";
+		};
+	};
+
+	psci {
+		compatible = "arm,psci-1.0";
+		method = "smc";
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */
+		             <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
+		             <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */
+		             <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */
+		interrupt-parent = <&gic>;
+		arm,no-tick-in-suspend;
+	};
+
+	display-subsystem {
+		compatible = "fsl,imx-display-subsystem";
+		ports = <&dcss_disp0>;
+	};
+
+	peripherals at 0 {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0x0 0x0 0x0 0x3e000000>;
+
+		bus at 30000000 { /* AIPS1 */
+			compatible = "fsl,imx8mq-aips-bus", "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x30000000 0x30000000 0x400000>;
+
+			gpio1: gpio at 30200000 {
+				compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
+				reg = <0x30200000 0x10000>;
+				interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
+				             <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+			};
+
+			gpio2: gpio at 30210000 {
+				compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
+				reg = <0x30210000 0x10000>;
+				interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
+				        <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+			};
+
+			gpio3: gpio at 30220000 {
+				compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
+				reg = <0x30220000 0x10000>;
+				interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
+				        <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+			};
+
+			gpio4: gpio at 30230000 {
+				compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
+				reg = <0x30230000 0x10000>;
+				interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
+				                <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+			};
+
+			gpio5: gpio at 30240000 {
+				compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
+				reg = <0x30240000 0x10000>;
+				interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
+				        <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+			};
+
+			iomuxc: iomuxc at 30330000 {
+				compatible = "fsl,imx8mq-iomuxc";
+				reg = <0x30330000 0x10000>;
+			};
+
+			gpr: iomuxc-gpr at 30340000 {
+				compatible = "fsl,imx8mq-iomuxc-gpr", "syscon";
+				reg = <0x30340000 0x10000>;
+			};
+
+			ocotp: ocotp at 30350000 {
+				compatible = "fsl,imx8mq-ocotp";
+				reg = <0x30350000 0x10000>;
+				clocks = <&clk IMX8MQ_CLK_OCOTP_ROOT>;
+			};
+
+			anatop: anatop at 30360000 {
+				compatible = "fsl,imx8mq-anatop", "syscon";
+				reg = <0x30360000 0x10000>;
+				interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
+			clk: clock-controller at 30380000 {
+				compatible = "fsl,imx8mq-ccm";
+				reg = <0x30380000 0x10000>;
+				interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
+				             <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+				#clock-cells = <1>;
+				clocks = <&ckil>, <&osc_25m>, <&osc_27m>,
+				         <&clk_ext1>, <&clk_ext2>,
+				         <&clk_ext3>, <&clk_ext4>;
+				clock-names = "ckil", "osc_25m", "osc_27m",
+				              "clk_ext1", "clk_ext2",
+				              "clk_ext3", "clk_ext4";
+			};
+
+			wdog1: watchdog at 30280000 {
+				compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
+				reg = <0x30280000 0x10000>;
+				interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MQ_CLK_WDOG1_ROOT>;
+				status = "disabled";
+			};
+
+			wdog2: watchdog at 30290000 {
+				compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
+				reg = <0x30290000 0x10000>;
+				interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MQ_CLK_WDOG2_ROOT>;
+				status = "disabled";
+			};
+
+			wdog3: watchdog at 302a0000 {
+				compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
+				reg = <0x302a0000 0x10000>;
+				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MQ_CLK_WDOG3_ROOT>;
+				status = "disabled";
+			};
+		};
+
+		bus at 30400000 { /* AIPS2 */
+			compatible = "fsl,imx8mq-aips-bus", "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x30400000 0x30400000 0x400000>;
+		};
+
+		bus at 30800000 { /* AIPS3 */
+			compatible = "fsl,imx8mq-aips-bus", "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x30800000 0x30800000 0x400000>;
+
+			uart1: serial at 30860000 {
+				compatible = "fsl,imx8mq-uart",
+				             "fsl,imx6q-uart";
+				reg = <0x30860000 0x10000>;
+				interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MQ_CLK_UART1_ROOT>,
+				         <&clk IMX8MQ_CLK_UART1_ROOT>;
+				clock-names = "ipg", "per";
+				status = "disabled";
+			};
+
+			uart3: serial at 30880000 {
+				compatible = "fsl,imx8mq-uart",
+				             "fsl,imx6q-uart";
+				reg = <0x30880000 0x10000>;
+				interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MQ_CLK_UART3_ROOT>,
+				         <&clk IMX8MQ_CLK_UART3_ROOT>;
+				clock-names = "ipg", "per";
+				status = "disabled";
+			};
+
+			uart2: serial at 30890000 {
+				compatible = "fsl,imx8mq-uart",
+				             "fsl,imx6q-uart";
+				reg = <0x30890000 0x10000>;
+				interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MQ_CLK_UART2_ROOT>,
+				         <&clk IMX8MQ_CLK_UART2_ROOT>;
+				clock-names = "ipg", "per";
+				status = "disabled";
+			};
+
+			i2c1: i2c at 30a20000 {
+				compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
+				reg = <0x30a20000 0x10000>;
+				interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MQ_CLK_I2C1_ROOT>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+
+			i2c2: i2c at 30a30000 {
+				compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
+				reg = <0x30a30000 0x10000>;
+				interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MQ_CLK_I2C2_ROOT>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+
+			i2c3: i2c at 30a40000 {
+				compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
+				reg = <0x30a40000 0x10000>;
+				interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MQ_CLK_I2C3_ROOT>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+
+			i2c4: i2c at 30a50000 {
+				compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
+				reg = <0x30a50000 0x10000>;
+				interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MQ_CLK_I2C4_ROOT>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+
+			uart4: serial at 30a60000 {
+				compatible = "fsl,imx8mq-uart",
+				             "fsl,imx6q-uart";
+				reg = <0x30a60000 0x10000>;
+				interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MQ_CLK_UART4_ROOT>,
+				         <&clk IMX8MQ_CLK_UART4_ROOT>;
+				clock-names = "ipg", "per";
+				status = "disabled";
+			};
+
+			usdhc1: usdhc at 30b40000 {
+				compatible = "fsl,imx8mq-usdhc",
+				             "fsl,imx7d-usdhc";
+				reg = <0x30b40000 0x10000>;
+				interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MQ_CLK_DUMMY>,
+				         <&clk IMX8MQ_CLK_NAND_USDHC_BUS_DIV>,
+				         <&clk IMX8MQ_CLK_USDHC1_ROOT>;
+				clock-names = "ipg", "ahb", "per";
+				fsl,tuning-start-tap = <20>;
+				fsl,tuning-step = <2>;
+				bus-width = <4>;
+				status = "disabled";
+			};
+
+			usdhc2: usdhc at 30b50000 {
+				compatible = "fsl,imx8mq-usdhc",
+				             "fsl,imx7d-usdhc";
+				reg = <0x30b50000 0x10000>;
+				interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MQ_CLK_DUMMY>,
+				         <&clk IMX8MQ_CLK_NAND_USDHC_BUS_DIV>,
+				         <&clk IMX8MQ_CLK_USDHC2_ROOT>;
+				clock-names = "ipg", "ahb", "per";
+				fsl,tuning-start-tap = <20>;
+				fsl,tuning-step = <2>;
+				bus-width = <4>;
+				status = "disabled";
+			};
+
+			fec1: ethernet at 30be0000 {
+				compatible = "fsl,imx8mq-fec", "fsl,imx6sx-fec";
+				reg = <0x30be0000 0x10000>;
+				interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+				             <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
+				             <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MQ_CLK_ENET1_ROOT>,
+				         <&clk IMX8MQ_CLK_ENET1_ROOT>,
+				         <&clk IMX8MQ_CLK_ENET_TIMER_DIV>,
+				         <&clk IMX8MQ_CLK_ENET_REF_DIV>,
+				         <&clk IMX8MQ_CLK_ENET_PHY_REF_DIV>;
+				clock-names = "ipg", "ahb", "ptp",
+				              "enet_clk_ref", "enet_out";
+				fsl,num-tx-queues = <3>;
+				fsl,num-rx-queues = <3>;
+				status = "disabled";
+			};
+		};
+
+		bus at 32c00000 { /* AIPS4 */
+			compatible = "fsl,imx8mq-aips-bus", "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x32c00000 0x32c00000 0x400000>;
+
+			hdmi: hdmi at 32c00000 {
+				compatible = "fsl,imx8mq-hdmi";
+				reg = <0x32c00000 0x33800>,	/* HDP registers */
+				      <0x32e40000 0x40000>;	/* HDP SEC register */
+				interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+				             <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-names = "plug_in", "plug_out";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+
+				port at 0 {
+					reg = <0>;
+					hdmi_disp: endpoint {
+						remote-endpoint = <&dcss_disp0_hdmi>;
+					};
+				};
+			};
+
+			dcss: dcss at 32e00000 {
+				compatible = "nxp,imx8mq-dcss";
+				reg = <0x32e00000 0x30000>;
+				interrupts = <3 IRQ_TYPE_LEVEL_HIGH>,
+				             <4 IRQ_TYPE_LEVEL_HIGH>,
+				             <5 IRQ_TYPE_LEVEL_HIGH>,
+				             <6 IRQ_TYPE_LEVEL_HIGH>,
+				             <8 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-names = "dpr_dc_ch0",
+				                  "dpr_dc_ch1",
+				                  "dpr_dc_ch2",
+				                  "ctx_ld",
+				                  "dtg_prg1";
+				interrupt-parent = <&irqsteer_dcss>;
+				clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>,
+				         <&clk IMX8MQ_CLK_DISP_AXI_ROOT>,
+				         <&clk IMX8MQ_CLK_DISP_RTRM_ROOT>,
+				         <&clk IMX8MQ_CLK_DC_PIXEL_DIV>,
+				         <&clk IMX8MQ_CLK_DISP_DTRC_DIV>;
+				clock-names = "apb", "axi", "rtrm",
+				              "pixel", "dtrc";
+				assigned-clocks = <&clk IMX8MQ_CLK_DC_PIXEL_SRC>,
+				                  <&clk IMX8MQ_CLK_DISP_AXI_SRC>,
+				                  <&clk IMX8MQ_CLK_DISP_RTRM_SRC>,
+				                  <&clk IMX8MQ_CLK_DISP_RTRM_PRE_DIV>;
+				assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>,
+				                         <&clk IMX8MQ_SYS1_PLL_800M>,
+				                         <&clk IMX8MQ_SYS1_PLL_800M>;
+				assigned-clock-rates = <594000000>,
+				                       <800000000>,
+				                       <400000000>,
+				                       <400000000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+
+				dcss_disp0: port at 0 {
+					reg = <0>;
+					dcss_disp0_hdmi: hdmi-endpoint {
+						remote-endpoint = <&hdmi_disp>;
+					};
+				};
+			};
+
+			irqsteer_dcss: interrupt-controller at 32e2d000 {
+				compatible = "nxp,imx-irqsteer";
+				reg = <0x32e2d000 0x1000>;
+				interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>;
+				clock-names = "ipg";
+				nxp,channel = <2>;
+				nxp,endian = <1>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+			};
+		};
+
+		gpu: gpu at 38000000 {
+			compatible = "vivante,gc";
+			reg = <0x38000000 0x40000>;
+			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk IMX8MQ_CLK_GPU_ROOT>,
+			         <&clk IMX8MQ_CLK_GPU_SHADER_DIV>,
+			         <&clk IMX8MQ_CLK_GPU_AXI_DIV>,
+			         <&clk IMX8MQ_CLK_GPU_AHB_DIV>;
+			clock-names = "core", "shader", "bus", "reg";
+
+			assigned-clocks = <&clk IMX8MQ_CLK_GPU_CORE_SRC>,
+			                  <&clk IMX8MQ_CLK_GPU_SHADER_SRC>,
+			                  <&clk IMX8MQ_CLK_GPU_AXI_SRC>,
+			                  <&clk IMX8MQ_CLK_GPU_AHB_SRC>;
+			assigned-clock-parents = <&clk IMX8MQ_GPU_PLL_OUT>,
+			                         <&clk IMX8MQ_GPU_PLL_OUT>,
+			                         <&clk IMX8MQ_GPU_PLL_OUT>,
+			                         <&clk IMX8MQ_GPU_PLL_OUT>;
+			assigned-clock-rates = <800000000>, <800000000>,
+			                       <800000000>, <800000000>;
+			//power-domains = <&gpu_pd>;
+		};
+
+		usb3_0: usb0 at 38100000 {
+			compatible = "fsl,imx8mq-dwc3";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x38100000 0x38100000 0x10000>;
+			clocks = <&clk IMX8MQ_CLK_USB1_CTRL_ROOT>;
+			clock-names = "usb1_ctrl_root_clk";
+			assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS_SRC>,
+			                  <&clk IMX8MQ_CLK_USB_CORE_REF_SRC>;
+			assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>,
+			                         <&clk IMX8MQ_SYS1_PLL_100M>;
+			assigned-clock-rates = <500000000>, <100000000>;
+			status = "disabled";
+
+			usb_dwc3_0: dwc3 at 38100000 {
+				compatible = "snps,dwc3";
+				reg = <0x38100000 0x10000>;
+				interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+				phys = <&usb3_phy0 0>, <&usb3_phy0 1>;
+				phy-names = "usb2-phy", "usb3-phy";
+				//power-domains = <&usb_otg1_pd>;
+				snps,power-down-scale = <2>;
+				usb3-resume-missing-cas;
+				status = "disabled";
+			};
+		};
+
+		usb3_phy0: phy at 381f0040 {
+			compatible = "fsl,imx8mq-usb-phy";
+			reg = <0x381f0040 0x40>;
+			clocks = <&clk IMX8MQ_CLK_USB1_PHY_ROOT>;
+			clock-names = "usb_phy_root_clk";
+			#phy-cells = <1>;
+
+			assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF_SRC>;
+			assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>;
+			assigned-clock-rates = <100000000>;
+
+			status = "disabled";
+		};
+
+		usb3_1: usb1 at 38200000 {
+			compatible = "fsl,imx8mq-dwc3";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x38200000 0x38200000 0x10000>;
+			clocks = <&clk IMX8MQ_CLK_USB2_CTRL_ROOT>;
+			clock-names = "usb2_ctrl_root_clk";
+			assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS_SRC>,
+			                <&clk IMX8MQ_CLK_USB_CORE_REF_SRC>;
+			assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>,
+			                        <&clk IMX8MQ_SYS1_PLL_100M>;
+			assigned-clock-rates = <500000000>, <100000000>;
+			status = "disabled";
+
+			usb_dwc3_1: dwc3 at 38200000 {
+				compatible = "snps,dwc3";
+				reg = <0x38200000 0x10000>;
+				interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+				phys = <&usb3_phy1 0>, <&usb3_phy1 1>;
+				phy-names = "usb2-phy", "usb3-phy";
+				//power-domains = <&usb_otg2_pd>;
+				snps,power-down-scale = <2>;
+				usb3-resume-missing-cas;
+				status = "disabled";
+			};
+		};
+
+		usb3_phy1: phy at 382f0040 {
+			compatible = "fsl,imx8mq-usb-phy";
+			reg = <0x382f0040 0x40>;
+			clocks = <&clk IMX8MQ_CLK_USB2_PHY_ROOT>;
+			clock-names = "usb_phy_root_clk";
+			#phy-cells = <1>;
+
+			assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF_SRC>;
+			assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>;
+			assigned-clock-rates = <100000000>;
+
+			status = "disabled";
+		};
+
+		gic: interrupt-controller at 38800000 {
+			compatible = "arm,gic-v3";
+			reg = <0x38800000 0x10000>,	/* GIC Dist */
+			      <0x38880000 0xc0000>,	/* GICR */
+			      <0x31000000 0x2000>,	/* GICC */
+			      <0x31010000 0x2000>,	/* GICV */
+			      <0x31020000 0x2000>;	/* GICH */
+			#interrupt-cells = <3>;
+			interrupt-controller;
+			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-parent = <&gic>;
+		};
+	};
+};
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index eb135c3f53..54078cc65b 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -170,6 +170,15 @@ config ARCH_IMX7
 	select COMMON_CLK_OF_PROVIDER
 	select ARCH_HAS_FEC_IMX
 
+config ARCH_IMX8MQ
+	bool
+	select CPU_V8
+	select PINCTRL_IMX_IOMUX_V3
+	select OFTREE
+	select SYS_SUPPORTS_64BIT_KERNEL
+	select COMMON_CLK_OF_PROVIDER
+	select ARCH_HAS_FEC_IMX
+
 config ARCH_VF610
 	bool
 	select ARCH_HAS_L2X0
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 8ec846ccef..a6385ff90b 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_ARCH_IMX6) += imx6.o usb-imx6.o
 CFLAGS_imx6.o := -march=armv7-a
 lwl-$(CONFIG_ARCH_IMX6) += imx6-mmdc.o
 obj-$(CONFIG_ARCH_IMX7) += imx7.o
+obj-$(CONFIG_ARCH_IMX8MQ) += imx8mq.o
 obj-$(CONFIG_ARCH_IMX_XLOAD) += xload.o
 obj-$(CONFIG_IMX_IIM)	+= iim.o
 obj-$(CONFIG_IMX_OCOTP)	+= ocotp.o
diff --git a/arch/arm/mach-imx/imx.c b/arch/arm/mach-imx/imx.c
index 9400105c66..e5fe4a2646 100644
--- a/arch/arm/mach-imx/imx.c
+++ b/arch/arm/mach-imx/imx.c
@@ -73,6 +73,8 @@ static int imx_soc_from_dt(void)
 		return IMX_CPU_IMX7;
 	if (of_machine_is_compatible("fsl,imx7d"))
 		return IMX_CPU_IMX7;
+	if (of_machine_is_compatible("fsl,imx8mq"))
+		return IMX_CPU_IMX8MQ;
 	if (of_machine_is_compatible("fsl,vf610"))
 		return IMX_CPU_VF610;
 
@@ -113,6 +115,8 @@ static int imx_init(void)
 		ret = imx6_init();
 	else if (cpu_is_mx7())
 		ret = imx7_init();
+	else if (cpu_is_mx8mq())
+		ret = imx8mq_init();
 	else if (cpu_is_vf610())
 		ret = 0;
 	else
diff --git a/arch/arm/mach-imx/imx8mq.c b/arch/arm/mach-imx/imx8mq.c
new file mode 100644
index 0000000000..a9bd9f444b
--- /dev/null
+++ b/arch/arm/mach-imx/imx8mq.c
@@ -0,0 +1,66 @@
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <init.h>
+#include <common.h>
+#include <io.h>
+#include <mach/generic.h>
+#include <mach/revision.h>
+#include <mach/imx8mq-regs.h>
+
+#define IMX8MQ_ROM_VERSION_A0	0x800
+#define IMX8MQ_ROM_VERSION_B0	0x83C
+
+#define MX8MQ_ANATOP_DIGPROG	0x6c
+
+static void imx8mq_silicon_revision(void)
+{
+	void __iomem *anatop = IOMEM(MX8MQ_ANATOP_BASE_ADDR);
+	uint32_t reg = readl(anatop + MX8MQ_ANATOP_DIGPROG);
+	uint32_t type = (reg >> 16) & 0xff;
+	uint32_t rom_version;
+	const char *cputypestr;
+
+	reg &= 0xff;
+
+	if (reg == IMX_CHIP_REV_1_0) {
+		/*
+		 * For B0 chip, the DIGPROG is not updated, still TO1.0.
+		 * we have to check ROM version further
+		 */
+		rom_version = readl(IOMEM(IMX8MQ_ROM_VERSION_A0));
+		if (rom_version != IMX_CHIP_REV_1_0) {
+			rom_version = readl(IOMEM(IMX8MQ_ROM_VERSION_B0));
+			if (rom_version >= IMX_CHIP_REV_2_0)
+				reg = IMX_CHIP_REV_1_0;
+		}
+	}
+
+	switch (type) {
+	case 0x82:
+		cputypestr = "i.MX8MQ";
+		break;
+	default:
+		cputypestr = "unknown i.MX8M";
+		break;
+	};
+
+	imx_set_silicon_revision(cputypestr, reg);
+}
+
+int imx8mq_init(void)
+{
+	imx8mq_silicon_revision();
+
+	return 0;
+}
diff --git a/arch/arm/mach-imx/include/mach/generic.h b/arch/arm/mach-imx/include/mach/generic.h
index f68dc875b0..ff93d944ed 100644
--- a/arch/arm/mach-imx/include/mach/generic.h
+++ b/arch/arm/mach-imx/include/mach/generic.h
@@ -34,6 +34,7 @@ int imx51_init(void);
 int imx53_init(void);
 int imx6_init(void);
 int imx7_init(void);
+int imx8mq_init(void);
 
 int imx1_devices_init(void);
 int imx21_devices_init(void);
@@ -191,6 +192,18 @@ extern unsigned int __imx_cpu_type;
 # define cpu_is_mx7()		(0)
 #endif
 
+#ifdef CONFIG_ARCH_IMX8MQ
+# ifdef imx_cpu_type
+#  undef imx_cpu_type
+#  define imx_cpu_type __imx_cpu_type
+# else
+#  define imx_cpu_type IMX_CPU_IMX8MQ
+# endif
+# define cpu_is_mx8mq()	(imx_cpu_type == IMX_CPU_IMX8MQ)
+#else
+# define cpu_is_mx8mq()	(0)
+#endif
+
 #ifdef CONFIG_ARCH_VF610
 # ifdef imx_cpu_type
 #  undef imx_cpu_type
diff --git a/arch/arm/mach-imx/include/mach/imx8mq-regs.h b/arch/arm/mach-imx/include/mach/imx8mq-regs.h
new file mode 100644
index 0000000000..6dac00107f
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/imx8mq-regs.h
@@ -0,0 +1,121 @@
+#ifndef __MACH_IMX8MQ_REGS_H
+#define __MACH_IMX8MQ_REGS_H
+
+#define MX8MQ_M4_BOOTROM_BASE_ADDR	0x007E0000
+
+#define MX8MQ_SAI1_BASE_ADDR		0x30010000
+#define MX8MQ_SAI6_BASE_ADDR		0x30030000
+#define MX8MQ_SAI5_BASE_ADDR		0x30040000
+#define MX8MQ_SAI4_BASE_ADDR		0x30050000
+#define MX8MQ_SPBA2_BASE_ADDR		0x300F0000
+#define MX8MQ_AIPS1_BASE_ADDR		0x301F0000
+#define MX8MQ_GPIO1_BASE_ADDR		0X30200000
+#define MX8MQ_GPIO2_BASE_ADDR		0x30210000
+#define MX8MQ_GPIO3_BASE_ADDR		0x30220000
+#define MX8MQ_GPIO4_BASE_ADDR		0x30230000
+#define MX8MQ_GPIO5_BASE_ADDR		0x30240000
+#define MX8MQ_ANA_TSENSOR_BASE_ADDR	0x30260000
+#define MX8MQ_ANA_OSC_BASE_ADDR		0x30270000
+#define MX8MQ_WDOG1_BASE_ADDR		0x30280000
+#define MX8MQ_WDOG2_BASE_ADDR		0x30290000
+#define MX8MQ_WDOG3_BASE_ADDR		0x302A0000
+#define MX8MQ_SDMA2_BASE_ADDR		0x302C0000
+#define MX8MQ_GPT1_BASE_ADDR		0x302D0000
+#define MX8MQ_GPT2_BASE_ADDR		0x302E0000
+#define MX8MQ_GPT3_BASE_ADDR		0x302F0000
+#define MX8MQ_ROMCP_BASE_ADDR		0x30310000
+#define MX8MQ_LCDIF_BASE_ADDR		0x30320000
+#define MX8MQ_IOMUXC_BASE_ADDR		0x30330000
+#define MX8MQ_IOMUXC_GPR_BASE_ADDR	0x30340000
+#define MX8MQ_OCOTP_BASE_ADDR		0x30350000
+#define MX8MQ_ANATOP_BASE_ADDR		0x30360000
+#define MX8MQ_SNVS_HP_BASE_ADDR		0x30370000
+#define MX8MQ_CCM_BASE_ADDR		0x30380000
+#define MX8MQ_SRC_BASE_ADDR		0x30390000
+#define MX8MQ_GPC_BASE_ADDR		0x303A0000
+#define MX8MQ_SEMAPHORE1_BASE_ADDR	0x303B0000
+#define MX8MQ_SEMAPHORE2_BASE_ADDR	0x303C0000
+#define MX8MQ_RDC_BASE_ADDR		0x303D0000
+#define MX8MQ_CSU_BASE_ADDR		0x303E0000
+
+#define MX8MQ_AIPS2_BASE_ADDR		0x305F0000
+#define MX8MQ_PWM1_BASE_ADDR		0x30660000
+#define MX8MQ_PWM2_BASE_ADDR		0x30670000
+#define MX8MQ_PWM3_BASE_ADDR		0x30680000
+#define MX8MQ_PWM4_BASE_ADDR		0x30690000
+#define MX8MQ_SYSCNT_RD_BASE_ADDR	0x306A0000
+#define MX8MQ_SYSCNT_CMP_BASE_ADDR	0x306B0000
+#define MX8MQ_SYSCNT_CTRL_BASE_ADDR	0x306C0000
+#define MX8MQ_GPT6_BASE_ADDR		0x306E0000
+#define MX8MQ_GPT5_BASE_ADDR		0x306F0000
+#define MX8MQ_GPT4_BASE_ADDR		0x30700000
+#define MX8MQ_PERFMON1_BASE_ADDR	0x307C0000
+#define MX8MQ_PERFMON2_BASE_ADDR	0x307D0000
+#define MX8MQ_QOSC_BASE_ADDR		0x307F0000
+
+#define MX8MQ_SPDIF1_BASE_ADDR		0x30810000
+#define MX8MQ_ECSPI1_BASE_ADDR		0x30820000
+#define MX8MQ_ECSPI2_BASE_ADDR		0x30830000
+#define MX8MQ_ECSPI3_BASE_ADDR		0x30840000
+#define MX8MQ_UART1_BASE_ADDR		0x30860000
+#define MX8MQ_UART3_BASE_ADDR		0x30880000
+#define MX8MQ_UART2_BASE_ADDR		0x30890000
+#define MX8MQ_SPDIF2_BASE_ADDR		0x308A0000
+#define MX8MQ_SAI2_BASE_ADDR		0x308B0000
+#define MX8MQ_SAI3_BASE_ADDR		0x308C0000
+#define MX8MQ_SPBA1_BASE_ADDR		0x308F0000
+#define MX8MQ_CAAM_BASE_ADDR		0x30900000
+#define MX8MQ_AIPS3_BASE_ADDR		0x309F0000
+#define MX8MQ_MIPI_PHY_BASE_ADDR	0x30A00000
+#define MX8MQ_MIPI_DSI_BASE_ADDR	0x30A10000
+#define MX8MQ_I2C1_BASE_ADDR		0x30A20000
+#define MX8MQ_I2C2_BASE_ADDR		0x30A30000
+#define MX8MQ_I2C3_BASE_ADDR		0x30A40000
+#define MX8MQ_I2C4_BASE_ADDR		0x30A50000
+#define MX8MQ_UART4_BASE_ADDR		0x30A60000
+#define MX8MQ_MIPI_CSI_BASE_ADDR	0x30A70000
+#define MX8MQ_MIPI_CSI_PHY1_BASE_ADDR	0x30A80000
+#define MX8MQ_CSI1_BASE_ADDR		0x30A90000
+#define MX8MQ_MU_A_BASE_ADDR		0x30AA0000
+#define MX8MQ_MU_B_BASE_ADDR		0x30AB0000
+#define MX8MQ_SEMAPHOR_HS_BASE_ADDR	0x30AC0000
+#define MX8MQ_USDHC1_BASE_ADDR		0x30B40000
+#define MX8MQ_USDHC2_BASE_ADDR		0x30B50000
+#define MX8MQ_MIPI_CS2_BASE_ADDR	0x30B60000
+#define MX8MQ_MIPI_CSI_PHY2_BASE_ADDR	0x30B70000
+#define MX8MQ_CSI2_BASE_ADDR		0x30B80000
+#define MX8MQ_QSPI0_BASE_ADDR		0x30BB0000
+#define MX8MQ_QSPI0_AMBA_BASE		0x08000000
+#define MX8MQ_SDMA1_BASE_ADDR		0x30BD0000
+#define MX8MQ_ENET1_BASE_ADDR		0x30BE0000
+
+#define MX8MQ_HDMI_CTRL_BASE_ADDR	0x32C00000
+#define MX8MQ_AIPS4_BASE_ADDR		0x32DF0000
+#define MX8MQ_DC1_BASE_ADDR		0x32E00000
+#define MX8MQ_DC2_BASE_ADDR		0x32E10000
+#define MX8MQ_DC3_BASE_ADDR		0x32E20000
+#define MX8MQ_HDMI_SEC_BASE_ADDR	0x32E40000
+#define MX8MQ_TZASC_BASE_ADDR		0x32F80000
+#define MX8MQ_MTR_BASE_ADDR		0x32FB0000
+#define MX8MQ_PLATFORM_CTRL_BASE_ADDR	0x32FE0000
+
+#define MX8MQ_MXS_APBH_BASE		0x33000000
+#define MX8MQ_MXS_GPMI_BASE		0x33002000
+#define MX8MQ_MXS_BCH_BASE		0x33004000
+
+#define MX8MQ_USB1_BASE_ADDR		0x38100000
+#define MX8MQ_USB2_BASE_ADDR		0x38200000
+#define MX8MQ_USB1_PHY_BASE_ADDR	0x381F0000
+#define MX8MQ_USB2_PHY_BASE_ADDR	0x382F0000
+
+#define MX8MQ_MXS_LCDIF_BASE		LCDIF_BASE_ADDR
+
+#define MX8MQ_SRC_IPS_BASE_ADDR		0x30390000
+#define MX8MQ_SRC_DDRC_RCR_ADDR		0x30391000
+#define MX8MQ_SRC_DDRC2_RCR_ADDR	0x30391004
+
+#define MX8MQ_DDRC_DDR_SS_GPR0		0x3d000000
+#define MX8MQ_DDRC_IPS_BASE_ADDR(X)	(0x3d400000 + ((X) * 0x2000000))
+#define MX8MQ_DDR_CSD1_BASE_ADDR	0x40000000
+
+#endif /* __MACH_IMX8MQ_REGS_H */
diff --git a/arch/arm/mach-imx/include/mach/imx_cpu_types.h b/arch/arm/mach-imx/include/mach/imx_cpu_types.h
index f95ef6f135..754fb9822b 100644
--- a/arch/arm/mach-imx/include/mach/imx_cpu_types.h
+++ b/arch/arm/mach-imx/include/mach/imx_cpu_types.h
@@ -12,6 +12,7 @@
 #define IMX_CPU_IMX53	53
 #define IMX_CPU_IMX6	6
 #define IMX_CPU_IMX7	7
+#define IMX_CPU_IMX8MQ	8
 #define IMX_CPU_VF610	610
 
 #endif /* __MACH_IMX_CPU_TYPES_H */
diff --git a/include/dt-bindings/clock/imx8mq-clock.h b/include/dt-bindings/clock/imx8mq-clock.h
new file mode 100644
index 0000000000..7f880629e0
--- /dev/null
+++ b/include/dt-bindings/clock/imx8mq-clock.h
@@ -0,0 +1,629 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_IMX8MQ_H
+#define __DT_BINDINGS_CLOCK_IMX8MQ_H
+
+#define IMX8MQ_CLK_DUMMY		0
+#define IMX8MQ_CLK_32K			1
+#define IMX8MQ_CLK_25M			2
+#define IMX8MQ_CLK_27M			3
+#define IMX8MQ_CLK_EXT1			4
+#define IMX8MQ_CLK_EXT2			5
+#define IMX8MQ_CLK_EXT3			6
+#define IMX8MQ_CLK_EXT4			7
+
+/* ANAMIX PLL clocks */
+/* FRAC PLLs */
+/* ARM PLL */
+#define IMX8MQ_ARM_PLL_REF_SEL		8
+#define IMX8MQ_ARM_PLL_REF_DIV		9
+#define IMX8MQ_ARM_PLL			10
+#define IMX8MQ_ARM_PLL_BYPASS		11
+#define IMX8MQ_ARM_PLL_OUT		12
+
+/* GPU PLL */
+#define IMX8MQ_GPU_PLL_REF_SEL		13
+#define IMX8MQ_GPU_PLL_REF_DIV		14
+#define IMX8MQ_GPU_PLL			15
+#define IMX8MQ_GPU_PLL_BYPASS		16
+#define IMX8MQ_GPU_PLL_OUT		17
+
+/* VPU PLL */
+#define IMX8MQ_VPU_PLL_REF_SEL		18
+#define IMX8MQ_VPU_PLL_REF_DIV		19
+#define IMX8MQ_VPU_PLL			20
+#define IMX8MQ_VPU_PLL_BYPASS		21
+#define IMX8MQ_VPU_PLL_OUT		22
+
+/* AUDIO PLL1 */
+#define IMX8MQ_AUDIO_PLL1_REF_SEL	23
+#define IMX8MQ_AUDIO_PLL1_REF_DIV	24
+#define IMX8MQ_AUDIO_PLL1		25
+#define IMX8MQ_AUDIO_PLL1_BYPASS	26
+#define IMX8MQ_AUDIO_PLL1_OUT		27
+
+/* AUDIO PLL2 */
+#define IMX8MQ_AUDIO_PLL2_REF_SEL	28
+#define IMX8MQ_AUDIO_PLL2_REF_DIV	29
+#define IMX8MQ_AUDIO_PLL2		30
+#define IMX8MQ_AUDIO_PLL2_BYPASS	31
+#define IMX8MQ_AUDIO_PLL2_OUT		32
+
+/* VIDEO PLL1 */
+#define IMX8MQ_VIDEO_PLL1_REF_SEL	33
+#define IMX8MQ_VIDEO_PLL1_REF_DIV	34
+#define IMX8MQ_VIDEO_PLL1		35
+#define IMX8MQ_VIDEO_PLL1_BYPASS	36
+#define IMX8MQ_VIDEO_PLL1_OUT		37
+
+/* SYS1 PLL */
+#define IMX8MQ_SYS1_PLL1_REF_SEL	38
+#define IMX8MQ_SYS1_PLL1_REF_DIV	39
+#define IMX8MQ_SYS1_PLL1		40
+#define IMX8MQ_SYS1_PLL1_OUT		41
+#define IMX8MQ_SYS1_PLL1_OUT_DIV	42
+#define IMX8MQ_SYS1_PLL2		43
+#define IMX8MQ_SYS1_PLL2_DIV		44
+#define IMX8MQ_SYS1_PLL2_OUT		45
+
+/* SYS2 PLL */
+#define IMX8MQ_SYS2_PLL1_REF_SEL	46
+#define IMX8MQ_SYS2_PLL1_REF_DIV	47
+#define IMX8MQ_SYS2_PLL1		48
+#define IMX8MQ_SYS2_PLL1_OUT		49
+#define IMX8MQ_SYS2_PLL1_OUT_DIV	50
+#define IMX8MQ_SYS2_PLL2		51
+#define IMX8MQ_SYS2_PLL2_DIV		52
+#define IMX8MQ_SYS2_PLL2_OUT		53
+
+/* SYS3 PLL */
+#define IMX8MQ_SYS3_PLL1_REF_SEL	54
+#define IMX8MQ_SYS3_PLL1_REF_DIV	55
+#define IMX8MQ_SYS3_PLL1		56
+#define IMX8MQ_SYS3_PLL1_OUT		57
+#define IMX8MQ_SYS3_PLL1_OUT_DIV	58
+#define IMX8MQ_SYS3_PLL2		59
+#define IMX8MQ_SYS3_PLL2_DIV		60
+#define IMX8MQ_SYS3_PLL2_OUT		61
+
+/* DRAM PLL */
+#define IMX8MQ_DRAM_PLL1_REF_SEL	62
+#define IMX8MQ_DRAM_PLL1_REF_DIV	63
+#define IMX8MQ_DRAM_PLL1		64
+#define IMX8MQ_DRAM_PLL1_OUT		65
+#define IMX8MQ_DRAM_PLL1_OUT_DIV	66
+#define IMX8MQ_DRAM_PLL2		67
+#define IMX8MQ_DRAM_PLL2_DIV		68
+#define IMX8MQ_DRAM_PLL2_OUT		69
+
+/* SYS PLL DIV */
+#define IMX8MQ_SYS1_PLL_40M		70
+#define IMX8MQ_SYS1_PLL_80M		71
+#define IMX8MQ_SYS1_PLL_100M		72
+#define IMX8MQ_SYS1_PLL_133M		73
+#define IMX8MQ_SYS1_PLL_160M		74
+#define IMX8MQ_SYS1_PLL_200M		75
+#define IMX8MQ_SYS1_PLL_266M		76
+#define IMX8MQ_SYS1_PLL_400M		77
+#define IMX8MQ_SYS1_PLL_800M		78
+
+#define IMX8MQ_SYS2_PLL_50M		79
+#define IMX8MQ_SYS2_PLL_100M		80
+#define IMX8MQ_SYS2_PLL_125M		81
+#define IMX8MQ_SYS2_PLL_166M		82
+#define IMX8MQ_SYS2_PLL_200M		83
+#define IMX8MQ_SYS2_PLL_250M		84
+#define IMX8MQ_SYS2_PLL_333M		85
+#define IMX8MQ_SYS2_PLL_500M		86
+#define IMX8MQ_SYS2_PLL_1000M		87
+
+/* CCM ROOT clocks */
+/* A53 */
+#define IMX8MQ_CLK_A53_SRC		88
+#define IMX8MQ_CLK_A53_CG		89
+#define IMX8MQ_CLK_A53_DIV		90
+/* M4 */
+#define IMX8MQ_CLK_M4_SRC		91
+#define IMX8MQ_CLK_M4_CG		92
+#define IMX8MQ_CLK_M4_DIV		93
+/* VPU */
+#define IMX8MQ_CLK_VPU_SRC		94
+#define IMX8MQ_CLK_VPU_CG		95
+#define IMX8MQ_CLK_VPU_DIV		96
+/* GPU CORE */
+#define IMX8MQ_CLK_GPU_CORE_SRC		97
+#define IMX8MQ_CLK_GPU_CORE_CG		98
+#define IMX8MQ_CLK_GPU_CORE_DIV		99
+/* GPU SHADER */
+#define IMX8MQ_CLK_GPU_SHADER_SRC	100
+#define IMX8MQ_CLK_GPU_SHADER_CG	101
+#define IMX8MQ_CLK_GPU_SHADER_DIV	102
+
+/* BUS TYPE */
+/* MAIN AXI */
+#define IMX8MQ_CLK_MAIN_AXI_SRC		103
+#define IMX8MQ_CLK_MAIN_AXI_CG		104
+#define IMX8MQ_CLK_MAIN_AXI_PRE_DIV	105
+#define IMX8MQ_CLK_MAIN_AXI_DIV		106
+/* ENET AXI */
+#define IMX8MQ_CLK_ENET_AXI_SRC		107
+#define IMX8MQ_CLK_ENET_AXI_CG		108
+#define IMX8MQ_CLK_ENET_AXI_PRE_DIV	109
+#define IMX8MQ_CLK_ENET_AXI_DIV		110
+/* NAND_USDHC_BUS */
+#define IMX8MQ_CLK_NAND_USDHC_BUS_SRC		111
+#define IMX8MQ_CLK_NAND_USDHC_BUS_CG		112
+#define IMX8MQ_CLK_NAND_USDHC_BUS_PRE_DIV	113
+#define IMX8MQ_CLK_NAND_USDHC_BUS_DIV		114
+/* VPU BUS */
+#define IMX8MQ_CLK_VPU_BUS_SRC			115
+#define IMX8MQ_CLK_VPU_BUS_CG			116
+#define IMX8MQ_CLK_VPU_BUS_PRE_DIV		117
+#define IMX8MQ_CLK_VPU_BUS_DIV			118
+/* DISP_AXI */
+#define IMX8MQ_CLK_DISP_AXI_SRC			119
+#define IMX8MQ_CLK_DISP_AXI_CG			120
+#define IMX8MQ_CLK_DISP_AXI_PRE_DIV		121
+#define IMX8MQ_CLK_DISP_AXI_DIV			122
+/* DISP APB */
+#define IMX8MQ_CLK_DISP_APB_SRC			123
+#define IMX8MQ_CLK_DISP_APB_CG			124
+#define IMX8MQ_CLK_DISP_APB_PRE_DIV		125
+#define IMX8MQ_CLK_DISP_APB_DIV			126
+/* DISP RTRM */
+#define IMX8MQ_CLK_DISP_RTRM_SRC		127
+#define IMX8MQ_CLK_DISP_RTRM_CG			128
+#define IMX8MQ_CLK_DISP_RTRM_PRE_DIV		129
+#define IMX8MQ_CLK_DISP_RTRM_DIV		130
+/* USB_BUS */
+#define IMX8MQ_CLK_USB_BUS_SRC			131
+#define IMX8MQ_CLK_USB_BUS_CG			132
+#define IMX8MQ_CLK_USB_BUS_PRE_DIV		133
+#define IMX8MQ_CLK_USB_BUS_DIV			134
+/* GPU_AXI */
+#define IMX8MQ_CLK_GPU_AXI_SRC			135
+#define IMX8MQ_CLK_GPU_AXI_CG			136
+#define IMX8MQ_CLK_GPU_AXI_PRE_DIV		137
+#define IMX8MQ_CLK_GPU_AXI_DIV			138
+/* GPU_AHB */
+#define IMX8MQ_CLK_GPU_AHB_SRC			139
+#define IMX8MQ_CLK_GPU_AHB_CG			140
+#define IMX8MQ_CLK_GPU_AHB_PRE_DIV		141
+#define IMX8MQ_CLK_GPU_AHB_DIV			142
+/* NOC */
+#define IMX8MQ_CLK_NOC_SRC			143
+#define IMX8MQ_CLK_NOC_CG			144
+#define IMX8MQ_CLK_NOC_PRE_DIV			145
+#define IMX8MQ_CLK_NOC_DIV			146
+/* NOC_APB */
+#define IMX8MQ_CLK_NOC_APB_SRC			147
+#define IMX8MQ_CLK_NOC_APB_CG			148
+#define IMX8MQ_CLK_NOC_APB_PRE_DIV		149
+#define IMX8MQ_CLK_NOC_APB_DIV			150
+
+/* AHB */
+#define IMX8MQ_CLK_AHB_SRC			151
+#define IMX8MQ_CLK_AHB_CG			152
+#define IMX8MQ_CLK_AHB_PRE_DIV			153
+#define IMX8MQ_CLK_AHB_DIV			154
+/* AUDIO AHB */
+#define IMX8MQ_CLK_AUDIO_AHB_SRC		155
+#define IMX8MQ_CLK_AUDIO_AHB_CG			156
+#define IMX8MQ_CLK_AUDIO_AHB_PRE_DIV		157
+#define IMX8MQ_CLK_AUDIO_AHB_DIV		158
+
+/* DRAM_ALT */
+#define IMX8MQ_CLK_DRAM_ALT_SRC			159
+#define IMX8MQ_CLK_DRAM_ALT_CG			160
+#define IMX8MQ_CLK_DRAM_ALT_PRE_DIV		161
+#define IMX8MQ_CLK_DRAM_ALT_DIV			162
+/* DRAM APB */
+#define IMX8MQ_CLK_DRAM_APB_SRC			163
+#define IMX8MQ_CLK_DRAM_APB_CG			164
+#define IMX8MQ_CLK_DRAM_APB_PRE_DIV		165
+#define IMX8MQ_CLK_DRAM_APB_DIV			166
+/* VPU_G1 */
+#define IMX8MQ_CLK_VPU_G1_SRC			167
+#define IMX8MQ_CLK_VPU_G1_CG			168
+#define IMX8MQ_CLK_VPU_G1_PRE_DIV		169
+#define IMX8MQ_CLK_VPU_G1_DIV			170
+/* VPU_G2 */
+#define IMX8MQ_CLK_VPU_G2_SRC			171
+#define IMX8MQ_CLK_VPU_G2_CG			172
+#define IMX8MQ_CLK_VPU_G2_PRE_DIV		173
+#define IMX8MQ_CLK_VPU_G2_DIV			174
+/* DISP_DTRC */
+#define IMX8MQ_CLK_DISP_DTRC_SRC		175
+#define IMX8MQ_CLK_DISP_DTRC_CG			176
+#define IMX8MQ_CLK_DISP_DTRC_PRE_DIV		177
+#define IMX8MQ_CLK_DISP_DTRC_DIV		178
+/* DISP_DC8000 */
+#define IMX8MQ_CLK_DISP_DC8000_SRC		179
+#define IMX8MQ_CLK_DISP_DC8000_CG		180
+#define IMX8MQ_CLK_DISP_DC8000_PRE_DIV		181
+#define IMX8MQ_CLK_DISP_DC8000_DIV		182
+/* PCIE_CTRL */
+#define IMX8MQ_CLK_PCIE1_CTRL_SRC		183
+#define IMX8MQ_CLK_PCIE1_CTRL_CG		184
+#define IMX8MQ_CLK_PCIE1_CTRL_PRE_DIV		185
+#define IMX8MQ_CLK_PCIE1_CTRL_DIV		186
+/* PCIE_PHY */
+#define IMX8MQ_CLK_PCIE1_PHY_SRC		187
+#define IMX8MQ_CLK_PCIE1_PHY_CG			188
+#define IMX8MQ_CLK_PCIE1_PHY_PRE_DIV		189
+#define IMX8MQ_CLK_PCIE1_PHY_DIV		190
+/* PCIE_AUX */
+#define IMX8MQ_CLK_PCIE1_AUX_SRC		191
+#define IMX8MQ_CLK_PCIE1_AUX_CG			192
+#define IMX8MQ_CLK_PCIE1_AUX_PRE_DIV		193
+#define IMX8MQ_CLK_PCIE1_AUX_DIV		194
+/* DC_PIXEL */
+#define IMX8MQ_CLK_DC_PIXEL_SRC			195
+#define IMX8MQ_CLK_DC_PIXEL_CG			196
+#define IMX8MQ_CLK_DC_PIXEL_PRE_DIV		197
+#define IMX8MQ_CLK_DC_PIXEL_DIV			198
+/* LCDIF_PIXEL */
+#define IMX8MQ_CLK_LCDIF_PIXEL_SRC		199
+#define IMX8MQ_CLK_LCDIF_PIXEL_CG		200
+#define IMX8MQ_CLK_LCDIF_PIXEL_PRE_DIV		201
+#define IMX8MQ_CLK_LCDIF_PIXEL_DIV		202
+/* SAI1~6 */
+#define IMX8MQ_CLK_SAI1_SRC			203
+#define IMX8MQ_CLK_SAI1_CG			204
+#define IMX8MQ_CLK_SAI1_PRE_DIV			205
+#define IMX8MQ_CLK_SAI1_DIV			206
+
+#define IMX8MQ_CLK_SAI2_SRC			207
+#define IMX8MQ_CLK_SAI2_CG			208
+#define IMX8MQ_CLK_SAI2_PRE_DIV			209
+#define IMX8MQ_CLK_SAI2_DIV			210
+
+#define IMX8MQ_CLK_SAI3_SRC			211
+#define IMX8MQ_CLK_SAI3_CG			212
+#define IMX8MQ_CLK_SAI3_PRE_DIV			213
+#define IMX8MQ_CLK_SAI3_DIV			214
+
+#define IMX8MQ_CLK_SAI4_SRC			215
+#define IMX8MQ_CLK_SAI4_CG			216
+#define IMX8MQ_CLK_SAI4_PRE_DIV			217
+#define IMX8MQ_CLK_SAI4_DIV			218
+
+#define IMX8MQ_CLK_SAI5_SRC			219
+#define IMX8MQ_CLK_SAI5_CG			220
+#define IMX8MQ_CLK_SAI5_PRE_DIV			221
+#define IMX8MQ_CLK_SAI5_DIV			222
+
+#define IMX8MQ_CLK_SAI6_SRC			223
+#define IMX8MQ_CLK_SAI6_CG			224
+#define IMX8MQ_CLK_SAI6_PRE_DIV			225
+#define IMX8MQ_CLK_SAI6_DIV			226
+/* SPDIF1 */
+#define IMX8MQ_CLK_SPDIF1_SRC			227
+#define IMX8MQ_CLK_SPDIF1_CG			228
+#define IMX8MQ_CLK_SPDIF1_PRE_DIV		229
+#define IMX8MQ_CLK_SPDIF1_DIV			230
+/* SPDIF2 */
+#define IMX8MQ_CLK_SPDIF2_SRC			231
+#define IMX8MQ_CLK_SPDIF2_CG			232
+#define IMX8MQ_CLK_SPDIF2_PRE_DIV		233
+#define IMX8MQ_CLK_SPDIF2_DIV			234
+/* ENET_REF */
+#define IMX8MQ_CLK_ENET_REF_SRC			235
+#define IMX8MQ_CLK_ENET_REF_CG			236
+#define IMX8MQ_CLK_ENET_REF_PRE_DIV		237
+#define IMX8MQ_CLK_ENET_REF_DIV			238
+/* ENET_TIMER */
+#define IMX8MQ_CLK_ENET_TIMER_SRC		239
+#define IMX8MQ_CLK_ENET_TIMER_CG		240
+#define IMX8MQ_CLK_ENET_TIMER_PRE_DIV		241
+#define IMX8MQ_CLK_ENET_TIMER_DIV		242
+/* ENET_PHY */
+#define IMX8MQ_CLK_ENET_PHY_REF_SRC		243
+#define IMX8MQ_CLK_ENET_PHY_REF_CG		244
+#define IMX8MQ_CLK_ENET_PHY_REF_PRE_DIV		245
+#define IMX8MQ_CLK_ENET_PHY_REF_DIV		246
+/* NAND */
+#define IMX8MQ_CLK_NAND_SRC			247
+#define IMX8MQ_CLK_NAND_CG			248
+#define IMX8MQ_CLK_NAND_PRE_DIV			249
+#define IMX8MQ_CLK_NAND_DIV			250
+/* QSPI */
+#define IMX8MQ_CLK_QSPI_SRC			251
+#define IMX8MQ_CLK_QSPI_CG			252
+#define IMX8MQ_CLK_QSPI_PRE_DIV			253
+#define IMX8MQ_CLK_QSPI_DIV			254
+/* USDHC1 */
+#define IMX8MQ_CLK_USDHC1_SRC			255
+#define IMX8MQ_CLK_USDHC1_CG			256
+#define IMX8MQ_CLK_USDHC1_PRE_DIV		257
+#define IMX8MQ_CLK_USDHC1_DIV			258
+/* USDHC2 */
+#define IMX8MQ_CLK_USDHC2_SRC			259
+#define IMX8MQ_CLK_USDHC2_CG			260
+#define IMX8MQ_CLK_USDHC2_PRE_DIV		261
+#define IMX8MQ_CLK_USDHC2_DIV			262
+/* I2C1 */
+#define IMX8MQ_CLK_I2C1_SRC			263
+#define IMX8MQ_CLK_I2C1_CG			264
+#define IMX8MQ_CLK_I2C1_PRE_DIV			265
+#define IMX8MQ_CLK_I2C1_DIV			266
+/* I2C2 */
+#define IMX8MQ_CLK_I2C2_SRC			267
+#define IMX8MQ_CLK_I2C2_CG			268
+#define IMX8MQ_CLK_I2C2_PRE_DIV			269
+#define IMX8MQ_CLK_I2C2_DIV			270
+/* I2C3 */
+#define IMX8MQ_CLK_I2C3_SRC			271
+#define IMX8MQ_CLK_I2C3_CG			272
+#define IMX8MQ_CLK_I2C3_PRE_DIV			273
+#define IMX8MQ_CLK_I2C3_DIV			274
+/* I2C4 */
+#define IMX8MQ_CLK_I2C4_SRC			275
+#define IMX8MQ_CLK_I2C4_CG			276
+#define IMX8MQ_CLK_I2C4_PRE_DIV			277
+#define IMX8MQ_CLK_I2C4_DIV			278
+/* UART1 */
+#define IMX8MQ_CLK_UART1_SRC			279
+#define IMX8MQ_CLK_UART1_CG			280
+#define IMX8MQ_CLK_UART1_PRE_DIV		281
+#define IMX8MQ_CLK_UART1_DIV			282
+/* UART2 */
+#define IMX8MQ_CLK_UART2_SRC			283
+#define IMX8MQ_CLK_UART2_CG			284
+#define IMX8MQ_CLK_UART2_PRE_DIV		285
+#define IMX8MQ_CLK_UART2_DIV			286
+/* UART3 */
+#define IMX8MQ_CLK_UART3_SRC			287
+#define IMX8MQ_CLK_UART3_CG			288
+#define IMX8MQ_CLK_UART3_PRE_DIV		289
+#define IMX8MQ_CLK_UART3_DIV			290
+/* UART4 */
+#define IMX8MQ_CLK_UART4_SRC			291
+#define IMX8MQ_CLK_UART4_CG			292
+#define IMX8MQ_CLK_UART4_PRE_DIV		293
+#define IMX8MQ_CLK_UART4_DIV			294
+/* USB_CORE_REF */
+#define IMX8MQ_CLK_USB_CORE_REF_SRC		295
+#define IMX8MQ_CLK_USB_CORE_REF_CG		296
+#define IMX8MQ_CLK_USB_CORE_REF_PRE_DIV		297
+#define IMX8MQ_CLK_USB_CORE_REF_DIV		298
+/* USB_PHY_REF */
+#define IMX8MQ_CLK_USB_PHY_REF_SRC		299
+#define IMX8MQ_CLK_USB_PHY_REF_CG		300
+#define IMX8MQ_CLK_USB_PHY_REF_PRE_DIV		301
+#define IMX8MQ_CLK_USB_PHY_REF_DIV		302
+/* ECSPI1 */
+#define IMX8MQ_CLK_ECSPI1_SRC			303
+#define IMX8MQ_CLK_ECSPI1_CG			304
+#define IMX8MQ_CLK_ECSPI1_PRE_DIV		305
+#define IMX8MQ_CLK_ECSPI1_DIV			306
+/* ECSPI2 */
+#define IMX8MQ_CLK_ECSPI2_SRC			307
+#define IMX8MQ_CLK_ECSPI2_CG			308
+#define IMX8MQ_CLK_ECSPI2_PRE_DIV		309
+#define IMX8MQ_CLK_ECSPI2_DIV			310
+/* PWM1 */
+#define IMX8MQ_CLK_PWM1_SRC			311
+#define IMX8MQ_CLK_PWM1_CG			312
+#define IMX8MQ_CLK_PWM1_PRE_DIV			313
+#define IMX8MQ_CLK_PWM1_DIV			314
+/* PWM2 */
+#define IMX8MQ_CLK_PWM2_SRC			315
+#define IMX8MQ_CLK_PWM2_CG			316
+#define IMX8MQ_CLK_PWM2_PRE_DIV			317
+#define IMX8MQ_CLK_PWM2_DIV			318
+/* PWM3 */
+#define IMX8MQ_CLK_PWM3_SRC			319
+#define IMX8MQ_CLK_PWM3_CG			320
+#define IMX8MQ_CLK_PWM3_PRE_DIV			321
+#define IMX8MQ_CLK_PWM3_DIV			322
+/* PWM4 */
+#define IMX8MQ_CLK_PWM4_SRC			323
+#define IMX8MQ_CLK_PWM4_CG			324
+#define IMX8MQ_CLK_PWM4_PRE_DIV			325
+#define IMX8MQ_CLK_PWM4_DIV			326
+/* GPT1 */
+#define IMX8MQ_CLK_GPT1_SRC			327
+#define IMX8MQ_CLK_GPT1_CG			328
+#define IMX8MQ_CLK_GPT1_PRE_DIV			329
+#define IMX8MQ_CLK_GPT1_DIV			330
+/* WDOG */
+#define IMX8MQ_CLK_WDOG_SRC			331
+#define IMX8MQ_CLK_WDOG_CG			332
+#define IMX8MQ_CLK_WDOG_PRE_DIV			333
+#define IMX8MQ_CLK_WDOG_DIV			334
+/* WRCLK */
+#define IMX8MQ_CLK_WRCLK_SRC			335
+#define IMX8MQ_CLK_WRCLK_CG			336
+#define IMX8MQ_CLK_WRCLK_PRE_DIV		337
+#define IMX8MQ_CLK_WRCLK_DIV			338
+/* DSI_CORE */
+#define IMX8MQ_CLK_DSI_CORE_SRC			339
+#define IMX8MQ_CLK_DSI_CORE_CG			340
+#define IMX8MQ_CLK_DSI_CORE_PRE_DIV		341
+#define IMX8MQ_CLK_DSI_CORE_DIV			342
+/* DSI_PHY */
+#define IMX8MQ_CLK_DSI_PHY_REF_SRC		343
+#define IMX8MQ_CLK_DSI_PHY_REF_CG		344
+#define IMX8MQ_CLK_DSI_PHY_REF_PRE_DIV		345
+#define IMX8MQ_CLK_DSI_PHY_REF_DIV		346
+/* DSI_DBI */
+#define IMX8MQ_CLK_DSI_DBI_SRC			347
+#define IMX8MQ_CLK_DSI_DBI_CG			348
+#define IMX8MQ_CLK_DSI_DBI_PRE_DIV		349
+#define IMX8MQ_CLK_DSI_DBI_DIV			350
+/*DSI_ESC */
+#define IMX8MQ_CLK_DSI_ESC_SRC			351
+#define IMX8MQ_CLK_DSI_ESC_CG			352
+#define IMX8MQ_CLK_DSI_ESC_PRE_DIV		353
+#define IMX8MQ_CLK_DSI_ESC_DIV			354
+/* CSI1_CORE */
+#define IMX8MQ_CLK_CSI1_CORE_SRC		355
+#define IMX8MQ_CLK_CSI1_CORE_CG			356
+#define  IMX8MQ_CLK_CSI1_CORE_PRE_DIV		357
+#define IMX8MQ_CLK_CSI1_CORE_DIV		358
+/* CSI1_PHY */
+#define IMX8MQ_CLK_CSI1_PHY_REF_SRC		359
+#define IMX8MQ_CLK_CSI1_PHY_REF_CG		360
+#define IMX8MQ_CLK_CSI1_PHY_REF_PRE_DIV		361
+#define IMX8MQ_CLK_CSI1_PHY_REF_DIV		362
+/* CSI_ESC */
+#define IMX8MQ_CLK_CSI1_ESC_SRC			363
+#define IMX8MQ_CLK_CSI1_ESC_CG			364
+#define IMX8MQ_CLK_CSI1_ESC_PRE_DIV		365
+#define IMX8MQ_CLK_CSI1_ESC_DIV			366
+/* CSI2_CORE */
+#define IMX8MQ_CLK_CSI2_CORE_SRC		367
+#define IMX8MQ_CLK_CSI2_CORE_CG			368
+#define IMX8MQ_CLK_CSI2_CORE_PRE_DIV		369
+#define IMX8MQ_CLK_CSI2_CORE_DIV		370
+/* CSI2_PHY */
+#define IMX8MQ_CLK_CSI2_PHY_REF_SRC		371
+#define IMX8MQ_CLK_CSI2_PHY_REF_CG		372
+#define IMX8MQ_CLK_CSI2_PHY_REF_PRE_DIV		373
+#define IMX8MQ_CLK_CSI2_PHY_REF_DIV		374
+/* CSI2_ESC */
+#define IMX8MQ_CLK_CSI2_ESC_SRC			375
+#define IMX8MQ_CLK_CSI2_ESC_CG			376
+#define IMX8MQ_CLK_CSI2_ESC_PRE_DIV		377
+#define IMX8MQ_CLK_CSI2_ESC_DIV			378
+/* PCIE2_CTRL */
+#define IMX8MQ_CLK_PCIE2_CTRL_SRC		379
+#define IMX8MQ_CLK_PCIE2_CTRL_CG		380
+#define IMX8MQ_CLK_PCIE2_CTRL_PRE_DIV		381
+#define IMX8MQ_CLK_PCIE2_CTRL_DIV		382
+/* PCIE2_PHY */
+#define IMX8MQ_CLK_PCIE2_PHY_SRC		383
+#define IMX8MQ_CLK_PCIE2_PHY_CG			384
+#define IMX8MQ_CLK_PCIE2_PHY_PRE_DIV		385
+#define IMX8MQ_CLK_PCIE2_PHY_DIV		386
+/* PCIE2_AUX */
+#define IMX8MQ_CLK_PCIE2_AUX_SRC		387
+#define IMX8MQ_CLK_PCIE2_AUX_CG			388
+#define IMX8MQ_CLK_PCIE2_AUX_PRE_DIV		389
+#define IMX8MQ_CLK_PCIE2_AUX_DIV		390
+/* ECSPI3 */
+#define IMX8MQ_CLK_ECSPI3_SRC			391
+#define IMX8MQ_CLK_ECSPI3_CG			392
+#define IMX8MQ_CLK_ECSPI3_PRE_DIV		393
+#define IMX8MQ_CLK_ECSPI3_DIV			394
+
+/* CCGR clocks */
+#define IMX8MQ_CLK_A53_ROOT			395
+#define IMX8MQ_CLK_DRAM_ROOT			396
+#define IMX8MQ_CLK_ECSPI1_ROOT			397
+#define IMX8MQ_CLK_ECSPI2_ROOT			398
+#define IMX8MQ_CLK_ECSPI3_ROOT			399
+#define IMX8MQ_CLK_ENET1_ROOT			400
+#define IMX8MQ_CLK_GPT1_ROOT			401
+#define IMX8MQ_CLK_I2C1_ROOT			402
+#define IMX8MQ_CLK_I2C2_ROOT			403
+#define IMX8MQ_CLK_I2C3_ROOT			404
+#define IMX8MQ_CLK_I2C4_ROOT			405
+#define IMX8MQ_CLK_M4_ROOT			406
+#define IMX8MQ_CLK_PCIE1_ROOT			407
+#define IMX8MQ_CLK_PCIE2_ROOT			408
+#define IMX8MQ_CLK_PWM1_ROOT			409
+#define IMX8MQ_CLK_PWM2_ROOT			410
+#define IMX8MQ_CLK_PWM3_ROOT			411
+#define IMX8MQ_CLK_PWM4_ROOT			412
+#define IMX8MQ_CLK_QSPI_ROOT			413
+#define IMX8MQ_CLK_SAI1_ROOT			414
+#define IMX8MQ_CLK_SAI2_ROOT			415
+#define IMX8MQ_CLK_SAI3_ROOT			416
+#define IMX8MQ_CLK_SAI4_ROOT			417
+#define IMX8MQ_CLK_SAI5_ROOT			418
+#define IMX8MQ_CLK_SAI6_ROOT			419
+#define IMX8MQ_CLK_UART1_ROOT			420
+#define IMX8MQ_CLK_UART2_ROOT			421
+#define IMX8MQ_CLK_UART3_ROOT			422
+#define IMX8MQ_CLK_UART4_ROOT			423
+#define IMX8MQ_CLK_USB1_CTRL_ROOT		424
+#define IMX8MQ_CLK_USB2_CTRL_ROOT		425
+#define IMX8MQ_CLK_USB1_PHY_ROOT		426
+#define IMX8MQ_CLK_USB2_PHY_ROOT		427
+#define IMX8MQ_CLK_USDHC1_ROOT			428
+#define IMX8MQ_CLK_USDHC2_ROOT			429
+#define IMX8MQ_CLK_WDOG1_ROOT			430
+#define IMX8MQ_CLK_WDOG2_ROOT			431
+#define IMX8MQ_CLK_WDOG3_ROOT			432
+#define IMX8MQ_CLK_GPU_ROOT			433
+#define IMX8MQ_CLK_HEVC_ROOT			434
+#define IMX8MQ_CLK_AVC_ROOT			435
+#define IMX8MQ_CLK_VP9_ROOT			436
+#define IMX8MQ_CLK_HEVC_INTER_ROOT		437
+#define IMX8MQ_CLK_DISP_ROOT			438
+#define IMX8MQ_CLK_HDMI_ROOT			439
+#define IMX8MQ_CLK_HDMI_PHY_ROOT		440
+#define IMX8MQ_CLK_VPU_DEC_ROOT			441
+#define IMX8MQ_CLK_CSI1_ROOT			442
+#define IMX8MQ_CLK_CSI2_ROOT			443
+#define IMX8MQ_CLK_RAWNAND_ROOT			444
+#define IMX8MQ_CLK_SDMA1_ROOT			445
+#define IMX8MQ_CLK_SDMA2_ROOT			446
+#define IMX8MQ_CLK_VPU_G1_ROOT			447
+#define IMX8MQ_CLK_VPU_G2_ROOT			448
+
+/* SCCG PLL GATE */
+#define IMX8MQ_SYS1_PLL_OUT			449
+#define IMX8MQ_SYS2_PLL_OUT			450
+#define IMX8MQ_SYS3_PLL_OUT			451
+#define IMX8MQ_DRAM_PLL_OUT			452
+
+#define IMX8MQ_GPT_3M_CLK			453
+
+#define IMX8MQ_CLK_IPG_ROOT			454
+#define IMX8MQ_CLK_IPG_AUDIO_ROOT		455
+#define IMX8MQ_CLK_SAI1_IPG			456
+#define IMX8MQ_CLK_SAI2_IPG			457
+#define IMX8MQ_CLK_SAI3_IPG			458
+#define IMX8MQ_CLK_SAI4_IPG			459
+#define IMX8MQ_CLK_SAI5_IPG			460
+#define IMX8MQ_CLK_SAI6_IPG			461
+
+/* DSI AHB/IPG clocks */
+/* rxesc clock */
+#define IMX8MQ_CLK_DSI_AHB_SRC                  462
+#define IMX8MQ_CLK_DSI_AHB_CG                   463
+#define IMX8MQ_CLK_DSI_AHB_PRE_DIV              464
+#define IMX8MQ_CLK_DSI_AHB_DIV                  465
+/* txesc clock */
+#define IMX8MQ_CLK_DSI_IPG_DIV                  466
+
+/* VIDEO2 PLL */
+#define IMX8MQ_VIDEO2_PLL1_REF_SEL		467
+#define IMX8MQ_VIDEO2_PLL1_REF_DIV		468
+#define IMX8MQ_VIDEO2_PLL1			469
+#define IMX8MQ_VIDEO2_PLL1_OUT			470
+#define IMX8MQ_VIDEO2_PLL1_OUT_DIV		471
+#define IMX8MQ_VIDEO2_PLL2			472
+#define IMX8MQ_VIDEO2_PLL2_DIV			473
+#define IMX8MQ_VIDEO2_PLL2_OUT			474
+#define IMX8MQ_CLK_TMU_ROOT			475
+
+/* Display root clocks */
+#define IMX8MQ_CLK_DISP_AXI_ROOT		476
+#define IMX8MQ_CLK_DISP_APB_ROOT		477
+#define IMX8MQ_CLK_DISP_RTRM_ROOT		478
+
+#define IMX8MQ_CLK_OCOTP_ROOT			479
+
+#define IMX8MQ_CLK_DRAM_ALT_ROOT		480
+#define IMX8MQ_CLK_DRAM_CORE			481
+
+#define IMX8MQ_CLK_MU_ROOT			482
+#define IMX8MQ_VIDEO2_PLL_OUT			483
+
+#define IMX8MQ_CLK_CLKO2_SRC			484
+#define IMX8MQ_CLK_CLKO2_CG			485
+#define IMX8MQ_CLK_CLKO2_PRE_DIV		486
+#define IMX8MQ_CLK_CLKO2_DIV			487
+
+#define IMX8MQ_CLK_NAND_USDHC_BUS_RAWNAND_CLK	488
+
+#define IMX8MQ_CLK_END				489
+#endif /* __DT_BINDINGS_CLOCK_IMX8MQ_H */
-- 
2.16.1



From m.grzeschik at pengutronix.de  Mon Mar 19 02:21:18 2018
From: m.grzeschik at pengutronix.de (Michael Grzeschik)
Date: Mon, 19 Mar 2018 10:21:18 +0100
Subject: [PATCH v2 0/2] Add support for kontron samx6i boards
Message-ID: <20180319092120.11773-1-m.grzeschik@pengutronix.de>

These patches add support for the kontron samx6i smarc modules.
The memory size gets selected by gpio setup in the lowlevel setup.
For this we add some lowlevel gpio input functions.

Michael Grzeschik (2):
  ARM: i.MX: Add lowlevel gpio input functions
  boards: samx6: add initial support for kontron samx6i

 arch/arm/boards/Makefile                           |   1 +
 arch/arm/boards/kontron-samx6i/Makefile            |   2 +
 arch/arm/boards/kontron-samx6i/board.c             | 103 +++++
 .../flash-header-samx6i-duallite.imxcfg            | 102 +++++
 .../kontron-samx6i/flash-header-samx6i-quad.imxcfg | 118 +++++
 arch/arm/boards/kontron-samx6i/lowlevel.c          |  66 +++
 arch/arm/boards/kontron-samx6i/mem.c               |  85 ++++
 arch/arm/configs/imx_v7_defconfig                  |   1 +
 arch/arm/dts/Makefile                              |   2 +
 arch/arm/dts/imx6dl-samx6i.dts                     |  20 +
 arch/arm/dts/imx6q-samx6i.dts                      |  20 +
 arch/arm/dts/imx6qdl-smarc-samx6i.dtsi             | 509 +++++++++++++++++++++
 arch/arm/mach-imx/Kconfig                          |   4 +
 arch/arm/mach-imx/include/mach/imx-gpio.h          |  46 +-
 images/Makefile.imx                                |  10 +
 15 files changed, 1084 insertions(+), 5 deletions(-)
 create mode 100644 arch/arm/boards/kontron-samx6i/Makefile
 create mode 100644 arch/arm/boards/kontron-samx6i/board.c
 create mode 100644 arch/arm/boards/kontron-samx6i/flash-header-samx6i-duallite.imxcfg
 create mode 100644 arch/arm/boards/kontron-samx6i/flash-header-samx6i-quad.imxcfg
 create mode 100644 arch/arm/boards/kontron-samx6i/lowlevel.c
 create mode 100644 arch/arm/boards/kontron-samx6i/mem.c
 create mode 100644 arch/arm/dts/imx6dl-samx6i.dts
 create mode 100644 arch/arm/dts/imx6q-samx6i.dts
 create mode 100644 arch/arm/dts/imx6qdl-smarc-samx6i.dtsi

-- 
2.16.1



From m.grzeschik at pengutronix.de  Mon Mar 19 02:21:19 2018
From: m.grzeschik at pengutronix.de (Michael Grzeschik)
Date: Mon, 19 Mar 2018 10:21:19 +0100
Subject: [PATCH v2 1/2] ARM: i.MX: Add lowlevel gpio input functions
In-Reply-To: <20180319092120.11773-1-m.grzeschik@pengutronix.de>
References: <20180319092120.11773-1-m.grzeschik@pengutronix.de>
Message-ID: <20180319092120.11773-2-m.grzeschik@pengutronix.de>

This adds the function to set direction input and read the values
in the header file for setting i.MX gpios early.

Signed-off-by: Michael Grzeschik <m.grzeschik at pengutronix.de>
---
 arch/arm/mach-imx/include/mach/imx-gpio.h | 46 +++++++++++++++++++++++++++----
 1 file changed, 41 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-imx/include/mach/imx-gpio.h b/arch/arm/mach-imx/include/mach/imx-gpio.h
index 5e673beef9..891c33a3f4 100644
--- a/arch/arm/mach-imx/include/mach/imx-gpio.h
+++ b/arch/arm/mach-imx/include/mach/imx-gpio.h
@@ -8,15 +8,21 @@
  * regular gpio functions outside of lowlevel code!
  */
 
-static inline void imx_gpio_direction_output(void __iomem *gdir, void __iomem *dr,
-		int gpio, int value)
+static inline void imx_gpio_direction(void __iomem *gdir, void __iomem *dr,
+		int gpio, int out, int value)
 {
 	uint32_t val;
 
 	val = readl(gdir);
-	val |= 1 << gpio;
+	if (out)
+		val |= 1 << gpio;
+	else
+		val &= ~(1 << gpio);
 	writel(val, gdir);
 
+	if (!out)
+		return;
+
 	val = readl(dr);
 	if (value)
 		val |= 1 << gpio;
@@ -28,7 +34,7 @@ static inline void imx_gpio_direction_output(void __iomem *gdir, void __iomem *d
 
 static inline void imx1_gpio_direction_output(void *base, int gpio, int value)
 {
-	imx_gpio_direction_output(base + 0x0, base + 0x1c, gpio, value);
+	imx_gpio_direction(base + 0x0, base + 0x1c, gpio, 1, value);
 }
 
 #define imx21_gpio_direction_output(base, gpio, value) imx1_gpio_direction_output(base, gpio,value)
@@ -36,7 +42,7 @@ static inline void imx1_gpio_direction_output(void *base, int gpio, int value)
 
 static inline void imx31_gpio_direction_output(void *base, int gpio, int value)
 {
-	imx_gpio_direction_output(base + 0x4, base + 0x0, gpio, value);
+	imx_gpio_direction(base + 0x4, base + 0x0, gpio, 1, value);
 }
 
 #define imx25_gpio_direction_output(base, gpio, value) imx31_gpio_direction_output(base, gpio,value)
@@ -45,4 +51,34 @@ static inline void imx31_gpio_direction_output(void *base, int gpio, int value)
 #define imx53_gpio_direction_output(base, gpio, value) imx31_gpio_direction_output(base, gpio,value)
 #define imx6_gpio_direction_output(base, gpio, value) imx31_gpio_direction_output(base, gpio,value)
 
+static inline void imx1_gpio_direction_input(void *base, int gpio, int value)
+{
+	imx_gpio_direction(base + 0x0, base + 0x1c, gpio, 0, 0);
+}
+
+#define imx21_gpio_direction_input(base, gpio, value) imx1_gpio_direction_input(base, gpio)
+#define imx27_gpio_direction_input(base, gpio, value) imx1_gpio_direction_input(base, gpio)
+
+static inline void imx31_gpio_direction_input(void *base, int gpio)
+{
+	imx_gpio_direction(base + 0x4, base + 0x0, gpio, 0, 0);
+}
+
+#define imx25_gpio_direction_input(base, gpio, value) imx31_gpio_direction_input(base, gpio)
+#define imx35_gpio_direction_input(base, gpio, value) imx31_gpio_direction_input(base, gpio)
+#define imx51_gpio_direction_input(base, gpio, value) imx31_gpio_direction_input(base, gpio)
+#define imx53_gpio_direction_input(base, gpio, value) imx31_gpio_direction_input(base, gpio)
+#define imx6_gpio_direction_input(base, gpio) imx31_gpio_direction_input(base, gpio)
+
+#define imx1_gpio_val(base, gpio) readl(base + 0x1c) & (1 << gpio) ? 1 : 0
+#define imx21_gpio_val(base, gpio) imx1_gpio_val(base, gpio)
+#define imx27_gpio_val(base, gpio) imx1_gpio_val(base, gpio)
+
+#define imx31_gpio_val(base, gpio) readl(base) & (1 << gpio) ? 1 : 0
+#define imx25_gpio_val(base, gpio) imx31_gpio_val(base, gpio)
+#define imx35_gpio_val(base, gpio) imx31_gpio_val(base, gpio)
+#define imx51_gpio_val(base, gpio) imx31_gpio_val(base, gpio)
+#define imx53_gpio_val(base, gpio) imx31_gpio_val(base, gpio)
+#define imx6_gpio_val(base, gpio) imx31_gpio_val(base, gpio)
+
 #endif /* __MACH_IMX_GPIO_H */
-- 
2.16.1



From m.grzeschik at pengutronix.de  Mon Mar 19 02:21:20 2018
From: m.grzeschik at pengutronix.de (Michael Grzeschik)
Date: Mon, 19 Mar 2018 10:21:20 +0100
Subject: [PATCH v2 2/2] boards: samx6: add initial support for kontron samx6i
In-Reply-To: <20180319092120.11773-1-m.grzeschik@pengutronix.de>
References: <20180319092120.11773-1-m.grzeschik@pengutronix.de>
Message-ID: <20180319092120.11773-3-m.grzeschik@pengutronix.de>

Signed-off-by: Michael Grzeschik <m.grzeschik at pengutronix.de>
---
v1 -> v2:
	- dropped SZ_4G
	- fixed and clean env prepraration in board.c
	- added compatible checks for initcalls
	- dropped clock gate in flash headers
	- added memory detection in lowlevel
	- merged imx6qdl-samx6i with imx6qdl-smarc-samx6i
	- fixed dts
	- use imx_esdctl_disable instead of dts disable

 arch/arm/boards/Makefile                           |   1 +
 arch/arm/boards/kontron-samx6i/Makefile            |   2 +
 arch/arm/boards/kontron-samx6i/board.c             | 103 +++++
 .../flash-header-samx6i-duallite.imxcfg            | 102 +++++
 .../kontron-samx6i/flash-header-samx6i-quad.imxcfg | 118 +++++
 arch/arm/boards/kontron-samx6i/lowlevel.c          |  66 +++
 arch/arm/boards/kontron-samx6i/mem.c               |  85 ++++
 arch/arm/configs/imx_v7_defconfig                  |   1 +
 arch/arm/dts/Makefile                              |   2 +
 arch/arm/dts/imx6dl-samx6i.dts                     |  20 +
 arch/arm/dts/imx6q-samx6i.dts                      |  20 +
 arch/arm/dts/imx6qdl-smarc-samx6i.dtsi             | 509 +++++++++++++++++++++
 arch/arm/mach-imx/Kconfig                          |   4 +
 images/Makefile.imx                                |  10 +
 14 files changed, 1043 insertions(+)
 create mode 100644 arch/arm/boards/kontron-samx6i/Makefile
 create mode 100644 arch/arm/boards/kontron-samx6i/board.c
 create mode 100644 arch/arm/boards/kontron-samx6i/flash-header-samx6i-duallite.imxcfg
 create mode 100644 arch/arm/boards/kontron-samx6i/flash-header-samx6i-quad.imxcfg
 create mode 100644 arch/arm/boards/kontron-samx6i/lowlevel.c
 create mode 100644 arch/arm/boards/kontron-samx6i/mem.c
 create mode 100644 arch/arm/dts/imx6dl-samx6i.dts
 create mode 100644 arch/arm/dts/imx6q-samx6i.dts
 create mode 100644 arch/arm/dts/imx6qdl-smarc-samx6i.dtsi

diff --git a/arch/arm/boards/Makefile b/arch/arm/boards/Makefile
index ca187ccb89..30f4c299f1 100644
--- a/arch/arm/boards/Makefile
+++ b/arch/arm/boards/Makefile
@@ -61,6 +61,7 @@ obj-$(CONFIG_MACH_IMX21ADS)			+= freescale-mx21-ads/
 obj-$(CONFIG_MACH_IMX233_OLINUXINO)		+= imx233-olinuxino/
 obj-$(CONFIG_MACH_IMX27ADS)			+= freescale-mx27-ads/
 obj-$(CONFIG_MACH_KINDLE3)			+= kindle3/
+obj-$(CONFIG_MACH_KONTRON_SAMX6I)		+= kontron-samx6i/
 obj-$(CONFIG_MACH_LENOVO_IX4_300D)		+= lenovo-ix4-300d/
 obj-$(CONFIG_MACH_LUBBOCK)			+= lubbock/
 obj-$(CONFIG_MACH_MAINSTONE)			+= mainstone/
diff --git a/arch/arm/boards/kontron-samx6i/Makefile b/arch/arm/boards/kontron-samx6i/Makefile
new file mode 100644
index 0000000000..816962241a
--- /dev/null
+++ b/arch/arm/boards/kontron-samx6i/Makefile
@@ -0,0 +1,2 @@
+obj-y += board.o mem.o
+lwl-y += lowlevel.o mem.o
diff --git a/arch/arm/boards/kontron-samx6i/board.c b/arch/arm/boards/kontron-samx6i/board.c
new file mode 100644
index 0000000000..01826b67d2
--- /dev/null
+++ b/arch/arm/boards/kontron-samx6i/board.c
@@ -0,0 +1,103 @@
+/*
+ * Copyright 2018 (C) Pengutronix, Michael Grzeschik <mgr at pengutronix.de>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#define pr_fmt(fmt) "samx6i: " fmt
+
+#include <malloc.h>
+#include <envfs.h>
+#include <environment.h>
+#include <bootsource.h>
+#include <common.h>
+#include <init.h>
+#include <of.h>
+#include <mach/bbu.h>
+#include <mach/esdctl.h>
+
+#include <asm/armlinux.h>
+
+resource_size_t samx6i_get_size(void);
+
+/*
+ * On this board the SDRAM size is always configured by pin selection.
+ */
+static int samx6i_sdram_fixup(void)
+{
+	if (!(of_machine_is_compatible("kontron,imx6q-samx6i") ||
+		of_machine_is_compatible("kontron,imx6dl-samx6i")))
+		return 0;
+
+	imx_esdctl_disable();
+
+	return 0;
+}
+postcore_initcall(samx6i_sdram_fixup);
+
+static int samx6i_mem_init(void)
+{
+	resource_size_t size = 0;
+
+	if (!(of_machine_is_compatible("kontron,imx6q-samx6i") ||
+		of_machine_is_compatible("kontron,imx6dl-samx6i")))
+		return 0;
+
+	size = samx6i_get_size();
+	if (size)
+		arm_add_mem_device("ram0", 0x10000000, size);
+
+	return 0;
+}
+mem_initcall(samx6i_mem_init);
+
+static int samx6i_devices_init(void)
+{
+	int ret;
+	char *environment_path, *envdev;
+	int flag_spi = 0, flag_mmc = 0;
+
+	if (!(of_machine_is_compatible("kontron,imx6q-samx6i") ||
+		of_machine_is_compatible("kontron,imx6dl-samx6i")))
+		return 0;
+
+	barebox_set_hostname("samx6i");
+
+	switch (bootsource_get()) {
+	case BOOTSOURCE_MMC:
+		environment_path = basprintf("/chosen/environment-sd%d",
+					       bootsource_get_instance() + 1);
+		envdev = "MMC";
+		flag_mmc = BBU_HANDLER_FLAG_DEFAULT;
+		break;
+	default:
+		environment_path = basprintf("/chosen/environment-spinor");
+		envdev = "SPI NOR flash";
+		flag_spi = BBU_HANDLER_FLAG_DEFAULT;
+		break;
+	}
+
+	ret = of_device_enable_path(environment_path);
+	if (ret < 0)
+		pr_warn("Failed to enable environment partition '%s' (%d)\n",
+			environment_path, ret);
+	free(environment_path);
+
+	pr_notice("Using environment in %s\n", envdev);
+
+	imx6_bbu_internal_spi_i2c_register_handler("m25p80",
+					"/dev/m25p0.bootloader",
+					flag_spi);
+
+	imx6_bbu_internal_mmc_register_handler("mmc3",
+					"/dev/mmc3.bootloader",
+					flag_mmc);
+
+	return 0;
+}
+device_initcall(samx6i_devices_init);
diff --git a/arch/arm/boards/kontron-samx6i/flash-header-samx6i-duallite.imxcfg b/arch/arm/boards/kontron-samx6i/flash-header-samx6i-duallite.imxcfg
new file mode 100644
index 0000000000..9906617083
--- /dev/null
+++ b/arch/arm/boards/kontron-samx6i/flash-header-samx6i-duallite.imxcfg
@@ -0,0 +1,102 @@
+soc imx6
+loadaddr 0x10000000
+dcdofs 0x400
+
+wm 32 0x020e0774 0x000c0000
+wm 32 0x020e0754 0x00000000
+
+wm 32 0x020e04ac 0x00000030
+wm 32 0x020e04b0 0x00000030
+
+wm 32 0x020e0464 0x00000030
+wm 32 0x020e0490 0x00000030
+wm 32 0x020e074c 0x00000030
+
+wm 32 0x020e0494 0x000c0030
+wm 32 0x020e04a4 0x00003000
+wm 32 0x020e04a8 0x00003000
+wm 32 0x020e04a0 0x00000000
+wm 32 0x020e04b4 0x00003030
+wm 32 0x020e04b8 0x00003030
+wm 32 0x020e076c 0x00000030
+
+wm 32 0x020e0750 0x00020000
+wm 32 0x020e04bc 0x00000038
+wm 32 0x020e04c0 0x00000038
+wm 32 0x020e04c4 0x00000038
+wm 32 0x020e04c8 0x00000038
+wm 32 0x020e04cc 0x00000038
+wm 32 0x020e04d0 0x00000038
+wm 32 0x020e04d4 0x00000038
+wm 32 0x020e04d8 0x00000038
+
+wm 32 0x020e0760 0x00020000
+wm 32 0x020e0764 0x00000030
+wm 32 0x020e0770 0x00000030
+wm 32 0x020e0778 0x00000030
+wm 32 0x020e077c 0x00000030
+wm 32 0x020e0780 0x00000030
+wm 32 0x020e0784 0x00000030
+wm 32 0x020e078c 0x00000030
+wm 32 0x020e0748 0x00000030
+
+wm 32 0x020e0470 0x00000030
+wm 32 0x020e0474 0x00000030
+wm 32 0x020e0478 0x00000030
+wm 32 0x020e047c 0x00000030
+wm 32 0x020e0480 0x00000030
+wm 32 0x020e0484 0x00000030
+wm 32 0x020e0488 0x00000030
+wm 32 0x020e048c 0x000C0030
+
+wm 32 0x021b0800 0xa1390003
+wm 32 0x021b4800 0xa1390003
+
+wm 32 0x021b080c 0x0040003c
+wm 32 0x021b0810 0x0032003e
+
+wm 32 0x021b083c 0x42350231
+wm 32 0x021b0840 0x021a0218
+wm 32 0x021b0848 0x4b4b4e49
+wm 32 0x021b0850 0x3f3f3035
+
+wm 32 0x021b081c 0x33333333
+wm 32 0x021b0820 0x33333333
+wm 32 0x021b0824 0x33333333
+wm 32 0x021b0828 0x33333333
+wm 32 0x021b481c 0x33333333
+wm 32 0x021b4820 0x33333333
+wm 32 0x021b4824 0x33333333
+wm 32 0x021b4828 0x33333333
+
+
+wm 32 0x021b08b8 0x00000800
+wm 32 0x021b48b8 0x00000800
+
+wm 32 0x021b0004 0x0002002d
+wm 32 0x021b0008 0x00333030
+wm 32 0x021b000c 0x696d5323
+wm 32 0x021b0010 0xb66e8c63
+wm 32 0x021b0014 0x01ff00db
+wm 32 0x021b0018 0x00001740
+wm 32 0x021b001c 0x00008000
+wm 32 0x021b002c 0x000026d2
+wm 32 0x021b0030 0x006d0e21
+wm 32 0x021b0040 0x00000027
+wm 32 0x021b0000 0x84190000
+wm 32 0x021b001c 0x04008032
+wm 32 0x021b001c 0x00008033
+wm 32 0x021b001c 0x00048031
+wm 32 0x021b001c 0x07208030
+wm 32 0x021b001c 0x04008040
+wm 32 0x021b0020 0x00005800
+wm 32 0x021b0818 0x00022227
+wm 32 0x021b4818 0x00022227
+wm 32 0x021b0004 0x0002556d
+wm 32 0x021b4004 0x00011006
+wm 32 0x021b001c 0x00000000
+
+wm 32 0x020e0010 0xf00000ff
+
+wm 32 0x020e0018 0x00070007
+wm 32 0x020e001c 0x00070007
diff --git a/arch/arm/boards/kontron-samx6i/flash-header-samx6i-quad.imxcfg b/arch/arm/boards/kontron-samx6i/flash-header-samx6i-quad.imxcfg
new file mode 100644
index 0000000000..7e6ffd7983
--- /dev/null
+++ b/arch/arm/boards/kontron-samx6i/flash-header-samx6i-quad.imxcfg
@@ -0,0 +1,118 @@
+soc imx6
+loadaddr 0x10000000
+dcdofs 0x400
+
+wm 32 0x020e05a8 0x00000030
+wm 32 0x020e05b0 0x00000030
+wm 32 0x020e0524 0x00000030
+wm 32 0x020e051c 0x00000030
+
+wm 32 0x020e0518 0x00000030
+wm 32 0x020e050c 0x00000030
+wm 32 0x020e05b8 0x00000030
+wm 32 0x020e05c0 0x00000030
+
+wm 32 0x020e05ac 0x00020030
+wm 32 0x020e05b4 0x00020030
+wm 32 0x020e0528 0x00020030
+wm 32 0x020e0520 0x00020030
+
+wm 32 0x020e0514 0x00020030
+wm 32 0x020e0510 0x00020030
+wm 32 0x020e05bc 0x00020030
+wm 32 0x020e05c4 0x00020030
+
+wm 32 0x020e056c 0x00020030
+wm 32 0x020e0578 0x00020030
+wm 32 0x020e0588 0x00020030
+wm 32 0x020e0594 0x00020030
+
+wm 32 0x020e057c 0x00020030
+wm 32 0x020e0590 0x00003000
+wm 32 0x020e0598 0x00003000
+wm 32 0x020e058c 0x00000000
+
+wm 32 0x020e059c 0x00003030
+wm 32 0x020e05a0 0x00003030
+wm 32 0x020e0784 0x00000030
+wm 32 0x020e0788 0x00000030
+
+wm 32 0x020e0794 0x00000030
+wm 32 0x020e079c 0x00000030
+wm 32 0x020e07a0 0x00000030
+wm 32 0x020e07a4 0x00000030
+
+wm 32 0x020e07a8 0x00000030
+wm 32 0x020e0748 0x00000030
+wm 32 0x020e074c 0x00000030
+wm 32 0x020e0750 0x00020000
+
+wm 32 0x020e0758 0x00000000
+wm 32 0x020e0774 0x00020000
+wm 32 0x020e078c 0x00000030
+wm 32 0x020e0798 0x000C0000
+
+wm 32 0x021b081c 0x33333333
+wm 32 0x021b0820 0x33333333
+wm 32 0x021b0824 0x33333333
+wm 32 0x021b0828 0x33333333
+
+wm 32 0x021b481c 0x33333333
+wm 32 0x021b4820 0x33333333
+wm 32 0x021b4824 0x33333333
+wm 32 0x021b4828 0x33333333
+
+wm 32 0x021b0018 0x00081740
+
+wm 32 0x021b001c 0x00008000
+wm 32 0x021b000c 0x898E7975
+wm 32 0x021b0010 0xFF538E64
+wm 32 0x021b0014 0x01FF00DD
+wm 32 0x021b002c 0x000026D2
+
+wm 32 0x021b0030 0x005B0E21
+wm 32 0x021b0008 0x09444040
+wm 32 0x021b0004 0x00025576
+/*  CS0_END = 4GB */
+wm 32 0x021b0040 0x0000007F
+
+wm 32 0x021b0000 0x841A0000
+
+wm 32 0x021b001c 0x04088032
+wm 32 0x021b001c 0x00008033
+wm 32 0x021b001c 0x00428031
+wm 32 0x021b001c 0x09408030
+
+wm 32 0x021b001c 0x04008040
+wm 32 0x021b0800 0xA1390003
+wm 32 0x021b4800 0xA1390003
+wm 32 0x021b0020 0x00007800
+wm 32 0x021b0818 0x00022227
+wm 32 0x021b4818 0x00022227
+
+wm 32 0x021b083c 0x42740304
+wm 32 0x021b0840 0x026e0265
+wm 32 0x021b483c 0x02750306
+wm 32 0x021b4840 0x02720244
+wm 32 0x021b0848 0x463d4041
+wm 32 0x021b4848 0x42413c47
+wm 32 0x021b0850 0x37414441
+wm 32 0x021b4850 0x4633473b
+
+wm 32 0x021b080c 0x0025001f
+wm 32 0x021b0810 0x00290027
+
+wm 32 0x021b480c 0x001f002b
+wm 32 0x021b4810 0x000f0029
+
+wm 32 0x021b08b8 0x00000800
+wm 32 0x021b48b8 0x00000800
+
+wm 32 0x021b001c 0x00000000
+wm 32 0x021b0404 0x00011006
+
+/* enable AXI cache for VDOA/VPU/IPU */
+wm 32 0x020e0010 0xF00000FF
+/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+wm 32 0x020e0018 0x007F007F
+wm 32 0x020e001c 0x007F007F
diff --git a/arch/arm/boards/kontron-samx6i/lowlevel.c b/arch/arm/boards/kontron-samx6i/lowlevel.c
new file mode 100644
index 0000000000..4113ddbb40
--- /dev/null
+++ b/arch/arm/boards/kontron-samx6i/lowlevel.c
@@ -0,0 +1,66 @@
+/*
+ * Copyright 2018 (C) Pengutronix, Michael Grzeschik <mgr at pengutronix.de>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <debug_ll.h>
+#include <common.h>
+#include <io.h>
+#include <asm/barebox-arm-head.h>
+#include <asm/barebox-arm.h>
+#include <asm/sections.h>
+#include <asm/cache.h>
+#include <asm/mmu.h>
+#include <mach/imx6.h>
+#include <mach/esdctl.h>
+
+resource_size_t samx6i_get_size(void);
+
+static inline void setup_uart(void)
+{
+	void __iomem *iomuxbase = (void *)MX6_IOMUXC_BASE_ADDR;
+
+	writel(0x4, iomuxbase + 0x016c);
+
+	imx6_ungate_all_peripherals();
+	imx6_uart_setup_ll();
+
+	putc_ll('>');
+}
+
+static void __noreturn start_imx6_samx6i_common(void *fdt_blob_fixed_offset)
+{
+	void *fdt;
+	resource_size_t size = 0;
+
+	size = samx6i_get_size();
+
+	imx6_cpu_lowlevel_init();
+	arm_setup_stack(0x00920000 - 8);
+
+	if (IS_ENABLED(CONFIG_DEBUG_LL))
+		setup_uart();
+
+	fdt = fdt_blob_fixed_offset - get_runtime_offset();
+
+	barebox_arm_entry(0x10000000, size, fdt);
+}
+
+extern char __dtb_imx6dl_samx6i_start[];
+extern char __dtb_imx6q_samx6i_start[];
+
+ENTRY_FUNCTION(start_imx6q_samx6i, r0, r1, r2)
+{
+	start_imx6_samx6i_common(__dtb_imx6q_samx6i_start);
+}
+
+ENTRY_FUNCTION(start_imx6dl_samx6i, r0, r1, r2)
+{
+	start_imx6_samx6i_common(__dtb_imx6dl_samx6i_start);
+}
diff --git a/arch/arm/boards/kontron-samx6i/mem.c b/arch/arm/boards/kontron-samx6i/mem.c
new file mode 100644
index 0000000000..ab9969e32c
--- /dev/null
+++ b/arch/arm/boards/kontron-samx6i/mem.c
@@ -0,0 +1,85 @@
+/*
+ * Copyright 2018 (C) Pengutronix, Michael Grzeschik <mgr at pengutronix.de>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/sizes.h>
+#include <common.h>
+#include <mach/iomux-mx6.h>
+#include <mach/imx-gpio.h>
+#include <mach/imx6.h>
+
+#define PCBVERSION_PIN IMX_GPIO_NR(2, 2)
+#define PCBID0_PIN IMX_GPIO_NR(6, 7)
+#define PCBID1_PIN IMX_GPIO_NR(6, 9)
+
+#define MX6S_PAD_NANDF_CLE__GPIO_6_7 \
+	IOMUX_PAD(0x0658, 0x0270, 5, 0x0000, 0, 0)
+#define MX6S_PAD_NANDF_WP_B__GPIO_6_9 \
+	IOMUX_PAD(0x0690, 0x02A8, 5, 0x0000, 0, 0)
+#define MX6S_PAD_NANDF_D2__GPIO_2_2 \
+	IOMUX_PAD(0x028c, 0x0674, 5, 0x0000, 0, 0)
+
+resource_size_t samx6i_get_size(void)
+{
+	resource_size_t size = 0;
+	int ver, id0, id1;
+	int cpu_type = __imx6_cpu_type();
+	void __iomem *iomuxbase = IOMEM(MX6_IOMUXC_BASE_ADDR);
+	void __iomem *gpio6 = IOMEM(MX6_GPIO6_BASE_ADDR);
+	void __iomem *gpio2 = IOMEM(MX6_GPIO2_BASE_ADDR);
+
+	if (cpu_type == IMX6_CPUTYPE_IMX6D ||
+			cpu_type == IMX6_CPUTYPE_IMX6Q) {
+		imx_setup_pad(iomuxbase, MX6Q_PAD_NANDF_CLE__GPIO_6_7);
+		imx_setup_pad(iomuxbase, MX6Q_PAD_NANDF_WP_B__GPIO_6_9);
+		imx_setup_pad(iomuxbase, MX6Q_PAD_NANDF_D2__GPIO_2_2);
+	} else if (cpu_type == IMX6_CPUTYPE_IMX6S ||
+			cpu_type == IMX6_CPUTYPE_IMX6DL) {
+		imx_setup_pad(iomuxbase, MX6S_PAD_NANDF_CLE__GPIO_6_7);
+		imx_setup_pad(iomuxbase, MX6S_PAD_NANDF_WP_B__GPIO_6_9);
+		imx_setup_pad(iomuxbase, MX6S_PAD_NANDF_D2__GPIO_2_2);
+	};
+
+	imx6_gpio_direction_input(gpio6, 6);
+	imx6_gpio_direction_input(gpio6, 9);
+	imx6_gpio_direction_input(gpio2, 2);
+
+	ver = imx6_gpio_val(gpio2, 2);
+	id0 = imx6_gpio_val(gpio6, 7);
+	id1 = imx6_gpio_val(gpio6, 9);
+
+	if (cpu_type == IMX6_CPUTYPE_IMX6D ||
+			cpu_type == IMX6_CPUTYPE_IMX6Q) {
+		if (ver)
+			size = SZ_1G;
+		else if (id0 && id1)
+			size = SZ_2G;
+		else if (id0)
+			size = SZ_2G;
+		else if (id1)
+			size = SZ_1G;
+		else
+			size = SZ_512M;
+	} else if (cpu_type == IMX6_CPUTYPE_IMX6S ||
+			cpu_type == IMX6_CPUTYPE_IMX6DL) {
+		if (ver)
+			size = SZ_512M;
+		if (id0 && id1)
+			size = SZ_2G;
+		else if (id0)
+			size = SZ_1G;
+		else if (id1)
+			size = SZ_512M;
+		else
+			size = SZ_128M;
+	}
+
+	return size;
+}
diff --git a/arch/arm/configs/imx_v7_defconfig b/arch/arm/configs/imx_v7_defconfig
index 62d623806c..08ec6eb862 100644
--- a/arch/arm/configs/imx_v7_defconfig
+++ b/arch/arm/configs/imx_v7_defconfig
@@ -11,6 +11,7 @@ CONFIG_MACH_GUF_VINCELL_XLOAD=y
 CONFIG_MACH_TQMA53=y
 CONFIG_MACH_FREESCALE_MX53_VMX53=y
 CONFIG_MACH_PHYTEC_SOM_IMX6=y
+CONFIG_MACH_KONTRON_SAMX6I=y
 CONFIG_MACH_DFI_FS700_M60=y
 CONFIG_MACH_GUF_SANTARO=y
 CONFIG_MACH_REALQ7=y
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 0526a6f407..db703c1e0f 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -28,6 +28,8 @@ pbl-dtb-$(CONFIG_MACH_GLOBALSCALE_MIRABOX) += armada-370-mirabox-bb.dtb.o
 pbl-dtb-$(CONFIG_MACH_GUF_SANTARO) += imx6q-guf-santaro.dtb.o
 pbl-dtb-$(CONFIG_MACH_GUF_VINCELL) += imx53-guf-vincell.dtb.o imx53-guf-vincell-lt.dtb.o
 pbl-dtb-$(CONFIG_MACH_GW_VENTANA) += imx6q-gw54xx.dtb.o
+pbl-dtb-$(CONFIG_MACH_KONTRON_SAMX6I) += imx6q-samx6i.dtb.o \
+					imx6dl-samx6i.dtb.o
 pbl-dtb-$(CONFIG_MACH_LENOVO_IX4_300D) += armada-xp-lenovo-ix4-300d-bb.dtb.o
 pbl-dtb-$(CONFIG_MACH_MARVELL_ARMADA_XP_GP) += armada-xp-gp-bb.dtb.o
 pbl-dtb-$(CONFIG_MACH_NETGEAR_RN104) += armada-370-rn104-bb.dtb.o
diff --git a/arch/arm/dts/imx6dl-samx6i.dts b/arch/arm/dts/imx6dl-samx6i.dts
new file mode 100644
index 0000000000..d688b9c6ca
--- /dev/null
+++ b/arch/arm/dts/imx6dl-samx6i.dts
@@ -0,0 +1,20 @@
+/*
+ * Copyright 2018 (C) Pengutronix, Michael Grzeschik <mgr at pengutronix.de>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+#include <arm/imx6dl.dtsi>
+#include "imx6dl.dtsi"
+#include "imx6qdl-smarc-samx6i.dtsi"
+
+/ {
+	model = "Kontron sAMX6i";
+	compatible = "kontron,imx6dl-samx6i", "fsl,imx6dl";
+};
diff --git a/arch/arm/dts/imx6q-samx6i.dts b/arch/arm/dts/imx6q-samx6i.dts
new file mode 100644
index 0000000000..83f19bcaf8
--- /dev/null
+++ b/arch/arm/dts/imx6q-samx6i.dts
@@ -0,0 +1,20 @@
+/*
+ * Copyright 2018 (C) Pengutronix, Michael Grzeschik <mgr at pengutronix.de>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+#include <arm/imx6q.dtsi>
+#include "imx6q.dtsi"
+#include "imx6qdl-smarc-samx6i.dtsi"
+
+/ {
+	model = "Kontron sAMX6i";
+	compatible = "kontron,imx6q-samx6i", "fsl,imx6q";
+};
diff --git a/arch/arm/dts/imx6qdl-smarc-samx6i.dtsi b/arch/arm/dts/imx6qdl-smarc-samx6i.dtsi
new file mode 100644
index 0000000000..3cbf11672d
--- /dev/null
+++ b/arch/arm/dts/imx6qdl-smarc-samx6i.dtsi
@@ -0,0 +1,509 @@
+/*
+ * Copyright 2017 (C) Priit Laes <plaes at plaes.org>
+ * Copyright 2018 (C) Pengutronix, Michael Grzeschik <mgr at pengutronix.de>
+ *
+ * Based on initial work by Nikita Yushchenko <nyushchenko at dev.rtsoft.ru>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of
+ *     the License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+	chosen {
+		linux,stdout-path = &uart2;
+
+		environment-spinor {
+			compatible = "barebox,environment";
+			device-path = &flash_bareboxenv;
+			status = "disabled";
+		};
+
+		environment-sd4 {
+			compatible = "barebox,environment";
+			device-path = &usdhc4_bareboxenv;
+			status = "disabled";
+		};
+	};
+
+	reg_3v3_s5: regulator at 0 {
+		compatible = "regulator-fixed";
+		regulator-name = "V_3V3_S5";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
+	reg_1v8_s5: regulator at 1 {
+		compatible = "regulator-fixed";
+		regulator-name = "V_1V8_S5";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
+	reg_3v3_s0: regulator at 2 {
+		compatible = "regulator-fixed";
+		regulator-name = "V_3V3_S0";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
+	reg_1v0_s0: regulator at 3 {
+		compatible = "regulator-fixed";
+		regulator-name = "V_1V0_S0";
+		regulator-min-microvolt = <1000000>;
+		regulator-max-microvolt = <1000000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
+	i2c_pfuze: i2c-gpio-0 {
+		compatible = "i2c-gpio";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_i2c_gpio_0>;
+		sda-gpios = <&gpio1 28 0>;
+		scl-gpios = <&gpio1 30 0>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		i2c-gpio,delay-us = <2>;
+	};
+};
+
+&can1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_flexcan1>;
+};
+
+&can2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_flexcan2>;
+};
+
+&fec {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_enet_smarc>;
+	phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
+	phy-mode = "rgmii";
+	status = "okay";
+};
+
+&i2c_pfuze {
+	pfuze100 at 08 {
+		compatible = "fsl,pfuze100";
+		reg = <0x08>;
+
+		/* Looks unused by pfuze100 driver */
+		interrupt-parent = <&gpio7>;
+		interrupts = <13 IRQ_TYPE_LEVEL_LOW>;
+
+		regulators {
+			reg_v_core_s0: sw1ab {
+				regulator-name = "V_CORE_S0";
+				regulator-min-microvolt = <300000>;
+				regulator-max-microvolt = <1875000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			reg_vddsoc_s0: sw1c {
+				regulator-name = "V_VDDSOC_S0";
+				regulator-min-microvolt = <300000>;
+				regulator-max-microvolt = <1875000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			reg_3v15_s0: sw2 {
+				regulator-name = "V_3V15_S0";
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			/* sw3a/b is used in dual mode, but driver does not
+			 * support it? Although, there's no need to control
+			 * DDR power - so just leaving dummy entries for sw3a
+			 * and sw3b for now.
+			 */
+			sw3a {
+				regulator-min-microvolt = <400000>;
+				regulator-max-microvolt = <1975000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			sw3b {
+				regulator-min-microvolt = <400000>;
+				regulator-max-microvolt = <1975000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			reg_1v8_s0: sw4 {
+				regulator-name = "V_1V8_S0";
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			/* Regulator for USB */
+			reg_5v0_s0: swbst {
+				regulator-name = "V_5V0_S0";
+				regulator-min-microvolt = <5000000>;
+				regulator-max-microvolt = <5150000>;
+				regulator-boot-on;
+			};
+
+			reg_vsnvs: vsnvs {
+				regulator-min-microvolt = <1000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			reg_vrefddr: vrefddr {
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			/* Per schematics, of all VGEN's, only VGEN5 has some
+			 * usage ... but even that - over DNI resistor
+			 */
+			vgen1 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1550000>;
+			};
+
+			vgen2 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1550000>;
+			};
+
+			vgen3 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+			};
+
+			vgen4 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+			};
+
+			reg_2v5_s0: vgen5 {
+				regulator-name = "V_2V5_S0";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+			};
+
+			vgen6 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+			};
+		};
+	};
+};
+
+&ecspi4 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_ecspi4>;
+	fsl,spi-num-chipselects = <3>;
+	cs-gpios = <&gpio3 24 0>, <&gpio3 29 0>, <&gpio3 25 0>;
+	status = "okay";
+
+	flash: m25p80 at 0 {
+		compatible = "winbond,w25q16dw", "jedec,spi-nor";
+		spi-max-frequency = <20000000>;
+		reg = <0>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		partition at 0 {
+			label = "bootloader";
+			reg = <0x000000 0x0c0000>;
+		};
+
+		flash_bareboxenv: partition at c0000 {
+			label = "environment";
+			reg = <0x0c0000 0x010000>;
+		};
+
+		partition at d0000 {
+			label = "user";
+			reg = <0x0d0000 0x130000>;
+		};
+	};
+};
+
+&i2c3 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c3>;
+};
+
+&pcie {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pcie>;
+	wake-up-gpio = <&gpio6 18 GPIO_ACTIVE_HIGH>;
+	reset-gpio = <&gpio3 13 GPIO_ACTIVE_HIGH>;
+};
+
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart1_smarc>;
+	fsl,uart-has-rtscts;
+};
+
+&uart2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart2_smarc>;
+	status = "okay";
+};
+
+&uart4 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart4_smarc>;
+	fsl,uart-has-rtscts;
+};
+
+&uart5 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart5_smarc>;
+};
+
+&usbotg {
+	/*
+	 * no 'imx6-usb-charger-detection'
+	 * since USB_OTG_CHD_B pin is not wired
+	 */
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usbotg>;
+	status = "okay";
+};
+
+&usbh1 {
+	vbus-supply = <&reg_5v0_s0>;
+	status = "okay";
+};
+
+&usdhc4 {
+	/* Internal eMMC, optional on some boards */
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc4>;
+	bus-width = <8>;
+	no-1-8-v;
+	non-removable;
+	status = "okay";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	partition at 0 {
+		label = "bootloader";
+		reg = <0x0 0xe0000>;
+	};
+
+	usdhc4_bareboxenv: partition at e0000 {
+		label = "environment";
+		reg = <0xe0000 0x20000>;
+	};
+};
+
+&iomuxc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_boot>;
+
+	pinctrl_boot: boot {
+		fsl,pins = <
+			/* GPIOS for version and id detection */
+			MX6QDL_PAD_NANDF_CLE__GPIO6_IO07	0x80000000
+			MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09	0x80000000
+			MX6QDL_PAD_NANDF_D2__GPIO2_IO02		0x80000000
+		>;
+	};
+
+	pinctrl_flexcan1: flexcan1-smarc {
+		fsl,pins = <
+			MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x80000000
+			MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x80000000
+		>;
+	};
+
+	pinctrl_flexcan2: flexcan2-smarc {
+		fsl,pins = <
+			MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x80000000
+			MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x80000000
+		>;
+	};
+
+	pinctrl_enet_smarc: fecgrp-smarc {
+		fsl,pins = <
+			MX6QDL_PAD_ENET_MDIO__ENET_MDIO       0x1b0b0
+			MX6QDL_PAD_ENET_MDC__ENET_MDC         0x1b0b0
+			MX6QDL_PAD_RGMII_TXC__RGMII_TXC       0x1b0b0
+			MX6QDL_PAD_RGMII_TD0__RGMII_TD0       0x1b0b0
+			MX6QDL_PAD_RGMII_TD1__RGMII_TD1       0x1b0b0
+			MX6QDL_PAD_RGMII_TD2__RGMII_TD2       0x1b0b0
+			MX6QDL_PAD_RGMII_TD3__RGMII_TD3       0x1b0b0
+			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
+			MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK  0x1b0b0
+			MX6QDL_PAD_RGMII_RXC__RGMII_RXC       0x1b0b0
+			MX6QDL_PAD_RGMII_RD0__RGMII_RD0       0x1b0b0
+			MX6QDL_PAD_RGMII_RD1__RGMII_RD1       0x1b0b0
+			MX6QDL_PAD_RGMII_RD2__RGMII_RD2       0x1b0b0
+			MX6QDL_PAD_RGMII_RD3__RGMII_RD3       0x1b0b0
+			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
+			MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25    0x80000000
+		>;
+	};
+
+	pinctrl_i2c_gpio_0: i2c-gpio-0-smarc {
+		fsl,pins = <
+			/* SCL GPIO */
+			MX6QDL_PAD_ENET_TXD0__GPIO1_IO30  0x80000000
+			/* SDA GPIO */
+			MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x80000000
+		>;
+	};
+
+	pinctrl_i2c3: i2c3-smarc {
+		fsl,pins = <
+			MX6QDL_PAD_EIM_D17__I2C3_SCL		0x4001b8b1
+			MX6QDL_PAD_EIM_D18__I2C3_SDA		0x4001b8b1
+		>;
+	};
+
+	pinctrl_ecspi4: ecspi4-smarc {
+		fsl,pins = <
+			MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x80000000
+			MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x80000000
+			MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x80000000
+                        MX6QDL_PAD_EIM_D29__ECSPI4_SS0  0x80000000
+
+			/* In hardware, ECSPI4's SS0,SS1,SS3 are wired.
+			   But spi-imx driver support only continuous
+			   numbering, and only can use GPIOs (and not
+			   ECSPI's hardware SS) for CS. So linux view
+			   of CS numbers differs from hw view, and
+			   pins are configured as GPIOs */
+
+			/* physical - CS2, in linux - CS0, either internal flash or SMARC CS0 */
+			MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x80000000
+			/* physical - CS0, in linux - CS1, either SMARC CS0 or not-connected */
+			MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x80000000
+			/* physical - CS3, in linux - CS2, SMARC CS1 */
+			MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x80000000
+		>;
+	};
+
+	pinctrl_pcie: pcie-smarc {
+		fsl,pins = <
+			/* RST_PCIE_A# */
+			MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x80000000
+			/* PCIE_WAKE# */
+			MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0x80000000
+		>;
+	};
+
+	pinctrl_uart1_smarc: uart1grp-smarc {
+		fsl,pins = <
+			MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
+			MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
+			MX6QDL_PAD_EIM_D20__UART1_RTS_B 0x1b0b1
+			MX6QDL_PAD_EIM_D19__UART1_CTS_B 0x1b0b1
+		>;
+	};
+
+	pinctrl_uart2_smarc: uart2grp-smarc {
+		fsl,pins = <
+			MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
+			MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
+		>;
+	};
+
+	pinctrl_uart4_smarc: uart4grp-smarc {
+		fsl,pins = <
+			MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1
+			MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1
+			MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1
+			MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1
+		>;
+	};
+
+	pinctrl_uart5_smarc: uart5grp-smarc {
+		fsl,pins = <
+			MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x1b0b1
+			MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x1b0b1
+		>;
+	};
+
+	pinctrl_usbotg: usbotg-grp-smarc {
+		fsl,pins = <
+			MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x1f8b0
+			/* TODO: Comment out power and OC gpio's for now, since
+			 * these are not used by driver
+			 */
+			/* USB power */
+			// MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x80000000
+			/* USB OC */
+			// MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x80000000
+		>;
+	};
+
+	pinctrl_usdhc4: usdhc4grp-smarc {
+		fsl,pins = <
+			MX6QDL_PAD_SD4_CLK__SD4_CLK 0x17059
+			MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
+			MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
+			MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
+			MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
+			MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
+			MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
+			MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
+			MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
+			MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
+		>;
+	};
+};
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index eb135c3f53..cf5338e5fa 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -294,6 +294,10 @@ config MACH_PHYTEC_SOM_IMX6
         select ARCH_IMX6
 	select ARCH_IMX6UL
 
+config MACH_KONTRON_SAMX6I
+        bool "Kontron sAMX6i"
+        select ARCH_IMX6
+
 config MACH_DFI_FS700_M60
 	bool "DFI i.MX6 FS700 M60 Q7 Board"
 	select ARCH_IMX6
diff --git a/images/Makefile.imx b/images/Makefile.imx
index 5e0043f1f0..0428c48ade 100644
--- a/images/Makefile.imx
+++ b/images/Makefile.imx
@@ -455,6 +455,16 @@ CFG_start_phytec_phycore_imx6ull_som_256mb.pblx.imximg = $(board)/phytec-som-imx
 FILE_barebox-phytec-phycore-imx6ull-256mb.img = start_phytec_phycore_imx6ull_som_256mb.pblx.imximg
 image-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += barebox-phytec-phycore-imx6ull-256mb.img
 
+pblx-$(CONFIG_MACH_KONTRON_SAMX6I) += start_imx6q_samx6i
+CFG_start_imx6q_samx6i.pblx.imximg = $(board)/kontron-samx6i/flash-header-samx6i-quad.imxcfg
+FILE_barebox-imx6q-samx6i.img = start_imx6q_samx6i.pblx.imximg
+image-$(CONFIG_MACH_KONTRON_SAMX6I) += barebox-imx6q-samx6i.img
+
+pblx-$(CONFIG_MACH_KONTRON_SAMX6I) += start_imx6dl_samx6i
+CFG_start_imx6dl_samx6i.pblx.imximg = $(board)/kontron-samx6i/flash-header-samx6i-duallite.imxcfg
+FILE_barebox-imx6dl-samx6i.img = start_imx6dl_samx6i.pblx.imximg
+image-$(CONFIG_MACH_KONTRON_SAMX6I) += barebox-imx6dl-samx6i.img
+
 pblx-$(CONFIG_MACH_GW_VENTANA) += start_imx6q_gw54xx_1gx64
 CFG_start_imx6q_gw54xx_1gx64.pblx.imximg = $(board)/gateworks-ventana/flash-header-ventana-quad-1gx64.imxcfg
 FILE_barebox-gateworks-imx6q-ventana-1gx64.img = start_imx6q_gw54xx_1gx64.pblx.imximg
-- 
2.16.1



From s.hauer at pengutronix.de  Mon Mar 19 03:30:41 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Mon, 19 Mar 2018 11:30:41 +0100
Subject: [PATCH] of: Pass barebox version to kernel
Message-ID: <20180319103041.19815-1-s.hauer@pengutronix.de>

Pass the barebox version to Linux in case somebody is interested in it
under Linux. We use put the version under /chosen/barebox-version and
it can be read under Linux in /sys/firmware/devicetree/base/chosen/barebox-version.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 common/oftree.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/common/oftree.c b/common/oftree.c
index 40eb35f188..8a2ede4c60 100644
--- a/common/oftree.c
+++ b/common/oftree.c
@@ -128,6 +128,7 @@ static int of_fixup_bootargs(struct device_node *root, void *unused)
 	if (!node)
 		return -ENOMEM;
 
+	of_property_write_string(node, "barebox-version", release_string);
 
 	err = of_property_write_string(node, "bootargs", str);
 
-- 
2.16.1



From o.rempel at pengutronix.de  Mon Mar 19 03:37:31 2018
From: o.rempel at pengutronix.de (Oleksij Rempel)
Date: Mon, 19 Mar 2018 11:37:31 +0100
Subject: [PATCH v3] watchdog: add watchdog poller
Message-ID: <20180319103731.5629-1-o.rempel@pengutronix.de>

In some cases it is practical to supervise as much as possible of
the barebox execution with a watchdog (or multiple watchdogs). This
patch provides an async poller for watchdog core framework which can
be enabled by the user and stores this configuration to nv.

Signed-off-by: Oleksij Rempel <o.rempel at pengutronix.de>
---
changes v3:
- rename variable to automatic_dog_feeder 

 drivers/watchdog/Kconfig   |  6 ++++
 drivers/watchdog/wd_core.c | 74 ++++++++++++++++++++++++++++++++++++++++++----
 include/watchdog.h         |  4 +++
 3 files changed, 78 insertions(+), 6 deletions(-)

diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index 3defb9da6..1d6b15617 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -10,6 +10,12 @@ menuconfig WATCHDOG
 
 if WATCHDOG
 
+menuconfig WATCHDOG_POLLER
+	bool "Watchdog periodic feeder support"
+	select POLLER
+	help
+	  Provides support for periodic watchdog feeder.
+
 config WATCHDOG_AR9344
 	bool "QCA AR9344"
 	depends on SOC_QCA_AR9344 || SOC_QCA_AR9331
diff --git a/drivers/watchdog/wd_core.c b/drivers/watchdog/wd_core.c
index 69663b39c..0ff09500c 100644
--- a/drivers/watchdog/wd_core.c
+++ b/drivers/watchdog/wd_core.c
@@ -31,6 +31,16 @@ static const char *watchdog_name(struct watchdog *wd)
 	return "unknown";
 }
 
+static int _watchdog_set_timeout(struct watchdog *wd, unsigned timeout)
+{
+	if (timeout > wd->timeout_max)
+		return -EINVAL;
+
+	pr_debug("setting timeout on %s to %ds\n", watchdog_name(wd), timeout);
+
+	return wd->set_timeout(wd, timeout);
+}
+
 static int watchdog_set_cur(struct param_d *param, void *priv)
 {
 	struct watchdog *wd = priv;
@@ -41,6 +51,55 @@ static int watchdog_set_cur(struct param_d *param, void *priv)
 	return 0;
 }
 
+static void watchdog_poller_cb(void *priv);
+
+static void watchdog_poller_start(struct watchdog *wd)
+{
+	_watchdog_set_timeout(wd, wd->timeout_cur);
+	poller_call_async(&wd->poller, 500 * MSECOND,
+			watchdog_poller_cb, wd);
+
+}
+
+static void watchdog_poller_cb(void *priv)
+{
+	struct watchdog *wd = priv;
+
+	if (wd->poller_enable)
+		watchdog_poller_start(wd);
+}
+
+static int watchdog_set_poller(struct param_d *param, void *priv)
+{
+	struct watchdog *wd = priv;
+
+
+	if (wd->poller_enable) {
+		dev_info(&wd->dev, "enable watchdog poller\n");
+		watchdog_poller_start(wd);
+	} else {
+		dev_info(&wd->dev, "disable watchdog poller\n");
+		poller_async_cancel(&wd->poller);
+	}
+
+	return 0;
+}
+
+static int watchdog_register_poller(struct watchdog *wd)
+{
+	struct param_d *p;
+	int ret;
+
+	ret = poller_async_register(&wd->poller);
+	if (ret)
+		return ret;
+
+	p = dev_add_param_bool(&wd->dev, "automatic_dog_feeder", watchdog_set_poller,
+			NULL, &wd->poller_enable, wd);
+
+	return PTR_ERR_OR_ZERO(p);
+}
+
 static int watchdog_register_dev(struct watchdog *wd, const char *name, int id)
 {
 	wd->dev.parent = wd->hwdev;
@@ -86,6 +145,12 @@ int watchdog_register(struct watchdog *wd)
 	if (IS_ERR(p))
 		return PTR_ERR(p);
 
+	if (IS_ENABLED(CONFIG_WATCHDOG_POLLER)) {
+		ret = watchdog_register_poller(wd);
+		if (ret)
+			return ret;
+	}
+
 	list_add_tail(&wd->list, &watchdog_list);
 
 	pr_debug("registering watchdog %s with priority %d\n", watchdog_name(wd),
@@ -97,6 +162,8 @@ EXPORT_SYMBOL(watchdog_register);
 
 int watchdog_deregister(struct watchdog *wd)
 {
+	poller_async_cancel(&wd->poller);
+	poller_async_unregister(&wd->poller);
 	unregister_device(&wd->dev);
 	list_del(&wd->list);
 
@@ -132,12 +199,7 @@ int watchdog_set_timeout(unsigned timeout)
 	if (!wd)
 		return -ENODEV;
 
-	if (timeout > wd->timeout_max)
-		return -EINVAL;
-
-	pr_debug("setting timeout on %s to %ds\n", watchdog_name(wd), timeout);
-
-	return wd->set_timeout(wd, timeout);
+	return _watchdog_set_timeout(wd, timeout);
 }
 EXPORT_SYMBOL(watchdog_set_timeout);
 
diff --git a/include/watchdog.h b/include/watchdog.h
index 2f1874c19..0db4263a3 100644
--- a/include/watchdog.h
+++ b/include/watchdog.h
@@ -13,6 +13,8 @@
 #ifndef INCLUDE_WATCHDOG_H
 # define INCLUDE_WATCHDOG_H
 
+#include <poller.h>
+
 struct watchdog {
 	int (*set_timeout)(struct watchdog *, unsigned);
 	const char *name;
@@ -21,6 +23,8 @@ struct watchdog {
 	unsigned int priority;
 	unsigned int timeout_max;
 	unsigned int timeout_cur;
+	unsigned int poller_enable;
+	struct poller_async poller;
 	struct list_head list;
 };
 
-- 
2.16.1



From mgr at pengutronix.de  Mon Mar 19 04:48:37 2018
From: mgr at pengutronix.de (Michael Grzeschik)
Date: Mon, 19 Mar 2018 12:48:37 +0100
Subject: [PATCH v2 2/2] boards: samx6: add initial support for kontron
 samx6i
In-Reply-To: <20180319092120.11773-3-m.grzeschik@pengutronix.de>
References: <20180319092120.11773-1-m.grzeschik@pengutronix.de>
 <20180319092120.11773-3-m.grzeschik@pengutronix.de>
Message-ID: <20180319114837.xobu4rn3r7skzsta@pengutronix.de>

On Mon, Mar 19, 2018 at 10:21:20AM +0100, Michael Grzeschik wrote:
> Signed-off-by: Michael Grzeschik <m.grzeschik at pengutronix.de>
> ---
> v1 -> v2:
> 	- dropped SZ_4G
> 	- fixed and clean env prepraration in board.c
> 	- added compatible checks for initcalls
> 	- dropped clock gate in flash headers
> 	- added memory detection in lowlevel
> 	- merged imx6qdl-samx6i with imx6qdl-smarc-samx6i
> 	- fixed dts
> 	- use imx_esdctl_disable instead of dts disable
> 
>  arch/arm/boards/Makefile                           |   1 +
>  arch/arm/boards/kontron-samx6i/Makefile            |   2 +
>  arch/arm/boards/kontron-samx6i/board.c             | 103 +++++
>  .../flash-header-samx6i-duallite.imxcfg            | 102 +++++
>  .../kontron-samx6i/flash-header-samx6i-quad.imxcfg | 118 +++++
>  arch/arm/boards/kontron-samx6i/lowlevel.c          |  66 +++
>  arch/arm/boards/kontron-samx6i/mem.c               |  85 ++++
>  arch/arm/configs/imx_v7_defconfig                  |   1 +
>  arch/arm/dts/Makefile                              |   2 +
>  arch/arm/dts/imx6dl-samx6i.dts                     |  20 +
>  arch/arm/dts/imx6q-samx6i.dts                      |  20 +
>  arch/arm/dts/imx6qdl-smarc-samx6i.dtsi             | 509 +++++++++++++++++++++
>  arch/arm/mach-imx/Kconfig                          |   4 +
>  images/Makefile.imx                                |  10 +
>  14 files changed, 1043 insertions(+)
>  create mode 100644 arch/arm/boards/kontron-samx6i/Makefile
>  create mode 100644 arch/arm/boards/kontron-samx6i/board.c
>  create mode 100644 arch/arm/boards/kontron-samx6i/flash-header-samx6i-duallite.imxcfg
>  create mode 100644 arch/arm/boards/kontron-samx6i/flash-header-samx6i-quad.imxcfg
>  create mode 100644 arch/arm/boards/kontron-samx6i/lowlevel.c
>  create mode 100644 arch/arm/boards/kontron-samx6i/mem.c
>  create mode 100644 arch/arm/dts/imx6dl-samx6i.dts
>  create mode 100644 arch/arm/dts/imx6q-samx6i.dts
>  create mode 100644 arch/arm/dts/imx6qdl-smarc-samx6i.dtsi
> 
> diff --git a/arch/arm/boards/Makefile b/arch/arm/boards/Makefile
> index ca187ccb89..30f4c299f1 100644
> --- a/arch/arm/boards/Makefile
> +++ b/arch/arm/boards/Makefile
> @@ -61,6 +61,7 @@ obj-$(CONFIG_MACH_IMX21ADS)			+= freescale-mx21-ads/
>  obj-$(CONFIG_MACH_IMX233_OLINUXINO)		+= imx233-olinuxino/
>  obj-$(CONFIG_MACH_IMX27ADS)			+= freescale-mx27-ads/
>  obj-$(CONFIG_MACH_KINDLE3)			+= kindle3/
> +obj-$(CONFIG_MACH_KONTRON_SAMX6I)		+= kontron-samx6i/
>  obj-$(CONFIG_MACH_LENOVO_IX4_300D)		+= lenovo-ix4-300d/
>  obj-$(CONFIG_MACH_LUBBOCK)			+= lubbock/
>  obj-$(CONFIG_MACH_MAINSTONE)			+= mainstone/
> diff --git a/arch/arm/boards/kontron-samx6i/Makefile b/arch/arm/boards/kontron-samx6i/Makefile
> new file mode 100644
> index 0000000000..816962241a
> --- /dev/null
> +++ b/arch/arm/boards/kontron-samx6i/Makefile
> @@ -0,0 +1,2 @@
> +obj-y += board.o mem.o
> +lwl-y += lowlevel.o mem.o
> diff --git a/arch/arm/boards/kontron-samx6i/board.c b/arch/arm/boards/kontron-samx6i/board.c
> new file mode 100644
> index 0000000000..01826b67d2
> --- /dev/null
> +++ b/arch/arm/boards/kontron-samx6i/board.c
> @@ -0,0 +1,103 @@
> +/*
> + * Copyright 2018 (C) Pengutronix, Michael Grzeschik <mgr at pengutronix.de>
> + *
> + * The code contained herein is licensed under the GNU General Public
> + * License. You may obtain a copy of the GNU General Public License
> + * Version 2 or later at the following locations:
> + *
> + * http://www.opensource.org/licenses/gpl-license.html
> + * http://www.gnu.org/copyleft/gpl.html
> + */
> +
> +#define pr_fmt(fmt) "samx6i: " fmt
> +
> +#include <malloc.h>
> +#include <envfs.h>
> +#include <environment.h>
> +#include <bootsource.h>
> +#include <common.h>
> +#include <init.h>
> +#include <of.h>
> +#include <mach/bbu.h>
> +#include <mach/esdctl.h>
> +
> +#include <asm/armlinux.h>
> +
> +resource_size_t samx6i_get_size(void);
> +
> +/*
> + * On this board the SDRAM size is always configured by pin selection.
> + */
> +static int samx6i_sdram_fixup(void)
> +{
> +	if (!(of_machine_is_compatible("kontron,imx6q-samx6i") ||
> +		of_machine_is_compatible("kontron,imx6dl-samx6i")))
> +		return 0;
> +
> +	imx_esdctl_disable();
> +
> +	return 0;
> +}
> +postcore_initcall(samx6i_sdram_fixup);
> +
> +static int samx6i_mem_init(void)
> +{
> +	resource_size_t size = 0;
> +
> +	if (!(of_machine_is_compatible("kontron,imx6q-samx6i") ||
> +		of_machine_is_compatible("kontron,imx6dl-samx6i")))
> +		return 0;
> +
> +	size = samx6i_get_size();
> +	if (size)
> +		arm_add_mem_device("ram0", 0x10000000, size);
> +
> +	return 0;
> +}
> +mem_initcall(samx6i_mem_init);
> +
> +static int samx6i_devices_init(void)
> +{
> +	int ret;
> +	char *environment_path, *envdev;
> +	int flag_spi = 0, flag_mmc = 0;
> +
> +	if (!(of_machine_is_compatible("kontron,imx6q-samx6i") ||
> +		of_machine_is_compatible("kontron,imx6dl-samx6i")))
> +		return 0;
> +
> +	barebox_set_hostname("samx6i");
> +
> +	switch (bootsource_get()) {
> +	case BOOTSOURCE_MMC:
> +		environment_path = basprintf("/chosen/environment-sd%d",
> +					       bootsource_get_instance() + 1);
> +		envdev = "MMC";
> +		flag_mmc = BBU_HANDLER_FLAG_DEFAULT;
> +		break;
> +	default:
> +		environment_path = basprintf("/chosen/environment-spinor");
> +		envdev = "SPI NOR flash";
> +		flag_spi = BBU_HANDLER_FLAG_DEFAULT;
> +		break;
> +	}
> +
> +	ret = of_device_enable_path(environment_path);
> +	if (ret < 0)
> +		pr_warn("Failed to enable environment partition '%s' (%d)\n",
> +			environment_path, ret);
> +	free(environment_path);
> +
> +	pr_notice("Using environment in %s\n", envdev);
> +
> +	imx6_bbu_internal_spi_i2c_register_handler("m25p80",
> +					"/dev/m25p0.bootloader",
> +					flag_spi);
> +
> +	imx6_bbu_internal_mmc_register_handler("mmc3",
> +					"/dev/mmc3.bootloader",
> +					flag_mmc);
> +
> +	return 0;
> +}
> +device_initcall(samx6i_devices_init);
> diff --git a/arch/arm/boards/kontron-samx6i/flash-header-samx6i-duallite.imxcfg b/arch/arm/boards/kontron-samx6i/flash-header-samx6i-duallite.imxcfg
> new file mode 100644
> index 0000000000..9906617083
> --- /dev/null
> +++ b/arch/arm/boards/kontron-samx6i/flash-header-samx6i-duallite.imxcfg
> @@ -0,0 +1,102 @@
> +soc imx6
> +loadaddr 0x10000000
> +dcdofs 0x400
> +
> +wm 32 0x020e0774 0x000c0000
> +wm 32 0x020e0754 0x00000000
> +
> +wm 32 0x020e04ac 0x00000030
> +wm 32 0x020e04b0 0x00000030
> +
> +wm 32 0x020e0464 0x00000030
> +wm 32 0x020e0490 0x00000030
> +wm 32 0x020e074c 0x00000030
> +
> +wm 32 0x020e0494 0x000c0030
> +wm 32 0x020e04a4 0x00003000
> +wm 32 0x020e04a8 0x00003000
> +wm 32 0x020e04a0 0x00000000
> +wm 32 0x020e04b4 0x00003030
> +wm 32 0x020e04b8 0x00003030
> +wm 32 0x020e076c 0x00000030
> +
> +wm 32 0x020e0750 0x00020000
> +wm 32 0x020e04bc 0x00000038
> +wm 32 0x020e04c0 0x00000038
> +wm 32 0x020e04c4 0x00000038
> +wm 32 0x020e04c8 0x00000038
> +wm 32 0x020e04cc 0x00000038
> +wm 32 0x020e04d0 0x00000038
> +wm 32 0x020e04d4 0x00000038
> +wm 32 0x020e04d8 0x00000038
> +
> +wm 32 0x020e0760 0x00020000
> +wm 32 0x020e0764 0x00000030
> +wm 32 0x020e0770 0x00000030
> +wm 32 0x020e0778 0x00000030
> +wm 32 0x020e077c 0x00000030
> +wm 32 0x020e0780 0x00000030
> +wm 32 0x020e0784 0x00000030
> +wm 32 0x020e078c 0x00000030
> +wm 32 0x020e0748 0x00000030
> +
> +wm 32 0x020e0470 0x00000030
> +wm 32 0x020e0474 0x00000030
> +wm 32 0x020e0478 0x00000030
> +wm 32 0x020e047c 0x00000030
> +wm 32 0x020e0480 0x00000030
> +wm 32 0x020e0484 0x00000030
> +wm 32 0x020e0488 0x00000030
> +wm 32 0x020e048c 0x000C0030
> +
> +wm 32 0x021b0800 0xa1390003
> +wm 32 0x021b4800 0xa1390003
> +
> +wm 32 0x021b080c 0x0040003c
> +wm 32 0x021b0810 0x0032003e
> +
> +wm 32 0x021b083c 0x42350231
> +wm 32 0x021b0840 0x021a0218
> +wm 32 0x021b0848 0x4b4b4e49
> +wm 32 0x021b0850 0x3f3f3035
> +
> +wm 32 0x021b081c 0x33333333
> +wm 32 0x021b0820 0x33333333
> +wm 32 0x021b0824 0x33333333
> +wm 32 0x021b0828 0x33333333
> +wm 32 0x021b481c 0x33333333
> +wm 32 0x021b4820 0x33333333
> +wm 32 0x021b4824 0x33333333
> +wm 32 0x021b4828 0x33333333
> +
> +
> +wm 32 0x021b08b8 0x00000800
> +wm 32 0x021b48b8 0x00000800
> +
> +wm 32 0x021b0004 0x0002002d
> +wm 32 0x021b0008 0x00333030
> +wm 32 0x021b000c 0x696d5323
> +wm 32 0x021b0010 0xb66e8c63
> +wm 32 0x021b0014 0x01ff00db
> +wm 32 0x021b0018 0x00001740
> +wm 32 0x021b001c 0x00008000
> +wm 32 0x021b002c 0x000026d2
> +wm 32 0x021b0030 0x006d0e21
> +wm 32 0x021b0040 0x00000027
> +wm 32 0x021b0000 0x84190000
> +wm 32 0x021b001c 0x04008032
> +wm 32 0x021b001c 0x00008033
> +wm 32 0x021b001c 0x00048031
> +wm 32 0x021b001c 0x07208030
> +wm 32 0x021b001c 0x04008040
> +wm 32 0x021b0020 0x00005800
> +wm 32 0x021b0818 0x00022227
> +wm 32 0x021b4818 0x00022227
> +wm 32 0x021b0004 0x0002556d
> +wm 32 0x021b4004 0x00011006
> +wm 32 0x021b001c 0x00000000
> +
> +wm 32 0x020e0010 0xf00000ff
> +
> +wm 32 0x020e0018 0x00070007
> +wm 32 0x020e001c 0x00070007
> diff --git a/arch/arm/boards/kontron-samx6i/flash-header-samx6i-quad.imxcfg b/arch/arm/boards/kontron-samx6i/flash-header-samx6i-quad.imxcfg
> new file mode 100644
> index 0000000000..7e6ffd7983
> --- /dev/null
> +++ b/arch/arm/boards/kontron-samx6i/flash-header-samx6i-quad.imxcfg
> @@ -0,0 +1,118 @@
> +soc imx6
> +loadaddr 0x10000000
> +dcdofs 0x400
> +
> +wm 32 0x020e05a8 0x00000030
> +wm 32 0x020e05b0 0x00000030
> +wm 32 0x020e0524 0x00000030
> +wm 32 0x020e051c 0x00000030
> +
> +wm 32 0x020e0518 0x00000030
> +wm 32 0x020e050c 0x00000030
> +wm 32 0x020e05b8 0x00000030
> +wm 32 0x020e05c0 0x00000030
> +
> +wm 32 0x020e05ac 0x00020030
> +wm 32 0x020e05b4 0x00020030
> +wm 32 0x020e0528 0x00020030
> +wm 32 0x020e0520 0x00020030
> +
> +wm 32 0x020e0514 0x00020030
> +wm 32 0x020e0510 0x00020030
> +wm 32 0x020e05bc 0x00020030
> +wm 32 0x020e05c4 0x00020030
> +
> +wm 32 0x020e056c 0x00020030
> +wm 32 0x020e0578 0x00020030
> +wm 32 0x020e0588 0x00020030
> +wm 32 0x020e0594 0x00020030
> +
> +wm 32 0x020e057c 0x00020030
> +wm 32 0x020e0590 0x00003000
> +wm 32 0x020e0598 0x00003000
> +wm 32 0x020e058c 0x00000000
> +
> +wm 32 0x020e059c 0x00003030
> +wm 32 0x020e05a0 0x00003030
> +wm 32 0x020e0784 0x00000030
> +wm 32 0x020e0788 0x00000030
> +
> +wm 32 0x020e0794 0x00000030
> +wm 32 0x020e079c 0x00000030
> +wm 32 0x020e07a0 0x00000030
> +wm 32 0x020e07a4 0x00000030
> +
> +wm 32 0x020e07a8 0x00000030
> +wm 32 0x020e0748 0x00000030
> +wm 32 0x020e074c 0x00000030
> +wm 32 0x020e0750 0x00020000
> +
> +wm 32 0x020e0758 0x00000000
> +wm 32 0x020e0774 0x00020000
> +wm 32 0x020e078c 0x00000030
> +wm 32 0x020e0798 0x000C0000
> +
> +wm 32 0x021b081c 0x33333333
> +wm 32 0x021b0820 0x33333333
> +wm 32 0x021b0824 0x33333333
> +wm 32 0x021b0828 0x33333333
> +
> +wm 32 0x021b481c 0x33333333
> +wm 32 0x021b4820 0x33333333
> +wm 32 0x021b4824 0x33333333
> +wm 32 0x021b4828 0x33333333
> +
> +wm 32 0x021b0018 0x00081740
> +
> +wm 32 0x021b001c 0x00008000
> +wm 32 0x021b000c 0x898E7975
> +wm 32 0x021b0010 0xFF538E64
> +wm 32 0x021b0014 0x01FF00DD
> +wm 32 0x021b002c 0x000026D2
> +
> +wm 32 0x021b0030 0x005B0E21
> +wm 32 0x021b0008 0x09444040
> +wm 32 0x021b0004 0x00025576
> +/*  CS0_END = 4GB */
> +wm 32 0x021b0040 0x0000007F
> +
> +wm 32 0x021b0000 0x841A0000
> +
> +wm 32 0x021b001c 0x04088032
> +wm 32 0x021b001c 0x00008033
> +wm 32 0x021b001c 0x00428031
> +wm 32 0x021b001c 0x09408030
> +
> +wm 32 0x021b001c 0x04008040
> +wm 32 0x021b0800 0xA1390003
> +wm 32 0x021b4800 0xA1390003
> +wm 32 0x021b0020 0x00007800
> +wm 32 0x021b0818 0x00022227
> +wm 32 0x021b4818 0x00022227
> +
> +wm 32 0x021b083c 0x42740304
> +wm 32 0x021b0840 0x026e0265
> +wm 32 0x021b483c 0x02750306
> +wm 32 0x021b4840 0x02720244
> +wm 32 0x021b0848 0x463d4041
> +wm 32 0x021b4848 0x42413c47
> +wm 32 0x021b0850 0x37414441
> +wm 32 0x021b4850 0x4633473b
> +
> +wm 32 0x021b080c 0x0025001f
> +wm 32 0x021b0810 0x00290027
> +
> +wm 32 0x021b480c 0x001f002b
> +wm 32 0x021b4810 0x000f0029
> +
> +wm 32 0x021b08b8 0x00000800
> +wm 32 0x021b48b8 0x00000800
> +
> +wm 32 0x021b001c 0x00000000
> +wm 32 0x021b0404 0x00011006
> +
> +/* enable AXI cache for VDOA/VPU/IPU */
> +wm 32 0x020e0010 0xF00000FF
> +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
> +wm 32 0x020e0018 0x007F007F
> +wm 32 0x020e001c 0x007F007F
> diff --git a/arch/arm/boards/kontron-samx6i/lowlevel.c b/arch/arm/boards/kontron-samx6i/lowlevel.c
> new file mode 100644
> index 0000000000..4113ddbb40
> --- /dev/null
> +++ b/arch/arm/boards/kontron-samx6i/lowlevel.c
> @@ -0,0 +1,66 @@
> +/*
> + * Copyright 2018 (C) Pengutronix, Michael Grzeschik <mgr at pengutronix.de>
> + *
> + * The code contained herein is licensed under the GNU General Public
> + * License. You may obtain a copy of the GNU General Public License
> + * Version 2 or later at the following locations:
> + *
> + * http://www.opensource.org/licenses/gpl-license.html
> + * http://www.gnu.org/copyleft/gpl.html
> + */
> +
> +#include <debug_ll.h>
> +#include <common.h>
> +#include <io.h>
> +#include <asm/barebox-arm-head.h>
> +#include <asm/barebox-arm.h>
> +#include <asm/sections.h>
> +#include <asm/cache.h>
> +#include <asm/mmu.h>
> +#include <mach/imx6.h>
> +#include <mach/esdctl.h>
> +
> +resource_size_t samx6i_get_size(void);
> +
> +static inline void setup_uart(void)
> +{
> +	void __iomem *iomuxbase = (void *)MX6_IOMUXC_BASE_ADDR;
> +
> +	writel(0x4, iomuxbase + 0x016c);
> +
> +	imx6_ungate_all_peripherals();
> +	imx6_uart_setup_ll();
> +
> +	putc_ll('>');
> +}
> +
> +static void __noreturn start_imx6_samx6i_common(void *fdt_blob_fixed_offset)
> +{
> +	void *fdt;
> +	resource_size_t size = 0;
> +
> +	size = samx6i_get_size();
> +
> +	imx6_cpu_lowlevel_init();
> +	arm_setup_stack(0x00920000 - 8);
> +
> +	if (IS_ENABLED(CONFIG_DEBUG_LL))
> +		setup_uart();
> +
> +	fdt = fdt_blob_fixed_offset - get_runtime_offset();
> +
> +	barebox_arm_entry(0x10000000, size, fdt);
> +}
> +
> +extern char __dtb_imx6dl_samx6i_start[];
> +extern char __dtb_imx6q_samx6i_start[];
> +
> +ENTRY_FUNCTION(start_imx6q_samx6i, r0, r1, r2)
> +{
> +	start_imx6_samx6i_common(__dtb_imx6q_samx6i_start);
> +}
> +
> +ENTRY_FUNCTION(start_imx6dl_samx6i, r0, r1, r2)
> +{
> +	start_imx6_samx6i_common(__dtb_imx6dl_samx6i_start);
> +}
> diff --git a/arch/arm/boards/kontron-samx6i/mem.c b/arch/arm/boards/kontron-samx6i/mem.c
> new file mode 100644
> index 0000000000..ab9969e32c
> --- /dev/null
> +++ b/arch/arm/boards/kontron-samx6i/mem.c
> @@ -0,0 +1,85 @@
> +/*
> + * Copyright 2018 (C) Pengutronix, Michael Grzeschik <mgr at pengutronix.de>
> + *
> + * The code contained herein is licensed under the GNU General Public
> + * License. You may obtain a copy of the GNU General Public License
> + * Version 2 or later at the following locations:
> + *
> + * http://www.opensource.org/licenses/gpl-license.html
> + * http://www.gnu.org/copyleft/gpl.html
> + */
> +
> +#include <linux/sizes.h>
> +#include <common.h>
> +#include <mach/iomux-mx6.h>
> +#include <mach/imx-gpio.h>
> +#include <mach/imx6.h>
> +
> +#define PCBVERSION_PIN IMX_GPIO_NR(2, 2)
> +#define PCBID0_PIN IMX_GPIO_NR(6, 7)
> +#define PCBID1_PIN IMX_GPIO_NR(6, 9)
> +
> +#define MX6S_PAD_NANDF_CLE__GPIO_6_7 \
> +	IOMUX_PAD(0x0658, 0x0270, 5, 0x0000, 0, 0)
> +#define MX6S_PAD_NANDF_WP_B__GPIO_6_9 \
> +	IOMUX_PAD(0x0690, 0x02A8, 5, 0x0000, 0, 0)
> +#define MX6S_PAD_NANDF_D2__GPIO_2_2 \
> +	IOMUX_PAD(0x028c, 0x0674, 5, 0x0000, 0, 0)
> +
> +resource_size_t samx6i_get_size(void)
> +{
> +	resource_size_t size = 0;
> +	int ver, id0, id1;
> +	int cpu_type = __imx6_cpu_type();
> +	void __iomem *iomuxbase = IOMEM(MX6_IOMUXC_BASE_ADDR);
> +	void __iomem *gpio6 = IOMEM(MX6_GPIO6_BASE_ADDR);
> +	void __iomem *gpio2 = IOMEM(MX6_GPIO2_BASE_ADDR);
> +
> +	if (cpu_type == IMX6_CPUTYPE_IMX6D ||
> +			cpu_type == IMX6_CPUTYPE_IMX6Q) {
> +		imx_setup_pad(iomuxbase, MX6Q_PAD_NANDF_CLE__GPIO_6_7);
> +		imx_setup_pad(iomuxbase, MX6Q_PAD_NANDF_WP_B__GPIO_6_9);
> +		imx_setup_pad(iomuxbase, MX6Q_PAD_NANDF_D2__GPIO_2_2);
> +	} else if (cpu_type == IMX6_CPUTYPE_IMX6S ||
> +			cpu_type == IMX6_CPUTYPE_IMX6DL) {
> +		imx_setup_pad(iomuxbase, MX6S_PAD_NANDF_CLE__GPIO_6_7);
> +		imx_setup_pad(iomuxbase, MX6S_PAD_NANDF_WP_B__GPIO_6_9);
> +		imx_setup_pad(iomuxbase, MX6S_PAD_NANDF_D2__GPIO_2_2);
> +	};
> +
> +	imx6_gpio_direction_input(gpio6, 6);
> +	imx6_gpio_direction_input(gpio6, 9);
> +	imx6_gpio_direction_input(gpio2, 2);
> +
> +	ver = imx6_gpio_val(gpio2, 2);
> +	id0 = imx6_gpio_val(gpio6, 7);
> +	id1 = imx6_gpio_val(gpio6, 9);
> +
> +	if (cpu_type == IMX6_CPUTYPE_IMX6D ||
> +			cpu_type == IMX6_CPUTYPE_IMX6Q) {
> +		if (ver)
> +			size = SZ_1G;
> +		else if (id0 && id1)
> +			size = SZ_2G;
> +		else if (id0)
> +			size = SZ_2G;
> +		else if (id1)
> +			size = SZ_1G;
> +		else
> +			size = SZ_512M;
> +	} else if (cpu_type == IMX6_CPUTYPE_IMX6S ||
> +			cpu_type == IMX6_CPUTYPE_IMX6DL) {
> +		if (ver)
> +			size = SZ_512M;
> +		if (id0 && id1)
> +			size = SZ_2G;
> +		else if (id0)
> +			size = SZ_1G;
> +		else if (id1)
> +			size = SZ_512M;
> +		else
> +			size = SZ_128M;
> +	}
> +
> +	return size;
> +}
> diff --git a/arch/arm/configs/imx_v7_defconfig b/arch/arm/configs/imx_v7_defconfig
> index 62d623806c..08ec6eb862 100644
> --- a/arch/arm/configs/imx_v7_defconfig
> +++ b/arch/arm/configs/imx_v7_defconfig
> @@ -11,6 +11,7 @@ CONFIG_MACH_GUF_VINCELL_XLOAD=y
>  CONFIG_MACH_TQMA53=y
>  CONFIG_MACH_FREESCALE_MX53_VMX53=y
>  CONFIG_MACH_PHYTEC_SOM_IMX6=y
> +CONFIG_MACH_KONTRON_SAMX6I=y
>  CONFIG_MACH_DFI_FS700_M60=y
>  CONFIG_MACH_GUF_SANTARO=y
>  CONFIG_MACH_REALQ7=y
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index 0526a6f407..db703c1e0f 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -28,6 +28,8 @@ pbl-dtb-$(CONFIG_MACH_GLOBALSCALE_MIRABOX) += armada-370-mirabox-bb.dtb.o
>  pbl-dtb-$(CONFIG_MACH_GUF_SANTARO) += imx6q-guf-santaro.dtb.o
>  pbl-dtb-$(CONFIG_MACH_GUF_VINCELL) += imx53-guf-vincell.dtb.o imx53-guf-vincell-lt.dtb.o
>  pbl-dtb-$(CONFIG_MACH_GW_VENTANA) += imx6q-gw54xx.dtb.o
> +pbl-dtb-$(CONFIG_MACH_KONTRON_SAMX6I) += imx6q-samx6i.dtb.o \
> +					imx6dl-samx6i.dtb.o
>  pbl-dtb-$(CONFIG_MACH_LENOVO_IX4_300D) += armada-xp-lenovo-ix4-300d-bb.dtb.o
>  pbl-dtb-$(CONFIG_MACH_MARVELL_ARMADA_XP_GP) += armada-xp-gp-bb.dtb.o
>  pbl-dtb-$(CONFIG_MACH_NETGEAR_RN104) += armada-370-rn104-bb.dtb.o
> diff --git a/arch/arm/dts/imx6dl-samx6i.dts b/arch/arm/dts/imx6dl-samx6i.dts
> new file mode 100644
> index 0000000000..d688b9c6ca
> --- /dev/null
> +++ b/arch/arm/dts/imx6dl-samx6i.dts
> @@ -0,0 +1,20 @@
> +/*
> + * Copyright 2018 (C) Pengutronix, Michael Grzeschik <mgr at pengutronix.de>
> + *
> + * The code contained herein is licensed under the GNU General Public
> + * License. You may obtain a copy of the GNU General Public License
> + * Version 2 or later at the following locations:
> + *
> + * http://www.opensource.org/licenses/gpl-license.html
> + * http://www.gnu.org/copyleft/gpl.html
> + */
> +
> +/dts-v1/;
> +#include <arm/imx6dl.dtsi>
> +#include "imx6dl.dtsi"
> +#include "imx6qdl-smarc-samx6i.dtsi"
> +
> +/ {
> +	model = "Kontron sAMX6i";
> +	compatible = "kontron,imx6dl-samx6i", "fsl,imx6dl";
> +};
> diff --git a/arch/arm/dts/imx6q-samx6i.dts b/arch/arm/dts/imx6q-samx6i.dts
> new file mode 100644
> index 0000000000..83f19bcaf8
> --- /dev/null
> +++ b/arch/arm/dts/imx6q-samx6i.dts
> @@ -0,0 +1,20 @@
> +/*
> + * Copyright 2018 (C) Pengutronix, Michael Grzeschik <mgr at pengutronix.de>
> + *
> + * The code contained herein is licensed under the GNU General Public
> + * License. You may obtain a copy of the GNU General Public License
> + * Version 2 or later at the following locations:
> + *
> + * http://www.opensource.org/licenses/gpl-license.html
> + * http://www.gnu.org/copyleft/gpl.html
> + */
> +
> +/dts-v1/;
> +#include <arm/imx6q.dtsi>
> +#include "imx6q.dtsi"
> +#include "imx6qdl-smarc-samx6i.dtsi"
> +
> +/ {
> +	model = "Kontron sAMX6i";
> +	compatible = "kontron,imx6q-samx6i", "fsl,imx6q";
> +};
> diff --git a/arch/arm/dts/imx6qdl-smarc-samx6i.dtsi b/arch/arm/dts/imx6qdl-smarc-samx6i.dtsi
> new file mode 100644
> index 0000000000..3cbf11672d
> --- /dev/null
> +++ b/arch/arm/dts/imx6qdl-smarc-samx6i.dtsi
> @@ -0,0 +1,509 @@
> +/*
> + * Copyright 2017 (C) Priit Laes <plaes at plaes.org>
> + * Copyright 2018 (C) Pengutronix, Michael Grzeschik <mgr at pengutronix.de>
> + *
> + * Based on initial work by Nikita Yushchenko <nyushchenko at dev.rtsoft.ru>
> + *
> + * This file is dual-licensed: you can use it either under the terms
> + * of the GPL or the X11 license, at your option. Note that this dual
> + * licensing only applies to this file, and not this project as a
> + * whole.
> + *
> + *  a) This file is free software; you can redistribute it and/or
> + *     modify it under the terms of the GNU General Public License as
> + *     published by the Free Software Foundation; either version 2 of
> + *     the License, or (at your option) any later version.
> + *
> + *     This file is distributed in the hope that it will be useful,
> + *     but WITHOUT ANY WARRANTY; without even the implied warranty of
> + *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + *     GNU General Public License for more details.
> + *
> + * Or, alternatively,
> + *
> + *  b) Permission is hereby granted, free of charge, to any person
> + *     obtaining a copy of this software and associated documentation
> + *     files (the "Software"), to deal in the Software without
> + *     restriction, including without limitation the rights to use,
> + *     copy, modify, merge, publish, distribute, sublicense, and/or
> + *     sell copies of the Software, and to permit persons to whom the
> + *     Software is furnished to do so, subject to the following
> + *     conditions:
> + *
> + *     The above copyright notice and this permission notice shall be
> + *     included in all copies or substantial portions of the Software.
> + *
> + *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> + *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> + *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + *     OTHER DEALINGS IN THE SOFTWARE.
> + *
> + */
> +
> +#include <dt-bindings/gpio/gpio.h>
> +
> +/ {
> +	chosen {
> +		linux,stdout-path = &uart2;
> +
> +		environment-spinor {
> +			compatible = "barebox,environment";
> +			device-path = &flash_bareboxenv;
> +			status = "disabled";
> +		};
> +
> +		environment-sd4 {
> +			compatible = "barebox,environment";
> +			device-path = &usdhc4_bareboxenv;
> +			status = "disabled";
> +		};
> +	};
> +
> +	reg_3v3_s5: regulator at 0 {
> +		compatible = "regulator-fixed";
> +		regulator-name = "V_3V3_S5";
> +		regulator-min-microvolt = <3300000>;
> +		regulator-max-microvolt = <3300000>;
> +		regulator-boot-on;
> +		regulator-always-on;
> +	};
> +
> +	reg_1v8_s5: regulator at 1 {
> +		compatible = "regulator-fixed";
> +		regulator-name = "V_1V8_S5";
> +		regulator-min-microvolt = <1800000>;
> +		regulator-max-microvolt = <1800000>;
> +		regulator-boot-on;
> +		regulator-always-on;
> +	};
> +
> +	reg_3v3_s0: regulator at 2 {
> +		compatible = "regulator-fixed";
> +		regulator-name = "V_3V3_S0";
> +		regulator-min-microvolt = <3300000>;
> +		regulator-max-microvolt = <3300000>;
> +		regulator-boot-on;
> +		regulator-always-on;
> +	};
> +
> +	reg_1v0_s0: regulator at 3 {
> +		compatible = "regulator-fixed";
> +		regulator-name = "V_1V0_S0";
> +		regulator-min-microvolt = <1000000>;
> +		regulator-max-microvolt = <1000000>;
> +		regulator-boot-on;
> +		regulator-always-on;
> +	};
> +
> +	i2c_pfuze: i2c-gpio-0 {
> +		compatible = "i2c-gpio";
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&pinctrl_i2c_gpio_0>;
> +		sda-gpios = <&gpio1 28 0>;
> +		scl-gpios = <&gpio1 30 0>;
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		i2c-gpio,delay-us = <2>;
> +	};
> +};
> +
> +&can1 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_flexcan1>;
> +};
> +
> +&can2 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_flexcan2>;
> +};
> +
> +&fec {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_enet_smarc>;
> +	phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
> +	phy-mode = "rgmii";
> +	status = "okay";
> +};
> +
> +&i2c_pfuze {
> +	pfuze100 at 08 {
> +		compatible = "fsl,pfuze100";
> +		reg = <0x08>;
> +
> +		/* Looks unused by pfuze100 driver */
> +		interrupt-parent = <&gpio7>;
> +		interrupts = <13 IRQ_TYPE_LEVEL_LOW>;
> +
> +		regulators {
> +			reg_v_core_s0: sw1ab {
> +				regulator-name = "V_CORE_S0";
> +				regulator-min-microvolt = <300000>;
> +				regulator-max-microvolt = <1875000>;
> +				regulator-boot-on;
> +				regulator-always-on;
> +			};
> +
> +			reg_vddsoc_s0: sw1c {
> +				regulator-name = "V_VDDSOC_S0";
> +				regulator-min-microvolt = <300000>;
> +				regulator-max-microvolt = <1875000>;
> +				regulator-boot-on;
> +				regulator-always-on;
> +			};
> +
> +			reg_3v15_s0: sw2 {
> +				regulator-name = "V_3V15_S0";
> +				regulator-min-microvolt = <800000>;
> +				regulator-max-microvolt = <3300000>;
> +				regulator-boot-on;
> +				regulator-always-on;
> +			};
> +
> +			/* sw3a/b is used in dual mode, but driver does not
> +			 * support it? Although, there's no need to control
> +			 * DDR power - so just leaving dummy entries for sw3a
> +			 * and sw3b for now.
> +			 */
> +			sw3a {
> +				regulator-min-microvolt = <400000>;
> +				regulator-max-microvolt = <1975000>;
> +				regulator-boot-on;
> +				regulator-always-on;
> +			};
> +
> +			sw3b {
> +				regulator-min-microvolt = <400000>;
> +				regulator-max-microvolt = <1975000>;
> +				regulator-boot-on;
> +				regulator-always-on;
> +			};
> +
> +			reg_1v8_s0: sw4 {
> +				regulator-name = "V_1V8_S0";
> +				regulator-min-microvolt = <800000>;
> +				regulator-max-microvolt = <3300000>;
> +				regulator-boot-on;
> +				regulator-always-on;
> +			};
> +
> +			/* Regulator for USB */
> +			reg_5v0_s0: swbst {
> +				regulator-name = "V_5V0_S0";
> +				regulator-min-microvolt = <5000000>;
> +				regulator-max-microvolt = <5150000>;
> +				regulator-boot-on;
> +			};
> +
> +			reg_vsnvs: vsnvs {
> +				regulator-min-microvolt = <1000000>;
> +				regulator-max-microvolt = <3000000>;
> +				regulator-boot-on;
> +				regulator-always-on;
> +			};
> +
> +			reg_vrefddr: vrefddr {
> +				regulator-boot-on;
> +				regulator-always-on;
> +			};
> +
> +			/* Per schematics, of all VGEN's, only VGEN5 has some
> +			 * usage ... but even that - over DNI resistor
> +			 */
> +			vgen1 {
> +				regulator-min-microvolt = <800000>;
> +				regulator-max-microvolt = <1550000>;
> +			};
> +
> +			vgen2 {
> +				regulator-min-microvolt = <800000>;
> +				regulator-max-microvolt = <1550000>;
> +			};
> +
> +			vgen3 {
> +				regulator-min-microvolt = <1800000>;
> +				regulator-max-microvolt = <3300000>;
> +			};
> +
> +			vgen4 {
> +				regulator-min-microvolt = <1800000>;
> +				regulator-max-microvolt = <3300000>;
> +			};
> +
> +			reg_2v5_s0: vgen5 {
> +				regulator-name = "V_2V5_S0";
> +				regulator-min-microvolt = <1800000>;
> +				regulator-max-microvolt = <3300000>;
> +			};
> +
> +			vgen6 {
> +				regulator-min-microvolt = <1800000>;
> +				regulator-max-microvolt = <3300000>;
> +			};
> +		};
> +	};
> +};
> +
> +&ecspi4 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_ecspi4>;
> +	fsl,spi-num-chipselects = <3>;
> +	cs-gpios = <&gpio3 24 0>, <&gpio3 29 0>, <&gpio3 25 0>;
> +	status = "okay";
> +
> +	flash: m25p80 at 0 {
> +		compatible = "winbond,w25q16dw", "jedec,spi-nor";
> +		spi-max-frequency = <20000000>;
> +		reg = <0>;
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +
> +		partition at 0 {
> +			label = "bootloader";
> +			reg = <0x000000 0x0c0000>;
> +		};
> +
> +		flash_bareboxenv: partition at c0000 {
> +			label = "environment";
> +			reg = <0x0c0000 0x010000>;
> +		};
> +
> +		partition at d0000 {
> +			label = "user";
> +			reg = <0x0d0000 0x130000>;
> +		};
> +	};
> +};
> +
> +&i2c3 {
> +	clock-frequency = <100000>;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_i2c3>;
> +};
> +
> +&pcie {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_pcie>;
> +	wake-up-gpio = <&gpio6 18 GPIO_ACTIVE_HIGH>;
> +	reset-gpio = <&gpio3 13 GPIO_ACTIVE_HIGH>;
> +};
> +
> +&uart1 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_uart1_smarc>;
> +	fsl,uart-has-rtscts;
> +};
> +
> +&uart2 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_uart2_smarc>;
> +	status = "okay";
> +};
> +
> +&uart4 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_uart4_smarc>;
> +	fsl,uart-has-rtscts;
> +};
> +
> +&uart5 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_uart5_smarc>;
> +};
> +
> +&usbotg {
> +	/*
> +	 * no 'imx6-usb-charger-detection'
> +	 * since USB_OTG_CHD_B pin is not wired
> +	 */
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_usbotg>;
> +	status = "okay";
> +};
> +
> +&usbh1 {
> +	vbus-supply = <&reg_5v0_s0>;
> +	status = "okay";
> +};
> +
> +&usdhc4 {
> +	/* Internal eMMC, optional on some boards */
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_usdhc4>;
> +	bus-width = <8>;
> +	no-1-8-v;
> +	non-removable;
> +	status = "okay";
> +	#address-cells = <1>;
> +	#size-cells = <1>;
> +
> +	partition at 0 {
> +		label = "bootloader";
> +		reg = <0x0 0xe0000>;
> +	};
> +
> +	usdhc4_bareboxenv: partition at e0000 {
> +		label = "environment";
> +		reg = <0xe0000 0x20000>;
> +	};
> +};
> +
> +&iomuxc {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_boot>;
> +
> +	pinctrl_boot: boot {
> +		fsl,pins = <
> +			/* GPIOS for version and id detection */
> +			MX6QDL_PAD_NANDF_CLE__GPIO6_IO07	0x80000000
> +			MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09	0x80000000
> +			MX6QDL_PAD_NANDF_D2__GPIO2_IO02		0x80000000
> +		>;
> +	};
> +
> +	pinctrl_flexcan1: flexcan1-smarc {
> +		fsl,pins = <
> +			MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x80000000
> +			MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x80000000
> +		>;
> +	};
> +
> +	pinctrl_flexcan2: flexcan2-smarc {
> +		fsl,pins = <
> +			MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x80000000
> +			MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x80000000
> +		>;
> +	};
> +
> +	pinctrl_enet_smarc: fecgrp-smarc {
> +		fsl,pins = <
> +			MX6QDL_PAD_ENET_MDIO__ENET_MDIO       0x1b0b0
> +			MX6QDL_PAD_ENET_MDC__ENET_MDC         0x1b0b0
> +			MX6QDL_PAD_RGMII_TXC__RGMII_TXC       0x1b0b0
> +			MX6QDL_PAD_RGMII_TD0__RGMII_TD0       0x1b0b0
> +			MX6QDL_PAD_RGMII_TD1__RGMII_TD1       0x1b0b0
> +			MX6QDL_PAD_RGMII_TD2__RGMII_TD2       0x1b0b0
> +			MX6QDL_PAD_RGMII_TD3__RGMII_TD3       0x1b0b0
> +			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
> +			MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK  0x1b0b0
> +			MX6QDL_PAD_RGMII_RXC__RGMII_RXC       0x1b0b0
> +			MX6QDL_PAD_RGMII_RD0__RGMII_RD0       0x1b0b0
> +			MX6QDL_PAD_RGMII_RD1__RGMII_RD1       0x1b0b0
> +			MX6QDL_PAD_RGMII_RD2__RGMII_RD2       0x1b0b0
> +			MX6QDL_PAD_RGMII_RD3__RGMII_RD3       0x1b0b0
> +			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
> +			MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25    0x80000000
> +		>;
> +	};
> +
> +	pinctrl_i2c_gpio_0: i2c-gpio-0-smarc {
> +		fsl,pins = <
> +			/* SCL GPIO */
> +			MX6QDL_PAD_ENET_TXD0__GPIO1_IO30  0x80000000
> +			/* SDA GPIO */
> +			MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x80000000
> +		>;
> +	};
> +
> +	pinctrl_i2c3: i2c3-smarc {
> +		fsl,pins = <
> +			MX6QDL_PAD_EIM_D17__I2C3_SCL		0x4001b8b1
> +			MX6QDL_PAD_EIM_D18__I2C3_SDA		0x4001b8b1
> +		>;
> +	};
> +
> +	pinctrl_ecspi4: ecspi4-smarc {
> +		fsl,pins = <
> +			MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x80000000
> +			MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x80000000
> +			MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x80000000
> +                        MX6QDL_PAD_EIM_D29__ECSPI4_SS0  0x80000000

Just found this wrong indentation. If more work appears I will resend.
Otherwise, please fix on commit.

> +
> +			/* In hardware, ECSPI4's SS0,SS1,SS3 are wired.
> +			   But spi-imx driver support only continuous
> +			   numbering, and only can use GPIOs (and not
> +			   ECSPI's hardware SS) for CS. So linux view
> +			   of CS numbers differs from hw view, and
> +			   pins are configured as GPIOs */
> +
> +			/* physical - CS2, in linux - CS0, either internal flash or SMARC CS0 */
> +			MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x80000000
> +			/* physical - CS0, in linux - CS1, either SMARC CS0 or not-connected */
> +			MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x80000000
> +			/* physical - CS3, in linux - CS2, SMARC CS1 */
> +			MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x80000000
> +		>;
> +	};
> +
> +	pinctrl_pcie: pcie-smarc {
> +		fsl,pins = <
> +			/* RST_PCIE_A# */
> +			MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x80000000
> +			/* PCIE_WAKE# */
> +			MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0x80000000
> +		>;
> +	};
> +
> +	pinctrl_uart1_smarc: uart1grp-smarc {
> +		fsl,pins = <
> +			MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
> +			MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
> +			MX6QDL_PAD_EIM_D20__UART1_RTS_B 0x1b0b1
> +			MX6QDL_PAD_EIM_D19__UART1_CTS_B 0x1b0b1
> +		>;
> +	};
> +
> +	pinctrl_uart2_smarc: uart2grp-smarc {
> +		fsl,pins = <
> +			MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
> +			MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
> +		>;
> +	};
> +
> +	pinctrl_uart4_smarc: uart4grp-smarc {
> +		fsl,pins = <
> +			MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1
> +			MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1
> +			MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1
> +			MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1
> +		>;
> +	};
> +
> +	pinctrl_uart5_smarc: uart5grp-smarc {
> +		fsl,pins = <
> +			MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x1b0b1
> +			MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x1b0b1
> +		>;
> +	};
> +
> +	pinctrl_usbotg: usbotg-grp-smarc {
> +		fsl,pins = <
> +			MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x1f8b0
> +			/* TODO: Comment out power and OC gpio's for now, since
> +			 * these are not used by driver
> +			 */
> +			/* USB power */
> +			// MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x80000000
> +			/* USB OC */
> +			// MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x80000000
> +		>;
> +	};
> +
> +	pinctrl_usdhc4: usdhc4grp-smarc {
> +		fsl,pins = <
> +			MX6QDL_PAD_SD4_CLK__SD4_CLK 0x17059
> +			MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
> +			MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
> +			MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
> +			MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
> +			MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
> +			MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
> +			MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
> +			MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
> +			MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
> +		>;
> +	};
> +};
> diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
> index eb135c3f53..cf5338e5fa 100644
> --- a/arch/arm/mach-imx/Kconfig
> +++ b/arch/arm/mach-imx/Kconfig
> @@ -294,6 +294,10 @@ config MACH_PHYTEC_SOM_IMX6
>          select ARCH_IMX6
>  	select ARCH_IMX6UL
>  
> +config MACH_KONTRON_SAMX6I
> +        bool "Kontron sAMX6i"
> +        select ARCH_IMX6
> +
>  config MACH_DFI_FS700_M60
>  	bool "DFI i.MX6 FS700 M60 Q7 Board"
>  	select ARCH_IMX6
> diff --git a/images/Makefile.imx b/images/Makefile.imx
> index 5e0043f1f0..0428c48ade 100644
> --- a/images/Makefile.imx
> +++ b/images/Makefile.imx
> @@ -455,6 +455,16 @@ CFG_start_phytec_phycore_imx6ull_som_256mb.pblx.imximg = $(board)/phytec-som-imx
>  FILE_barebox-phytec-phycore-imx6ull-256mb.img = start_phytec_phycore_imx6ull_som_256mb.pblx.imximg
>  image-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += barebox-phytec-phycore-imx6ull-256mb.img
>  
> +pblx-$(CONFIG_MACH_KONTRON_SAMX6I) += start_imx6q_samx6i
> +CFG_start_imx6q_samx6i.pblx.imximg = $(board)/kontron-samx6i/flash-header-samx6i-quad.imxcfg
> +FILE_barebox-imx6q-samx6i.img = start_imx6q_samx6i.pblx.imximg
> +image-$(CONFIG_MACH_KONTRON_SAMX6I) += barebox-imx6q-samx6i.img
> +
> +pblx-$(CONFIG_MACH_KONTRON_SAMX6I) += start_imx6dl_samx6i
> +CFG_start_imx6dl_samx6i.pblx.imximg = $(board)/kontron-samx6i/flash-header-samx6i-duallite.imxcfg
> +FILE_barebox-imx6dl-samx6i.img = start_imx6dl_samx6i.pblx.imximg
> +image-$(CONFIG_MACH_KONTRON_SAMX6I) += barebox-imx6dl-samx6i.img
> +
>  pblx-$(CONFIG_MACH_GW_VENTANA) += start_imx6q_gw54xx_1gx64
>  CFG_start_imx6q_gw54xx_1gx64.pblx.imximg = $(board)/gateworks-ventana/flash-header-ventana-quad-1gx64.imxcfg
>  FILE_barebox-gateworks-imx6q-ventana-1gx64.img = start_imx6q_gw54xx_1gx64.pblx.imximg
> -- 
> 2.16.1
> 
> 
> _______________________________________________
> barebox mailing list
> barebox at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/barebox
> 

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |
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From p.zabel at pengutronix.de  Mon Mar 19 04:57:14 2018
From: p.zabel at pengutronix.de (Philipp Zabel)
Date: Mon, 19 Mar 2018 12:57:14 +0100
Subject: [PATCH] reset-source: pass reset reason to kernel via device tree
Message-ID: <20180319115714.1238-1-p.zabel@pengutronix.de>

Add a device tree fixup that adds a /chosen/barebox-reset-reason string
property to the device tree chosen node. It can be read under Linux in
/sys/firmware/devicetree/base/chosen/barebox-reset-reason.

Signed-off-by: Philipp Zabel <p.zabel at pengutronix.de>
---
 Documentation/user/reset-reason.rst |  3 +++
 common/reset_source.c               | 22 ++++++++++++++++++++++
 2 files changed, 25 insertions(+)

diff --git a/Documentation/user/reset-reason.rst b/Documentation/user/reset-reason.rst
index 26d37f86dd..26022ba6d7 100644
--- a/Documentation/user/reset-reason.rst
+++ b/Documentation/user/reset-reason.rst
@@ -45,3 +45,6 @@ The following values can help to detect the reason why the bootloader runs:
 It depends on your board/SoC and its features if the hardware is able to detect
 these reset reasons. Most of the time only ``POR`` and ``RST`` are supported
 but often ``WDG`` as well.
+
+The reset reason is passed to the kernel via the device tree property string
+``/chosen/barebox-reset-reason``.
diff --git a/common/reset_source.c b/common/reset_source.c
index 06e2ca85f5..e14ba3fc16 100644
--- a/common/reset_source.c
+++ b/common/reset_source.c
@@ -77,3 +77,25 @@ unsigned int of_get_reset_source_priority(struct device_node *node)
 
 	return priority;
 }
+
+#ifdef CONFIG_OFTREE
+static int reset_source_of_fixup(struct device_node *root, void *context)
+{
+	struct device_node *node;
+
+	node = of_create_node(root, "/chosen");
+	if (!node)
+		return -ENOMEM;
+
+	return of_property_write_string(node, "barebox-reset-reason",
+			reset_src_names[reset_source]);
+}
+
+static int reset_source_register_of_fixup(void)
+{
+	of_register_fixup(reset_source_of_fixup, NULL);
+
+	return 0;
+}
+late_initcall(reset_source_register_of_fixup);
+#endif
-- 
2.16.1



From andrew.smirnov at gmail.com  Tue Mar 20 21:53:56 2018
From: andrew.smirnov at gmail.com (Andrey Smirnov)
Date: Tue, 20 Mar 2018 21:53:56 -0700
Subject: [PATCH 61/78] ARM: aarch64: mmu: Make zero page faulting
In-Reply-To: <20180316125354.23462-62-s.hauer@pengutronix.de>
References: <20180316125354.23462-1-s.hauer@pengutronix.de>
 <20180316125354.23462-62-s.hauer@pengutronix.de>
Message-ID: <CAHQ1cqEAim+g-NWynFYkX_0MeB9PYzOiXPFiV5=uyfzqnDBy8A@mail.gmail.com>

On Fri, Mar 16, 2018 at 5:53 AM, Sascha Hauer <s.hauer at pengutronix.de> wrote:
> Make zero page faulting which allows us to catch NULL pointer derefs.
>
> Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
> ---
>  arch/arm/cpu/mmu_64.c | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm/cpu/mmu_64.c b/arch/arm/cpu/mmu_64.c
> index 20f6c387f3..094bc0ac62 100644
> --- a/arch/arm/cpu/mmu_64.c
> +++ b/arch/arm/cpu/mmu_64.c
> @@ -316,6 +316,8 @@ static int mmu_init(void)
>         for_each_memory_bank(bank)
>                 create_sections(bank->start, bank->start, bank->size, CACHED_MEM);
>
> +       create_sections(0x0, 0x0, 0x1000, 0x0);

Sascha:

Maybe add commit message as comment to the line above as well?


Thanks,
Andrey Smirnov

> +
>         mmu_enable();
>
>         return 0;
> --
> 2.16.1
>
>
> _______________________________________________
> barebox mailing list
> barebox at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/barebox


From andrew.smirnov at gmail.com  Tue Mar 20 22:27:37 2018
From: andrew.smirnov at gmail.com (Andrey Smirnov)
Date: Tue, 20 Mar 2018 22:27:37 -0700
Subject: [PATCH 30/78] ARM: aarch64: Add relocation support
In-Reply-To: <20180319085019.qbcgurw2aspsmxcr@pengutronix.de>
References: <20180316125354.23462-1-s.hauer@pengutronix.de>
 <20180316125354.23462-31-s.hauer@pengutronix.de>
 <CAHQ1cqGbkHN+Csi7-Bb=_iTea4zXK3-mmK8EK0x-UW9niHNCQg@mail.gmail.com>
 <20180319085019.qbcgurw2aspsmxcr@pengutronix.de>
Message-ID: <CAHQ1cqH+FNuwxYzV6YKv9LNi=DPt_DbK1K3WNzQkMs0eL89vag@mail.gmail.com>

On Mon, Mar 19, 2018 at 1:50 AM, Sascha Hauer <s.hauer at pengutronix.de> wrote:
> Hi Andrey,
>
> On Fri, Mar 16, 2018 at 02:51:19PM -0700, Andrey Smirnov wrote:
>> On Fri, Mar 16, 2018 at 5:53 AM, Sascha Hauer <s.hauer at pengutronix.de> wrote:
>> > This adds aarch64 support for relocating binaries linked with -pie.
>> >
>> > Support is integrated into the already exisiting
>> > relocate_to_current_adr() function which is now used for both arm32
>> > and aarch64.
>> >
>> > Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
>>
>>
>> Sascha:
>>
>> Two small suggestions w.r.t. this patch:
>>
>>  - I'd consider changing the code of relocate_to_current_adr() such
>> that AARCH64 specific codepaths are not taken on ARM32 (via IS_ENABLED
>> check or something similar)
>
> Why? Do you want to make the code more clear or do you fear that we
> apply fixups for a foreign architecture?
>

You'd be able to get the value of *_R_TYPE(type) once and then use
switch to structure code handling various types, which might be a bit
more readable. But that 50% personal preference, so feel free to keep
the code as is.

>>
>>  - I've always wanted to fix the original code to use Elf32_rel type
>> instead of magic hard-coded offsets, so depending on your
>> willingness/time-budget, maybe now would be a good time to do that as
>> well as use Elf64_rela for AARCH64?
>
> You mean using
>
>> struct elf32_rel {
>>       Elf32_Addr    r_offset;
>>       Elf32_Word    r_info;
>> } Elf32_Rel;
>
> and:
>
>> struct elf64_rela {
>>       Elf64_Addr r_offset;  /* Location at which to apply the action */
>>       Elf64_Xword r_info;   /* index and type of relocation */
>>       Elf64_Sxword r_addend;        /* Constant addend used to compute value */
>> } Elf64_Rela;
>
> ?

Yep, those are the two types.

>
> Yes, I can change that. I wonder though which type is behind R_ARM_ABS32
>

I think its still would be Elf32_Rel. From what I can tell both
R_ARM_ABS32 and R_ARM_RELATIVE calculate "*fixup = *fixup + offset"
using same pointer offsets it's just former also adds "r" that is
derived from "r_info". With enough #ifdefing it might even be possible
to convert that while() to a for() loop.

Thanks,
Andrey Smirnov


From andrew.smirnov at gmail.com  Tue Mar 20 22:35:42 2018
From: andrew.smirnov at gmail.com (Andrey Smirnov)
Date: Tue, 20 Mar 2018 22:35:42 -0700
Subject: [PATCH 00/78] ARM aarch64 updates
In-Reply-To: <20180316125354.23462-1-s.hauer@pengutronix.de>
References: <20180316125354.23462-1-s.hauer@pengutronix.de>
Message-ID: <CAHQ1cqE7MiV_eq3LBSQQM8bgJZo3rVGOsZzgJ4mVXB42KFeAYA@mail.gmail.com>

On Fri, Mar 16, 2018 at 5:52 AM, Sascha Hauer <s.hauer at pengutronix.de> wrote:
> Hi All,
>
> Here is a massive update for the ARM aarch64 port. With the following
> series the aarch64 port should be on par with the 32bit support.
>
> With this aarch64 supports relocatable binaries, proper MMU support, DMA
> cache maintenance operations, and finally starting a aarch64 Linux
> image :)
>
> This all has been developed on a i.MX8MQ EVK board. The i.MX8MQ patches
> are currently evolving, but are not yet quite ready. DDR setup is still
> very crude and pinmux is not yet working. NXP did a nice job with the
> i.MX8MQ: It behaves very much like a i.MX6 with a different core, so
> we already have most of the drivers and I could concentrate on the
> aarch64 update. I hope I can send i.MX8 patches soon.

Sascha:

I only vaguely familiar with AARCH64, so take the tag with a grain of
salt, but I read through the patchset and it all looks reasonable, so
FWIW:

Reviewed-by: Andrey Smirnov <andrew.smirnov at gmail.com>

I commented on individual patches with suggestions, but they are just
that, so feel free to ignore.

Thanks,
Andrey Smirnov


From andrew.smirnov at gmail.com  Tue Mar 20 22:41:17 2018
From: andrew.smirnov at gmail.com (Andrey Smirnov)
Date: Tue, 20 Mar 2018 22:41:17 -0700
Subject: [PATCH 00/14] ARM: i.MX8MQ and EVK support
In-Reply-To: <20180319091146.4112-1-s.hauer@pengutronix.de>
References: <20180319091146.4112-1-s.hauer@pengutronix.de>
Message-ID: <CAHQ1cqGxgwDd7bdNtaE5xZbSfcXhBCmRe_wAG1y9aFiKfrDBAw@mail.gmail.com>

On Mon, Mar 19, 2018 at 2:11 AM, Sascha Hauer <s.hauer at pengutronix.de> wrote:
> This series adds support for the i.MX8MQ SoC and the EVK board from NXP.
> Currently only 2nd stage after U-Boot is supported, 1st stage support
> will still need some time. Besides of the missing first stage support
> the EVK support should be fairly complete already, as the i.MX8MQ is
> very similar to the i.MX6 and only the core has been changed.
>
> This series is likely not the final one as the clock driver and the
> device tree are derived from mailing list patches and not from the
> final versions (which do not exist yet).

Sascha:

Same as with other i.MX8 patchset, take it with a grain of salt, but FWIW:

Reviewed-by: Andrey Smirnov <andrew.smirnov at gmail.com>

Thanks,
Andrey Smirnov

>
> Sascha
>
> Sascha Hauer (14):
>   ARM: i.MX: xload: Fix compiler warning
>   ARM: i.MX: compile arm32 specific errata only for CPU32
>   ARM: Add i.MX8 support
>   aarch64: Add i.MX8 debug UART support
>   Include our own include/dt-bindings
>   ARM: i.MX8: Add i.MX8mq EVK support
>   mci: imx-esdhc: use dma mapping functions
>   net: fec_imx: remove unnecessary DMA sync ops
>   net: fec_imx: Use dma mapping functions
>   clock: Add i.MX8MQ clock driver
>   serial: i.MX: Add i.MX8 support
>   mmc: i.MX esdhc: Add i.MX8 support
>   gpio: i.MX: Add i.MX8mq support
>   ARM: i.MX: ocotp: Add i.MX8MQ support
>
>  arch/arm/boards/Makefile                       |   1 +
>  arch/arm/boards/nxp-imx8mq-evk/Makefile        |   2 +
>  arch/arm/boards/nxp-imx8mq-evk/board.c         |  44 ++
>  arch/arm/boards/nxp-imx8mq-evk/lowlevel.c      |  43 ++
>  arch/arm/dts/Makefile                          |   1 +
>  arch/arm/dts/imx8mq-evk.dts                    | 446 ++++++++++++++++++
>  arch/arm/dts/imx8mq-pinfunc.h                  | 623 ++++++++++++++++++++++++
>  arch/arm/dts/imx8mq.dtsi                       | 624 ++++++++++++++++++++++++
>  arch/arm/mach-imx/Kconfig                      |  15 +-
>  arch/arm/mach-imx/Makefile                     |   1 +
>  arch/arm/mach-imx/cpu_init.c                   |   2 +
>  arch/arm/mach-imx/imx.c                        |   4 +
>  arch/arm/mach-imx/imx8mq.c                     |  66 +++
>  arch/arm/mach-imx/include/mach/debug_ll.h      |   3 +
>  arch/arm/mach-imx/include/mach/generic.h       |  13 +
>  arch/arm/mach-imx/include/mach/imx8mq-regs.h   | 121 +++++
>  arch/arm/mach-imx/include/mach/imx_cpu_types.h |   1 +
>  arch/arm/mach-imx/ocotp.c                      |  10 +
>  arch/arm/mach-imx/xload-esdhc.c                |   7 +-
>  arch/mips/dts/include/dt-bindings              |   1 -
>  common/Kconfig                                 |   8 +
>  drivers/clk/imx/Makefile                       |   3 +
>  drivers/clk/imx/clk-frac-pll.c                 | 226 +++++++++
>  drivers/clk/imx/clk-imx8mq.c                   | 580 +++++++++++++++++++++++
>  drivers/clk/imx/clk-sccg-pll.c                 | 242 ++++++++++
>  drivers/clk/imx/clk.h                          |  27 ++
>  drivers/gpio/gpio-imx.c                        |   3 +
>  drivers/mci/imx-esdhc.c                        |  54 +--
>  drivers/net/fec_imx.c                          |  19 +-
>  drivers/net/fec_imx.h                          |   1 +
>  drivers/serial/serial_imx.c                    |   5 +-
>  images/Makefile.imx                            |   6 +
>  include/dt-bindings/clock/imx8mq-clock.h       | 629 +++++++++++++++++++++++++
>  include/serial/imx-uart.h                      |   5 +
>  scripts/Makefile.lib                           |   1 +
>  35 files changed, 3796 insertions(+), 41 deletions(-)
>  create mode 100644 arch/arm/boards/nxp-imx8mq-evk/Makefile
>  create mode 100644 arch/arm/boards/nxp-imx8mq-evk/board.c
>  create mode 100644 arch/arm/boards/nxp-imx8mq-evk/lowlevel.c
>  create mode 100644 arch/arm/dts/imx8mq-evk.dts
>  create mode 100644 arch/arm/dts/imx8mq-pinfunc.h
>  create mode 100644 arch/arm/dts/imx8mq.dtsi
>  create mode 100644 arch/arm/mach-imx/imx8mq.c
>  create mode 100644 arch/arm/mach-imx/include/mach/imx8mq-regs.h
>  delete mode 120000 arch/mips/dts/include/dt-bindings
>  create mode 100644 drivers/clk/imx/clk-frac-pll.c
>  create mode 100644 drivers/clk/imx/clk-imx8mq.c
>  create mode 100644 drivers/clk/imx/clk-sccg-pll.c
>  create mode 100644 include/dt-bindings/clock/imx8mq-clock.h
>
> --
> 2.16.1
>
>
> _______________________________________________
> barebox mailing list
> barebox at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/barebox


From s.hauer at pengutronix.de  Wed Mar 21 01:04:09 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Wed, 21 Mar 2018 09:04:09 +0100
Subject: [PATCH v2 0/2] Add support for kontron samx6i boards
In-Reply-To: <20180319092120.11773-1-m.grzeschik@pengutronix.de>
References: <20180319092120.11773-1-m.grzeschik@pengutronix.de>
Message-ID: <20180321080409.dfuhca4jkg6rlxfb@pengutronix.de>

On Mon, Mar 19, 2018 at 10:21:18AM +0100, Michael Grzeschik wrote:
> These patches add support for the kontron samx6i smarc modules.
> The memory size gets selected by gpio setup in the lowlevel setup.
> For this we add some lowlevel gpio input functions.
> 
> Michael Grzeschik (2):
>   ARM: i.MX: Add lowlevel gpio input functions
>   boards: samx6: add initial support for kontron samx6i

Applied with your additional whitespace fixup.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From s.hauer at pengutronix.de  Wed Mar 21 01:14:40 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Wed, 21 Mar 2018 09:14:40 +0100
Subject: [PATCH v3] watchdog: add watchdog poller
In-Reply-To: <20180319103731.5629-1-o.rempel@pengutronix.de>
References: <20180319103731.5629-1-o.rempel@pengutronix.de>
Message-ID: <20180321081440.ha4774t3mi2i3fc4@pengutronix.de>

On Mon, Mar 19, 2018 at 11:37:31AM +0100, Oleksij Rempel wrote:
> In some cases it is practical to supervise as much as possible of
> the barebox execution with a watchdog (or multiple watchdogs). This
> patch provides an async poller for watchdog core framework which can
> be enabled by the user and stores this configuration to nv.
> 
> Signed-off-by: Oleksij Rempel <o.rempel at pengutronix.de>
> ---
> changes v3:
> - rename variable to automatic_dog_feeder

Applied with "infinite_dog_food" .. wait .. no .. "autoping" as variable
name.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From s.hauer at pengutronix.de  Wed Mar 21 04:26:09 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Wed, 21 Mar 2018 12:26:09 +0100
Subject: [PATCH v2 30/78] ARM: aarch64: Add relocation support
In-Reply-To: <20180316125354.23462-31-s.hauer@pengutronix.de>
References: <20180316125354.23462-1-s.hauer@pengutronix.de>
 <20180316125354.23462-31-s.hauer@pengutronix.de>
Message-ID: <20180321112609.pfn4at7zbat7xapf@pengutronix.de>


Ok, here's an updated version.

--------------------------------8<------------------------------

This adds aarch64 support for relocating binaries linked with -pie.

Support is integrated into the already exisiting
relocate_to_current_adr() function which is now used for both arm32
and aarch64.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/cpu/common.c    | 69 ++++++++++++++++++++++++++++++++++++++----------
 arch/arm/cpu/setupc_64.S | 60 +++++++++++++++++++++++++++++++++++++++++
 common/Kconfig           |  2 +-
 3 files changed, 116 insertions(+), 15 deletions(-)

diff --git a/arch/arm/cpu/common.c b/arch/arm/cpu/common.c
index 7c07d00c1b..00ce3efb2f 100644
--- a/arch/arm/cpu/common.c
+++ b/arch/arm/cpu/common.c
@@ -17,6 +17,7 @@
 
 #include <common.h>
 #include <init.h>
+#include <elf.h>
 #include <linux/sizes.h>
 #include <asm/system_info.h>
 #include <asm/barebox-arm.h>
@@ -24,42 +25,82 @@
 #include <asm-generic/memory_layout.h>
 #include <asm/sections.h>
 #include <asm/cache.h>
+#include <debug_ll.h>
+
+#define R_ARM_RELATIVE 23
+#define R_AARCH64_RELATIVE 1027
 
 /*
  * relocate binary to the currently running address
  */
 void relocate_to_current_adr(void)
 {
-	uint32_t offset;
-	uint32_t *dstart, *dend, *dynsym, *dynend;
+	unsigned long offset, offset_var;
+	unsigned long __maybe_unused *dynsym, *dynend;
+	void *dstart, *dend;
 
 	/* Get offset between linked address and runtime address */
 	offset = get_runtime_offset();
+	offset_var = global_variable_offset();
+
+	dstart = (void *)__rel_dyn_start + offset_var;
+	dend = (void *)__rel_dyn_end + offset_var;
 
-	dstart = (void *)__rel_dyn_start + offset;
-	dend = (void *)__rel_dyn_end + offset;
+#if defined(CONFIG_CPU_64)
+	while (dstart < dend) {
+		struct elf64_rela *rel = dstart;
 
-	dynsym = (void *)__dynsym_start + offset;
-	dynend = (void *)__dynsym_end + offset;
+		if (ELF64_R_TYPE(rel->r_info) == R_AARCH64_RELATIVE) {
+			unsigned long *fixup = (unsigned long *)(rel->r_offset + offset);
+
+			*fixup = rel->r_addend + offset;
+		} else {
+			putc_ll('>');
+			puthex_ll(rel->r_info);
+			putc_ll(' ');
+			puthex_ll(rel->r_offset);
+			putc_ll(' ');
+			puthex_ll(rel->r_addend);
+			putc_ll('\n');
+			panic("");
+		}
+
+		dstart += sizeof(*rel);
+	}
+#elif defined(CONFIG_CPU_32)
+	dynsym = (void *)__dynsym_start + offset_var;
+	dynend = (void *)__dynsym_end + offset_var;
 
 	while (dstart < dend) {
-		uint32_t *fixup = (uint32_t *)(*dstart + offset);
-		uint32_t type = *(dstart + 1);
+		struct elf32_rel *rel = dstart;
+
+		if (ELF32_R_TYPE(rel->r_info) == R_ARM_RELATIVE) {
+			unsigned long *fixup = (unsigned long *)(rel->r_offset + offset);
 
-		if ((type & 0xff) == 0x17) {
 			*fixup = *fixup + offset;
-		} else {
-			int index = type >> 8;
-			uint32_t r = dynsym[index * 4 + 1];
+
+			rel->r_offset += offset;
+		} else if (ELF32_R_TYPE(rel->r_info) == R_ARM_ABS32) {
+			unsigned long r = dynsym[ELF32_R_SYM(rel->r_info) * 4 + 1];
+			unsigned long *fixup = (unsigned long *)(rel->r_offset + offset);
 
 			*fixup = *fixup + r + offset;
+		} else {
+			putc_ll('>');
+			puthex_ll(rel->r_info);
+			putc_ll(' ');
+			puthex_ll(rel->r_offset);
+			putc_ll('\n');
+			panic("");
 		}
 
-		*dstart += offset;
-		dstart += 2;
+		dstart += sizeof(*rel);
 	}
 
 	memset(dynsym, 0, (unsigned long)dynend - (unsigned long)dynsym);
+#else
+#error "Architecture not specified"
+#endif
 
 	arm_early_mmu_cache_flush();
 	icache_invalidate();
diff --git a/arch/arm/cpu/setupc_64.S b/arch/arm/cpu/setupc_64.S
index 3515854784..13f19fcc4d 100644
--- a/arch/arm/cpu/setupc_64.S
+++ b/arch/arm/cpu/setupc_64.S
@@ -16,3 +16,63 @@ ENTRY(setup_c)
 	mov	x30, x15
 	ret
 ENDPROC(setup_c)
+
+/*
+ * void relocate_to_adr(unsigned long targetadr)
+ *
+ * Copy binary to targetadr, relocate code and continue
+ * executing at new address.
+ */
+.section .text.relocate_to_adr
+ENTRY(relocate_to_adr)
+					/* x0: target address */
+
+	stp	x19, x20, [sp, #-16]!
+	stp	x21, x22, [sp, #-16]!
+
+	mov	x19, lr
+
+	mov	x21, x0
+
+	bl	get_runtime_offset
+	mov	x5, x0
+
+	ldr	x0, =_text
+	mov	x20, x0
+
+	add	x1, x0, x5		/* x1: from address */
+
+	cmp	x1, x21			/* already at correct address? */
+	beq	1f			/* yes, skip copy to new address */
+
+	ldr	x2, =__bss_start
+
+	sub	x2, x2, x0		/* x2: size */
+	mov	x0, x21			/* x0: target */
+
+	/* adjust return address */
+	sub	x19, x19, x1		/* sub address where we are actually running */
+	add	x19, x19, x0		/* add address where we are going to run */
+
+	bl	memcpy			/* copy binary */
+
+#ifdef CONFIG_MMU
+	bl	arm_early_mmu_cache_flush
+#endif
+	mov	x0,#0
+	ic	ivau, x0	/* flush icache */
+
+	ldr	x0,=1f
+	sub	x0, x0, x20
+	add	x0, x0, x21
+	br	x0			/* jump to relocated address */
+1:
+	bl	relocate_to_current_adr	/* relocate binary */
+
+	mov	lr, x19
+
+	ldp	x21, x22, [sp], #16
+	ldp	x19, x20, [sp], #16
+	ret
+
+ENDPROC(relocate_to_adr)
diff --git a/common/Kconfig b/common/Kconfig
index af71d6888a..b7000c4d73 100644
--- a/common/Kconfig
+++ b/common/Kconfig
@@ -344,7 +344,7 @@ config KALLSYMS
 	  This is useful to print a nice backtrace when an exception occurs.
 
 config RELOCATABLE
-	depends on PPC || (ARM && !CPU_V8)
+	depends on PPC || ARM
 	bool "generate relocatable barebox binary"
 	help
 	  A non relocatable barebox binary will run at it's compiled in
-- 
2.16.1

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From s.hauer at pengutronix.de  Thu Mar 22 00:54:38 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Thu, 22 Mar 2018 08:54:38 +0100
Subject: [PATCH 2/2] mtd: spi-nor: add manufacturer IDs for ISSI and Winbond
In-Reply-To: <20180322075438.10581-1-s.hauer@pengutronix.de>
References: <20180322075438.10581-1-s.hauer@pengutronix.de>
Message-ID: <20180322075438.10581-2-s.hauer@pengutronix.de>

From: michael grassmann <m.grassmann at phytec.de>

This patch includes new NOR flash IDs to support flashes from the
manufacturers ISSI and Winbond
- ISSI IS25LP128-JBLA3 and IS25LP128-JBLE
- Winbond W25Q128JVSIM

Signed-off-by: michael grassmann <m.grassmann at phytec.de>
Signed-off-by: Christian Hemp <c.hemp at phytec.de>
---
 drivers/mtd/spi-nor/spi-nor.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index 057638ec5a..d15a795413 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -519,6 +519,9 @@ static const struct spi_device_id spi_nor_ids[] = {
 	{ "320s33b",  INFO(0x898912, 0, 64 * 1024,  64, 0) },
 	{ "640s33b",  INFO(0x898913, 0, 64 * 1024, 128, 0) },
 
+	/* ISSI */
+	{ "is25lq128", INFO(0x9d6018,  0,  64 * 1024, 256, 0) },
+
 	/* Macronix */
 	{ "mx25l2005a",  INFO(0xc22012, 0, 64 * 1024,   4, SECT_4K) },
 	{ "mx25l4005a",  INFO(0xc22013, 0, 64 * 1024,   8, SECT_4K) },
@@ -650,6 +653,7 @@ static const struct spi_device_id spi_nor_ids[] = {
 	{ "w25q80", INFO(0xef5014, 0, 64 * 1024,  16, SECT_4K) },
 	{ "w25q80bl", INFO(0xef4014, 0, 64 * 1024,  16, SECT_4K) },
 	{ "w25q128", INFO(0xef4018, 0, 64 * 1024, 256, SECT_4K) },
+	{ "w25q128", INFO(0xef7018, 0, 64 * 1024, 256, SECT_4K) },
 	{ "w25q256", INFO(0xef4019, 0, 64 * 1024, 512, SECT_4K) },
 
 	/* Catalyst / On Semiconductor -- non-JEDEC */
-- 
2.16.1



From s.hauer at pengutronix.de  Thu Mar 22 00:54:37 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Thu, 22 Mar 2018 08:54:37 +0100
Subject: [PATCH 1/2] mtd: nand: Add Winbond manufacturer ID
Message-ID: <20180322075438.10581-1-s.hauer@pengutronix.de>

From: Stefan Riedmueller <s.riedmueller at phytec.de>

Add Winbond 0xef manufacturer ID for NAND flashes to support Winbond as
an additional manufacturer.

Signed-off-by: Stefan Riedmueller <s.riedmueller at phytec.de>
Signed-off-by: Christian Hemp <c.hemp at phytec.de>
---
 drivers/mtd/nand/nand_ids.c | 1 +
 include/linux/mtd/nand.h    | 1 +
 2 files changed, 2 insertions(+)

diff --git a/drivers/mtd/nand/nand_ids.c b/drivers/mtd/nand/nand_ids.c
index dc0f8c6aa3..863e8d49ab 100644
--- a/drivers/mtd/nand/nand_ids.c
+++ b/drivers/mtd/nand/nand_ids.c
@@ -175,6 +175,7 @@ struct nand_manufacturers nand_manuf_ids[] = {
 	{NAND_MFR_AMD, "AMD/Spansion"},
 	{NAND_MFR_MACRONIX, "Macronix"},
 	{NAND_MFR_EON, "Eon"},
+	{NAND_MFR_WINBOND, "Winbond"},
 	{0x0, "Unknown"}
 };
 
diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
index 88a8fe9756..ec2237f7c9 100644
--- a/include/linux/mtd/nand.h
+++ b/include/linux/mtd/nand.h
@@ -560,6 +560,7 @@ struct nand_chip {
 #define NAND_MFR_AMD		0x01
 #define NAND_MFR_MACRONIX	0xc2
 #define NAND_MFR_EON		0x92
+#define NAND_MFR_WINBOND	0xef
 
 /* The maximum expected count of bytes in the NAND ID sequence */
 #define NAND_MAX_ID_LEN 8
-- 
2.16.1



From m.grzeschik at pengutronix.de  Fri Mar 23 01:43:49 2018
From: m.grzeschik at pengutronix.de (Michael Grzeschik)
Date: Fri, 23 Mar 2018 09:43:49 +0100
Subject: [PATCH 1/4] i.MX53/TX53: cfg revxx30: don't disable usb clks,
 so imx-usb-loader works
In-Reply-To: <20180323084352.20931-1-m.grzeschik@pengutronix.de>
References: <20180323084352.20931-1-m.grzeschik@pengutronix.de>
Message-ID: <20180323084352.20931-2-m.grzeschik@pengutronix.de>

In the current configuration the usb related clocks get disabled
immediately which breaks the imx-usb-loader boot. We fix that by leaving
them enabled.

Signed-off-by: Michael Grzeschik <m.grzeschik at pengutronix.de>
---
 arch/arm/boards/karo-tx53/flash-header-tx53-revxx30.imxcfg | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boards/karo-tx53/flash-header-tx53-revxx30.imxcfg b/arch/arm/boards/karo-tx53/flash-header-tx53-revxx30.imxcfg
index aec88ad59b..df0c2d7f10 100644
--- a/arch/arm/boards/karo-tx53/flash-header-tx53-revxx30.imxcfg
+++ b/arch/arm/boards/karo-tx53/flash-header-tx53-revxx30.imxcfg
@@ -3,9 +3,9 @@ soc imx53
 dcdofs 0x400
 wm 32 0x53fd4068 0xffcc0fff
 wm 32 0x53fd406c 0x000fffc3
-wm 32 0x53fd4070 0x033c0000
+wm 32 0x53fd4070 0x0f3c0000
 wm 32 0x53fd4074 0x00000000
-wm 32 0x53fd4078 0x00000000
+wm 32 0x53fd4078 0x00000c00
 wm 32 0x53fd407c 0x00fff033
 wm 32 0x53fd4080 0x0f00030f
 wm 32 0x53fd4084 0xfff00000
-- 
2.16.1



From m.grzeschik at pengutronix.de  Fri Mar 23 01:43:48 2018
From: m.grzeschik at pengutronix.de (Michael Grzeschik)
Date: Fri, 23 Mar 2018 09:43:48 +0100
Subject: [PATCH 0/4] i.MX53/TX53: rework to dts, fix and add samsung variant
Message-ID: <20180323084352.20931-1-m.grzeschik@pengutronix.de>

This series fixes the imx-usb-loader based boot of the revxx30.
It also reworks the whole platform to dts and adds the new
samsung based xx30 platform.

Juergen reworked the interpreter logic description on the way.
Don't know if we should send this seperatly. For now it is
included in this series, as the new samsung based platform
was not tested without.

Juergen Borleis (1):
  i.MX/DCD compiler and interpreter: logic is different

Michael Grzeschik (3):
  i.MX53/TX53: cfg revxx30: don't disable usb clks, so imx-usb-loader
    works
  i.MX53/TX53: rework to dts based boot
  i.MX53/TX53: add new samsung based xx30 variant

 Documentation/boards/imx.rst                       |  57 ++++++
 arch/arm/Makefile                                  |   2 -
 .../element14-warp7/flash-header-mx7-warp.imxcfg   |   4 +-
 .../flash-header-mx7-sabresd.imxcfg                |   4 +-
 .../flash-header-vf610-twr.imxcfg                  |  10 +-
 arch/arm/boards/karo-tx53/board.c                  | 222 +++------------------
 .../flash-header-tx53-revxx30-samsung.imxcfg       | 177 ++++++++++++++++
 .../karo-tx53/flash-header-tx53-revxx30.imxcfg     |  14 +-
 arch/arm/boards/karo-tx53/lowlevel.c               |  61 +++++-
 arch/arm/boards/karo-tx6x/1600mhz_4x128mx16.imxcfg |  24 +--
 .../karo-tx6x/flash-header-tx6dl-512m.imxcfg       |  14 +-
 .../boards/karo-tx6x/flash-header-tx6q-1g.imxcfg   |  18 +-
 .../boards/karo-tx6x/flash-header-tx6qp-2g.imxcfg  |  18 +-
 .../kindle-mx50/flash-header-kindle-lpddr1.imxcfg  |   6 +-
 .../kindle-mx50/flash-header-kindle-lpddr2.imxcfg  |   6 +-
 .../flash-header-phytec-phycore-imx7.imxcfg        |   4 +-
 .../flash-header-zii-vf610-dev.imxcfg              |  22 +-
 arch/arm/configs/imx_v7_defconfig                  |   1 +
 arch/arm/dts/Makefile                              |   1 +
 arch/arm/dts/imx53-tx53-1011.dts                   |  13 ++
 arch/arm/dts/imx53-tx53-xx30.dts                   |  13 ++
 arch/arm/mach-imx/Kconfig                          |  25 +--
 images/Makefile.imx                                |  15 ++
 scripts/imx/README                                 |  30 +--
 scripts/imx/imx-usb-loader.c                       |  24 +--
 scripts/imx/imx.c                                  |  16 +-
 scripts/imx/imx.h                                  |   8 +-
 27 files changed, 463 insertions(+), 346 deletions(-)
 create mode 100644 arch/arm/boards/karo-tx53/flash-header-tx53-revxx30-samsung.imxcfg
 create mode 100644 arch/arm/dts/imx53-tx53-1011.dts
 create mode 100644 arch/arm/dts/imx53-tx53-xx30.dts

-- 
2.16.1



From m.grzeschik at pengutronix.de  Fri Mar 23 01:43:52 2018
From: m.grzeschik at pengutronix.de (Michael Grzeschik)
Date: Fri, 23 Mar 2018 09:43:52 +0100
Subject: [PATCH 4/4] i.MX53/TX53: add new samsung based xx30 variant
In-Reply-To: <20180323084352.20931-1-m.grzeschik@pengutronix.de>
References: <20180323084352.20931-1-m.grzeschik@pengutronix.de>
Message-ID: <20180323084352.20931-5-m.grzeschik@pengutronix.de>

Karo is deploying there latest tx53 modules with samsung instead of
nanya ram. Unfortunatly the still keep the old revision for that
modules. We add this modules as an extra xx30 samsung variant.

Signed-off-by: Michael Grzeschik <m.grzeschik at pengutronix.de>
---
 .../flash-header-tx53-revxx30-samsung.imxcfg       | 177 +++++++++++++++++++++
 arch/arm/boards/karo-tx53/lowlevel.c               |   5 +
 images/Makefile.imx                                |   5 +
 3 files changed, 187 insertions(+)
 create mode 100644 arch/arm/boards/karo-tx53/flash-header-tx53-revxx30-samsung.imxcfg

diff --git a/arch/arm/boards/karo-tx53/flash-header-tx53-revxx30-samsung.imxcfg b/arch/arm/boards/karo-tx53/flash-header-tx53-revxx30-samsung.imxcfg
new file mode 100644
index 0000000000..6962abd5e6
--- /dev/null
+++ b/arch/arm/boards/karo-tx53/flash-header-tx53-revxx30-samsung.imxcfg
@@ -0,0 +1,177 @@
+loadaddr 0x71000000
+soc imx53
+dcdofs 0x400
+
+wm 32 0x53fa8004 0x00194005 /* set LDO to 1.3V */
+
+/* "AXI/DDR FREQ" fuse seems programmed to 1, so the SDRAM runs at 333 MHz */
+/* "BT_Freq" fuse seems unprogrammed and 0, so the CPU core runs at 800 MHz */
+
+/* re-program the PLL2 for the SDRAM clock prior signal calibration */
+
+wm 32 0x63F84000 0x00001232 /* MX5_PLL_DP_CTL */
+wm 32 0x63F84004 0x00000002 /* MX5_PLL_DP_CONFIG */
+wm 32 0x63F84008 0x00000081 /* MX5_PLL_DP_OP */
+wm 32 0x63F8401c 0x00000081 /* MX5_PLL_DP_HFS_OP */
+wm 32 0x63F8400c 0x00000002 /* MX5_PLL_DP_MFD */
+wm 32 0x63F84020 0x00000002 /* MX5_PLL_DP_HFS_MFD */
+wm 32 0x63F84010 0x00000001 /* MX5_PLL_DP_MFN */
+wm 32 0x63F84024 0x00000001 /* MX5_PLL_DP_HFS_MFN */
+wm 32 0x63F84000 0x00001232 /* MX5_PLL_DP_CTL */
+/* wait until PLL has locked again */
+check 32 until_all_bits_set 0x63F84000 0x00000001
+
+wm 32 0x53fa8340 0x00000011 /* GPIO_17 => RESET_OUT */
+wm 32 0x63fd800c 0x00000000 /* M4IF: MUX NFC signals on WEIM TODO */
+/* Setup clock tree */
+wm 32 0x53fd4014 0x00888944 /* CBCDR for SDRAM clock > 333 AXI_A: /1, AXI_B: /2 */
+wm 32 0x53fd4018 0x00016154 /* CBCMR SDRAM Controller uses AXI_A */
+/* peripherals */
+wm 32 0x53fd401c 0xa6a2a020 /* CSCMR1 */
+wm 32 0x53fd4020 0xb6b12f0a /* CSCMR2 */
+wm 32 0x53fd4024 0x00080b18 /* CSCDR1 */
+
+wm 32 0x53fa8724 0x00000000 /* DDR_TYPE: DDR3 */
+wm 32 0x53fa86f4 0x00000000 /* DDRMODE_CTL */
+wm 32 0x53fa8714 0x00000000 /* GRP_DDRMODE */
+wm 32 0x53fa86fc 0x00000080 /* GRP_DDRPKE */
+wm 32 0x53fa8710 0x00000000 /* GRP_DDRHYS */
+wm 32 0x53fa8708 0x00000040 /* GRP_DDRPK */
+
+wm 32 0x53fa8584 0x00300000 /* DQM0 */
+wm 32 0x53fa8594 0x00300000 /* DQM1 */
+wm 32 0x53fa8560 0x00300000 /* DQM2 */
+wm 32 0x53fa8554 0x00300000 /* DQM3 */
+
+wm 32 0x53fa857c 0x00b00040 /* SDQS0 */
+wm 32 0x53fa8590 0x00b00040 /* SDQS1 */
+wm 32 0x53fa8568 0x00b00040 /* SDQS2 */
+wm 32 0x53fa8558 0x00b00040 /* SDQS3 */
+
+wm 32 0x53fa8580 0x00300040 /* SDODT0 */
+wm 32 0x53fa8578 0x00300000 /* SDCLK0 */
+
+wm 32 0x53fa8564 0x00300040 /* SDODT1 */
+wm 32 0x53fa8570 0x00300000 /* SDCLK1 */
+
+wm 32 0x53fa858c 0x000000c0 /* SDCKE0 */
+wm 32 0x53fa855c 0x000000c0 /* SDCKE1 */
+
+wm 32 0x53fa8574 0x00300000 /* DRAM_CAS */
+wm 32 0x53fa8588 0x00300000 /* DRAM_RAS */
+
+wm 32 0x53fa86f0 0x00300000 /* GRP_ADDDS */
+wm 32 0x53fa8720 0x00300000 /* GRP_CTLDS */
+wm 32 0x53fa8718 0x00300000 /* GRP_B0DS */
+wm 32 0x53fa871c 0x00300000 /* GRP_B1DS */
+wm 32 0x53fa8728 0x00300000 /* GRP_B2DS */
+wm 32 0x53fa872c 0x00300000 /* GRP_B3DS */
+
+/* calibration defaults */
+wm 32 0x63fd904c 0x001f001f
+wm 32 0x63fd9050 0x001f001f
+wm 32 0x63fd907c 0x011e011e
+wm 32 0x63fd9080 0x011f0120
+wm 32 0x63fd9088 0x3a393d3b
+wm 32 0x63fd9090 0x3f3f3f3f
+
+wm 32 0x63fd9018 0x00000740
+wm 32 0x63fd9000 0x83190000
+wm 32 0x63fd900c 0x3f435333
+wm 32 0x63fd9010 0x926e8a63
+wm 32 0x63fd9014 0x01ff00db
+
+wm 32 0x63fd902c 0x000026d2
+wm 32 0x63fd9030 0x00430f24
+wm 32 0x63fd9008 0x1b333030
+wm 32 0x63fd9004 0x0002006d
+
+/* use the SDRAM controller for specific accesses into the SDRAM */
+wm 32 0x63fd901c 0x00008000 /* CON_REQ -> aquire AXI bus */
+check 32 until_all_bits_set 0x63fd901c 0x00004000 /* wait for acknowledge */
+
+/* Setup SDRAM's MR0..3 at CS0 */
+wm 32 0x63fd901c 0x004080b2 /* MRS: MR2 */
+wm 32 0x63fd901c 0x000080b3 /* MRS: MR3 */
+wm 32 0x63fd901c 0x000480b1 /* MRS: MR1 */
+wm 32 0x63fd901c 0x052080b0 /* MRS: MR0 */
+
+/* no memory at CS1 */
+
+wm 32 0x63fd9020 0x0000c000 /* disable refresh during calibration */
+wm 32 0x63fd9058 0x00022222
+
+wm 32 0x63fd90d0 0x00000003 /* select default compare pattern for calibration */
+
+/* ZQ calibration */
+wm 32 0x63fd901c 0x04008010 /* precharge all */
+wm 32 0x63fd901c 0x00008040 /* MRS: ZQ calibration */
+wm 32 0x63fd9040 0x0539002b /* Force ZQ calibration */
+check 32 until_all_bits_clear 0x63fd9040 0x00010000 /* wait until ZQ calibration is done */
+
+/* DQS calibration */
+wm 32 0x63fd901c 0x04008010 /* precharge all */
+wm 32 0x63fd901c 0x000480b3 /* MRS: select MPR */
+wm 32 0x63fd907c 0x90000000 /* reset RD fifo and start DQS calib. */
+
+check 32 until_all_bits_clear 0x63fd907c 0x90000000 /* wait until DQS calibration is done */
+wm 32 0x63fd901c 0x000080b3 /* MRS: select normal data path */
+
+/* WR DL calibration */
+wm 32 0x63fd901c 0x00008000
+wm 32 0x63fd901c 0x04008010 /* precharge all */
+wm 32 0x63fd901c 0x000480b3 /* MRS: select MPR */
+wm 32 0x63fd90a4 0x00000010 /* start WR DL calibration */
+
+check 32 until_all_bits_clear 0x63fd90a4 0x00000010 /* wait until WR DL calibration is done */
+wm 32 0x63fd901c 0x000080b3 /* MRS: select normal data path */
+
+/* RD DL calibration */
+wm 32 0x63fd901c 0x04008010 /* precharge all */
+wm 32 0x63fd901c 0x000480b3 /* MRS: select MPR */
+wm 32 0x63fd90a0 0x00000010 /* start WR DL calibration */
+
+check 32 until_all_bits_clear 0x63fd90a0 0x00000010 /* wait until RD DL calibration is done */
+wm 32 0x63fd901c 0x000080b3 /* MRS: select normal data path */
+
+wm 32 0x63fd9020 0x00001800 /* refresh interval: 4 cycles every 64kHz period */
+wm 32 0x63fd9004 0x0002556d
+
+/* DDR calibration done */
+wm 32 0x63fd901c 0x00000000
+
+/* setup NFC pads */
+
+/* MUX_SEL */
+wm 32 0x53fa819c 0x00000000 /* EIM_DA0 */
+wm 32 0x53fa81a0 0x00000000 /* EIM_DA1 */
+wm 32 0x53fa81a4 0x00000000 /* EIM_DA2 */
+wm 32 0x53fa81a8 0x00000000 /* EIM_DA3 */
+wm 32 0x53fa81ac 0x00000000 /* EIM_DA4 */
+wm 32 0x53fa81b0 0x00000000 /* EIM_DA5 */
+wm 32 0x53fa81b4 0x00000000 /* EIM_DA6 */
+wm 32 0x53fa81b8 0x00000000 /* EIM_DA7 */
+wm 32 0x53fa81dc 0x00000000 /* WE_B */
+wm 32 0x53fa81e0 0x00000000 /* RE_B */
+wm 32 0x53fa8228 0x00000000 /* CLE */
+wm 32 0x53fa822c 0x00000000 /* ALE */
+wm 32 0x53fa8230 0x00000000 /* WP_B */
+wm 32 0x53fa8234 0x00000000 /* RB0 */
+wm 32 0x53fa8238 0x00000000 /* CS0 */
+
+/* PAD_CTL */
+wm 32 0x53fa84ec 0x000000e4 /* EIM_DA0 */
+wm 32 0x53fa84f0 0x000000e4 /* EIM_DA1 */
+wm 32 0x53fa84f4 0x000000e4 /* EIM_DA2 */
+wm 32 0x53fa84f8 0x000000e4 /* EIM_DA3 */
+wm 32 0x53fa84fc 0x000000e4 /* EIM_DA4 */
+wm 32 0x53fa8500 0x000000e4 /* EIM_DA5 */
+wm 32 0x53fa8504 0x000000e4 /* EIM_DA6 */
+wm 32 0x53fa8508 0x000000e4 /* EIM_DA7 */
+wm 32 0x53fa852c 0x00000004 /* NANDF_WE_B */
+wm 32 0x53fa8530 0x00000004 /* NANDF_RE_B */
+wm 32 0x53fa85a0 0x00000004 /* NANDF_CLE_B */
+wm 32 0x53fa85a4 0x00000004 /* NANDF_ALE_B */
+wm 32 0x53fa85a8 0x000000e4 /* NANDF_WE_B */
+wm 32 0x53fa85ac 0x000000e4 /* NANDF_RB0 */
+wm 32 0x53fa85b0 0x00000004 /* NANDF_CS0 */
diff --git a/arch/arm/boards/karo-tx53/lowlevel.c b/arch/arm/boards/karo-tx53/lowlevel.c
index 15dba7df22..cb324b2007 100644
--- a/arch/arm/boards/karo-tx53/lowlevel.c
+++ b/arch/arm/boards/karo-tx53/lowlevel.c
@@ -52,6 +52,11 @@ static void __imx53_tx53_init(int is_xx30)
 	imx53_barebox_entry(fdt);
 }
 
+ENTRY_FUNCTION(start_imx53_tx53_xx30_samsung, r0, r1, r2)
+{
+	__imx53_tx53_init(1);
+}
+
 ENTRY_FUNCTION(start_imx53_tx53_xx30, r0, r1, r2)
 {
 	__imx53_tx53_init(1);
diff --git a/images/Makefile.imx b/images/Makefile.imx
index ed2774263d..ac46d51c59 100644
--- a/images/Makefile.imx
+++ b/images/Makefile.imx
@@ -139,6 +139,11 @@ CFG_start_imx53_mba53_1gib.pblx.imximg = $(board)/tqma53/flash-header-tq-tqma53-
 FILE_barebox-tq-mba53-1gib.img = start_imx53_mba53_1gib.pblx.imximg
 image-$(CONFIG_MACH_TQMA53) += barebox-tq-mba53-1gib.img
 
+pblx-$(CONFIG_MACH_TX53) += start_imx53_imx53_tx53_xx30_samsung
+CFG_start_imx53_tx53_xx30_samsung.pblx.imximg = $(board)/karo-tx53/flash-header-tx53-revxx30-samsung.imxcfg
+FILE_barebox-tx53-xx30-samsung.img = start_imx53_tx53_xx30_samsung.pblx.imximg
+image-$(CONFIG_MACH_TX53) += barebox-tx53-xx30-samsung.img
+
 pblx-$(CONFIG_MACH_TX53) += start_imx53_imx53_tx53_xx30
 CFG_start_imx53_tx53_xx30.pblx.imximg = $(board)/karo-tx53/flash-header-tx53-revxx30.imxcfg
 FILE_barebox-tx53-xx30.img = start_imx53_tx53_xx30.pblx.imximg
-- 
2.16.1



From m.grzeschik at pengutronix.de  Fri Mar 23 01:43:50 2018
From: m.grzeschik at pengutronix.de (Michael Grzeschik)
Date: Fri, 23 Mar 2018 09:43:50 +0100
Subject: [PATCH 2/4] i.MX53/TX53: rework to dts based boot
In-Reply-To: <20180323084352.20931-1-m.grzeschik@pengutronix.de>
References: <20180323084352.20931-1-m.grzeschik@pengutronix.de>
Message-ID: <20180323084352.20931-3-m.grzeschik@pengutronix.de>

Since nobody likes to use platformcode based machines any more, we also
switch this one to use dts based booting.

Signed-off-by: Michael Grzeschik <m.grzeschik at pengutronix.de>
---
 arch/arm/Makefile                    |   2 -
 arch/arm/boards/karo-tx53/board.c    | 222 +++++------------------------------
 arch/arm/boards/karo-tx53/lowlevel.c |  56 +++++++--
 arch/arm/configs/imx_v7_defconfig    |   1 +
 arch/arm/dts/Makefile                |   1 +
 arch/arm/dts/imx53-tx53-1011.dts     |  13 ++
 arch/arm/dts/imx53-tx53-xx30.dts     |  13 ++
 arch/arm/mach-imx/Kconfig            |  25 +---
 images/Makefile.imx                  |  10 ++
 9 files changed, 119 insertions(+), 224 deletions(-)
 create mode 100644 arch/arm/dts/imx53-tx53-1011.dts
 create mode 100644 arch/arm/dts/imx53-tx53-xx30.dts

diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 620a3ccb0b..070a9903f2 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -254,8 +254,6 @@ imxcfg-$(CONFIG_MACH_EUKREA_CPUIMX25) += $(boarddir)/eukrea_cpuimx25/flash-heade
 imxcfg-$(CONFIG_MACH_EUKREA_CPUIMX35) += $(boarddir)/eukrea_cpuimx35/flash-header.imxcfg
 imxcfg-$(CONFIG_MACH_PCM043) += $(boarddir)/phytec-phycore-imx35/flash-header.imxcfg
 imxcfg-$(CONFIG_MACH_KINDLE3) += $(boarddir)/kindle3/flash-header.imxcfg
-imxcfg-$(CONFIG_TX53_REV_1011) += $(boarddir)/karo-tx53/flash-header-tx53-rev1011.imxcfg
-imxcfg-$(CONFIG_TX53_REV_XX30) += $(boarddir)/karo-tx53/flash-header-tx53-revxx30.imxcfg
 ifneq ($(imxcfg-y),)
 CFG_barebox.imximg := $(imxcfg-y)
 KBUILD_IMAGE  := barebox.imximg
diff --git a/arch/arm/boards/karo-tx53/board.c b/arch/arm/boards/karo-tx53/board.c
index 51b534d01f..9f1485ad0b 100644
--- a/arch/arm/boards/karo-tx53/board.c
+++ b/arch/arm/boards/karo-tx53/board.c
@@ -41,223 +41,55 @@
 #include <io.h>
 #include <asm/mmu.h>
 
-static struct fec_platform_data fec_info = {
-	.xcv_type = PHY_INTERFACE_MODE_RMII,
-};
-
-static iomux_v3_cfg_t tx53_pads[] = {
-	/* UART1 */
-	MX53_PAD_PATA_DIOW__UART1_TXD_MUX,
-	MX53_PAD_PATA_DMACK__UART1_RXD_MUX,
-
-	MX53_PAD_PATA_DMARQ__UART2_TXD_MUX,
-	MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX,
-
-	MX53_PAD_PATA_CS_0__UART3_TXD_MUX,
-	MX53_PAD_PATA_CS_1__UART3_RXD_MUX,
-
-	/* setup FEC PHY pins for GPIO function */
-	MX53_PAD_FEC_REF_CLK__GPIO1_23,
-	MX53_PAD_FEC_MDC__GPIO1_31,
-	MX53_PAD_FEC_MDIO__GPIO1_22,
-	MX53_PAD_FEC_RXD0__GPIO1_27,
-	MX53_PAD_FEC_RXD1__GPIO1_26,
-	MX53_PAD_FEC_RX_ER__GPIO1_24,
-	MX53_PAD_FEC_TX_EN__GPIO1_28,
-	MX53_PAD_FEC_TXD0__GPIO1_30,
-	MX53_PAD_FEC_TXD1__GPIO1_29,
-	MX53_PAD_FEC_CRS_DV__GPIO1_25,
-
-	/* FEC PHY reset */
-	MX53_PAD_PATA_DA_0__GPIO7_6,
-	/* FEC PHY power */
-	MX53_PAD_EIM_D20__GPIO3_20,
-
-	/* SD1 */
-	MX53_PAD_SD1_CMD__ESDHC1_CMD,
-	MX53_PAD_SD1_CLK__ESDHC1_CLK,
-	MX53_PAD_SD1_DATA0__ESDHC1_DAT0,
-	MX53_PAD_SD1_DATA1__ESDHC1_DAT1,
-	MX53_PAD_SD1_DATA2__ESDHC1_DAT2,
-	MX53_PAD_SD1_DATA3__ESDHC1_DAT3,
-
-	/* SD1_CD */
-	MX53_PAD_EIM_D24__GPIO3_24,
-
-	MX53_PAD_GPIO_3__I2C3_SCL,
-	MX53_PAD_GPIO_6__I2C3_SDA,
-
-	MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12,
-	MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13,
-	MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14,
-	MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15,
-	MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16,
-	MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17,
-	MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18,
-	MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19,
-	MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC,
-	MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC,
-	MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK,
-};
-
-#define TX53_SD1_CD			IMX_GPIO_NR(3, 24)
-
-static struct esdhc_platform_data tx53_sd1_data = {
-	.cd_gpio = TX53_SD1_CD,
-	.cd_type = ESDHC_CD_GPIO,
-	.wp_type = ESDHC_WP_NONE,
-	.caps    = MMC_CAP_4_BIT_DATA,
-};
-
-struct imx_nand_platform_data nand_info = {
-	.width		= 1,
-	.hw_ecc		= 1,
-	.flash_bbt	= 1,
-};
-
-#define FEC_POWER_GPIO		IMX_GPIO_NR(3, 20)
-#define FEC_RESET_GPIO		IMX_GPIO_NR(7, 6)
-
-static struct tx53_fec_gpio_setup {
-	iomux_v3_cfg_t pad;
-	unsigned gpio:9,
-		dir:1,
-		level:1;
-} tx53_fec_gpios[] = {
-	{ MX53_PAD_PATA_DA_0__GPIO7_6, FEC_RESET_GPIO,	   1, 0, }, /* PHY reset */
-	{ MX53_PAD_EIM_D20__GPIO3_20, FEC_POWER_GPIO,	   1, 1, }, /* PHY power enable */
-	{ MX53_PAD_FEC_REF_CLK__GPIO1_23, IMX_GPIO_NR(1, 23), 0, }, /* ENET_CLK */
-	{ MX53_PAD_FEC_MDC__GPIO1_31, IMX_GPIO_NR(1, 31), 1, 0, }, /* MDC */
-	{ MX53_PAD_FEC_MDIO__GPIO1_22, IMX_GPIO_NR(1, 22), 1, 0, }, /* MDIO */
-	{ MX53_PAD_FEC_RXD0__GPIO1_27, IMX_GPIO_NR(1, 27), 1, 1, }, /* Mode0/RXD0 */
-	{ MX53_PAD_FEC_RXD1__GPIO1_26, IMX_GPIO_NR(1, 26), 1, 1, }, /* Mode1/RXD1 */
-	{ MX53_PAD_FEC_RX_ER__GPIO1_24, IMX_GPIO_NR(1, 24), 0, }, /* RX_ER */
-	{ MX53_PAD_FEC_TX_EN__GPIO1_28, IMX_GPIO_NR(1, 28), 1, 0, }, /* TX_EN */
-	{ MX53_PAD_FEC_TXD0__GPIO1_30, IMX_GPIO_NR(1, 30), 1, 0, }, /* TXD0 */
-	{ MX53_PAD_FEC_TXD1__GPIO1_29, IMX_GPIO_NR(1, 29), 1, 0, }, /* TXD1 */
-	{ MX53_PAD_FEC_CRS_DV__GPIO1_25, IMX_GPIO_NR(1, 25), 1, 1, }, /* Mode2/CRS_DV */
-};
-
-static iomux_v3_cfg_t tx53_fec_pads[] = {
-	MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
-	MX53_PAD_FEC_MDC__FEC_MDC,
-	MX53_PAD_FEC_MDIO__FEC_MDIO,
-	MX53_PAD_FEC_RXD0__FEC_RDATA_0,
-	MX53_PAD_FEC_RXD1__FEC_RDATA_1,
-	MX53_PAD_FEC_RX_ER__FEC_RX_ER,
-	MX53_PAD_FEC_TX_EN__FEC_TX_EN,
-	MX53_PAD_FEC_TXD0__FEC_TDATA_0,
-	MX53_PAD_FEC_TXD1__FEC_TDATA_1,
-	MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
-};
-
-static inline void tx53_fec_init(void)
-{
-	int i;
-
-	/* Configure LAN8700 pads as GPIO and set up
-	 * necessary strap options for PHY
-	 */
-	for (i = 0; i < ARRAY_SIZE(tx53_fec_gpios); i++) {
-		struct tx53_fec_gpio_setup *gs = &tx53_fec_gpios[i];
-
-		if (gs->dir)
-			gpio_direction_output(gs->gpio, gs->level);
-		else
-			gpio_direction_input(gs->gpio);
-
-		mxc_iomux_v3_setup_pad(gs->pad);
-	}
-
-	/*
-	 *Turn on phy power, leave in reset state
-	 */
-	gpio_set_value(FEC_POWER_GPIO, 1);
-
-	/*
-	 * Wait some time to let the phy activate the internal regulator
-	 */
-	mdelay(10);
-
-	/*
-	 * Deassert reset, phy latches the rest of bootstrap pins
-	 */
-	gpio_set_value(FEC_RESET_GPIO, 1);
-
-	/* LAN7800 has an internal Power On Reset (POR) signal (OR'ed with
-	 * the external RESET signal) which is deactivated 21ms after
-	 * power on and latches the strap options.
-	 * Delay for 22ms to ensure, that the internal POR is inactive
-	 * before reconfiguring the strap pins.
-	 */
-	mdelay(22);
-
-	/*
-	 * The phy is ready, now configure imx51 pads for fec operation
-	 */
-	mxc_iomux_v3_setup_multiple_pads(tx53_fec_pads,
-			ARRAY_SIZE(tx53_fec_pads));
-}
-
 static int tx53_devices_init(void)
 {
-	imx53_iim_register_fec_ethaddr();
-	tx53_fec_init();
-	imx53_add_fec(&fec_info);
-	imx53_add_mmc0(&tx53_sd1_data);
-	imx53_add_nand(&nand_info);
-
-	armlinux_set_architecture(MACH_TYPE_TX53);
-
-	/* rev xx30 can boot from nand or USB */
-	imx53_bbu_internal_nand_register_handler("nand-xx30",
-		BBU_HANDLER_FLAG_DEFAULT, SZ_512K);
-
-	/* rev 1011 can boot from MMC/SD, other bootsource currently unknown */
-	imx53_bbu_internal_mmc_register_handler("mmc-1011", "/dev/disk0", 0);
+	const char *envdev;
+	uint32_t flag_nand = 0;
+	uint32_t flag_mmc = 0;
 
-	return 0;
-}
+	if (!of_machine_is_compatible("karo,tx53"))
+		return 0;
 
-device_initcall(tx53_devices_init);
-
-static int tx53_part_init(void)
-{
-	const char *envdev;
+	barebox_set_model("Ka-Ro TX53");
+	barebox_set_hostname("tx53");
 
 	switch (bootsource_get()) {
 	case BOOTSOURCE_MMC:
-		devfs_add_partition("disk0", 0x00000, SZ_512K, DEVFS_PARTITION_FIXED, "self0");
-		devfs_add_partition("disk0", SZ_512K, SZ_1M, DEVFS_PARTITION_FIXED, "env0");
+		devfs_add_partition("mmc0", 0x00000, SZ_512K,
+				DEVFS_PARTITION_FIXED, "self0");
+		devfs_add_partition("mmc0", SZ_512K, SZ_1M,
+				DEVFS_PARTITION_FIXED, "env0");
 		envdev = "MMC";
+		flag_mmc |= BBU_HANDLER_FLAG_DEFAULT;
 		break;
 	case BOOTSOURCE_NAND:
 	default:
-		devfs_add_partition("nand0", 0x00000, 0x80000, DEVFS_PARTITION_FIXED, "self_raw");
+		devfs_add_partition("nand0", 0x00000, 0x80000,
+				DEVFS_PARTITION_FIXED, "self_raw");
 		dev_add_bb_dev("self_raw", "self0");
-		devfs_add_partition("nand0", 0x80000, 0x100000, DEVFS_PARTITION_FIXED, "env_raw");
+		devfs_add_partition("nand0", 0x80000, 0x100000,
+				DEVFS_PARTITION_FIXED, "env_raw");
 		dev_add_bb_dev("env_raw", "env0");
 		envdev = "NAND";
+		flag_nand |= BBU_HANDLER_FLAG_DEFAULT;
 		break;
 	}
 
-	printf("Using environment in %s\n", envdev);
+	armlinux_set_architecture(MACH_TYPE_TX53);
 
-	return 0;
-}
-late_initcall(tx53_part_init);
+	/* rev xx30 can boot from nand or USB */
+	imx53_bbu_internal_nand_register_handler("nand-xx30",
+						flag_nand, SZ_512K);
 
-static int tx53_console_init(void)
-{
-	mxc_iomux_v3_setup_multiple_pads(tx53_pads, ARRAY_SIZE(tx53_pads));
+	/* rev 1011 can boot from MMC/SD, other bootsource currently unknown */
+	imx53_bbu_internal_mmc_register_handler("mmc-1011",
+						"/dev/mmc0", flag_mmc);
 
-	if (!IS_ENABLED(CONFIG_TX53_REV_XX30))
+	if (of_machine_is_compatible("karo,tx53-1011"))
 		imx53_init_lowlevel(1000);
 
-	barebox_set_model("Ka-Ro TX53");
-	barebox_set_hostname("tx53");
+	printf("Using environment in %s\n", envdev);
 
-	imx53_add_uart0();
 	return 0;
 }
-console_initcall(tx53_console_init);
+device_initcall(tx53_devices_init);
diff --git a/arch/arm/boards/karo-tx53/lowlevel.c b/arch/arm/boards/karo-tx53/lowlevel.c
index 9f584fa256..15dba7df22 100644
--- a/arch/arm/boards/karo-tx53/lowlevel.c
+++ b/arch/arm/boards/karo-tx53/lowlevel.c
@@ -1,23 +1,63 @@
 #include <common.h>
+#include <debug_ll.h>
 #include <asm/barebox-arm-head.h>
 #include <asm/barebox-arm.h>
 #include <mach/imx5.h>
 #include <mach/imx53-regs.h>
 #include <mach/esdctl.h>
 #include <mach/generic.h>
+#include <asm/cache.h>
 
-void __naked barebox_arm_reset_vector(void)
+extern char __dtb_imx53_tx53_xx30_start[];
+extern char __dtb_imx53_tx53_1011_start[];
+
+static inline void setup_uart(void)
 {
+	void __iomem *uart = IOMEM(MX53_UART1_BASE_ADDR);
+
+	writel(0x3, MX53_IOMUXC_BASE_ADDR + 0x270);
+	writel(0x3, MX53_IOMUXC_BASE_ADDR + 0x274);
+	writel(0x3, MX53_IOMUXC_BASE_ADDR + 0x878);
+
+	imx53_ungate_all_peripherals();
+	imx53_uart_setup(uart);
+	pbl_set_putc(imx_uart_putc, uart);
+
+	putc_ll('>');
+}
+
+static void __imx53_tx53_init(int is_xx30)
+{
+	void *fdt;
+	void *fdt_blob_fixed_offset = __dtb_imx53_tx53_1011_start;
+
+	arm_early_mmu_cache_invalidate();
 	imx5_cpu_lowlevel_init();
+	relocate_to_current_adr();
+	setup_c();
+	barrier();
+
 	arm_setup_stack(MX53_IRAM_BASE_ADDR + MX53_IRAM_SIZE - 8);
 
-	/*
-	 * For the TX53 rev 8030 the SDRAM setup is not stable without
-	 * the proper PLL setup. It will crash once we enable the MMU,
-	 * so do the PLL setup here.
-	 */
-	if (IS_ENABLED(CONFIG_TX53_REV_XX30))
+	if (is_xx30) {
 		imx53_init_lowlevel_early(800);
+		fdt_blob_fixed_offset = __dtb_imx53_tx53_xx30_start;
+	}
 
-	imx53_barebox_entry(NULL);
+	if (IS_ENABLED(CONFIG_DEBUG_LL))
+		setup_uart();
+
+	fdt = fdt_blob_fixed_offset - get_runtime_offset();
+
+	imx53_barebox_entry(fdt);
+}
+
+ENTRY_FUNCTION(start_imx53_tx53_xx30, r0, r1, r2)
+{
+	__imx53_tx53_init(1);
+}
+
+ENTRY_FUNCTION(start_imx53_tx53_1011, r0, r1, r2)
+{
+	__imx53_tx53_init(0);
 }
diff --git a/arch/arm/configs/imx_v7_defconfig b/arch/arm/configs/imx_v7_defconfig
index 08ec6eb862..426bc04651 100644
--- a/arch/arm/configs/imx_v7_defconfig
+++ b/arch/arm/configs/imx_v7_defconfig
@@ -10,6 +10,7 @@ CONFIG_MACH_GUF_VINCELL=y
 CONFIG_MACH_GUF_VINCELL_XLOAD=y
 CONFIG_MACH_TQMA53=y
 CONFIG_MACH_FREESCALE_MX53_VMX53=y
+CONFIG_MACH_TX53=y
 CONFIG_MACH_PHYTEC_SOM_IMX6=y
 CONFIG_MACH_KONTRON_SAMX6I=y
 CONFIG_MACH_DFI_FS700_M60=y
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index db703c1e0f..e60e0ea0c6 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -19,6 +19,7 @@ pbl-dtb-$(CONFIG_MACH_EMBEST_RIOTBOARD) += imx6s-riotboard.dtb.o
 pbl-dtb-$(CONFIG_MACH_EMBEDSKY_E9) += imx6q-embedsky-e9.dtb.o
 pbl-dtb-$(CONFIG_MACH_FREESCALE_MX51_PDK) += imx51-babbage.dtb.o
 pbl-dtb-$(CONFIG_MACH_FREESCALE_MX53_LOCO) += imx53-qsb.dtb.o imx53-qsrb.dtb.o
+pbl-dtb-$(CONFIG_MACH_TX53) += imx53-tx53-xx30.dtb.o imx53-tx53-1011.dtb.o
 pbl-dtb-$(CONFIG_MACH_CCMX53) += imx53-ccxmx53.dtb.o
 pbl-dtb-$(CONFIG_MACH_FREESCALE_MX53_VMX53) += imx53-voipac-bsb.dtb.o
 pbl-dtb-$(CONFIG_MACH_FREESCALE_MX7_SABRESD) += imx7d-sdb.dtb.o
diff --git a/arch/arm/dts/imx53-tx53-1011.dts b/arch/arm/dts/imx53-tx53-1011.dts
new file mode 100644
index 0000000000..e9b1b3a221
--- /dev/null
+++ b/arch/arm/dts/imx53-tx53-1011.dts
@@ -0,0 +1,13 @@
+/dts-v1/;
+#include <arm/imx53-tx53.dtsi>
+
+/ {
+	model = "Ka-Ro electronics TX53 module";
+	compatible = "karo,tx53-1011", "karo,tx53", "fsl,imx53";
+
+	chosen {
+		stdout-path = &uart1;
+	};
+
+	sgtl5000: dummy { };
+};
diff --git a/arch/arm/dts/imx53-tx53-xx30.dts b/arch/arm/dts/imx53-tx53-xx30.dts
new file mode 100644
index 0000000000..b9d1c65a2a
--- /dev/null
+++ b/arch/arm/dts/imx53-tx53-xx30.dts
@@ -0,0 +1,13 @@
+/dts-v1/;
+#include <arm/imx53-tx53.dtsi>
+
+/ {
+	model = "Ka-Ro electronics TX53 module";
+	compatible = "karo,tx53-xx30", "karo,tx53", "fsl,imx53";
+
+	chosen {
+		stdout-path = &uart1;
+	};
+
+	sgtl5000: dummy { };
+};
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index cf5338e5fa..9052a94ea0 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -289,6 +289,12 @@ config MACH_FREESCALE_MX53_VMX53
 	  Say Y here if you are using the Voipac Technologies X53-DMM-668
 	  module equipped with a Freescale i.MX53 Processor
 
+config MACH_TX53
+	bool "Ka-Ro TX53"
+	select ARCH_IMX53
+	help
+	  Say Y here if you are using the Ka-Ro tx53 board
+
 config MACH_PHYTEC_SOM_IMX6
         bool "Phytec phyCARD-i.MX6 and phyFLEX-i.MX6"
         select ARCH_IMX6
@@ -610,12 +616,6 @@ config MACH_FREESCALE_MX53_SMD
 	bool "Freescale i.MX53 SMD"
 	select ARCH_IMX53
 
-config MACH_TX53
-	bool "Ka-Ro TX53"
-	select ARCH_IMX53
-	help
-	  Say Y here if you are using the Ka-Ro tx53 board
-
 endchoice
 
 # ----------------------------------------------------------
@@ -689,19 +689,6 @@ endchoice
 
 endif
 
-if MACH_TX53
-
-choice
-	prompt "TX53 board revision"
-config TX53_REV_1011
-	bool "1011"
-config TX53_REV_XX30
-	bool "8030 / 1030"
-
-endchoice
-
-endif
-
 endmenu
 
 menu "i.MX specific settings"
diff --git a/images/Makefile.imx b/images/Makefile.imx
index 0428c48ade..ed2774263d 100644
--- a/images/Makefile.imx
+++ b/images/Makefile.imx
@@ -139,6 +139,16 @@ CFG_start_imx53_mba53_1gib.pblx.imximg = $(board)/tqma53/flash-header-tq-tqma53-
 FILE_barebox-tq-mba53-1gib.img = start_imx53_mba53_1gib.pblx.imximg
 image-$(CONFIG_MACH_TQMA53) += barebox-tq-mba53-1gib.img
 
+pblx-$(CONFIG_MACH_TX53) += start_imx53_imx53_tx53_xx30
+CFG_start_imx53_tx53_xx30.pblx.imximg = $(board)/karo-tx53/flash-header-tx53-revxx30.imxcfg
+FILE_barebox-tx53-xx30.img = start_imx53_tx53_xx30.pblx.imximg
+image-$(CONFIG_MACH_TX53) += barebox-tx53-xx30.img
+
+pblx-$(CONFIG_MACH_TX53) += start_imx53_imx53_tx53_1011
+CFG_start_imx53_tx53_1011.pblx.imximg = $(board)/karo-tx53/flash-header-tx53-rev1011.imxcfg
+FILE_barebox-tx53-1011.img = start_imx53_tx53_1011.pblx.imximg
+image-$(CONFIG_MACH_TX53) += barebox-tx53-1011.img
+
 # ----------------------- i.MX6 based boards ---------------------------
 pblx-$(CONFIG_MACH_REALQ7) += start_imx6_realq7
 CFG_start_imx6_realq7.pblx.imximg = $(board)/datamodul-edm-qmx6/flash-header.imxcfg
-- 
2.16.1



From m.grzeschik at pengutronix.de  Fri Mar 23 01:43:51 2018
From: m.grzeschik at pengutronix.de (Michael Grzeschik)
Date: Fri, 23 Mar 2018 09:43:51 +0100
Subject: [PATCH 3/4] i.MX/DCD compiler and interpreter: logic is different
In-Reply-To: <20180323084352.20931-1-m.grzeschik@pengutronix.de>
References: <20180323084352.20931-1-m.grzeschik@pengutronix.de>
Message-ID: <20180323084352.20931-4-m.grzeschik@pengutronix.de>

From: Juergen Borleis <jbe at pengutronix.de>

Reading the manual more carefully discovers a different logic for the
DCD 'check' command. They use the term "until". In order to get the
manual and the software in sync, this change switches to the term
"until" as well. Changing must happen at compiler and interpreter level
to make it work.

Signed-off-by: Juergen Borleis <jbe at pengutronix.de>
---
 Documentation/boards/imx.rst                       | 57 ++++++++++++++++++++++
 .../element14-warp7/flash-header-mx7-warp.imxcfg   |  4 +-
 .../flash-header-mx7-sabresd.imxcfg                |  4 +-
 .../flash-header-vf610-twr.imxcfg                  | 10 ++--
 .../karo-tx53/flash-header-tx53-revxx30.imxcfg     | 10 ++--
 arch/arm/boards/karo-tx6x/1600mhz_4x128mx16.imxcfg | 24 ++++-----
 .../karo-tx6x/flash-header-tx6dl-512m.imxcfg       | 14 +++---
 .../boards/karo-tx6x/flash-header-tx6q-1g.imxcfg   | 18 +++----
 .../boards/karo-tx6x/flash-header-tx6qp-2g.imxcfg  | 18 +++----
 .../kindle-mx50/flash-header-kindle-lpddr1.imxcfg  |  6 +--
 .../kindle-mx50/flash-header-kindle-lpddr2.imxcfg  |  6 +--
 .../flash-header-phytec-phycore-imx7.imxcfg        |  4 +-
 .../flash-header-zii-vf610-dev.imxcfg              | 22 ++++-----
 scripts/imx/README                                 | 30 ++----------
 scripts/imx/imx-usb-loader.c                       | 24 ++++-----
 scripts/imx/imx.c                                  | 16 +++---
 scripts/imx/imx.h                                  |  8 +--
 17 files changed, 155 insertions(+), 120 deletions(-)

diff --git a/Documentation/boards/imx.rst b/Documentation/boards/imx.rst
index 704aa027b6..9b1eb82d41 100644
--- a/Documentation/boards/imx.rst
+++ b/Documentation/boards/imx.rst
@@ -48,6 +48,63 @@ The images can also always be started second stage::
 
   bootm /mnt/tftp/barebox-freescale-imx51-babbage.img
 
+Information about the ``imx-image`` tool
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+The imx-image tool can be used to generate imximages from raw binaries.
+It requires an configuration file describing how to setup the SDRAM on
+a particular board. This mainly consists of a poke table. The recognized
+options in this file are:
+
+Header:
+
++----------------+--------------------------------------------------------------+
+| soc <soctype>  | soctype can be one of imx35, imx51, imx53, imx6              |
++----------------+--------------------------------------------------------------+
+| loadaddr <adr> |     The address the binary is uploaded to                    |
++----------------+--------------------------------------------------------------+
+| dcdofs <ofs>   | The offset of the image header in the image. This should be: |
+|                | * ``0x400``:  MMC/SD, NAND, serial ROM, PATA, SATA           |
+|                | * ``0x1000``: NOR Flash                                      |
+|                | * ``0x100``: OneNAND                                         |
++----------------+--------------------------------------------------------------+
+
+Memory manipulation:
+
++------------------------------------+-----------------------------------------+
+| wm 8 <addr> <value>                | write <value> into byte <addr>          |
++------------------------------------+-----------------------------------------+
+| wm 16 <addr> <value>               | write <value> into short <addr>         |
++------------------------------------+-----------------------------------------+
+| wm 32 <addr> <value>               | write <value> into word <addr>          |
++------------------------------------+-----------------------------------------+
+| set_bits <width> <addr> <value>    | set set bits in <value> in <addr>       |
++------------------------------------+-----------------------------------------+
+| clear_bits <width> <addr> <value>  | clear set bits in <value> in <addr>     |
++------------------------------------+-----------------------------------------+
+| nop                                | do nothing (just waste time)            |
++------------------------------------+-----------------------------------------+
+
+<width> can be of 8, 16 or 32.
+
+Checking conditions:
+
++------------------------------------+-----------------------------------------+
+| check <width> <cond> <addr> <mask> | Poll until condition becomes true.      |
+|                                    | with <cond> being one of:               |
+|                                    | * ``until_all_bits_clear``              |
+|                                    | * ``until_all_bits_set``                |
+|                                    | * ``until_any_bit_clear``               |
+|                                    | * ``until_any_bit_set``                 |
++------------------------------------+-----------------------------------------+
+
+Some notes about the mentioned *conditions*.
+
+ - ``until_all_bits_clear`` waits until ``(*addr & mask) == 0`` is true
+ - ``until_all_bits_set`` waits until ``(*addr & mask) == mask`` is true
+ - ``until_any_bit_clear`` waits until ``(*addr & mask) != mask`` is true
+ - ``until_any_bit_set`` waits until ``(*addr & mask) != 0`` is true.
+
 Internal Boot Mode Through Internal RAM(IRAM)
 ---------------------------------------------
 
diff --git a/arch/arm/boards/element14-warp7/flash-header-mx7-warp.imxcfg b/arch/arm/boards/element14-warp7/flash-header-mx7-warp.imxcfg
index d54b3ea851..7aa5dd8d45 100644
--- a/arch/arm/boards/element14-warp7/flash-header-mx7-warp.imxcfg
+++ b/arch/arm/boards/element14-warp7/flash-header-mx7-warp.imxcfg
@@ -72,7 +72,7 @@ wm 32 MX7_DDR_PHY_ZQ_CON0 0x0e4c7304
 wm 32 MX7_DDR_PHY_ZQ_CON0 0x0e4c7306
 wm 32 MX7_DDR_PHY_ZQ_CON0 0x0e4c7304
 
-check 32 while_any_bit_clear MX7_DDR_PHY_ZQ_CON1 0x1
+check 32 until_any_bit_set MX7_DDR_PHY_ZQ_CON1 0x1
 
 wm 32 MX7_DDR_PHY_ZQ_CON0 0x0e487304
 
@@ -80,4 +80,4 @@ wm 32 0x30384130 0x00000000
 wm 32 0x30340020 0x00000178
 wm 32 0x30384130 0x00000002
 
-check 32 while_any_bit_clear MX7_DDRC_STAT 0x1
+check 32 until_any_bit_set MX7_DDRC_STAT 0x1
diff --git a/arch/arm/boards/freescale-mx7-sabresd/flash-header-mx7-sabresd.imxcfg b/arch/arm/boards/freescale-mx7-sabresd/flash-header-mx7-sabresd.imxcfg
index fd4861153f..83ed2dc065 100644
--- a/arch/arm/boards/freescale-mx7-sabresd/flash-header-mx7-sabresd.imxcfg
+++ b/arch/arm/boards/freescale-mx7-sabresd/flash-header-mx7-sabresd.imxcfg
@@ -68,7 +68,7 @@ wm 32 MX7_DDR_PHY_ZQ_CON0 0x0e407304
 wm 32 MX7_DDR_PHY_ZQ_CON0 0x0e447304
 wm 32 MX7_DDR_PHY_ZQ_CON0 0x0e447306
 
-check 32 while_any_bit_clear MX7_DDR_PHY_ZQ_CON1 0x1
+check 32 until_any_bit_set MX7_DDR_PHY_ZQ_CON1 0x1
 
 wm 32 MX7_DDR_PHY_ZQ_CON0 0x0e447304
 wm 32 MX7_DDR_PHY_ZQ_CON0 0x0e407304
@@ -79,4 +79,4 @@ wm 32 0x30384130 0x00000002
 
 wm 32 MX7_DDR_PHY_LP_CON0 0x0000000f
 
-check 32 while_any_bit_clear MX7_DDRC_STAT 0x1
+check 32 until_any_bit_set MX7_DDRC_STAT 0x1
diff --git a/arch/arm/boards/freescale-vf610-twr/flash-header-vf610-twr.imxcfg b/arch/arm/boards/freescale-vf610-twr/flash-header-vf610-twr.imxcfg
index 01ffc6998a..8dd62be210 100644
--- a/arch/arm/boards/freescale-vf610-twr/flash-header-vf610-twr.imxcfg
+++ b/arch/arm/boards/freescale-vf610-twr/flash-header-vf610-twr.imxcfg
@@ -65,7 +65,7 @@ CHECKPOINT(2)
 /*
  * Wait for PLLs to lock
  */
-check 32 while_any_bit_clear 0x40050030 0x80000000
+check 32 until_any_bit_set 0x40050030 0x80000000
 
 
 CHECKPOINT(3)
@@ -240,7 +240,7 @@ wm 32 0x400ae000 0x00000601
 
 CHECKPOINT(7)
 
-check 32 while_any_bit_clear 0x400ae140 0x100
+check 32 until_any_bit_set 0x400ae140 0x100
 
 CHECKPOINT(8)
 
@@ -268,11 +268,11 @@ CHECKPOINT(8)
  * against that pattern
  */
 wm 32 0x80000000 0xa5a5a5a5
-check 32 while_any_bit_clear 0x80000000 0xa5a5a5a5
+check 32 until_any_bit_set 0x80000000 0xa5a5a5a5
 
 wm 32 0x400ae000 0x00000600
 wm 32 0x400ae000 0x00000601
 
-check 32 while_any_bit_clear 0x400ae140 0x100
+check 32 until_any_bit_set 0x400ae140 0x100
 
-CHECKPOINT(9)
\ No newline at end of file
+CHECKPOINT(9)
diff --git a/arch/arm/boards/karo-tx53/flash-header-tx53-revxx30.imxcfg b/arch/arm/boards/karo-tx53/flash-header-tx53-revxx30.imxcfg
index df0c2d7f10..2b47d63bd4 100644
--- a/arch/arm/boards/karo-tx53/flash-header-tx53-revxx30.imxcfg
+++ b/arch/arm/boards/karo-tx53/flash-header-tx53-revxx30.imxcfg
@@ -68,29 +68,29 @@ wm 32 0x63fd90d0 0x00000003
 wm 32 0x63fd901c 0x04008010
 wm 32 0x63fd901c 0x00008040
 wm 32 0x63fd9040 0x0539002b
-check 32 while_all_bits_set 0x63fd9040 0x00010000
+check 32 until_all_bits_clear 0x63fd9040 0x00010000
 wm 32 0x63fd901c 0x00048033
 wm 32 0x63fd901c 0x00848231
 wm 32 0x63fd901c 0x00000000
 wm 32 0x63fd9048 0x00000001
-check 32 while_all_bits_set 0x63fd9048 0x00000001
+check 32 until_all_bits_clear 0x63fd9048 0x00000001
 wm 32 0x63fd901c 0x00048031
 wm 32 0x63fd901c 0x00008033
 wm 32 0x63fd901c 0x04008010
 wm 32 0x63fd901c 0x00048033
 wm 32 0x63fd907c 0x90000000
-check 32 while_all_bits_set 0x63fd907c 0x90000000
+check 32 until_all_bits_clear 0x63fd907c 0x90000000
 wm 32 0x63fd901c 0x00008033
 wm 32 0x63fd901c 0x00000000
 wm 32 0x63fd901c 0x04008010
 wm 32 0x63fd901c 0x00048033
 wm 32 0x63fd90a4 0x00000010
-check 32 while_all_bits_set 0x63fd90a4 0x00000010
+check 32 until_all_bits_clear 0x63fd90a4 0x00000010
 wm 32 0x63fd901c 0x00008033
 wm 32 0x63fd901c 0x04008010
 wm 32 0x63fd901c 0x00048033
 wm 32 0x63fd90a0 0x00000010
-check 32 while_all_bits_set 0x63fd90a0 0x00000010
+check 32 until_all_bits_clear 0x63fd90a0 0x00000010
 wm 32 0x63fd901c 0x00008033
 wm 32 0x63fd901c 0x00000000
 wm 32 0x53fa8004 0x00194005
diff --git a/arch/arm/boards/karo-tx6x/1600mhz_4x128mx16.imxcfg b/arch/arm/boards/karo-tx6x/1600mhz_4x128mx16.imxcfg
index b5c59e3c3c..7e244edfd3 100644
--- a/arch/arm/boards/karo-tx6x/1600mhz_4x128mx16.imxcfg
+++ b/arch/arm/boards/karo-tx6x/1600mhz_4x128mx16.imxcfg
@@ -1,12 +1,12 @@
 /* MDMISC	mirroring	interleaved (row/bank/col) */
 wm 32 MX6_MMDC_P0_MDMISC		0x00000742
-check 32 while_all_bits_clear MX6_MMDC_P0_MDMISC 0x00000002
+check 32 until_all_bits_set MX6_MMDC_P0_MDMISC 0x00000002
 
 wm 32 MX6_MMDC_P0_MDSCR			0x00008000
-check 32 while_any_bit_clear MX6_MMDC_P0_MDSCR 0x00004000
+check 32 until_any_bit_set MX6_MMDC_P0_MDSCR 0x00004000
 
 wm 32 MX6_MMDC_P0_MDCTL			0x831a0000
-check 32 while_any_bit_clear MX6_MMDC_P0_MDMISC 0x40000000
+check 32 until_any_bit_set MX6_MMDC_P0_MDMISC 0x40000000
 
 wm 32 MX6_MMDC_P0_MDCFG0		0x3f435333
 wm 32 MX6_MMDC_P0_MDCFG1		0x926e8a63
@@ -34,7 +34,7 @@ wm 32 MX6_MMDC_P0_MDSCR			0x04008010
 wm 32 MX6_MMDC_P0_MDSCR			0x04008040
 
 wm 32 MX6_MMDC_P0_MPZQHWCTRL		0xA1390001
-check 32 while_all_bits_clear MX6_MMDC_P0_MPZQHWCTRL 0x00010000
+check 32 until_all_bits_set MX6_MMDC_P0_MPZQHWCTRL 0x00010000
 wm 32 MX6_MMDC_P0_MPZQHWCTRL		0xA1380000
 
 wm 32 MX6_MMDC_P0_MPWLDECTRL0	0x001e001e
@@ -62,11 +62,11 @@ wm 32 MX6_MMDC_P1_MPWRDLCTL		0x40404040
 wm 32 MX6_MMDC_P0_MPMUR0		0x00000800
 
 wm 32 MX6_MMDC_P0_MPDGCTRL0		0x80000000
-check 32 while_all_bits_clear MX6_MMDC_P0_MPDGCTRL0 0x80000000
+check 32 until_all_bits_set MX6_MMDC_P0_MPDGCTRL0 0x80000000
 wm 32 MX6_MMDC_P0_MPDGCTRL0		0x80000000
-check 32 while_all_bits_clear MX6_MMDC_P0_MPDGCTRL0 0x80000000
+check 32 until_all_bits_set MX6_MMDC_P0_MPDGCTRL0 0x80000000
 wm 32 MX6_MMDC_P0_MPDGCTRL0		0x50800000
-check 32 while_all_bits_clear MX6_MMDC_P0_MPDGCTRL0 0x10001000
+check 32 until_all_bits_set MX6_MMDC_P0_MPDGCTRL0 0x10001000
 
 wm 32 MX6_IOM_DRAM_SDQS0		0x00000030
 wm 32 MX6_IOM_DRAM_SDQS1		0x00000030
@@ -81,16 +81,16 @@ wm 32 MX6_MMDC_P0_MDSCR			0x04008050
 wm 32 MX6_MMDC_P0_MPRDDLHWCTL		0x00000030
 wm 32 MX6_MMDC_P1_MPRDDLHWCTL		0x00000030
 
-check 32 while_all_bits_clear MX6_MMDC_P0_MPRDDLHWCTL 0x0000001f
-check 32 while_all_bits_clear MX6_MMDC_P1_MPRDDLHWCTL 0x0000001f
+check 32 until_all_bits_set MX6_MMDC_P0_MPRDDLHWCTL 0x0000001f
+check 32 until_all_bits_set MX6_MMDC_P1_MPRDDLHWCTL 0x0000001f
 
 wm 32 MX6_MMDC_P0_MDSCR			0x04008050
 wm 32 MX6_MMDC_P0_MPWRDLHWCTL		0x00000030
-check 32 while_all_bits_clear MX6_MMDC_P0_MPWRDLHWCTL 0x0000001f
+check 32 until_all_bits_set MX6_MMDC_P0_MPWRDLHWCTL 0x0000001f
 
 wm 32 MX6_MMDC_P0_MDSCR			0x04008050
 wm 32 MX6_MMDC_P1_MPWRDLHWCTL		0x00000030
-check 32 while_all_bits_clear MX6_MMDC_P1_MPWRDLHWCTL 0x0000001f
+check 32 until_all_bits_set MX6_MMDC_P1_MPWRDLHWCTL 0x0000001f
 wm 32 MX6_MMDC_P0_MDSCR			0x00008033
 wm 32 MX6_MMDC_P0_MPZQHWCTRL		0xa138002b
 wm 32 MX6_MMDC_P0_MDREF			0x00001800
@@ -98,4 +98,4 @@ wm 32 MX6_MMDC_P0_MAPSR			0x00001006
 wm 32 MX6_MMDC_P0_MDPDC			0x0002556d
 wm 32 MX6_MMDC_P1_MDPDC			0x0002556d
 wm 32 MX6_MMDC_P0_MDSCR			0x00000000
-check 32 while_all_bits_clear MX6_MMDC_P0_MDSCR 0x00004000
+check 32 until_all_bits_set MX6_MMDC_P0_MDSCR 0x00004000
diff --git a/arch/arm/boards/karo-tx6x/flash-header-tx6dl-512m.imxcfg b/arch/arm/boards/karo-tx6x/flash-header-tx6dl-512m.imxcfg
index c58ef4e35a..3f6578e19c 100644
--- a/arch/arm/boards/karo-tx6x/flash-header-tx6dl-512m.imxcfg
+++ b/arch/arm/boards/karo-tx6x/flash-header-tx6dl-512m.imxcfg
@@ -92,11 +92,11 @@ wm 32 MX6_MMDC_P0_MPRDDQBY2DL 0x33333333
 wm 32 MX6_MMDC_P0_MPRDDQBY3DL 0x33333333
 wm 32 MX6_MMDC_P0_MPMUR0 0x00000800
 wm 32 MX6_MMDC_P0_MDMISC 0x00000742
-check 32 while_all_bits_clear MX6_MMDC_P0_MDMISC 0x00000002
+check 32 until_all_bits_set MX6_MMDC_P0_MDMISC 0x00000002
 wm 32 MX6_MMDC_P0_MDSCR 0x00008000
-check 32 while_any_bit_clear MX6_MMDC_P0_MDSCR 0x00004000
+check 32 until_any_bit_set MX6_MMDC_P0_MDSCR 0x00004000
 wm 32 MX6_MMDC_P0_MDCTL 0x83190000
-check 32 while_any_bit_clear MX6_MMDC_P0_MDMISC 0x40000000
+check 32 until_any_bit_set MX6_MMDC_P0_MDMISC 0x40000000
 wm 32 MX6_MMDC_P0_MDCFG0 0x3f435333
 wm 32 MX6_MMDC_P0_MDCFG1 0xb66e8a63
 wm 32 MX6_MMDC_P0_MDCFG2 0x01ff00db
@@ -117,7 +117,7 @@ wm 32 MX6_MMDC_P0_MAPSR 0x00000001
 wm 32 MX6_MMDC_P0_MDSCR 0x04008010
 wm 32 MX6_MMDC_P0_MDSCR 0x04008040
 wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xa1390001
-check 32 while_all_bits_clear MX6_MMDC_P0_MPZQHWCTRL 0x00010000
+check 32 until_all_bits_set MX6_MMDC_P0_MPZQHWCTRL 0x00010000
 wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xa1380000
 wm 32 MX6_MMDC_P0_MDSCR 0x00048033
 wm 32 MX6_IOM_DRAM_SDQS0 0x00000030
@@ -126,14 +126,14 @@ wm 32 MX6_IOM_DRAM_SDQS2 0x00000030
 wm 32 MX6_IOM_DRAM_SDQS3 0x00000030
 wm 32 MX6_MMDC_P0_MDSCR 0x04008050
 wm 32 MX6_MMDC_P0_MPRDDLHWCTL 0x00000030
-check 32 while_all_bits_clear MX6_MMDC_P0_MPRDDLHWCTL 0x0000001f
+check 32 until_all_bits_set MX6_MMDC_P0_MPRDDLHWCTL 0x0000001f
 wm 32 MX6_MMDC_P0_MDSCR 0x04008050
 wm 32 MX6_MMDC_P0_MPWRDLHWCTL 0x00000030
-check 32 while_all_bits_clear MX6_MMDC_P0_MPWRDLHWCTL 0x0000001f
+check 32 until_all_bits_set MX6_MMDC_P0_MPWRDLHWCTL 0x0000001f
 wm 32 MX6_MMDC_P0_MDSCR 0x00008033
 wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xa138002b
 wm 32 MX6_MMDC_P0_MDREF 0x00001800
 wm 32 MX6_MMDC_P0_MAPSR 0x00001000
 wm 32 MX6_MMDC_P0_MDPDC 0x0002556d
 wm 32 MX6_MMDC_P0_MDSCR 0x00000000
-check 32 while_all_bits_clear MX6_MMDC_P0_MDSCR 0x00004000
+check 32 until_all_bits_set MX6_MMDC_P0_MDSCR 0x00004000
diff --git a/arch/arm/boards/karo-tx6x/flash-header-tx6q-1g.imxcfg b/arch/arm/boards/karo-tx6x/flash-header-tx6q-1g.imxcfg
index 56cb3292a9..165b69fb19 100644
--- a/arch/arm/boards/karo-tx6x/flash-header-tx6q-1g.imxcfg
+++ b/arch/arm/boards/karo-tx6x/flash-header-tx6q-1g.imxcfg
@@ -119,11 +119,11 @@ wm 32 MX6_MMDC_P1_MPRDDQBY3DL 0x33333333
 wm 32 MX6_MMDC_P0_MPMUR0 0x00000800
 wm 32 MX6_MMDC_P1_MPMUR0 0x00000800
 wm 32 MX6_MMDC_P0_MDMISC 0x00000742
-check 32 while_all_bits_clear MX6_MMDC_P0_MDMISC 0x00000002
+check 32 until_all_bits_set MX6_MMDC_P0_MDMISC 0x00000002
 wm 32 MX6_MMDC_P0_MDSCR 0x00008000
-check 32 while_any_bit_clear MX6_MMDC_P0_MDSCR 0x00004000
+check 32 until_any_bit_set MX6_MMDC_P0_MDSCR 0x00004000
 wm 32 MX6_MMDC_P0_MDCTL 0x831a0000
-check 32 while_any_bit_clear MX6_MMDC_P0_MDMISC 0x40000000
+check 32 until_any_bit_set MX6_MMDC_P0_MDMISC 0x40000000
 wm 32 MX6_MMDC_P0_MDCFG0 0x545a79a4
 wm 32 MX6_MMDC_P0_MDCFG1 0xff538e64
 wm 32 MX6_MMDC_P0_MDCFG2 0x01ff00dd
@@ -145,7 +145,7 @@ wm 32 MX6_MMDC_P0_MAPSR 0x00000001
 wm 32 MX6_MMDC_P0_MDSCR 0x04008010
 wm 32 MX6_MMDC_P0_MDSCR 0x04008040
 wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xa1390001
-check 32 while_all_bits_clear MX6_MMDC_P0_MPZQHWCTRL 0x00010000
+check 32 until_all_bits_set MX6_MMDC_P0_MPZQHWCTRL 0x00010000
 wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xa1380000
 wm 32 MX6_MMDC_P0_MDSCR 0x00048033
 wm 32 MX6_IOM_DRAM_SDQS0 0x00000030
@@ -159,19 +159,19 @@ wm 32 MX6_IOM_DRAM_SDQS7 0x00000030
 wm 32 MX6_MMDC_P0_MDSCR 0x04008050
 wm 32 MX6_MMDC_P0_MPRDDLHWCTL 0x00000030
 wm 32 MX6_MMDC_P1_MPRDDLHWCTL 0x00000030
-check 32 while_all_bits_clear MX6_MMDC_P0_MPRDDLHWCTL 0x0000001f
-check 32 while_all_bits_clear MX6_MMDC_P1_MPRDDLHWCTL 0x0000001f
+check 32 until_all_bits_set MX6_MMDC_P0_MPRDDLHWCTL 0x0000001f
+check 32 until_all_bits_set MX6_MMDC_P1_MPRDDLHWCTL 0x0000001f
 wm 32 MX6_MMDC_P0_MDSCR 0x04008050
 wm 32 MX6_MMDC_P0_MPWRDLHWCTL 0x00000030
-check 32 while_all_bits_clear MX6_MMDC_P0_MPWRDLHWCTL 0x0000001f
+check 32 until_all_bits_set MX6_MMDC_P0_MPWRDLHWCTL 0x0000001f
 wm 32 MX6_MMDC_P0_MDSCR 0x04008050
 wm 32 MX6_MMDC_P1_MPWRDLHWCTL 0x00000030
-check 32 while_all_bits_clear MX6_MMDC_P1_MPWRDLHWCTL 0x0000001f
+check 32 until_all_bits_set MX6_MMDC_P1_MPWRDLHWCTL 0x0000001f
 wm 32 MX6_MMDC_P0_MDSCR 0x00008033
 wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xa138002b
 wm 32 MX6_MMDC_P0_MDREF 0x00001800
 wm 32 MX6_MMDC_P0_MAPSR 0x00001000
 wm 32 MX6_MMDC_P0_MDPDC 0x00025576
 wm 32 MX6_MMDC_P0_MDSCR 0x00000000
-check 32 while_all_bits_clear MX6_MMDC_P0_MDSCR 0x00004000
+check 32 until_all_bits_set MX6_MMDC_P0_MDSCR 0x00004000
 
diff --git a/arch/arm/boards/karo-tx6x/flash-header-tx6qp-2g.imxcfg b/arch/arm/boards/karo-tx6x/flash-header-tx6qp-2g.imxcfg
index 4eaca00fc7..fc00de957c 100644
--- a/arch/arm/boards/karo-tx6x/flash-header-tx6qp-2g.imxcfg
+++ b/arch/arm/boards/karo-tx6x/flash-header-tx6qp-2g.imxcfg
@@ -128,11 +128,11 @@ wm 32 MX6_MMDC_P1_MPRDDQBY3DL 0x33333333
 wm 32 MX6_MMDC_P0_MPMUR0 0x00000800
 wm 32 MX6_MMDC_P1_MPMUR0 0x00000800
 wm 32 MX6_MMDC_P0_MDMISC 0x00000742
-check 32 while_all_bits_clear MX6_MMDC_P0_MDMISC 0x00000002
+check 32 until_all_bits_set MX6_MMDC_P0_MDMISC 0x00000002
 wm 32 MX6_MMDC_P0_MDSCR 0x00008000
-check 32 while_any_bit_clear MX6_MMDC_P0_MDSCR 0x00004000
+check 32 until_any_bit_set MX6_MMDC_P0_MDSCR 0x00004000
 wm 32 MX6_MMDC_P0_MDCTL 0x841a0000
-check 32 while_any_bit_clear MX6_MMDC_P0_MDMISC 0x40000000
+check 32 until_any_bit_set MX6_MMDC_P0_MDMISC 0x40000000
 wm 32 MX6_MMDC_P0_MDCFG0 0x898f78f4
 wm 32 MX6_MMDC_P0_MDCFG1 0xff328e64
 wm 32 MX6_MMDC_P0_MDCFG2 0x01ff00db
@@ -155,7 +155,7 @@ wm 32 MX6_MMDC_P0_MAPSR 0x00000001
 wm 32 MX6_MMDC_P0_MDSCR 0x04008010
 wm 32 MX6_MMDC_P0_MDSCR 0x04008040
 wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xa1390001
-check 32 while_all_bits_clear MX6_MMDC_P0_MPZQHWCTRL 0x00010000
+check 32 until_all_bits_set MX6_MMDC_P0_MPZQHWCTRL 0x00010000
 wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xa1380000
 wm 32 MX6_MMDC_P0_MDSCR 0x00048033
 wm 32 MX6_IOM_DRAM_SDQS0 0x00000030
@@ -169,18 +169,18 @@ wm 32 MX6_IOM_DRAM_SDQS7 0x00000030
 wm 32 MX6_MMDC_P0_MDSCR 0x04008050
 wm 32 MX6_MMDC_P0_MPRDDLHWCTL 0x00000030
 wm 32 MX6_MMDC_P1_MPRDDLHWCTL 0x00000030
-check 32 while_all_bits_clear MX6_MMDC_P0_MPRDDLHWCTL 0x0000001f
-check 32 while_all_bits_clear MX6_MMDC_P1_MPRDDLHWCTL 0x0000001f
+check 32 until_all_bits_set MX6_MMDC_P0_MPRDDLHWCTL 0x0000001f
+check 32 until_all_bits_set MX6_MMDC_P1_MPRDDLHWCTL 0x0000001f
 wm 32 MX6_MMDC_P0_MDSCR 0x04008050
 wm 32 MX6_MMDC_P0_MPWRDLHWCTL 0x00000030
-check 32 while_all_bits_clear MX6_MMDC_P0_MPWRDLHWCTL 0x0000001f
+check 32 until_all_bits_set MX6_MMDC_P0_MPWRDLHWCTL 0x0000001f
 wm 32 MX6_MMDC_P0_MDSCR 0x04008050
 wm 32 MX6_MMDC_P1_MPWRDLHWCTL 0x00000030
-check 32 while_all_bits_clear MX6_MMDC_P1_MPWRDLHWCTL 0x0000001f
+check 32 until_all_bits_set MX6_MMDC_P1_MPWRDLHWCTL 0x0000001f
 wm 32 MX6_MMDC_P0_MDSCR 0x00008033
 wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xa138002b
 wm 32 MX6_MMDC_P0_MDREF 0x00001800
 wm 32 MX6_MMDC_P0_MAPSR 0x00001000
 wm 32 MX6_MMDC_P0_MDPDC 0x00025576
 wm 32 MX6_MMDC_P0_MDSCR 0x00000000
-check 32 while_all_bits_clear MX6_MMDC_P0_MDSCR 0x00004000
+check 32 until_all_bits_set MX6_MMDC_P0_MDSCR 0x00004000
diff --git a/arch/arm/boards/kindle-mx50/flash-header-kindle-lpddr1.imxcfg b/arch/arm/boards/kindle-mx50/flash-header-kindle-lpddr1.imxcfg
index e6b6098973..fae10423c5 100644
--- a/arch/arm/boards/kindle-mx50/flash-header-kindle-lpddr1.imxcfg
+++ b/arch/arm/boards/kindle-mx50/flash-header-kindle-lpddr1.imxcfg
@@ -21,7 +21,7 @@ wm 32 0x63f8001c 0x00000080
 wm 32 0x63f80020 0x00000002
 wm 32 0x63f80024 0x00000001
 wm 32 0x63f80000 0x00001232
-check 8 while_any_bit_clear 0x63f80000 0x01
+check 8 until_any_bit_set 0x63f80000 0x01
 # Switch pll1_sw_clk to pll1
 wm 32 0x53fd400c 0x00000000
 
@@ -38,7 +38,7 @@ wm 32 0x53FD4098 0x80000004
 
 # CCM DDR div 4 / 200MHz
 wm 32 0x53fd4098 0x80000004
-check 32 while_all_bits_set 0x53fd408c 0x00000004
+check 32 until_all_bits_clear 0x53fd408c 0x00000004
 
 # IOMUX
 wm 32 0x53fa8490 0x00180000
@@ -163,4 +163,4 @@ wm 32 0x1400025c 0x00102201
 
 # start DDR
 wm 32 0x14000000 0x00000101
-check 32 while_any_bit_clear 0x140000a8 0x00000010
+check 32 until_any_bit_set 0x140000a8 0x00000010
diff --git a/arch/arm/boards/kindle-mx50/flash-header-kindle-lpddr2.imxcfg b/arch/arm/boards/kindle-mx50/flash-header-kindle-lpddr2.imxcfg
index ffceac34b5..94436a7b54 100644
--- a/arch/arm/boards/kindle-mx50/flash-header-kindle-lpddr2.imxcfg
+++ b/arch/arm/boards/kindle-mx50/flash-header-kindle-lpddr2.imxcfg
@@ -22,7 +22,7 @@ wm 32 0x63f8001c 0x00000080
 wm 32 0x63f80020 0x000000b3
 wm 32 0x63f80024 0x000000b4
 wm 32 0x63f80000 0x00001236
-check 8 while_any_bit_clear 0x63f80000 0x01
+check 8 until_any_bit_set 0x63f80000 0x01
 # Switch pll1_sw_clk to pll1
 wm 32 0x53fd400c 0x00000000
 
@@ -39,7 +39,7 @@ wm 32 0x53FD4098 0x80000004
 
 # CCM DDR div 3 / 266MHz
 wm 32 0x53fd4098 0x80000003
-check 32 while_all_bits_set 0x53fd408c 0x00000004
+check 32 until_all_bits_clear 0x53fd408c 0x00000004
 
 # IOMUX
 wm 32 0x53fa86ac 0x04000000
@@ -173,4 +173,4 @@ wm 32 0x1400025c 0x00100b01
 
 # start DDR
 wm 32 0x14000000 0x00000501
-check 32 while_any_bit_clear 0x140000a8 0x00000010
+check 32 until_any_bit_set 0x140000a8 0x00000010
diff --git a/arch/arm/boards/phytec-phycore-imx7/flash-header-phytec-phycore-imx7.imxcfg b/arch/arm/boards/phytec-phycore-imx7/flash-header-phytec-phycore-imx7.imxcfg
index 6c256e8fc5..6e08b6c1b1 100644
--- a/arch/arm/boards/phytec-phycore-imx7/flash-header-phytec-phycore-imx7.imxcfg
+++ b/arch/arm/boards/phytec-phycore-imx7/flash-header-phytec-phycore-imx7.imxcfg
@@ -65,7 +65,7 @@ wm 32 MX7_DDR_PHY_ZQ_CON0 0x0e407304
 wm 32 MX7_DDR_PHY_ZQ_CON0 0x0e447304
 wm 32 MX7_DDR_PHY_ZQ_CON0 0x0e447306
 
-check 32 while_any_bit_clear MX7_DDR_PHY_ZQ_CON1 0x1
+check 32 until_any_bit_set MX7_DDR_PHY_ZQ_CON1 0x1
 
 wm 32 MX7_DDR_PHY_ZQ_CON0 0x0e447304
 wm 32 MX7_DDR_PHY_ZQ_CON0 0x0e407304
@@ -75,4 +75,4 @@ wm 32 0x30340020 0x00000178
 wm 32 0x30384130 0x00000002
 wm 32 MX7_DDR_PHY_LP_CON0 0x0000000f
 
-check 32 while_any_bit_clear MX7_DDRC_STAT 0x1
+check 32 until_any_bit_set MX7_DDRC_STAT 0x1
diff --git a/arch/arm/boards/zii-vf610-dev/flash-header-zii-vf610-dev.imxcfg b/arch/arm/boards/zii-vf610-dev/flash-header-zii-vf610-dev.imxcfg
index 177f4e8bdc..bb858907a4 100644
--- a/arch/arm/boards/zii-vf610-dev/flash-header-zii-vf610-dev.imxcfg
+++ b/arch/arm/boards/zii-vf610-dev/flash-header-zii-vf610-dev.imxcfg
@@ -45,7 +45,7 @@ CHECKPOINT(2)
 /*
  * Wait for PLLs to lock
  */
-check 32 while_any_bit_clear 0x40050030 0x80000000
+check 32 until_any_bit_set 0x40050030 0x80000000
 
 
 CHECKPOINT(3)
@@ -218,26 +218,26 @@ wm 32 0x400ae000 0x00000601
 
 CHECKPOINT(7)
 
-check 32 while_any_bit_clear 0x400ae140 0x100
-# check 32 while_any_bit_clear 0x400ae42c 0x1
-# check 32 while_any_bit_clear 0x400ae46c 0x1
-# check 32 while_any_bit_clear 0x400ae4ac 0x1
+check 32 until_any_bit_set 0x400ae140 0x100
+# check 32 until_any_bit_set 0x400ae42c 0x1
+# check 32 until_any_bit_set 0x400ae46c 0x1
+# check 32 until_any_bit_set 0x400ae4ac 0x1
 
 CHECKPOINT(8)
 
 wm 32 0x80000000 0xa5a5a5a5
-check 32 while_any_bit_clear 0x80000000 0xa5a5a5a5
+check 32 until_any_bit_set 0x80000000 0xa5a5a5a5
 
 wm 32 0x400ae000 0x00000600
 wm 32 0x400ae000 0x00000601
 
-check 32 while_any_bit_clear 0x400ae140 0x100
-# check 32 while_any_bit_clear 0x400ae42c 0x1
-# check 32 while_any_bit_clear 0x400ae46c 0x1
-# check 32 while_any_bit_clear 0x400ae4ac 0x1
+check 32 until_any_bit_set 0x400ae140 0x100
+# check 32 until_any_bit_set 0x400ae42c 0x1
+# check 32 until_any_bit_set 0x400ae46c 0x1
+# check 32 until_any_bit_set 0x400ae4ac 0x1
 
 /* wm 32 0x3f040000 0xf0
- check 32 while_any_bit_clear 0x3f040000 0x0f */
+ check 32 until_any_bit_set 0x3f040000 0x0f */
 
 
 CHECKPOINT(9)
diff --git a/scripts/imx/README b/scripts/imx/README
index b5cdb487a0..d573d3a6be 100644
--- a/scripts/imx/README
+++ b/scripts/imx/README
@@ -7,34 +7,12 @@ The imx-usb-loader tool is used to upload and start i.MX images. These
 are images containing a DCD (Device Configuration Data) table. To generate
 these images from raw binaries use the imx-image tool.
 
-imx-image
----------
+Refer the i.MX related documentation about the DCD source files and their
+content.
 
-The imx-image tool can be used to generate imximages from raw binaries.
-It requires an configuration file describing how to setup the SDRAM on
-a particular board. This mainly consists of a poke table. The recognized
-options in this file are:
+Example for a DCD source file:
 
-soc <soctype>      soctype can be one of imx35, imx51, imx53, imx6
-loadaddr <adr>     The address the binary is uploaded to
-dcdofs <ofs>       The offset of the image header in the image. This should be:
-                   0x400  - MMC/SD, NAND, serial ROM, PATA, SATA
-                   0x1000 - NOR Flash
-                   0x100  - OneNAND
-wm 8 <adr> <value>                    do a byte memory write
-wm 16 <adr> <value>                   do a short memory write
-wm 32 <adr> <value>                   do a word memory write
-check <width> <cond> <addr> <mask>    Poll until condition becomes true.
-                                      with <cond> being one of:
-                                      while_all_bits_clear,
-                                      while_all_bits_set,
-                                      while_any_bit_clear,
-                                      while_any_bit_set
-set_bits <width> <addr> <bits>        set <bits> in register <addr>
-clear_bits <width> <addr> <bits>      clear <bits> in register <addr>
-nop                                   do nothing
-
-the i.MX SoCs support a wide range of fancy things doing with the flash header.
+The i.MX SoCs support a wide range of fancy things doing with the flash header.
 We limit ourselves to a very simple case, that is the flash header has a fixed
 size of 0x1000 bytes. The application is expected right thereafter, so if you
 specify a loadaddr of 0x80000000 in the config file, the first 0x1000 bytes
diff --git a/scripts/imx/imx-usb-loader.c b/scripts/imx/imx-usb-loader.c
index 6052343e00..43dde8b7f2 100644
--- a/scripts/imx/imx-usb-loader.c
+++ b/scripts/imx/imx-usb-loader.c
@@ -935,10 +935,10 @@ static int do_dcd_v2_cmd_check(const unsigned char *dcd)
 	}
 
 	switch ((check->param & 0xf8) >> 3) {
-	case check_all_bits_clear:
-	case check_all_bits_set:
-	case check_any_bit_clear:
-	case check_any_bit_set:
+	case until_all_bits_clear:
+	case until_all_bits_set:
+	case until_any_bit_clear:
+	case until_any_bit_set:
 		cond = (check->param & 0xf8) >> 3;
 		break;
 	default:
@@ -966,20 +966,20 @@ static int do_dcd_v2_cmd_check(const unsigned char *dcd)
 		data &= mask;
 
 		switch (cond) {
-		case check_all_bits_clear:
-			if (data != 0)
+		case until_all_bits_clear:
+			if (data == 0)
 				return 0;
 			break;
-		case check_all_bits_set:
-			if (data != mask)
+		case until_all_bits_set:
+			if (data == mask)
 				return 0;
 			break;
-		case check_any_bit_clear:
-			if (data == mask)
+		case until_any_bit_clear:
+			if (data != mask)
 				return 0;
 			break;
-		case check_any_bit_set:
-			if (data == 0)
+		case until_any_bit_set:
+			if (data != 0)
 				return 0;
 			break;
 		}
diff --git a/scripts/imx/imx.c b/scripts/imx/imx.c
index 809d8a7f71..fb6ac001e2 100644
--- a/scripts/imx/imx.c
+++ b/scripts/imx/imx.c
@@ -69,10 +69,10 @@ struct command {
 };
 
 static const char *check_cmds[] = {
-	"while_all_bits_clear",		/* while ((*address & mask) == 0); */
-	"while_all_bits_set"	,	/* while ((*address & mask) == mask); */
-	"while_any_bit_clear",		/* while ((*address & mask) != mask); */
-	"while_any_bit_set",		/* while ((*address & mask) != 0); */
+	"until_all_bits_clear",	/* until ((*address & mask) == 0) { }; */
+	"until_any_bit_clear",	/* until ((*address & mask) != mask) { }; */
+	"until_all_bits_set",	/* until ((*address & mask) == mask) { }; */
+	"until_any_bit_set",	/* until ((*address & mask) != 0) { }; */
 };
 
 static void do_cmd_check_usage(void)
@@ -81,10 +81,10 @@ static void do_cmd_check_usage(void)
 			"usage: check <width> <cmd> <addr> <mask>\n"
 			"<width> access width in bytes [1|2|4]\n"
 			"with <cmd> one of:\n"
-			"while_all_bits_clear: while ((*addr & mask) == 0)\n"
-			"while_all_bits_set:   while ((*addr & mask) == mask)\n"
-			"while_any_bit_clear:  while ((*addr & mask) != mask)\n"
-			"while_any_bit_set:    while ((*addr & mask) != 0)\n");
+			"until_all_bits_clear: while ((*addr & mask) == 0)\n"
+			"until_all_bits_set:   while ((*addr & mask) == mask)\n"
+			"until_any_bit_clear:  while ((*addr & mask) != mask)\n"
+			"until_any_bit_set:    while ((*addr & mask) != 0)\n");
 }
 
 static int do_cmd_check(struct config_data *data, int argc, char *argv[])
diff --git a/scripts/imx/imx.h b/scripts/imx/imx.h
index f32ae52abf..c7677f81a4 100644
--- a/scripts/imx/imx.h
+++ b/scripts/imx/imx.h
@@ -105,10 +105,10 @@ struct imx_dcd_v2_check {
 } __attribute__((packed));
 
 enum imx_dcd_v2_check_cond {
-	check_all_bits_clear = 0,
-	check_all_bits_set = 1,
-	check_any_bit_clear = 2,
-	check_any_bit_set = 3,
+	until_all_bits_clear = 0, /* until ((*address & mask) == 0) { ...} */
+	until_any_bit_clear = 1, /* until ((*address & mask) != mask) { ...} */
+	until_all_bits_set = 2, /* until ((*address & mask) == mask) { ...} */
+	until_any_bit_set = 3, /* until ((*address & mask) != 0) { ...} */
 } __attribute__((packed));
 
 int parse_config(struct config_data *data, const char *filename);
-- 
2.16.1



From andrey.gusakov at cogentembedded.com  Fri Mar 23 10:12:23 2018
From: andrey.gusakov at cogentembedded.com (Andrey Gusakov)
Date: Fri, 23 Mar 2018 20:12:23 +0300
Subject: [PATCH] video: tc358767: set num_modes=0 if no valid mode found
Message-ID: <1521825143-9979-1-git-send-email-andrey.gusakov@cogentembedded.com>

Since commit f986661 "video: ipu: register framebuffer,
even when no modes are found" value returned from
VPL_GET_VIDEOMODES ioctl is ignored. So set valid num_modes
in error case to avoid crash in register_framebuffer.

Signed-off-by: Andrey Gusakov <andrey.gusakov at cogentembedded.com>
---
 drivers/video/tc358767.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/video/tc358767.c b/drivers/video/tc358767.c
index 5ad5cb4..d4749b1 100644
--- a/drivers/video/tc358767.c
+++ b/drivers/video/tc358767.c
@@ -1258,6 +1258,7 @@ static int tc_filter_videomodes(struct tc_data *tc, struct display_timings *timi
 	} while (1);
 
 	free(timings->modes);
+	timings->num_modes = 0;
 	timings->modes = NULL;
 
 	if (!num_modes) {
-- 
1.9.1



From l.stach at pengutronix.de  Fri Mar 23 16:14:22 2018
From: l.stach at pengutronix.de (Lucas Stach)
Date: Sat, 24 Mar 2018 00:14:22 +0100
Subject: [PATCH v2 10/10] ARM: rpi: autosize malloc area
In-Reply-To: <20180323231422.21137-1-l.stach@pengutronix.de>
References: <20180323231422.21137-1-l.stach@pengutronix.de>
Message-ID: <20180323231422.21137-10-l.stach@pengutronix.de>

Autosize the malloc area according to the available RAM size.

Signed-off-by: Lucas Stach <l.stach at pengutronix.de>
---
 arch/arm/configs/rpi_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/configs/rpi_defconfig b/arch/arm/configs/rpi_defconfig
index 34070a05abe7..ddd1a5970f9e 100644
--- a/arch/arm/configs/rpi_defconfig
+++ b/arch/arm/configs/rpi_defconfig
@@ -7,6 +7,7 @@ CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
 CONFIG_ARM_UNWIND=y
 CONFIG_IMAGE_COMPRESSION_NONE=y
 CONFIG_MMU=y
+CONFIG_MALLOC_SIZE=0x0
 CONFIG_MALLOC_TLSF=y
 CONFIG_KALLSYMS=y
 CONFIG_PROMPT="R-Pi> "
-- 
2.16.1



From l.stach at pengutronix.de  Fri Mar 23 16:14:17 2018
From: l.stach at pengutronix.de (Lucas Stach)
Date: Sat, 24 Mar 2018 00:14:17 +0100
Subject: [PATCH v2 05/10] ARM: don't try to install secure monitor when
 entered in HYP mode
In-Reply-To: <20180323231422.21137-1-l.stach@pengutronix.de>
References: <20180323231422.21137-1-l.stach@pengutronix.de>
Message-ID: <20180323231422.21137-5-l.stach@pengutronix.de>

When Barebox has been entered in HYP mode, the CPU is already switched
to the non-secure world and it's not possible for Barebox to install
it's own secure monitor.

Signed-off-by: Lucas Stach <l.stach at pengutronix.de>
---
 arch/arm/cpu/sm.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/cpu/sm.c b/arch/arm/cpu/sm.c
index 5808dfd92bdc..71bb394c8540 100644
--- a/arch/arm/cpu/sm.c
+++ b/arch/arm/cpu/sm.c
@@ -184,6 +184,9 @@ int armv7_secure_monitor_install(void)
 		return -EINVAL;
 	}
 
+	if (__boot_cpu_mode == HYP_MODE)
+		return 0;
+
 	mmuon = get_cr() & CR_M;
 
 	vbar = get_vbar();
-- 
2.16.1



From l.stach at pengutronix.de  Fri Mar 23 16:14:15 2018
From: l.stach at pengutronix.de (Lucas Stach)
Date: Sat, 24 Mar 2018 00:14:15 +0100
Subject: [PATCH v2 03/10] ARM: allow secure monitor code to be built without
 PSCI
In-Reply-To: <20180323231422.21137-1-l.stach@pengutronix.de>
References: <20180323231422.21137-1-l.stach@pengutronix.de>
Message-ID: <20180323231422.21137-3-l.stach@pengutronix.de>

The hyp mode handling added in the secure monitor code is also useful
when Barebox doesn't have PSCI control. Allow to build without PSCI.

Signed-off-by: Lucas Stach <l.stach at pengutronix.de>
---
 arch/arm/cpu/sm_as.S | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/cpu/sm_as.S b/arch/arm/cpu/sm_as.S
index 09580e75de5f..0d01e1bf2435 100644
--- a/arch/arm/cpu/sm_as.S
+++ b/arch/arm/cpu/sm_as.S
@@ -129,7 +129,9 @@ secure_monitor:
 	sub	sp, sp, #4*4			@ allocate result structure on stack
 	mov	r12, sp
 	push	{r4-r6, r12}
+#ifdef CONFIG_ARM_PSCI
 	bl	psci_entry
+#endif
 	pop	{r4-r6, r12}
 	ldm	r12, {r0-r3}
 	add	sp, sp, #4*4
@@ -163,6 +165,8 @@ ENTRY(psci_cpu_entry)
 	mcr	p15, 0, r0, c1, c0, 1	@ ACTLR
 
 	bl	secure_monitor_stack_setup
+#ifdef CONFIG_ARM_PSCI
 	bl	psci_cpu_entry_c
+#endif
 
 ENDPROC(psci_cpu_entry)
-- 
2.16.1



From l.stach at pengutronix.de  Fri Mar 23 16:14:20 2018
From: l.stach at pengutronix.de (Lucas Stach)
Date: Sat, 24 Mar 2018 00:14:20 +0100
Subject: [PATCH v2 08/10] ARM: rpi: add revision IDs for Pi 3 Model B and Pi
 Zero
In-Reply-To: <20180323231422.21137-1-l.stach@pengutronix.de>
References: <20180323231422.21137-1-l.stach@pengutronix.de>
Message-ID: <20180323231422.21137-8-l.stach@pengutronix.de>

From: Enrico Joerns <ejo at pengutronix.de>

Signed-off-by: Enrico Joerns <ejo at pengutronix.de>
---
 arch/arm/boards/raspberry-pi/rpi-common.c | 2 ++
 arch/arm/mach-bcm283x/include/mach/mbox.h | 4 ++++
 2 files changed, 6 insertions(+)

diff --git a/arch/arm/boards/raspberry-pi/rpi-common.c b/arch/arm/boards/raspberry-pi/rpi-common.c
index 6e375bc984de..aec8cb27ed40 100644
--- a/arch/arm/boards/raspberry-pi/rpi-common.c
+++ b/arch/arm/boards/raspberry-pi/rpi-common.c
@@ -174,6 +174,8 @@ const struct rpi_model rpi_models_old_scheme[] = {
 const struct rpi_model rpi_models_new_scheme[] = {
 	RPI_MODEL(0, "Unknown model", NULL),
 	RPI_MODEL(BCM2836_BOARD_REV_2_B, "2 Model B", rpi_b_plus_init),
+	RPI_MODEL(BCM2837_BOARD_REV_3_B, "3 Model B", rpi_b_plus_init),
+	RPI_MODEL(BCM2837_BOARD_REV_ZERO, "Zero", rpi_b_plus_init),
 };
 
 static int rpi_board_rev = 0;
diff --git a/arch/arm/mach-bcm283x/include/mach/mbox.h b/arch/arm/mach-bcm283x/include/mach/mbox.h
index 2b5aea88ee0a..4cddf99a8429 100644
--- a/arch/arm/mach-bcm283x/include/mach/mbox.h
+++ b/arch/arm/mach-bcm283x/include/mach/mbox.h
@@ -129,6 +129,10 @@ struct bcm2835_mbox_tag_hdr {
 
 /* RPi 2 */
 #define BCM2836_BOARD_REV_2_B		0x4
+/* RPi 3 */
+#define BCM2837_BOARD_REV_3_B		0x8
+/* Zero */
+#define BCM2837_BOARD_REV_ZERO		0x9
 
 /*
  * 0x2..0xf from:
-- 
2.16.1



From l.stach at pengutronix.de  Fri Mar 23 16:14:18 2018
From: l.stach at pengutronix.de (Lucas Stach)
Date: Sat, 24 Mar 2018 00:14:18 +0100
Subject: [PATCH v2 06/10] ARM: default to starting kernel in HYP mode when
 entered in HYP
In-Reply-To: <20180323231422.21137-1-l.stach@pengutronix.de>
References: <20180323231422.21137-1-l.stach@pengutronix.de>
Message-ID: <20180323231422.21137-6-l.stach@pengutronix.de>

When Barebox has been entered in HYP mode, there is a high chance that
the kernel is  intended to be started in HYP mode also. Get this
default into place.

Signed-off-by: Lucas Stach <l.stach at pengutronix.de>
---
 arch/arm/cpu/sm.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/cpu/sm.c b/arch/arm/cpu/sm.c
index 71bb394c8540..3369fbb5ff1a 100644
--- a/arch/arm/cpu/sm.c
+++ b/arch/arm/cpu/sm.c
@@ -264,6 +264,9 @@ static int sm_init(void)
 				  bootm_secure_state_names,
 				  ARRAY_SIZE(bootm_secure_state_names));
 
+	if (__boot_cpu_mode == HYP_MODE)
+		bootm_secure_state = ARM_STATE_HYP;
+
 	return 0;
 }
 device_initcall(sm_init);
\ No newline at end of file
-- 
2.16.1



From l.stach at pengutronix.de  Fri Mar 23 16:14:19 2018
From: l.stach at pengutronix.de (Lucas Stach)
Date: Sat, 24 Mar 2018 00:14:19 +0100
Subject: [PATCH v2 07/10] ARM: install HYP vectors at PBL and Barebox entry
In-Reply-To: <20180323231422.21137-1-l.stach@pengutronix.de>
References: <20180323231422.21137-1-l.stach@pengutronix.de>
Message-ID: <20180323231422.21137-7-l.stach@pengutronix.de>

If the CPU was already in HYP mode when entering the PBL, install a
simple trap handler to allow to get back from SVC to HYP before
switching to HYP mode.

As the vectors are part of the currently running binary, we need to
do the same setup when starting the real Barebox binary, as the PBL
setup vectors might get overwritten. To do this we trap into HYP mode
just before jumping to Barebox and then re-do the vector setup and
SVC switch as the first thing in Barebox proper.

Signed-off-by: Lucas Stach <l.stach at pengutronix.de>
---
 arch/arm/cpu/lowlevel.S   | 3 +++
 arch/arm/cpu/start-pbl.c  | 4 ++++
 arch/arm/cpu/start.c      | 3 +++
 arch/arm/cpu/uncompress.c | 4 ++++
 4 files changed, 14 insertions(+)

diff --git a/arch/arm/cpu/lowlevel.S b/arch/arm/cpu/lowlevel.S
index 194ce0e7c274..28ad8508726f 100644
--- a/arch/arm/cpu/lowlevel.S
+++ b/arch/arm/cpu/lowlevel.S
@@ -8,6 +8,9 @@ ENTRY(arm_cpu_lowlevel_init)
 	/* save lr, since it may be banked away with a processor mode change */
 	mov	r2, lr
 
+	/* careful: the hyp install corrupts r0 and r1 */
+	bl	__hyp_install
+
 	/* set the cpu to SVC32 mode, mask irq and fiq */
 	mrs	r12 , cpsr
 	eor	r12, r12, #HYP_MODE
diff --git a/arch/arm/cpu/start-pbl.c b/arch/arm/cpu/start-pbl.c
index e851b4a2da5e..e0793579e2e8 100644
--- a/arch/arm/cpu/start-pbl.c
+++ b/arch/arm/cpu/start-pbl.c
@@ -26,6 +26,7 @@
 #include <asm/barebox-arm-head.h>
 #include <asm-generic/memory_layout.h>
 #include <asm/sections.h>
+#include <asm/secure.h>
 #include <asm/pgtable.h>
 #include <asm/cache.h>
 #include <asm/unaligned.h>
@@ -100,5 +101,8 @@ __noreturn void barebox_single_pbl_start(unsigned long membase,
 	else
 		barebox = (void *)barebox_base;
 
+	if (__boot_cpu_mode == HYP_MODE)
+		armv7_switch_to_hyp();
+
 	barebox(membase, memsize, boarddata);
 }
diff --git a/arch/arm/cpu/start.c b/arch/arm/cpu/start.c
index 171e6ad0eb7a..a0db6436f387 100644
--- a/arch/arm/cpu/start.c
+++ b/arch/arm/cpu/start.c
@@ -24,6 +24,7 @@
 #include <asm/barebox-arm-head.h>
 #include <asm-generic/memory_layout.h>
 #include <asm/sections.h>
+#include <asm/secure.h>
 #include <asm/unaligned.h>
 #include <asm/cache.h>
 #include <memory.h>
@@ -145,6 +146,8 @@ __noreturn void barebox_non_pbl_start(unsigned long membase,
 	unsigned long malloc_start, malloc_end;
 	unsigned long barebox_size = barebox_image_size + MAX_BSS_SIZE;
 
+	armv7_hyp_install();
+
 	if (IS_ENABLED(CONFIG_RELOCATABLE)) {
 		unsigned long barebox_base = arm_mem_barebox_image(membase,
 								   endmem,
diff --git a/arch/arm/cpu/uncompress.c b/arch/arm/cpu/uncompress.c
index 9d7fe0e921a9..28636aa8101f 100644
--- a/arch/arm/cpu/uncompress.c
+++ b/arch/arm/cpu/uncompress.c
@@ -27,6 +27,7 @@
 #include <asm/barebox-arm-head.h>
 #include <asm-generic/memory_layout.h>
 #include <asm/sections.h>
+#include <asm/secure.h>
 #include <asm/pgtable.h>
 #include <asm/cache.h>
 #include <asm/unaligned.h>
@@ -109,5 +110,8 @@ void __noreturn barebox_multi_pbl_start(unsigned long membase,
 
 	pr_debug("jumping to uncompressed image at 0x%p\n", barebox);
 
+	if (__boot_cpu_mode == HYP_MODE)
+		armv7_switch_to_hyp();
+
 	barebox(membase, memsize, boarddata);
 }
-- 
2.16.1



From l.stach at pengutronix.de  Fri Mar 23 16:14:16 2018
From: l.stach at pengutronix.de (Lucas Stach)
Date: Sat, 24 Mar 2018 00:14:16 +0100
Subject: [PATCH v2 04/10] ARM: add file for HYP mode related setup
In-Reply-To: <20180323231422.21137-1-l.stach@pengutronix.de>
References: <20180323231422.21137-1-l.stach@pengutronix.de>
Message-ID: <20180323231422.21137-4-l.stach@pengutronix.de>

This adds routines to add hyp mode vectors and switch back to HYP
mode from SVC. This is needed in both the PBL and Barebox proper.

Signed-off-by: Lucas Stach <l.stach at pengutronix.de>
---
 arch/arm/cpu/Makefile         |   4 ++
 arch/arm/cpu/hyp.S            | 115 ++++++++++++++++++++++++++++++++++++++++++
 arch/arm/cpu/sm_as.S          |  11 ----
 arch/arm/include/asm/secure.h |   8 +++
 4 files changed, 127 insertions(+), 11 deletions(-)
 create mode 100644 arch/arm/cpu/hyp.S

diff --git a/arch/arm/cpu/Makefile b/arch/arm/cpu/Makefile
index 13fe12c31f6f..f86dff975bb4 100644
--- a/arch/arm/cpu/Makefile
+++ b/arch/arm/cpu/Makefile
@@ -9,6 +9,10 @@ obj-$(CONFIG_ARM_EXCEPTIONS) += exceptions.o
 obj-$(CONFIG_MMU) += mmu.o mmu-early.o
 pbl-$(CONFIG_MMU) += mmu-early.o
 lwl-y += lowlevel.o
+obj-y += hyp.o
+AFLAGS_hyp.o :=-Wa,-march=armv7-a -Wa,-mcpu=all
+pbl-y += hyp.o
+AFLAGS_pbl-hyp.o :=-Wa,-march=armv7-a -Wa,-mcpu=all
 endif
 
 obj-$(CONFIG_ARM_EXCEPTIONS) += interrupts.o
diff --git a/arch/arm/cpu/hyp.S b/arch/arm/cpu/hyp.S
new file mode 100644
index 000000000000..435d416f980a
--- /dev/null
+++ b/arch/arm/cpu/hyp.S
@@ -0,0 +1,115 @@
+#include <linux/linkage.h>
+#include <asm/system.h>
+#include <asm/opcodes-virt.h>
+
+.arch_extension sec
+.arch_extension virt
+
+.section ".text_bare_init_","ax"
+
+.data
+	.align  2
+ENTRY(__boot_cpu_mode)
+	.long   0
+.text
+
+ENTRY(__hyp_install)
+	mrs	r12, cpsr
+	and	r12, r12, #MODE_MASK
+
+	@ Save the initial CPU state
+	adr	r0, .L__boot_cpu_mode_offset
+	ldr	r1, [r0]
+	str	r12, [r0, r1]
+
+	cmp	r12, #HYP_MODE
+	movne	pc, lr			@ give up if the CPU is not in HYP mode
+
+	@ Now install the hypervisor stub:
+	adr	r12, __hyp_vectors
+	mcr	p15, 4, r12, c12, c0, 0	@ set hypervisor vector base (HVBAR)
+
+	@ Disable all traps, so we don't get any nasty surprise
+	mov	r12, #0
+	mcr	p15, 4, r12, c1, c1, 0	@ HCR
+	mcr	p15, 4, r12, c1, c1, 2	@ HCPTR
+	mcr	p15, 4, r12, c1, c1, 3	@ HSTR
+
+THUMB(	orr	r12, #(1 << 30)	)	@ HSCTLR.TE
+	mcr	p15, 4, r12, c1, c0, 0	@ HSCTLR
+
+	mrc	p15, 4, r12, c1, c1, 1	@ HDCR
+	and	r12, #0x1f		@ Preserve HPMN
+	mcr	p15, 4, r12, c1, c1, 1	@ HDCR
+
+	@ Make sure NS-SVC is initialised appropriately
+	mrc	p15, 0, r12, c1, c0, 0	@ SCTLR
+	orr	r12, #(1 << 5)		@ CP15 barriers enabled
+	bic	r12, #(3 << 7)		@ Clear SED/ITD for v8 (RES0 for v7)
+	bic	r12, #(3 << 19)		@ WXN and UWXN disabled
+	mcr	p15, 0, r12, c1, c0, 0	@ SCTLR
+
+	mrc	p15, 0, r12, c0, c0, 0	@ MIDR
+	mcr	p15, 4, r12, c0, c0, 0	@ VPIDR
+
+	mrc	p15, 0, r12, c0, c0, 5	@ MPIDR
+	mcr	p15, 4, r12, c0, c0, 5	@ VMPIDR
+	bx	lr
+ENDPROC(__hyp_install)
+
+ENTRY(armv7_hyp_install)
+	mov	r2, lr
+
+	bl	__hyp_install
+
+	/* set the cpu to SVC32 mode, mask irq and fiq */
+	mrs	r12 , cpsr
+	eor	r12, r12, #HYP_MODE
+	tst	r12, #MODE_MASK
+	bic	r12 , r12 , #MODE_MASK
+	orr	r12 , r12 , #(PSR_I_BIT | PSR_F_BIT | SVC_MODE)
+THUMB(	orr	r12 , r12 , #PSR_T_BIT	)
+	bne	1f
+	orr	r12, r12, #PSR_A_BIT
+	adr	lr, 2f
+	msr	spsr_cxsf, r12
+	__MSR_ELR_HYP(14)
+	__ERET
+1:	msr	cpsr_c, r12
+2:
+	mov	pc, r2
+ENDPROC(armv7_hyp_install)
+
+ENTRY(armv7_switch_to_hyp)
+	mov	r0, lr
+	mov	r1, sp		@ save SVC copy of LR and SP
+	isb
+	hvc #0			@ for older asm: .byte 0x70, 0x00, 0x40, 0xe1
+	mov	sp, r1
+	mov	lr, r0		@ restore SVC copy of LR and SP
+
+	bx	lr
+ENDPROC(armv7_switch_to_hyp)
+
+.align 2
+.L__boot_cpu_mode_offset:
+	.long	__boot_cpu_mode - .
+
+/* The HYP trap is crafted to match armv7_switch_to_hyp() */
+__hyp_do_trap:
+	mov lr, r0
+	mov sp, r1
+	bx  lr
+ENDPROC(__hyp_do_trap)
+
+.align 5
+__hyp_vectors:
+__hyp_reset:	W(b)	.
+__hyp_und:	W(b)	.
+__hyp_svc:	W(b)	.
+__hyp_pabort:	W(b)	.
+__hyp_dabort:	W(b)	.
+__hyp_trap:	W(b)	__hyp_do_trap
+__hyp_irq:	W(b)	.
+__hyp_fiq:	W(b)	.
+ENDPROC(__hyp_vectors)
diff --git a/arch/arm/cpu/sm_as.S b/arch/arm/cpu/sm_as.S
index 0d01e1bf2435..de6cd0406f4f 100644
--- a/arch/arm/cpu/sm_as.S
+++ b/arch/arm/cpu/sm_as.S
@@ -148,17 +148,6 @@ hyp_trap:
         mov pc, lr                              @ do no switch modes, but
                                                 @ return to caller
 
-ENTRY(armv7_switch_to_hyp)
-	mov	r0, lr
-	mov	r1, sp		@ save SVC copy of LR and SP
-	isb
-	hvc #0			@ for older asm: .byte 0x70, 0x00, 0x40, 0xe1
-	mov	sp, r1
-	mov	lr, r0		@ restore SVC copy of LR and SP
-
-	bx	lr
-ENDPROC(armv7_switch_to_hyp)
-
 ENTRY(psci_cpu_entry)
 	mrc	p15, 0, r0, c1, c0, 1	@ ACTLR
 	orr	r0, r0, #(1 << 6)	@ Set SMP bit
diff --git a/arch/arm/include/asm/secure.h b/arch/arm/include/asm/secure.h
index a4cb1f6c1c44..4eb2c3ec3011 100644
--- a/arch/arm/include/asm/secure.h
+++ b/arch/arm/include/asm/secure.h
@@ -5,9 +5,17 @@
 
 int armv7_secure_monitor_install(void);
 int __armv7_secure_monitor_install(void);
+
+#ifndef CONFIG_CPU_V8
 void armv7_switch_to_hyp(void);
+void armv7_hyp_install(void);
+#else
+static inline void armv7_switch_to_hyp(void) { };
+static inline void armv7_hyp_install(void) { };
+#endif
 
 extern unsigned char secure_monitor_init_vectors[];
+extern int __boot_cpu_mode;
 
 enum arm_security_state {
 	ARM_STATE_SECURE,
-- 
2.16.1



From l.stach at pengutronix.de  Fri Mar 23 16:14:14 2018
From: l.stach at pengutronix.de (Lucas Stach)
Date: Sat, 24 Mar 2018 00:14:14 +0100
Subject: [PATCH v2 02/10] ARM: safely switch from HYP to SVC mode if required
In-Reply-To: <20180323231422.21137-1-l.stach@pengutronix.de>
References: <20180323231422.21137-1-l.stach@pengutronix.de>
Message-ID: <20180323231422.21137-2-l.stach@pengutronix.de>

This is a port of the Linux safe_svcmode_maskall macro to
the Barebox lowlevel init.

Signed-off-by: Lucas Stach <l.stach at pengutronix.de>
---
 arch/arm/cpu/lowlevel.S       | 20 ++++++++++++++++----
 arch/arm/include/asm/system.h | 26 ++++++++++++++++++++++++++
 2 files changed, 42 insertions(+), 4 deletions(-)

diff --git a/arch/arm/cpu/lowlevel.S b/arch/arm/cpu/lowlevel.S
index 7696a198e764..194ce0e7c274 100644
--- a/arch/arm/cpu/lowlevel.S
+++ b/arch/arm/cpu/lowlevel.S
@@ -1,16 +1,28 @@
 #include <linux/linkage.h>
 #include <init.h>
 #include <asm/system.h>
+#include <asm/opcodes-virt.h>
 
 .section ".text_bare_init_","ax"
 ENTRY(arm_cpu_lowlevel_init)
 	/* save lr, since it may be banked away with a processor mode change */
 	mov	r2, lr
+
 	/* set the cpu to SVC32 mode, mask irq and fiq */
-	mrs	r12, cpsr
-	bic	r12, r12, #0x1f
-	orr	r12, r12, #0xd3
-	msr	cpsr, r12
+	mrs	r12 , cpsr
+	eor	r12, r12, #HYP_MODE
+	tst	r12, #MODE_MASK
+	bic	r12 , r12 , #MODE_MASK
+	orr	r12 , r12 , #(PSR_I_BIT | PSR_F_BIT | SVC_MODE)
+THUMB(	orr	r12 , r12 , #PSR_T_BIT	)
+	bne	1f
+	orr	r12, r12, #PSR_A_BIT
+	adr	lr, 2f
+	msr	spsr_cxsf, r12
+	__MSR_ELR_HYP(14)
+	__ERET
+1:	msr	cpsr_c, r12
+2:
 
 #if __LINUX_ARM_ARCH__ >= 6
 	/*
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 57c76186b499..55e0f4090295 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -60,6 +60,32 @@
 #define CR_AFE  (1 << 29)	/* Access flag enable			*/
 #define CR_TE   (1 << 30)	/* Thumb exception enable		*/
 
+/*
+ * PSR bits
+ */
+#define USR_MODE	0x00000010
+#define FIQ_MODE	0x00000011
+#define IRQ_MODE	0x00000012
+#define SVC_MODE	0x00000013
+#define ABT_MODE	0x00000017
+#define HYP_MODE	0x0000001a
+#define UND_MODE	0x0000001b
+#define SYSTEM_MODE	0x0000001f
+#define MODE32_BIT	0x00000010
+#define MODE_MASK	0x0000001f
+
+#define PSR_T_BIT	0x00000020
+#define PSR_F_BIT	0x00000040
+#define PSR_I_BIT	0x00000080
+#define PSR_A_BIT	0x00000100
+#define PSR_E_BIT	0x00000200
+#define PSR_J_BIT	0x01000000
+#define PSR_Q_BIT	0x08000000
+#define PSR_V_BIT	0x10000000
+#define PSR_C_BIT	0x20000000
+#define PSR_Z_BIT	0x40000000
+#define PSR_N_BIT	0x80000000
+
 #ifndef __ASSEMBLY__
 #if __LINUX_ARM_ARCH__ >= 7
 static inline unsigned int current_el(void)
-- 
2.16.1



From l.stach at pengutronix.de  Fri Mar 23 16:14:21 2018
From: l.stach at pengutronix.de (Lucas Stach)
Date: Sat, 24 Mar 2018 00:14:21 +0100
Subject: [PATCH v2 09/10] ARM: rpi: add raspberry pi 3 support
In-Reply-To: <20180323231422.21137-1-l.stach@pengutronix.de>
References: <20180323231422.21137-1-l.stach@pengutronix.de>
Message-ID: <20180323231422.21137-9-l.stach@pengutronix.de>

This adds basic support at the same feature level as the other
supported raspberry pi boards.

Signed-off-by: Lucas Stach <l.stach at pengutronix.de>
---
 arch/arm/boards/raspberry-pi/lowlevel.c | 14 ++++++++++++--
 arch/arm/configs/rpi_defconfig          |  2 ++
 arch/arm/dts/Makefile                   |  1 +
 arch/arm/dts/bcm2837-rpi-3.dts          | 15 +++++++++++++++
 arch/arm/mach-bcm283x/Kconfig           |  6 ++++++
 arch/arm/mach-bcm283x/core.c            |  1 +
 images/Makefile.bcm283x                 |  4 ++++
 7 files changed, 41 insertions(+), 2 deletions(-)
 create mode 100644 arch/arm/dts/bcm2837-rpi-3.dts

diff --git a/arch/arm/boards/raspberry-pi/lowlevel.c b/arch/arm/boards/raspberry-pi/lowlevel.c
index 4e71e29e0c0b..5ca0d3877069 100644
--- a/arch/arm/boards/raspberry-pi/lowlevel.c
+++ b/arch/arm/boards/raspberry-pi/lowlevel.c
@@ -1,7 +1,7 @@
+#include <asm/barebox-arm.h>
+#include <asm/cache.h>
 #include <common.h>
 #include <linux/sizes.h>
-#include <asm/barebox-arm.h>
-#include <asm/barebox-arm-head.h>
 #include <mach/platform.h>
 
 extern char __dtb_bcm2835_rpi_start[];
@@ -23,3 +23,13 @@ ENTRY_FUNCTION(start_raspberry_pi2, r0, r1, r2)
 
 	barebox_arm_entry(BCM2835_SDRAM_BASE, SZ_512M, fdt);
 }
+
+extern char __dtb_bcm2837_rpi_3_start[];
+ENTRY_FUNCTION(start_raspberry_pi3, r0, r1, r2)
+{
+	void *fdt = __dtb_bcm2837_rpi_3_start - get_runtime_offset();
+
+	arm_cpu_lowlevel_init();
+
+	barebox_arm_entry(BCM2835_SDRAM_BASE, SZ_512M, fdt);
+}
diff --git a/arch/arm/configs/rpi_defconfig b/arch/arm/configs/rpi_defconfig
index 6dc90c59b36d..34070a05abe7 100644
--- a/arch/arm/configs/rpi_defconfig
+++ b/arch/arm/configs/rpi_defconfig
@@ -1,9 +1,11 @@
 CONFIG_ARCH_BCM283X=y
 CONFIG_MACH_RPI=y
 CONFIG_MACH_RPI2=y
+CONFIG_MACH_RPI3=y
 CONFIG_AEABI=y
 CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
 CONFIG_ARM_UNWIND=y
+CONFIG_IMAGE_COMPRESSION_NONE=y
 CONFIG_MMU=y
 CONFIG_MALLOC_TLSF=y
 CONFIG_KALLSYMS=y
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 0526a6f40724..0eab313c5011 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -66,6 +66,7 @@ pbl-dtb-$(CONFIG_MACH_PHYTEC_SOM_RK3288) += rk3288-phycore-som.dtb.o
 pbl-dtb-$(CONFIG_MACH_REALQ7) += imx6q-dmo-edmqmx6.dtb.o
 pbl-dtb-$(CONFIG_MACH_RPI) += bcm2835-rpi.dtb.o
 pbl-dtb-$(CONFIG_MACH_RPI2) += bcm2836-rpi-2.dtb.o
+pbl-dtb-$(CONFIG_MACH_RPI3) += bcm2837-rpi-3.dtb.o
 pbl-dtb-$(CONFIG_MACH_SABRELITE) += imx6q-sabrelite.dtb.o imx6dl-sabrelite.dtb.o
 pbl-dtb-$(CONFIG_MACH_SABRESD) += imx6q-sabresd.dtb.o
 pbl-dtb-$(CONFIG_MACH_FREESCALE_IMX6SX_SABRESDB) += imx6sx-sdb.dtb.o
diff --git a/arch/arm/dts/bcm2837-rpi-3.dts b/arch/arm/dts/bcm2837-rpi-3.dts
new file mode 100644
index 000000000000..f8c58c570137
--- /dev/null
+++ b/arch/arm/dts/bcm2837-rpi-3.dts
@@ -0,0 +1,15 @@
+#include <arm64/broadcom/bcm2837-rpi-3-b.dts>
+
+/ {
+	chosen {
+		stdout-path = &uart0;
+	};
+
+	memory {
+		reg = <0x0 0x0>;
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
diff --git a/arch/arm/mach-bcm283x/Kconfig b/arch/arm/mach-bcm283x/Kconfig
index 1457f114ccaa..af2f88c47acb 100644
--- a/arch/arm/mach-bcm283x/Kconfig
+++ b/arch/arm/mach-bcm283x/Kconfig
@@ -19,6 +19,12 @@ config MACH_RPI2
 	select CPU_V7
 	select MACH_RPI_COMMON
 
+config MACH_RPI3
+	bool "RaspberryPi 3 (BCM2837/CORTEX-A53)"
+	select CPU_V7
+	select MACH_RPI_COMMON
+	select ARM_SECURE_MONITOR
+
 endmenu
 
 config MACH_RPI_DEBUG_UART_BASE
diff --git a/arch/arm/mach-bcm283x/core.c b/arch/arm/mach-bcm283x/core.c
index fddcb0d1a1d4..26f0996b1cb8 100644
--- a/arch/arm/mach-bcm283x/core.c
+++ b/arch/arm/mach-bcm283x/core.c
@@ -41,6 +41,7 @@ static int bcm2835_clk_init(void)
 	clk = clk_fixed("uart0-pl0110", 3 * 1000 * 1000);
 	clk_register_clkdev(clk, NULL, "uart0-pl0110");
 	clk_register_clkdev(clk, NULL, "20201000.serial");
+	clk_register_clkdev(clk, NULL, "3f201000.serial");
 
 	clk = clk_fixed("bcm2835-cs", 1 * 1000 * 1000);
 	clk_register_clkdev(clk, NULL, "bcm2835-cs");
diff --git a/images/Makefile.bcm283x b/images/Makefile.bcm283x
index d59ef043f05c..d14e648926ac 100644
--- a/images/Makefile.bcm283x
+++ b/images/Makefile.bcm283x
@@ -9,3 +9,7 @@ image-$(CONFIG_MACH_RPI) += barebox-raspberry-pi-1.img
 pblx-$(CONFIG_MACH_RPI2) += start_raspberry_pi2
 FILE_barebox-raspberry-pi-2.img = start_raspberry_pi2.pblx
 image-$(CONFIG_MACH_RPI2) += barebox-raspberry-pi-2.img
+
+pblx-$(CONFIG_MACH_RPI3) += start_raspberry_pi3
+FILE_barebox-raspberry-pi-3.img = start_raspberry_pi3.pblx
+image-$(CONFIG_MACH_RPI3) += barebox-raspberry-pi-3.img
\ No newline at end of file
-- 
2.16.1



From l.stach at pengutronix.de  Fri Mar 23 16:14:13 2018
From: l.stach at pengutronix.de (Lucas Stach)
Date: Sat, 24 Mar 2018 00:14:13 +0100
Subject: [PATCH v2 01/10] ARM: import opcode helpers from Linux kernel
Message-ID: <20180323231422.21137-1-l.stach@pengutronix.de>

Those are needed to generate some of the ARM SEC and VIRT
opcodes in a portable way.

Signed-off-by: Lucas Stach <l.stach at pengutronix.de>
---
 arch/arm/include/asm/opcodes-virt.h |  39 ++++++
 arch/arm/include/asm/opcodes.h      | 231 ++++++++++++++++++++++++++++++++++++
 2 files changed, 270 insertions(+)
 create mode 100644 arch/arm/include/asm/opcodes-virt.h
 create mode 100644 arch/arm/include/asm/opcodes.h

diff --git a/arch/arm/include/asm/opcodes-virt.h b/arch/arm/include/asm/opcodes-virt.h
new file mode 100644
index 000000000000..efcfdf92d9d5
--- /dev/null
+++ b/arch/arm/include/asm/opcodes-virt.h
@@ -0,0 +1,39 @@
+/*
+ * opcodes-virt.h: Opcode definitions for the ARM virtualization extensions
+ * Copyright (C) 2012  Linaro Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+#ifndef __ASM_ARM_OPCODES_VIRT_H
+#define __ASM_ARM_OPCODES_VIRT_H
+
+#include <asm/opcodes.h>
+
+#define __HVC(imm16) __inst_arm_thumb32(				\
+	0xE1400070 | (((imm16) & 0xFFF0) << 4) | ((imm16) & 0x000F),	\
+	0xF7E08000 | (((imm16) & 0xF000) << 4) | ((imm16) & 0x0FFF)	\
+)
+
+#define __ERET	__inst_arm_thumb32(					\
+	0xE160006E,							\
+	0xF3DE8F00							\
+)
+
+#define __MSR_ELR_HYP(regnum)	__inst_arm_thumb32(			\
+	0xE12EF300 | regnum,						\
+	0xF3808E30 | (regnum << 16)					\
+)
+
+#endif /* ! __ASM_ARM_OPCODES_VIRT_H */
diff --git a/arch/arm/include/asm/opcodes.h b/arch/arm/include/asm/opcodes.h
new file mode 100644
index 000000000000..a78bf5d2c518
--- /dev/null
+++ b/arch/arm/include/asm/opcodes.h
@@ -0,0 +1,231 @@
+/*
+ *  arch/arm/include/asm/opcodes.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARM_OPCODES_H
+#define __ASM_ARM_OPCODES_H
+
+#ifndef __ASSEMBLY__
+#include <linux/linkage.h>
+extern asmlinkage unsigned int arm_check_condition(u32 opcode, u32 psr);
+#endif
+
+#define ARM_OPCODE_CONDTEST_FAIL   0
+#define ARM_OPCODE_CONDTEST_PASS   1
+#define ARM_OPCODE_CONDTEST_UNCOND 2
+
+
+/*
+ * Assembler opcode byteswap helpers.
+ * These are only intended for use by this header: don't use them directly,
+ * because they will be suboptimal in most cases.
+ */
+#define ___asm_opcode_swab32(x) (	\
+	  (((x) << 24) & 0xFF000000)	\
+	| (((x) <<  8) & 0x00FF0000)	\
+	| (((x) >>  8) & 0x0000FF00)	\
+	| (((x) >> 24) & 0x000000FF)	\
+)
+#define ___asm_opcode_swab16(x) (	\
+	  (((x) << 8) & 0xFF00)		\
+	| (((x) >> 8) & 0x00FF)		\
+)
+#define ___asm_opcode_swahb32(x) (	\
+	  (((x) << 8) & 0xFF00FF00)	\
+	| (((x) >> 8) & 0x00FF00FF)	\
+)
+#define ___asm_opcode_swahw32(x) (	\
+	  (((x) << 16) & 0xFFFF0000)	\
+	| (((x) >> 16) & 0x0000FFFF)	\
+)
+#define ___asm_opcode_identity32(x) ((x) & 0xFFFFFFFF)
+#define ___asm_opcode_identity16(x) ((x) & 0xFFFF)
+
+
+/*
+ * Opcode byteswap helpers
+ *
+ * These macros help with converting instructions between a canonical integer
+ * format and in-memory representation, in an endianness-agnostic manner.
+ *
+ * __mem_to_opcode_*() convert from in-memory representation to canonical form.
+ * __opcode_to_mem_*() convert from canonical form to in-memory representation.
+ *
+ *
+ * Canonical instruction representation:
+ *
+ *	ARM:		0xKKLLMMNN
+ *	Thumb 16-bit:	0x0000KKLL, where KK < 0xE8
+ *	Thumb 32-bit:	0xKKLLMMNN, where KK >= 0xE8
+ *
+ * There is no way to distinguish an ARM instruction in canonical representation
+ * from a Thumb instruction (just as these cannot be distinguished in memory).
+ * Where this distinction is important, it needs to be tracked separately.
+ *
+ * Note that values in the range 0x0000E800..0xE7FFFFFF intentionally do not
+ * represent any valid Thumb-2 instruction.  For this range,
+ * __opcode_is_thumb32() and __opcode_is_thumb16() will both be false.
+ *
+ * The ___asm variants are intended only for use by this header, in situations
+ * involving inline assembler.  For .S files, the normal __opcode_*() macros
+ * should do the right thing.
+ */
+#ifdef __ASSEMBLY__
+
+#define ___opcode_swab32(x) ___asm_opcode_swab32(x)
+#define ___opcode_swab16(x) ___asm_opcode_swab16(x)
+#define ___opcode_swahb32(x) ___asm_opcode_swahb32(x)
+#define ___opcode_swahw32(x) ___asm_opcode_swahw32(x)
+#define ___opcode_identity32(x) ___asm_opcode_identity32(x)
+#define ___opcode_identity16(x) ___asm_opcode_identity16(x)
+
+#else /* ! __ASSEMBLY__ */
+
+#include <linux/types.h>
+#include <linux/swab.h>
+
+#define ___opcode_swab32(x) swab32(x)
+#define ___opcode_swab16(x) swab16(x)
+#define ___opcode_swahb32(x) swahb32(x)
+#define ___opcode_swahw32(x) swahw32(x)
+#define ___opcode_identity32(x) ((u32)(x))
+#define ___opcode_identity16(x) ((u16)(x))
+
+#endif /* ! __ASSEMBLY__ */
+
+
+#ifdef CONFIG_CPU_ENDIAN_BE8
+
+#define __opcode_to_mem_arm(x) ___opcode_swab32(x)
+#define __opcode_to_mem_thumb16(x) ___opcode_swab16(x)
+#define __opcode_to_mem_thumb32(x) ___opcode_swahb32(x)
+#define ___asm_opcode_to_mem_arm(x) ___asm_opcode_swab32(x)
+#define ___asm_opcode_to_mem_thumb16(x) ___asm_opcode_swab16(x)
+#define ___asm_opcode_to_mem_thumb32(x) ___asm_opcode_swahb32(x)
+
+#else /* ! CONFIG_CPU_ENDIAN_BE8 */
+
+#define __opcode_to_mem_arm(x) ___opcode_identity32(x)
+#define __opcode_to_mem_thumb16(x) ___opcode_identity16(x)
+#define ___asm_opcode_to_mem_arm(x) ___asm_opcode_identity32(x)
+#define ___asm_opcode_to_mem_thumb16(x) ___asm_opcode_identity16(x)
+#ifndef CONFIG_CPU_ENDIAN_BE32
+/*
+ * On BE32 systems, using 32-bit accesses to store Thumb instructions will not
+ * work in all cases, due to alignment constraints.  For now, a correct
+ * version is not provided for BE32.
+ */
+#define __opcode_to_mem_thumb32(x) ___opcode_swahw32(x)
+#define ___asm_opcode_to_mem_thumb32(x) ___asm_opcode_swahw32(x)
+#endif
+
+#endif /* ! CONFIG_CPU_ENDIAN_BE8 */
+
+#define __mem_to_opcode_arm(x) __opcode_to_mem_arm(x)
+#define __mem_to_opcode_thumb16(x) __opcode_to_mem_thumb16(x)
+#ifndef CONFIG_CPU_ENDIAN_BE32
+#define __mem_to_opcode_thumb32(x) __opcode_to_mem_thumb32(x)
+#endif
+
+/* Operations specific to Thumb opcodes */
+
+/* Instruction size checks: */
+#define __opcode_is_thumb32(x) (		\
+	   ((x) & 0xF8000000) == 0xE8000000	\
+	|| ((x) & 0xF0000000) == 0xF0000000	\
+)
+#define __opcode_is_thumb16(x) (					\
+	   ((x) & 0xFFFF0000) == 0					\
+	&& !(((x) & 0xF800) == 0xE800 || ((x) & 0xF000) == 0xF000)	\
+)
+
+/* Operations to construct or split 32-bit Thumb instructions: */
+#define __opcode_thumb32_first(x) (___opcode_identity16((x) >> 16))
+#define __opcode_thumb32_second(x) (___opcode_identity16(x))
+#define __opcode_thumb32_compose(first, second) (			\
+	  (___opcode_identity32(___opcode_identity16(first)) << 16)	\
+	| ___opcode_identity32(___opcode_identity16(second))		\
+)
+#define ___asm_opcode_thumb32_first(x) (___asm_opcode_identity16((x) >> 16))
+#define ___asm_opcode_thumb32_second(x) (___asm_opcode_identity16(x))
+#define ___asm_opcode_thumb32_compose(first, second) (			    \
+	  (___asm_opcode_identity32(___asm_opcode_identity16(first)) << 16) \
+	| ___asm_opcode_identity32(___asm_opcode_identity16(second))	    \
+)
+
+/*
+ * Opcode injection helpers
+ *
+ * In rare cases it is necessary to assemble an opcode which the
+ * assembler does not support directly, or which would normally be
+ * rejected because of the CFLAGS or AFLAGS used to build the affected
+ * file.
+ *
+ * Before using these macros, consider carefully whether it is feasible
+ * instead to change the build flags for your file, or whether it really
+ * makes sense to support old assembler versions when building that
+ * particular kernel feature.
+ *
+ * The macros defined here should only be used where there is no viable
+ * alternative.
+ *
+ *
+ * __inst_arm(x): emit the specified ARM opcode
+ * __inst_thumb16(x): emit the specified 16-bit Thumb opcode
+ * __inst_thumb32(x): emit the specified 32-bit Thumb opcode
+ *
+ * __inst_arm_thumb16(arm, thumb): emit either the specified arm or
+ *	16-bit Thumb opcode, depending on whether an ARM or Thumb-2
+ *	kernel is being built
+ *
+ * __inst_arm_thumb32(arm, thumb): emit either the specified arm or
+ *	32-bit Thumb opcode, depending on whether an ARM or Thumb-2
+ *	kernel is being built
+ *
+ *
+ * Note that using these macros directly is poor practice.  Instead, you
+ * should use them to define human-readable wrapper macros to encode the
+ * instructions that you care about.  In code which might run on ARMv7 or
+ * above, you can usually use the __inst_arm_thumb{16,32} macros to
+ * specify the ARM and Thumb alternatives at the same time.  This ensures
+ * that the correct opcode gets emitted depending on the instruction set
+ * used for the kernel build.
+ *
+ * Look at opcodes-virt.h for an example of how to use these macros.
+ */
+#include <linux/stringify.h>
+
+#define __inst_arm(x) ___inst_arm(___asm_opcode_to_mem_arm(x))
+#define __inst_thumb32(x) ___inst_thumb32(				\
+	___asm_opcode_to_mem_thumb16(___asm_opcode_thumb32_first(x)),	\
+	___asm_opcode_to_mem_thumb16(___asm_opcode_thumb32_second(x))	\
+)
+#define __inst_thumb16(x) ___inst_thumb16(___asm_opcode_to_mem_thumb16(x))
+
+#ifdef CONFIG_THUMB2_BAREBOX
+#define __inst_arm_thumb16(arm_opcode, thumb_opcode) \
+	__inst_thumb16(thumb_opcode)
+#define __inst_arm_thumb32(arm_opcode, thumb_opcode) \
+	__inst_thumb32(thumb_opcode)
+#else
+#define __inst_arm_thumb16(arm_opcode, thumb_opcode) __inst_arm(arm_opcode)
+#define __inst_arm_thumb32(arm_opcode, thumb_opcode) __inst_arm(arm_opcode)
+#endif
+
+/* Helpers for the helpers.  Don't use these directly. */
+#ifdef __ASSEMBLY__
+#define ___inst_arm(x) .long x
+#define ___inst_thumb16(x) .short x
+#define ___inst_thumb32(first, second) .short first, second
+#else
+#define ___inst_arm(x) ".long " __stringify(x) "\n\t"
+#define ___inst_thumb16(x) ".short " __stringify(x) "\n\t"
+#define ___inst_thumb32(first, second) \
+	".short " __stringify(first) ", " __stringify(second) "\n\t"
+#endif
+
+#endif /* __ASM_ARM_OPCODES_H */
-- 
2.16.1



From sam at ravnborg.org  Sat Mar 24 03:06:03 2018
From: sam at ravnborg.org (Sam Ravnborg)
Date: Sat, 24 Mar 2018 11:06:03 +0100
Subject: [PATCH v2 02/10] ARM: safely switch from HYP to SVC mode if
 required
In-Reply-To: <20180323231422.21137-2-l.stach@pengutronix.de>
References: <20180323231422.21137-1-l.stach@pengutronix.de>
 <20180323231422.21137-2-l.stach@pengutronix.de>
Message-ID: <20180324100603.GA3784@ravnborg.org>

On Sat, Mar 24, 2018 at 12:14:14AM +0100, Lucas Stach wrote:
> This is a port of the Linux safe_svcmode_maskall macro to
> the Barebox lowlevel init.
> 
> Signed-off-by: Lucas Stach <l.stach at pengutronix.de>
> ---
>  arch/arm/cpu/lowlevel.S       | 20 ++++++++++++++++----
>  arch/arm/include/asm/system.h | 26 ++++++++++++++++++++++++++
>  2 files changed, 42 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm/cpu/lowlevel.S b/arch/arm/cpu/lowlevel.S
> index 7696a198e764..194ce0e7c274 100644
> --- a/arch/arm/cpu/lowlevel.S
> +++ b/arch/arm/cpu/lowlevel.S
> @@ -1,16 +1,28 @@
>  #include <linux/linkage.h>
>  #include <init.h>
>  #include <asm/system.h>
> +#include <asm/opcodes-virt.h>
>  
>  .section ".text_bare_init_","ax"
>  ENTRY(arm_cpu_lowlevel_init)
>  	/* save lr, since it may be banked away with a processor mode change */
>  	mov	r2, lr
> +
>  	/* set the cpu to SVC32 mode, mask irq and fiq */
> -	mrs	r12, cpsr
> -	bic	r12, r12, #0x1f
> -	orr	r12, r12, #0xd3
> -	msr	cpsr, r12
> +	mrs	r12 , cpsr
                   ^ extra space

> +	eor	r12, r12, #HYP_MODE
> +	tst	r12, #MODE_MASK
> +	bic	r12 , r12 , #MODE_MASK
                   ^ extra space
> +	orr	r12 , r12 , #(PSR_I_BIT | PSR_F_BIT | SVC_MODE)
                   ^extra sapce
> +THUMB(	orr	r12 , r12 , #PSR_T_BIT	)
                           ^ extra space

If there is a "rule" about the extra space then I have missed it

	Sam


From sam at ravnborg.org  Sat Mar 24 03:10:19 2018
From: sam at ravnborg.org (Sam Ravnborg)
Date: Sat, 24 Mar 2018 11:10:19 +0100
Subject: [PATCH v2 04/10] ARM: add file for HYP mode related setup
In-Reply-To: <20180323231422.21137-4-l.stach@pengutronix.de>
References: <20180323231422.21137-1-l.stach@pengutronix.de>
 <20180323231422.21137-4-l.stach@pengutronix.de>
Message-ID: <20180324101019.GB3784@ravnborg.org>

On Sat, Mar 24, 2018 at 12:14:16AM +0100, Lucas Stach wrote:
> This adds routines to add hyp mode vectors and switch back to HYP
> mode from SVC. This is needed in both the PBL and Barebox proper.
> 
> Signed-off-by: Lucas Stach <l.stach at pengutronix.de>
> ---
>  arch/arm/cpu/Makefile         |   4 ++
>  arch/arm/cpu/hyp.S            | 115 ++++++++++++++++++++++++++++++++++++++++++
>  arch/arm/cpu/sm_as.S          |  11 ----
>  arch/arm/include/asm/secure.h |   8 +++
>  4 files changed, 127 insertions(+), 11 deletions(-)
>  create mode 100644 arch/arm/cpu/hyp.S
> 
> diff --git a/arch/arm/cpu/Makefile b/arch/arm/cpu/Makefile
> index 13fe12c31f6f..f86dff975bb4 100644
> --- a/arch/arm/cpu/Makefile
> +++ b/arch/arm/cpu/Makefile
> @@ -9,6 +9,10 @@ obj-$(CONFIG_ARM_EXCEPTIONS) += exceptions.o
>  obj-$(CONFIG_MMU) += mmu.o mmu-early.o
>  pbl-$(CONFIG_MMU) += mmu-early.o
>  lwl-y += lowlevel.o
> +obj-y += hyp.o
> +AFLAGS_hyp.o :=-Wa,-march=armv7-a -Wa,-mcpu=all
> +pbl-y += hyp.o
> +AFLAGS_pbl-hyp.o :=-Wa,-march=armv7-a -Wa,-mcpu=all
>  endif
>  
>  obj-$(CONFIG_ARM_EXCEPTIONS) += interrupts.o
> diff --git a/arch/arm/cpu/hyp.S b/arch/arm/cpu/hyp.S
> new file mode 100644
> index 000000000000..435d416f980a
> --- /dev/null
> +++ b/arch/arm/cpu/hyp.S
> @@ -0,0 +1,115 @@
> +#include <linux/linkage.h>
> +#include <asm/system.h>
> +#include <asm/opcodes-virt.h>
> +
> +.arch_extension sec
> +.arch_extension virt
> +
> +.section ".text_bare_init_","ax"
Here you could use __BARE_INIT - from init.h

	Sam


From sam at ravnborg.org  Sat Mar 24 03:13:14 2018
From: sam at ravnborg.org (Sam Ravnborg)
Date: Sat, 24 Mar 2018 11:13:14 +0100
Subject: [PATCH v2 08/10] ARM: rpi: add revision IDs for Pi 3 Model B and
 Pi Zero
In-Reply-To: <20180323231422.21137-8-l.stach@pengutronix.de>
References: <20180323231422.21137-1-l.stach@pengutronix.de>
 <20180323231422.21137-8-l.stach@pengutronix.de>
Message-ID: <20180324101314.GC3784@ravnborg.org>

On Sat, Mar 24, 2018 at 12:14:20AM +0100, Lucas Stach wrote:
> From: Enrico Joerns <ejo at pengutronix.de>
> 
> Signed-off-by: Enrico Joerns <ejo at pengutronix.de>
> ---
This patch is authored by Enrico but enters the tree via Lucas.
So there is a Signed-off-by: missing for Lucas here.

	Sam


From antonynpavlov at gmail.com  Mon Mar 26 00:20:37 2018
From: antonynpavlov at gmail.com (Antony Pavlov)
Date: Mon, 26 Mar 2018 10:20:37 +0300
Subject: socfpga: ethernet problem
Message-ID: <20180326102037.57959f6175c61967d9e9c5b4@gmail.com>

Hi!

Barebox for DE0-Nano-SoC succesfully starts on Terasic DE10-Nano board
but there is an ethernet issue.

After `make ARCH=arm socfpga_defconfig` I see that the CONFIG_DRIVER_NET_DESIGNWARE_SOCFPGA
option is disabled.

  #
  # Network drivers
  #
  ...
  CONFIG_DRIVER_NET_DESIGNWARE=y
  # CONFIG_DRIVER_NET_DESIGNWARE_GENERIC is not set
  # CONFIG_DRIVER_NET_DESIGNWARE_SOCFPGA is not set

after enabling CONFIG_DRIVER_NET_DESIGNWARE_SOCFPGA I see 'Could not get sysmgr-syscon node'
error message:


  barebox 2018.03.0-00408-g5b07a6b67d #5 Sat Mar 24 19:50:00 MSK 2018


  Board: Terasic DE0-Nano-SoC/Atlas-SoC Kit
  socfpga_designware_eth ff702000.ethernet: user ID: 0x10, Synopsys ID: 0x37
  mdio_bus: miibus0: probed
  WARNING: at include/linux/reset.h:43/reset_control_get()!
  socfpga_designware_eth ff702000.ethernet: Could not get sysmgr-syscon node
  socfpga_designware_eth ff702000.ethernet: probe failed: Function not implemented
  dw_mmc ff704000.dwmmc0: registered as ff704000.dwmmc0
  netconsole: registered as netconsole-1
  malloc space: 0x1fefd9c0 -> 0x3fdfb37f (size 511 MiB)
  mmc0: detected SD card version 2.0
  mmc0: registered mmc0
  environment load /boot/barebox.env: No such file or directory
  Maybe you have to create the partition.
  running /env/bin/init...

  Hit any key to stop autoboot:    3
  barebox at Terasic DE0-Nano-SoC/Atlas-SoC Kit:/


Any suggestions or comments, please?

-- 
Best regards,
? Antony Pavlov


From s.hauer at pengutronix.de  Mon Mar 26 00:23:46 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Mon, 26 Mar 2018 09:23:46 +0200
Subject: [PATCH 0/4] i.MX53/TX53: rework to dts, fix and add samsung
 variant
In-Reply-To: <20180323084352.20931-1-m.grzeschik@pengutronix.de>
References: <20180323084352.20931-1-m.grzeschik@pengutronix.de>
Message-ID: <20180326072346.37bc425jui75vrad@pengutronix.de>

On Fri, Mar 23, 2018 at 09:43:48AM +0100, Michael Grzeschik wrote:
> This series fixes the imx-usb-loader based boot of the revxx30.
> It also reworks the whole platform to dts and adds the new
> samsung based xx30 platform.
> 
> Juergen reworked the interpreter logic description on the way.
> Don't know if we should send this seperatly. For now it is
> included in this series, as the new samsung based platform
> was not tested without.

Applied, thanks

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From s.hauer at pengutronix.de  Mon Mar 26 00:25:24 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Mon, 26 Mar 2018 09:25:24 +0200
Subject: [PATCH] video: tc358767: set num_modes=0 if no valid mode found
In-Reply-To: <1521825143-9979-1-git-send-email-andrey.gusakov@cogentembedded.com>
References: <1521825143-9979-1-git-send-email-andrey.gusakov@cogentembedded.com>
Message-ID: <20180326072524.tated4gxccrlemgg@pengutronix.de>

On Fri, Mar 23, 2018 at 08:12:23PM +0300, Andrey Gusakov wrote:
> Since commit f986661 "video: ipu: register framebuffer,
> even when no modes are found" value returned from
> VPL_GET_VIDEOMODES ioctl is ignored. So set valid num_modes
> in error case to avoid crash in register_framebuffer.
> 
> Signed-off-by: Andrey Gusakov <andrey.gusakov at cogentembedded.com>
> ---
>  drivers/video/tc358767.c | 1 +
>  1 file changed, 1 insertion(+)

Applied, thanks

Sascha

> 
> diff --git a/drivers/video/tc358767.c b/drivers/video/tc358767.c
> index 5ad5cb4..d4749b1 100644
> --- a/drivers/video/tc358767.c
> +++ b/drivers/video/tc358767.c
> @@ -1258,6 +1258,7 @@ static int tc_filter_videomodes(struct tc_data *tc, struct display_timings *timi
>  	} while (1);
>  
>  	free(timings->modes);
> +	timings->num_modes = 0;
>  	timings->modes = NULL;
>  
>  	if (!num_modes) {
> -- 
> 1.9.1
> 
> 

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From r.hieber at pengutronix.de  Mon Mar 26 02:31:42 2018
From: r.hieber at pengutronix.de (Roland Hieber)
Date: Mon, 26 Mar 2018 11:31:42 +0200
Subject: [PATCH] doc: bcm283x: update documentation for Raspberry Pi
In-Reply-To: <20180206085229.g2isjcnbioa7xk7k@pengutronix.de>
References: <20180130112523.20258-1-r.hieber@pengutronix.de>
 <20180206085229.g2isjcnbioa7xk7k@pengutronix.de>
Message-ID: <3d280e5b-7a74-16cf-5b09-eecb87d35a84@pengutronix.de>

On 06.02.2018 09:52, Sascha Hauer wrote:
> On Tue, Jan 30, 2018 at 12:25:23PM +0100, Roland Hieber wrote:
>> The old way does not seem to work for RPi 3, as the UART pins are
>> mapped differently and the NOOBS bootcode does not seem to read a
>> config.txt.
>>
>> Signed-off-by: Roland Hieber <r.hieber at pengutronix.de>
>> ---
>>   Documentation/boards/bcm2835.rst | 34 ++++++++++++++++++++++++++--------
>>   1 file changed, 26 insertions(+), 8 deletions(-)
> 
> Applied, thanks
> 
> Sascha

I do not see this one in current master (ca880912a4). Did it get lost?

  - Roland

>>
>> diff --git a/Documentation/boards/bcm2835.rst b/Documentation/boards/bcm2835.rst
>> index 13cebb01c4..1a78cfba3c 100644
>> --- a/Documentation/boards/bcm2835.rst
>> +++ b/Documentation/boards/bcm2835.rst
>> @@ -1,17 +1,35 @@
>> -Broadcom BCM2835
>> +Broadcom BCM283x
>>   ================
>>   
>>   Raspberry Pi
>>   ------------
>>   
>> -  1. Prepare a card with a FAT filesystem. Download a tiny NOOBS LITE
>> -     zip archive and unpack it into FAT partition.
>> -     See http://www.raspberrypi.org/help/noobs-setup/ for details.
>> +  1. Prepare an SD or microSD card with a FAT filesystem of at least 30 MB in size.
>> +
>> +  2. Download the `Raspberry Pi firmware`_ (120 MB), unzip it, and copy the
>> +     contents of the ``boot/`` folder to your card.
>>   
>> -  2. Compile ``barebox.bin`` image (use ``rpi_defconfig``).
>> -     Copy it to the SD/microSD card and name it ``recovery.img``.
>> +  3. Use ``make rpi_defconfig; make`` to build barebox. This will create the following images:
>>   
>> -  3. Connect to board's UART (115200 8N1);
>> +     - ``images/barebox-raspberry-pi-1.img`` for the BCM2835/ARM1176JZF-S (Raspberry Pi 1)
>> +     - ``images/barebox-raspberry-pi-2.img`` for the BCM2836/CORTEX-A7 (Raspberry Pi 2)
>> +     - ``images/barebox-raspberry-pi-3.img`` for the BCM2837/CORTEX-A53 (Raspberry Pi 3, Raspberry Pi Zero)
>> +
>> +     Copy the respective image for your model to your SD card and name it
>> +     ``barebox.img``.
>> +
>> +  4. Create a text file ``config.txt`` on the SD card with the following content::
>> +
>> +         kernel=barebox.img
>> +         enable_uart=1
>> +         dtoverlay=pi3-miniuart-bt
>> +
>> +     (For more information, refer to the `documentation for config.txt`_.)
>> +
>> +  5. Connect to board's UART (115200 8N1);
>>        Use PIN6 (GND), PIN8 (UART_TX), PIN10 (UART_RX) pins.
>>   
>> -  4. Turn board's power on.
>> +  6. Turn board's power on.
>> +
>> +.. _Raspberry Pi firmware: https://codeload.github.com/raspberrypi/firmware/zip/80e1fbeb78f9df06701d28c0ed3a3060a3f557ef
>> +.. _documentation for config.txt: https://www.raspberrypi.org/documentation/configuration/config-txt/
>> -- 
>> 2.11.0
>>
>>
>> _______________________________________________
>> barebox mailing list
>> barebox at lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/barebox
>>
> 

-- 
Pengutronix e.K.                  | Roland Hieber               |
Industrial Linux Solutions        | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim | Phone: +49-5121-206917-5086 |
Amtsgericht Hildesheim, HRA 2686  | Fax:   +49-5121-206917-5555 |


From r.hieber at pengutronix.de  Mon Mar 26 03:06:40 2018
From: r.hieber at pengutronix.de (Roland Hieber)
Date: Mon, 26 Mar 2018 12:06:40 +0200
Subject: [PATCH v2 01/10] ARM: import opcode helpers from Linux kernel
In-Reply-To: <20180323231422.21137-1-l.stach@pengutronix.de>
References: <20180323231422.21137-1-l.stach@pengutronix.de>
Message-ID: <f7fbf670-4b5e-063a-1dd8-5b1400800b57@pengutronix.de>

Hmm. I don't see any sdhci driver being loaded on RPi 2, resulting in no 
SD Card. But this is probably not related to the changes in this series.

Otherwise, as for v1:

Tested-on: bcm2835-rpi, bcm2836-rpi-2, bcm2837-rpi-3
Tested-by: Roland Hieber <r.hieber at pengutronix.de>

On 24.03.2018 00:14, Lucas Stach wrote:
> Those are needed to generate some of the ARM SEC and VIRT
> opcodes in a portable way.
> 
> Signed-off-by: Lucas Stach <l.stach at pengutronix.de>
> ---
>   arch/arm/include/asm/opcodes-virt.h |  39 ++++++
>   arch/arm/include/asm/opcodes.h      | 231 ++++++++++++++++++++++++++++++++++++
>   2 files changed, 270 insertions(+)
>   create mode 100644 arch/arm/include/asm/opcodes-virt.h
>   create mode 100644 arch/arm/include/asm/opcodes.h
> 
> diff --git a/arch/arm/include/asm/opcodes-virt.h b/arch/arm/include/asm/opcodes-virt.h
> new file mode 100644
> index 000000000000..efcfdf92d9d5
> --- /dev/null
> +++ b/arch/arm/include/asm/opcodes-virt.h
> @@ -0,0 +1,39 @@
> +/*
> + * opcodes-virt.h: Opcode definitions for the ARM virtualization extensions
> + * Copyright (C) 2012  Linaro Limited
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License along
> + * with this program; if not, write to the Free Software Foundation, Inc.,
> + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
> + */
> +#ifndef __ASM_ARM_OPCODES_VIRT_H
> +#define __ASM_ARM_OPCODES_VIRT_H
> +
> +#include <asm/opcodes.h>
> +
> +#define __HVC(imm16) __inst_arm_thumb32(				\
> +	0xE1400070 | (((imm16) & 0xFFF0) << 4) | ((imm16) & 0x000F),	\
> +	0xF7E08000 | (((imm16) & 0xF000) << 4) | ((imm16) & 0x0FFF)	\
> +)
> +
> +#define __ERET	__inst_arm_thumb32(					\
> +	0xE160006E,							\
> +	0xF3DE8F00							\
> +)
> +
> +#define __MSR_ELR_HYP(regnum)	__inst_arm_thumb32(			\
> +	0xE12EF300 | regnum,						\
> +	0xF3808E30 | (regnum << 16)					\
> +)
> +
> +#endif /* ! __ASM_ARM_OPCODES_VIRT_H */
> diff --git a/arch/arm/include/asm/opcodes.h b/arch/arm/include/asm/opcodes.h
> new file mode 100644
> index 000000000000..a78bf5d2c518
> --- /dev/null
> +++ b/arch/arm/include/asm/opcodes.h
> @@ -0,0 +1,231 @@
> +/*
> + *  arch/arm/include/asm/opcodes.h
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#ifndef __ASM_ARM_OPCODES_H
> +#define __ASM_ARM_OPCODES_H
> +
> +#ifndef __ASSEMBLY__
> +#include <linux/linkage.h>
> +extern asmlinkage unsigned int arm_check_condition(u32 opcode, u32 psr);
> +#endif
> +
> +#define ARM_OPCODE_CONDTEST_FAIL   0
> +#define ARM_OPCODE_CONDTEST_PASS   1
> +#define ARM_OPCODE_CONDTEST_UNCOND 2
> +
> +
> +/*
> + * Assembler opcode byteswap helpers.
> + * These are only intended for use by this header: don't use them directly,
> + * because they will be suboptimal in most cases.
> + */
> +#define ___asm_opcode_swab32(x) (	\
> +	  (((x) << 24) & 0xFF000000)	\
> +	| (((x) <<  8) & 0x00FF0000)	\
> +	| (((x) >>  8) & 0x0000FF00)	\
> +	| (((x) >> 24) & 0x000000FF)	\
> +)
> +#define ___asm_opcode_swab16(x) (	\
> +	  (((x) << 8) & 0xFF00)		\
> +	| (((x) >> 8) & 0x00FF)		\
> +)
> +#define ___asm_opcode_swahb32(x) (	\
> +	  (((x) << 8) & 0xFF00FF00)	\
> +	| (((x) >> 8) & 0x00FF00FF)	\
> +)
> +#define ___asm_opcode_swahw32(x) (	\
> +	  (((x) << 16) & 0xFFFF0000)	\
> +	| (((x) >> 16) & 0x0000FFFF)	\
> +)
> +#define ___asm_opcode_identity32(x) ((x) & 0xFFFFFFFF)
> +#define ___asm_opcode_identity16(x) ((x) & 0xFFFF)
> +
> +
> +/*
> + * Opcode byteswap helpers
> + *
> + * These macros help with converting instructions between a canonical integer
> + * format and in-memory representation, in an endianness-agnostic manner.
> + *
> + * __mem_to_opcode_*() convert from in-memory representation to canonical form.
> + * __opcode_to_mem_*() convert from canonical form to in-memory representation.
> + *
> + *
> + * Canonical instruction representation:
> + *
> + *	ARM:		0xKKLLMMNN
> + *	Thumb 16-bit:	0x0000KKLL, where KK < 0xE8
> + *	Thumb 32-bit:	0xKKLLMMNN, where KK >= 0xE8
> + *
> + * There is no way to distinguish an ARM instruction in canonical representation
> + * from a Thumb instruction (just as these cannot be distinguished in memory).
> + * Where this distinction is important, it needs to be tracked separately.
> + *
> + * Note that values in the range 0x0000E800..0xE7FFFFFF intentionally do not
> + * represent any valid Thumb-2 instruction.  For this range,
> + * __opcode_is_thumb32() and __opcode_is_thumb16() will both be false.
> + *
> + * The ___asm variants are intended only for use by this header, in situations
> + * involving inline assembler.  For .S files, the normal __opcode_*() macros
> + * should do the right thing.
> + */
> +#ifdef __ASSEMBLY__
> +
> +#define ___opcode_swab32(x) ___asm_opcode_swab32(x)
> +#define ___opcode_swab16(x) ___asm_opcode_swab16(x)
> +#define ___opcode_swahb32(x) ___asm_opcode_swahb32(x)
> +#define ___opcode_swahw32(x) ___asm_opcode_swahw32(x)
> +#define ___opcode_identity32(x) ___asm_opcode_identity32(x)
> +#define ___opcode_identity16(x) ___asm_opcode_identity16(x)
> +
> +#else /* ! __ASSEMBLY__ */
> +
> +#include <linux/types.h>
> +#include <linux/swab.h>
> +
> +#define ___opcode_swab32(x) swab32(x)
> +#define ___opcode_swab16(x) swab16(x)
> +#define ___opcode_swahb32(x) swahb32(x)
> +#define ___opcode_swahw32(x) swahw32(x)
> +#define ___opcode_identity32(x) ((u32)(x))
> +#define ___opcode_identity16(x) ((u16)(x))
> +
> +#endif /* ! __ASSEMBLY__ */
> +
> +
> +#ifdef CONFIG_CPU_ENDIAN_BE8
> +
> +#define __opcode_to_mem_arm(x) ___opcode_swab32(x)
> +#define __opcode_to_mem_thumb16(x) ___opcode_swab16(x)
> +#define __opcode_to_mem_thumb32(x) ___opcode_swahb32(x)
> +#define ___asm_opcode_to_mem_arm(x) ___asm_opcode_swab32(x)
> +#define ___asm_opcode_to_mem_thumb16(x) ___asm_opcode_swab16(x)
> +#define ___asm_opcode_to_mem_thumb32(x) ___asm_opcode_swahb32(x)
> +
> +#else /* ! CONFIG_CPU_ENDIAN_BE8 */
> +
> +#define __opcode_to_mem_arm(x) ___opcode_identity32(x)
> +#define __opcode_to_mem_thumb16(x) ___opcode_identity16(x)
> +#define ___asm_opcode_to_mem_arm(x) ___asm_opcode_identity32(x)
> +#define ___asm_opcode_to_mem_thumb16(x) ___asm_opcode_identity16(x)
> +#ifndef CONFIG_CPU_ENDIAN_BE32
> +/*
> + * On BE32 systems, using 32-bit accesses to store Thumb instructions will not
> + * work in all cases, due to alignment constraints.  For now, a correct
> + * version is not provided for BE32.
> + */
> +#define __opcode_to_mem_thumb32(x) ___opcode_swahw32(x)
> +#define ___asm_opcode_to_mem_thumb32(x) ___asm_opcode_swahw32(x)
> +#endif
> +
> +#endif /* ! CONFIG_CPU_ENDIAN_BE8 */
> +
> +#define __mem_to_opcode_arm(x) __opcode_to_mem_arm(x)
> +#define __mem_to_opcode_thumb16(x) __opcode_to_mem_thumb16(x)
> +#ifndef CONFIG_CPU_ENDIAN_BE32
> +#define __mem_to_opcode_thumb32(x) __opcode_to_mem_thumb32(x)
> +#endif
> +
> +/* Operations specific to Thumb opcodes */
> +
> +/* Instruction size checks: */
> +#define __opcode_is_thumb32(x) (		\
> +	   ((x) & 0xF8000000) == 0xE8000000	\
> +	|| ((x) & 0xF0000000) == 0xF0000000	\
> +)
> +#define __opcode_is_thumb16(x) (					\
> +	   ((x) & 0xFFFF0000) == 0					\
> +	&& !(((x) & 0xF800) == 0xE800 || ((x) & 0xF000) == 0xF000)	\
> +)
> +
> +/* Operations to construct or split 32-bit Thumb instructions: */
> +#define __opcode_thumb32_first(x) (___opcode_identity16((x) >> 16))
> +#define __opcode_thumb32_second(x) (___opcode_identity16(x))
> +#define __opcode_thumb32_compose(first, second) (			\
> +	  (___opcode_identity32(___opcode_identity16(first)) << 16)	\
> +	| ___opcode_identity32(___opcode_identity16(second))		\
> +)
> +#define ___asm_opcode_thumb32_first(x) (___asm_opcode_identity16((x) >> 16))
> +#define ___asm_opcode_thumb32_second(x) (___asm_opcode_identity16(x))
> +#define ___asm_opcode_thumb32_compose(first, second) (			    \
> +	  (___asm_opcode_identity32(___asm_opcode_identity16(first)) << 16) \
> +	| ___asm_opcode_identity32(___asm_opcode_identity16(second))	    \
> +)
> +
> +/*
> + * Opcode injection helpers
> + *
> + * In rare cases it is necessary to assemble an opcode which the
> + * assembler does not support directly, or which would normally be
> + * rejected because of the CFLAGS or AFLAGS used to build the affected
> + * file.
> + *
> + * Before using these macros, consider carefully whether it is feasible
> + * instead to change the build flags for your file, or whether it really
> + * makes sense to support old assembler versions when building that
> + * particular kernel feature.
> + *
> + * The macros defined here should only be used where there is no viable
> + * alternative.
> + *
> + *
> + * __inst_arm(x): emit the specified ARM opcode
> + * __inst_thumb16(x): emit the specified 16-bit Thumb opcode
> + * __inst_thumb32(x): emit the specified 32-bit Thumb opcode
> + *
> + * __inst_arm_thumb16(arm, thumb): emit either the specified arm or
> + *	16-bit Thumb opcode, depending on whether an ARM or Thumb-2
> + *	kernel is being built
> + *
> + * __inst_arm_thumb32(arm, thumb): emit either the specified arm or
> + *	32-bit Thumb opcode, depending on whether an ARM or Thumb-2
> + *	kernel is being built
> + *
> + *
> + * Note that using these macros directly is poor practice.  Instead, you
> + * should use them to define human-readable wrapper macros to encode the
> + * instructions that you care about.  In code which might run on ARMv7 or
> + * above, you can usually use the __inst_arm_thumb{16,32} macros to
> + * specify the ARM and Thumb alternatives at the same time.  This ensures
> + * that the correct opcode gets emitted depending on the instruction set
> + * used for the kernel build.
> + *
> + * Look at opcodes-virt.h for an example of how to use these macros.
> + */
> +#include <linux/stringify.h>
> +
> +#define __inst_arm(x) ___inst_arm(___asm_opcode_to_mem_arm(x))
> +#define __inst_thumb32(x) ___inst_thumb32(				\
> +	___asm_opcode_to_mem_thumb16(___asm_opcode_thumb32_first(x)),	\
> +	___asm_opcode_to_mem_thumb16(___asm_opcode_thumb32_second(x))	\
> +)
> +#define __inst_thumb16(x) ___inst_thumb16(___asm_opcode_to_mem_thumb16(x))
> +
> +#ifdef CONFIG_THUMB2_BAREBOX
> +#define __inst_arm_thumb16(arm_opcode, thumb_opcode) \
> +	__inst_thumb16(thumb_opcode)
> +#define __inst_arm_thumb32(arm_opcode, thumb_opcode) \
> +	__inst_thumb32(thumb_opcode)
> +#else
> +#define __inst_arm_thumb16(arm_opcode, thumb_opcode) __inst_arm(arm_opcode)
> +#define __inst_arm_thumb32(arm_opcode, thumb_opcode) __inst_arm(arm_opcode)
> +#endif
> +
> +/* Helpers for the helpers.  Don't use these directly. */
> +#ifdef __ASSEMBLY__
> +#define ___inst_arm(x) .long x
> +#define ___inst_thumb16(x) .short x
> +#define ___inst_thumb32(first, second) .short first, second
> +#else
> +#define ___inst_arm(x) ".long " __stringify(x) "\n\t"
> +#define ___inst_thumb16(x) ".short " __stringify(x) "\n\t"
> +#define ___inst_thumb32(first, second) \
> +	".short " __stringify(first) ", " __stringify(second) "\n\t"
> +#endif
> +
> +#endif /* __ASM_ARM_OPCODES_H */
> 

-- 
Pengutronix e.K.                  | Roland Hieber               |
Industrial Linux Solutions        | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim | Phone: +49-5121-206917-5086 |
Amtsgericht Hildesheim, HRA 2686  | Fax:   +49-5121-206917-5555 |


From andrew.smirnov at gmail.com  Mon Mar 26 06:09:12 2018
From: andrew.smirnov at gmail.com (Andrey Smirnov)
Date: Mon, 26 Mar 2018 06:09:12 -0700
Subject: [PATCH 0/3] Linux's serdev framwork port
Message-ID: <20180326130915.8726-1-andrew.smirnov@gmail.com>

Hi everyone:

In an effort to bring this kernel driver
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/mfd/rave-sp.c?h=v4.16-rc7
to Barebox, I ended up creating a miniature and extremely simplified
version of 'serdev' subsystem which is presented in this patchset.

All feedback is wellcome!

Thanks,
Andrey Smirnov

Andrey Smirnov (3):
  console: Introduce console_drain()
  console: Add simplified 'serdev' framework from Linux kernel
  serial: Check result of console_unregister()

 common/Kconfig                   |   6 +++
 common/Makefile                  |   1 +
 common/console.c                 |  24 +++++++--
 common/serdev.c                  |  87 ++++++++++++++++++++++++++++++
 drivers/serial/serial_auart.c    |   6 ++-
 drivers/serial/serial_cadence.c  |   6 ++-
 drivers/serial/serial_clps711x.c |   6 ++-
 drivers/serial/serial_imx.c      |   6 ++-
 drivers/serial/serial_lpuart.c   |   6 ++-
 drivers/serial/serial_pxa.c      |   6 ++-
 drivers/serial/serial_s3c.c      |   6 ++-
 drivers/serial/stm-serial.c      |   6 ++-
 include/console.h                | 112 ++++++++++++++++++++++++++++++++++++++-
 include/serdev.h                 |  36 +++++++++++++
 lib/xymodem.c                    |  30 ++---------
 15 files changed, 307 insertions(+), 37 deletions(-)
 create mode 100644 common/serdev.c
 create mode 100644 include/serdev.h

-- 
2.14.3



From andrew.smirnov at gmail.com  Mon Mar 26 06:09:13 2018
From: andrew.smirnov at gmail.com (Andrey Smirnov)
Date: Mon, 26 Mar 2018 06:09:13 -0700
Subject: [PATCH 1/3] console: Introduce console_drain()
In-Reply-To: <20180326130915.8726-1-andrew.smirnov@gmail.com>
References: <20180326130915.8726-1-andrew.smirnov@gmail.com>
Message-ID: <20180326130915.8726-2-andrew.smirnov@gmail.com>

Generalize high baud rate UART polling code found in lib/xmodem.c and
expose it as a generic function in console API.

The usecase for this -- besides X/Y-mode data transfers where the code
originated -- is command/reply type of serial exchages at high baud
rates (~1Mbaud) with payloads exceeding inernal UART FIFOs in
size. Such interactions are not uncommon in serdev device and this
patch is done in preparation for serdev support code that will follow.

Signed-off-by: Andrey Smirnov <andrew.smirnov at gmail.com>
---
 include/console.h | 83 +++++++++++++++++++++++++++++++++++++++++++++++++++++++
 lib/xymodem.c     | 30 ++++----------------
 2 files changed, 88 insertions(+), 25 deletions(-)

diff --git a/include/console.h b/include/console.h
index 724168e07..4aa4c8f9e 100644
--- a/include/console.h
+++ b/include/console.h
@@ -23,6 +23,7 @@
 #include <param.h>
 #include <linux/list.h>
 #include <driver.h>
+#include <clock.h>
 
 #define CONSOLE_STDIN           (1 << 0)
 #define CONSOLE_STDOUT          (1 << 1)
@@ -88,6 +89,88 @@ unsigned console_get_active(struct console_device *cdev);
 int console_set_baudrate(struct console_device *cdev, unsigned baudrate);
 unsigned console_get_baudrate(struct console_device *cdev);
 
+
+/**
+ * console_fifo_fill - fill FIFO with as much console data as possible
+ *
+ * @cdev:	Console to poll for dat
+ * @fifo:	FIFO to store the data in
+ */
+static inline int console_fifo_fill(struct console_device *cdev,
+				    struct kfifo *fifo)
+{
+	size_t len = kfifo_len(fifo);
+	while (cdev->tstc(cdev) && len < fifo->size) {
+		kfifo_putc(fifo, (unsigned char)(cdev->getc(cdev)));
+		len++;
+	}
+
+	return len;
+}
+
+/**
+ * __console_drain - Drain console into a buffer via FIFO
+ *
+ * @__is_timeout	Callback used to determine timeout condition
+ * @cdev		Console to drain
+ * @fifo		FIFO to use as a transient buffer
+ * @buf			Buffer to drain console into
+ * @len			Size of the drain buffer
+ * @timeout		Console polling timeout in ns
+ *
+ * This function is optimized to :
+ * - maximize throughput (ie. read as much as is available in lower layer fifo)
+ * - minimize latencies (no delay or wait timeout if data available)
+ * - have a timeout
+ * This is why standard getc() is not used, and input_fifo_fill() exists.
+ */
+static inline int __console_drain(int (*__is_timeout)(uint64_t start_ns,
+						      uint64_t time_offset_ns),
+				  struct console_device *cdev,
+				  struct kfifo *fifo,
+				  unsigned char *buf,
+				  int len,
+				  uint64_t timeout)
+{
+	int i = 0;
+	uint64_t start = get_time_ns();
+
+	if (!len)
+		return -EINVAL;
+
+	do {
+		/*
+		 * To minimize wait time before we start polling Rx
+		 * (to potentially avoid overruning Rx FIFO) we call
+		 * console_fifo_fill first
+		 */
+		if (console_fifo_fill(cdev, fifo))
+			kfifo_getc(fifo, &buf[i++]);
+
+	} while (i < len && !__is_timeout(start, timeout));
+
+	return i;
+}
+
+static inline int console_drain_non_interruptible(struct console_device *cdev,
+						  struct kfifo *fifo,
+						  unsigned char *buf,
+						  int len,
+						  uint64_t timeout)
+{
+	return __console_drain(is_timeout_non_interruptible,
+			       cdev, fifo, buf, len, timeout);
+}
+
+static inline int console_drain(struct console_device *cdev,
+				struct kfifo *fifo,
+				unsigned char *buf,
+				int len,
+				uint64_t timeout)
+{
+	return __console_drain(is_timeout, cdev, fifo, buf, len, timeout);
+}
+
 #ifdef CONFIG_PBL_CONSOLE
 void pbl_set_putc(void (*putcf)(void *ctx, int c), void *ctx);
 #else
diff --git a/lib/xymodem.c b/lib/xymodem.c
index a6c4d3cd5..ff052ef8f 100644
--- a/lib/xymodem.c
+++ b/lib/xymodem.c
@@ -146,36 +146,16 @@ static const char block_nack[MAX_PROTOS][MAX_CRCS] = {
 	{ 0, 0, 0 },		/* YMODEM-G */
 };
 
-static int input_fifo_fill(struct console_device *cdev, struct kfifo *fifo)
-{
-	while (cdev->tstc(cdev) && kfifo_len(fifo) < INPUT_FIFO_SIZE)
-		kfifo_putc(fifo, (unsigned char)(cdev->getc(cdev)));
-	return kfifo_len(fifo);
-}
-
-/*
- * This function is optimized to :
- * - maximize throughput (ie. read as much as is available in lower layer fifo)
- * - minimize latencies (no delay or wait timeout if data available)
- * - have a timeout
- * This is why standard getc() is not used, and input_fifo_fill() exists.
- */
 static int xy_gets(struct console_device *cdev, struct kfifo *fifo,
 		      unsigned char *buf, int len, uint64_t timeout)
 {
-	int i, rc;
-	uint64_t start = get_time_ns();
+	int rc;
 
-	for (i = 0, rc = 0; rc >= 0 && i < len; ) {
-		if (is_timeout(start, timeout)) {
-			rc = -ETIMEDOUT;
-			continue;
-		}
-		if (input_fifo_fill(cdev, fifo))
-			kfifo_getc(fifo, &buf[i++]);
-	}
+	rc = console_drain(cdev, fifo, buf, len, timeout);
+	if (rc != len)
+		return -ETIMEDOUT;
 
-	return rc < 0 ? rc : i;
+	return len;
 }
 
 static void xy_putc(struct console_device *cdev, unsigned char c)
-- 
2.14.3



From andrew.smirnov at gmail.com  Mon Mar 26 06:09:15 2018
From: andrew.smirnov at gmail.com (Andrey Smirnov)
Date: Mon, 26 Mar 2018 06:09:15 -0700
Subject: [PATCH 3/3] serial: Check result of console_unregister()
In-Reply-To: <20180326130915.8726-1-andrew.smirnov@gmail.com>
References: <20180326130915.8726-1-andrew.smirnov@gmail.com>
Message-ID: <20180326130915.8726-4-andrew.smirnov@gmail.com>

In order to allow 'serdev' devices to prevent parent console device
removal and correspondign memory deallocation add code to all serial
driver to check result of console_unregister() and bail out early if
it is unsuccessful.

One example of a use-case for this would be a reset handler relying on
a serdev device for transport. Without this patch underlying console
device would be removed and de-allocated before reset handler is even
run thus leading to unpredictable behaviour and crashes.

Signed-off-by: Andrey Smirnov <andrew.smirnov at gmail.com>
---
 drivers/serial/serial_auart.c    | 6 +++++-
 drivers/serial/serial_cadence.c  | 6 +++++-
 drivers/serial/serial_clps711x.c | 6 +++++-
 drivers/serial/serial_imx.c      | 6 +++++-
 drivers/serial/serial_lpuart.c   | 6 +++++-
 drivers/serial/serial_pxa.c      | 6 +++++-
 drivers/serial/serial_s3c.c      | 6 +++++-
 drivers/serial/stm-serial.c      | 6 +++++-
 include/console.h                | 2 +-
 9 files changed, 41 insertions(+), 9 deletions(-)

diff --git a/drivers/serial/serial_auart.c b/drivers/serial/serial_auart.c
index c3b9a1995..9bd0d991e 100644
--- a/drivers/serial/serial_auart.c
+++ b/drivers/serial/serial_auart.c
@@ -224,9 +224,13 @@ static int auart_serial_probe(struct device_d *dev)
 static void auart_serial_remove(struct device_d *dev)
 {
 	struct auart_priv *priv = dev->priv;
+	int ret;
 
 	auart_serial_flush(&priv->cdev);
-	console_unregister(&priv->cdev);
+	ret = console_unregister(&priv->cdev);
+	if (ret < 0)
+		return;
+
 	free(priv);
 }
 
diff --git a/drivers/serial/serial_cadence.c b/drivers/serial/serial_cadence.c
index 36dfa2084..f43d98172 100644
--- a/drivers/serial/serial_cadence.c
+++ b/drivers/serial/serial_cadence.c
@@ -270,8 +270,12 @@ err_free:
 static void cadence_serial_remove(struct device_d *dev)
 {
 	struct cadence_serial_priv *priv = dev->priv;
+	int ret;
+
+	ret = console_unregister(&priv->cdev);
+	if (ret < 0)
+		return;
 
-	console_unregister(&priv->cdev);
 	free(priv);
 }
 
diff --git a/drivers/serial/serial_clps711x.c b/drivers/serial/serial_clps711x.c
index ad14373ac..24ae3fdd3 100644
--- a/drivers/serial/serial_clps711x.c
+++ b/drivers/serial/serial_clps711x.c
@@ -184,9 +184,13 @@ out_err:
 static void clps711x_remove(struct device_d *dev)
 {
 	struct clps711x_uart *s = dev->priv;
+	int ret;
 
 	clps711x_flush(&s->cdev);
-	console_unregister(&s->cdev);
+	ret = console_unregister(&s->cdev);
+	if (ret < 0)
+		return;
+
 	free(s);
 }
 
diff --git a/drivers/serial/serial_imx.c b/drivers/serial/serial_imx.c
index e8c3836a6..fb865f554 100644
--- a/drivers/serial/serial_imx.c
+++ b/drivers/serial/serial_imx.c
@@ -274,9 +274,13 @@ err_free:
 static void imx_serial_remove(struct device_d *dev)
 {
 	struct imx_serial_priv *priv = dev->priv;
+	int ret;
 
 	imx_serial_flush(&priv->cdev);
-	console_unregister(&priv->cdev);
+	ret = console_unregister(&priv->cdev);
+	if (ret < 0)
+		return;
+
 	free(priv);
 }
 
diff --git a/drivers/serial/serial_lpuart.c b/drivers/serial/serial_lpuart.c
index 52fb6d39c..42fab8a56 100644
--- a/drivers/serial/serial_lpuart.c
+++ b/drivers/serial/serial_lpuart.c
@@ -194,9 +194,13 @@ err_free:
 static void lpuart_serial_remove(struct device_d *dev)
 {
 	struct lpuart *lpuart = dev->priv;
+	int ret;
 
 	lpuart_serial_flush(&lpuart->cdev);
-	console_unregister(&lpuart->cdev);
+	ret = console_unregister(&lpuart->cdev);
+	if (ret < 0)
+		return;
+
 	release_region(lpuart->io);
 	clk_put(lpuart->clk);
 
diff --git a/drivers/serial/serial_pxa.c b/drivers/serial/serial_pxa.c
index 1a4d7b430..146f19cf3 100644
--- a/drivers/serial/serial_pxa.c
+++ b/drivers/serial/serial_pxa.c
@@ -188,8 +188,12 @@ static int pxa_serial_probe(struct device_d *dev)
 static void pxa_serial_remove(struct device_d *dev)
 {
 	struct pxa_serial_priv *priv = dev->priv;
+	int ret;
+
+	ret = console_unregister(&priv->cdev);
+	if (ret < 0)
+		return;
 
-	console_unregister(&priv->cdev);
 	free(priv);
 }
 
diff --git a/drivers/serial/serial_s3c.c b/drivers/serial/serial_s3c.c
index 0a6e22d97..8c6443acd 100644
--- a/drivers/serial/serial_s3c.c
+++ b/drivers/serial/serial_s3c.c
@@ -205,9 +205,13 @@ static int s3c_serial_probe(struct device_d *dev)
 static void s3c_serial_remove(struct device_d *dev)
 {
 	struct s3c_uart *priv= dev->priv;
+	int ret;
 
 	s3c_serial_flush(&priv->cdev);
-	console_unregister(&priv->cdev);
+	ret = console_unregister(&priv->cdev);
+	if (ret < 0)
+		return;
+
 	free(priv);
 }
 
diff --git a/drivers/serial/stm-serial.c b/drivers/serial/stm-serial.c
index 83328f455..3edcdd7e8 100644
--- a/drivers/serial/stm-serial.c
+++ b/drivers/serial/stm-serial.c
@@ -185,9 +185,13 @@ static int stm_serial_probe(struct device_d *dev)
 static void stm_serial_remove(struct device_d *dev)
 {
 	struct stm_priv *priv = dev->priv;
+	int ret;
 
 	stm_serial_flush(&priv->cdev);
-	console_unregister(&priv->cdev);
+	ret = console_unregister(&priv->cdev);
+	if (ret < 0)
+		return;
+
 	free(priv);
 }
 
diff --git a/include/console.h b/include/console.h
index 14f00fa1e..3870e67a4 100644
--- a/include/console.h
+++ b/include/console.h
@@ -95,7 +95,7 @@ console_is_serdev_node(struct console_device *cdev)
 }
 
 int console_register(struct console_device *cdev);
-int console_unregister(struct console_device *cdev);
+int __must_check console_unregister(struct console_device *cdev);
 
 struct console_device *console_get_by_dev(struct device_d *dev);
 struct console_device *console_get_by_name(const char *name);
-- 
2.14.3



From andrew.smirnov at gmail.com  Mon Mar 26 06:09:14 2018
From: andrew.smirnov at gmail.com (Andrey Smirnov)
Date: Mon, 26 Mar 2018 06:09:14 -0700
Subject: [PATCH 2/3] console: Add simplified 'serdev' framework from Linux
 kernel
In-Reply-To: <20180326130915.8726-1-andrew.smirnov@gmail.com>
References: <20180326130915.8726-1-andrew.smirnov@gmail.com>
Message-ID: <20180326130915.8726-3-andrew.smirnov@gmail.com>

Port 'serdev' UART-slave deivce framework found in recent Linux
kernels (post 4.13) in order to be able to port 'serdev' slave drivers
from Linux.

Signed-off-by: Andrey Smirnov <andrew.smirnov at gmail.com>
---
 common/Kconfig    |  6 ++++
 common/Makefile   |  1 +
 common/console.c  | 24 +++++++++++++--
 common/serdev.c   | 87 +++++++++++++++++++++++++++++++++++++++++++++++++++++++
 include/console.h | 27 +++++++++++++++++
 include/serdev.h  | 36 +++++++++++++++++++++++
 6 files changed, 178 insertions(+), 3 deletions(-)
 create mode 100644 common/serdev.c
 create mode 100644 include/serdev.h

diff --git a/common/Kconfig b/common/Kconfig
index 81cf72a95..601bc95a4 100644
--- a/common/Kconfig
+++ b/common/Kconfig
@@ -712,6 +712,12 @@ config CONSOLE_NONE
 
 endchoice
 
+config SERIAL_DEV_BUS
+	bool "Serial device bus"
+	depends on CONSOLE_FULL
+	help
+	  Core support for devices connected via a serial port.
+
 choice
 	prompt "Console activation strategy"
 	depends on CONSOLE_FULL
diff --git a/common/Makefile b/common/Makefile
index a9abcd1bc..c945dd78e 100644
--- a/common/Makefile
+++ b/common/Makefile
@@ -61,6 +61,7 @@ obj-$(CONFIG_FIRMWARE)		+= firmware.o
 obj-$(CONFIG_UBIFORMAT)		+= ubiformat.o
 obj-$(CONFIG_BAREBOX_UPDATE_IMX_NAND_FCB) += imx-bbu-nand-fcb.o
 obj-$(CONFIG_BOOT)		+= boot.o
+obj-$(CONFIG_SERIAL_DEV_BUS)	+= serdev.o
 
 ifdef CONFIG_PASSWORD
 
diff --git a/common/console.c b/common/console.c
index f4c799fa5..13b1360b5 100644
--- a/common/console.c
+++ b/common/console.c
@@ -305,10 +305,11 @@ static ssize_t fops_write(struct cdev* dev, const void* buf, size_t count,
 
 int console_register(struct console_device *newcdev)
 {
+	struct device_node *serdev_node = console_is_serdev_node(newcdev);
 	struct device_d *dev = &newcdev->class_dev;
 	int activate = 0, ret;
 
-	if (initialized == CONSOLE_UNINITIALIZED)
+	if (!serdev_node && initialized == CONSOLE_UNINITIALIZED)
 		console_init_early();
 
 	if (newcdev->devname) {
@@ -323,6 +324,17 @@ int console_register(struct console_device *newcdev)
 		dev->parent = newcdev->dev;
 	platform_device_register(dev);
 
+	newcdev->open_count = 0;
+
+	/*
+	 * If our console deive is a serdev, we skip the creation of
+	 * corresponding entry in /dev as well as registration in
+	 * console_list and just go straigh to populating child
+	 * devices.
+	 */
+	if (serdev_node)
+		return of_platform_populate(serdev_node, NULL, dev);
+
 	if (newcdev->setbrg) {
 		ret = newcdev->setbrg(newcdev, CONFIG_BAUDRATE);
 		if (ret)
@@ -335,8 +347,6 @@ int console_register(struct console_device *newcdev)
 	if (newcdev->putc && !newcdev->puts)
 		newcdev->puts = __console_puts;
 
-	newcdev->open_count = 0;
-
 	dev_add_param_string(dev, "active", console_active_set, console_active_get,
 			     &newcdev->active_string, newcdev);
 
@@ -386,6 +396,14 @@ int console_unregister(struct console_device *cdev)
 	struct device_d *dev = &cdev->class_dev;
 	int status;
 
+	/*
+	 * We don't do any sophisticated serdev device de-population
+	 * and instead claim this console busy, preventing its
+	 * de-initialization, 'till the very end of our execution.
+	 */
+	if (console_is_serdev_node(cdev))
+		return -EBUSY;
+
 	devfs_remove(&cdev->devfs);
 
 	list_del(&cdev->list);
diff --git a/common/serdev.c b/common/serdev.c
new file mode 100644
index 000000000..58985c4b1
--- /dev/null
+++ b/common/serdev.c
@@ -0,0 +1,87 @@
+
+#include <common.h>
+#include <serdev.h>
+
+static void serdev_device_poller(void *context)
+{
+	struct serdev_device *serdev = context;
+	struct console_device *cdev = to_console_device(serdev);
+	unsigned char *buf = serdev->buf;
+	int ret, len;
+
+	/*
+	 * Since this callback is a part of poller infrastructure we
+	 * want to use _non_interruptible version of the function
+	 * below to prevent recursion from happening (regular
+	 * console_drain will call is_timeout, which might end up
+	 * calling this function again).
+	 */
+	len = console_drain_non_interruptible(cdev, serdev->fifo, buf,
+					      PAGE_SIZE,
+					      serdev->polling_window);
+	while (len > 0) {
+		ret = serdev->receive_buf(serdev, buf, len);
+		len -= ret;
+		buf += ret;
+	}
+
+	/*
+	 * Re-schedule ourselves in 'serdev->polling_interval'
+	 * nanoseconds
+	 */
+	poller_call_async(&serdev->poller,
+			  serdev->polling_interval,
+			  serdev_device_poller,
+			  serdev);
+}
+
+int serdev_device_open(struct serdev_device *serdev)
+{
+	struct console_device *cdev = to_console_device(serdev);
+	int ret;
+
+	if (!cdev->putc || !cdev->getc)
+		return -EINVAL;
+
+	if (!serdev->polling_window || !serdev->polling_interval)
+		return -EINVAL;
+
+	serdev->buf = xzalloc(PAGE_SIZE);
+	serdev->fifo = kfifo_alloc(PAGE_SIZE);
+	if (!serdev->fifo)
+		return -ENOMEM;
+
+	ret = poller_async_register(&serdev->poller);
+	if (ret)
+		return ret;
+
+	return console_open(cdev);
+}
+
+unsigned int serdev_device_set_baudrate(struct serdev_device *serdev,
+					unsigned int speed)
+{
+	struct console_device *cdev = to_console_device(serdev);
+
+	if (console_set_baudrate(cdev, speed) < 0)
+		return 0;
+
+	return console_get_baudrate(cdev);
+}
+
+int serdev_device_write(struct serdev_device *serdev, const unsigned char *buf,
+			size_t count, unsigned long timeout)
+{
+	struct console_device *cdev = to_console_device(serdev);
+
+	while (count--)
+		cdev->putc(cdev, *buf++);
+	/*
+	 * Poll Rx once right after we just send some data in case our
+	 * serdev device implements command/response type of a
+	 * protocol and we need to start draining input as soon as
+	 * possible.
+	 */
+	serdev_device_poller(serdev);
+	return 0;
+}
diff --git a/include/console.h b/include/console.h
index 4aa4c8f9e..14f00fa1e 100644
--- a/include/console.h
+++ b/include/console.h
@@ -23,6 +23,7 @@
 #include <param.h>
 #include <linux/list.h>
 #include <driver.h>
+#include <serdev.h>
 #include <clock.h>
 
 #define CONSOLE_STDIN           (1 << 0)
@@ -65,8 +66,34 @@ struct console_device {
 
 	struct cdev devfs;
 	struct file_operations fops;
+
+	struct serdev_device serdev;
 };
 
+static inline struct serdev_device *to_serdev_device(struct device_d *d)
+{
+	struct console_device *cdev =
+		container_of(d, struct console_device, class_dev);
+	return &cdev->serdev;
+}
+
+static inline struct console_device *
+to_console_device(struct serdev_device *serdev)
+{
+	return container_of(serdev, struct console_device, serdev);
+}
+
+static inline struct device_node *
+console_is_serdev_node(struct console_device *cdev)
+{
+	struct device_d *dev = cdev->dev;
+	if (dev && dev->device_node &&
+	    of_get_child_count(dev->device_node))
+		return dev->device_node;
+
+	return NULL;
+}
+
 int console_register(struct console_device *cdev);
 int console_unregister(struct console_device *cdev);
 
diff --git a/include/serdev.h b/include/serdev.h
new file mode 100644
index 000000000..efc735fed
--- /dev/null
+++ b/include/serdev.h
@@ -0,0 +1,36 @@
+#ifndef _SERDEV_H_
+#define _SERDEV_H_
+
+#include <driver.h>
+#include <poller.h>
+#include <kfifo.h>
+
+/**
+ * struct serdev_device - Basic representation of an serdev device
+ *
+ * @dev:		Corresponding device
+ * @fifo:		Circular buffer used for console draining
+ * @buf:		Buffer used to pass Rx data to consumers
+ * @poller		Async poller used to poll this serdev
+ * @polling_interval:	Async poller periodicity
+ * @polling_window:	Duration of a single busy loop poll
+ * @receive_buf:	Function called with data received from device;
+ *			returns number of bytes accepted;
+ */
+struct serdev_device {
+	struct device_d *dev;
+	struct kfifo *fifo;
+	unsigned char *buf;
+	struct poller_async poller;
+	uint64_t polling_interval;
+	uint64_t polling_window;
+
+	int (*receive_buf)(struct serdev_device *, const unsigned char *,
+			   size_t);
+};
+
+int serdev_device_open(struct serdev_device *);
+unsigned int serdev_device_set_baudrate(struct serdev_device *, unsigned int);
+int serdev_device_write(struct serdev_device *, const unsigned char *,
+			size_t, unsigned long);
+#endif
-- 
2.14.3



From andrew.smirnov at gmail.com  Mon Mar 26 06:12:31 2018
From: andrew.smirnov at gmail.com (Andrey Smirnov)
Date: Mon, 26 Mar 2018 06:12:31 -0700
Subject: [PATCH] lib: Port CRC-CCITT functions from Linux kernel
Message-ID: <20180326131231.9268-1-andrew.smirnov@gmail.com>

Port CRC-CCITT implemenation in order to support porting MFD driver
for RAVE SP.

Signed-off-by: Andrey Smirnov <andrew.smirnov at gmail.com>
---
 include/linux/crc-ccitt.h |  23 +++++++++
 lib/Kconfig               |   8 +++
 lib/Makefile              |   1 +
 lib/crc-ccitt.c           | 124 ++++++++++++++++++++++++++++++++++++++++++++++
 4 files changed, 156 insertions(+)
 create mode 100644 include/linux/crc-ccitt.h
 create mode 100644 lib/crc-ccitt.c

diff --git a/include/linux/crc-ccitt.h b/include/linux/crc-ccitt.h
new file mode 100644
index 000000000..72c92c396
--- /dev/null
+++ b/include/linux/crc-ccitt.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _LINUX_CRC_CCITT_H
+#define _LINUX_CRC_CCITT_H
+
+#include <linux/types.h>
+
+extern u16 const crc_ccitt_table[256];
+extern u16 const crc_ccitt_false_table[256];
+
+extern u16 crc_ccitt(u16 crc, const u8 *buffer, size_t len);
+extern u16 crc_ccitt_false(u16 crc, const u8 *buffer, size_t len);
+
+static inline u16 crc_ccitt_byte(u16 crc, const u8 c)
+{
+	return (crc >> 8) ^ crc_ccitt_table[(crc ^ c) & 0xff];
+}
+
+static inline u16 crc_ccitt_false_byte(u16 crc, const u8 c)
+{
+    return (crc << 8) ^ crc_ccitt_false_table[(crc >> 8) ^ c];
+}
+
+#endif /* _LINUX_CRC_CCITT_H */
diff --git a/lib/Kconfig b/lib/Kconfig
index 4e9213f3e..b4b10afa2 100644
--- a/lib/Kconfig
+++ b/lib/Kconfig
@@ -110,6 +110,14 @@ config ALLOW_PRNG_FALLBACK
 	  available and this option is disabled, cmd_password will fail.
 	  Enable it on your own risk.
 
+config CRC_CCITT
+        bool "CRC-CCITT functions"
+	help
+	  This option is provided for the case where no in-kernel-tree
+	  modules require CRC-CCITT functions, but a module built outside
+	  the kernel tree does. Such modules that use library CRC-CCITT
+	  functions require M here.
+
 source lib/gui/Kconfig
 
 source lib/fonts/Kconfig
diff --git a/lib/Makefile b/lib/Makefile
index e5cf32c16..a285f6d0c 100644
--- a/lib/Makefile
+++ b/lib/Makefile
@@ -63,3 +63,4 @@ obj-$(CONFIG_RATP)	+= ratp.o
 obj-y			+= list_sort.o
 obj-y			+= int_sqrt.o
 obj-y			+= parseopt.o
+obj-$(CONFIG_CRC_CCITT) += crc-ccitt.o
diff --git a/lib/crc-ccitt.c b/lib/crc-ccitt.c
new file mode 100644
index 000000000..b5a916dd8
--- /dev/null
+++ b/lib/crc-ccitt.c
@@ -0,0 +1,124 @@
+/*
+ *	linux/lib/crc-ccitt.c
+ *
+ *	This source code is licensed under the GNU General Public License,
+ *	Version 2. See the file COPYING for more details.
+ */
+#include <common.h>
+#include <linux/types.h>
+#include <linux/crc-ccitt.h>
+
+/*
+ * This mysterious table is just the CRC of each possible byte. It can be
+ * computed using the standard bit-at-a-time methods. The polynomial can
+ * be seen in entry 128, 0x8408. This corresponds to x^0 + x^5 + x^12.
+ * Add the implicit x^16, and you have the standard CRC-CCITT.
+ */
+u16 const crc_ccitt_table[256] = {
+	0x0000, 0x1189, 0x2312, 0x329b, 0x4624, 0x57ad, 0x6536, 0x74bf,
+	0x8c48, 0x9dc1, 0xaf5a, 0xbed3, 0xca6c, 0xdbe5, 0xe97e, 0xf8f7,
+	0x1081, 0x0108, 0x3393, 0x221a, 0x56a5, 0x472c, 0x75b7, 0x643e,
+	0x9cc9, 0x8d40, 0xbfdb, 0xae52, 0xdaed, 0xcb64, 0xf9ff, 0xe876,
+	0x2102, 0x308b, 0x0210, 0x1399, 0x6726, 0x76af, 0x4434, 0x55bd,
+	0xad4a, 0xbcc3, 0x8e58, 0x9fd1, 0xeb6e, 0xfae7, 0xc87c, 0xd9f5,
+	0x3183, 0x200a, 0x1291, 0x0318, 0x77a7, 0x662e, 0x54b5, 0x453c,
+	0xbdcb, 0xac42, 0x9ed9, 0x8f50, 0xfbef, 0xea66, 0xd8fd, 0xc974,
+	0x4204, 0x538d, 0x6116, 0x709f, 0x0420, 0x15a9, 0x2732, 0x36bb,
+	0xce4c, 0xdfc5, 0xed5e, 0xfcd7, 0x8868, 0x99e1, 0xab7a, 0xbaf3,
+	0x5285, 0x430c, 0x7197, 0x601e, 0x14a1, 0x0528, 0x37b3, 0x263a,
+	0xdecd, 0xcf44, 0xfddf, 0xec56, 0x98e9, 0x8960, 0xbbfb, 0xaa72,
+	0x6306, 0x728f, 0x4014, 0x519d, 0x2522, 0x34ab, 0x0630, 0x17b9,
+	0xef4e, 0xfec7, 0xcc5c, 0xddd5, 0xa96a, 0xb8e3, 0x8a78, 0x9bf1,
+	0x7387, 0x620e, 0x5095, 0x411c, 0x35a3, 0x242a, 0x16b1, 0x0738,
+	0xffcf, 0xee46, 0xdcdd, 0xcd54, 0xb9eb, 0xa862, 0x9af9, 0x8b70,
+	0x8408, 0x9581, 0xa71a, 0xb693, 0xc22c, 0xd3a5, 0xe13e, 0xf0b7,
+	0x0840, 0x19c9, 0x2b52, 0x3adb, 0x4e64, 0x5fed, 0x6d76, 0x7cff,
+	0x9489, 0x8500, 0xb79b, 0xa612, 0xd2ad, 0xc324, 0xf1bf, 0xe036,
+	0x18c1, 0x0948, 0x3bd3, 0x2a5a, 0x5ee5, 0x4f6c, 0x7df7, 0x6c7e,
+	0xa50a, 0xb483, 0x8618, 0x9791, 0xe32e, 0xf2a7, 0xc03c, 0xd1b5,
+	0x2942, 0x38cb, 0x0a50, 0x1bd9, 0x6f66, 0x7eef, 0x4c74, 0x5dfd,
+	0xb58b, 0xa402, 0x9699, 0x8710, 0xf3af, 0xe226, 0xd0bd, 0xc134,
+	0x39c3, 0x284a, 0x1ad1, 0x0b58, 0x7fe7, 0x6e6e, 0x5cf5, 0x4d7c,
+	0xc60c, 0xd785, 0xe51e, 0xf497, 0x8028, 0x91a1, 0xa33a, 0xb2b3,
+	0x4a44, 0x5bcd, 0x6956, 0x78df, 0x0c60, 0x1de9, 0x2f72, 0x3efb,
+	0xd68d, 0xc704, 0xf59f, 0xe416, 0x90a9, 0x8120, 0xb3bb, 0xa232,
+	0x5ac5, 0x4b4c, 0x79d7, 0x685e, 0x1ce1, 0x0d68, 0x3ff3, 0x2e7a,
+	0xe70e, 0xf687, 0xc41c, 0xd595, 0xa12a, 0xb0a3, 0x8238, 0x93b1,
+	0x6b46, 0x7acf, 0x4854, 0x59dd, 0x2d62, 0x3ceb, 0x0e70, 0x1ff9,
+	0xf78f, 0xe606, 0xd49d, 0xc514, 0xb1ab, 0xa022, 0x92b9, 0x8330,
+	0x7bc7, 0x6a4e, 0x58d5, 0x495c, 0x3de3, 0x2c6a, 0x1ef1, 0x0f78
+};
+EXPORT_SYMBOL(crc_ccitt_table);
+
+/*
+ * Similar table to calculate CRC16 variant known as CRC-CCITT-FALSE
+ * Reflected bits order, does not augment final value.
+ */
+u16 const crc_ccitt_false_table[256] = {
+    0x0000, 0x1021, 0x2042, 0x3063, 0x4084, 0x50A5, 0x60C6, 0x70E7,
+    0x8108, 0x9129, 0xA14A, 0xB16B, 0xC18C, 0xD1AD, 0xE1CE, 0xF1EF,
+    0x1231, 0x0210, 0x3273, 0x2252, 0x52B5, 0x4294, 0x72F7, 0x62D6,
+    0x9339, 0x8318, 0xB37B, 0xA35A, 0xD3BD, 0xC39C, 0xF3FF, 0xE3DE,
+    0x2462, 0x3443, 0x0420, 0x1401, 0x64E6, 0x74C7, 0x44A4, 0x5485,
+    0xA56A, 0xB54B, 0x8528, 0x9509, 0xE5EE, 0xF5CF, 0xC5AC, 0xD58D,
+    0x3653, 0x2672, 0x1611, 0x0630, 0x76D7, 0x66F6, 0x5695, 0x46B4,
+    0xB75B, 0xA77A, 0x9719, 0x8738, 0xF7DF, 0xE7FE, 0xD79D, 0xC7BC,
+    0x48C4, 0x58E5, 0x6886, 0x78A7, 0x0840, 0x1861, 0x2802, 0x3823,
+    0xC9CC, 0xD9ED, 0xE98E, 0xF9AF, 0x8948, 0x9969, 0xA90A, 0xB92B,
+    0x5AF5, 0x4AD4, 0x7AB7, 0x6A96, 0x1A71, 0x0A50, 0x3A33, 0x2A12,
+    0xDBFD, 0xCBDC, 0xFBBF, 0xEB9E, 0x9B79, 0x8B58, 0xBB3B, 0xAB1A,
+    0x6CA6, 0x7C87, 0x4CE4, 0x5CC5, 0x2C22, 0x3C03, 0x0C60, 0x1C41,
+    0xEDAE, 0xFD8F, 0xCDEC, 0xDDCD, 0xAD2A, 0xBD0B, 0x8D68, 0x9D49,
+    0x7E97, 0x6EB6, 0x5ED5, 0x4EF4, 0x3E13, 0x2E32, 0x1E51, 0x0E70,
+    0xFF9F, 0xEFBE, 0xDFDD, 0xCFFC, 0xBF1B, 0xAF3A, 0x9F59, 0x8F78,
+    0x9188, 0x81A9, 0xB1CA, 0xA1EB, 0xD10C, 0xC12D, 0xF14E, 0xE16F,
+    0x1080, 0x00A1, 0x30C2, 0x20E3, 0x5004, 0x4025, 0x7046, 0x6067,
+    0x83B9, 0x9398, 0xA3FB, 0xB3DA, 0xC33D, 0xD31C, 0xE37F, 0xF35E,
+    0x02B1, 0x1290, 0x22F3, 0x32D2, 0x4235, 0x5214, 0x6277, 0x7256,
+    0xB5EA, 0xA5CB, 0x95A8, 0x8589, 0xF56E, 0xE54F, 0xD52C, 0xC50D,
+    0x34E2, 0x24C3, 0x14A0, 0x0481, 0x7466, 0x6447, 0x5424, 0x4405,
+    0xA7DB, 0xB7FA, 0x8799, 0x97B8, 0xE75F, 0xF77E, 0xC71D, 0xD73C,
+    0x26D3, 0x36F2, 0x0691, 0x16B0, 0x6657, 0x7676, 0x4615, 0x5634,
+    0xD94C, 0xC96D, 0xF90E, 0xE92F, 0x99C8, 0x89E9, 0xB98A, 0xA9AB,
+    0x5844, 0x4865, 0x7806, 0x6827, 0x18C0, 0x08E1, 0x3882, 0x28A3,
+    0xCB7D, 0xDB5C, 0xEB3F, 0xFB1E, 0x8BF9, 0x9BD8, 0xABBB, 0xBB9A,
+    0x4A75, 0x5A54, 0x6A37, 0x7A16, 0x0AF1, 0x1AD0, 0x2AB3, 0x3A92,
+    0xFD2E, 0xED0F, 0xDD6C, 0xCD4D, 0xBDAA, 0xAD8B, 0x9DE8, 0x8DC9,
+    0x7C26, 0x6C07, 0x5C64, 0x4C45, 0x3CA2, 0x2C83, 0x1CE0, 0x0CC1,
+    0xEF1F, 0xFF3E, 0xCF5D, 0xDF7C, 0xAF9B, 0xBFBA, 0x8FD9, 0x9FF8,
+    0x6E17, 0x7E36, 0x4E55, 0x5E74, 0x2E93, 0x3EB2, 0x0ED1, 0x1EF0
+};
+EXPORT_SYMBOL(crc_ccitt_false_table);
+
+/**
+ *	crc_ccitt - recompute the CRC (CRC-CCITT variant) for the data
+ *	buffer
+ *	@crc: previous CRC value
+ *	@buffer: data pointer
+ *	@len: number of bytes in the buffer
+ */
+u16 crc_ccitt(u16 crc, u8 const *buffer, size_t len)
+{
+	while (len--)
+		crc = crc_ccitt_byte(crc, *buffer++);
+	return crc;
+}
+EXPORT_SYMBOL(crc_ccitt);
+
+/**
+ *	crc_ccitt_false - recompute the CRC (CRC-CCITT-FALSE variant)
+ *	for the data buffer
+ *	@crc: previous CRC value
+ *	@buffer: data pointer
+ *	@len: number of bytes in the buffer
+ */
+u16 crc_ccitt_false(u16 crc, u8 const *buffer, size_t len)
+{
+	while (len--)
+		crc = crc_ccitt_false_byte(crc, *buffer++);
+	return crc;
+}
+EXPORT_SYMBOL(crc_ccitt_false);
+
+MODULE_DESCRIPTION("CRC-CCITT calculations");
+MODULE_LICENSE("GPL");
-- 
2.14.3



From andrew.smirnov at gmail.com  Mon Mar 26 06:14:45 2018
From: andrew.smirnov at gmail.com (Andrey Smirnov)
Date: Mon, 26 Mar 2018 06:14:45 -0700
Subject: [PATCH] aiodev: Constify 'unit' in 'struct aiodev'
Message-ID: <20180326131445.11229-1-andrew.smirnov@gmail.com>

The way it is currently used, there's no reason for 'uint' field to be
mutable, so constify it in order to allow 'aiodev' drivers to pass
sting literals in that field.

Signed-off-by: Andrey Smirnov <andrew.smirnov at gmail.com>
---
 include/aiodev.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/aiodev.h b/include/aiodev.h
index 0d4f7a294..5e38b4fab 100644
--- a/include/aiodev.h
+++ b/include/aiodev.h
@@ -23,7 +23,7 @@
 struct aiodevice;
 struct aiochannel {
 	int index;
-	char *unit;
+	const char *unit;
 	struct aiodevice *aiodev;
 
 	int value;
-- 
2.14.3



From p.zabel at pengutronix.de  Mon Mar 26 07:25:56 2018
From: p.zabel at pengutronix.de (Philipp Zabel)
Date: Mon, 26 Mar 2018 16:25:56 +0200
Subject: [PATCH] of: partition: fix typo when writing #address-cells
Message-ID: <20180326142556.27727-1-p.zabel@pengutronix.de>

On > 4 GiB eMMC devices, barebox writes a 32-bit address and a 64-bit
size into the partition reg property, because #address-cells is
accidentally written as '#addres-cells'. This causes a fallback to
32-bit address size. Fix the typo and thereby of_partition_fixup for
64-bit partitions.

Fixes: a2fa18f9f483 ("mtd: of: Make used partition binding configurable")
Signed-off-by: Philipp Zabel <p.zabel at pengutronix.de>
---
 drivers/of/partition.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/of/partition.c b/drivers/of/partition.c
index 6f9651a9e4..aa6e601b7f 100644
--- a/drivers/of/partition.c
+++ b/drivers/of/partition.c
@@ -190,7 +190,7 @@ static int of_partition_fixup(struct device_node *root, void *ctx)
 	if (ret)
 		return ret;
 
-	of_property_write_u32(partnode, "#addres-cells", n_cells);
+	of_property_write_u32(partnode, "#address-cells", n_cells);
 	if (ret)
 		return ret;
 
-- 
2.16.1



From l.stach at pengutronix.de  Mon Mar 26 12:20:17 2018
From: l.stach at pengutronix.de (Lucas Stach)
Date: Mon, 26 Mar 2018 21:20:17 +0200
Subject: [PATCH v3 02/10] ARM: safely switch from HYP to SVC mode if required
In-Reply-To: <20180326192025.28809-1-l.stach@pengutronix.de>
References: <20180326192025.28809-1-l.stach@pengutronix.de>
Message-ID: <20180326192025.28809-2-l.stach@pengutronix.de>

This is a port of the Linux safe_svcmode_maskall macro to
the Barebox lowlevel init.

Signed-off-by: Lucas Stach <l.stach at pengutronix.de>
Tested-by: Roland Hieber <r.hieber at pengutronix.de>
---
v3: fix whitespace
---
 arch/arm/cpu/lowlevel.S       | 18 +++++++++++++++---
 arch/arm/include/asm/system.h | 26 ++++++++++++++++++++++++++
 2 files changed, 41 insertions(+), 3 deletions(-)

diff --git a/arch/arm/cpu/lowlevel.S b/arch/arm/cpu/lowlevel.S
index 7696a198e764..43665981e48b 100644
--- a/arch/arm/cpu/lowlevel.S
+++ b/arch/arm/cpu/lowlevel.S
@@ -1,16 +1,28 @@
 #include <linux/linkage.h>
 #include <init.h>
 #include <asm/system.h>
+#include <asm/opcodes-virt.h>
 
 .section ".text_bare_init_","ax"
 ENTRY(arm_cpu_lowlevel_init)
 	/* save lr, since it may be banked away with a processor mode change */
 	mov	r2, lr
+
 	/* set the cpu to SVC32 mode, mask irq and fiq */
 	mrs	r12, cpsr
-	bic	r12, r12, #0x1f
-	orr	r12, r12, #0xd3
-	msr	cpsr, r12
+	eor	r12, r12, #HYP_MODE
+	tst	r12, #MODE_MASK
+	bic	r12, r12, #MODE_MASK
+	orr	r12, r12, #(PSR_I_BIT | PSR_F_BIT | SVC_MODE)
+THUMB(	orr	r12, r12, #PSR_T_BIT	)
+	bne	1f
+	orr	r12, r12, #PSR_A_BIT
+	adr	lr, 2f
+	msr	spsr_cxsf, r12
+	__MSR_ELR_HYP(14)
+	__ERET
+1:	msr	cpsr_c, r12
+2:
 
 #if __LINUX_ARM_ARCH__ >= 6
 	/*
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 57c76186b499..55e0f4090295 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -60,6 +60,32 @@
 #define CR_AFE  (1 << 29)	/* Access flag enable			*/
 #define CR_TE   (1 << 30)	/* Thumb exception enable		*/
 
+/*
+ * PSR bits
+ */
+#define USR_MODE	0x00000010
+#define FIQ_MODE	0x00000011
+#define IRQ_MODE	0x00000012
+#define SVC_MODE	0x00000013
+#define ABT_MODE	0x00000017
+#define HYP_MODE	0x0000001a
+#define UND_MODE	0x0000001b
+#define SYSTEM_MODE	0x0000001f
+#define MODE32_BIT	0x00000010
+#define MODE_MASK	0x0000001f
+
+#define PSR_T_BIT	0x00000020
+#define PSR_F_BIT	0x00000040
+#define PSR_I_BIT	0x00000080
+#define PSR_A_BIT	0x00000100
+#define PSR_E_BIT	0x00000200
+#define PSR_J_BIT	0x01000000
+#define PSR_Q_BIT	0x08000000
+#define PSR_V_BIT	0x10000000
+#define PSR_C_BIT	0x20000000
+#define PSR_Z_BIT	0x40000000
+#define PSR_N_BIT	0x80000000
+
 #ifndef __ASSEMBLY__
 #if __LINUX_ARM_ARCH__ >= 7
 static inline unsigned int current_el(void)
-- 
2.16.1



From l.stach at pengutronix.de  Mon Mar 26 12:20:24 2018
From: l.stach at pengutronix.de (Lucas Stach)
Date: Mon, 26 Mar 2018 21:20:24 +0200
Subject: [PATCH v3 09/10] ARM: rpi: add raspberry pi 3 support
In-Reply-To: <20180326192025.28809-1-l.stach@pengutronix.de>
References: <20180326192025.28809-1-l.stach@pengutronix.de>
Message-ID: <20180326192025.28809-9-l.stach@pengutronix.de>

This adds basic support at the same feature level as the other
supported raspberry pi boards.

Signed-off-by: Lucas Stach <l.stach at pengutronix.de>
Tested-by: Roland Hieber <r.hieber at pengutronix.de>
---
 arch/arm/boards/raspberry-pi/lowlevel.c | 14 ++++++++++++--
 arch/arm/configs/rpi_defconfig          |  2 ++
 arch/arm/dts/Makefile                   |  1 +
 arch/arm/dts/bcm2837-rpi-3.dts          | 15 +++++++++++++++
 arch/arm/mach-bcm283x/Kconfig           |  6 ++++++
 arch/arm/mach-bcm283x/core.c            |  1 +
 images/Makefile.bcm283x                 |  4 ++++
 7 files changed, 41 insertions(+), 2 deletions(-)
 create mode 100644 arch/arm/dts/bcm2837-rpi-3.dts

diff --git a/arch/arm/boards/raspberry-pi/lowlevel.c b/arch/arm/boards/raspberry-pi/lowlevel.c
index 4e71e29e0c0b..5ca0d3877069 100644
--- a/arch/arm/boards/raspberry-pi/lowlevel.c
+++ b/arch/arm/boards/raspberry-pi/lowlevel.c
@@ -1,7 +1,7 @@
+#include <asm/barebox-arm.h>
+#include <asm/cache.h>
 #include <common.h>
 #include <linux/sizes.h>
-#include <asm/barebox-arm.h>
-#include <asm/barebox-arm-head.h>
 #include <mach/platform.h>
 
 extern char __dtb_bcm2835_rpi_start[];
@@ -23,3 +23,13 @@ ENTRY_FUNCTION(start_raspberry_pi2, r0, r1, r2)
 
 	barebox_arm_entry(BCM2835_SDRAM_BASE, SZ_512M, fdt);
 }
+
+extern char __dtb_bcm2837_rpi_3_start[];
+ENTRY_FUNCTION(start_raspberry_pi3, r0, r1, r2)
+{
+	void *fdt = __dtb_bcm2837_rpi_3_start - get_runtime_offset();
+
+	arm_cpu_lowlevel_init();
+
+	barebox_arm_entry(BCM2835_SDRAM_BASE, SZ_512M, fdt);
+}
diff --git a/arch/arm/configs/rpi_defconfig b/arch/arm/configs/rpi_defconfig
index f3aef4290425..cd88b4ac751c 100644
--- a/arch/arm/configs/rpi_defconfig
+++ b/arch/arm/configs/rpi_defconfig
@@ -1,9 +1,11 @@
 CONFIG_ARCH_BCM283X=y
 CONFIG_MACH_RPI=y
 CONFIG_MACH_RPI2=y
+CONFIG_MACH_RPI3=y
 CONFIG_AEABI=y
 CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
 CONFIG_ARM_UNWIND=y
+CONFIG_IMAGE_COMPRESSION_NONE=y
 CONFIG_MMU=y
 CONFIG_MALLOC_TLSF=y
 CONFIG_KALLSYMS=y
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 0526a6f40724..0eab313c5011 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -66,6 +66,7 @@ pbl-dtb-$(CONFIG_MACH_PHYTEC_SOM_RK3288) += rk3288-phycore-som.dtb.o
 pbl-dtb-$(CONFIG_MACH_REALQ7) += imx6q-dmo-edmqmx6.dtb.o
 pbl-dtb-$(CONFIG_MACH_RPI) += bcm2835-rpi.dtb.o
 pbl-dtb-$(CONFIG_MACH_RPI2) += bcm2836-rpi-2.dtb.o
+pbl-dtb-$(CONFIG_MACH_RPI3) += bcm2837-rpi-3.dtb.o
 pbl-dtb-$(CONFIG_MACH_SABRELITE) += imx6q-sabrelite.dtb.o imx6dl-sabrelite.dtb.o
 pbl-dtb-$(CONFIG_MACH_SABRESD) += imx6q-sabresd.dtb.o
 pbl-dtb-$(CONFIG_MACH_FREESCALE_IMX6SX_SABRESDB) += imx6sx-sdb.dtb.o
diff --git a/arch/arm/dts/bcm2837-rpi-3.dts b/arch/arm/dts/bcm2837-rpi-3.dts
new file mode 100644
index 000000000000..f8c58c570137
--- /dev/null
+++ b/arch/arm/dts/bcm2837-rpi-3.dts
@@ -0,0 +1,15 @@
+#include <arm64/broadcom/bcm2837-rpi-3-b.dts>
+
+/ {
+	chosen {
+		stdout-path = &uart0;
+	};
+
+	memory {
+		reg = <0x0 0x0>;
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
diff --git a/arch/arm/mach-bcm283x/Kconfig b/arch/arm/mach-bcm283x/Kconfig
index 1457f114ccaa..af2f88c47acb 100644
--- a/arch/arm/mach-bcm283x/Kconfig
+++ b/arch/arm/mach-bcm283x/Kconfig
@@ -19,6 +19,12 @@ config MACH_RPI2
 	select CPU_V7
 	select MACH_RPI_COMMON
 
+config MACH_RPI3
+	bool "RaspberryPi 3 (BCM2837/CORTEX-A53)"
+	select CPU_V7
+	select MACH_RPI_COMMON
+	select ARM_SECURE_MONITOR
+
 endmenu
 
 config MACH_RPI_DEBUG_UART_BASE
diff --git a/arch/arm/mach-bcm283x/core.c b/arch/arm/mach-bcm283x/core.c
index fddcb0d1a1d4..26f0996b1cb8 100644
--- a/arch/arm/mach-bcm283x/core.c
+++ b/arch/arm/mach-bcm283x/core.c
@@ -41,6 +41,7 @@ static int bcm2835_clk_init(void)
 	clk = clk_fixed("uart0-pl0110", 3 * 1000 * 1000);
 	clk_register_clkdev(clk, NULL, "uart0-pl0110");
 	clk_register_clkdev(clk, NULL, "20201000.serial");
+	clk_register_clkdev(clk, NULL, "3f201000.serial");
 
 	clk = clk_fixed("bcm2835-cs", 1 * 1000 * 1000);
 	clk_register_clkdev(clk, NULL, "bcm2835-cs");
diff --git a/images/Makefile.bcm283x b/images/Makefile.bcm283x
index d59ef043f05c..d14e648926ac 100644
--- a/images/Makefile.bcm283x
+++ b/images/Makefile.bcm283x
@@ -9,3 +9,7 @@ image-$(CONFIG_MACH_RPI) += barebox-raspberry-pi-1.img
 pblx-$(CONFIG_MACH_RPI2) += start_raspberry_pi2
 FILE_barebox-raspberry-pi-2.img = start_raspberry_pi2.pblx
 image-$(CONFIG_MACH_RPI2) += barebox-raspberry-pi-2.img
+
+pblx-$(CONFIG_MACH_RPI3) += start_raspberry_pi3
+FILE_barebox-raspberry-pi-3.img = start_raspberry_pi3.pblx
+image-$(CONFIG_MACH_RPI3) += barebox-raspberry-pi-3.img
\ No newline at end of file
-- 
2.16.1



From l.stach at pengutronix.de  Mon Mar 26 12:20:23 2018
From: l.stach at pengutronix.de (Lucas Stach)
Date: Mon, 26 Mar 2018 21:20:23 +0200
Subject: [PATCH v3 08/10] ARM: rpi: add revision IDs for Pi 3 Model B and Pi
 Zero
In-Reply-To: <20180326192025.28809-1-l.stach@pengutronix.de>
References: <20180326192025.28809-1-l.stach@pengutronix.de>
Message-ID: <20180326192025.28809-8-l.stach@pengutronix.de>

From: Enrico Joerns <ejo at pengutronix.de>

Signed-off-by: Enrico Joerns <ejo at pengutronix.de>
Signed-off-by: Lucas Stach <l.stach at pengutronix.de>
Tested-by: Roland Hieber <r.hieber at pengutronix.de>
---
 arch/arm/boards/raspberry-pi/rpi-common.c | 2 ++
 arch/arm/mach-bcm283x/include/mach/mbox.h | 4 ++++
 2 files changed, 6 insertions(+)

diff --git a/arch/arm/boards/raspberry-pi/rpi-common.c b/arch/arm/boards/raspberry-pi/rpi-common.c
index 6e375bc984de..aec8cb27ed40 100644
--- a/arch/arm/boards/raspberry-pi/rpi-common.c
+++ b/arch/arm/boards/raspberry-pi/rpi-common.c
@@ -174,6 +174,8 @@ const struct rpi_model rpi_models_old_scheme[] = {
 const struct rpi_model rpi_models_new_scheme[] = {
 	RPI_MODEL(0, "Unknown model", NULL),
 	RPI_MODEL(BCM2836_BOARD_REV_2_B, "2 Model B", rpi_b_plus_init),
+	RPI_MODEL(BCM2837_BOARD_REV_3_B, "3 Model B", rpi_b_plus_init),
+	RPI_MODEL(BCM2837_BOARD_REV_ZERO, "Zero", rpi_b_plus_init),
 };
 
 static int rpi_board_rev = 0;
diff --git a/arch/arm/mach-bcm283x/include/mach/mbox.h b/arch/arm/mach-bcm283x/include/mach/mbox.h
index 2b5aea88ee0a..4cddf99a8429 100644
--- a/arch/arm/mach-bcm283x/include/mach/mbox.h
+++ b/arch/arm/mach-bcm283x/include/mach/mbox.h
@@ -129,6 +129,10 @@ struct bcm2835_mbox_tag_hdr {
 
 /* RPi 2 */
 #define BCM2836_BOARD_REV_2_B		0x4
+/* RPi 3 */
+#define BCM2837_BOARD_REV_3_B		0x8
+/* Zero */
+#define BCM2837_BOARD_REV_ZERO		0x9
 
 /*
  * 0x2..0xf from:
-- 
2.16.1



From l.stach at pengutronix.de  Mon Mar 26 12:20:16 2018
From: l.stach at pengutronix.de (Lucas Stach)
Date: Mon, 26 Mar 2018 21:20:16 +0200
Subject: [PATCH v3 01/10] ARM: import opcode helpers from Linux kernel
Message-ID: <20180326192025.28809-1-l.stach@pengutronix.de>

Those are needed to generate some of the ARM SEC and VIRT
opcodes in a portable way.

Signed-off-by: Lucas Stach <l.stach at pengutronix.de>
Tested-by: Roland Hieber <r.hieber at pengutronix.de>
---
 arch/arm/include/asm/opcodes-virt.h |  39 ++++++
 arch/arm/include/asm/opcodes.h      | 231 ++++++++++++++++++++++++++++++++++++
 2 files changed, 270 insertions(+)
 create mode 100644 arch/arm/include/asm/opcodes-virt.h
 create mode 100644 arch/arm/include/asm/opcodes.h

diff --git a/arch/arm/include/asm/opcodes-virt.h b/arch/arm/include/asm/opcodes-virt.h
new file mode 100644
index 000000000000..efcfdf92d9d5
--- /dev/null
+++ b/arch/arm/include/asm/opcodes-virt.h
@@ -0,0 +1,39 @@
+/*
+ * opcodes-virt.h: Opcode definitions for the ARM virtualization extensions
+ * Copyright (C) 2012  Linaro Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+#ifndef __ASM_ARM_OPCODES_VIRT_H
+#define __ASM_ARM_OPCODES_VIRT_H
+
+#include <asm/opcodes.h>
+
+#define __HVC(imm16) __inst_arm_thumb32(				\
+	0xE1400070 | (((imm16) & 0xFFF0) << 4) | ((imm16) & 0x000F),	\
+	0xF7E08000 | (((imm16) & 0xF000) << 4) | ((imm16) & 0x0FFF)	\
+)
+
+#define __ERET	__inst_arm_thumb32(					\
+	0xE160006E,							\
+	0xF3DE8F00							\
+)
+
+#define __MSR_ELR_HYP(regnum)	__inst_arm_thumb32(			\
+	0xE12EF300 | regnum,						\
+	0xF3808E30 | (regnum << 16)					\
+)
+
+#endif /* ! __ASM_ARM_OPCODES_VIRT_H */
diff --git a/arch/arm/include/asm/opcodes.h b/arch/arm/include/asm/opcodes.h
new file mode 100644
index 000000000000..a78bf5d2c518
--- /dev/null
+++ b/arch/arm/include/asm/opcodes.h
@@ -0,0 +1,231 @@
+/*
+ *  arch/arm/include/asm/opcodes.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARM_OPCODES_H
+#define __ASM_ARM_OPCODES_H
+
+#ifndef __ASSEMBLY__
+#include <linux/linkage.h>
+extern asmlinkage unsigned int arm_check_condition(u32 opcode, u32 psr);
+#endif
+
+#define ARM_OPCODE_CONDTEST_FAIL   0
+#define ARM_OPCODE_CONDTEST_PASS   1
+#define ARM_OPCODE_CONDTEST_UNCOND 2
+
+
+/*
+ * Assembler opcode byteswap helpers.
+ * These are only intended for use by this header: don't use them directly,
+ * because they will be suboptimal in most cases.
+ */
+#define ___asm_opcode_swab32(x) (	\
+	  (((x) << 24) & 0xFF000000)	\
+	| (((x) <<  8) & 0x00FF0000)	\
+	| (((x) >>  8) & 0x0000FF00)	\
+	| (((x) >> 24) & 0x000000FF)	\
+)
+#define ___asm_opcode_swab16(x) (	\
+	  (((x) << 8) & 0xFF00)		\
+	| (((x) >> 8) & 0x00FF)		\
+)
+#define ___asm_opcode_swahb32(x) (	\
+	  (((x) << 8) & 0xFF00FF00)	\
+	| (((x) >> 8) & 0x00FF00FF)	\
+)
+#define ___asm_opcode_swahw32(x) (	\
+	  (((x) << 16) & 0xFFFF0000)	\
+	| (((x) >> 16) & 0x0000FFFF)	\
+)
+#define ___asm_opcode_identity32(x) ((x) & 0xFFFFFFFF)
+#define ___asm_opcode_identity16(x) ((x) & 0xFFFF)
+
+
+/*
+ * Opcode byteswap helpers
+ *
+ * These macros help with converting instructions between a canonical integer
+ * format and in-memory representation, in an endianness-agnostic manner.
+ *
+ * __mem_to_opcode_*() convert from in-memory representation to canonical form.
+ * __opcode_to_mem_*() convert from canonical form to in-memory representation.
+ *
+ *
+ * Canonical instruction representation:
+ *
+ *	ARM:		0xKKLLMMNN
+ *	Thumb 16-bit:	0x0000KKLL, where KK < 0xE8
+ *	Thumb 32-bit:	0xKKLLMMNN, where KK >= 0xE8
+ *
+ * There is no way to distinguish an ARM instruction in canonical representation
+ * from a Thumb instruction (just as these cannot be distinguished in memory).
+ * Where this distinction is important, it needs to be tracked separately.
+ *
+ * Note that values in the range 0x0000E800..0xE7FFFFFF intentionally do not
+ * represent any valid Thumb-2 instruction.  For this range,
+ * __opcode_is_thumb32() and __opcode_is_thumb16() will both be false.
+ *
+ * The ___asm variants are intended only for use by this header, in situations
+ * involving inline assembler.  For .S files, the normal __opcode_*() macros
+ * should do the right thing.
+ */
+#ifdef __ASSEMBLY__
+
+#define ___opcode_swab32(x) ___asm_opcode_swab32(x)
+#define ___opcode_swab16(x) ___asm_opcode_swab16(x)
+#define ___opcode_swahb32(x) ___asm_opcode_swahb32(x)
+#define ___opcode_swahw32(x) ___asm_opcode_swahw32(x)
+#define ___opcode_identity32(x) ___asm_opcode_identity32(x)
+#define ___opcode_identity16(x) ___asm_opcode_identity16(x)
+
+#else /* ! __ASSEMBLY__ */
+
+#include <linux/types.h>
+#include <linux/swab.h>
+
+#define ___opcode_swab32(x) swab32(x)
+#define ___opcode_swab16(x) swab16(x)
+#define ___opcode_swahb32(x) swahb32(x)
+#define ___opcode_swahw32(x) swahw32(x)
+#define ___opcode_identity32(x) ((u32)(x))
+#define ___opcode_identity16(x) ((u16)(x))
+
+#endif /* ! __ASSEMBLY__ */
+
+
+#ifdef CONFIG_CPU_ENDIAN_BE8
+
+#define __opcode_to_mem_arm(x) ___opcode_swab32(x)
+#define __opcode_to_mem_thumb16(x) ___opcode_swab16(x)
+#define __opcode_to_mem_thumb32(x) ___opcode_swahb32(x)
+#define ___asm_opcode_to_mem_arm(x) ___asm_opcode_swab32(x)
+#define ___asm_opcode_to_mem_thumb16(x) ___asm_opcode_swab16(x)
+#define ___asm_opcode_to_mem_thumb32(x) ___asm_opcode_swahb32(x)
+
+#else /* ! CONFIG_CPU_ENDIAN_BE8 */
+
+#define __opcode_to_mem_arm(x) ___opcode_identity32(x)
+#define __opcode_to_mem_thumb16(x) ___opcode_identity16(x)
+#define ___asm_opcode_to_mem_arm(x) ___asm_opcode_identity32(x)
+#define ___asm_opcode_to_mem_thumb16(x) ___asm_opcode_identity16(x)
+#ifndef CONFIG_CPU_ENDIAN_BE32
+/*
+ * On BE32 systems, using 32-bit accesses to store Thumb instructions will not
+ * work in all cases, due to alignment constraints.  For now, a correct
+ * version is not provided for BE32.
+ */
+#define __opcode_to_mem_thumb32(x) ___opcode_swahw32(x)
+#define ___asm_opcode_to_mem_thumb32(x) ___asm_opcode_swahw32(x)
+#endif
+
+#endif /* ! CONFIG_CPU_ENDIAN_BE8 */
+
+#define __mem_to_opcode_arm(x) __opcode_to_mem_arm(x)
+#define __mem_to_opcode_thumb16(x) __opcode_to_mem_thumb16(x)
+#ifndef CONFIG_CPU_ENDIAN_BE32
+#define __mem_to_opcode_thumb32(x) __opcode_to_mem_thumb32(x)
+#endif
+
+/* Operations specific to Thumb opcodes */
+
+/* Instruction size checks: */
+#define __opcode_is_thumb32(x) (		\
+	   ((x) & 0xF8000000) == 0xE8000000	\
+	|| ((x) & 0xF0000000) == 0xF0000000	\
+)
+#define __opcode_is_thumb16(x) (					\
+	   ((x) & 0xFFFF0000) == 0					\
+	&& !(((x) & 0xF800) == 0xE800 || ((x) & 0xF000) == 0xF000)	\
+)
+
+/* Operations to construct or split 32-bit Thumb instructions: */
+#define __opcode_thumb32_first(x) (___opcode_identity16((x) >> 16))
+#define __opcode_thumb32_second(x) (___opcode_identity16(x))
+#define __opcode_thumb32_compose(first, second) (			\
+	  (___opcode_identity32(___opcode_identity16(first)) << 16)	\
+	| ___opcode_identity32(___opcode_identity16(second))		\
+)
+#define ___asm_opcode_thumb32_first(x) (___asm_opcode_identity16((x) >> 16))
+#define ___asm_opcode_thumb32_second(x) (___asm_opcode_identity16(x))
+#define ___asm_opcode_thumb32_compose(first, second) (			    \
+	  (___asm_opcode_identity32(___asm_opcode_identity16(first)) << 16) \
+	| ___asm_opcode_identity32(___asm_opcode_identity16(second))	    \
+)
+
+/*
+ * Opcode injection helpers
+ *
+ * In rare cases it is necessary to assemble an opcode which the
+ * assembler does not support directly, or which would normally be
+ * rejected because of the CFLAGS or AFLAGS used to build the affected
+ * file.
+ *
+ * Before using these macros, consider carefully whether it is feasible
+ * instead to change the build flags for your file, or whether it really
+ * makes sense to support old assembler versions when building that
+ * particular kernel feature.
+ *
+ * The macros defined here should only be used where there is no viable
+ * alternative.
+ *
+ *
+ * __inst_arm(x): emit the specified ARM opcode
+ * __inst_thumb16(x): emit the specified 16-bit Thumb opcode
+ * __inst_thumb32(x): emit the specified 32-bit Thumb opcode
+ *
+ * __inst_arm_thumb16(arm, thumb): emit either the specified arm or
+ *	16-bit Thumb opcode, depending on whether an ARM or Thumb-2
+ *	kernel is being built
+ *
+ * __inst_arm_thumb32(arm, thumb): emit either the specified arm or
+ *	32-bit Thumb opcode, depending on whether an ARM or Thumb-2
+ *	kernel is being built
+ *
+ *
+ * Note that using these macros directly is poor practice.  Instead, you
+ * should use them to define human-readable wrapper macros to encode the
+ * instructions that you care about.  In code which might run on ARMv7 or
+ * above, you can usually use the __inst_arm_thumb{16,32} macros to
+ * specify the ARM and Thumb alternatives at the same time.  This ensures
+ * that the correct opcode gets emitted depending on the instruction set
+ * used for the kernel build.
+ *
+ * Look at opcodes-virt.h for an example of how to use these macros.
+ */
+#include <linux/stringify.h>
+
+#define __inst_arm(x) ___inst_arm(___asm_opcode_to_mem_arm(x))
+#define __inst_thumb32(x) ___inst_thumb32(				\
+	___asm_opcode_to_mem_thumb16(___asm_opcode_thumb32_first(x)),	\
+	___asm_opcode_to_mem_thumb16(___asm_opcode_thumb32_second(x))	\
+)
+#define __inst_thumb16(x) ___inst_thumb16(___asm_opcode_to_mem_thumb16(x))
+
+#ifdef CONFIG_THUMB2_BAREBOX
+#define __inst_arm_thumb16(arm_opcode, thumb_opcode) \
+	__inst_thumb16(thumb_opcode)
+#define __inst_arm_thumb32(arm_opcode, thumb_opcode) \
+	__inst_thumb32(thumb_opcode)
+#else
+#define __inst_arm_thumb16(arm_opcode, thumb_opcode) __inst_arm(arm_opcode)
+#define __inst_arm_thumb32(arm_opcode, thumb_opcode) __inst_arm(arm_opcode)
+#endif
+
+/* Helpers for the helpers.  Don't use these directly. */
+#ifdef __ASSEMBLY__
+#define ___inst_arm(x) .long x
+#define ___inst_thumb16(x) .short x
+#define ___inst_thumb32(first, second) .short first, second
+#else
+#define ___inst_arm(x) ".long " __stringify(x) "\n\t"
+#define ___inst_thumb16(x) ".short " __stringify(x) "\n\t"
+#define ___inst_thumb32(first, second) \
+	".short " __stringify(first) ", " __stringify(second) "\n\t"
+#endif
+
+#endif /* __ASM_ARM_OPCODES_H */
-- 
2.16.1



From l.stach at pengutronix.de  Mon Mar 26 12:20:18 2018
From: l.stach at pengutronix.de (Lucas Stach)
Date: Mon, 26 Mar 2018 21:20:18 +0200
Subject: [PATCH v3 03/10] ARM: allow secure monitor code to be built without
 PSCI
In-Reply-To: <20180326192025.28809-1-l.stach@pengutronix.de>
References: <20180326192025.28809-1-l.stach@pengutronix.de>
Message-ID: <20180326192025.28809-3-l.stach@pengutronix.de>

The hyp mode handling added in the secure monitor code is also useful
when Barebox doesn't have PSCI control. Allow to build without PSCI.

Signed-off-by: Lucas Stach <l.stach at pengutronix.de>
Tested-by: Roland Hieber <r.hieber at pengutronix.de>
---
 arch/arm/cpu/sm_as.S | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/cpu/sm_as.S b/arch/arm/cpu/sm_as.S
index 09580e75de5f..0d01e1bf2435 100644
--- a/arch/arm/cpu/sm_as.S
+++ b/arch/arm/cpu/sm_as.S
@@ -129,7 +129,9 @@ secure_monitor:
 	sub	sp, sp, #4*4			@ allocate result structure on stack
 	mov	r12, sp
 	push	{r4-r6, r12}
+#ifdef CONFIG_ARM_PSCI
 	bl	psci_entry
+#endif
 	pop	{r4-r6, r12}
 	ldm	r12, {r0-r3}
 	add	sp, sp, #4*4
@@ -163,6 +165,8 @@ ENTRY(psci_cpu_entry)
 	mcr	p15, 0, r0, c1, c0, 1	@ ACTLR
 
 	bl	secure_monitor_stack_setup
+#ifdef CONFIG_ARM_PSCI
 	bl	psci_cpu_entry_c
+#endif
 
 ENDPROC(psci_cpu_entry)
-- 
2.16.1



From l.stach at pengutronix.de  Mon Mar 26 12:20:20 2018
From: l.stach at pengutronix.de (Lucas Stach)
Date: Mon, 26 Mar 2018 21:20:20 +0200
Subject: [PATCH v3 05/10] ARM: don't try to install secure monitor when
 entered in HYP mode
In-Reply-To: <20180326192025.28809-1-l.stach@pengutronix.de>
References: <20180326192025.28809-1-l.stach@pengutronix.de>
Message-ID: <20180326192025.28809-5-l.stach@pengutronix.de>

When Barebox has been entered in HYP mode, the CPU is already switched
to the non-secure world and it's not possible for Barebox to install
it's own secure monitor.

Signed-off-by: Lucas Stach <l.stach at pengutronix.de>
Tested-by: Roland Hieber <r.hieber at pengutronix.de>
---
 arch/arm/cpu/sm.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/cpu/sm.c b/arch/arm/cpu/sm.c
index 5808dfd92bdc..71bb394c8540 100644
--- a/arch/arm/cpu/sm.c
+++ b/arch/arm/cpu/sm.c
@@ -184,6 +184,9 @@ int armv7_secure_monitor_install(void)
 		return -EINVAL;
 	}
 
+	if (__boot_cpu_mode == HYP_MODE)
+		return 0;
+
 	mmuon = get_cr() & CR_M;
 
 	vbar = get_vbar();
-- 
2.16.1



From l.stach at pengutronix.de  Mon Mar 26 12:20:25 2018
From: l.stach at pengutronix.de (Lucas Stach)
Date: Mon, 26 Mar 2018 21:20:25 +0200
Subject: [PATCH v3 10/10] ARM: rpi: autosize malloc area
In-Reply-To: <20180326192025.28809-1-l.stach@pengutronix.de>
References: <20180326192025.28809-1-l.stach@pengutronix.de>
Message-ID: <20180326192025.28809-10-l.stach@pengutronix.de>

Autosize the malloc area according to the available RAM size.

Signed-off-by: Lucas Stach <l.stach at pengutronix.de>
Tested-by: Roland Hieber <r.hieber at pengutronix.de>
---
 arch/arm/configs/rpi_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/configs/rpi_defconfig b/arch/arm/configs/rpi_defconfig
index cd88b4ac751c..2bb615849324 100644
--- a/arch/arm/configs/rpi_defconfig
+++ b/arch/arm/configs/rpi_defconfig
@@ -7,6 +7,7 @@ CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
 CONFIG_ARM_UNWIND=y
 CONFIG_IMAGE_COMPRESSION_NONE=y
 CONFIG_MMU=y
+CONFIG_MALLOC_SIZE=0x0
 CONFIG_MALLOC_TLSF=y
 CONFIG_KALLSYMS=y
 CONFIG_PROMPT="R-Pi> "
-- 
2.16.1



From l.stach at pengutronix.de  Mon Mar 26 12:20:21 2018
From: l.stach at pengutronix.de (Lucas Stach)
Date: Mon, 26 Mar 2018 21:20:21 +0200
Subject: [PATCH v3 06/10] ARM: default to starting kernel in HYP mode when
 entered in HYP
In-Reply-To: <20180326192025.28809-1-l.stach@pengutronix.de>
References: <20180326192025.28809-1-l.stach@pengutronix.de>
Message-ID: <20180326192025.28809-6-l.stach@pengutronix.de>

When Barebox has been entered in HYP mode, there is a high chance that
the kernel is  intended to be started in HYP mode also. Get this
default into place.

Signed-off-by: Lucas Stach <l.stach at pengutronix.de>
Tested-by: Roland Hieber <r.hieber at pengutronix.de>
---
 arch/arm/cpu/sm.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/cpu/sm.c b/arch/arm/cpu/sm.c
index 71bb394c8540..3369fbb5ff1a 100644
--- a/arch/arm/cpu/sm.c
+++ b/arch/arm/cpu/sm.c
@@ -264,6 +264,9 @@ static int sm_init(void)
 				  bootm_secure_state_names,
 				  ARRAY_SIZE(bootm_secure_state_names));
 
+	if (__boot_cpu_mode == HYP_MODE)
+		bootm_secure_state = ARM_STATE_HYP;
+
 	return 0;
 }
 device_initcall(sm_init);
\ No newline at end of file
-- 
2.16.1



From l.stach at pengutronix.de  Mon Mar 26 12:20:22 2018
From: l.stach at pengutronix.de (Lucas Stach)
Date: Mon, 26 Mar 2018 21:20:22 +0200
Subject: [PATCH v3 07/10] ARM: install HYP vectors at PBL and Barebox entry
In-Reply-To: <20180326192025.28809-1-l.stach@pengutronix.de>
References: <20180326192025.28809-1-l.stach@pengutronix.de>
Message-ID: <20180326192025.28809-7-l.stach@pengutronix.de>

If the CPU was already in HYP mode when entering the PBL, install a
simple trap handler to allow to get back from SVC to HYP before
switching to HYP mode.

As the vectors are part of the currently running binary, we need to
do the same setup when starting the real Barebox binary, as the PBL
setup vectors might get overwritten. To do this we trap into HYP mode
just before jumping to Barebox and then re-do the vector setup and
SVC switch as the first thing in Barebox proper.

Signed-off-by: Lucas Stach <l.stach at pengutronix.de>
Tested-by: Roland Hieber <r.hieber at pengutronix.de>
---
 arch/arm/cpu/lowlevel.S   | 3 +++
 arch/arm/cpu/start-pbl.c  | 4 ++++
 arch/arm/cpu/start.c      | 3 +++
 arch/arm/cpu/uncompress.c | 4 ++++
 4 files changed, 14 insertions(+)

diff --git a/arch/arm/cpu/lowlevel.S b/arch/arm/cpu/lowlevel.S
index 43665981e48b..13dfe496ad17 100644
--- a/arch/arm/cpu/lowlevel.S
+++ b/arch/arm/cpu/lowlevel.S
@@ -8,6 +8,9 @@ ENTRY(arm_cpu_lowlevel_init)
 	/* save lr, since it may be banked away with a processor mode change */
 	mov	r2, lr
 
+	/* careful: the hyp install corrupts r0 and r1 */
+	bl	__hyp_install
+
 	/* set the cpu to SVC32 mode, mask irq and fiq */
 	mrs	r12, cpsr
 	eor	r12, r12, #HYP_MODE
diff --git a/arch/arm/cpu/start-pbl.c b/arch/arm/cpu/start-pbl.c
index e851b4a2da5e..e0793579e2e8 100644
--- a/arch/arm/cpu/start-pbl.c
+++ b/arch/arm/cpu/start-pbl.c
@@ -26,6 +26,7 @@
 #include <asm/barebox-arm-head.h>
 #include <asm-generic/memory_layout.h>
 #include <asm/sections.h>
+#include <asm/secure.h>
 #include <asm/pgtable.h>
 #include <asm/cache.h>
 #include <asm/unaligned.h>
@@ -100,5 +101,8 @@ __noreturn void barebox_single_pbl_start(unsigned long membase,
 	else
 		barebox = (void *)barebox_base;
 
+	if (__boot_cpu_mode == HYP_MODE)
+		armv7_switch_to_hyp();
+
 	barebox(membase, memsize, boarddata);
 }
diff --git a/arch/arm/cpu/start.c b/arch/arm/cpu/start.c
index 171e6ad0eb7a..a0db6436f387 100644
--- a/arch/arm/cpu/start.c
+++ b/arch/arm/cpu/start.c
@@ -24,6 +24,7 @@
 #include <asm/barebox-arm-head.h>
 #include <asm-generic/memory_layout.h>
 #include <asm/sections.h>
+#include <asm/secure.h>
 #include <asm/unaligned.h>
 #include <asm/cache.h>
 #include <memory.h>
@@ -145,6 +146,8 @@ __noreturn void barebox_non_pbl_start(unsigned long membase,
 	unsigned long malloc_start, malloc_end;
 	unsigned long barebox_size = barebox_image_size + MAX_BSS_SIZE;
 
+	armv7_hyp_install();
+
 	if (IS_ENABLED(CONFIG_RELOCATABLE)) {
 		unsigned long barebox_base = arm_mem_barebox_image(membase,
 								   endmem,
diff --git a/arch/arm/cpu/uncompress.c b/arch/arm/cpu/uncompress.c
index 9d7fe0e921a9..28636aa8101f 100644
--- a/arch/arm/cpu/uncompress.c
+++ b/arch/arm/cpu/uncompress.c
@@ -27,6 +27,7 @@
 #include <asm/barebox-arm-head.h>
 #include <asm-generic/memory_layout.h>
 #include <asm/sections.h>
+#include <asm/secure.h>
 #include <asm/pgtable.h>
 #include <asm/cache.h>
 #include <asm/unaligned.h>
@@ -109,5 +110,8 @@ void __noreturn barebox_multi_pbl_start(unsigned long membase,
 
 	pr_debug("jumping to uncompressed image at 0x%p\n", barebox);
 
+	if (__boot_cpu_mode == HYP_MODE)
+		armv7_switch_to_hyp();
+
 	barebox(membase, memsize, boarddata);
 }
-- 
2.16.1



From l.stach at pengutronix.de  Mon Mar 26 12:20:19 2018
From: l.stach at pengutronix.de (Lucas Stach)
Date: Mon, 26 Mar 2018 21:20:19 +0200
Subject: [PATCH v3 04/10] ARM: add file for HYP mode related setup
In-Reply-To: <20180326192025.28809-1-l.stach@pengutronix.de>
References: <20180326192025.28809-1-l.stach@pengutronix.de>
Message-ID: <20180326192025.28809-4-l.stach@pengutronix.de>

This adds routines to add hyp mode vectors and switch back to HYP
mode from SVC. This is needed in both the PBL and Barebox proper.

Signed-off-by: Lucas Stach <l.stach at pengutronix.de>
Tested-by: Roland Hieber <r.hieber at pengutronix.de>
---
v3:
- fix whitespace
- use __BARE_INIT
---
 arch/arm/cpu/Makefile         |   4 ++
 arch/arm/cpu/hyp.S            | 116 ++++++++++++++++++++++++++++++++++++++++++
 arch/arm/cpu/sm_as.S          |  11 ----
 arch/arm/include/asm/secure.h |   8 +++
 4 files changed, 128 insertions(+), 11 deletions(-)
 create mode 100644 arch/arm/cpu/hyp.S

diff --git a/arch/arm/cpu/Makefile b/arch/arm/cpu/Makefile
index 13fe12c31f6f..f86dff975bb4 100644
--- a/arch/arm/cpu/Makefile
+++ b/arch/arm/cpu/Makefile
@@ -9,6 +9,10 @@ obj-$(CONFIG_ARM_EXCEPTIONS) += exceptions.o
 obj-$(CONFIG_MMU) += mmu.o mmu-early.o
 pbl-$(CONFIG_MMU) += mmu-early.o
 lwl-y += lowlevel.o
+obj-y += hyp.o
+AFLAGS_hyp.o :=-Wa,-march=armv7-a -Wa,-mcpu=all
+pbl-y += hyp.o
+AFLAGS_pbl-hyp.o :=-Wa,-march=armv7-a -Wa,-mcpu=all
 endif
 
 obj-$(CONFIG_ARM_EXCEPTIONS) += interrupts.o
diff --git a/arch/arm/cpu/hyp.S b/arch/arm/cpu/hyp.S
new file mode 100644
index 000000000000..1314b56eab25
--- /dev/null
+++ b/arch/arm/cpu/hyp.S
@@ -0,0 +1,116 @@
+#include <linux/linkage.h>
+#include <asm/system.h>
+#include <asm/opcodes-virt.h>
+#include <init.h>
+
+.arch_extension sec
+.arch_extension virt
+
+__BARE_INIT
+
+.data
+	.align  2
+ENTRY(__boot_cpu_mode)
+	.long   0
+.text
+
+ENTRY(__hyp_install)
+	mrs	r12, cpsr
+	and	r12, r12, #MODE_MASK
+
+	@ Save the initial CPU state
+	adr	r0, .L__boot_cpu_mode_offset
+	ldr	r1, [r0]
+	str	r12, [r0, r1]
+
+	cmp	r12, #HYP_MODE
+	movne	pc, lr			@ give up if the CPU is not in HYP mode
+
+	@ Now install the hypervisor stub:
+	adr	r12, __hyp_vectors
+	mcr	p15, 4, r12, c12, c0, 0	@ set hypervisor vector base (HVBAR)
+
+	@ Disable all traps, so we don't get any nasty surprise
+	mov	r12, #0
+	mcr	p15, 4, r12, c1, c1, 0	@ HCR
+	mcr	p15, 4, r12, c1, c1, 2	@ HCPTR
+	mcr	p15, 4, r12, c1, c1, 3	@ HSTR
+
+THUMB(	orr	r12, #(1 << 30)	)	@ HSCTLR.TE
+	mcr	p15, 4, r12, c1, c0, 0	@ HSCTLR
+
+	mrc	p15, 4, r12, c1, c1, 1	@ HDCR
+	and	r12, #0x1f		@ Preserve HPMN
+	mcr	p15, 4, r12, c1, c1, 1	@ HDCR
+
+	@ Make sure NS-SVC is initialised appropriately
+	mrc	p15, 0, r12, c1, c0, 0	@ SCTLR
+	orr	r12, #(1 << 5)		@ CP15 barriers enabled
+	bic	r12, #(3 << 7)		@ Clear SED/ITD for v8 (RES0 for v7)
+	bic	r12, #(3 << 19)		@ WXN and UWXN disabled
+	mcr	p15, 0, r12, c1, c0, 0	@ SCTLR
+
+	mrc	p15, 0, r12, c0, c0, 0	@ MIDR
+	mcr	p15, 4, r12, c0, c0, 0	@ VPIDR
+
+	mrc	p15, 0, r12, c0, c0, 5	@ MPIDR
+	mcr	p15, 4, r12, c0, c0, 5	@ VMPIDR
+	bx	lr
+ENDPROC(__hyp_install)
+
+ENTRY(armv7_hyp_install)
+	mov	r2, lr
+
+	bl	__hyp_install
+
+	/* set the cpu to SVC32 mode, mask irq and fiq */
+	mrs	r12, cpsr
+	eor	r12, r12, #HYP_MODE
+	tst	r12, #MODE_MASK
+	bic	r12, r12, #MODE_MASK
+	orr	r12, r12, #(PSR_I_BIT | PSR_F_BIT | SVC_MODE)
+THUMB(	orr	r12, r12, #PSR_T_BIT	)
+	bne	1f
+	orr	r12, r12, #PSR_A_BIT
+	adr	lr, 2f
+	msr	spsr_cxsf, r12
+	__MSR_ELR_HYP(14)
+	__ERET
+1:	msr	cpsr_c, r12
+2:
+	mov	pc, r2
+ENDPROC(armv7_hyp_install)
+
+ENTRY(armv7_switch_to_hyp)
+	mov	r0, lr
+	mov	r1, sp		@ save SVC copy of LR and SP
+	isb
+	hvc #0			@ for older asm: .byte 0x70, 0x00, 0x40, 0xe1
+	mov	sp, r1
+	mov	lr, r0		@ restore SVC copy of LR and SP
+
+	bx	lr
+ENDPROC(armv7_switch_to_hyp)
+
+.align 2
+.L__boot_cpu_mode_offset:
+	.long	__boot_cpu_mode - .
+
+/* The HYP trap is crafted to match armv7_switch_to_hyp() */
+__hyp_do_trap:
+	mov lr, r0
+	mov sp, r1
+	bx  lr
+ENDPROC(__hyp_do_trap)
+
+.align 5
+__hyp_vectors:
+__hyp_reset:	W(b)	.
+__hyp_und:	W(b)	.
+__hyp_svc:	W(b)	.
+__hyp_pabort:	W(b)	.
+__hyp_dabort:	W(b)	.
+__hyp_trap:	W(b)	__hyp_do_trap
+__hyp_irq:	W(b)	.
+__hyp_fiq:	W(b)	.
+ENDPROC(__hyp_vectors)
diff --git a/arch/arm/cpu/sm_as.S b/arch/arm/cpu/sm_as.S
index 0d01e1bf2435..de6cd0406f4f 100644
--- a/arch/arm/cpu/sm_as.S
+++ b/arch/arm/cpu/sm_as.S
@@ -148,17 +148,6 @@ hyp_trap:
         mov pc, lr                              @ do no switch modes, but
                                                 @ return to caller
 
-ENTRY(armv7_switch_to_hyp)
-	mov	r0, lr
-	mov	r1, sp		@ save SVC copy of LR and SP
-	isb
-	hvc #0			@ for older asm: .byte 0x70, 0x00, 0x40, 0xe1
-	mov	sp, r1
-	mov	lr, r0		@ restore SVC copy of LR and SP
-
-	bx	lr
-ENDPROC(armv7_switch_to_hyp)
-
 ENTRY(psci_cpu_entry)
 	mrc	p15, 0, r0, c1, c0, 1	@ ACTLR
 	orr	r0, r0, #(1 << 6)	@ Set SMP bit
diff --git a/arch/arm/include/asm/secure.h b/arch/arm/include/asm/secure.h
index a4cb1f6c1c44..4eb2c3ec3011 100644
--- a/arch/arm/include/asm/secure.h
+++ b/arch/arm/include/asm/secure.h
@@ -5,9 +5,17 @@
 
 int armv7_secure_monitor_install(void);
 int __armv7_secure_monitor_install(void);
+
+#ifndef CONFIG_CPU_V8
 void armv7_switch_to_hyp(void);
+void armv7_hyp_install(void);
+#else
+static inline void armv7_switch_to_hyp(void) { };
+static inline void armv7_hyp_install(void) { };
+#endif
 
 extern unsigned char secure_monitor_init_vectors[];
+extern int __boot_cpu_mode;
 
 enum arm_security_state {
 	ARM_STATE_SECURE,
-- 
2.16.1



From s.trumtrar at pengutronix.de  Mon Mar 26 22:31:29 2018
From: s.trumtrar at pengutronix.de (Steffen Trumtrar)
Date: Tue, 27 Mar 2018 07:31:29 +0200
Subject: socfpga: ethernet problem
In-Reply-To: <20180326102037.57959f6175c61967d9e9c5b4@gmail.com>
References: <20180326102037.57959f6175c61967d9e9c5b4@gmail.com>
Message-ID: <73in9it77y.fsf@pengutronix.de>


Hi,

Antony Pavlov <antonynpavlov at gmail.com> writes:

> Hi!
>
> Barebox for DE0-Nano-SoC succesfully starts on Terasic DE10-Nano board
> but there is an ethernet issue.
>
> After `make ARCH=arm socfpga_defconfig` I see that the CONFIG_DRIVER_NET_DESIGNWARE_SOCFPGA
> option is disabled.
>
>   #
>   # Network drivers
>   #
>   ...
>   CONFIG_DRIVER_NET_DESIGNWARE=y
>   # CONFIG_DRIVER_NET_DESIGNWARE_GENERIC is not set
>   # CONFIG_DRIVER_NET_DESIGNWARE_SOCFPGA is not set
>
> after enabling CONFIG_DRIVER_NET_DESIGNWARE_SOCFPGA I see 'Could not get sysmgr-syscon node'
> error message:
>
>

Patch opportunity:

DRIVER_NET_DESIGNWARE_SOCFPGA is missing a
    select MFD_SYSCON

and the defconfig should be regenerated with the socfpga driver instead.

Best regards,
Steffen

-- 
Pengutronix e.K.                           | Steffen Trumtrar            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From antonynpavlov at gmail.com  Tue Mar 27 00:17:16 2018
From: antonynpavlov at gmail.com (Antony Pavlov)
Date: Tue, 27 Mar 2018 10:17:16 +0300
Subject: [PATCH] fs: check pointer returned by get_fsdevice_by_path
 before dereferencing
In-Reply-To: <20180318222236.28296-1-gael.portay@savoirfairelinux.com>
References: <20180318222236.28296-1-gael.portay@savoirfairelinux.com>
Message-ID: <20180327101716.697486501ccea51c7b98644a@gmail.com>

On Sun, 18 Mar 2018 18:22:36 -0400
Ga?l PORTAY <gael.portay at savoirfairelinux.com> wrote:

> In __canonicalize_path() we dereference the pointer returned by
> get_fsdevice_by_path() without checking if the pointer is NULL or not.
> When the pointer is NULL it leads to an Ooops.
> 
> 	Ooops, address error on load or ifetch!
> 
> 	$ 0   : 00000000 00000001 a0000026 a0811c10
> 	$ 4   : a0402e60 a0402e48 a0811c00 a0402e58
> 	$ 8   : 00000001 00000000 0000005a 00000023
> 	$12   : 00000000 00000002 00601021 00000000
> 	$16   : a0402e60 a0402e50 a0402e39 a0810000
> 	$20   : a0402e38 a0811420 a0811424 00000000
> 	$24   : 00000000 a080de10
> 	$28   : 87f87d40 a03ffa68 a0810000 a080ce30
> 	Hi    : 00000002
> 	Lo    : 00000000
> 	epc   : a080ce34

Salut Ga?l!

It looks like you use MIPS board.
Your epc == 0xa080ce34 is inside KSEG1 region (uncached memory).
May be there is no cache support in current barebox for your CPU.
Which CPU core you use?

Tr?s cordialement,
? Antony Pavlov

> 	ra    : a080ce30
> 	Status: 00000006
> 	Cause : 40008010
> 	Config: 80040483
> 
> 	### ERROR ### Please RESET the board ###
> 
> Fixes: d79a81736 fs: Don't bother filesystems without link support with additional stat() calls
> 
> Signed-off-by: Ga?l PORTAY <gael.portay at savoirfairelinux.com>
> ---
>  fs/fs.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/fs/fs.c b/fs/fs.c
> index 88f0b1478..5135112c8 100644
> --- a/fs/fs.c
> +++ b/fs/fs.c
> @@ -191,7 +191,7 @@ static char *__canonicalize_path(const char *_pathname, int level)
>  		 * with an additional stat() call.
>  		 */
>  		fsdev = get_fsdevice_by_path(outpath);
> -		if (!fsdev->driver->readlink)
> +		if (!fsdev || !fsdev->driver->readlink)
>  			continue;
>  
>  		ret = __lstat(outpath, &s);
> -- 
> 2.16.1
> 
> 
> _______________________________________________
> barebox mailing list
> barebox at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/barebox



From antonynpavlov at gmail.com  Tue Mar 27 02:21:38 2018
From: antonynpavlov at gmail.com (Antony Pavlov)
Date: Tue, 27 Mar 2018 12:21:38 +0300
Subject: socfpga: ethernet problem
In-Reply-To: <73in9it77y.fsf@pengutronix.de>
References: <20180326102037.57959f6175c61967d9e9c5b4@gmail.com>
 <73in9it77y.fsf@pengutronix.de>
Message-ID: <20180327122138.f276a11592e3fc167218af00@gmail.com>

On Tue, 27 Mar 2018 07:31:29 +0200
Steffen Trumtrar <s.trumtrar at pengutronix.de> wrote:

> 
> Hi,
> 
> Antony Pavlov <antonynpavlov at gmail.com> writes:
> 
> > Hi!
> >
> > Barebox for DE0-Nano-SoC succesfully starts on Terasic DE10-Nano board
> > but there is an ethernet issue.
> >
> > After `make ARCH=arm socfpga_defconfig` I see that the CONFIG_DRIVER_NET_DESIGNWARE_SOCFPGA
> > option is disabled.
> >
> >   #
> >   # Network drivers
> >   #
> >   ...
> >   CONFIG_DRIVER_NET_DESIGNWARE=y
> >   # CONFIG_DRIVER_NET_DESIGNWARE_GENERIC is not set
> >   # CONFIG_DRIVER_NET_DESIGNWARE_SOCFPGA is not set
> >
> > after enabling CONFIG_DRIVER_NET_DESIGNWARE_SOCFPGA I see 'Could not get sysmgr-syscon node'
> > error message:
> >
> >
> 
> Patch opportunity:
> 
> DRIVER_NET_DESIGNWARE_SOCFPGA is missing a
>     select MFD_SYSCON
> 
> and the defconfig should be regenerated with the socfpga driver instead.
> 

I made changes you suggest. Now ethernet works!

Many thanks!

Now I still have some minor issues with DE10-Nano:

  * socfpga-xload-2_defconfig does not work but socfpga-xload_defconfig does;
  * 'sleep 1' longs for 5 seconds.

I suppose that DE10-Nano is somewhat differ with DE0-Nano-SoC.

-- 
Best regards,
? Antony Pavlov


From s.hauer at pengutronix.de  Thu Mar 29 00:02:05 2018
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Thu, 29 Mar 2018 09:02:05 +0200
Subject: [PATCH] of: partition: fix typo when writing #address-cells
In-Reply-To: <20180326142556.27727-1-p.zabel@pengutronix.de>
References: <20180326142556.27727-1-p.zabel@pengutronix.de>
Message-ID: <20180329070205.dfiivafh5xghupvs@pengutronix.de>

On Mon, Mar 26, 2018 at 04:25:56PM +0200, Philipp Zabel wrote:
> On > 4 GiB eMMC devices, barebox writes a 32-bit address and a 64-bit
> size into the partition reg property, because #address-cells is
> accidentally written as '#addres-cells'. This causes a fallback to
> 32-bit address size. Fix the typo and thereby of_partition_fixup for
> 64-bit partitions.
> 
> Fixes: a2fa18f9f483 ("mtd: of: Make used partition binding configurable")
> Signed-off-by: Philipp Zabel <p.zabel at pengutronix.de>
> ---
>  drivers/of/partition.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)

Applied, thanks

Sascha

> 
> diff --git a/drivers/of/partition.c b/drivers/of/partition.c
> index 6f9651a9e4..aa6e601b7f 100644
> --- a/drivers/of/partition.c
> +++ b/drivers/of/partition.c
> @@ -190,7 +190,7 @@ static int of_partition_fixup(struct device_node *root, void *ctx)
>  	if (ret)
>  		return ret;
>  
> -	of_property_write_u32(partnode, "#addres-cells", n_cells);
> +	of_property_write_u32(partnode, "#address-cells", n_cells);
>  	if (ret)
>  		return ret;
>  
> -- 
> 2.16.1
> 
> 
> _______________________________________________
> barebox mailing list
> barebox at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/barebox
> 

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From andrew.smirnov at gmail.com  Sat Mar 31 18:13:54 2018
From: andrew.smirnov at gmail.com (Andrey Smirnov)
Date: Sat, 31 Mar 2018 18:13:54 -0700
Subject: [PATCH 0/3] APBH DMA fixes for i.MX7
Message-ID: <20180401011358.11621-1-andrew.smirnov@gmail.com>

Hi everyone:

The following two patches are to fix a case of broken boot I
discovered when I built a mult-image build for i.MX6 and i.MX7 and
tried to boot it on my i.MX7 SabreSD board.

Let me know if anything needs changing.

Thanks,
Andrey Smirnov

Andrey Smirnov (3):
  clk: i.MX7: Port NAND clock setup code from Linux
  clk: Forward declare struct of_device_id in linux/clk.h
  dma: apbh: Enable clock as a part of probing

 drivers/clk/imx/clk-imx7.c |  5 +++--
 drivers/clk/imx/clk.h      |  7 +++++++
 drivers/dma/apbh_dma.c     | 13 +++++++++++++
 include/linux/clk.h        |  1 +
 4 files changed, 24 insertions(+), 2 deletions(-)

-- 
2.14.3



From andrew.smirnov at gmail.com  Sat Mar 31 18:13:56 2018
From: andrew.smirnov at gmail.com (Andrey Smirnov)
Date: Sat, 31 Mar 2018 18:13:56 -0700
Subject: [PATCH 2/3] clk: Forward declare struct of_device_id in linux/clk.h
In-Reply-To: <20180401011358.11621-1-andrew.smirnov@gmail.com>
References: <20180401011358.11621-1-andrew.smirnov@gmail.com>
Message-ID: <20180401011358.11621-3-andrew.smirnov@gmail.com>

Forward declare struct of_device_id in linux/clk.h in order to avoid
warnings like the following:

warning: 'struct of_device_id' declared inside parameter list will not be visible outside
of this definition or declaration
 int of_clk_init(struct device_node *root, const struct of_device_id *matches);
                                                        ^~~~~~~~~~~~

Signed-off-by: Andrey Smirnov <andrew.smirnov at gmail.com>
---
 include/linux/clk.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/linux/clk.h b/include/linux/clk.h
index 081a85972..c6465b1c9 100644
--- a/include/linux/clk.h
+++ b/include/linux/clk.h
@@ -323,6 +323,7 @@ struct clk *clk_register_composite(const char *name,
 
 struct device_node;
 struct of_phandle_args;
+struct of_device_id;
 
 #if defined(CONFIG_COMMON_CLK_OF_PROVIDER)
 
-- 
2.14.3



From andrew.smirnov at gmail.com  Sat Mar 31 18:13:57 2018
From: andrew.smirnov at gmail.com (Andrey Smirnov)
Date: Sat, 31 Mar 2018 18:13:57 -0700
Subject: [PATCH 3/3] dma: apbh: Enable clock as a part of probing
In-Reply-To: <20180401011358.11621-1-andrew.smirnov@gmail.com>
References: <20180401011358.11621-1-andrew.smirnov@gmail.com>
Message-ID: <20180401011358.11621-4-andrew.smirnov@gmail.com>

Enable clock as a part of probing in order to avoid problems on SoCs
that do not have this block ungated out of reset (e.g. i.MX7).

Signed-off-by: Andrey Smirnov <andrew.smirnov at gmail.com>
---
 drivers/dma/apbh_dma.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/drivers/dma/apbh_dma.c b/drivers/dma/apbh_dma.c
index b84c0f798..79f25109f 100644
--- a/drivers/dma/apbh_dma.c
+++ b/drivers/dma/apbh_dma.c
@@ -17,6 +17,7 @@
 
 #include <dma/apbh-dma.h>
 #include <stmp-device.h>
+#include <linux/clk.h>
 #include <linux/list.h>
 #include <linux/err.h>
 #include <common.h>
@@ -55,6 +56,7 @@ enum mxs_dma_id {
 
 struct apbh_dma {
 	void __iomem *regs;
+	struct clk *clk;
 	enum mxs_dma_id id;
 };
 
@@ -606,6 +608,17 @@ static int apbh_dma_probe(struct device_d *dev)
 
 	apbh->id = id;
 
+	apbh->clk = clk_get(dev, NULL);
+	if (IS_ERR(apbh->clk))
+		return PTR_ERR(apbh->clk);
+
+	ret = clk_enable(apbh->clk);
+	if (ret) {
+		dev_err(dev, "Failed to enable clock: %s\n",
+			strerror(ret));
+		return ret;
+	}
+
 	ret = stmp_reset_block(apbh->regs, 0);
 	if (ret)
 		return ret;
-- 
2.14.3



From andrew.smirnov at gmail.com  Sat Mar 31 18:13:55 2018
From: andrew.smirnov at gmail.com (Andrey Smirnov)
Date: Sat, 31 Mar 2018 18:13:55 -0700
Subject: [PATCH 1/3] clk: i.MX7: Port NAND clock setup code from Linux
In-Reply-To: <20180401011358.11621-1-andrew.smirnov@gmail.com>
References: <20180401011358.11621-1-andrew.smirnov@gmail.com>
Message-ID: <20180401011358.11621-2-andrew.smirnov@gmail.com>

Port Linux kernel commit 22039d150f716e4e ("clk: imx7d: create clocks
behind rawnand clock gate") in order to correctly initialize clocks
necessary for APBH DMA block to be functional on i.MX7

Signed-off-by: Andrey Smirnov <andrew.smirnov at gmail.com>
---
 drivers/clk/imx/clk-imx7.c | 5 +++--
 drivers/clk/imx/clk.h      | 7 +++++++
 2 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/imx/clk-imx7.c b/drivers/clk/imx/clk-imx7.c
index b79c8c301..548f86cbe 100644
--- a/drivers/clk/imx/clk-imx7.c
+++ b/drivers/clk/imx/clk-imx7.c
@@ -676,7 +676,7 @@ static int imx7_ccm_probe(struct device_d *dev)
 	clks[IMX7D_ENET2_TIME_ROOT_DIV] = imx_clk_divider2("enet2_time_post_div", "enet2_time_pre_div", base + 0xa880, 0, 6);
 	clks[IMX7D_ENET_PHY_REF_ROOT_DIV] = imx_clk_divider2("enet_phy_ref_post_div", "enet_phy_ref_pre_div", base + 0xa900, 0, 6);
 	clks[IMX7D_EIM_ROOT_DIV] = imx_clk_divider2("eim_post_div", "eim_pre_div", base + 0xa980, 0, 6);
-	clks[IMX7D_NAND_ROOT_DIV] = imx_clk_divider2("nand_post_div", "nand_pre_div", base + 0xaa00, 0, 6);
+	clks[IMX7D_NAND_ROOT_CLK] = imx_clk_divider2("nand_root_clk", "nand_pre_div", base + 0xaa00, 0, 6);
 	clks[IMX7D_QSPI_ROOT_DIV] = imx_clk_divider2("qspi_post_div", "qspi_pre_div", base + 0xaa80, 0, 6);
 	clks[IMX7D_USDHC1_ROOT_DIV] = imx_clk_divider2("usdhc1_post_div", "usdhc1_pre_div", base + 0xab00, 0, 6);
 	clks[IMX7D_USDHC2_ROOT_DIV] = imx_clk_divider2("usdhc2_post_div", "usdhc2_pre_div", base + 0xab80, 0, 6);
@@ -751,7 +751,8 @@ static int imx7_ccm_probe(struct device_d *dev)
 	clks[IMX7D_ENET_PHY_REF_ROOT_CLK] = imx_clk_gate4("enet_phy_ref_root_clk", "enet_phy_ref_post_div", base + 0x4520, 0);
 
 	clks[IMX7D_EIM_ROOT_CLK] = imx_clk_gate4("eim_root_clk", "eim_post_div", base + 0x4160, 0);
-	clks[IMX7D_NAND_ROOT_CLK] = imx_clk_gate4("nand_root_clk", "nand_post_div", base + 0x4140, 0);
+	clks[IMX7D_NAND_RAWNAND_CLK] = imx_clk_gate2_shared2("nand_rawnand_clk", "nand_root_clk", base + 0x4140, 0);
+	clks[IMX7D_NAND_USDHC_BUS_RAWNAND_CLK] = imx_clk_gate2_shared2("nand_usdhc_rawnand_clk", "nand_usdhc_root_clk", base + 0x4140, 0);	
 	clks[IMX7D_QSPI_ROOT_CLK] = imx_clk_gate4("qspi_root_clk", "qspi_post_div", base + 0x4150, 0);
 	clks[IMX7D_USB_CTRL_CLK] = imx_clk_gate4("usb_ctrl_clk", "osc", base + 0x4680, 0);
 	clks[IMX7D_USB_PHY1_CLK] = imx_clk_gate4("usbphy1_clk", "osc", base + 0x46a0, 0);
diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h
index c46c2614d..71c6f459a 100644
--- a/drivers/clk/imx/clk.h
+++ b/drivers/clk/imx/clk.h
@@ -80,6 +80,13 @@ static inline struct clk *imx_clk_gate2(const char *name, const char *parent,
 	return clk_gate2(name, parent, reg, shift, 0x3, 0);
 }
 
+static inline struct clk *imx_clk_gate2_shared2(const char *name, const char *parent,
+						void __iomem *reg, u8 shift)
+{
+	return clk_gate2(name, parent, reg, shift, 0x3,
+			 CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE);
+}
+
 static inline struct clk *imx_clk_gate2_cgr(const char *name, const char *parent,
 					    void __iomem *reg, u8 shift, u8 cgr_val)
 {
-- 
2.14.3



From andrew.smirnov at gmail.com  Sat Mar 31 18:13:58 2018
From: andrew.smirnov at gmail.com (Andrey Smirnov)
Date: Sat, 31 Mar 2018 18:13:58 -0700
Subject: [PATCH] Revert "startup: Load default environment earlier"
In-Reply-To: <20180401011358.11621-1-andrew.smirnov@gmail.com>
References: <20180401011358.11621-1-andrew.smirnov@gmail.com>
Message-ID: <20180401011358.11621-5-andrew.smirnov@gmail.com>

From: Sascha Hauer <s.hauer at pengutronix.de>

Several boards use defaultenv_append_directory() to append a board
specific envfs snippet during runtime. This only works when
defaultenv_append_directory() is called before defaultenv_load() is
exectuted. Since that was executed at the end of the start process
every initcall level could be used to append a env directory. With this
patch only initcall levels earlier than fsdevice_initcall work and
most boards do not cope with this.

Revert this patch until a better solution is found.

Reported-by: Alexander Kurz <akurz at blala.de>

This reverts commit 5b92cfceff38f3a6462a21cf6b69159ad0ae9744.
---
 common/startup.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/common/startup.c b/common/startup.c
index 8940674528..8553849cb3 100644
--- a/common/startup.c
+++ b/common/startup.c
@@ -67,9 +67,6 @@ static int mount_root(void)
 		mount("none", "pstore", "/pstore", NULL);
 	}
 
-	if (IS_ENABLED(CONFIG_DEFAULT_ENVIRONMENT))
-		defaultenv_load("/env", 0);
-
 	return 0;
 }
 fs_initcall(mount_root);
@@ -82,6 +79,9 @@ static int load_environment(void)
 
 	default_environment_path = default_environment_path_get();
 
+	if (IS_ENABLED(CONFIG_DEFAULT_ENVIRONMENT))
+		defaultenv_load("/env", 0);
+
 	envfs_load(default_environment_path, "/env", 0);
 	nvvar_load();
 
-- 
2.16.1


