[PATCH v1 1/2] arm: arria10: enable errata 794072 and 845369

Oleksij Rempel o.rempel at pengutronix.de
Fri Jun 29 04:17:14 PDT 2018


This SoC is affected by this two any many other erratas.
So enable at least supported cases.

Signed-off-by: Oleksij Rempel <o.rempel at pengutronix.de>
---
 arch/arm/mach-socfpga/arria10-init.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/mach-socfpga/arria10-init.c b/arch/arm/mach-socfpga/arria10-init.c
index 07256da1db..f016b84bb7 100644
--- a/arch/arm/mach-socfpga/arria10-init.c
+++ b/arch/arm/mach-socfpga/arria10-init.c
@@ -14,6 +14,7 @@
 #include <mach/generic.h>
 #include <asm/io.h>
 #include <asm/cache-l2x0.h>
+#include <asm/errata.h>
 #include <asm/system.h>
 
 #define L310_AUX_CTRL_EARLY_BRESP		BIT(30)	/* R2P0+ */
@@ -70,6 +71,9 @@ static void arria10_initialize_security_policies(void)
 	/* BootROM leaves the L2X0 in a weird state. Always disable L2X0 for now. */
 	l2c310_disable(l2x0_base);
 
+	enable_arm_errata_794072_war();
+	enable_arm_errata_845369_war();
+
 	/* Put OCRAM in non-secure */
 	writel(0x003f0000, ARRIA10_NOC_FW_OCRAM_OCRAM_SCR_REGION0);
 	writel(0x1, ARRIA10_NOC_FW_OCRAM_OCRAM_SCR_EN);
-- 
2.17.1




More information about the barebox mailing list