[PATCH 2/4] pci: refactor bar configuration

[Uwe Kleine-König]

Instead of doing nearly the same three times for the three different
memory types, use some helper variables and do the same in a more
generic way only once.

Apart from minor changes in the pr_debug output there is no semantic
change intended.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig at pengutronix.de>
---
 drivers/pci/pci.c | 104 ++++++++++++++++++++++--------------------------------
 1 file changed, 43 insertions(+), 61 deletions(-)

diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 538903ee6607..87359b6de82c 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -169,8 +169,11 @@ static void setup_device(struct pci_dev *dev, int max_bar)
 			      cmd & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY));
 
 	for (bar = 0; bar < max_bar; bar++) {
-		resource_size_t last_addr;
-		u32 orig, barval, size;
+		u32 orig, barval, size, mask;
+		const char *type;
+		int restype;
+		unsigned long resflags;
+		resource_size_t *last;
 
 		pci_read_config_dword(dev, PCI_BASE_ADDRESS_0 + bar * 4, &orig);
 		pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + bar * 4, 0xfffffffe);
@@ -183,68 +186,47 @@ static void setup_device(struct pci_dev *dev, int max_bar)
 		}
 
 		if (barval & 0x01) { /* IO */
-			size = pci_size(orig, barval, 0xfffffffe);
-			if (!size) {
-				pr_debug("pbar%d bad IO mask\n", bar);
-				continue;
-			}
-			pr_debug("pbar%d: barval=%08x io %d bytes\n",
-				 bar, barval, size);
-			if (ALIGN(last_io, size) + size >
-			    dev->bus->resource[PCI_BUS_RESOURCE_IO]->end) {
-				pr_debug("BAR does not fit within bus IO res\n");
-				return;
-			}
-			last_io = ALIGN(last_io, size);
-			pr_debug("pbar%d: allocated at 0x%08x\n", bar, last_io);
-			pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + bar * 4, last_io);
-			dev->resource[bar].flags = IORESOURCE_IO;
-			last_addr = last_io;
-			last_io += size;
+			mask = 0xfffffffe;
+			type = "IO";
+			restype = PCI_BUS_RESOURCE_IO;
+			resflags = IORESOURCE_IO;
+			last = &last_io;
 		} else if ((barval & PCI_BASE_ADDRESS_MEM_PREFETCH) &&
-		           last_mem_pref) /* prefetchable MEM */ {
-			size = pci_size(orig, barval, 0xfffffff0);
-			if (!size) {
-				pr_debug("pbar%d bad P-MEM mask\n", bar);
-				continue;
-			}
-			pr_debug("pbar%d: barval=%08x P memory %d bytes\n",
-				 bar, barval, size);
-			if (ALIGN(last_mem_pref, size) + size >
-			    dev->bus->resource[PCI_BUS_RESOURCE_MEM_PREF]->end) {
-				pr_debug("BAR does not fit within bus p-mem res\n");
-				return;
-			}
-			last_mem_pref = ALIGN(last_mem_pref, size);
-			pr_debug("pbar%d: allocated at 0x%08x\n", bar, last_mem_pref);
-			pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + bar * 4, last_mem_pref);
-			dev->resource[bar].flags = IORESOURCE_MEM |
-			                           IORESOURCE_PREFETCH;
-			last_addr = last_mem_pref;
-			last_mem_pref += size;
-		} else { /* non-prefetch MEM */
-			size = pci_size(orig, barval, 0xfffffff0);
-			if (!size) {
-				pr_debug("pbar%d bad NP-MEM mask\n", bar);
-				continue;
-			}
-			pr_debug("pbar%d: barval=%08x NP memory %d bytes\n",
-				 bar, barval, size);
-			if (ALIGN(last_mem, size) + size >
-			    dev->bus->resource[PCI_BUS_RESOURCE_MEM]->end) {
-				pr_debug("BAR does not fit within bus np-mem res\n");
-				return;
-			}
-			last_mem = ALIGN(last_mem, size);
-			pr_debug("pbar%d: allocated at 0x%08x\n", bar, last_mem);
-			pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + bar * 4, last_mem);
-			dev->resource[bar].flags = IORESOURCE_MEM;
-			last_addr = last_mem;
-			last_mem += size;
+			   last_mem_pref) { /* prefetchable MEM */
+			mask = 0xfffffff0;
+			type = "P";
+			restype = PCI_BUS_RESOURCE_MEM_PREF;
+			resflags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
+			last = &last_mem_pref;
+		} else { /* non-prefetchable MEM */
+			mask = 0xfffffff0;
+			type = "NP";
+			restype = PCI_BUS_RESOURCE_MEM;
+			resflags = IORESOURCE_MEM;
+			last = &last_mem;
 		}
 
-		dev->resource[bar].start = last_addr;
-		dev->resource[bar].end = last_addr + size - 1;
+		size = pci_size(orig, barval, mask);
+		if (!size) {
+			pr_debug("pbar%d bad %s mask\n", bar, type);
+			continue;
+		}
+
+		pr_debug("pbar%d: barval=%08x type=%s size=0x%x\n",
+			 bar, barval, type, size);
+
+		if (ALIGN(*last, size) + size > dev->bus->resource[restype]->end) {
+			pr_debug("BAR does not fit within bus %s res\n", type);
+			return;
+		}
+
+		*last = ALIGN(*last, size);
+		pr_debug("pbar%d: allocated at 0x%08x\n", bar, *last);
+		pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + bar * 4, *last);
+		dev->resource[bar].flags = resflags;
+		dev->resource[bar].start = *last;
+		*last += size;
+		dev->resource[bar].end = *last - 1;
 
 		if ((barval & PCI_BASE_ADDRESS_MEM_TYPE_64)) {
 			dev->resource[bar].flags |= IORESOURCE_MEM_64;
-- 
2.16.3