[PATCH 15/16] i.MX6: PL310: Adjust settings for performance

[Andrey Smirnov]

According to commit f6b6f3c7b2bb7d6277801882afdced6f2b10fc17 from
git://git.freescale.com/imx/uboot-imx.git:

	Also set Prefetch offset to 15, since it improves
	memcpy performance by 35%. Don't enable Incr double
	Linefill enable since it adversely affects memcpy
	performance by about 32MB/s and reads by 90MB/s. Tested
	with 4K to 16MB sized src and dst aligned buffer.

This commit ports those chagnes from U-Boot.

Signed-off-by: Andrey Smirnov <andrew.smirnov at gmail.com>
---
 arch/arm/mach-imx/imx6.c | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-imx/imx6.c b/arch/arm/mach-imx/imx6.c
index 0c7338d..ba8fb89 100644
--- a/arch/arm/mach-imx/imx6.c
+++ b/arch/arm/mach-imx/imx6.c
@@ -223,8 +223,11 @@ static int imx6_mmu_init(void)
 	val = readl(l2x0_base + L2X0_PREFETCH_CTRL);
 	val |=  L2X0_DOUBLE_LINEFILL_EN |
 		L2X0_INSTRUCTION_PREFETCH_EN |
-		L2X0_DATA_PREFETCH_EN |
-		L2X0_INCR_DOUBLE_LINEFILL_EN;
+		L2X0_DATA_PREFETCH_EN;
+	/*
+	 * set prefetch offset to 15
+	 */
+	val |= 15;
 	/*
 	 * The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0
 	 * The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL is r3p2
@@ -236,8 +239,7 @@ static int imx6_mmu_init(void)
 	 */
 	if (cache_part == L2X0_CACHE_ID_PART_L310 &&
 	    cache_rtl < L2X0_CACHE_ID_RTL_R3P2)
-		val &= ~(L2X0_DOUBLE_LINEFILL_EN |
-			 L2X0_INCR_DOUBLE_LINEFILL_EN);
+		val &= ~L2X0_DOUBLE_LINEFILL_EN;
 
 	writel(val, l2x0_base + L2X0_PREFETCH_CTRL);
 
-- 
2.5.0