Barebox on small memory systems

[Trent Piepho]

I'm considering porting barebox to Altera's Arria10 SoC.  A key
difference from the existing Cyclone V support is that the SoC SDRAM
controller is part of the FPGA scanchain.  Which means that in order to
use SDRAM, the bootloader must load a file much larger than the maximum
bootloader size into the FPGA.

With Cyclone V the code needed to use SDRAM is a few kB, fits inside the
60 kB maximum bootloader size, and runs as part of the barebox PBL.  It
seems almost all other ARM SoC's also have SDRAM init code that is small
enough to fit inside barebox.  With Arria 10 the maximum bootloader size
is increased to 204 kB but the code/data needed to use SDRAM is several
MB.  So barebox will need to load it out of flash itself.

In order to get an image file out of flash and programmed into the FPGA,
it's useful to have a number of barebox drivers, like the MCI system,
partition table parsing, FAT filesystem, etc.  Basically getting the
full barebox (with a minimal set of drivers, e.g. no shell) running
without having SDRAM access.

So can one run barebox in 256 Kb?

A minimal config of a non-PBL non-relocatable barebox with the necessary
features is only about 54 Kb.  So that certainly fits.  But that doesn't
include stack, heap, bss, etc.  Can a stripped down barebox actually run
in 256 Kb and mount a FAT filesystem to get a next stage bootloader?