[PATCH] ARM: remove unused code from __v7_mmu_cache_flush_invalidate

[Masahiro Yamada]

This code is unnecessary (wrong) for the following reasons.

[1] As ARM ARM clearly says, the entire Level 1 cache maintenance
    operations are not supported for ARMv7, i.e. the bit19-16 of
    the ID_MMFR1 is always 0b0000.  The code always jumps to the
    "hierarchical" label.

[2] The value of "r0" is supposed to determine which cache operation
    should be done, invalidate or clean+invalidate.  The line
    "mcr     p15, 0, r12, c7, c14, 0" tries to clean+invalidate
    regardless of the value of "r0", this is weird.
    Anyway, as mentioned above, this line cannot be reached.

Signed-off-by: Masahiro Yamada <yamada.m at jp.panasonic.com>
---

 arch/arm/cpu/cache-armv7.S | 8 +-------
 1 file changed, 1 insertion(+), 7 deletions(-)

diff --git a/arch/arm/cpu/cache-armv7.S b/arch/arm/cpu/cache-armv7.S
index c19618b..f3f6bbb 100644
--- a/arch/arm/cpu/cache-armv7.S
+++ b/arch/arm/cpu/cache-armv7.S
@@ -68,15 +68,9 @@ ENTRY(v7_mmu_cache_flush)
 ENDPROC(v7_mmu_cache_flush)
 
 ENTRY(__v7_mmu_cache_flush_invalidate)
-		mrc	p15, 0, r12, c0, c1, 5	@ read ID_MMFR1
-		tst	r12, #0xf << 16		@ hierarchical cache (ARMv7)
-		mov	r12, #0
-		beq	hierarchical
-		mcr	p15, 0, r12, c7, c14, 0	@ clean+invalidate D
-		b	iflush
-hierarchical:
 		stmfd	sp!, {r4-r11}
 		mov	r8, r0
+		mov	r12, #0
 		mcr	p15, 0, r12, c7, c10, 5	@ DMB
 		mrc	p15, 1, r0, c0, c0, 1	@ read clidr
 		ands	r3, r0, #0x7000000	@ extract loc from clidr
-- 
1.9.1