[PATCH 1/5] ARM: am335x: phyFLEX-AM335x: Split DT and add MLO DT
Wadim Egorov
w.egorov at phytec.de
Wed Feb 4 06:00:49 PST 2015
To support different module variants, this patch splits the phyFLEX DT
in dts and dtsi.
And we are also adding a DT for the MLO, which has all bootable devices
disabled. The bootsource is checked in the board file and only the needed
device is enabled and registered.
Signed-off-by: Wadim Egorov <w.egorov at phytec.de>
---
arch/arm/boards/phytec-phyflex-am335x/board.c | 4 +
arch/arm/boards/phytec-phyflex-am335x/lowlevel.c | 7 +-
arch/arm/dts/Makefile | 2 +-
arch/arm/dts/am335x-phytec-phyflex-som-mlo.dts | 28 ++
arch/arm/dts/am335x-phytec-phyflex-som.dts | 24 ++
arch/arm/dts/am335x-phytec-phyflex-som.dtsi | 362 ++++++++++++++++++++++
arch/arm/dts/am335x-phytec-phyflex.dts | 368 -----------------------
7 files changed, 423 insertions(+), 372 deletions(-)
create mode 100644 arch/arm/dts/am335x-phytec-phyflex-som-mlo.dts
create mode 100644 arch/arm/dts/am335x-phytec-phyflex-som.dts
create mode 100644 arch/arm/dts/am335x-phytec-phyflex-som.dtsi
delete mode 100644 arch/arm/dts/am335x-phytec-phyflex.dts
diff --git a/arch/arm/boards/phytec-phyflex-am335x/board.c b/arch/arm/boards/phytec-phyflex-am335x/board.c
index e635532..aed5c31 100644
--- a/arch/arm/boards/phytec-phyflex-am335x/board.c
+++ b/arch/arm/boards/phytec-phyflex-am335x/board.c
@@ -87,6 +87,10 @@ static int pfla03_devices_init(void)
xloadslots, ARRAY_SIZE(xloadslots));
am33xx_bbu_nand_register_handler("nand", "/dev/nand0.barebox.bb");
+ if (IS_ENABLED(CONFIG_SHELL_NONE))
+ return am33xx_of_register_bootdevice();
+
+
return 0;
}
device_initcall(pfla03_devices_init);
diff --git a/arch/arm/boards/phytec-phyflex-am335x/lowlevel.c b/arch/arm/boards/phytec-phyflex-am335x/lowlevel.c
index a240401..f6029cd 100644
--- a/arch/arm/boards/phytec-phyflex-am335x/lowlevel.c
+++ b/arch/arm/boards/phytec-phyflex-am335x/lowlevel.c
@@ -102,7 +102,8 @@ struct pfla03_sdram_timings pfla03_timings[] = {
},
};
-extern char __dtb_am335x_phytec_phyflex_start[];
+extern char __dtb_am335x_phytec_phyflex_som_start[];
+extern char __dtb_am335x_phytec_phyflex_som_mlo_start[];
/**
* @brief The basic entry point for board initialization.
@@ -139,7 +140,7 @@ static noinline void pfla03_board_init(int sdram)
omap_uart_lowlevel_init((void *)AM33XX_UART0_BASE);
putc_ll('>');
- fdt = __dtb_am335x_phytec_phyflex_start - get_runtime_offset();
+ fdt = __dtb_am335x_phytec_phyflex_som_mlo_start - get_runtime_offset();
am335x_barebox_entry(fdt);
}
@@ -174,7 +175,7 @@ ENTRY_FUNCTION(start_am33xx_phytec_phyflex_sdram, r0, r1, r2)
{
void *fdt;
- fdt = __dtb_am335x_phytec_phyflex_start - get_runtime_offset();
+ fdt = __dtb_am335x_phytec_phyflex_som_start - get_runtime_offset();
am335x_barebox_entry(fdt);
}
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index dc32dd3..e87e612 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -29,7 +29,7 @@ pbl-dtb-$(CONFIG_MACH_PCA100) += imx27-phytec-phycard-s-rdk-bb.dtb.o
pbl-dtb-$(CONFIG_MACH_PCAAXL3) += imx6q-phytec-pbaa03.dtb.o
pbl-dtb-$(CONFIG_MACH_PCM038) += imx27-phytec-phycore-rdk.dtb.o
pbl-dtb-$(CONFIG_MACH_PCM051) += am335x-phytec-phycore-som.dtb.o am335x-phytec-phycore-som-no-spi.dtb.o am335x-phytec-phycore-som-mlo.dtb.o
-pbl-dtb-$(CONFIG_MACH_PFLA03) += am335x-phytec-phyflex.dtb.o
+pbl-dtb-$(CONFIG_MACH_PFLA03) += am335x-phytec-phyflex-som.dtb.o am335x-phytec-phyflex-som-mlo.dtb.o
pbl-dtb-$(CONFIG_MACH_PHYTEC_PFLA02) += imx6s-phytec-pbab01.dtb.o imx6dl-phytec-pbab01.dtb.o imx6q-phytec-pbab01.dtb.o imx6q-phytec-phyboard-alcor.dtb.o imx6dl-phytec-phyboard-subra.dtb.o
pbl-dtb-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_AX3) += armada-xp-openblocks-ax3-4-bb.dtb.o
pbl-dtb-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_A6) += kirkwood-openblocks_a6-bb.dtb.o
diff --git a/arch/arm/dts/am335x-phytec-phyflex-som-mlo.dts b/arch/arm/dts/am335x-phytec-phyflex-som-mlo.dts
new file mode 100644
index 0000000..ab9a9ec
--- /dev/null
+++ b/arch/arm/dts/am335x-phytec-phyflex-som-mlo.dts
@@ -0,0 +1,28 @@
+/*
+ * Copyright (C) 2015 Wadim Egorov <w.egorov at phytec.de> PHYTEC Messtechnik GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+
+#include "am33xx.dtsi"
+#include "am335x-phytec-phyflex-som.dtsi"
+
+/ {
+ model = "Phytec phyFLEX AM335x";
+ compatible = "phytec,phyflex-am335x-som", "ti,am33xx";
+};
+
+/* Keep all bootsources disabled, we enable and register them
+ * later while booting.
+ */
+
+&mmc1 {
+ status = "disabled";
+};
+
+&gpmc {
+ status = "disabled";
+};
diff --git a/arch/arm/dts/am335x-phytec-phyflex-som.dts b/arch/arm/dts/am335x-phytec-phyflex-som.dts
new file mode 100644
index 0000000..2239f07
--- /dev/null
+++ b/arch/arm/dts/am335x-phytec-phyflex-som.dts
@@ -0,0 +1,24 @@
+/*
+ * Copyright (C) 2015 Wadim Egorov <w.egorov at phytec.de> PHYTEC Messtechnik GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+
+#include "am33xx.dtsi"
+#include "am335x-phytec-phyflex-som.dtsi"
+
+/ {
+ model = "Phytec phyFLEX AM335x";
+ compatible = "phytec,phyflex-am335x-som", "ti,am33xx";
+};
+
+&spi0 {
+ status = "okay";
+};
+
+&at24c32 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/am335x-phytec-phyflex-som.dtsi b/arch/arm/dts/am335x-phytec-phyflex-som.dtsi
new file mode 100644
index 0000000..1837636
--- /dev/null
+++ b/arch/arm/dts/am335x-phytec-phyflex-som.dtsi
@@ -0,0 +1,362 @@
+/ {
+ chosen {
+ linux,stdout-path = &uart0;
+
+ environment-spi {
+ compatible = "barebox,environment";
+ device-path = &flash, "partname:bareboxenv";
+ status = "disabled";
+ };
+
+ environment-nand {
+ compatible = "barebox,environment";
+ device-path = &nand, "partname:bareboxenv";
+ status = "disabled";
+ };
+ };
+
+ vcc5v: fixedregulator at 0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-boot-on;
+ };
+
+ vcc3v3: fixedregulator at 1 {
+ compatible = "regulator-fixed";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ };
+
+};
+
+&am33xx_pinmux {
+ i2c0_pins: pinmux_i2c0_pins {
+ pinctrl-single,pins = <
+ 0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda */
+ 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl */
+ >;
+ };
+
+ spi0_pins: pinmux_spi0_pins {
+ pinctrl-single,pins = <
+ 0x150 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* spi0_clk.spi0_clk */
+ 0x154 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* spi0_d0.spi0_d0 */
+ 0x158 (PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_d1.spi0_d1 */
+ 0x15c (PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_cs0.spi0_cs0 */
+ >;
+ };
+
+ uart0_pins: pinmux_uart0_pins {
+ pinctrl-single,pins = <
+ 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd */
+ 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd */
+ >;
+ };
+
+ mmc1_pins: pinmux_mmc1_pins {
+ pinctrl-single,pins = <
+ 0x0f0 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3 */
+ 0x0f4 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2 */
+ 0x0f8 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat1 */
+ 0x0fc (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0 */
+ 0x100 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk */
+ 0x104 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd */
+ >;
+ };
+
+ emac_rgmii1_pins: pinmux_emac_rgmii1_pins {
+ pinctrl-single,pins = <
+ 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_tx_en.rgmii1_tctl */
+ 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rx_dv.rgmii1_rctl */
+ 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd3.rgmii1_td3 */
+ 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd2.rgmii1_td2 */
+ 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */
+ 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */
+ 0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_tx_clk.rgmii1_tclk */
+ 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rx_clk.rgmii1_rclk */
+ 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */
+ 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */
+ 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */
+ 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */
+ >;
+ };
+
+ emac_rmii2_pins: pinmux_emac_rmii2_pins {
+ pinctrl-single,pins = <
+ 0x040 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* gpmc_a0.rmii2_txen */
+ 0x050 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* gpmc_a4.rmii2_txd1 */
+ 0x054 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* gpmc_a5.rmii2_txd0 */
+ 0x068 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* gpmc_a10.rmii2_rxd1 */
+ 0x06c (PIN_INPUT_PULLDOWN | MUX_MODE3) /* gpmc_a11.rmii2_rxd0 */
+ 0x074 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_wpn.rmii2_rxer */
+ 0x108 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_col.rmii2_refclk */
+ >;
+ };
+
+ davinci_mdio_default: davinci_mdio_default {
+ pinctrl-single,pins = <
+ 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data */
+ 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk */
+ >;
+ };
+
+ nandflash_pins_s0: nandflash_pins_s0 {
+ pinctrl-single,pins = <
+ 0x000 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0 */
+ 0x004 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1 */
+ 0x008 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2 */
+ 0x00c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3 */
+ 0x010 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4 */
+ 0x014 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5 */
+ 0x018 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6 */
+ 0x01c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7 */
+ 0x070 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0 */
+ 0x07c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* gpmc_csn0 */
+ 0x090 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* gpmc_advn_ale */
+ 0x094 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* gpmc_oen_ren */
+ 0x098 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* gpmc_wen */
+ 0x09c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* gpmc_be0n_cle */
+ >;
+ };
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins>;
+ status = "okay";
+ clock-frequency = <400000>;
+
+ tps: pmic at 2d {
+ reg = <0x2d>;
+ };
+
+ at24c32: eeprom at 52 {
+ compatible = "atmel,24c32";
+ byte_len = <4096>;
+ pagesize = <32>;
+ reg = <0x52>;
+ };
+};
+
+&mmc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc1_pins>;
+ status = "okay";
+};
+
+&spi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi0_pins>;
+ status = "disabled";
+ flash: m25p80 {
+ compatible = "m25p80";
+ spi-max-frequency = <48000000>;
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ m25p,fast-read;
+
+ partition at 0 {
+ label = "xload";
+ reg = <0x0 0x20000>;
+ };
+
+ partition at 1 {
+ label = "barebox";
+ reg = <0x20000 0x80000>;
+ };
+
+ partition at 2 {
+ label = "bareboxenv";
+ reg = <0xa0000 0x20000>;
+ };
+
+ partition at 3 {
+ label = "oftree";
+ reg = <0xc0000 0x20000>;
+ };
+
+ partition at 4 {
+ label = "kernel";
+ reg = <0xe0000 0x0>;
+ };
+ };
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins>;
+ status = "okay";
+};
+
+&davinci_mdio {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&davinci_mdio_default>;
+ status = "okay";
+};
+
+&phy_sel {
+ rmii-clock-ext;
+};
+
+&cpsw_emac0 {
+ phy_id = <&davinci_mdio>, <1>;
+ phy-mode = "rgmii";
+ dual_emac_res_vlan = <1>;
+
+ /* clock skew correction, maximum possible on KSZ9031 is
+ 2^5 - 1 * 0,06ns = 1860ps, micrel datasheet M9999-081712-0.11 p.58*/
+ rxc-skew-ps = <1860>;
+ txc-skew-ps = <1860>;
+
+ /* align tx signals to zero, leave rx to default */
+ txd0-skew-ps = <0>;
+ txd1-skew-ps = <0>;
+ txd2-skew-ps = <0>;
+ txd3-skew-ps = <0>;
+};
+
+&cpsw_emac1 {
+ phy_id = <&davinci_mdio>, <2>;
+ phy-mode = "rmii";
+ dual_emac_res_vlan = <2>;
+};
+
+&mac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&emac_rgmii1_pins &emac_rmii2_pins>;
+ dual_emac;
+ status = "okay";
+};
+
+&elm {
+ status = "okay";
+};
+
+&gpmc {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&nandflash_pins_s0>;
+ ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */
+ nand: nand at 0,0 {
+ reg = <0 0 0>; /* CS0, offset 0 */
+ nand-bus-width = <8>;
+ ti,nand-ecc-opt = "bch8";
+ gpmc,device-nand = "true";
+ gpmc,device-width = <1>;
+ gpmc,sync-clk-ps = <0>;
+ gpmc,cs-on-ns = <0>;
+ gpmc,cs-rd-off-ns = <30>;
+ gpmc,cs-wr-off-ns = <30>;
+ gpmc,adv-on-ns = <0>;
+ gpmc,adv-rd-off-ns = <30>;
+ gpmc,adv-wr-off-ns = <30>;
+ gpmc,we-on-ns = <0>;
+ gpmc,we-off-ns = <20>;
+ gpmc,oe-on-ns = <10>;
+ gpmc,oe-off-ns = <30>;
+ gpmc,access-ns = <30>;
+ gpmc,rd-cycle-ns = <30>;
+ gpmc,wr-cycle-ns = <30>;
+ gpmc,wait-pin = <1>;
+ gpmc,wait-on-read = "true";
+ gpmc,wait-on-write = "true";
+ gpmc,bus-turnaround-ns = <0>;
+ gpmc,cycle2cycle-delay-ns = <50>;
+ gpmc,cycle2cycle-diffcsen;
+ gpmc,clk-activation-ns = <0>;
+ gpmc,wait-monitoring-ns = <0>;
+ gpmc,wr-access-ns = <0>;
+ gpmc,wr-data-mux-bus-ns = <0>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ elm_id = <&elm>;
+
+ partition at 0 {
+ label = "xload";
+ reg = <0x0 0x20000>;
+ };
+
+ partition at 1 {
+ label = "xload_backup1";
+ reg = <0x20000 0x20000>;
+ };
+
+ partition at 2 {
+ label = "xload_backup2";
+ reg = <0x40000 0x20000>;
+ };
+
+ partition at 3 {
+ label = "xload_backup3";
+ reg = <0x60000 0x20000>;
+ };
+
+ partition at 4 {
+ label = "barebox";
+ reg = <0x80000 0x80000>;
+ };
+
+ partition at 5 {
+ label = "bareboxenv";
+ reg = <0x100000 0x20000>;
+ };
+
+ partition at 6 {
+ label = "oftree";
+ reg = <0x120000 0x20000>;
+ };
+
+ partition at 7 {
+ label = "kernel";
+ reg = <0x140000 0x800000>;
+ };
+
+ partition at 8 {
+ label = "root";
+ reg = <0x940000 0x0>;
+ };
+ };
+};
+
+/include/ "tps65217.dtsi"
+&tps {
+ vcc1-supply = <&vcc5v>;
+ vcc2-supply = <&vcc5v>;
+ vcc3-supply = <&vcc5v>;
+ vcc4-supply = <&vcc5v>;
+ vcc5-supply = <&vcc5v>;
+ vcc6-supply = <&vcc5v>;
+ vcc7-supply = <&vcc5v>;
+ vccio-supply = <&vcc5v>;
+
+ regulators {
+ vdd1_reg: regulator at 2 {
+ /* VDD_MPU voltage limits 0.95V - 1.325V with +/-4% tolerance */
+ regulator-name = "vdd_mpu";
+ regulator-min-microvolt = <912500>;
+ regulator-max-microvolt = <1378000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vdd2_reg: regulator at 3 {
+ /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
+ regulator-name = "vdd_core";
+ regulator-min-microvolt = <912500>;
+ regulator-max-microvolt = <1150000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vmmc_reg: regulator at 12 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ };
+};
diff --git a/arch/arm/dts/am335x-phytec-phyflex.dts b/arch/arm/dts/am335x-phytec-phyflex.dts
deleted file mode 100644
index 6c49567..0000000
--- a/arch/arm/dts/am335x-phytec-phyflex.dts
+++ /dev/null
@@ -1,368 +0,0 @@
-/dts-v1/;
-
-#include "am33xx.dtsi"
-
-/ {
- model = "Phytec phyFLEX AM335x";
- compatible = "phytec,phyflex-am335x-som", "ti,am33xx";
-
- chosen {
- linux,stdout-path = &uart0;
-
- environment-spi {
- compatible = "barebox,environment";
- device-path = &flash, "partname:bareboxenv";
- status = "disabled";
- };
-
- environment-nand {
- compatible = "barebox,environment";
- device-path = &nand, "partname:bareboxenv";
- status = "disabled";
- };
- };
-
- vcc5v: fixedregulator at 0 {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-boot-on;
- };
-
- vcc3v3: fixedregulator at 1 {
- compatible = "regulator-fixed";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- };
-};
-
-&am33xx_pinmux {
- i2c0_pins: pinmux_i2c0_pins {
- pinctrl-single,pins = <
- 0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda */
- 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl */
- >;
- };
-
- spi0_pins: pinmux_spi0_pins {
- pinctrl-single,pins = <
- 0x150 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* spi0_clk.spi0_clk */
- 0x154 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* spi0_d0.spi0_d0 */
- 0x158 (PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_d1.spi0_d1 */
- 0x15c (PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_cs0.spi0_cs0 */
- >;
- };
-
- uart0_pins: pinmux_uart0_pins {
- pinctrl-single,pins = <
- 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd */
- 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd */
- >;
- };
-
- mmc1_pins: pinmux_mmc1_pins {
- pinctrl-single,pins = <
- 0x0f0 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3 */
- 0x0f4 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2 */
- 0x0f8 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat1 */
- 0x0fc (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0 */
- 0x100 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk */
- 0x104 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd */
- >;
- };
-
- emac_rgmii1_pins: pinmux_emac_rgmii1_pins {
- pinctrl-single,pins = <
- 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_tx_en.rgmii1_tctl */
- 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rx_dv.rgmii1_rctl */
- 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd3.rgmii1_td3 */
- 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd2.rgmii1_td2 */
- 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */
- 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */
- 0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_tx_clk.rgmii1_tclk */
- 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rx_clk.rgmii1_rclk */
- 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */
- 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */
- 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */
- 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */
- >;
- };
-
- emac_rmii2_pins: pinmux_emac_rmii2_pins {
- pinctrl-single,pins = <
- 0x040 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* gpmc_a0.rmii2_txen */
- 0x050 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* gpmc_a4.rmii2_txd1 */
- 0x054 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* gpmc_a5.rmii2_txd0 */
- 0x068 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* gpmc_a10.rmii2_rxd1 */
- 0x06c (PIN_INPUT_PULLDOWN | MUX_MODE3) /* gpmc_a11.rmii2_rxd0 */
- 0x074 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_wpn.rmii2_rxer */
- 0x108 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_col.rmii2_refclk */
- >;
- };
-
- davinci_mdio_default: davinci_mdio_default {
- pinctrl-single,pins = <
- 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data */
- 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk */
- >;
- };
-
- nandflash_pins_s0: nandflash_pins_s0 {
- pinctrl-single,pins = <
- 0x000 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0 */
- 0x004 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1 */
- 0x008 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2 */
- 0x00c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3 */
- 0x010 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4 */
- 0x014 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5 */
- 0x018 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6 */
- 0x01c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7 */
- 0x070 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0 */
- 0x07c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* gpmc_csn0 */
- 0x090 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* gpmc_advn_ale */
- 0x094 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* gpmc_oen_ren */
- 0x098 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* gpmc_wen */
- 0x09c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* gpmc_be0n_cle */
- >;
- };
-};
-
-&i2c0 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_pins>;
- status = "okay";
- clock-frequency = <400000>;
-
- tps: pmic at 2d {
- reg = <0x2d>;
- };
-
- at24c32: eeprom at 52 {
- compatible = "atmel,24c32";
- byte_len = <4096>;
- pagesize = <32>;
- reg = <0x52>;
- };
-};
-
-&mmc1 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc1_pins>;
- status = "okay";
-};
-
-&spi0 {
- pinctrl-names = "default";
- pinctrl-0 = <&spi0_pins>;
- status = "okay";
- flash: m25p80 {
- compatible = "m25p80";
- spi-max-frequency = <48000000>;
- reg = <0>;
- #address-cells = <1>;
- #size-cells = <1>;
- m25p,fast-read;
-
- partition at 0 {
- label = "xload";
- reg = <0x0 0x20000>;
- };
-
- partition at 1 {
- label = "barebox";
- reg = <0x20000 0x80000>;
- };
-
- partition at 2 {
- label = "bareboxenv";
- reg = <0xa0000 0x20000>;
- };
-
- partition at 3 {
- label = "oftree";
- reg = <0xc0000 0x20000>;
- };
-
- partition at 4 {
- label = "kernel";
- reg = <0xe0000 0x0>;
- };
- };
-};
-
-&uart0 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins>;
- status = "okay";
-};
-
-&davinci_mdio {
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&davinci_mdio_default>;
- status = "okay";
-};
-
-&phy_sel {
- rmii-clock-ext;
-};
-
-&cpsw_emac0 {
- phy_id = <&davinci_mdio>, <1>;
- phy-mode = "rgmii";
- dual_emac_res_vlan = <1>;
-
- /* clock skew correction, maximum possible on KSZ9031 is
- 2^5 - 1 * 0,06ns = 1860ps, micrel datasheet M9999-081712-0.11 p.58*/
- rxc-skew-ps = <1860>;
- txc-skew-ps = <1860>;
-
- /* align tx signals to zero, leave rx to default */
- txd0-skew-ps = <0>;
- txd1-skew-ps = <0>;
- txd2-skew-ps = <0>;
- txd3-skew-ps = <0>;
-};
-
-&cpsw_emac1 {
- phy_id = <&davinci_mdio>, <2>;
- phy-mode = "rmii";
- dual_emac_res_vlan = <2>;
-};
-
-&mac {
- pinctrl-names = "default";
- pinctrl-0 = <&emac_rgmii1_pins &emac_rmii2_pins>;
- dual_emac;
- status = "okay";
-};
-
-&elm {
- status = "okay";
-};
-
-&gpmc {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&nandflash_pins_s0>;
- ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */
- nand: nand at 0,0 {
- reg = <0 0 0>; /* CS0, offset 0 */
- nand-bus-width = <8>;
- ti,nand-ecc-opt = "bch8";
- gpmc,device-nand = "true";
- gpmc,device-width = <1>;
- gpmc,sync-clk-ps = <0>;
- gpmc,cs-on-ns = <0>;
- gpmc,cs-rd-off-ns = <30>;
- gpmc,cs-wr-off-ns = <30>;
- gpmc,adv-on-ns = <0>;
- gpmc,adv-rd-off-ns = <30>;
- gpmc,adv-wr-off-ns = <30>;
- gpmc,we-on-ns = <0>;
- gpmc,we-off-ns = <20>;
- gpmc,oe-on-ns = <10>;
- gpmc,oe-off-ns = <30>;
- gpmc,access-ns = <30>;
- gpmc,rd-cycle-ns = <30>;
- gpmc,wr-cycle-ns = <30>;
- gpmc,wait-pin = <1>;
- gpmc,wait-on-read = "true";
- gpmc,wait-on-write = "true";
- gpmc,bus-turnaround-ns = <0>;
- gpmc,cycle2cycle-delay-ns = <50>;
- gpmc,cycle2cycle-diffcsen;
- gpmc,clk-activation-ns = <0>;
- gpmc,wait-monitoring-ns = <0>;
- gpmc,wr-access-ns = <0>;
- gpmc,wr-data-mux-bus-ns = <0>;
-
- #address-cells = <1>;
- #size-cells = <1>;
- elm_id = <&elm>;
-
- partition at 0 {
- label = "xload";
- reg = <0x0 0x20000>;
- };
-
- partition at 1 {
- label = "xload_backup1";
- reg = <0x20000 0x20000>;
- };
-
- partition at 2 {
- label = "xload_backup2";
- reg = <0x40000 0x20000>;
- };
-
- partition at 3 {
- label = "xload_backup3";
- reg = <0x60000 0x20000>;
- };
-
- partition at 4 {
- label = "barebox";
- reg = <0x80000 0x80000>;
- };
-
- partition at 5 {
- label = "bareboxenv";
- reg = <0x100000 0x20000>;
- };
-
- partition at 6 {
- label = "oftree";
- reg = <0x120000 0x20000>;
- };
-
- partition at 7 {
- label = "kernel";
- reg = <0x140000 0x800000>;
- };
-
- partition at 8 {
- label = "root";
- reg = <0x940000 0x0>;
- };
- };
-};
-
-/include/ "tps65217.dtsi"
-&tps {
- vcc1-supply = <&vcc5v>;
- vcc2-supply = <&vcc5v>;
- vcc3-supply = <&vcc5v>;
- vcc4-supply = <&vcc5v>;
- vcc5-supply = <&vcc5v>;
- vcc6-supply = <&vcc5v>;
- vcc7-supply = <&vcc5v>;
- vccio-supply = <&vcc5v>;
-
- regulators {
- vdd1_reg: regulator at 2 {
- /* VDD_MPU voltage limits 0.95V - 1.325V with +/-4% tolerance */
- regulator-name = "vdd_mpu";
- regulator-min-microvolt = <912500>;
- regulator-max-microvolt = <1378000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- vdd2_reg: regulator at 3 {
- /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
- regulator-name = "vdd_core";
- regulator-min-microvolt = <912500>;
- regulator-max-microvolt = <1150000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- vmmc_reg: regulator at 12 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- };
-
- };
-};
--
1.9.1
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