[PATCH] mtd: nand-mxs: Gate ENFC_CLK_ROOT clock off before changing nand clock rate

[Sascha Hauer]

On Mon, Nov 17, 2014 at 12:58:34AM +0300, Dmitry Lavnikevich wrote:
> This fixes NAND initialization issue which appears occasionally on
> some i.MX6 SoCs (particulary was observed on phyCARD-i.MX6 with
> i.MX6Solo).
> 
> Signed-off-by: Dmitry Lavnikevich <d.lavnikevich at sam-solutions.com>

I had to revert this one. It breaks compilation on i.MX28. Looking
closer at it reveals this is the wrong approach.

>  	if (mxs_nand_is_imx6(nand_info)) {
> +		val = readl(MXC_CCM_CCGR2);
> +		val &= ~MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK;
> +		writel(val, MXC_CCM_CCGR2);
> +
>  		clk_set_rate(nand_info->clk, 96000000);
> +
> +		val = readl(MXC_CCM_CCGR2);
> +		val |= MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK;
> +		writel(val, MXC_CCM_CCGR2);
> +
>  		clk_enable(nand_info->clk);

First of all please look at the kernel driver. It uses a clock of 22MHz
normally and 100 or 80MHz for EDO mode, which seems to require setup of
other registers. So it might be that there's something else that makes
trouble here.

The clk API is for abstracting the clock providers from its consumers.
It's unnecessary to directly fiddle with the clock registers in the nand
driver. Instead of passing the enfc_podf to the nand controller
arch/arm/mach-imx/clk-imx6.c should be changed to pass the gate to the
controller and here. In the final enabling of all the gates in
clk-imx6.c clear MXC_CCM_CCGR2[14..15] and enable the clock here after
setting the rate.

Sascha

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