From josh.wu at atmel.com  Sun Mar  2 22:45:16 2014
From: josh.wu at atmel.com (Josh Wu)
Date: Mon, 3 Mar 2014 11:45:16 +0800
Subject: nand pmecc crash detected
In-Reply-To: <5310B108.8040800@celad.com>
References: <5310B108.8040800@celad.com>
Message-ID: <5313FACC.8030202@atmel.com>

Dear Herve

On 2/28/2014 11:53 PM, Herve Codina wrote:
> Hi,
>
> I am using an sam5d35 and its pmecc nand ecc controller.
>
> In barebox, using similar atmel_nand.c the system crashes.
>
> The problem was a call to chip->ecc.hwctl from nand_write_subpage_hwecc
> (nand_base.c) when we write a sub page.
>
> chip->ecc.hwctl function is not set when we are using PMECC controller.
>
> As a workaround, i set NAND_NO_SUBPAGE_WRITE for PMECC controller in
> order to disable sub page access in nand_write_page.
>
> I think we can have the same problem in Linux. I do not performed
> subpage nand writes from Linux but i made the following patch according
> to my Barebox defect.

Thank you for catching this crash bug. The fix is fine for me. But I 
think it's better to send out the Linux kernel patch alone.

You can rebase your patch on the top of Linux-mtd git 
repo(git://git.infradead.org/l2-mtd.git) instead of your local Linux.
Then use 'git send-email' send to linux-mtd at lists.infradead.org and 
linux-arm-kernel at lists.infradead.org. I will ack your patch.

If the patch is merged in Linux-mtd, it should be easier port to barebox 
then.

>
> Here after are my patches (same modification) for 1st my local Barebox
> and 2nd my local Linux :
>
> ---8<-------------------
>  From 757e8dbf141619a55b7a5b1ca11780b2589eacc1 Mon Sep 17 00:00:00 2001
> From: Herve Codina <Herve.CODINA at celad.com>
> Date: Fri, 28 Feb 2014 08:39:08 +0100
> Subject: [PATCH 5/5] Disable Subpage nand write when using Atmel PMECC.
>
>
> Signed-off-by: Herve Codina <Herve.CODINA at celad.com>
> ---
>   drivers/mtd/nand/atmel_nand.c |    1 +
>   1 file changed, 1 insertion(+)
>
> diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
> index 2ff7427..cdbe685 100644
> --- a/drivers/mtd/nand/atmel_nand.c
> +++ b/drivers/mtd/nand/atmel_nand.c
> @@ -837,6 +837,7 @@ static int __init
> atmel_pmecc_nand_init_params(struct device_d *dev,
>   		return err_no;
>   	}
>
> +	nand_chip->options |= NAND_NO_SUBPAGE_WRITE;
>   	nand_chip->ecc.read_page = atmel_nand_pmecc_read_page;
>   	nand_chip->ecc.write_page = atmel_nand_pmecc_write_page;
>

Best Regards,
Josh Wu


From s.hauer at pengutronix.de  Mon Mar  3 02:02:07 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Mon, 3 Mar 2014 08:02:07 +0100
Subject: [PATCH 1/1 v2] ARM: i.MX31: Add support for mx31moboard board
In-Reply-To: <1393605311.755068563@f12.i.mail.ru>
References: <1393604879-29317-1-git-send-email-philippe.retornaz@epfl.ch>
 <1393604879-29317-2-git-send-email-philippe.retornaz@epfl.ch>
 <1393605311.755068563@f12.i.mail.ru>
Message-ID: <20140303070207.GH17250@pengutronix.de>

On Fri, Feb 28, 2014 at 08:35:11PM +0400, Alexander Shiyan wrote:
> ???????, 28 ??????? 2014, 17:27 +01:00 ?? Philippe R?tornaz <philippe.retornaz at epfl.ch>:
> > The mx31moboard is used on the marXbot, Eyebot and Footbot robot.
> ...
> > diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
> > index 79ea694..b7e7533 100644
> > --- a/arch/arm/mach-imx/Kconfig
> > +++ b/arch/arm/mach-imx/Kconfig
> > @@ -14,6 +14,7 @@ config ARCH_TEXT_BASE
> >  	default 0xa7f00000 if MACH_PCA100
> >  	default 0xa0000000 if MACH_PCM038
> >  	default 0x87f00000 if MACH_PCM037
> > +	default 0x87f00000 if MACH_MX31MOBOARD
> >  	default 0x87f00000 if MACH_PCM043
> >  	default 0x08f80000 if MACH_SCB9328
> >  	default 0xa7e00000 if MACH_NESO
> > @@ -363,6 +364,16 @@ config MACH_PCM037
> >  	  Say Y here if you are using Phytec's phyCORE-i.MX31 (pcm037) equipped
> >  	  with a Freescale i.MX31 Processor
> 
> Just a hint for Sascha. Can we replace all of these with
> default 0xXX if ARCH_IMXxx?

No, because the location is at the end of SDRAM. With the SoC we only
know the start of SDRAM, but not the size which is board specific.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From s.hauer at pengutronix.de  Mon Mar  3 02:13:52 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Mon, 3 Mar 2014 08:13:52 +0100
Subject: [PATCH 1/1] blspec: Fix when NFS is not enabled
In-Reply-To: <1393599567-20329-1-git-send-email-philippe.retornaz@epfl.ch>
References: <1393599567-20329-1-git-send-email-philippe.retornaz@epfl.ch>
Message-ID: <20140303071352.GI17250@pengutronix.de>

Hi Philippe,

On Fri, Feb 28, 2014 at 03:59:27PM +0100, Philippe R?tornaz wrote:
> Commit 0b10801bb (blspec: Add NFS support) broke blspec when NFS is
> disabled as parse_nfs_url() will return NULL.
> 
> So use IS_ERR_OR_NULL() instead of IS_ERR().
> 
> Signed-off-by: Philippe R?tornaz <philippe.retornaz at epfl.ch>
> ---
>  common/blspec.c |    2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/common/blspec.c b/common/blspec.c
> index fcdcc77..8c2b6ca 100644
> --- a/common/blspec.c
> +++ b/common/blspec.c
> @@ -252,7 +252,7 @@ int blspec_scan_directory(struct blspec *blspec, const char *root)
>  	char *entry_default = NULL, *entry_once = NULL, *name, *nfspath = NULL;
>  
>  	nfspath = parse_nfs_url(root);
> -	if (!IS_ERR(nfspath))
> +	if (!IS_ERR_OR_NULL(nfspath))
>  		root = nfspath;

Thanks for catching this. The usage of IS_ERR_OR_NULL is frowned upon in
the Kernel, we shouldn't use it in barebox either. A function should
either return a valid error pointer or NULL for failure, but not both. I
fixed this with changing parse_nfs_url() to:

	if (!IS_ENABLED(CONFIG_FS_NFS))
		return ERR_PTR(-ENOSYS);

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From s.hauer at pengutronix.de  Mon Mar  3 02:50:13 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Mon,  3 Mar 2014 08:50:13 +0100
Subject: [PATCH] mtd: nand: disable subpage reads
Message-ID: <1393833013-7783-1-git-send-email-s.hauer@pengutronix.de>

The default nand_read_subpage implementation returns -ENOSUPP, so we have
to make sure that barebox never uses this implementation. By setting the
NAND_SUBPAGE_READ flag to 0x0 we ensure NAND_HAS_SUBPAGE_READ() never returns
true and also give the compiler a chance to optimize away some unused code.

subpage reads are a rather exotic feature even in Linux. It is only used on
largepage NANDs with soft ecc. Even if we have this case it needs non page
aligned reads to actually profit from this feature.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
Cc: Hattink, Tjalling [FINT] <T.Hattink at fugro.nl>
---

Hi Tjalling,
I had a closer look at the subpage read stuff and saw that this
is really an exotic feature that even if we could support it doesn't
help very much. So I decided to go back to a variant of your first
patch: Fix subpage reads by disabling them completely.


 include/linux/mtd/nand.h | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
index 74ea0b4..3c7509f 100644
--- a/include/linux/mtd/nand.h
+++ b/include/linux/mtd/nand.h
@@ -162,7 +162,8 @@ typedef enum {
 #define NAND_ROM		0x00000800
 
 /* Device supports subpage reads */
-#define NAND_SUBPAGE_READ	0x00001000
+/* Disabled in barebox for smaller binary sizes */
+#define NAND_SUBPAGE_READ	(__BAREBOX__ ? 0x0 : 0x00001000)
 
 /* Options valid for Samsung large page devices */
 #define NAND_SAMSUNG_LP_OPTIONS NAND_CACHEPRG
-- 
1.8.5.3



From s.hauer at pengutronix.de  Mon Mar  3 02:58:01 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Mon, 3 Mar 2014 08:58:01 +0100
Subject: nand pmecc crash detected
In-Reply-To: <5310B108.8040800@celad.com>
References: <5310B108.8040800@celad.com>
Message-ID: <20140303075801.GJ17250@pengutronix.de>

On Fri, Feb 28, 2014 at 04:53:44PM +0100, Herve Codina wrote:
> Hi,
> 
> I am using an sam5d35 and its pmecc nand ecc controller.
> 
> In barebox, using similar atmel_nand.c the system crashes.
> 
> The problem was a call to chip->ecc.hwctl from nand_write_subpage_hwecc
> (nand_base.c) when we write a sub page.
> 
> chip->ecc.hwctl function is not set when we are using PMECC controller.
> 
> As a workaround, i set NAND_NO_SUBPAGE_WRITE for PMECC controller in
> order to disable sub page access in nand_write_page.
> 
> I think we can have the same problem in Linux. I do not performed
> subpage nand writes from Linux but i made the following patch according
> to my Barebox defect.
> 
> Here after are my patches (same modification) for 1st my local Barebox
> and 2nd my local Linux :

Applied (for barebox ;), thanks

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From s.hauer at pengutronix.de  Mon Mar  3 03:08:03 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Mon, 3 Mar 2014 09:08:03 +0100
Subject: [PATCH v2 0/4] ppc: memory layout and memtest
In-Reply-To: <1393592335-9871-1-git-send-email-renaud.barbier@ge.com>
References: <1393592335-9871-1-git-send-email-renaud.barbier@ge.com>
Message-ID: <20140303080803.GK17250@pengutronix.de>

On Fri, Feb 28, 2014 at 12:58:51PM +0000, Renaud Barbier wrote:
> Like version 1, this patchset updates the PPC memory layout and memtest with
> the addition of the first item below:
> 
>  - Move configurable memory layout selection from PPC to MPC5xxx and disable
>    CONFIGURABLE_MEMORY_LAYOUT on MPC85xx platforms.
> 
>  - Memory regions on PPC are redefined to prevent corruption of critical memory
>    areas while running the memtest.
> 
>  - To support the memory test framework with cache disabled, a TLB remapping
>    function is added for the memtest to enable/disable caching on a mapped
>    memory region.
> 
>  - To prevent memtest failure, the memory test is updated to exclude memory
>    region at the bank start.
> 
> Finally, the configuration files are updated for the DA923RC and P2020RDB.
> 
> 
> Renaud Barbier (4):
>   MPC85xx: fix memory layout to prevent corruption during memtest
>   ppc: add support for memtest with cache disabled
>   memtest: exclude page starting at address 0.
>   ppc: P2020RDB and DA923RC configuration

Applied, thanks

Sascha

> 
>  arch/ppc/Kconfig                         |    1 -
>  arch/ppc/configs/da923rc_defconfig       |    2 +
>  arch/ppc/configs/p2020rdb_defconfig      |    2 +
>  arch/ppc/cpu-85xx/Makefile               |    1 +
>  arch/ppc/cpu-85xx/mmu.c                  |   54 ++++++++++++++++++++++++++++++
>  arch/ppc/cpu-85xx/start.S                |    3 --
>  arch/ppc/cpu-85xx/tlb.c                  |   17 +++++++++-
>  arch/ppc/include/asm/mmu.h               |    6 +++
>  arch/ppc/lib/board.c                     |    6 +---
>  arch/ppc/mach-mpc5xxx/Kconfig            |    1 +
>  arch/ppc/mach-mpc85xx/Kconfig            |    3 ++
>  arch/ppc/mach-mpc85xx/barebox.lds.S      |    8 +++--
>  arch/ppc/mach-mpc85xx/cpu.c              |   11 ++++++
>  arch/ppc/mach-mpc85xx/include/mach/mmu.h |    5 +++
>  commands/memtest.c                       |   10 +++---
>  15 files changed, 112 insertions(+), 18 deletions(-)
>  create mode 100644 arch/ppc/cpu-85xx/mmu.c
> 
> 
> _______________________________________________
> barebox mailing list
> barebox at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/barebox
> 

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From s.hauer at pengutronix.de  Mon Mar  3 03:09:35 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Mon, 3 Mar 2014 09:09:35 +0100
Subject: [PATCH 1/1 v2] ARM: i.MX31: Add support for mx31moboard board
In-Reply-To: <1393604879-29317-2-git-send-email-philippe.retornaz@epfl.ch>
References: <1393604879-29317-1-git-send-email-philippe.retornaz@epfl.ch>
 <1393604879-29317-2-git-send-email-philippe.retornaz@epfl.ch>
Message-ID: <20140303080935.GL17250@pengutronix.de>

On Fri, Feb 28, 2014 at 05:27:59PM +0100, Philippe R?tornaz wrote:
> The mx31moboard is used on the marXbot, Eyebot and Footbot robot.
> 
> Signed-off-by: Philippe R?tornaz <philippe.retornaz at epfl.ch>

Applied, thanks

Sascha

> ---
>  arch/arm/boards/Makefile                          |    1 +
>  arch/arm/boards/mx31moboard/Makefile              |   20 ++
>  arch/arm/boards/mx31moboard/env/boot/nor          |    9 +
>  arch/arm/boards/mx31moboard/env/boot/sd           |    8 +
>  arch/arm/boards/mx31moboard/env/boot/usbmsd       |    8 +
>  arch/arm/boards/mx31moboard/env/config-board      |    7 +
>  arch/arm/boards/mx31moboard/env/init/mtdparts-nor |   11 +
>  arch/arm/boards/mx31moboard/lowlevel.c            |  114 +++++++++
>  arch/arm/boards/mx31moboard/mx31moboard.c         |  259 +++++++++++++++++++++
>  arch/arm/boards/mx31moboard/mx31moboard.dox       |   10 +
>  arch/arm/mach-imx/Kconfig                         |   11 +
>  11 files changed, 458 insertions(+)
>  create mode 100644 arch/arm/boards/mx31moboard/Makefile
>  create mode 100644 arch/arm/boards/mx31moboard/env/boot/nor
>  create mode 100644 arch/arm/boards/mx31moboard/env/boot/sd
>  create mode 100644 arch/arm/boards/mx31moboard/env/boot/usbmsd
>  create mode 100644 arch/arm/boards/mx31moboard/env/config-board
>  create mode 100644 arch/arm/boards/mx31moboard/env/init/mtdparts-nor
>  create mode 100644 arch/arm/boards/mx31moboard/lowlevel.c
>  create mode 100644 arch/arm/boards/mx31moboard/mx31moboard.c
>  create mode 100644 arch/arm/boards/mx31moboard/mx31moboard.dox
> 
> diff --git a/arch/arm/boards/Makefile b/arch/arm/boards/Makefile
> index ffd6bb3..0d8c9cf 100644
> --- a/arch/arm/boards/Makefile
> +++ b/arch/arm/boards/Makefile
> @@ -51,6 +51,7 @@ obj-$(CONFIG_MACH_MIOA701)			+= mioa701/
>  obj-$(CONFIG_MACH_MMCCPU)			+= mmccpu/
>  obj-$(CONFIG_MACH_MX23EVK)			+= freescale-mx23-evk/
>  obj-$(CONFIG_MACH_MX28EVK)			+= freescale-mx28-evk/
> +obj-$(CONFIG_MACH_MX31MOBOARD)			+= mx31moboard/
>  obj-$(CONFIG_MACH_MX6Q_ARM2)			+= freescale-mx6-arm2/
>  obj-$(CONFIG_MACH_NESO)				+= guf-neso/
>  obj-$(CONFIG_MACH_NOMADIK_8815NHK)		+= nhk8815/
> diff --git a/arch/arm/boards/mx31moboard/Makefile b/arch/arm/boards/mx31moboard/Makefile
> new file mode 100644
> index 0000000..83a6016
> --- /dev/null
> +++ b/arch/arm/boards/mx31moboard/Makefile
> @@ -0,0 +1,20 @@
> +#
> +# (C) Copyright 2007 Juergen Beisert <jbe at pengutronix.de>
> +#
> +# See file CREDITS for list of people who contributed to this
> +# project.
> +#
> +# This program is free software; you can redistribute it and/or
> +# modify it under the terms of the GNU General Public License as
> +# published by the Free Software Foundation; either version 2 of
> +# the License, or (at your option) any later version.
> +#
> +# This program is distributed in the hope that it will be useful,
> +# but WITHOUT ANY WARRANTY; without even the implied warranty of
> +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> +# GNU General Public License for more details.
> +#
> +#
> +
> +lwl-y += lowlevel.o
> +obj-y += mx31moboard.o
> diff --git a/arch/arm/boards/mx31moboard/env/boot/nor b/arch/arm/boards/mx31moboard/env/boot/nor
> new file mode 100644
> index 0000000..e36655c
> --- /dev/null
> +++ b/arch/arm/boards/mx31moboard/env/boot/nor
> @@ -0,0 +1,9 @@
> +#!/bin/sh
> +
> +if [ "$1" = menu ]; then
> +        boot-menu-add-entry "$0" "NOR Flash"
> +        exit
> +fi
> +
> +global.bootm.image="/dev/nor0.kernel"
> +global.linux.bootargs.dyn.root="root=/dev/mtdblock3 ro"
> diff --git a/arch/arm/boards/mx31moboard/env/boot/sd b/arch/arm/boards/mx31moboard/env/boot/sd
> new file mode 100644
> index 0000000..16e734d
> --- /dev/null
> +++ b/arch/arm/boards/mx31moboard/env/boot/sd
> @@ -0,0 +1,8 @@
> +#!/bin/sh
> +
> +if [ "$1" = menu ]; then
> +        boot-menu-add-entry "$0" "SD Boot"
> +        exit
> +fi
> +
> +boot mci0
> diff --git a/arch/arm/boards/mx31moboard/env/boot/usbmsd b/arch/arm/boards/mx31moboard/env/boot/usbmsd
> new file mode 100644
> index 0000000..6a16d3e
> --- /dev/null
> +++ b/arch/arm/boards/mx31moboard/env/boot/usbmsd
> @@ -0,0 +1,8 @@
> +#!/bin/sh
> +
> +if [ "$1" = menu ]; then
> +        boot-menu-add-entry "$0" "USB Boot"
> +        exit
> +fi
> +
> +boot ehci0
> diff --git a/arch/arm/boards/mx31moboard/env/config-board b/arch/arm/boards/mx31moboard/env/config-board
> new file mode 100644
> index 0000000..f67b333
> --- /dev/null
> +++ b/arch/arm/boards/mx31moboard/env/config-board
> @@ -0,0 +1,7 @@
> +#!/bin/sh
> +
> +# board defaults, do not change in running system. Change /env/config
> +# instead
> +
> +global.boot.default="usbmsd sd nor"
> +global.linux.bootargs.base="console=ttymxc0,921600"
> diff --git a/arch/arm/boards/mx31moboard/env/init/mtdparts-nor b/arch/arm/boards/mx31moboard/env/init/mtdparts-nor
> new file mode 100644
> index 0000000..f09a9cc
> --- /dev/null
> +++ b/arch/arm/boards/mx31moboard/env/init/mtdparts-nor
> @@ -0,0 +1,11 @@
> +#!/bin/sh
> +
> +if [ "$1" = menu ]; then
> +	init-menu-add-entry "$0" "NOR partitions"
> +	exit
> +fi
> +
> +mtdparts="512k(nor0.barebox)ro,256k(nor0.bareboxenv),4M(nor0.kernel),-(nor0.root)"
> +kernelname="physmap-flash.0"
> +
> +mtdparts-add -d nor0 -k ${kernelname} -p ${mtdparts}
> diff --git a/arch/arm/boards/mx31moboard/lowlevel.c b/arch/arm/boards/mx31moboard/lowlevel.c
> new file mode 100644
> index 0000000..e9ffb74
> --- /dev/null
> +++ b/arch/arm/boards/mx31moboard/lowlevel.c
> @@ -0,0 +1,114 @@
> +/*
> + *
> + * (c) 2007 Pengutronix, Sascha Hauer <s.hauer at pengutronix.de>
> + * (c) 2014 EPFL, Philippe R?tornaz <philippe.retornaz at epfl.ch>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + */
> +#include <common.h>
> +#include <init.h>
> +#include <io.h>
> +#include <asm/barebox-arm.h>
> +#include <asm/system.h>
> +#include <asm-generic/memory_layout.h>
> +#include <asm-generic/sections.h>
> +#include <asm/barebox-arm-head.h>
> +#include <mach/imx31-regs.h>
> +#include <mach/imx-pll.h>
> +#include <asm/barebox-arm-head.h>
> +#include <mach/esdctl.h>
> +
> +static noinline __noreturn void mx31moboard_startup(void)
> +{
> +	uint32_t r;
> +	volatile int c;
> +
> +	/* Enable IPU Display interface */
> +	writel(1 << 6, MX31_IPU_CTRL_BASE_ADDR);
> +
> +	writel(0x074B0BF5, MX31_CCM_BASE_ADDR + MX31_CCM_CCMR);
> +
> +	for (c = 0; c < 0x4000; c++) ;
> +
> +	writel(0x074B0BF5 | MX31_CCMR_MPE, MX31_CCM_BASE_ADDR +
> +			MX31_CCM_CCMR);
> +	writel((0x074B0BF5 | MX31_CCMR_MPE) & ~MX31_CCMR_MDS,
> +			MX31_CCM_BASE_ADDR + MX31_CCM_CCMR);
> +
> +	writel(MX31_PDR0_CSI_PODF(0x1ff) | \
> +		MX31_PDR0_PER_PODF(7) | \
> +		MX31_PDR0_HSP_PODF(3) | \
> +		MX31_PDR0_NFC_PODF(5) | \
> +		MX31_PDR0_IPG_PODF(1) | \
> +		MX31_PDR0_MAX_PODF(3) | \
> +		MX31_PDR0_MCU_PODF(0), \
> +		MX31_CCM_BASE_ADDR + MX31_CCM_PDR0);
> +
> +	writel(IMX_PLL_PD(0) | IMX_PLL_MFD(0x33) |
> +			IMX_PLL_MFI(0xa) | IMX_PLL_MFN(0x0C),
> +			MX31_CCM_BASE_ADDR + MX31_CCM_MPCTL);
> +	writel(IMX_PLL_PD(1) | IMX_PLL_MFD(0x43) | IMX_PLL_MFI(12) |
> +			IMX_PLL_MFN(1), MX31_CCM_BASE_ADDR +
> +			MX31_CCM_SPCTL);
> +
> +	/*
> +	 * Configure IOMUXC
> +	 * Clears 0x43fa_c26c - 0x43fa_c2dc with 0,
> +	 * except 0x43fa_c278 (untouched), 0x43fa_c27c (set to 0x1000)
> +	 * and 0x43fa_c280 (untouched)
> +	 * (behaviour copied by sha, source unknown)
> +	 */
> +	writel(0, 0x43fac26c); /* SDCLK */
> +	writel(0, 0x43fac270); /* CAS */
> +	writel(0, 0x43fac274); /* RAS */
> +
> +	writel(0x1000, 0x43fac27c); /* CSD0 */
> +
> +	/* DQM3, DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 */
> +	for (r = 0x43fac284; r <= 0x43fac2dc; r += 4)
> +		writel(0, r);
> +
> +	/* Skip SDRAM initialization if we run from RAM */
> +	r = get_pc();
> +	if (r > 0x80000000 && r < 0xa0000000)
> +		imx31_barebox_entry(0);
> +
> +	writel(0x00000004, MX31_ESDCTL_BASE_ADDR + IMX_ESDMISC);
> +	writel(0x00695727, MX31_ESDCTL_BASE_ADDR + IMX_ESDCFG0);
> +	writel(0x92100000, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
> +	writel(0x12344321, MX31_CSD0_BASE_ADDR + 0xf00);
> +	writel(0xa2100000, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
> +	writel(0x12344321, MX31_CSD0_BASE_ADDR);
> +	writel(0x12344321, MX31_CSD0_BASE_ADDR);
> +	writel(0xb2100000, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
> +	writeb(0xda, MX31_CSD0_BASE_ADDR + 0x33);
> +	writeb(0xff, MX31_CSD0_BASE_ADDR + 0x01000000);
> +	writel(0x82226080, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
> +	writel(0xDEADBEEF, MX31_CSD0_BASE_ADDR);
> +	writel(0x0000000c, MX31_ESDCTL_BASE_ADDR + IMX_ESDMISC);
> +
> +	imx31_barebox_entry(0);
> +
> +}
> +
> +void __bare_init __naked barebox_arm_reset_vector(void)
> +{
> +	arm_cpu_lowlevel_init();
> +
> +	/* Temporary stack location in internal SRAM */
> +	arm_setup_stack(MX31_IRAM_BASE_ADDR + MX31_IRAM_SIZE - 8);
> +
> +	mx31moboard_startup();
> +}
> diff --git a/arch/arm/boards/mx31moboard/mx31moboard.c b/arch/arm/boards/mx31moboard/mx31moboard.c
> new file mode 100644
> index 0000000..2ec1f4f
> --- /dev/null
> +++ b/arch/arm/boards/mx31moboard/mx31moboard.c
> @@ -0,0 +1,259 @@
> +/*
> + * (C) 2007 Pengutronix, Sascha Hauer <s.hauer at pengutronix.de>
> + * (C) 2014 EPFL, Philippe R?tornaz <philippe.retornaz at epfl.ch>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + *
> + * Board support for EPFL's, i.MX31 based CPU card
> + *
> + * Based on:
> + * Board support for Phytec's, i.MX31 based CPU card, called: PCM037
> + */
> +
> +#include <common.h>
> +#include <init.h>
> +#include <driver.h>
> +#include <fs.h>
> +#include <gpio.h>
> +#include <led.h>
> +#include <environment.h>
> +#include <usb/ulpi.h>
> +#include <mach/imx31-regs.h>
> +#include <mach/iomux-mx31.h>
> +#include <asm/armlinux.h>
> +#include <asm/sections.h>
> +#include <mach/weim.h>
> +#include <io.h>
> +#include <asm/mmu.h>
> +#include <partition.h>
> +#include <generated/mach-types.h>
> +#include <asm/barebox-arm.h>
> +#include <mach/devices-imx31.h>
> +
> +#define USBH2_EN_B	IOMUX_TO_GPIO(MX31_PIN_SCK6)
> +#define USB_RESET_B	IOMUX_TO_GPIO(MX31_PIN_GPIO1_0)
> +
> +static void mx31moboard_usb_init(void)
> +{
> +	u32 tmp;
> +
> +	if (!IS_ENABLED(CONFIG_USB))
> +		return;
> +
> +	/* enable clock */
> +	tmp = readl(0x53f80000);
> +	tmp |= (1 << 9);
> +	writel(tmp, 0x53f80000);
> +
> +	/* Host 2 */
> +	tmp = readl(MX31_IOMUXC_GPR);
> +	tmp |= 1 << 11;	/* IOMUX GPR: enable USBH2 signals */
> +	writel(tmp, MX31_IOMUXC_GPR);
> +
> +	imx_iomux_mode(IOMUX_MODE(MX31_PIN_SCK6, IOMUX_CONFIG_GPIO));
> +	imx_iomux_mode(IOMUX_MODE(MX31_PIN_GPIO1_0, IOMUX_CONFIG_GPIO));
> +	imx_iomux_mode(IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC));
> +	imx_iomux_mode(IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC));
> +	imx_iomux_mode(IOMUX_MODE(MX31_PIN_USBH2_NXT, IOMUX_CONFIG_FUNC));
> +	imx_iomux_mode(IOMUX_MODE(MX31_PIN_USBH2_STP, IOMUX_CONFIG_FUNC));
> +	imx_iomux_mode(IOMUX_MODE(MX31_PIN_USBH2_DATA0, IOMUX_CONFIG_FUNC));
> +	imx_iomux_mode(IOMUX_MODE(MX31_PIN_USBH2_DATA1, IOMUX_CONFIG_FUNC));
> +	imx_iomux_mode(IOMUX_MODE(MX31_PIN_STXD3, IOMUX_CONFIG_FUNC));
> +	imx_iomux_mode(IOMUX_MODE(MX31_PIN_SRXD3, IOMUX_CONFIG_FUNC));
> +	imx_iomux_mode(IOMUX_MODE(MX31_PIN_SCK3, IOMUX_CONFIG_FUNC));
> +	imx_iomux_mode(IOMUX_MODE(MX31_PIN_SFS3, IOMUX_CONFIG_FUNC));
> +	imx_iomux_mode(IOMUX_MODE(MX31_PIN_STXD6, IOMUX_CONFIG_FUNC));
> +	imx_iomux_mode(IOMUX_MODE(MX31_PIN_SRXD6, IOMUX_CONFIG_FUNC));
> +
> +#define H2_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS \
> +			| PAD_CTL_ODE_CMOS)
> +	imx_iomux_set_pad(MX31_PIN_USBH2_CLK, H2_PAD_CFG | PAD_CTL_100K_PU);
> +	imx_iomux_set_pad(MX31_PIN_USBH2_DIR, H2_PAD_CFG | PAD_CTL_100K_PU);
> +	imx_iomux_set_pad(MX31_PIN_USBH2_NXT, H2_PAD_CFG | PAD_CTL_100K_PU);
> +	imx_iomux_set_pad(MX31_PIN_USBH2_STP, H2_PAD_CFG | PAD_CTL_100K_PU);
> +	imx_iomux_set_pad(MX31_PIN_USBH2_DATA0, H2_PAD_CFG); /* USBH2_DATA0 */
> +	imx_iomux_set_pad(MX31_PIN_USBH2_DATA1, H2_PAD_CFG); /* USBH2_DATA1 */
> +	imx_iomux_set_pad(MX31_PIN_SRXD6, H2_PAD_CFG);	/* USBH2_DATA2 */
> +	imx_iomux_set_pad(MX31_PIN_STXD6, H2_PAD_CFG);	/* USBH2_DATA3 */
> +	imx_iomux_set_pad(MX31_PIN_SFS3, H2_PAD_CFG);	/* USBH2_DATA4 */
> +	imx_iomux_set_pad(MX31_PIN_SCK3, H2_PAD_CFG);	/* USBH2_DATA5 */
> +	imx_iomux_set_pad(MX31_PIN_SRXD3, H2_PAD_CFG);	/* USBH2_DATA6 */
> +	imx_iomux_set_pad(MX31_PIN_STXD3, H2_PAD_CFG);	/* USBH2_DATA7 */
> +
> +
> +	gpio_request(USB_RESET_B, "usb-reset");
> +	gpio_direction_output(USB_RESET_B, 0);
> +	mdelay(5);
> +	gpio_set_value(USB_RESET_B, 1);
> +	mdelay(10);
> +
> +	gpio_request(USBH2_EN_B, "usbh2-en");
> +	gpio_direction_output(USBH2_EN_B, 0);
> +	udelay(900);
> +	gpio_set_value(USBH2_EN_B, 1);
> +	udelay(200);
> +
> +	tmp = readl(MX31_USB_OTG_BASE_ADDR + 0x600);
> +	tmp &= ~((3 << 21) | 1);
> +	tmp |= (1 << 5) | (1 << 16) | (1 << 19) | (1 << 20);
> +	writel(tmp, MX31_USB_OTG_BASE_ADDR + 0x600);
> +
> +	tmp = readl(MX31_USB_OTG_BASE_ADDR + 0x584);
> +	tmp &= ~(3 << 30);
> +	tmp |= 2 << 30;
> +	writel(tmp, MX31_USB_OTG_BASE_ADDR + 0x584);
> +
> +	gpio_set_value(USBH2_EN_B, 0);
> +
> +	mdelay(50);
> +
> +	ulpi_setup((void *)(MX31_USB_OTG_BASE_ADDR + 0x570), 1);
> +
> +	/* Set to Host mode */
> +	tmp = readl(MX31_USB_OTG_BASE_ADDR + 0x1a8);
> +	writel(tmp | 0x3, MX31_USB_OTG_BASE_ADDR + 0x1a8);
> +
> +}
> +
> +static struct gpio_led mx31moboard_leds[] = {
> +	{
> +		.led = {
> +			.name = "coreboard-led-0:red:running"
> +		},
> +		.gpio = IOMUX_TO_GPIO(MX31_PIN_SVEN0),
> +	}, {
> +		.led = {
> +			.name   = "coreboard-led-1:red",
> +		},
> +		.gpio = IOMUX_TO_GPIO(MX31_PIN_STX0),
> +	}, {
> +		.led = {
> +			.name   = "coreboard-led-2:red",
> +		},
> +		.gpio   = IOMUX_TO_GPIO(MX31_PIN_SRX0),
> +	}, {
> +		.led = {
> +			.name   = "coreboard-led-3:red",
> +		},
> +		.gpio = IOMUX_TO_GPIO(MX31_PIN_SIMPD0),
> +	},
> +};
> +
> +static void mx31moboard_add_leds(void)
> +{
> +	int i;
> +
> +	if (!IS_ENABLED(CONFIG_LED_GPIO))
> +		return;
> +
> +	for (i = 0; i < ARRAY_SIZE(mx31moboard_leds); i++) {
> +		led_gpio_register(&mx31moboard_leds[i]);
> +		led_set(&mx31moboard_leds[i].led, 0);
> +	}
> +
> +	led_set_trigger(LED_TRIGGER_HEARTBEAT, &mx31moboard_leds[0].led);
> +}
> +
> +static int mx31moboard_mmu_init(void)
> +{
> +	l2x0_init((void __iomem *)0x30000000, 0x00030024, 0x00000000);
> +
> +	return 0;
> +}
> +postmmu_initcall(mx31moboard_mmu_init);
> +
> +static const struct devfs_partition mx31moboard_nor0_partitions[] = {
> +	{
> +		.offset = 0,
> +		.size = SZ_512K,
> +		.flags = DEVFS_PARTITION_FIXED,
> +		.name = "self0",
> +	}, {
> +		.offset = DEVFS_PARTITION_APPEND,
> +		.size = SZ_256K,
> +		.name = "env0",
> +	}, {
> +		/* Sentinel */
> +	}
> +};
> +
> +static int mx31moboard_devices_init(void)
> +{
> +	/* CS0: Nor Flash */
> +	imx31_setup_weimcs(0, 0x0000CC03, 0xa0330D01, 0x00220800);
> +
> +	/*
> +	 * Up to 32MiB NOR type flash, connected to
> +	 * CS line 0, data width is 16 bit
> +	 */
> +	add_cfi_flash_device(DEVICE_ID_DYNAMIC, MX31_CS0_BASE_ADDR, SZ_32M, 0);
> +
> +	imx31_add_mmc0(NULL);
> +
> +	/*
> +	 * Create partitions that should be
> +	 * not touched by any regular user
> +	 */
> +	devfs_create_partitions("nor0", mx31moboard_nor0_partitions);
> +	protect_file("/dev/env0", 1);
> +
> +	mx31moboard_usb_init();
> +	add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC,
> +					MX31_USB_HS2_BASE_ADDR, NULL);
> +
> +	mx31moboard_add_leds();
> +
> +	armlinux_set_architecture(MACH_TYPE_MX31MOBOARD);
> +
> +	return 0;
> +}
> +
> +device_initcall(mx31moboard_devices_init);
> +
> +static unsigned int mx31moboard_iomux[] = {
> +	/* UART1 */
> +	MX31_PIN_RXD1__RXD1,
> +	MX31_PIN_TXD1__TXD1,
> +	MX31_PIN_CTS1__GPIO2_7,
> +	/* SDHC1 */
> +	MX31_PIN_SD1_DATA3__SD1_DATA3,
> +	MX31_PIN_SD1_DATA2__SD1_DATA2,
> +	MX31_PIN_SD1_DATA1__SD1_DATA1,
> +	MX31_PIN_SD1_DATA0__SD1_DATA0,
> +	MX31_PIN_SD1_CLK__SD1_CLK,
> +	MX31_PIN_SD1_CMD__SD1_CMD,
> +	MX31_PIN_ATA_CS0__GPIO3_26, MX31_PIN_ATA_CS1__GPIO3_27,
> +	/* LEDS */
> +	MX31_PIN_SVEN0__GPIO2_0, MX31_PIN_STX0__GPIO2_1,
> +	MX31_PIN_SRX0__GPIO2_2, MX31_PIN_SIMPD0__GPIO2_3,
> +};
> +
> +static int imx31_console_init(void)
> +{
> +	imx_iomux_setup_multiple_pins(mx31moboard_iomux,
> +					ARRAY_SIZE(mx31moboard_iomux));
> +
> +	gpio_request(IOMUX_TO_GPIO(MX31_PIN_CTS1), "uart0-cts-hack");
> +	gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_CTS1), 0);
> +
> +	barebox_set_model("EPFL mx31moboard");
> +	barebox_set_hostname("mx31moboard");
> +
> +	imx31_add_uart0();
> +
> +	return 0;
> +}
> +
> +console_initcall(imx31_console_init);
> diff --git a/arch/arm/boards/mx31moboard/mx31moboard.dox b/arch/arm/boards/mx31moboard/mx31moboard.dox
> new file mode 100644
> index 0000000..41c8bbb
> --- /dev/null
> +++ b/arch/arm/boards/mx31moboard/mx31moboard.dox
> @@ -0,0 +1,10 @@
> +/** @page mx31moboard EPFL mx31moboard
> +
> +This CPU card is based on a Freescale i.MX31 CPU. The card is shipped with:
> +
> +- 32MiB NOR type Flash Memory
> +- 128MiB LPDDR
> +- A least one SD slot
> +- A least one USB host (H2)
> +
> +*/
> diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
> index 79ea694..b7e7533 100644
> --- a/arch/arm/mach-imx/Kconfig
> +++ b/arch/arm/mach-imx/Kconfig
> @@ -14,6 +14,7 @@ config ARCH_TEXT_BASE
>  	default 0xa7f00000 if MACH_PCA100
>  	default 0xa0000000 if MACH_PCM038
>  	default 0x87f00000 if MACH_PCM037
> +	default 0x87f00000 if MACH_MX31MOBOARD
>  	default 0x87f00000 if MACH_PCM043
>  	default 0x08f80000 if MACH_SCB9328
>  	default 0xa7e00000 if MACH_NESO
> @@ -363,6 +364,16 @@ config MACH_PCM037
>  	  Say Y here if you are using Phytec's phyCORE-i.MX31 (pcm037) equipped
>  	  with a Freescale i.MX31 Processor
>  
> +config MACH_MX31MOBOARD
> +	bool "mx31moboard-i.MX31"
> +	select ARCH_IMX31
> +	select USB_ULPI if USB
> +	select HAVE_DEFAULT_ENVIRONMENT_NEW
> +	select ARCH_HAS_L2X0
> +	help
> +	  Say Y here if you are using EPFL mx31moboard board equipped
> +	  with a Freescale i.MX31 Processor
> +
>  # ----------------------------------------------------------
>  
>  comment "i.MX35 Boards"
> -- 
> 1.7.9.5
> 
> 

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From T.Hattink at fugro.nl  Mon Mar  3 03:15:36 2014
From: T.Hattink at fugro.nl (Hattink, Tjalling [FINT])
Date: Mon, 3 Mar 2014 09:15:36 +0100
Subject: [PATCH] mtd: nand: disable subpage reads
In-Reply-To: <1393833013-7783-1-git-send-email-s.hauer@pengutronix.de>
References: <1393833013-7783-1-git-send-email-s.hauer@pengutronix.de>
Message-ID: <C89EFD3CD56F64468D3D206D683A8D220304224D@ldam-msx2.fugro-nl.local>

> -----Original Message-----
> From: Sascha Hauer [mailto:s.hauer at pengutronix.de]
> Sent: Monday, March 03, 2014 08:50
> To: barebox at lists.infradead.org
> Cc: Sascha Hauer; Hattink, Tjalling [FINT]
> Subject: [PATCH] mtd: nand: disable subpage reads
> 
> The default nand_read_subpage implementation returns -ENOSUPP, so we
> have to make sure that barebox never uses this implementation. By
> setting the NAND_SUBPAGE_READ flag to 0x0 we ensure
> NAND_HAS_SUBPAGE_READ() never returns true and also give the compiler
a
> chance to optimize away some unused code.
> 
> subpage reads are a rather exotic feature even in Linux. It is only
> used on largepage NANDs with soft ecc. Even if we have this case it
> needs non page aligned reads to actually profit from this feature.
> 
> Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
> Cc: Hattink, Tjalling [FINT] <T.Hattink at fugro.nl>
> ---
> 
> Hi Tjalling,
> I had a closer look at the subpage read stuff and saw that this is
> really an exotic feature that even if we could support it doesn't help
> very much. So I decided to go back to a variant of your first
> patch: Fix subpage reads by disabling them completely.
> 
> 
>  include/linux/mtd/nand.h | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h index
> 74ea0b4..3c7509f 100644
> --- a/include/linux/mtd/nand.h
> +++ b/include/linux/mtd/nand.h
> @@ -162,7 +162,8 @@ typedef enum {
>  #define NAND_ROM		0x00000800
> 
>  /* Device supports subpage reads */
> -#define NAND_SUBPAGE_READ	0x00001000
> +/* Disabled in barebox for smaller binary sizes */
> +#define NAND_SUBPAGE_READ	(__BAREBOX__ ? 0x0 : 0x00001000)
> 
>  /* Options valid for Samsung large page devices */  #define
> NAND_SAMSUNG_LP_OPTIONS NAND_CACHEPRG
> --
> 1.8.5.3

Hi Sascha,

I don't think it matters much either when subpage read is disabled.
Barebox will not do heavy read operations on the nand so the subpage
support will not do much.

Thanks for resolving this bug,

Tjalling


From s.hauer at pengutronix.de  Mon Mar  3 03:30:50 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Mon, 3 Mar 2014 09:30:50 +0100
Subject: [RFC 3/3] libbb: read_full: use read return instead size
In-Reply-To: <20140228171207.GA615@omega>
References: <1393573468-31105-1-git-send-email-alex.aring@gmail.com>
 <1393573468-31105-4-git-send-email-alex.aring@gmail.com>
 <20140228080333.GA31407@omega>
 <20140228142118.GF17250@pengutronix.de>
 <20140228171207.GA615@omega>
Message-ID: <20140303083050.GM17250@pengutronix.de>

On Fri, Feb 28, 2014 at 06:12:09PM +0100, Alexander Aring wrote:
> Hi Sascha,
> 
> On Fri, Feb 28, 2014 at 03:21:18PM +0100, Sascha Hauer wrote:
> > On Fri, Feb 28, 2014 at 09:03:34AM +0100, Alexander Aring wrote:
> > > On Fri, Feb 28, 2014 at 08:44:28AM +0100, Alexander Aring wrote:
> > > > Signed-off-by: Alexander Aring <alex.aring at gmail.com>
> > > > ---
> > > >  lib/libbb.c | 2 +-
> > > >  1 file changed, 1 insertion(+), 1 deletion(-)
> > > > 
> > > > diff --git a/lib/libbb.c b/lib/libbb.c
> > > > index 189a170..c8d0835 100644
> > > > --- a/lib/libbb.c
> > > > +++ b/lib/libbb.c
> > > > @@ -162,7 +162,7 @@ int read_full(int fd, void *buf, size_t size)
> > > >  	int now;
> > > >  	int total = 0;
> > > >  
> > > > -	while (size) {
> > > > +	while (now) {
> > > >  		now = read(fd, buf, size);
> > > >  		if (now == 0)
> > > >  			return total;
> > > and this should be a:
> > > 
> > > do {
> > > ...
> > > } while (now);
> > > 
> > > sry, it's only to demonstrate the issue.
> > 
> > 'now' will never be 0 at the end of the loop, so you could equally well
> > write while(1). With this change we try to read as long as we read
> yes, I did it quickly to make something that command "edit" works in
> some way. The whole patches is only to demonstrate the issue. Also the
> foofs demo works if we read the whole thing at once, but that's okay for
> the test.
> 
> 
> > something last time, even if there's nothing left to read (size is 0).
> > What issue do you see with this function?
> 
> The function read_full makes similar things like:

s/read_full/read_file/

> 
> stat(fd, &statbuf);
> ...
> read(fd, buf, statbuf.st_size);
> 
> this is wrong because a filesize can be zero and read can read something
> from this file.
> 
> For example procfs in linux, if you run this under linux for /proc/version
> it will do nothing.

So our read_file implementation doesn't work procfs like filesystems where
all sizes are 0. Your patch doesn't change this though. In 2/3 you
remove the if (!size) check and call the fs drivers read function with
size 0. In this case the read function may return values, but never
actually read something because the buffer size is 0.

Sascha

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From s.hauer at pengutronix.de  Mon Mar  3 03:36:20 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Mon, 3 Mar 2014 09:36:20 +0100
Subject: [RFC 1/3] ramfs: add foofs for testing
In-Reply-To: <1393573468-31105-2-git-send-email-alex.aring@gmail.com>
References: <1393573468-31105-1-git-send-email-alex.aring@gmail.com>
 <1393573468-31105-2-git-send-email-alex.aring@gmail.com>
Message-ID: <20140303083620.GN17250@pengutronix.de>

On Fri, Feb 28, 2014 at 08:44:26AM +0100, Alexander Aring wrote:
> Signed-off-by: Alexander Aring <alex.aring at gmail.com>
> ---
>  fs/ramfs.c | 69 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 69 insertions(+)
> 
> diff --git a/fs/ramfs.c b/fs/ramfs.c
> index f45a454..4b93c2e 100644
> --- a/fs/ramfs.c
> +++ b/fs/ramfs.c
> @@ -608,6 +608,48 @@ static int ramfs_probe(struct device_d *dev)
>  	return 0;
>  }
>  
> +static int foofs_read(struct device_d *_dev, FILE *f, void *buf, size_t insize)
> +{
> +	if (f->pos == strlen("Hello World!\n"))
> +		return 0;
> +
> +	return sprintf(buf, "%s", "Hello World!\n");
> +}

You should never read more bytes than insize. This is also true for
insize == 0. Implement this correctly and you'll see that your patches
do not solve the problem.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From alex.aring at gmail.com  Mon Mar  3 04:04:13 2014
From: alex.aring at gmail.com (Alexander Aring)
Date: Mon, 3 Mar 2014 10:04:13 +0100
Subject: [RFC 3/3] libbb: read_full: use read return instead size
In-Reply-To: <20140303083050.GM17250@pengutronix.de>
References: <1393573468-31105-1-git-send-email-alex.aring@gmail.com>
 <1393573468-31105-4-git-send-email-alex.aring@gmail.com>
 <20140228080333.GA31407@omega>
 <20140228142118.GF17250@pengutronix.de>
 <20140228171207.GA615@omega>
 <20140303083050.GM17250@pengutronix.de>
Message-ID: <20140303090411.GA24214@x61s.Speedport_W_921V_1_24_000>

Hi Sascha,

On Mon, Mar 03, 2014 at 09:30:50AM +0100, Sascha Hauer wrote:
> 
> So our read_file implementation doesn't work procfs like filesystems where
> all sizes are 0. Your patch doesn't change this though. In 2/3 you
> remove the if (!size) check and call the fs drivers read function with
> size 0. In this case the read function may return values, but never
> actually read something because the buffer size is 0.
> 
exactly. The imporant question for me is "do you want to accept patches
to changes this behaviour, so we can read zero file size files". I mean
this would be a huge change in internal api of filesystem layer and I
hope we doesn't break anything else.

But your are fine with me to say "there exists a problem with read of
zero sized files?".

I will create some "better" patches for this, this RFC should only answer
the question if you apply fixes or not.

- Alex


From alex.aring at gmail.com  Mon Mar  3 04:08:21 2014
From: alex.aring at gmail.com (Alexander Aring)
Date: Mon, 3 Mar 2014 10:08:21 +0100
Subject: [RFC 1/3] ramfs: add foofs for testing
In-Reply-To: <20140303083620.GN17250@pengutronix.de>
References: <1393573468-31105-1-git-send-email-alex.aring@gmail.com>
 <1393573468-31105-2-git-send-email-alex.aring@gmail.com>
 <20140303083620.GN17250@pengutronix.de>
Message-ID: <20140303090820.GB24214@x61s.Speedport_W_921V_1_24_000>

Hi Sascha,

On Mon, Mar 03, 2014 at 09:36:20AM +0100, Sascha Hauer wrote:
> On Fri, Feb 28, 2014 at 08:44:26AM +0100, Alexander Aring wrote:
> > Signed-off-by: Alexander Aring <alex.aring at gmail.com>
> > ---
> >  fs/ramfs.c | 69 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> >  1 file changed, 69 insertions(+)
> > 
> > diff --git a/fs/ramfs.c b/fs/ramfs.c
> > index f45a454..4b93c2e 100644
> > --- a/fs/ramfs.c
> > +++ b/fs/ramfs.c
> > @@ -608,6 +608,48 @@ static int ramfs_probe(struct device_d *dev)
> >  	return 0;
> >  }
> >  
> > +static int foofs_read(struct device_d *_dev, FILE *f, void *buf, size_t insize)
> > +{
> > +	if (f->pos == strlen("Hello World!\n"))
> > +		return 0;
> > +
> > +	return sprintf(buf, "%s", "Hello World!\n");
> > +}
> 
> You should never read more bytes than insize. This is also true for
> insize == 0. Implement this correctly and you'll see that your patches
> do not solve the problem.
> 
yes it's not correctly implemented. Maybe I implement a "testfs"
filesystem for barebox with unit-tests which can be used to test the
filesystem layer to see if something broken or not. This fs should be
based on ramfs.

The fs tests be placed into commands -> testing and it's only interesting for
some developers.

- Alex


From trini at ti.com  Mon Mar  3 09:28:20 2014
From: trini at ti.com (Tom Rini)
Date: Mon, 3 Mar 2014 09:28:20 -0500
Subject: [U-Boot] [PATCH V2] hush: fix some quoted variable expansion
 issues
In-Reply-To: <5312B2F2.1070000@wwwdotorg.org>
References: <1393563654-16490-1-git-send-email-swarren@wwwdotorg.org>
 <CAPnjgZ0rBFV=CbOJ1G8WgUi1fH2=apKA1Q3i8Pd5_Z_ag_2s0Q@mail.gmail.com>
 <5312B2F2.1070000@wwwdotorg.org>
Message-ID: <20140303142820.GS16805@bill-the-cat>

On Sat, Mar 01, 2014 at 09:26:26PM -0700, Stephen Warren wrote:
> On 03/01/2014 05:10 PM, Simon Glass wrote:
> > Hi Stephen,
> > 
> > On 27 February 2014 22:00, Stephen Warren <swarren at wwwdotorg.org
> > <mailto:swarren at wwwdotorg.org>> wrote:
> > 
> >     The following shell command fails:
> > 
> >     if test -z "$x"; then echo "zero"; else echo "non-zero"; fi
> > 
> >     (assuming $x does not exist, it prints "non-zero" rather than "zero").
> > 
> >     ... since "$x" expands to nothing, and the argument is completely
> >     dropped, causing too few to be passed to -z, causing cmd_test() to
> >     error out early.
> > 
> >     This is because when variable expansions are processed by make_string(),
> >     the expanded results are concatenated back into a new string. However,
> >     no quoting is applied when doing so, so any empty variables simply don't
> >     generate any parameter when the combined string is parsed again.
> > 
> >     Fix this by explicitly replacing quoting any argument that was
> >     originally
> >     quoted when re-generating a string from the already-parsed argument
> >     list.
> > 
> >     This also fixes loss of whitespace in commands such as:
> > 
> >     setenv space " "
> >     setenv var " 1${space}${space} 2 "
> >     echo ">>${var}<<"
> > 
> > 
> > Is there an upstream still for hush, or are we so far away that it
> > doesn't matter? If there is, was this bug fixed there?
> 
> Well, the comments at the head of the file say it came from Busybox, but
> it's obviously diverged massively since it was imported:
> 
> $ wc -l busybox/shell/hush.c u-boot/common/hush.c
> 9156 busybox/shell/hush.c
> 3682 u-boot/common/hush.c
> $ diff -u busybox/shell/hush.c u-boot/common/hush.c|wc -l
> 12264
> 
> Also, the function this patch touches doesn't seem to exist under that
> name any more. From a quick look at the source, I couldn't tell what the
> equivalent is.
> 
> Perhaps replaying patches to that file in Busybox since the fork might
> be more useful.
> 
> A quick Google search for "hush" or "hush shell" doesn't seem to yield
> any other alternative upstreams.

For reference the patch is at http://patchwork.ozlabs.org/patch/325023/

Since U-Boot and Barebox are the only users of this particular hush
fork, and from G+ they also have this problem, maybe we can use this as
a starting point of a little more friendly coordination between the
projects?

-- 
Tom
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From plagnioj at jcrosoft.com  Mon Mar  3 23:03:45 2014
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Tue, 4 Mar 2014 05:03:45 +0100
Subject: [PATCH 3/5] net: remove old nfs support
In-Reply-To: <1393534812-30995-4-git-send-email-s.hauer@pengutronix.de>
References: <1393534812-30995-1-git-send-email-s.hauer@pengutronix.de>
 <1393534812-30995-4-git-send-email-s.hauer@pengutronix.de>
Message-ID: <20140304040345.GP9671@ns203013.ovh.net>

On 22:00 Thu 27 Feb     , Sascha Hauer wrote:
> Now that we have the NFS as filesystem support for several releases
> remove the old command based NFS support.
> 
> Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>

as the bootp is not fully supported on default env2 do not drop it

Best Regards,
J.
> ---
>  net/Kconfig  |   4 -
>  net/Makefile |   1 -
>  net/nfs.c    | 737 -----------------------------------------------------------
>  3 files changed, 742 deletions(-)
>  delete mode 100644 net/nfs.c
> 
> diff --git a/net/Kconfig b/net/Kconfig
> index c12193d..adafa9b 100644
> --- a/net/Kconfig
> +++ b/net/Kconfig
> @@ -7,10 +7,6 @@ config NET_DHCP
>  	bool
>  	prompt "dhcp support"
>  
> -config NET_NFS
> -	bool
> -	prompt "nfs support"
> -
>  config NET_PING
>  	bool
>  	prompt "ping support"
> diff --git a/net/Makefile b/net/Makefile
> index 416e30a..98e0f09 100644
> --- a/net/Makefile
> +++ b/net/Makefile
> @@ -1,7 +1,6 @@
>  obj-$(CONFIG_NET_DHCP)	+= dhcp.o
>  obj-$(CONFIG_NET)	+= eth.o
>  obj-$(CONFIG_NET)	+= net.o
> -obj-$(CONFIG_NET_NFS)	+= nfs.o
>  obj-$(CONFIG_NET_PING)	+= ping.o
>  obj-$(CONFIG_NET_RESOLV)+= dns.o
>  obj-$(CONFIG_NET_NETCONSOLE) += netconsole.o
> diff --git a/net/nfs.c b/net/nfs.c
> deleted file mode 100644
> index 9cb7dc9..0000000
> --- a/net/nfs.c
> +++ /dev/null
> @@ -1,737 +0,0 @@
> -/*
> - * NFS support driver - based on etherboot and barebox's tftp.c
> - *
> - * Masami Komiya <mkomiya at sonare.it> 2004
> - *
> - */
> -
> -/* NOTE: the NFS code is heavily inspired by the NetBSD netboot code (read:
> - * large portions are copied verbatim) as distributed in OSKit 0.97.  A few
> - * changes were necessary to adapt the code to Etherboot and to fix several
> - * inconsistencies.  Also the RPC message preparation is done "by hand" to
> - * avoid adding netsprintf() which I find hard to understand and use.  */
> -
> -/* NOTE 2: Etherboot does not care about things beyond the kernel image, so
> - * it loads the kernel image off the boot server (ARP_SERVER) and does not
> - * access the client root disk (root-path in dhcpd.conf), which would use
> - * ARP_ROOTSERVER.  The root disk is something the operating system we are
> - * about to load needs to use.	This is different from the OSKit 0.97 logic.  */
> -
> -/* NOTE 3: Symlink handling introduced by Anselm M Hoffmeister, 2003-July-14
> - * If a symlink is encountered, it is followed as far as possible (recursion
> - * possible, maximum 16 steps). There is no clearing of ".."'s inside the
> - * path, so please DON'T DO THAT. thx. */
> -
> -#include <common.h>
> -#include <command.h>
> -#include <clock.h>
> -#include <net.h>
> -#include <malloc.h>
> -#include <libgen.h>
> -#include <fs.h>
> -#include <libgen.h>
> -#include <fcntl.h>
> -#include <errno.h>
> -#include <progress.h>
> -#include <linux/err.h>
> -
> -#define SUNRPC_PORT     111
> -
> -#define PROG_PORTMAP    100000
> -#define PROG_NFS        100003
> -#define PROG_MOUNT      100005
> -
> -#define MSG_CALL        0
> -#define MSG_REPLY       1
> -
> -#define PORTMAP_GETPORT 3
> -
> -#define MOUNT_ADDENTRY  1
> -#define MOUNT_UMOUNTALL 4
> -
> -#define NFS_LOOKUP      4
> -#define NFS_READLINK    5
> -#define NFS_READ        6
> -
> -#define NFS_FHSIZE      32
> -
> -enum nfs_stat {
> -	NFS_OK		= 0,
> -	NFSERR_PERM	= 1,
> -	NFSERR_NOENT	= 2,
> -	NFSERR_IO	= 5,
> -	NFSERR_NXIO	= 6,
> -	NFSERR_ACCES	= 13,
> -	NFSERR_EXIST	= 17,
> -	NFSERR_NODEV	= 19,
> -	NFSERR_NOTDIR	= 20,
> -	NFSERR_ISDIR	= 21,
> -	NFSERR_FBIG	= 27,
> -	NFSERR_NOSPC	= 28,
> -	NFSERR_ROFS	= 30,
> -	NFSERR_NAMETOOLONG=63,
> -	NFSERR_NOTEMPTY	= 66,
> -	NFSERR_DQUOT	= 69,
> -	NFSERR_STALE	= 70,
> -	NFSERR_WFLUSH	= 99,
> -};
> -
> -/* Block size used for NFS read accesses.  A RPC reply packet (including  all
> - * headers) must fit within a single Ethernet frame to avoid fragmentation.
> - * Chosen to be a power of two, as most NFS servers are optimized for this.  */
> -#define NFS_READ_SIZE   1024
> -
> -struct rpc_call {
> -	uint32_t id;
> -	uint32_t type;
> -	uint32_t rpcvers;
> -	uint32_t prog;
> -	uint32_t vers;
> -	uint32_t proc;
> -	uint32_t data[0];
> -};
> -
> -struct rpc_reply {
> -	uint32_t id;
> -	uint32_t type;
> -	uint32_t rstatus;
> -	uint32_t verifier;
> -	uint32_t v2;
> -	uint32_t astatus;
> -	uint32_t data[0];
> -};
> -
> -struct rpc_t {
> -	union {
> -		struct {
> -			uint32_t id;
> -			uint32_t type;
> -			uint32_t rpcvers;
> -			uint32_t prog;
> -			uint32_t vers;
> -			uint32_t proc;
> -			uint32_t data[1];
> -		} call;
> -		struct {
> -			uint32_t id;
> -			uint32_t type;
> -			uint32_t rstatus;
> -			uint32_t verifier;
> -			uint32_t v2;
> -			uint32_t astatus;
> -			uint32_t data[19];
> -		} reply;
> -	} u;
> -};
> -
> -#define NFS_TIMEOUT 15
> -
> -static unsigned long rpc_id = 0;
> -static int nfs_offset = -1;
> -static uint64_t nfs_timer_start;
> -static int nfs_err;
> -
> -static char dirfh[NFS_FHSIZE];	/* file handle of directory */
> -static char filefh[NFS_FHSIZE]; /* file handle of kernel image */
> -
> -static int	nfs_server_mount_port;
> -static int	nfs_server_nfs_port;
> -static int	nfs_state;
> -#define STATE_PRCLOOKUP_PROG_MOUNT_REQ	1
> -#define STATE_PRCLOOKUP_PROG_NFS_REQ	2
> -#define STATE_MOUNT_REQ			3
> -#define STATE_UMOUNT_REQ		4
> -#define STATE_LOOKUP_REQ		5
> -#define STATE_READ_REQ			6
> -#define STATE_READLINK_REQ		7
> -#define STATE_DONE			8
> -
> -static char *nfs_filename;
> -static char *nfs_path;
> -static char nfs_path_buff[2048];
> -
> -static int net_store_fd;
> -static struct net_connection *nfs_con;
> -
> -/**************************************************************************
> -RPC_ADD_CREDENTIALS - Add RPC authentication/verifier entries
> -**************************************************************************/
> -static uint32_t *rpc_add_credentials(uint32_t *p)
> -{
> -	int hl;
> -	int hostnamelen = 0;
> -
> -	/* Here's the executive summary on authentication requirements of the
> -	 * various NFS server implementations:	Linux accepts both AUTH_NONE
> -	 * and AUTH_UNIX authentication (also accepts an empty hostname field
> -	 * in the AUTH_UNIX scheme).  *BSD refuses AUTH_NONE, but accepts
> -	 * AUTH_UNIX (also accepts an empty hostname field in the AUTH_UNIX
> -	 * scheme).  To be safe, use AUTH_UNIX and pass the hostname if we have
> -	 * it (if the BOOTP/DHCP reply didn't give one, just use an empty
> -	 * hostname).  */
> -
> -	hl = (hostnamelen + 3) & ~3;
> -
> -	/* Provide an AUTH_UNIX credential.  */
> -	*p++ = htonl(1);		/* AUTH_UNIX */
> -	*p++ = htonl(hl+20);		/* auth length */
> -	*p++ = htonl(0);		/* stamp */
> -	*p++ = htonl(hostnamelen);	/* hostname string */
> -
> -	if (hostnamelen & 3)
> -		*(p + hostnamelen / 4) = 0; /* add zero padding */
> -
> -	/* memcpy(p, hostname, hostnamelen); */ /* empty hostname */
> -
> -	p += hl / 4;
> -	*p++ = 0;			/* uid */
> -	*p++ = 0;			/* gid */
> -	*p++ = 0;			/* auxiliary gid list */
> -
> -	/* Provide an AUTH_NONE verifier.  */
> -	*p++ = 0;			/* AUTH_NONE */
> -	*p++ = 0;			/* auth length */
> -
> -	return p;
> -}
> -
> -/**************************************************************************
> -RPC_LOOKUP - Lookup RPC Port numbers
> -**************************************************************************/
> -static int rpc_req(int rpc_prog, int rpc_proc, uint32_t *data, int datalen)
> -{
> -	struct rpc_call pkt;
> -	unsigned long id;
> -	int sport;
> -	int ret;
> -	unsigned char *payload = net_udp_get_payload(nfs_con);
> -
> -	id = ++rpc_id;
> -	pkt.id = htonl(id);
> -	pkt.type = htonl(MSG_CALL);
> -	pkt.rpcvers = htonl(2);	/* use RPC version 2 */
> -	pkt.prog = htonl(rpc_prog);
> -	pkt.vers = htonl(2);	/* portmapper is version 2 */
> -	pkt.proc = htonl(rpc_proc);
> -
> -	memcpy(payload, &pkt, sizeof(pkt));
> -	memcpy(payload + sizeof(pkt), data, datalen * sizeof(uint32_t));
> -
> -	if (rpc_prog == PROG_PORTMAP)
> -		sport = SUNRPC_PORT;
> -	else if (rpc_prog == PROG_MOUNT)
> -		sport = nfs_server_mount_port;
> -	else
> -		sport = nfs_server_nfs_port;
> -
> -	nfs_con->udp->uh_dport = htons(sport);
> -	ret = net_udp_send(nfs_con, sizeof(pkt) + datalen * sizeof(uint32_t));
> -
> -	return ret;
> -}
> -
> -/**************************************************************************
> -RPC_LOOKUP - Lookup RPC Port numbers
> -**************************************************************************/
> -static void rpc_lookup_req(int prog, int ver)
> -{
> -	uint32_t data[16];
> -
> -	data[0] = 0; data[1] = 0;	/* auth credential */
> -	data[2] = 0; data[3] = 0;	/* auth verifier */
> -	data[4] = htonl(prog);
> -	data[5] = htonl(ver);
> -	data[6] = htonl(17);	/* IP_UDP */
> -	data[7] = 0;
> -
> -	rpc_req(PROG_PORTMAP, PORTMAP_GETPORT, data, 8);
> -}
> -
> -/**************************************************************************
> -NFS_MOUNT - Mount an NFS Filesystem
> -**************************************************************************/
> -static void nfs_mount_req(char *path)
> -{
> -	uint32_t data[1024];
> -	uint32_t *p;
> -	int len;
> -	int pathlen;
> -
> -	pathlen = strlen (path);
> -
> -	p = &(data[0]);
> -	p = rpc_add_credentials(p);
> -
> -	*p++ = htonl(pathlen);
> -	if (pathlen & 3)
> -		*(p + pathlen / 4) = 0;
> -	memcpy (p, path, pathlen);
> -	p += (pathlen + 3) / 4;
> -
> -	len = p - &(data[0]);
> -
> -	rpc_req(PROG_MOUNT, MOUNT_ADDENTRY, data, len);
> -}
> -
> -/**************************************************************************
> -NFS_UMOUNTALL - Unmount all our NFS Filesystems on the Server
> -**************************************************************************/
> -static void nfs_umountall_req(void)
> -{
> -	uint32_t data[1024];
> -	uint32_t *p;
> -	int len;
> -
> -	if (nfs_server_mount_port < 0)
> -		/* Nothing mounted, nothing to umount */
> -		return;
> -
> -	p = &(data[0]);
> -	p = rpc_add_credentials(p);
> -
> -	len = p - &(data[0]);
> -
> -	rpc_req(PROG_MOUNT, MOUNT_UMOUNTALL, data, len);
> -}
> -
> -/***************************************************************************
> - * NFS_READLINK (AH 2003-07-14)
> - * This procedure is called when read of the first block fails -
> - * this probably happens when it's a directory or a symlink
> - * In case of successful readlink(), the dirname is manipulated,
> - * so that inside the nfs() function a recursion can be done.
> - **************************************************************************/
> -static void nfs_readlink_req(void)
> -{
> -	uint32_t data[1024];
> -	uint32_t *p;
> -	int len;
> -
> -	p = &(data[0]);
> -	p = rpc_add_credentials(p);
> -
> -	memcpy (p, filefh, NFS_FHSIZE);
> -	p += (NFS_FHSIZE / 4);
> -
> -	len = p - &(data[0]);
> -
> -	rpc_req(PROG_NFS, NFS_READLINK, data, len);
> -}
> -
> -/**************************************************************************
> -NFS_LOOKUP - Lookup Pathname
> -**************************************************************************/
> -static void nfs_lookup_req(char *fname)
> -{
> -	uint32_t data[1024];
> -	uint32_t *p;
> -	int len;
> -	int fnamelen;
> -
> -	fnamelen = strlen (fname);
> -
> -	p = &(data[0]);
> -	p = rpc_add_credentials(p);
> -
> -	memcpy (p, dirfh, NFS_FHSIZE);
> -	p += (NFS_FHSIZE / 4);
> -	*p++ = htonl(fnamelen);
> -	if (fnamelen & 3)
> -		*(p + fnamelen / 4) = 0;
> -	memcpy (p, fname, fnamelen);
> -	p += (fnamelen + 3) / 4;
> -
> -	len = p - &(data[0]);
> -
> -	rpc_req(PROG_NFS, NFS_LOOKUP, data, len);
> -}
> -
> -/**************************************************************************
> -NFS_READ - Read File on NFS Server
> -**************************************************************************/
> -static void nfs_read_req(int offset, int readlen)
> -{
> -	uint32_t data[1024];
> -	uint32_t *p;
> -	int len;
> -
> -	p = &(data[0]);
> -	p = rpc_add_credentials(p);
> -
> -	memcpy (p, filefh, NFS_FHSIZE);
> -	p += (NFS_FHSIZE / 4);
> -	*p++ = htonl(offset);
> -	*p++ = htonl(readlen);
> -	*p++ = 0;
> -
> -	len = p - &(data[0]);
> -
> -	rpc_req(PROG_NFS, NFS_READ, data, len);
> -}
> -
> -/**************************************************************************
> -RPC request dispatcher
> -**************************************************************************/
> -static void nfs_send(void)
> -{
> -	debug("%s\n", __func__);
> -
> -	switch (nfs_state) {
> -	case STATE_PRCLOOKUP_PROG_MOUNT_REQ:
> -		rpc_lookup_req(PROG_MOUNT, 1);
> -		break;
> -	case STATE_PRCLOOKUP_PROG_NFS_REQ:
> -		rpc_lookup_req(PROG_NFS, 2);
> -		break;
> -	case STATE_MOUNT_REQ:
> -		nfs_mount_req(nfs_path);
> -		break;
> -	case STATE_UMOUNT_REQ:
> -		nfs_umountall_req();
> -		break;
> -	case STATE_LOOKUP_REQ:
> -		nfs_lookup_req(nfs_filename);
> -		break;
> -	case STATE_READ_REQ:
> -		nfs_read_req(nfs_offset, NFS_READ_SIZE);
> -		break;
> -	case STATE_READLINK_REQ:
> -		nfs_readlink_req();
> -		break;
> -	}
> -
> -	nfs_timer_start = get_time_ns();
> -}
> -
> -static int rpc_check_reply(unsigned char *pkt, int isnfs)
> -{
> -	uint32_t *data;
> -	int nfserr;
> -	struct rpc_reply rpc;
> -
> -	memcpy(&rpc, pkt, sizeof(rpc));
> -
> -	if (ntohl(rpc.id) != rpc_id)
> -		return -EINVAL;
> -
> -	if (rpc.rstatus  ||
> -	    rpc.verifier ||
> -	    rpc.astatus ) {
> -		return -EINVAL;
> -	}
> -
> -	if (!isnfs)
> -		return 0;
> -
> -	data = (uint32_t *)(pkt + sizeof(struct rpc_reply));
> -	nfserr = ntohl(net_read_uint32(data));
> -
> -	debug("%s: state: %d, err %d\n", __func__, nfs_state, -nfserr);
> -
> -	if (nfserr <= 30)
> -		/* These nfs codes correspond with those in errno.h */
> -		return -nfserr;
> -	if (nfserr == NFSERR_STALE)
> -		return -ESTALE;
> -
> -	return -EINVAL;
> -}
> -
> -static int rpc_lookup_reply(int prog, unsigned char *pkt, unsigned len)
> -{
> -	uint32_t port;
> -	int ret;
> -
> -	ret = rpc_check_reply(pkt, 0);
> -	if (ret)
> -		return ret;
> -
> -	port = net_read_uint32((uint32_t *)(pkt + sizeof(struct rpc_reply)));
> -	switch (prog) {
> -	case PROG_MOUNT:
> -		nfs_server_mount_port = ntohl(port);
> -		break;
> -	case PROG_NFS:
> -		nfs_server_nfs_port = ntohl(port);
> -		break;
> -	}
> -
> -	return 0;
> -}
> -
> -static int nfs_mount_reply(unsigned char *pkt, unsigned len)
> -{
> -	int ret;
> -
> -	ret = rpc_check_reply(pkt, 1);
> -	if (ret)
> -		return ret;
> -
> -	memcpy(dirfh, pkt + sizeof(struct rpc_reply) + 4, NFS_FHSIZE);
> -
> -	return 0;
> -}
> -
> -static int nfs_umountall_reply(unsigned char *pkt, unsigned len)
> -{
> -	int ret;
> -
> -	ret = rpc_check_reply(pkt, 0);
> -	if (ret)
> -		return ret;
> -
> -	memset(dirfh, 0, sizeof(dirfh));
> -
> -	return 0;
> -}
> -
> -static int nfs_lookup_reply(unsigned char *pkt, unsigned len)
> -{
> -	int ret;
> -
> -	ret = rpc_check_reply(pkt, 1);
> -	if (ret)
> -		return ret;
> -
> -	memcpy(filefh, pkt + sizeof(struct rpc_reply) + 4, NFS_FHSIZE);
> -
> -	return 0;
> -}
> -
> -static int nfs_readlink_reply(unsigned char *pkt, unsigned len)
> -{
> -	uint32_t *data;
> -	char *path;
> -	int rlen;
> -	int ret;
> -
> -	ret = rpc_check_reply(pkt, 1);
> -	if (ret)
> -		return ret;
> -
> -	data = (uint32_t *)(pkt + sizeof(struct rpc_reply));
> -
> -	data++;
> -
> -	rlen = ntohl(net_read_uint32(data)); /* new path length */
> -
> -	data++;
> -	path = (char *)data;
> -
> -	if (*path != '/') {
> -		strcat(nfs_path, "/");
> -		strncat(nfs_path, path, rlen);
> -	} else {
> -		memcpy(nfs_path, path, rlen);
> -		nfs_path[rlen] = 0;
> -	}
> -	return 0;
> -}
> -
> -static int nfs_read_reply(unsigned char *pkt, unsigned len)
> -{
> -	int rlen;
> -	uint32_t *data;
> -	int ret;
> -
> -	debug("%s\n", __func__);
> -
> -	ret = rpc_check_reply(pkt, 1);
> -	if (ret)
> -		return ret;
> -
> -	data = (uint32_t *)(pkt + sizeof(struct rpc_reply));
> -
> -	if (!nfs_offset) {
> -		uint32_t filesize = ntohl(net_read_uint32(data + 6));
> -		init_progression_bar(filesize);
> -	}
> -
> -	rlen = ntohl(net_read_uint32(data + 18));
> -
> -	ret = write(net_store_fd, (char *)(data + 19), rlen);
> -	if (ret < 0) {
> -		perror("write");
> -		return ret;
> -	}
> -
> -	return rlen;
> -}
> -
> -/**************************************************************************
> -Interfaces of barebox
> -**************************************************************************/
> -
> -static void nfs_handler(void *ctx, char *packet, unsigned len)
> -{
> -	char *pkt = net_eth_to_udp_payload(packet);
> -	int ret;
> -
> -	debug("%s\n", __func__);
> -
> -	switch (nfs_state) {
> -	case STATE_PRCLOOKUP_PROG_MOUNT_REQ:
> -		ret = rpc_lookup_reply(PROG_MOUNT, pkt, len);
> -		if (ret)
> -			goto err_out;
> -		nfs_state = STATE_PRCLOOKUP_PROG_NFS_REQ;
> -		break;
> -
> -	case STATE_PRCLOOKUP_PROG_NFS_REQ:
> -		ret = rpc_lookup_reply(PROG_NFS, pkt, len);
> -		if (ret)
> -			goto err_out;
> -		nfs_state = STATE_MOUNT_REQ;
> -		break;
> -
> -	case STATE_MOUNT_REQ:
> -		ret = nfs_mount_reply(pkt, len);
> -		if (ret)
> -			goto err_out;
> -
> -		nfs_state = STATE_LOOKUP_REQ;
> -		break;
> -
> -	case STATE_UMOUNT_REQ:
> -		ret = nfs_umountall_reply(pkt, len);
> -		if (ret)
> -			nfs_err = ret;
> -		nfs_state = STATE_DONE;
> -		return;
> -
> -	case STATE_LOOKUP_REQ:
> -		ret = nfs_lookup_reply(pkt, len);
> -		if (ret)
> -			goto err_umount;
> -
> -		nfs_state = STATE_READ_REQ;
> -		nfs_offset = 0;
> -		break;
> -
> -	case STATE_READLINK_REQ:
> -		ret = nfs_readlink_reply(pkt, len);
> -		if (ret)
> -			goto err_umount;
> -
> -		debug("Symlink --> %s\n", nfs_path);
> -
> -		nfs_filename = basename(nfs_path);
> -		nfs_path     = dirname(nfs_path);
> -
> -		nfs_state = STATE_MOUNT_REQ;
> -		break;
> -
> -	case STATE_READ_REQ:
> -		ret = nfs_read_reply(pkt, len);
> -		nfs_timer_start = get_time_ns();
> -		if (ret > 0)
> -			nfs_offset += ret;
> -		else if (ret == -EISDIR || ret == -EINVAL)
> -			/* symbolic link */
> -			nfs_state = STATE_READLINK_REQ;
> -		else
> -			goto err_umount;
> -		show_progress(nfs_offset);
> -		break;
> -	}
> -
> -	nfs_send();
> -
> -	return;
> -
> -err_umount:
> -	nfs_state = STATE_UMOUNT_REQ;
> -	nfs_err = ret;
> -	nfs_send();
> -	return;
> -
> -err_out:
> -	nfs_state = STATE_DONE;
> -	nfs_err = ret;
> -}
> -
> -static void nfs_start(char *p)
> -{
> -	debug("%s\n", __func__);
> -
> -	nfs_path = (char *)nfs_path_buff;
> -
> -	strcpy(nfs_path, p);
> -
> -	nfs_filename = basename (nfs_path);
> -	nfs_path     = dirname (nfs_path);
> -
> -	printf("\nFilename '%s/%s'.\n", nfs_path, nfs_filename);
> -
> -	nfs_state = STATE_PRCLOOKUP_PROG_MOUNT_REQ;
> -
> -	nfs_send();
> -}
> -
> -static int do_nfs(int argc, char *argv[])
> -{
> -	char  *localfile;
> -	char  *remotefile;
> -
> -	if (argc < 2)
> -		return COMMAND_ERROR_USAGE;
> -
> -	remotefile = argv[1];
> -
> -	if (argc == 2)
> -		localfile = basename(remotefile);
> -	else
> -		localfile = argv[2];
> -
> -	net_store_fd = open(localfile, O_WRONLY | O_CREAT);
> -	if (net_store_fd < 0) {
> -		perror("open");
> -		return 1;
> -	}
> -
> -	nfs_con = net_udp_new(net_get_serverip(), 0, nfs_handler, NULL);
> -	if (IS_ERR(nfs_con)) {
> -		nfs_err = PTR_ERR(nfs_con);
> -		goto err_udp;
> -	}
> -	net_udp_bind(nfs_con, 1000);
> -
> -	nfs_err = 0;
> -
> -	nfs_start(remotefile);
> -
> -	while (nfs_state != STATE_DONE) {
> -		if (ctrlc()) {
> -			nfs_err = -EINTR;
> -			break;
> -		}
> -		net_poll();
> -		if (is_timeout(nfs_timer_start, NFS_TIMEOUT * SECOND)) {
> -			show_progress(-1);
> -			nfs_send();
> -		}
> -	}
> -
> -	net_unregister(nfs_con);
> -err_udp:
> -	close(net_store_fd);
> -	if (nfs_err) {
> -		printf("NFS failed: %s\n", strerror(-nfs_err));
> -		unlink(localfile);
> -	}
> -
> -	printf("\n");
> -
> -	return nfs_err == 0 ? 0 : 1;
> -}
> -
> -static const __maybe_unused char cmd_nfs_help[] =
> -"Usage: nfs <file> [localfile]\n"
> -"Load a file via network using nfs protocol.\n";
> -
> -BAREBOX_CMD_START(nfs)
> -	.cmd		= do_nfs,
> -	.usage		= "boot image via network using nfs protocol",
> -	BAREBOX_CMD_HELP(cmd_nfs_help)
> -BAREBOX_CMD_END
> -
> -- 
> 1.8.5.3
> 
> 
> _______________________________________________
> barebox mailing list
> barebox at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/barebox


From plagnioj at jcrosoft.com  Mon Mar  3 23:02:06 2014
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Tue, 4 Mar 2014 05:02:06 +0100
Subject: nand pmecc crash detected
In-Reply-To: <5313FACC.8030202@atmel.com>
References: <5310B108.8040800@celad.com>
 <5313FACC.8030202@atmel.com>
Message-ID: <20140304040206.GO9671@ns203013.ovh.net>

On 11:45 Mon 03 Mar     , Josh Wu wrote:
> Dear Herve
> 
> On 2/28/2014 11:53 PM, Herve Codina wrote:
> >Hi,
> >
> >I am using an sam5d35 and its pmecc nand ecc controller.
> >
> >In barebox, using similar atmel_nand.c the system crashes.
> >
> >The problem was a call to chip->ecc.hwctl from nand_write_subpage_hwecc
> >(nand_base.c) when we write a sub page.
> >
> >chip->ecc.hwctl function is not set when we are using PMECC controller.
> >
> >As a workaround, i set NAND_NO_SUBPAGE_WRITE for PMECC controller in
> >order to disable sub page access in nand_write_page.
> >
> >I think we can have the same problem in Linux. I do not performed
> >subpage nand writes from Linux but i made the following patch according
> >to my Barebox defect.
> 
> Thank you for catching this crash bug. The fix is fine for me. But I
> think it's better to send out the Linux kernel patch alone.
> 
> You can rebase your patch on the top of Linux-mtd git
> repo(git://git.infradead.org/l2-mtd.git) instead of your local
> Linux.
> Then use 'git send-email' send to linux-mtd at lists.infradead.org and
> linux-arm-kernel at lists.infradead.org. I will ack your patch.
> 
> If the patch is merged in Linux-mtd, it should be easier port to
> barebox then.

no need for that notion of priority send it to both

Best Regards,
J.
> 
> >
> >Here after are my patches (same modification) for 1st my local Barebox
> >and 2nd my local Linux :
> >
> >---8<-------------------
> > From 757e8dbf141619a55b7a5b1ca11780b2589eacc1 Mon Sep 17 00:00:00 2001
> >From: Herve Codina <Herve.CODINA at celad.com>
> >Date: Fri, 28 Feb 2014 08:39:08 +0100
> >Subject: [PATCH 5/5] Disable Subpage nand write when using Atmel PMECC.
> >
> >
> >Signed-off-by: Herve Codina <Herve.CODINA at celad.com>
> >---
> >  drivers/mtd/nand/atmel_nand.c |    1 +
> >  1 file changed, 1 insertion(+)
> >
> >diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
> >index 2ff7427..cdbe685 100644
> >--- a/drivers/mtd/nand/atmel_nand.c
> >+++ b/drivers/mtd/nand/atmel_nand.c
> >@@ -837,6 +837,7 @@ static int __init
> >atmel_pmecc_nand_init_params(struct device_d *dev,
> >  		return err_no;
> >  	}
> >
> >+	nand_chip->options |= NAND_NO_SUBPAGE_WRITE;
> >  	nand_chip->ecc.read_page = atmel_nand_pmecc_read_page;
> >  	nand_chip->ecc.write_page = atmel_nand_pmecc_write_page;
> >
> 
> Best Regards,
> Josh Wu
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel


From W.Vanhauwaert at TELEVIC.com  Wed Mar  5 04:55:16 2014
From: W.Vanhauwaert at TELEVIC.com (Vanhauwaert Wouter)
Date: Wed, 5 Mar 2014 10:55:16 +0100
Subject: at91sam9260-ek ...
Message-ID: <E78BBE677EB9144B8F0A0A29674CD5338F93D8D2DF@SRV-VS06.TELEVIC.COM>

Hello,

Is the setup for a at91sam9260-ek still functioning?
I have troubles with my nand flash. At first it boots and writes BBT-tables.
However, next boot, it won't read the BBT, and has errors with the magic on the environment variables.
Erase /dev/env0 and saveenv do not make a difference.
Nandtest does not give me errors...

I'm just using the latest barebox 2014.2 and loading it on a at91sam9260-ek through usb (sam-ba). I'm just using the plain at91sam9260ek_defconfig

My output:

First boot:
barebox 2014.02.0 #4 Wed Mar 5 10:39:35 CET 2014

Board: Atmel at91sam9260-ek
AT91: Detected soc type: at91sam9260
AT91: Detected soc subtype: Unknown
Clocks: CPU 198 MHz, master 99 MHz, main 18.432 MHz
netconsole: registered as cs1
atmel_nand: Use On Flash BBT
nand: NAND device: Manufacturer ID: 0xec, Chip ID: 0xda (Samsung NAND 256MiB 3,3                                                      V 8-bit), 256MiB, page size: 2048, OOB size: 64
Bad block table not found for chip 0
Bad block table not found for chip 0
Scanning device for bad blocks
Bad block table written to 0x00000ffe0000, version 0x01
Bad block table written to 0x00000ffc0000, version 0x01
mdio_bus: miibus0: probed
macb macb0: Cadence MACB at 0xfffc4000
at91_udc at91_udc0: at91_udc version 3 May 2006
atmel_mci atmel_mci0: version: 0x210
atmel_mci atmel_mci0: registered as atmel_mci0
atmel_mci atmel_mci0: command/data timeout
atmel_mci atmel_mci0: command/data timeout
atmel_mci atmel_mci0: command/data timeout
malloc space: 0x23b00000 -> 0x23efffff (size 4 MiB)
envfs: wrong magic on /dev/env0
no valid environment found on /dev/env0. Using default environment
running /env/bin/init...
enable tty over USB Device, increase the boot delay to 16s

Hit any key to stop autoboot

Second boot:
barebox 2014.02.0 #4 Wed Mar 5 10:39:35 CET 2014

Board: Atmel at91sam9260-ek
AT91: Detected soc type: at91sam9260
AT91: Detected soc subtype: Unknown
Clocks: CPU 198 MHz, master 99 MHz, main 18.432 MHz
netconsole: registered as cs1
atmel_nand: Use On Flash BBT
nand: NAND device: Manufacturer ID: 0xec, Chip ID: 0xda (Samsung NAND 256MiB 3,3                                                      V 8-bit), 256MiB, page size: 2048, OOB size: 64
Bad block table found at page 131008, version 0x01
Bad block table found at page 130944, version 0x01
nand_bbt: error reading BBT
mdio_bus: miibus0: probed
macb macb0: Cadence MACB at 0xfffc4000
at91_udc at91_udc0: at91_udc version 3 May 2006
atmel_mci atmel_mci0: version: 0x210
atmel_mci atmel_mci0: registered as atmel_mci0
atmel_mci atmel_mci0: command/data timeout
atmel_mci atmel_mci0: command/data timeout
atmel_mci atmel_mci0: command/data timeout
malloc space: 0x23b00000 -> 0x23efffff (size 4 MiB)
envfs: wrong magic on /dev/env0
no valid environment found on /dev/env0. Using default environment
running /env/bin/init...
enable tty over USB Device, increase the boot delay to 16s

Hit any key to stop autoboot


From s.trumtrar at pengutronix.de  Wed Mar  5 06:47:11 2014
From: s.trumtrar at pengutronix.de (Steffen Trumtrar)
Date: Wed,  5 Mar 2014 12:47:11 +0100
Subject: [PATCH] Makefile: add target for gtags
Message-ID: <1394020031-339-1-git-send-email-s.trumtrar@pengutronix.de>

The scripts/tags.sh file already supports the generation of gtags with
GNU GLOBAL. The only thing missing is the makefile target to use it.

Copy the setup from the Linux Kernel to allow usage of gtags with barebox.

Signed-off-by: Steffen Trumtrar <s.trumtrar at pengutronix.de>
---
 Makefile |    7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/Makefile b/Makefile
index 640e589..502e009 100644
--- a/Makefile
+++ b/Makefile
@@ -353,7 +353,7 @@ endif
 # of make so .config is not included in this case either (for *config).
 
 no-dot-config-targets := clean mrproper distclean \
-			 cscope TAGS tags help %docs check% \
+			 cscope gtags TAGS tags help %docs check% \
 			 include/generated/version.h headers_% \
 			 kernelrelease kernelversion
 
@@ -986,7 +986,7 @@ MRPROPER_DIRS  += include/config include2 usr/include
 MRPROPER_FILES += .config .config.old include/asm .version .old_version \
                   include/generated/autoconf.h include/generated/version.h      \
                   include/generated/utsrelease.h include/config.h           \
-		  Module.symvers tags TAGS cscope*
+		  Module.symvers tags TAGS cscope* GPATH GTAGS GRTAGS GSYMS
 
 # clean - Delete most, but leave enough to build external modules
 #
@@ -1072,6 +1072,7 @@ help:
 	@echo  '  dir/file.ko     - Build module including final link'
 	@echo  '  tags/TAGS	  - Generate tags file for editors'
 	@echo  '  cscope	  - Generate cscope index'
+	@echo  '  gtags	  	  - Generate GNU GLOBAL index'
 	@echo  '                    (default: $(INSTALL_HDR_PATH))'
 	@echo  ''
 	@echo  'Static analysers'
@@ -1114,7 +1115,7 @@ htmldocs: Doxyfile.version
 quiet_cmd_tags = GEN     $@
       cmd_tags = $(CONFIG_SHELL) $(srctree)/scripts/tags.sh $@
 
-tags TAGS cscope: FORCE
+tags TAGS cscope gtags: FORCE
 	$(call cmd,tags)
 
 
-- 
1.7.10.4



From baruch at tkos.co.il  Wed Mar  5 06:55:57 2014
From: baruch at tkos.co.il (Baruch Siach)
Date: Wed, 5 Mar 2014 13:55:57 +0200
Subject: [PATCH] Makefile: add target for gtags
In-Reply-To: <1394020031-339-1-git-send-email-s.trumtrar@pengutronix.de>
References: <1394020031-339-1-git-send-email-s.trumtrar@pengutronix.de>
Message-ID: <20140305115557.GJ4238@tarshish>

Hi Steffen,

On Wed, Mar 05, 2014 at 12:47:11PM +0100, Steffen Trumtrar wrote:
> The scripts/tags.sh file already supports the generation of gtags with
> GNU GLOBAL. The only thing missing is the makefile target to use it.
> 
> Copy the setup from the Linux Kernel to allow usage of gtags with barebox.

Adding gnu global generated files to top level .gitignore would be nice as 
well. See kernel commit f2ac5e78928bf.

baruch

> Signed-off-by: Steffen Trumtrar <s.trumtrar at pengutronix.de>
> ---
>  Makefile |    7 ++++---
>  1 file changed, 4 insertions(+), 3 deletions(-)
> 
> diff --git a/Makefile b/Makefile
> index 640e589..502e009 100644
> --- a/Makefile
> +++ b/Makefile
> @@ -353,7 +353,7 @@ endif
>  # of make so .config is not included in this case either (for *config).
>  
>  no-dot-config-targets := clean mrproper distclean \
> -			 cscope TAGS tags help %docs check% \
> +			 cscope gtags TAGS tags help %docs check% \
>  			 include/generated/version.h headers_% \
>  			 kernelrelease kernelversion
>  
> @@ -986,7 +986,7 @@ MRPROPER_DIRS  += include/config include2 usr/include
>  MRPROPER_FILES += .config .config.old include/asm .version .old_version \
>                    include/generated/autoconf.h include/generated/version.h      \
>                    include/generated/utsrelease.h include/config.h           \
> -		  Module.symvers tags TAGS cscope*
> +		  Module.symvers tags TAGS cscope* GPATH GTAGS GRTAGS GSYMS
>  
>  # clean - Delete most, but leave enough to build external modules
>  #
> @@ -1072,6 +1072,7 @@ help:
>  	@echo  '  dir/file.ko     - Build module including final link'
>  	@echo  '  tags/TAGS	  - Generate tags file for editors'
>  	@echo  '  cscope	  - Generate cscope index'
> +	@echo  '  gtags	  	  - Generate GNU GLOBAL index'
>  	@echo  '                    (default: $(INSTALL_HDR_PATH))'
>  	@echo  ''
>  	@echo  'Static analysers'
> @@ -1114,7 +1115,7 @@ htmldocs: Doxyfile.version
>  quiet_cmd_tags = GEN     $@
>        cmd_tags = $(CONFIG_SHELL) $(srctree)/scripts/tags.sh $@
>  
> -tags TAGS cscope: FORCE
> +tags TAGS cscope gtags: FORCE
>  	$(call cmd,tags)
>  
>  
> -- 
> 1.7.10.4

-- 
     http://baruch.siach.name/blog/                  ~. .~   Tk Open Systems
=}------------------------------------------------ooO--U--Ooo------------{=
   - baruch at tkos.co.il - tel: +972.2.679.5364, http://www.tkos.co.il -


From s.trumtrar at pengutronix.de  Wed Mar  5 06:59:17 2014
From: s.trumtrar at pengutronix.de (Steffen Trumtrar)
Date: Wed, 5 Mar 2014 12:59:17 +0100
Subject: [PATCH] Makefile: add target for gtags
In-Reply-To: <20140305115557.GJ4238@tarshish>
References: <1394020031-339-1-git-send-email-s.trumtrar@pengutronix.de>
 <20140305115557.GJ4238@tarshish>
Message-ID: <20140305115917.GF6918@pengutronix.de>

On Wed, Mar 05, 2014 at 01:55:57PM +0200, Baruch Siach wrote:
> Hi Steffen,
> 
> On Wed, Mar 05, 2014 at 12:47:11PM +0100, Steffen Trumtrar wrote:
> > The scripts/tags.sh file already supports the generation of gtags with
> > GNU GLOBAL. The only thing missing is the makefile target to use it.
> > 
> > Copy the setup from the Linux Kernel to allow usage of gtags with barebox.
> 
> Adding gnu global generated files to top level .gitignore would be nice as 
> well. See kernel commit f2ac5e78928bf.

Oops, yeah. Of course. I will add that.

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From s.trumtrar at pengutronix.de  Wed Mar  5 07:02:09 2014
From: s.trumtrar at pengutronix.de (Steffen Trumtrar)
Date: Wed,  5 Mar 2014 13:02:09 +0100
Subject: [PATCH v2] Makefile: add target for gtags
Message-ID: <1394020929-7603-1-git-send-email-s.trumtrar@pengutronix.de>

The scripts/tags.sh file already supports the generation of gtags with
GNU GLOBAL. The only thing missing is the makefile target to use it.

Copy the setup from the Linux Kernel to allow usage of gtags with barebox.

Signed-off-by: Steffen Trumtrar <s.trumtrar at pengutronix.de>
---
 .gitignore |    6 ++++++
 Makefile   |    7 ++++---
 2 files changed, 10 insertions(+), 3 deletions(-)

diff --git a/.gitignore b/.gitignore
index 1dec248..710bce0 100644
--- a/.gitignore
+++ b/.gitignore
@@ -70,6 +70,12 @@ series
 # cscope files
 cscope.*
 
+# gnu global files
+GPATH
+GRTAGS
+GSYMS
+GTAGS
+
 # patches
 *.patch
 scripts/gen_netx_image
diff --git a/Makefile b/Makefile
index 640e589..502e009 100644
--- a/Makefile
+++ b/Makefile
@@ -353,7 +353,7 @@ endif
 # of make so .config is not included in this case either (for *config).
 
 no-dot-config-targets := clean mrproper distclean \
-			 cscope TAGS tags help %docs check% \
+			 cscope gtags TAGS tags help %docs check% \
 			 include/generated/version.h headers_% \
 			 kernelrelease kernelversion
 
@@ -986,7 +986,7 @@ MRPROPER_DIRS  += include/config include2 usr/include
 MRPROPER_FILES += .config .config.old include/asm .version .old_version \
                   include/generated/autoconf.h include/generated/version.h      \
                   include/generated/utsrelease.h include/config.h           \
-		  Module.symvers tags TAGS cscope*
+		  Module.symvers tags TAGS cscope* GPATH GTAGS GRTAGS GSYMS
 
 # clean - Delete most, but leave enough to build external modules
 #
@@ -1072,6 +1072,7 @@ help:
 	@echo  '  dir/file.ko     - Build module including final link'
 	@echo  '  tags/TAGS	  - Generate tags file for editors'
 	@echo  '  cscope	  - Generate cscope index'
+	@echo  '  gtags	  	  - Generate GNU GLOBAL index'
 	@echo  '                    (default: $(INSTALL_HDR_PATH))'
 	@echo  ''
 	@echo  'Static analysers'
@@ -1114,7 +1115,7 @@ htmldocs: Doxyfile.version
 quiet_cmd_tags = GEN     $@
       cmd_tags = $(CONFIG_SHELL) $(srctree)/scripts/tags.sh $@
 
-tags TAGS cscope: FORCE
+tags TAGS cscope gtags: FORCE
 	$(call cmd,tags)
 
 
-- 
1.7.10.4



From W.Vanhauwaert at TELEVIC.com  Wed Mar  5 09:56:00 2014
From: W.Vanhauwaert at TELEVIC.com (Vanhauwaert Wouter)
Date: Wed, 5 Mar 2014 15:56:00 +0100
Subject: at91sam9260-ek ...
In-Reply-To: <E78BBE677EB9144B8F0A0A29674CD5338F93D8D2DF@SRV-VS06.TELEVIC.COM>
References: <E78BBE677EB9144B8F0A0A29674CD5338F93D8D2DF@SRV-VS06.TELEVIC.COM>
Message-ID: <E78BBE677EB9144B8F0A0A29674CD5338F93D8D578@SRV-VS06.TELEVIC.COM>

> -----Original Message----
> From: barebox [mailto:barebox-bounces at lists.infradead.org] On Behalf Of
> Vanhauwaert Wouter
> Sent: woensdag 5 maart 2014 10:55
> To: barebox at lists.infradead.org
> Subject: at91sam9260-ek ...
> 
> Hello,
> 
> Is the setup for a at91sam9260-ek still functioning?
> I have troubles with my nand flash. At first it boots and writes BBT-tables.
> However, next boot, it won't read the BBT, and has errors with the magic on the
> environment variables.
> Erase /dev/env0 and saveenv do not make a difference.
> Nandtest does not give me errors...
> 
> I'm just using the latest barebox 2014.2 and loading it on a at91sam9260-ek
> through usb (sam-ba). I'm just using the plain at91sam9260ek_defconfig
> 

loadenv /dev/env0 
Gives me: 
Envfs: wrong magic on /dev/env0
Loadenv: I/O error


From s.hauer at pengutronix.de  Thu Mar  6 04:55:41 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Thu, 6 Mar 2014 10:55:41 +0100
Subject: at91sam9260-ek ...
In-Reply-To: <E78BBE677EB9144B8F0A0A29674CD5338F93D8D2DF@SRV-VS06.TELEVIC.COM>
References: <E78BBE677EB9144B8F0A0A29674CD5338F93D8D2DF@SRV-VS06.TELEVIC.COM>
Message-ID: <20140306095541.GY17250@pengutronix.de>

On Wed, Mar 05, 2014 at 10:55:16AM +0100, Vanhauwaert Wouter wrote:
> Hello,
> 
> Is the setup for a at91sam9260-ek still functioning?
> I have troubles with my nand flash. At first it boots and writes BBT-tables.
> However, next boot, it won't read the BBT, and has errors with the magic on the environment variables.
> Erase /dev/env0 and saveenv do not make a difference.
> Nandtest does not give me errors...
> 
> I'm just using the latest barebox 2014.2 and loading it on a at91sam9260-ek through usb (sam-ba). I'm just using the plain at91sam9260ek_defconfig

Seems there's something broken. I have no better idea other than
bisecting it.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From W.Vanhauwaert at TELEVIC.com  Thu Mar  6 05:04:28 2014
From: W.Vanhauwaert at TELEVIC.com (Vanhauwaert Wouter)
Date: Thu, 6 Mar 2014 11:04:28 +0100
Subject: at91sam9260-ek ...
In-Reply-To: <20140306095541.GY17250@pengutronix.de>
References: <E78BBE677EB9144B8F0A0A29674CD5338F93D8D2DF@SRV-VS06.TELEVIC.COM>
 <20140306095541.GY17250@pengutronix.de>
Message-ID: <E78BBE677EB9144B8F0A0A29674CD5338F93D8D897@SRV-VS06.TELEVIC.COM>

> -----Original Message-----
> From: Sascha Hauer [mailto:s.hauer at pengutronix.de]
> Sent: donderdag 6 maart 2014 10:56
> To: Vanhauwaert Wouter
> Cc: barebox at lists.infradead.org
> Subject: Re: at91sam9260-ek ...
> 
> On Wed, Mar 05, 2014 at 10:55:16AM +0100, Vanhauwaert Wouter wrote:
> > Hello,
> >
> > Is the setup for a at91sam9260-ek still functioning?
> > I have troubles with my nand flash. At first it boots and writes BBT-tables.
> > However, next boot, it won't read the BBT, and has errors with the magic on
> the environment variables.
> > Erase /dev/env0 and saveenv do not make a difference.
> > Nandtest does not give me errors...
> >
> > I'm just using the latest barebox 2014.2 and loading it on a
> > at91sam9260-ek through usb (sam-ba). I'm just using the plain
> > at91sam9260ek_defconfig
> 
> Seems there's something broken. I have no better idea other than bisecting it.
> 

Is there a version which is definitely working and tested with at91sam9260-ek?


From s.hauer at pengutronix.de  Thu Mar  6 05:18:26 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Thu, 6 Mar 2014 11:18:26 +0100
Subject: at91sam9260-ek ...
In-Reply-To: <E78BBE677EB9144B8F0A0A29674CD5338F93D8D897@SRV-VS06.TELEVIC.COM>
References: <E78BBE677EB9144B8F0A0A29674CD5338F93D8D2DF@SRV-VS06.TELEVIC.COM>
 <20140306095541.GY17250@pengutronix.de>
 <E78BBE677EB9144B8F0A0A29674CD5338F93D8D897@SRV-VS06.TELEVIC.COM>
Message-ID: <20140306101826.GA17250@pengutronix.de>

On Thu, Mar 06, 2014 at 11:04:28AM +0100, Vanhauwaert Wouter wrote:
> > -----Original Message-----
> > From: Sascha Hauer [mailto:s.hauer at pengutronix.de]
> > Sent: donderdag 6 maart 2014 10:56
> > To: Vanhauwaert Wouter
> > Cc: barebox at lists.infradead.org
> > Subject: Re: at91sam9260-ek ...
> > 
> > On Wed, Mar 05, 2014 at 10:55:16AM +0100, Vanhauwaert Wouter wrote:
> > > Hello,
> > >
> > > Is the setup for a at91sam9260-ek still functioning?
> > > I have troubles with my nand flash. At first it boots and writes BBT-tables.
> > > However, next boot, it won't read the BBT, and has errors with the magic on
> > the environment variables.
> > > Erase /dev/env0 and saveenv do not make a difference.
> > > Nandtest does not give me errors...
> > >
> > > I'm just using the latest barebox 2014.2 and loading it on a
> > > at91sam9260-ek through usb (sam-ba). I'm just using the plain
> > > at91sam9260ek_defconfig
> > 
> > Seems there's something broken. I have no better idea other than bisecting it.
> > 
> 
> Is there a version which is definitely working and tested with at91sam9260-ek?

I'd probably start at somewhere near:

ecdb717 at91/boards: switch to software ecc as in linux kernel

But I don't know if that version really works.

(If you don't know already, you can always start barebox second stage
from an already running barebox, normally you shouldn't have to reflash
for each bisecting step. Something like "tftp barebox.bin /dev/ram0; go
/dev/ram0" should work.)

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From W.Vanhauwaert at TELEVIC.com  Thu Mar  6 07:04:20 2014
From: W.Vanhauwaert at TELEVIC.com (Vanhauwaert Wouter)
Date: Thu, 6 Mar 2014 13:04:20 +0100
Subject: at91sam9260-ek ...
In-Reply-To: <20140306101826.GA17250@pengutronix.de>
References: <E78BBE677EB9144B8F0A0A29674CD5338F93D8D2DF@SRV-VS06.TELEVIC.COM>
 <20140306095541.GY17250@pengutronix.de>
 <E78BBE677EB9144B8F0A0A29674CD5338F93D8D897@SRV-VS06.TELEVIC.COM>
 <20140306101826.GA17250@pengutronix.de>
Message-ID: <E78BBE677EB9144B8F0A0A29674CD5338F93D8D937@SRV-VS06.TELEVIC.COM>


> -----Original Message-----
> From: Sascha Hauer [mailto:s.hauer at pengutronix.de]
> Sent: donderdag 6 maart 2014 11:18
> To: Vanhauwaert Wouter
> Cc: barebox at lists.infradead.org
> Subject: Re: at91sam9260-ek ...
> 
> On Thu, Mar 06, 2014 at 11:04:28AM +0100, Vanhauwaert Wouter wrote:
> > > -----Original Message-----
> > > From: Sascha Hauer [mailto:s.hauer at pengutronix.de]
> > > Sent: donderdag 6 maart 2014 10:56
> > > To: Vanhauwaert Wouter
> > > Cc: barebox at lists.infradead.org
> > > Subject: Re: at91sam9260-ek ...
> > >
> > > On Wed, Mar 05, 2014 at 10:55:16AM +0100, Vanhauwaert Wouter wrote:
> > > > Hello,
> > > >
> > > > Is the setup for a at91sam9260-ek still functioning?
> > > > I have troubles with my nand flash. At first it boots and writes BBT-tables.
> > > > However, next boot, it won't read the BBT, and has errors with the
> > > > magic on
> > > the environment variables.
> > > > Erase /dev/env0 and saveenv do not make a difference.
> > > > Nandtest does not give me errors...
> > > >
> > > > I'm just using the latest barebox 2014.2 and loading it on a
> > > > at91sam9260-ek through usb (sam-ba). I'm just using the plain
> > > > at91sam9260ek_defconfig
> > >
> > > Seems there's something broken. I have no better idea other than bisecting
> it.
> > >
> >
> > Is there a version which is definitely working and tested with at91sam9260-ek?
> 
> I'd probably start at somewhere near:
> 
> ecdb717 at91/boards: switch to software ecc as in linux kernel
> 
> But I don't know if that version really works.
> 
> (If you don't know already, you can always start barebox second stage from an
> already running barebox, normally you shouldn't have to reflash for each
> bisecting step. Something like "tftp barebox.bin /dev/ram0; go /dev/ram0"
> should work.)
> 

I did some tests and seems that it worked ok until version release 2013.08.0, from 2013.09.0 on it gives me these errors...



From W.Vanhauwaert at TELEVIC.com  Thu Mar  6 07:20:47 2014
From: W.Vanhauwaert at TELEVIC.com (Vanhauwaert Wouter)
Date: Thu, 6 Mar 2014 13:20:47 +0100
Subject: at91sam9260-ek ...
In-Reply-To: <E78BBE677EB9144B8F0A0A29674CD5338F93D8D937@SRV-VS06.TELEVIC.COM>
References: <E78BBE677EB9144B8F0A0A29674CD5338F93D8D2DF@SRV-VS06.TELEVIC.COM>
 <20140306095541.GY17250@pengutronix.de>
 <E78BBE677EB9144B8F0A0A29674CD5338F93D8D897@SRV-VS06.TELEVIC.COM>
 <20140306101826.GA17250@pengutronix.de>
 <E78BBE677EB9144B8F0A0A29674CD5338F93D8D937@SRV-VS06.TELEVIC.COM>
Message-ID: <E78BBE677EB9144B8F0A0A29674CD5338F93D8D94D@SRV-VS06.TELEVIC.COM>

> -----Original Message-----
> From: barebox [mailto:barebox-bounces at lists.infradead.org] On Behalf Of
> Vanhauwaert Wouter
> Sent: donderdag 6 maart 2014 13:04
> To: Sascha Hauer
> Cc: barebox at lists.infradead.org
> Subject: RE: at91sam9260-ek ...
> 
> 
> > I'd probably start at somewhere near:
> >
> > ecdb717 at91/boards: switch to software ecc as in linux kernel
> >
> > But I don't know if that version really works.
> >
> > (If you don't know already, you can always start barebox second stage from an
> > already running barebox, normally you shouldn't have to reflash for each
> > bisecting step. Something like "tftp barebox.bin /dev/ram0; go /dev/ram0"
> > should work.)
> >
> 
> I did some tests and seems that it worked ok until version release 2013.08.0,
> from 2013.09.0 on it gives me these errors...
> 

Between 2013.09.0 and 2013.08.0 there's much changed in the mtd driver... Also in atmel_nand.c, 2 parameters (int oob_required, int page) are added to the page operations.
Although nothing is done with it. I don't know what's going on further. I'll just stick with 2013.08.0 for now, I think it'll just fit my needs. Maybe somebody who knows what's going on can take a look at it?

Grtz,
Wouter


From shc_work at mail.ru  Thu Mar  6 09:29:54 2014
From: shc_work at mail.ru (=?UTF-8?B?QWxleGFuZGVyIFNoaXlhbg==?=)
Date: Thu, 06 Mar 2014 18:29:54 +0400
Subject: =?UTF-8?B?UmU6IGF0OTFzYW05MjYwLWVrIC4uLg==?=
In-Reply-To: <E78BBE677EB9144B8F0A0A29674CD5338F93D8D94D@SRV-VS06.TELEVIC.COM>
References: <E78BBE677EB9144B8F0A0A29674CD5338F93D8D2DF@SRV-VS06.TELEVIC.COM>
 <E78BBE677EB9144B8F0A0A29674CD5338F93D8D937@SRV-VS06.TELEVIC.COM>
 <E78BBE677EB9144B8F0A0A29674CD5338F93D8D94D@SRV-VS06.TELEVIC.COM>
Message-ID: <1394116194.121153777@f66.i.mail.ru>

???????,  6 ????? 2014, 13:20 +01:00 ?? Vanhauwaert Wouter <W.Vanhauwaert at TELEVIC.com>:
> > -----Original Message-----
> > From: barebox [mailto:barebox-bounces at lists.infradead.org] On Behalf Of
> > Vanhauwaert Wouter
> > Sent: donderdag 6 maart 2014 13:04
> > To: Sascha Hauer
> > Cc: barebox at lists.infradead.org
> > Subject: RE: at91sam9260-ek ...
> > 
> > 
> > > I'd probably start at somewhere near:
> > >
> > > ecdb717 at91/boards: switch to software ecc as in linux kernel
> > >
> > > But I don't know if that version really works.
> > >
> > > (If you don't know already, you can always start barebox second stage from an
> > > already running barebox, normally you shouldn't have to reflash for each
> > > bisecting step. Something like "tftp barebox.bin /dev/ram0; go /dev/ram0"
> > > should work.)
> > >
> > 
> > I did some tests and seems that it worked ok until version release 2013.08.0,
> > from 2013.09.0 on it gives me these errors...
> > 
> 
> Between 2013.09.0 and 2013.08.0 there's much changed in the mtd driver... Also in atmel_nand.c, 2 parameters (int oob_required, int page) are added to the page operations.
> Although nothing is done with it. I don't know what's going on further. I'll just stick with 2013.08.0 for now, I think it'll just fit my needs. Maybe somebody who knows what's going on can take a look at it?

It would be great if you could find the initial point of this bug
by using git-bisect, as Sascha says.
We could help in using this tool if you have trouble.

---

From s.hauer at pengutronix.de  Thu Mar  6 11:21:00 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Thu, 6 Mar 2014 17:21:00 +0100
Subject: [PATCH 3/5] net: remove old nfs support
In-Reply-To: <20140304040345.GP9671@ns203013.ovh.net>
References: <1393534812-30995-1-git-send-email-s.hauer@pengutronix.de>
 <1393534812-30995-4-git-send-email-s.hauer@pengutronix.de>
 <20140304040345.GP9671@ns203013.ovh.net>
Message-ID: <20140306162100.GC17250@pengutronix.de>

On Tue, Mar 04, 2014 at 05:03:45AM +0100, Jean-Christophe PLAGNIOL-VILLARD wrote:
> On 22:00 Thu 27 Feb     , Sascha Hauer wrote:
> > Now that we have the NFS as filesystem support for several releases
> > remove the old command based NFS support.
> > 
> > Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
> 
> as the bootp is not fully supported on default env2 do not drop it

Ok for now, but I really want to get rid of it. Would a nfs wrapper
command be ok?

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From herve.codina at celad.com  Thu Mar  6 12:42:05 2014
From: herve.codina at celad.com (Herve Codina)
Date: Thu, 6 Mar 2014 18:42:05 +0100
Subject: nand pmecc crash detected
In-Reply-To: <5313FACC.8030202@atmel.com>
References: <5310B108.8040800@celad.com> <5313FACC.8030202@atmel.com>
Message-ID: <5318B36D.4020700@celad.com>

Dear Josh

As suggested, i made a patch and sent it this week to
linux-mtd at lists.infradead.org and linux-arm-kernel at lists.infradead.org.
Hope you have seen it. Is subject is : "[PATCH] Disable Subpage nand
write when using Atmel PMECC".

Best regards,
Herve




Le 03/03/2014 04:45, Josh Wu a ?crit :
> Dear Herve
> 
> On 2/28/2014 11:53 PM, Herve Codina wrote:
>> Hi,
>>
>> I am using an sam5d35 and its pmecc nand ecc controller.
>>
>> In barebox, using similar atmel_nand.c the system crashes.
>>
>> The problem was a call to chip->ecc.hwctl from nand_write_subpage_hwecc
>> (nand_base.c) when we write a sub page.
>>
>> chip->ecc.hwctl function is not set when we are using PMECC controller.
>>
>> As a workaround, i set NAND_NO_SUBPAGE_WRITE for PMECC controller in
>> order to disable sub page access in nand_write_page.
>>
>> I think we can have the same problem in Linux. I do not performed
>> subpage nand writes from Linux but i made the following patch according
>> to my Barebox defect.
> 
> Thank you for catching this crash bug. The fix is fine for me. But I 
> think it's better to send out the Linux kernel patch alone.
> 
> You can rebase your patch on the top of Linux-mtd git 
> repo(git://git.infradead.org/l2-mtd.git) instead of your local Linux.
> Then use 'git send-email' send to linux-mtd at lists.infradead.org and 
> linux-arm-kernel at lists.infradead.org. I will ack your patch.
> 
> If the patch is merged in Linux-mtd, it should be easier port to barebox 
> then.
> 
>>
>> Here after are my patches (same modification) for 1st my local Barebox
>> and 2nd my local Linux :
>>
>> ---8<-------------------
>>  From 757e8dbf141619a55b7a5b1ca11780b2589eacc1 Mon Sep 17 00:00:00 2001
>> From: Herve Codina <Herve.CODINA at celad.com>
>> Date: Fri, 28 Feb 2014 08:39:08 +0100
>> Subject: [PATCH 5/5] Disable Subpage nand write when using Atmel PMECC.
>>
>>
>> Signed-off-by: Herve Codina <Herve.CODINA at celad.com>
>> ---
>>   drivers/mtd/nand/atmel_nand.c |    1 +
>>   1 file changed, 1 insertion(+)
>>
>> diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
>> index 2ff7427..cdbe685 100644
>> --- a/drivers/mtd/nand/atmel_nand.c
>> +++ b/drivers/mtd/nand/atmel_nand.c
>> @@ -837,6 +837,7 @@ static int __init
>> atmel_pmecc_nand_init_params(struct device_d *dev,
>>   		return err_no;
>>   	}
>>
>> +	nand_chip->options |= NAND_NO_SUBPAGE_WRITE;
>>   	nand_chip->ecc.read_page = atmel_nand_pmecc_read_page;
>>   	nand_chip->ecc.write_page = atmel_nand_pmecc_write_page;
>>
> 
> Best Regards,
> Josh Wu
> 


From s.hauer at pengutronix.de  Fri Mar  7 01:54:07 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 7 Mar 2014 07:54:07 +0100
Subject: v2014.03.0
Message-ID: <20140307065407.GD17250@pengutronix.de>

We have a march release. The diffstat is huge this time, but this
is only due to the phytec/freescale board rename. Other things worth
noting are:

- i.MX25 and i.MX27 now have devicetree support
- We have initial MIPS Loongson support
- UBIFS Can now read links
- We can now automatically construct a console= parameter for the kernel

Sascha

----------------------------------------------------------------
Alexander Shiyan (13):
      ARM: i.MX51: Sync DT files with kernel
      ARM: freescale-mx51-pdk: Remove FEC GPIO handling
      mfd: syscon: Introduce syscon_base_lookup_by_phandle() function
      ARM: clps711x: Remove the special name for the syscon driver
      gpio: clps711x: Update driver
      serial: clps711x: Update driver
      ARM: uncompress: Remove unused variable
      ARM: animeo_ip: Use __iomem specifier for memory pointer
      ARM: at91: irq_fixup: Use __iomem specifier for memory pointer
      ARM: i.MX: external_nand_boot: Use __iomem specifier for memory pointer
      ARM: i.MX: esdctl: Use __iomem specifier for memory pointer
      ARM: i.MX: esdctl-v4: Use __iomem specifier for memory pointer
      Make generated variables static

Antony Pavlov (18):
      gpiolib: gpio_request(): print message on error
      gpiolib: gpio_free: clear gpio's "label" field too
      gpiolib: gpiolib command: show label only for requested pins
      net/phy: add driver for National Semiconductor DP83865 PHY
      MIPS: add initial Loongson-based boards support
      MIPS: add initial Loongson-family documentation
      MIPS: add Loongson-1B CPU Kbuild stuff
      MIPS: add Loongson-1B processor constants and CPU probe
      MIPS: add initial Loongson-1X SoC stuff
      MIPS: mach-loongson: add loongson-ls1b board
      MIPS: mach-loongson: add DEBUG_LL support
      MIPS: loongson-ls1b: add DEBUG_LL support
      MIPS: loongson-ls1b: add ns16550-based console
      MIPS: loongson-ls1b: add PBL support
      MIPS: loongson-ls1b: add NMON support
      MIPS: loongson-ls1b: add documentation
      MIPS: add loongson-ls1b_defconfig
      MIPS: csrc-r4k: use CLOCKSOURCE_MASK() macro

Cristiano De Alti (1):
      cfi_flash.c: correct calculation of region erasesize and offset for multiple (size_ratio > 1) chips in parallel

Herve Codina (1):
      mtd: nand: atmel pmecc: disable subpage writes

Jan Weitzel (1):
      of: find also nodes by mixture of alias and path

Jes?s Guitarte (1):
      ARM: i.MX6: correct work flow of PFDs from uboot-sources

Lucas Stach (25):
      ARM: imx6: pull imx6qdl-pingrp.h from linux
      ARM: imx6q: update sabrelite DT
      ARM: imx6: update SabreSD DTs
      ARM: imx6: update phytec-pfla02 DT
      ARM: imx6: update Carrier-1 DTs
      ARM: imx6: update TQ DTs
      ARM: imx6: update GK802 DT
      ARM: imx6: update DMO RealQ7 DT
      ARM: imx6: update DFI FS700 M60 DT
      ARM: imx6: remove old pingroups
      ARM: imx53: guard voipac vmx53 init function
      dt-bindings: import input.h
      ARM: imx6: update pin related DT headers
      ARM: imx6: update base DTs
      ARM: imx6: split sabrelite DT
      ARM: imx6: add support for DL variant of SabreLite Board
      ARM: imx6: add initial support for Nitrogen6X boards
      ARM: imx6: rename Carrier-1 to Hummingboard
      hummingboard: fix entryfunction for real
      dt-bindings: add ARM GIC
      dt-bindings: add Tegra GPIO
      dt-bindings: add Tegra CAR
      ARM: dts: pull in complete DTs from Linux 3.13
      ARM: i.MX: edmqmx6: fix startup
      ARM: i.MX: edmqmx6: choose correct env when booting from SD

Marek Vasut (2):
      net usb asix: Simplify condition in rx_fixup()
      net usb asix: Use only 11 bits of header for data size

Markus Niebel (6):
      mci: Support the correct version for eMMC
      mci: production year for eMMC 4.41 and later
      mci: add DSR support
      mci: add device tree support for DSR
      mci: imx-esdhc: add DSR support
      boards: tqma53: add DSR support for eMMC

Michael Grzeschik (2):
      sandbox: update defconfig to use new environment
      sandbox: update to new environment

Michael Olbrich (2):
      ARM: i.MX: edmqmx6: choose the environment at the correct time
      ARM: i.MX: edmqmx6: set display GPIOs

Philipp Zabel (3):
      net usb asix: read MAC from EEPROM on AX88772B
      net usb asix: add AX88772B USB ID
      ARM: i.MX: edmqmx6: correct MMDC init

Philippe R?tornaz (1):
      cfi_flash: fix NULL pointer dereference

Renaud Barbier (9):
      ppc: cpu-85xx: upgrade MMU support to v2 pages sizes
      ppc: mpc85xx: use common linker script
      ppc: mpc85xx: change bss relocation
      ppc: cpu-85xx: import U-Boot start-up code
      cpu-85xx: start.S: clean up imported code
      ppc: remove bit operation headers file conflict
      UBIFS: implement readlink entry point
      DA923RC: enable UBI/UBIFS configuration
      ppc: mpc85xx: fix memory size calculation

Robert Jarzmik (6):
      ARM: mioa701: fix frequence speedup code
      ARM: pxa: add reset source detection
      ARM: pxa: add poweroff capability
      ARM: mioa701 defconfig update
      ARM: mioa701 change MTD layout
      ARM: mioa701: poweroff the board on long power press

Sascha Hauer (100):
      list: add list_first_entry_or_null()
      bootm: introduce bootm_load_os helper
      ARM: bootm: move os loading to do_bootm_linux
      bootm: introduce bootm_load_initrd helper
      bootm: introduce bootm_load_devicetree helper
      ARM: i.MX: Add correct SoC type detection for i.MX6
      ARM: i.MX DFI FS700-M60: Add SPI NOR flash support
      ARM: i.MX DFI FS700-M60: Add SPI NOR flash update handler
      fs ubifs: Use pr_* for printing messages
      net: Fix error return value for string_to_ethaddr
      console: Set Linux console parameter automatically
      ARM: bootm: locate zImage higher into RAM
      ARM: bootm: pass free memory to __do_bootm_linux
      ARM: i.MX DFI FS700-M60: Update for new boards
      ARM: dts: rename imx6q-dmo-realq7.dts to imx6q-dmo-edmqmx6.dts
      ARM: dts: change dmo,imx6q-realq7 compatible to dmo,imx6q-edmqmx6
      ARM: Karo TX25: register external NAND boot update handler
      ARM: phyCARD-i.MX27: remove unused variable
      ARM: phyCARD-i.MX27: increase barebox and kernel partition
      ARM: phyCARD-i.MX27: register barebox update handler
      ARM: phyCARD-i.MX27: switch to new environment
      ARM: phyCARD-i.MX27: convert lowlevel init to c code
      ARM: i.MX27: Add missing MPLL clock sources
      ARM: phyCARD-i.MX27: Update defconfig
      ARM: Fix image size calculation for CONFIG_PBL_RELOCATABLE
      ARM: i.MX: external NAND boot: factor out a 2k pagesize detection function
      ARM: i.MX: external NAND boot: create function macro for different SoCs
      environment: Use accessor functions for default environment path
      environment: Fix wrong Kconfig dependency
      net: phy: Add static inline wrapper for phy_register_fixup_for_uid
      env: make path arguments to envfs_load/save const
      misc Kconfig: always ask for misc devices
      misc: Add devicetree SRAM driver
      ARM: Make thumb2 compilation only visible on CPUs that support it
      ARM: Pass armv7-a AFLAGS to cache-v7
      ARM: Do not use BUG() in pbl code
      ARM: mode cpu_architecture() to common.c
      images: remove unused command
      ARM: i.MX: external NAND boot: make it work with relocatable PBL
      ARM: i.MX: external NAND boot: do not depend on cpu_is_*
      ARM: dts: Add i.MX27 devicetree files
      ARM: dts: Add Phytec phyCARD-i.MX27 devicetree files
      ARM: i.MX: external NAND boot: pass boarddata
      pinctrl: Add pinctrl driver for i.MX1/21/27
      ARM: i.MX clocksource: return successful for multiple instances
      ARM: phycard-i.MX27: Add NAND support to dts
      ARM: phycard-i.MX27: Add stdout-path property
      ARM: dts: phycard-i.MX27: Add environment and NAND partitioning
      ARM: dts: phycard-i.MX27: Add sdhc2 pinctrl
      mci: imx: Add devicetree probe support
      ARM: phyCARD-i.MX27: Switch to devicetree probe support
      ARM: imx_v7_defconfig: Enable new boards
      ARM: dts: Add TQ tqma53/mba53 dts files
      ARM: dts: i.MX53: tqma53: Add barebox specifics
      ARM: i.MX53: tqma53: Switch to devicetree and multiboard support
      reset_source: rename set_reset_source to reset_source_set
      reset_source: add reset_source_get
      scripts: fix_size: check magic
      images: fix image size in pblx
      ARM: i.MX: external NAND boot: use image size from image header
      ARM: i.MX: external NAND boot: make dtb boarddata work
      mci: imx-esdhc: Add i.MX25 compatible entry
      ARM: dts: Add i.MX25 devicetree files
      ARM: dts: i.MX25: Add mmc aliases
      ARM: dts: i.MX25: remove disabled status of usbmisc unit
      ARM: i.MX25: Add missing GPT clock lookups
      ARM: dts: Add i.MX25 Karo TX25 dts
      ARM: dts: i.MX25: Add iram to devicetree
      ARM: dts: Karo TX25: Add pinctrl nodes
      ARM: dts: Karo TX25: Add phy-reset-gpio
      ARM: dts: Karo TX25: add missing nfc properties
      ARM: dts: Karo TX25: add phy supply for fec
      ARM: dts: Karo TX25: add barebox specifics
      ARM: i.MX25: Karo TX25: Switch to devicetree support
      ARM: i.MX: cleanup bootmode selection
      ARM: i.MX: Karo TX25: Switch to multiboard support
      ARM: i.MX: Add lowlevel gpio functions
      Merge branch 'for-next/arm'
      Merge branch 'for-next/bootm'
      Merge branch 'for-next/clps711x'
      Merge branch 'for-next/gpio'
      Merge branch 'for-next/imx'
      Merge branch 'for-next/iomem'
      Merge branch 'for-next/mci'
      Merge branch 'for-next/mips'
      Merge branch 'for-next/misc'
      Merge branch 'for-next/mtd'
      Merge branch 'for-next/net'
      Merge branch 'for-next/ppc'
      Merge branch 'for-next/pxa'
      Merge branch 'for-next/tegra'
      ARM: rename boards to more consistent naming
      ARM: i.MX21 ads: remove garbage at end of #ifdef
      ARM: omap3: Add missing include
      bootm: Return error when devicetree file is not a dtb
      read_file: Use read_full
      mci: Fix version handling
      fs: tftp: Fix writing files to tftp
      mtd: nand: disable subpage reads
      Release v2014.03.0

Steffen Trumtrar (2):
      ARM: i.MX53: dts: move QSB pmic to own file
      ARM: i.MX53: dts: add support for MCIMX53-START-R

??? (1):
      bugfix: don't rely on lr in arm_cpu_lowlevel_init

 Documentation/boards.dox                           |   1 +
 Makefile                                           |   2 +-
 arch/arm/Kconfig                                   |   3 +-
 arch/arm/Makefile                                  |   2 +-
 arch/arm/boards/Makefile                           |  35 +-
 arch/arm/boards/animeo_ip/init.c                   |   2 +-
 .../arm/boards/boundarydevices-nitrogen6x/Makefile |   3 +
 arch/arm/boards/boundarydevices-nitrogen6x/board.c |  77 +++
 .../env/config-board                               |   0
 .../flash-header-nitrogen6x-1g.imxcfg              | 106 ++++
 .../boards/boundarydevices-nitrogen6x/lowlevel.c   |  30 +
 .../Makefile                                       |   0
 .../{dmo-mx6-realq7 => datamodul-edm-qmx6}/board.c |  37 +-
 .../env/boot/mmc                                   |   0
 .../arm/boards/datamodul-edm-qmx6/env/config-board |   6 +
 .../env/init/automount                             |   0
 .../flash-header.imxcfg                            |   0
 .../lowlevel.c                                     |  23 +-
 arch/arm/boards/dfi-fs700-m60/Makefile             |   5 +-
 arch/arm/boards/dfi-fs700-m60/board.c              |  45 +-
 ...cfg => flash-header-fs700-m60-6q-micron.imxcfg} | 126 ++---
 .../flash-header-fs700-m60-6q-nanya.imxcfg         | 102 ++++
 .../dfi-fs700-m60/flash-header-fs700-m60-6s.imxcfg |  40 +-
 arch/arm/boards/dfi-fs700-m60/lowlevel.c           |  69 ++-
 arch/arm/boards/efika-mx-smartbook/env/config      |   2 +-
 arch/arm/boards/eukrea_cpuimx25/lowlevel.c         |  10 +-
 arch/arm/boards/eukrea_cpuimx27/lowlevel_init.S    |   5 +-
 arch/arm/boards/eukrea_cpuimx35/lowlevel.c         |  25 +-
 .../{imx21ads => freescale-mx21-ads}/Makefile      |   0
 .../{imx21ads => freescale-mx21-ads}/env/bin/init  |   0
 .../{imx21ads => freescale-mx21-ads}/imx21ads.c    |   0
 .../{imx21ads => freescale-mx21-ads}/imx21ads.dox  |   0
 .../lowlevel_init.S                                |   5 +-
 .../3stack.c                                       |   0
 .../Makefile                                       |   0
 .../env/bin/_update                                |   0
 .../env/bin/boot                                   |   0
 .../env/bin/hush_hack                              |   0
 .../env/bin/init                                   |   0
 .../env/bin/update_kernel                          |   0
 .../env/bin/update_root                            |   0
 .../env/config                                     |   0
 .../lowlevel_init.S                                |   6 +-
 .../{imx27ads => freescale-mx27-ads}/Makefile      |   0
 .../env/bin/_update                                |   0
 .../{imx27ads => freescale-mx27-ads}/env/bin/boot  |   0
 .../{imx27ads => freescale-mx27-ads}/env/bin/init  |   0
 .../env/bin/update_kernel                          |   0
 .../env/bin/update_root                            |   0
 .../{imx27ads => freescale-mx27-ads}/env/config    |   0
 .../{imx27ads => freescale-mx27-ads}/imx27ads.c    |   0
 .../{imx27ads => freescale-mx27-ads}/imx27ads.dox  |   0
 .../lowlevel_init.S                                |   0
 .../3stack.c                                       |   0
 .../3stack.dox                                     |   0
 .../Makefile                                       |   0
 .../board-mx35_3stack.h                            |   0
 .../env/config                                     |   0
 .../flash_header.c                                 |   0
 .../lowlevel_init.S                                |   5 +-
 .../Makefile                                       |   0
 .../board.c                                        |   9 +-
 .../env/config-board                               |   0
 .../flash-header-imx51-babbage.imxcfg              |   0
 .../lowlevel.c                                     |   0
 .../mx51-pdk.dox                                   |   0
 .../Makefile                                       |   0
 .../board.c                                        |   0
 .../env/config-board                               |   0
 .../flash-header-imx53-loco.imxcfg                 |   0
 .../lowlevel.c                                     |  13 +
 .../mx53-pdk.dox                                   |   0
 arch/arm/boards/freescale-mx53-vmx53/board.c       |   3 +
 arch/arm/boards/freescale-mx6-sabrelite/board.c    |   9 +-
 arch/arm/boards/freescale-mx6-sabrelite/lowlevel.c |  15 +-
 arch/arm/boards/gk802/board.c                      |   4 +-
 arch/arm/boards/guf-cupid/lowlevel.c               |  21 +-
 arch/arm/boards/guf-neso/lowlevel.c                |  11 +-
 arch/arm/boards/karo-tx25/board.c                  | 132 ++---
 arch/arm/boards/karo-tx25/env/init/mtdparts-nand   |   2 +-
 arch/arm/boards/karo-tx25/lowlevel.c               |  23 +-
 arch/arm/boards/mioa701/Makefile                   |   2 +-
 arch/arm/boards/mioa701/board.c                    |   1 +
 arch/arm/boards/mioa701/env/bin/barebox_update     |   7 +-
 arch/arm/boards/mioa701/env/bin/console_mode       |   6 +
 arch/arm/boards/mioa701/env/bin/init               |  55 +-
 arch/arm/boards/mioa701/env/bin/sdcard_override    |   3 +
 arch/arm/boards/mioa701/env/config                 |   3 +-
 arch/arm/boards/mioa701/env/data/dps1.raw.gz       | Bin 1239 -> 1324 bytes
 arch/arm/boards/mioa701/gpio0_poweroff.c           |  81 +++
 arch/arm/boards/phycard-i.MX27/Makefile            |   3 -
 arch/arm/boards/phycard-i.MX27/env/config          |  48 --
 arch/arm/boards/phycard-i.MX27/lowlevel_init.S     | 119 ----
 arch/arm/boards/phytec-phycard-imx27/Makefile      |   3 +
 arch/arm/boards/phytec-phycard-imx27/lowlevel.c    | 103 ++++
 .../pca100.c                                       | 175 +-----
 .../pca100.dox                                     |   0
 .../Makefile                                       |   0
 .../env/config                                     |   0
 .../lowlevel.c                                     |   0
 .../pca-a-l1.c                                     |   0
 .../pca-a-l1.dox                                   |   0
 .../pca-a-l1.h                                     |   0
 .../Makefile                                       |   0
 .../env/bin/nand_bootstrap                         |   0
 .../env/config                                     |   0
 .../lowlevel.c                                     |   0
 .../{phycard-a-xl2 => phytec-phycard-omap4}/mux.c  |   0
 .../pca-a-xl2.c                                    |   0
 .../{pcm051 => phytec-phycore-am335x}/Makefile     |   0
 .../{pcm051 => phytec-phycore-am335x}/board.c      |   0
 .../{pcm051 => phytec-phycore-am335x}/env/boot/mmc |   0
 .../env/boot/nand                                  |   0
 .../{pcm051 => phytec-phycore-am335x}/env/boot/spi |   0
 .../env/config-board                               |   0
 .../{pcm051 => phytec-phycore-am335x}/lowlevel.c   |   0
 .../{pcm038 => phytec-phycore-imx27}/Makefile      |   0
 .../env/boot/nand-ubi                              |   0
 .../env/config-board                               |   0
 .../env/init/mtdparts-nand                         |   0
 .../env/init/mtdparts-nor                          |   0
 .../{pcm038 => phytec-phycore-imx27}/lowlevel.c    |  10 +-
 .../{pcm038 => phytec-phycore-imx27}/pcm038.c      |   0
 .../{pcm038 => phytec-phycore-imx27}/pcm038.dox    |   0
 .../{pcm038 => phytec-phycore-imx27}/pcm970.c      |   0
 .../boards/{pcm038 => phytec-phycore-imx27}/pll.h  |   0
 .../{pcm037 => phytec-phycore-imx31}/Makefile      |   0
 .../env/boot/nand-ubi                              |   0
 .../env/config-board                               |   0
 .../env/init/mtdparts-nand                         |   0
 .../env/init/mtdparts-nor                          |   0
 .../{pcm037 => phytec-phycore-imx31}/lowlevel.c    |  14 +-
 .../{pcm037 => phytec-phycore-imx31}/pcm037.c      |   0
 .../{pcm037 => phytec-phycore-imx31}/pcm037.dox    |   0
 .../{pcm043 => phytec-phycore-imx35}/Makefile      |   0
 .../env/boot/nand-ubi                              |   0
 .../env/config-board                               |   0
 .../env/init/mtdparts-nand                         |   0
 .../env/init/mtdparts-nor                          |   0
 .../{pcm043 => phytec-phycore-imx35}/lowlevel.c    |  25 +-
 .../{pcm043 => phytec-phycore-imx35}/pcm043.c      |   0
 .../{pcm043 => phytec-phycore-imx35}/pcm043.dox    |   0
 .../{pcm049 => phytec-phycore-omap4460}/Makefile   |   0
 .../{pcm049 => phytec-phycore-omap4460}/board.c    |   0
 .../env/bin/init_board                             |   0
 .../env/bin/nand_bootstrap                         |   0
 .../{pcm049 => phytec-phycore-omap4460}/env/config |   0
 .../{pcm049 => phytec-phycore-omap4460}/lowlevel.c |   0
 .../{pcm049 => phytec-phycore-omap4460}/mux.c      |   0
 .../{pcm027 => phytec-phycore-pxa270}/Makefile     |   0
 .../{pcm027 => phytec-phycore-pxa270}/board.c      |   0
 .../{pcm027 => phytec-phycore-pxa270}/config.h     |   0
 .../{pcm027 => phytec-phycore-pxa270}/env/config   |   0
 .../lowlevel_init.S                                |   0
 .../Makefile                                       |   0
 .../{phytec-pfla02 => phytec-phyflex-imx6}/board.c |   0
 .../flash-header-phytec-pfla02-1gib.imxcfg         |   0
 .../flash-header-phytec-pfla02-2gib.imxcfg         |   0
 .../flash-header-phytec-pfla02.h                   |   0
 .../lowlevel.c                                     |   0
 arch/arm/boards/raspberry-pi/rpi.c                 |   2 +-
 arch/arm/boards/solidrun-carrier-1/Makefile        |   3 -
 arch/arm/boards/solidrun-carrier-1/lowlevel.c      |  18 -
 arch/arm/boards/solidrun-hummingboard/Makefile     |   3 +
 .../board.c                                        |  14 +-
 .../flash-header-solidrun-hummingboard.imxcfg}     |   0
 arch/arm/boards/solidrun-hummingboard/lowlevel.c   |  16 +
 arch/arm/boards/tqma53/Makefile                    |   1 -
 arch/arm/boards/tqma53/board.c                     | 245 +-------
 .../tqma53/flash-header-tq-tqma53-1gib.imxcfg      |   5 +
 .../tqma53/flash-header-tq-tqma53-512mib.imxcfg    |   5 +
 arch/arm/boards/tqma53/flash-header-tq-tqma53.h    |  61 ++
 arch/arm/boards/tqma53/flash_header.c              | 113 ----
 arch/arm/boards/tqma53/lowlevel.c                  |  58 +-
 arch/arm/boards/tqma6x/board.c                     |   2 +-
 ...alq7_defconfig => datamodul-edm-qmx6_defconfig} |   2 +-
 ...1ads_defconfig => freescale-mx21-ads_defconfig} |   2 +-
 ...3evk_defconfig => freescale-mx23-evk_defconfig} |   0
 ...tack_defconfig => freescale-mx25-3ds_defconfig} |   2 +-
 ...7ads_defconfig => freescale-mx27-ads_defconfig} |   2 +-
 ...8evk_defconfig => freescale-mx28-evk_defconfig} |   0
 ...tack_defconfig => freescale-mx35-3ds_defconfig} |   2 +-
 ..._defconfig => freescale-mx51-babbage_defconfig} |   2 +-
 ...loco_defconfig => freescale-mx53-qsb_defconfig} |   2 +-
 ..._smd_defconfig => freescale-mx53-smd_defconfig} |   0
 arch/arm/configs/imx_v7_defconfig                  |   6 +-
 arch/arm/configs/mioa701_defconfig                 |  49 +-
 arch/arm/configs/pca100_defconfig                  |  70 ---
 arch/arm/configs/phytec-phycard-imx27_defconfig    |  91 +++
 ...config => phytec-phycard-omap3-xload_defconfig} |   0
 ...l1_defconfig => phytec-phycard-omap3_defconfig} |   2 +-
 ...config => phytec-phycard-omap4-xload_defconfig} |   0
 ...l2_defconfig => phytec-phycard-omap4_defconfig} |   2 +-
 ...1_defconfig => phytec-phycore-am335x_defconfig} |   2 +-
 ...38_defconfig => phytec-phycore-imx27_defconfig} |   2 +-
 ...37_defconfig => phytec-phycore-imx31_defconfig} |   2 +-
 ...43_defconfig => phytec-phycore-imx35_defconfig} |   2 +-
 ...fig => phytec-phycore-omap4460-xload_defconfig} |   0
 ...defconfig => phytec-phycore-omap4460_defconfig} |   2 +-
 ...7_defconfig => phytec-phycore-pxa270_defconfig} |   2 +-
 arch/arm/configs/tqma53_defconfig                  |  19 +-
 arch/arm/configs/tx25stk5_defconfig                |  21 +-
 arch/arm/cpu/Makefile                              |   2 +
 arch/arm/cpu/cache.c                               |   2 +-
 arch/arm/cpu/common.c                              |  14 +
 arch/arm/cpu/cpu.c                                 |  14 -
 arch/arm/cpu/lowlevel.S                            |   3 +-
 arch/arm/cpu/uncompress.c                          |   4 -
 arch/arm/dts/Makefile                              |  25 +-
 arch/arm/dts/imx25-karo-tx25.dts                   | 143 +++++
 arch/arm/dts/imx25-pinfunc.h                       | 494 ++++++++++++++++
 arch/arm/dts/imx25.dtsi                            | 558 +++++++++++++++++++
 arch/arm/dts/imx27-phytec-phycard-s-rdk.dts        | 145 +++++
 arch/arm/dts/imx27-phytec-phycard-s-som.dts        | 102 ++++
 arch/arm/dts/imx27-pinfunc.h                       | 526 ++++++++++++++++++
 arch/arm/dts/imx27-pingrp.h                        | 151 +++++
 arch/arm/dts/imx27.dtsi                            | 505 +++++++++++++++++
 arch/arm/dts/imx51-babbage.dts                     | 149 ++++-
 arch/arm/dts/imx51-genesi-efika-sb.dts             | 156 ++++--
 arch/arm/dts/imx51-pingrp.h                        | 249 +++++++++
 arch/arm/dts/imx51.dtsi                            | 465 +++-------------
 arch/arm/dts/imx53-mba53.dts                       | 253 +++++++++
 arch/arm/dts/imx53-qsb-common.dtsi                 | 224 ++++++++
 arch/arm/dts/imx53-qsb.dts                         | 210 +------
 arch/arm/dts/imx53-qsrb.dts                        | 157 ++++++
 arch/arm/dts/imx53-tqma53.dtsi                     | 196 +++++++
 ...box-i-carrier-1.dts => imx6dl-hummingboard.dts} |  24 +-
 arch/arm/dts/imx6dl-nitrogen6x.dts                 |  21 +
 arch/arm/dts/imx6dl-pinfunc.h                      |   2 +
 arch/arm/dts/imx6dl-sabrelite.dts                  |  20 +
 arch/arm/dts/imx6dl.dtsi                           |  36 +-
 ...{imx6q-dmo-realq7.dts => imx6q-dmo-edmqmx6.dts} |  79 ++-
 arch/arm/dts/imx6q-gk802.dts                       |  22 +-
 arch/arm/dts/imx6q-nitrogen6x.dts                  |  25 +
 arch/arm/dts/imx6q-phytec-pfla02.dtsi              | 146 ++++-
 arch/arm/dts/imx6q-pinfunc.h                       |  10 +-
 arch/arm/dts/imx6q-sabrelite.dts                   | 179 +-----
 arch/arm/dts/imx6q-sabresd.dts                     |  20 +-
 arch/arm/dts/imx6q.dtsi                            |  67 ++-
 arch/arm/dts/imx6qdl-dfi-fs700-m60.dtsi            |  75 ++-
 arch/arm/dts/imx6qdl-mba6x.dtsi                    |  16 +-
 arch/arm/dts/imx6qdl-microsom.dtsi                 |  17 +-
 arch/arm/dts/imx6qdl-nitrogen6x.dtsi               | 412 ++++++++++++++
 arch/arm/dts/imx6qdl-pingrp.h                      | 532 ++++++++++++++++++
 arch/arm/dts/imx6qdl-sabrelite.dtsi                | 413 ++++++++++++++
 arch/arm/dts/imx6qdl-sabresd.dtsi                  | 233 +++++++-
 arch/arm/dts/imx6qdl-tqma6x.dtsi                   |  36 +-
 arch/arm/dts/imx6qdl.dtsi                          | 577 ++++++-------------
 arch/arm/dts/tegra20-colibri-iris.dts              |  63 ++-
 arch/arm/dts/tegra20-colibri.dtsi                  | 338 ++++++++++-
 arch/arm/dts/tegra20-paz00.dts                     | 318 ++++++++++-
 arch/arm/dts/tegra20.dtsi                          | 618 ++++++++++++++++++++-
 arch/arm/lib/bootm.c                               | 173 ++++--
 arch/arm/lib/pbl.lds.S                             |  17 +-
 arch/arm/mach-at91/irq_fixup.c                     |   2 +-
 arch/arm/mach-clps711x/devices.c                   |  20 +-
 arch/arm/mach-imx/Kconfig                          |  68 +--
 arch/arm/mach-imx/clk-imx25.c                      |   3 +
 arch/arm/mach-imx/clk-imx27.c                      |  44 +-
 arch/arm/mach-imx/clocksource.c                    |   2 +-
 arch/arm/mach-imx/esdctl-v4.c                      |  24 +-
 arch/arm/mach-imx/esdctl.c                         |   2 +-
 arch/arm/mach-imx/external-nand-boot.c             | 292 +++++-----
 arch/arm/mach-imx/imx1.c                           |   6 +-
 arch/arm/mach-imx/imx6.c                           |  41 +-
 arch/arm/mach-imx/include/mach/esdhc.h             |   2 +
 arch/arm/mach-imx/include/mach/imx-gpio.h          |  48 ++
 arch/arm/mach-imx/include/mach/imx-nand.h          |  10 +-
 arch/arm/mach-imx/include/mach/imx25-regs.h        |   3 +
 arch/arm/mach-imx/include/mach/imx6.h              |  49 +-
 arch/arm/mach-omap/include/mach/omap3-generic.h    |   1 +
 arch/arm/mach-omap/omap_generic.c                  |   2 +-
 arch/arm/mach-pxa/Makefile                         |   2 +
 arch/arm/mach-pxa/common.c                         |  17 +
 arch/arm/mach-pxa/include/mach/hardware.h          |   4 +
 arch/arm/mach-pxa/reset_source.c                   |  41 ++
 arch/arm/mach-pxa/sleep.S                          |  81 +++
 arch/arm/mach-samsung/reset_source.c               |   6 +-
 arch/arm/mach-socfpga/generic.c                    |   2 +-
 arch/arm/pbl/Makefile                              |   2 +-
 arch/blackfin/lib/blackfin_linux.c                 |   6 +-
 arch/mips/Kconfig                                  |  21 +
 arch/mips/Makefile                                 |   6 +
 arch/mips/boards/loongson-ls1b/Makefile            |   2 +
 .../loongson-ls1b/include/board/board_pbl_start.h  |  41 ++
 .../boards/loongson-ls1b/include/board/debug_ll.h  |  34 ++
 arch/mips/boards/loongson-ls1b/loongson_ls1b.dox   |  47 ++
 arch/mips/boards/loongson-ls1b/ram.c               |  12 +
 arch/mips/boards/loongson-ls1b/serial.c            |  22 +
 arch/mips/configs/loongson-ls1b_defconfig          |  42 ++
 arch/mips/include/asm/cpu.h                        |  27 +
 arch/mips/lib/cpu-probe.c                          |  21 +
 arch/mips/lib/csrc-r4k.c                           |   2 +-
 arch/mips/mach-loongson/Kconfig                    |  24 +
 arch/mips/mach-loongson/Makefile                   |   1 +
 arch/mips/mach-loongson/include/mach/debug_ll.h    |  27 +
 arch/mips/mach-loongson/include/mach/loongson1.h   |  32 ++
 arch/mips/mach-loongson/loongson1_reset.c          |  27 +
 arch/mips/mach-loongson/mach-loongson.dox          |   7 +
 arch/mips/mach-mips.dox                            |   4 +
 arch/nios2/lib/bootm.c                             |   6 +-
 arch/ppc/Makefile                                  |   4 +
 arch/ppc/boards/freescale-p2020rdb/Makefile        |   1 -
 arch/ppc/boards/freescale-p2020rdb/barebox.lds.S   | 141 -----
 arch/ppc/boards/geip-da923rc/Makefile              |   1 -
 arch/ppc/boards/geip-da923rc/env/bin/init          |  12 +
 arch/ppc/configs/da923rc_defconfig                 |   6 +
 arch/ppc/cpu-85xx/start.S                          | 431 +++++++++-----
 arch/ppc/cpu-85xx/tlb.c                            |  32 +-
 arch/ppc/include/asm/bitops.h                      |  46 +-
 arch/ppc/include/asm/config.h                      |   2 +-
 arch/ppc/include/asm/mmu.h                         |  40 +-
 arch/ppc/include/asm/processor.h                   |   7 +
 arch/ppc/lib/ppclinux.c                            |   6 +-
 arch/ppc/mach-mpc85xx/Kconfig                      |   5 +
 arch/ppc/mach-mpc85xx/Makefile                     |   1 +
 .../geip-da923rc => mach-mpc85xx}/barebox.lds.S    |  11 +-
 arch/ppc/mach-mpc85xx/cpu.c                        |   4 +-
 arch/ppc/mach-mpc85xx/cpu_init.c                   |   2 +-
 arch/ppc/mach-mpc85xx/fsl_law.c                    |   1 +
 .../ppc/mach-mpc85xx/include/mach/config_mpc85xx.h |   4 +
 arch/ppc/mach-mpc85xx/include/mach/ffs64.h         |  20 +
 arch/sandbox/board/env/bin/init                    |   7 -
 arch/sandbox/board/env/config                      |   8 -
 arch/sandbox/board/env/network/eth0                |  11 +
 arch/sandbox/configs/sandbox_defconfig             |   9 +-
 commands/loadenv.c                                 |   2 +-
 commands/saveenv.c                                 |   2 +-
 common/Kconfig                                     |   2 +-
 common/Makefile                                    |   6 +-
 common/bootm.c                                     | 151 ++++-
 common/console.c                                   |  29 +-
 common/environment.c                               |  18 +-
 common/reset_source.c                              |  18 +-
 common/startup.c                                   |   1 +
 defaultenv-2/base/bin/init                         |   1 +
 drivers/gpio/gpio-clps711x.c                       |  39 +-
 drivers/gpio/gpiolib.c                             |  26 +-
 drivers/mci/imx-esdhc.c                            |   6 +
 drivers/mci/imx.c                                  |   9 +
 drivers/mci/mci-core.c                             | 108 +++-
 drivers/mfd/syscon.c                               |  23 +-
 drivers/misc/Kconfig                               |  14 +-
 drivers/misc/Makefile                              |   1 +
 drivers/misc/sram.c                                |  75 +++
 drivers/mtd/nand/atmel_nand.c                      |   1 +
 drivers/mtd/nor/cfi_flash.c                        |   6 +-
 drivers/net/phy/Kconfig                            |   5 +
 drivers/net/phy/Makefile                           |   1 +
 drivers/net/phy/national.c                         |  95 ++++
 drivers/net/usb/asix.c                             |  36 +-
 drivers/of/barebox.c                               |   2 +-
 drivers/of/base.c                                  |  23 +-
 drivers/pinctrl/Kconfig                            |   1 +
 drivers/pinctrl/imx-iomux-v1.c                     | 198 +++++++
 drivers/serial/serial_clps711x.c                   | 120 ++--
 drivers/serial/serial_imx.c                        |   1 +
 drivers/serial/serial_ns16550.c                    |   3 +
 drivers/watchdog/im28wd.c                          |   8 +-
 drivers/watchdog/imxwd.c                           |   6 +-
 fs/fs.c                                            |   3 +-
 fs/tftp.c                                          |  10 +-
 fs/ubifs/debug.h                                   |  10 +-
 fs/ubifs/ubifs.c                                   |  38 ++
 fs/ubifs/ubifs.h                                   |   6 +-
 images/Makefile                                    |   8 +-
 images/Makefile.imx                                |  76 ++-
 include/boot.h                                     |   5 +
 include/console.h                                  |   2 +
 include/dt-bindings/clock/imx5-clock.h             | 203 +++++++
 include/dt-bindings/clock/tegra20-car.h            | 158 ++++++
 include/dt-bindings/gpio/tegra-gpio.h              |  50 ++
 include/dt-bindings/input/input.h                  | 525 +++++++++++++++++
 include/dt-bindings/interrupt-controller/arm-gic.h |  22 +
 include/dt-bindings/interrupt-controller/irq.h     |  19 +
 include/envfs.h                                    |  18 +-
 include/linux/list.h                               |  11 +
 include/linux/mtd/nand.h                           |   3 +-
 include/linux/phy.h                                |  13 +-
 include/mci.h                                      |  24 +-
 include/mfd/syscon.h                               |   8 +
 include/reset_source.h                             |  10 +-
 net/net.c                                          |   4 +-
 scripts/bin2c.c                                    |   4 +-
 scripts/fix_size.c                                 |  39 +-
 385 files changed, 12594 insertions(+), 3449 deletions(-)
 create mode 100644 arch/arm/boards/boundarydevices-nitrogen6x/Makefile
 create mode 100644 arch/arm/boards/boundarydevices-nitrogen6x/board.c
 rename arch/arm/boards/{dmo-mx6-realq7 => boundarydevices-nitrogen6x}/env/config-board (100%)
 create mode 100644 arch/arm/boards/boundarydevices-nitrogen6x/flash-header-nitrogen6x-1g.imxcfg
 create mode 100644 arch/arm/boards/boundarydevices-nitrogen6x/lowlevel.c
 rename arch/arm/boards/{dmo-mx6-realq7 => datamodul-edm-qmx6}/Makefile (100%)
 rename arch/arm/boards/{dmo-mx6-realq7 => datamodul-edm-qmx6}/board.c (82%)
 rename arch/arm/boards/{dmo-mx6-realq7 => datamodul-edm-qmx6}/env/boot/mmc (100%)
 create mode 100644 arch/arm/boards/datamodul-edm-qmx6/env/config-board
 rename arch/arm/boards/{dmo-mx6-realq7 => datamodul-edm-qmx6}/env/init/automount (100%)
 rename arch/arm/boards/{dmo-mx6-realq7 => datamodul-edm-qmx6}/flash-header.imxcfg (100%)
 rename arch/arm/boards/{dmo-mx6-realq7 => datamodul-edm-qmx6}/lowlevel.c (90%)
 rename arch/arm/boards/dfi-fs700-m60/{flash-header-fs700-m60-6q.imxcfg => flash-header-fs700-m60-6q-micron.imxcfg} (71%)
 create mode 100644 arch/arm/boards/dfi-fs700-m60/flash-header-fs700-m60-6q-nanya.imxcfg
 rename arch/arm/boards/{imx21ads => freescale-mx21-ads}/Makefile (100%)
 rename arch/arm/boards/{imx21ads => freescale-mx21-ads}/env/bin/init (100%)
 rename arch/arm/boards/{imx21ads => freescale-mx21-ads}/imx21ads.c (100%)
 rename arch/arm/boards/{imx21ads => freescale-mx21-ads}/imx21ads.dox (100%)
 rename arch/arm/boards/{imx21ads => freescale-mx21-ads}/lowlevel_init.S (97%)
 rename arch/arm/boards/{freescale-mx25-3-stack => freescale-mx25-3ds}/3stack.c (100%)
 rename arch/arm/boards/{freescale-mx25-3-stack => freescale-mx25-3ds}/Makefile (100%)
 rename arch/arm/boards/{freescale-mx25-3-stack => freescale-mx25-3ds}/env/bin/_update (100%)
 rename arch/arm/boards/{freescale-mx25-3-stack => freescale-mx25-3ds}/env/bin/boot (100%)
 rename arch/arm/boards/{freescale-mx25-3-stack => freescale-mx25-3ds}/env/bin/hush_hack (100%)
 rename arch/arm/boards/{freescale-mx25-3-stack => freescale-mx25-3ds}/env/bin/init (100%)
 rename arch/arm/boards/{freescale-mx25-3-stack => freescale-mx25-3ds}/env/bin/update_kernel (100%)
 rename arch/arm/boards/{freescale-mx25-3-stack => freescale-mx25-3ds}/env/bin/update_root (100%)
 rename arch/arm/boards/{freescale-mx25-3-stack => freescale-mx25-3ds}/env/config (100%)
 rename arch/arm/boards/{freescale-mx25-3-stack => freescale-mx25-3ds}/lowlevel_init.S (98%)
 rename arch/arm/boards/{imx27ads => freescale-mx27-ads}/Makefile (100%)
 rename arch/arm/boards/{imx27ads => freescale-mx27-ads}/env/bin/_update (100%)
 rename arch/arm/boards/{imx27ads => freescale-mx27-ads}/env/bin/boot (100%)
 rename arch/arm/boards/{imx27ads => freescale-mx27-ads}/env/bin/init (100%)
 rename arch/arm/boards/{imx27ads => freescale-mx27-ads}/env/bin/update_kernel (100%)
 rename arch/arm/boards/{imx27ads => freescale-mx27-ads}/env/bin/update_root (100%)
 rename arch/arm/boards/{imx27ads => freescale-mx27-ads}/env/config (100%)
 rename arch/arm/boards/{imx27ads => freescale-mx27-ads}/imx27ads.c (100%)
 rename arch/arm/boards/{imx27ads => freescale-mx27-ads}/imx27ads.dox (100%)
 rename arch/arm/boards/{imx27ads => freescale-mx27-ads}/lowlevel_init.S (100%)
 rename arch/arm/boards/{freescale-mx35-3-stack => freescale-mx35-3ds}/3stack.c (100%)
 rename arch/arm/boards/{freescale-mx35-3-stack => freescale-mx35-3ds}/3stack.dox (100%)
 rename arch/arm/boards/{freescale-mx35-3-stack => freescale-mx35-3ds}/Makefile (100%)
 rename arch/arm/boards/{freescale-mx35-3-stack => freescale-mx35-3ds}/board-mx35_3stack.h (100%)
 rename arch/arm/boards/{freescale-mx35-3-stack => freescale-mx35-3ds}/env/config (100%)
 rename arch/arm/boards/{freescale-mx35-3-stack => freescale-mx35-3ds}/flash_header.c (100%)
 rename arch/arm/boards/{freescale-mx35-3-stack => freescale-mx35-3ds}/lowlevel_init.S (98%)
 rename arch/arm/boards/{freescale-mx51-pdk => freescale-mx51-babbage}/Makefile (100%)
 rename arch/arm/boards/{freescale-mx51-pdk => freescale-mx51-babbage}/board.c (96%)
 rename arch/arm/boards/{freescale-mx51-pdk => freescale-mx51-babbage}/env/config-board (100%)
 rename arch/arm/boards/{freescale-mx51-pdk => freescale-mx51-babbage}/flash-header-imx51-babbage.imxcfg (100%)
 rename arch/arm/boards/{freescale-mx51-pdk => freescale-mx51-babbage}/lowlevel.c (100%)
 rename arch/arm/boards/{freescale-mx51-pdk => freescale-mx51-babbage}/mx51-pdk.dox (100%)
 rename arch/arm/boards/{freescale-mx53-loco => freescale-mx53-qsb}/Makefile (100%)
 rename arch/arm/boards/{freescale-mx53-loco => freescale-mx53-qsb}/board.c (100%)
 rename arch/arm/boards/{freescale-mx53-loco => freescale-mx53-qsb}/env/config-board (100%)
 rename arch/arm/boards/{freescale-mx53-loco => freescale-mx53-qsb}/flash-header-imx53-loco.imxcfg (100%)
 rename arch/arm/boards/{freescale-mx53-loco => freescale-mx53-qsb}/lowlevel.c (59%)
 rename arch/arm/boards/{freescale-mx53-loco => freescale-mx53-qsb}/mx53-pdk.dox (100%)
 create mode 100644 arch/arm/boards/mioa701/env/bin/console_mode
 create mode 100644 arch/arm/boards/mioa701/gpio0_poweroff.c
 delete mode 100644 arch/arm/boards/phycard-i.MX27/Makefile
 delete mode 100644 arch/arm/boards/phycard-i.MX27/env/config
 delete mode 100644 arch/arm/boards/phycard-i.MX27/lowlevel_init.S
 create mode 100644 arch/arm/boards/phytec-phycard-imx27/Makefile
 create mode 100644 arch/arm/boards/phytec-phycard-imx27/lowlevel.c
 rename arch/arm/boards/{phycard-i.MX27 => phytec-phycard-imx27}/pca100.c (50%)
 rename arch/arm/boards/{phycard-i.MX27 => phytec-phycard-imx27}/pca100.dox (100%)
 rename arch/arm/boards/{phycard-a-l1 => phytec-phycard-omap3}/Makefile (100%)
 rename arch/arm/boards/{phycard-a-l1 => phytec-phycard-omap3}/env/config (100%)
 rename arch/arm/boards/{phycard-a-l1 => phytec-phycard-omap3}/lowlevel.c (100%)
 rename arch/arm/boards/{phycard-a-l1 => phytec-phycard-omap3}/pca-a-l1.c (100%)
 rename arch/arm/boards/{phycard-a-l1 => phytec-phycard-omap3}/pca-a-l1.dox (100%)
 rename arch/arm/boards/{phycard-a-l1 => phytec-phycard-omap3}/pca-a-l1.h (100%)
 rename arch/arm/boards/{phycard-a-xl2 => phytec-phycard-omap4}/Makefile (100%)
 rename arch/arm/boards/{phycard-a-xl2 => phytec-phycard-omap4}/env/bin/nand_bootstrap (100%)
 rename arch/arm/boards/{phycard-a-xl2 => phytec-phycard-omap4}/env/config (100%)
 rename arch/arm/boards/{phycard-a-xl2 => phytec-phycard-omap4}/lowlevel.c (100%)
 rename arch/arm/boards/{phycard-a-xl2 => phytec-phycard-omap4}/mux.c (100%)
 rename arch/arm/boards/{phycard-a-xl2 => phytec-phycard-omap4}/pca-a-xl2.c (100%)
 rename arch/arm/boards/{pcm051 => phytec-phycore-am335x}/Makefile (100%)
 rename arch/arm/boards/{pcm051 => phytec-phycore-am335x}/board.c (100%)
 rename arch/arm/boards/{pcm051 => phytec-phycore-am335x}/env/boot/mmc (100%)
 rename arch/arm/boards/{pcm051 => phytec-phycore-am335x}/env/boot/nand (100%)
 rename arch/arm/boards/{pcm051 => phytec-phycore-am335x}/env/boot/spi (100%)
 rename arch/arm/boards/{pcm051 => phytec-phycore-am335x}/env/config-board (100%)
 rename arch/arm/boards/{pcm051 => phytec-phycore-am335x}/lowlevel.c (100%)
 rename arch/arm/boards/{pcm038 => phytec-phycore-imx27}/Makefile (100%)
 rename arch/arm/boards/{pcm037 => phytec-phycore-imx27}/env/boot/nand-ubi (100%)
 rename arch/arm/boards/{pcm037 => phytec-phycore-imx27}/env/config-board (100%)
 rename arch/arm/boards/{pcm037 => phytec-phycore-imx27}/env/init/mtdparts-nand (100%)
 rename arch/arm/boards/{pcm038 => phytec-phycore-imx27}/env/init/mtdparts-nor (100%)
 rename arch/arm/boards/{pcm038 => phytec-phycore-imx27}/lowlevel.c (92%)
 rename arch/arm/boards/{pcm038 => phytec-phycore-imx27}/pcm038.c (100%)
 rename arch/arm/boards/{pcm038 => phytec-phycore-imx27}/pcm038.dox (100%)
 rename arch/arm/boards/{pcm038 => phytec-phycore-imx27}/pcm970.c (100%)
 rename arch/arm/boards/{pcm038 => phytec-phycore-imx27}/pll.h (100%)
 rename arch/arm/boards/{pcm037 => phytec-phycore-imx31}/Makefile (100%)
 rename arch/arm/boards/{pcm038 => phytec-phycore-imx31}/env/boot/nand-ubi (100%)
 rename arch/arm/boards/{pcm038 => phytec-phycore-imx31}/env/config-board (100%)
 rename arch/arm/boards/{pcm038 => phytec-phycore-imx31}/env/init/mtdparts-nand (100%)
 rename arch/arm/boards/{pcm037 => phytec-phycore-imx31}/env/init/mtdparts-nor (100%)
 rename arch/arm/boards/{pcm037 => phytec-phycore-imx31}/lowlevel.c (93%)
 rename arch/arm/boards/{pcm037 => phytec-phycore-imx31}/pcm037.c (100%)
 rename arch/arm/boards/{pcm037 => phytec-phycore-imx31}/pcm037.dox (100%)
 rename arch/arm/boards/{pcm043 => phytec-phycore-imx35}/Makefile (100%)
 rename arch/arm/boards/{pcm043 => phytec-phycore-imx35}/env/boot/nand-ubi (100%)
 rename arch/arm/boards/{pcm043 => phytec-phycore-imx35}/env/config-board (100%)
 rename arch/arm/boards/{pcm043 => phytec-phycore-imx35}/env/init/mtdparts-nand (100%)
 rename arch/arm/boards/{pcm043 => phytec-phycore-imx35}/env/init/mtdparts-nor (100%)
 rename arch/arm/boards/{pcm043 => phytec-phycore-imx35}/lowlevel.c (92%)
 rename arch/arm/boards/{pcm043 => phytec-phycore-imx35}/pcm043.c (100%)
 rename arch/arm/boards/{pcm043 => phytec-phycore-imx35}/pcm043.dox (100%)
 rename arch/arm/boards/{pcm049 => phytec-phycore-omap4460}/Makefile (100%)
 rename arch/arm/boards/{pcm049 => phytec-phycore-omap4460}/board.c (100%)
 rename arch/arm/boards/{pcm049 => phytec-phycore-omap4460}/env/bin/init_board (100%)
 rename arch/arm/boards/{pcm049 => phytec-phycore-omap4460}/env/bin/nand_bootstrap (100%)
 rename arch/arm/boards/{pcm049 => phytec-phycore-omap4460}/env/config (100%)
 rename arch/arm/boards/{pcm049 => phytec-phycore-omap4460}/lowlevel.c (100%)
 rename arch/arm/boards/{pcm049 => phytec-phycore-omap4460}/mux.c (100%)
 rename arch/arm/boards/{pcm027 => phytec-phycore-pxa270}/Makefile (100%)
 rename arch/arm/boards/{pcm027 => phytec-phycore-pxa270}/board.c (100%)
 rename arch/arm/boards/{pcm027 => phytec-phycore-pxa270}/config.h (100%)
 rename arch/arm/boards/{pcm027 => phytec-phycore-pxa270}/env/config (100%)
 rename arch/arm/boards/{pcm027 => phytec-phycore-pxa270}/lowlevel_init.S (100%)
 rename arch/arm/boards/{phytec-pfla02 => phytec-phyflex-imx6}/Makefile (100%)
 rename arch/arm/boards/{phytec-pfla02 => phytec-phyflex-imx6}/board.c (100%)
 rename arch/arm/boards/{phytec-pfla02 => phytec-phyflex-imx6}/flash-header-phytec-pfla02-1gib.imxcfg (100%)
 rename arch/arm/boards/{phytec-pfla02 => phytec-phyflex-imx6}/flash-header-phytec-pfla02-2gib.imxcfg (100%)
 rename arch/arm/boards/{phytec-pfla02 => phytec-phyflex-imx6}/flash-header-phytec-pfla02.h (100%)
 rename arch/arm/boards/{phytec-pfla02 => phytec-phyflex-imx6}/lowlevel.c (100%)
 delete mode 100644 arch/arm/boards/solidrun-carrier-1/Makefile
 delete mode 100644 arch/arm/boards/solidrun-carrier-1/lowlevel.c
 create mode 100644 arch/arm/boards/solidrun-hummingboard/Makefile
 rename arch/arm/boards/{solidrun-carrier-1 => solidrun-hummingboard}/board.c (85%)
 rename arch/arm/boards/{solidrun-carrier-1/flash-header-solidrun-carrier-1.imxcfg => solidrun-hummingboard/flash-header-solidrun-hummingboard.imxcfg} (100%)
 create mode 100644 arch/arm/boards/solidrun-hummingboard/lowlevel.c
 create mode 100644 arch/arm/boards/tqma53/flash-header-tq-tqma53-1gib.imxcfg
 create mode 100644 arch/arm/boards/tqma53/flash-header-tq-tqma53-512mib.imxcfg
 create mode 100644 arch/arm/boards/tqma53/flash-header-tq-tqma53.h
 delete mode 100644 arch/arm/boards/tqma53/flash_header.c
 rename arch/arm/configs/{dmo-realq7_defconfig => datamodul-edm-qmx6_defconfig} (96%)
 rename arch/arm/configs/{mx21ads_defconfig => freescale-mx21-ads_defconfig} (92%)
 rename arch/arm/configs/{imx23evk_defconfig => freescale-mx23-evk_defconfig} (100%)
 rename arch/arm/configs/{freescale_mx25_3stack_defconfig => freescale-mx25-3ds_defconfig} (98%)
 rename arch/arm/configs/{mx27ads_defconfig => freescale-mx27-ads_defconfig} (91%)
 rename arch/arm/configs/{imx28evk_defconfig => freescale-mx28-evk_defconfig} (100%)
 rename arch/arm/configs/{freescale_mx35_3stack_defconfig => freescale-mx35-3ds_defconfig} (99%)
 rename arch/arm/configs/{freescale_mx51_babbage_defconfig => freescale-mx51-babbage_defconfig} (99%)
 rename arch/arm/configs/{freescale_mx53_loco_defconfig => freescale-mx53-qsb_defconfig} (99%)
 rename arch/arm/configs/{freescale_mx53_smd_defconfig => freescale-mx53-smd_defconfig} (100%)
 delete mode 100644 arch/arm/configs/pca100_defconfig
 create mode 100644 arch/arm/configs/phytec-phycard-imx27_defconfig
 rename arch/arm/configs/{phycard_a_l1_xload_defconfig => phytec-phycard-omap3-xload_defconfig} (100%)
 rename arch/arm/configs/{phycard_a_l1_defconfig => phytec-phycard-omap3_defconfig} (98%)
 rename arch/arm/configs/{phycard_a_xl2_xload_defconfig => phytec-phycard-omap4-xload_defconfig} (100%)
 rename arch/arm/configs/{phycard_a_xl2_defconfig => phytec-phycard-omap4_defconfig} (93%)
 rename arch/arm/configs/{pcm051_defconfig => phytec-phycore-am335x_defconfig} (96%)
 rename arch/arm/configs/{pcm038_defconfig => phytec-phycore-imx27_defconfig} (95%)
 rename arch/arm/configs/{pcm037_defconfig => phytec-phycore-imx31_defconfig} (96%)
 rename arch/arm/configs/{pcm043_defconfig => phytec-phycore-imx35_defconfig} (96%)
 rename arch/arm/configs/{pcm049_xload_defconfig => phytec-phycore-omap4460-xload_defconfig} (100%)
 rename arch/arm/configs/{pcm049_defconfig => phytec-phycore-omap4460_defconfig} (95%)
 rename arch/arm/configs/{pcm027_defconfig => phytec-phycore-pxa270_defconfig} (94%)
 create mode 100644 arch/arm/dts/imx25-karo-tx25.dts
 create mode 100644 arch/arm/dts/imx25-pinfunc.h
 create mode 100644 arch/arm/dts/imx25.dtsi
 create mode 100644 arch/arm/dts/imx27-phytec-phycard-s-rdk.dts
 create mode 100644 arch/arm/dts/imx27-phytec-phycard-s-som.dts
 create mode 100644 arch/arm/dts/imx27-pinfunc.h
 create mode 100644 arch/arm/dts/imx27-pingrp.h
 create mode 100644 arch/arm/dts/imx27.dtsi
 create mode 100644 arch/arm/dts/imx51-pingrp.h
 create mode 100644 arch/arm/dts/imx53-mba53.dts
 create mode 100644 arch/arm/dts/imx53-qsb-common.dtsi
 create mode 100644 arch/arm/dts/imx53-qsrb.dts
 create mode 100644 arch/arm/dts/imx53-tqma53.dtsi
 rename arch/arm/dts/{imx6dl-cubox-i-carrier-1.dts => imx6dl-hummingboard.dts} (77%)
 create mode 100644 arch/arm/dts/imx6dl-nitrogen6x.dts
 create mode 100644 arch/arm/dts/imx6dl-sabrelite.dts
 rename arch/arm/dts/{imx6q-dmo-realq7.dts => imx6q-dmo-edmqmx6.dts} (85%)
 create mode 100644 arch/arm/dts/imx6q-nitrogen6x.dts
 create mode 100644 arch/arm/dts/imx6qdl-nitrogen6x.dtsi
 create mode 100644 arch/arm/dts/imx6qdl-pingrp.h
 create mode 100644 arch/arm/dts/imx6qdl-sabrelite.dtsi
 create mode 100644 arch/arm/mach-imx/include/mach/imx-gpio.h
 create mode 100644 arch/arm/mach-pxa/reset_source.c
 create mode 100644 arch/arm/mach-pxa/sleep.S
 create mode 100644 arch/mips/boards/loongson-ls1b/Makefile
 create mode 100644 arch/mips/boards/loongson-ls1b/include/board/board_pbl_start.h
 create mode 100644 arch/mips/boards/loongson-ls1b/include/board/debug_ll.h
 create mode 100644 arch/mips/boards/loongson-ls1b/loongson_ls1b.dox
 create mode 100644 arch/mips/boards/loongson-ls1b/ram.c
 create mode 100644 arch/mips/boards/loongson-ls1b/serial.c
 create mode 100644 arch/mips/configs/loongson-ls1b_defconfig
 create mode 100644 arch/mips/mach-loongson/Kconfig
 create mode 100644 arch/mips/mach-loongson/Makefile
 create mode 100644 arch/mips/mach-loongson/include/mach/debug_ll.h
 create mode 100644 arch/mips/mach-loongson/include/mach/loongson1.h
 create mode 100644 arch/mips/mach-loongson/loongson1_reset.c
 create mode 100644 arch/mips/mach-loongson/mach-loongson.dox
 delete mode 100644 arch/ppc/boards/freescale-p2020rdb/barebox.lds.S
 rename arch/ppc/{boards/geip-da923rc => mach-mpc85xx}/barebox.lds.S (94%)
 create mode 100644 arch/ppc/mach-mpc85xx/include/mach/ffs64.h
 delete mode 100644 arch/sandbox/board/env/bin/init
 delete mode 100644 arch/sandbox/board/env/config
 create mode 100644 arch/sandbox/board/env/network/eth0
 create mode 100644 drivers/misc/sram.c
 create mode 100644 drivers/net/phy/national.c
 create mode 100644 include/dt-bindings/clock/imx5-clock.h
 create mode 100644 include/dt-bindings/clock/tegra20-car.h
 create mode 100644 include/dt-bindings/gpio/tegra-gpio.h
 create mode 100644 include/dt-bindings/input/input.h
 create mode 100644 include/dt-bindings/interrupt-controller/arm-gic.h
 create mode 100644 include/dt-bindings/interrupt-controller/irq.h
-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From eric at eukrea.com  Fri Mar  7 05:39:57 2014
From: eric at eukrea.com (=?UTF-8?q?Eric=20B=C3=A9nard?=)
Date: Fri,  7 Mar 2014 11:39:57 +0100
Subject: [PATCH v2 1/7] sata-imx: i.MX53,
 use the internal 120MHz clock by default
In-Reply-To: <20140210091152.GM17250@pengutronix.de>
References: <20140210091152.GM17250@pengutronix.de>
Message-ID: <1394188803-13456-1-git-send-email-eric@eukrea.com>

this allows SATA to work on i.MX53 QSB-R :
barebox at Freescale i.MX53 Quick Start-R Board:/ ata0.probe=1
imx-sata 10000000.sata: port 0: SATA link ok
imx-sata 10000000.sata: port 0: Spinning up device...
imx-sata 10000000.sata: port 0: ok.
ata0: registered /dev/ata0

before this fix the log was :
barebox at Freescale i.MX53 Quick Start-R Board:/ ata0.probe=1
imx-sata 10000000.sata: port 0: SATA link timeout
set parameter: Connection timed out

Signed-off-by: Eric B?nard <eric at eukrea.com>
---
 drivers/ata/sata-imx.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/ata/sata-imx.c b/drivers/ata/sata-imx.c
index b7bd110..450cf4f 100644
--- a/drivers/ata/sata-imx.c
+++ b/drivers/ata/sata-imx.c
@@ -59,7 +59,7 @@ static int imx53_sata_init(struct imx_ahci *imx_ahci)
 	 */
 	val = readl(base + 0x180c);
 	val &= (0x3 << 1);
-	val |= (0x1 << 1);
+	val |= (0x2 << 1);
 	writel(val, base + 0x180c);
 
 	return 0;
-- 
1.8.3.1



From eric at eukrea.com  Fri Mar  7 05:39:58 2014
From: eric at eukrea.com (=?UTF-8?q?Eric=20B=C3=A9nard?=)
Date: Fri,  7 Mar 2014 11:39:58 +0100
Subject: [PATCH v2 2/7] ARM: i.MX53: Add sata to devicetree
In-Reply-To: <1394188803-13456-1-git-send-email-eric@eukrea.com>
References: <20140210091152.GM17250@pengutronix.de>
 <1394188803-13456-1-git-send-email-eric@eukrea.com>
Message-ID: <1394188803-13456-2-git-send-email-eric@eukrea.com>

Signed-off-by: Eric B?nard <eric at eukrea.com>
---
v2: update the SATA entry to be compatible with the kernel, but do
  not use the Linux-next dts. This means use plain numbers, but the
  correct clock names.
  
 arch/arm/dts/imx53.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/arm/dts/imx53.dtsi b/arch/arm/dts/imx53.dtsi
index 678547c..a28c4c7 100644
--- a/arch/arm/dts/imx53.dtsi
+++ b/arch/arm/dts/imx53.dtsi
@@ -75,6 +75,15 @@
 		interrupt-parent = <&tzic>;
 		ranges;
 
+		sata: sata at 10000000 {
+			compatible = "fsl,imx53-ahci";
+			reg = <0x10000000 0x1000>;
+			interrupts = <28>;
+			clocks = <&clks 173>, <&clks 188>, <&clks 5>;
+			clock-names = "sata_gate", "sata_ref", "ahb";
+			status = "disabled";
+		};
+
 		ipu: ipu at 18000000 {
 			#crtc-cells = <1>;
 			compatible = "fsl,imx53-ipu";
-- 
1.8.3.1



From eric at eukrea.com  Fri Mar  7 05:40:00 2014
From: eric at eukrea.com (=?UTF-8?q?Eric=20B=C3=A9nard?=)
Date: Fri,  7 Mar 2014 11:40:00 +0100
Subject: [PATCH v2 4/7] ARM: mx53-qsrb: enable USB host
In-Reply-To: <1394188803-13456-1-git-send-email-eric@eukrea.com>
References: <20140210091152.GM17250@pengutronix.de>
 <1394188803-13456-1-git-send-email-eric@eukrea.com>
Message-ID: <1394188803-13456-4-git-send-email-eric@eukrea.com>

- declare the rigth mux for the GPIO used to enable the USB's 5V
- enable USB host controller

tested on i.MX53 START-R :
barebox at Freescale i.MX53 Quick Start-R Board:/ usb -f
USB: scanning bus for devices...
Bus 001 Device 001: ID 0000:0000 EHCI Host Controller
Using index 0 for the new disk
Bus 002 Device 003: ID 0951:1654 DT R500
Bus 002 Device 002: ID 0000:0000 EHCI Host Controller
3 USB Device(s) found

Signed-off-by: Eric B?nard <eric at eukrea.com>
---
 arch/arm/dts/imx53-qsb-common.dtsi | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/arch/arm/dts/imx53-qsb-common.dtsi b/arch/arm/dts/imx53-qsb-common.dtsi
index f2f912b..4ae1f49 100644
--- a/arch/arm/dts/imx53-qsb-common.dtsi
+++ b/arch/arm/dts/imx53-qsb-common.dtsi
@@ -158,6 +158,7 @@
 				MX53_PAD_EIM_DA13__GPIO3_13       0x80000000
 				MX53_PAD_PATA_DA_0__GPIO7_6       0x80000000
 				MX53_PAD_GPIO_16__GPIO7_11        0x80000000
+				MX53_PAD_PATA_DA_2__GPIO7_8       0x80000000
 			>;
 		};
 
@@ -216,9 +217,12 @@
 };
 
 &usbh1 {
-       status = "okay";
+	phy_type = "utmi";
+	dr_mode = "host";
+	status = "okay";
 };
 
 &usbotg {
        status = "okay";
 };
+
-- 
1.8.3.1



From eric at eukrea.com  Fri Mar  7 05:39:59 2014
From: eric at eukrea.com (=?UTF-8?q?Eric=20B=C3=A9nard?=)
Date: Fri,  7 Mar 2014 11:39:59 +0100
Subject: [PATCH v2 3/7] ARM: mx53-qsrb: fix USB
In-Reply-To: <1394188803-13456-1-git-send-email-eric@eukrea.com>
References: <20140210091152.GM17250@pengutronix.de>
 <1394188803-13456-1-git-send-email-eric@eukrea.com>
Message-ID: <1394188803-13456-3-git-send-email-eric@eukrea.com>

- configure the MC34708 properly so that USB can work
(the sequence is taken from u-boot)
- add the required defines to the mc13xxx include file

Signed-off-by: Eric B?nard <eric at eukrea.com>
---
 arch/arm/boards/freescale-mx53-qsb/board.c | 45 ++++++++++++++++++++++++++++++
 include/mfd/mc13xxx.h                      | 11 ++++++++
 2 files changed, 56 insertions(+)

diff --git a/arch/arm/boards/freescale-mx53-qsb/board.c b/arch/arm/boards/freescale-mx53-qsb/board.c
index 69036da..74826e4 100644
--- a/arch/arm/boards/freescale-mx53-qsb/board.c
+++ b/arch/arm/boards/freescale-mx53-qsb/board.c
@@ -93,11 +93,56 @@ static int loco_late_init(void)
 
 	mc34708 = mc13xxx_get();
 	if (mc34708) {
+		unsigned int val;
+		int ret;
 		/* get the board revision from fuse */
 		rev = readl(MX53_IIM_BASE_ADDR + 0x878);
 		set_board_rev(rev);
 		printf("MCIMX53-START-R board 1.0 rev %c\n", (rev == 1) ? 'A' : 'B' );
 		armlinux_set_revision(loco_system_rev);
+		/* Set VDDGP to 1.25V for 1GHz on SW1 */
+		mc13xxx_reg_read(mc34708, MC13892_REG_SW_0, &val);
+		val = (val & ~SWx_VOLT_MASK_MC34708) | SWx_1_250V_MC34708;
+		ret = mc13xxx_reg_write(mc34708, MC13892_REG_SW_0, val);
+		if (ret) {
+			printf("Writing to REG_SW_0 failed: %d\n", ret);
+			return ret;
+		}
+
+		/* Set VCC as 1.30V on SW2 */
+		mc13xxx_reg_read(mc34708, MC13892_REG_SW_1, &val);
+		val = (val & ~SWx_VOLT_MASK_MC34708) | SWx_1_300V_MC34708;
+		ret = mc13xxx_reg_write(mc34708, MC13892_REG_SW_1, val);
+		if (ret) {
+			printf("Writing to REG_SW_1 failed: %d\n", ret);
+			return ret;
+		}
+
+		/* Set global reset timer to 4s */
+		mc13xxx_reg_read(mc34708, MC13892_REG_POWER_CTL2, &val);
+		val = (val & ~TIMER_MASK_MC34708) | TIMER_4S_MC34708;
+		ret = mc13xxx_reg_write(mc34708, MC13892_REG_POWER_CTL2, val);
+		if (ret) {
+			printf("Writing to REG_POWER_CTL2 failed: %d\n", ret);
+			return ret;
+		}
+
+		/* Set VUSBSEL and VUSBEN for USB PHY supply*/
+		mc13xxx_reg_read(mc34708, MC13892_REG_MODE_0, &val);
+		val |= (VUSBSEL_MC34708 | VUSBEN_MC34708);
+		ret = mc13xxx_reg_write(mc34708, MC13892_REG_MODE_0, val);
+		if (ret) {
+			printf("Writing to REG_MODE_0 failed: %d\n", ret);
+			return ret;
+		}
+
+		/* Set SWBST to 5V in auto mode */
+		val = SWBST_AUTO;
+		ret = mc13xxx_reg_write(mc34708, SWBST_CTRL, val);
+		if (ret) {
+			printf("Writing to SWBST_CTRL failed: %d\n", ret);
+			return ret;
+		}
 	} else {
 		/* so we have a DA9053 based board */
 		printf("MCIMX53-START board 1.0\n");
diff --git a/include/mfd/mc13xxx.h b/include/mfd/mc13xxx.h
index cba8589..1946b1a 100644
--- a/include/mfd/mc13xxx.h
+++ b/include/mfd/mc13xxx.h
@@ -152,6 +152,17 @@
 #define MC13783_SW1B_SOFTSTART		(1 << 17)
 #define MC13783_SW_PLL_FACTOR(x)	(((x) - 28) << 19)
 
+/* MC34708 Definitions */
+#define SWx_VOLT_MASK_MC34708	0x3F
+#define SWx_1_250V_MC34708	0x30
+#define SWx_1_300V_MC34708	0x34
+#define TIMER_MASK_MC34708	0x300
+#define TIMER_4S_MC34708	0x100
+#define VUSBSEL_MC34708		(1 << 2)
+#define VUSBEN_MC34708		(1 << 3)
+#define SWBST_CTRL		31
+#define SWBST_AUTO		0x8
+
 struct mc13xxx;
 
 #ifdef CONFIG_MFD_MC13XXX
-- 
1.8.3.1



From eric at eukrea.com  Fri Mar  7 05:40:01 2014
From: eric at eukrea.com (=?UTF-8?q?Eric=20B=C3=A9nard?=)
Date: Fri,  7 Mar 2014 11:40:01 +0100
Subject: [PATCH v2 5/7] ARM: mx53-qsrb: enable USB OTG in host mode
In-Reply-To: <1394188803-13456-1-git-send-email-eric@eukrea.com>
References: <20140210091152.GM17250@pengutronix.de>
 <1394188803-13456-1-git-send-email-eric@eukrea.com>
Message-ID: <1394188803-13456-5-git-send-email-eric@eukrea.com>

tested on i.MX53 START-R :
barebox at Freescale i.MX53 Quick Start-R Board:/ usb -f
USB: scanning bus for devices...
Using index 0 for the new disk
Bus 001 Device 002: ID 0951:1654 DT R500
Bus 001 Device 001: ID 0000:0000 EHCI Host Controller
Bus 002 Device 003: ID 0000:0000 EHCI Host Controller
3 USB Device(s) found

Signed-off-by: Eric B?nard <eric at eukrea.com>
---
v2 : Remove the dr_mode = "host" line

 arch/arm/dts/imx53-qsb-common.dtsi | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/dts/imx53-qsb-common.dtsi b/arch/arm/dts/imx53-qsb-common.dtsi
index 4ae1f49..3a9d55e 100644
--- a/arch/arm/dts/imx53-qsb-common.dtsi
+++ b/arch/arm/dts/imx53-qsb-common.dtsi
@@ -223,6 +223,7 @@
 };
 
 &usbotg {
-       status = "okay";
+	phy_type = "utmi";
+	status = "okay";
 };
 
-- 
1.8.3.1



From eric at eukrea.com  Fri Mar  7 05:40:02 2014
From: eric at eukrea.com (=?UTF-8?q?Eric=20B=C3=A9nard?=)
Date: Fri,  7 Mar 2014 11:40:02 +0100
Subject: [PATCH v2 6/7] ARM: mx53-qsrb: enable sata
In-Reply-To: <1394188803-13456-1-git-send-email-eric@eukrea.com>
References: <20140210091152.GM17250@pengutronix.de>
 <1394188803-13456-1-git-send-email-eric@eukrea.com>
Message-ID: <1394188803-13456-6-git-send-email-eric@eukrea.com>

tested on i.MX53 START-R :
barebox at Freescale i.MX53 Quick Start-R Board:/ ata0.probe=1
imx-sata 10000000.sata: port 0: SATA link ok
imx-sata 10000000.sata: port 0: Spinning up device...
imx-sata 10000000.sata: port 0: ok.
ata0: registered /dev/ata0

Signed-off-by: Eric B?nard <eric at eukrea.com>
---
 arch/arm/dts/imx53-qsb-common.dtsi | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/dts/imx53-qsb-common.dtsi b/arch/arm/dts/imx53-qsb-common.dtsi
index 3a9d55e..571da92 100644
--- a/arch/arm/dts/imx53-qsb-common.dtsi
+++ b/arch/arm/dts/imx53-qsb-common.dtsi
@@ -227,3 +227,6 @@
 	status = "okay";
 };
 
+&sata {
+	status = "okay";
+};
-- 
1.8.3.1



From eric at eukrea.com  Fri Mar  7 05:40:03 2014
From: eric at eukrea.com (=?UTF-8?q?Eric=20B=C3=A9nard?=)
Date: Fri,  7 Mar 2014 11:40:03 +0100
Subject: [PATCH v2 7/7] ARM: mx53-qsb: update defconfig
In-Reply-To: <1394188803-13456-1-git-send-email-eric@eukrea.com>
References: <20140210091152.GM17250@pengutronix.de>
 <1394188803-13456-1-git-send-email-eric@eukrea.com>
Message-ID: <1394188803-13456-7-git-send-email-eric@eukrea.com>

- enable more commands :
    (menu, password, loadb, let, mm, sha*, bootz, of*, memtest)
- enable led and led triggers
- enable sata support
- enable USB chipidea support
- enable USB network drivers
- enable NFS and DNS support
- enable EXT4 support

Signed-off-by: Eric B?nard <eric at eukrea.com>
---
 arch/arm/configs/freescale-mx53-qsb_defconfig | 31 +++++++++++++++++++++++++--
 1 file changed, 29 insertions(+), 2 deletions(-)

diff --git a/arch/arm/configs/freescale-mx53-qsb_defconfig b/arch/arm/configs/freescale-mx53-qsb_defconfig
index afe8b72..8365234 100644
--- a/arch/arm/configs/freescale-mx53-qsb_defconfig
+++ b/arch/arm/configs/freescale-mx53-qsb_defconfig
@@ -16,6 +16,7 @@ CONFIG_HUSH_FANCY_PROMPT=y
 CONFIG_CMDLINE_EDITING=y
 CONFIG_AUTO_COMPLETE=y
 CONFIG_MENU=y
+CONFIG_BLSPEC=y
 CONFIG_CONSOLE_ACTIVATE_NONE=y
 CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y
 CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/freescale-mx53-qsb/env/"
@@ -25,31 +26,44 @@ CONFIG_CMD_EDIT=y
 CONFIG_CMD_SLEEP=y
 CONFIG_CMD_MSLEEP=y
 CONFIG_CMD_SAVEENV=y
+CONFIG_CMD_LOADENV=y
 CONFIG_CMD_EXPORT=y
 CONFIG_CMD_PRINTENV=y
 CONFIG_CMD_READLINE=y
+CONFIG_CMD_LET=y
 CONFIG_CMD_MENU=y
 CONFIG_CMD_MENU_MANAGEMENT=y
+CONFIG_CMD_PASSWD=y
+CONFIG_PASSWD_MODE_STAR=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_LN=y
 CONFIG_CMD_TFTP=y
 CONFIG_CMD_FILETYPE=y
 CONFIG_CMD_ECHO_E=y
+CONFIG_CMD_LOADB=y
 CONFIG_CMD_MEMINFO=y
 CONFIG_CMD_IOMEM=y
+CONFIG_CMD_MM=y
 CONFIG_CMD_CRC=y
 CONFIG_CMD_CRC_CMP=y
 CONFIG_CMD_MD5SUM=y
+CONFIG_CMD_SHA1SUM=y
+CONFIG_CMD_SHA256SUM=y
+CONFIG_CMD_SHA224SUM=y
 CONFIG_CMD_BOOTM_SHOW_TYPE=y
 CONFIG_CMD_BOOTM_VERBOSE=y
 CONFIG_CMD_BOOTM_INITRD=y
 CONFIG_CMD_BOOTM_OFTREE=y
 CONFIG_CMD_BOOTM_OFTREE_UIMAGE=y
+CONFIG_CMD_BOOTM_AIMAGE=y
 CONFIG_CMD_UIMAGE=y
-# CONFIG_CMD_BOOTU is not set
+CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_RESET=y
 CONFIG_CMD_GO=y
 CONFIG_CMD_OFTREE=y
+CONFIG_CMD_OF_PROPERTY=y
+CONFIG_CMD_OF_NODE=y
+CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_BAREBOX_UPDATE=y
 CONFIG_CMD_TIMEOUT=y
 CONFIG_CMD_PARTITION=y
@@ -64,23 +78,36 @@ CONFIG_CMD_DETECT=y
 CONFIG_CMD_WD=y
 CONFIG_NET=y
 CONFIG_NET_DHCP=y
+CONFIG_NET_NFS=y
 CONFIG_NET_PING=y
 CONFIG_NET_NETCONSOLE=y
+CONFIG_NET_RESOLV=y
 CONFIG_OFDEVICE=y
 CONFIG_SMSC_PHY=y
 CONFIG_DRIVER_NET_FEC_IMX=y
+CONFIG_NET_USB=y
+CONFIG_NET_USB_ASIX=y
+CONFIG_NET_USB_SMSC95XX=y
 # CONFIG_SPI is not set
 CONFIG_I2C=y
 CONFIG_I2C_IMX=y
-CONFIG_DISK_ATA=y
+CONFIG_DISK_AHCI=y
+CONFIG_DISK_AHCI_IMX=y
 CONFIG_USB=y
+CONFIG_USB_IMX_CHIPIDEA=y
 CONFIG_USB_EHCI=y
+CONFIG_USB_ULPI=y
 CONFIG_USB_STORAGE=y
 CONFIG_MCI=y
 CONFIG_MCI_IMX_ESDHC=y
 CONFIG_MFD_MC13XXX=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_LED_GPIO_OF=y
+CONFIG_LED_TRIGGERS=y
 CONFIG_WATCHDOG=y
 CONFIG_WATCHDOG_IMX=y
+CONFIG_FS_EXT4=y
 CONFIG_FS_TFTP=y
 CONFIG_FS_NFS=y
 CONFIG_FS_FAT=y
-- 
1.8.3.1



From d.lavnikevich at sam-solutions.net  Fri Mar  7 06:14:45 2014
From: d.lavnikevich at sam-solutions.net (Dmitry Lavnikevich)
Date: Fri, 7 Mar 2014 14:14:45 +0300
Subject: [PATCH 1/5] mtd: Update internal API to support 64-bit device size
Message-ID: <5319AA25.5050803@sam-solutions.net>

MTD internal API presently uses 32-bit values to represent device
size. This patch updates them to 64-bits but leaves the external API
unchanged.

In general, changing from 32-bit to 64-bit values cause little
or no changes to the majority of the code with the following
exceptions:
   - printk message formats;
   - division and modulus of 64-bit values (mtd_div_by_wb,
     mtd_div_by_eb may be used in some of such cases).

Was tested on phyFLEX i.MX6.

Signed-off-by: Dmitry Lavnikevich <d.lavnikevich at sam-solutions.com>
Signed-off-by: Grigory Milev <g.milev at sam-solutions.com>
---
  commands/nandtest.c                 |  2 +-
  commands/partition.c                | 11 ++++++-----
  drivers/mtd/core.c                  |  2 +-
  drivers/mtd/devices/m25p80.c        |  5 +++--
  drivers/mtd/devices/mtd_dataflash.c |  2 +-
  drivers/mtd/mtdoob.c                |  2 +-
  drivers/mtd/mtdraw.c                |  2 +-
  include/linux/mtd/mtd-abi.h         | 12 +++++++++++-
  include/linux/mtd/mtd.h             |  9 ++++++++-
  lib/libmtd.c                        | 10 +++++-----
  10 files changed, 38 insertions(+), 19 deletions(-)

diff --git a/commands/nandtest.c b/commands/nandtest.c
index 0da5444..c64f244 100644
--- a/commands/nandtest.c
+++ b/commands/nandtest.c
@@ -277,7 +277,7 @@ static int do_nandtest(int argc, char *argv[])
  	}
  	if (length + flash_offset > meminfo.size) {
  		printf("Length 0x%08llx + offset 0x%08llx exceeds "
-				"device size 0x%08x\n", length,
+				"device size 0x%08llx\n", length,
  				flash_offset, meminfo.size);
  		goto err;
  	}
diff --git a/commands/partition.c b/commands/partition.c
index 6d37471..f825722 100644
--- a/commands/partition.c
+++ b/commands/partition.c
@@ -42,10 +42,11 @@
  #define PART_ADD_DEVNAME (1 << 0)
   static int mtd_part_do_parse_one(char *devname, const char *partstr,
-				 char **endp, unsigned long *offset,
-				 off_t devsize, size_t *retsize, unsigned int pflags)
+				 char **endp, loff_t *offset,
+				 loff_t devsize, size_t *retsize,
+				 unsigned int pflags)
  {
-	ulong size;
+	loff_t size;
  	char *end;
  	char buf[PATH_MAX] = {};
  	unsigned long flags = 0;
@@ -114,8 +115,8 @@ static int do_addpart(int argc, char *argv[])
  {
  	char *devname;
  	char *endp;
-	unsigned long offset = 0;
-	off_t devsize;
+	loff_t offset = 0;
+	loff_t devsize;
  	struct stat s;
  	int opt;
  	unsigned int flags = PART_ADD_DEVNAME;
diff --git a/drivers/mtd/core.c b/drivers/mtd/core.c
index 6db1c6d..7efb03c 100644
--- a/drivers/mtd/core.c
+++ b/drivers/mtd/core.c
@@ -397,7 +397,7 @@ int add_mtd_device(struct mtd_info *mtd, char 
*devname, int device_id)
  	mtd->cdev.mtd = mtd;
   	if (IS_ENABLED(CONFIG_PARAMETER)) {
-		dev_add_param_int_ro(&mtd->class_dev, "size", mtd->size, "%u");
+		dev_add_param_int_ro(&mtd->class_dev, "size", mtd->size, "%llu");
  		dev_add_param_int_ro(&mtd->class_dev, "erasesize", mtd->erasesize, 
"%u");
  		dev_add_param_int_ro(&mtd->class_dev, "writesize", mtd->oobsize, "%u");
  		dev_add_param_int_ro(&mtd->class_dev, "oobsize", mtd->oobsize, "%u");
diff --git a/drivers/mtd/devices/m25p80.c b/drivers/mtd/devices/m25p80.c
index 9594011..757a717 100644
--- a/drivers/mtd/devices/m25p80.c
+++ b/drivers/mtd/devices/m25p80.c
@@ -273,8 +273,9 @@ static int erase_sector(struct m25p *flash, u32 
offset, u32 command)
  static int m25p80_erase(struct mtd_info *mtd, struct erase_info *instr)
  {
  	struct m25p *flash = mtd_to_m25p(mtd);
-	u32 addr, len;
+	u32 addr;
  	uint32_t rem;
+	uint64_t len;
   	dev_dbg(&flash->spi->dev, "%s at 0x%llx, len %lld\n",
  			__func__, (long long)instr->addr,
@@ -896,7 +897,7 @@ static int m25p_probe(struct device_d *dev)
  	flash->mtd.type = MTD_NORFLASH;
  	flash->mtd.writesize = 1;
  	flash->mtd.flags = MTD_CAP_NORFLASH;
-	flash->mtd.size = info->sector_size * info->n_sectors;
+	flash->mtd.size = (uint64_t)info->sector_size * info->n_sectors;
  	flash->mtd.erase = m25p80_erase;
  	flash->mtd.read = m25p80_read;
  diff --git a/drivers/mtd/devices/mtd_dataflash.c 
b/drivers/mtd/devices/mtd_dataflash.c
index cdc0120..fa31b61 100644
--- a/drivers/mtd/devices/mtd_dataflash.c
+++ b/drivers/mtd/devices/mtd_dataflash.c
@@ -625,7 +625,7 @@ add_dataflash_otp(struct spi_device *spi, char *name,
   	device = &priv->mtd;
  	device->name = (pdata && pdata->name) ? pdata->name : "dataflash";
-	device->size = nr_pages * pagesize;
+	device->size = nr_pages * (uint64_t)pagesize;
  	device->erasesize = pagesize;
  	device->writesize = pagesize;
  	device->type = MTD_DATAFLASH;
diff --git a/drivers/mtd/mtdoob.c b/drivers/mtd/mtdoob.c
index 1e88b53..54888cd 100644
--- a/drivers/mtd/mtdoob.c
+++ b/drivers/mtd/mtdoob.c
@@ -78,7 +78,7 @@ static int add_mtdoob_device(struct mtd_info *mtd, 
char *devname, void **priv)
   	mtdoob = xzalloc(sizeof(*mtdoob));
  	mtdoob->cdev.ops = &mtd_ops_oob;
-	mtdoob->cdev.size = (mtd->size / mtd->writesize) * mtd->oobsize;
+	mtdoob->cdev.size = mtd_div_by_wb(mtd->size, mtd) * mtd->oobsize;
  	mtdoob->cdev.name = asprintf("%s_oob%d", devname, mtd->class_dev.id);
  	mtdoob->cdev.priv = mtdoob;
  	mtdoob->cdev.dev = &mtd->class_dev;
diff --git a/drivers/mtd/mtdraw.c b/drivers/mtd/mtdraw.c
index be34723..33ca05d 100644
--- a/drivers/mtd/mtdraw.c
+++ b/drivers/mtd/mtdraw.c
@@ -290,7 +290,7 @@ static int add_mtdraw_device(struct mtd_info *mtd, 
char *devname, void **priv)
  	mtdraw->mtd = mtd;
   	mtdraw->cdev.ops = (struct file_operations *)&mtd_raw_fops;
-	mtdraw->cdev.size = mtd->size / mtd->writesize *
+	mtdraw->cdev.size = mtd_div_by_wb(mtd->size, mtd) *
  		(mtd->writesize + mtd->oobsize);
  	mtdraw->cdev.name = asprintf("%s.raw", mtd->cdev.name);
  	mtdraw->cdev.priv = mtdraw;
diff --git a/include/linux/mtd/mtd-abi.h b/include/linux/mtd/mtd-abi.h
index 11d51e2..c1ba55b 100644
--- a/include/linux/mtd/mtd-abi.h
+++ b/include/linux/mtd/mtd-abi.h
@@ -9,6 +9,8 @@
   #ifndef DOXYGEN_SHOULD_SKIP_THIS
  +#include <asm-generic/div64.h>
+
  struct erase_info_user {
  	uint32_t start;
  	uint32_t length;
@@ -73,7 +75,7 @@ enum {
  struct mtd_info_user {
  	uint8_t type;
  	uint32_t flags;
-	uint32_t size;	 // Total size of the MTD
+	uint64_t size;	 /* Total size of the MTD */
  	uint32_t erasesize;
  	uint32_t writesize;
  	uint32_t oobsize;   // Amount of OOB data per block (e.g. 16)
@@ -173,6 +175,14 @@ enum mtd_file_modes {
  	MTD_MODE_RAW,
  };
  +
+static inline uint32_t mtd_user_div_by_eb(uint64_t sz,
+	struct mtd_info_user *mtd_user)
+{
+	do_div(sz, mtd_user->erasesize);
+	return sz;
+}
+
  #endif /* DOXYGEN_SHOULD_SKIP_THIS */
   #endif /* __MTD_ABI_H__ */
diff --git a/include/linux/mtd/mtd.h b/include/linux/mtd/mtd.h
index 402e497..d337455 100644
--- a/include/linux/mtd/mtd.h
+++ b/include/linux/mtd/mtd.h
@@ -86,7 +86,7 @@ struct mtd_oob_ops {
  struct mtd_info {
  	u_char type;
  	u_int32_t flags;
-	u_int32_t size;	 // Total size of the MTD
+	u_int64_t size;	 /* Total size of the MTD */
   	/* "Major" erase size for the device. Na?ve users may take this
  	 * to be the only erase size available, or may use the more detailed
@@ -253,6 +253,13 @@ static inline uint32_t mtd_mod_by_eb(uint64_t sz, 
struct mtd_info *mtd)
  {
  	return do_div(sz, mtd->erasesize);
  }
+
+static inline uint32_t mtd_div_by_wb(uint64_t sz, struct mtd_info *mtd)
+{
+	do_div(sz, mtd->writesize);
+	return sz;
+}
+
  	/* Kernel-side ioctl definitions */
   extern int add_mtd_device(struct mtd_info *mtd, char *devname, int 
device_id);
diff --git a/lib/libmtd.c b/lib/libmtd.c
index 1606b87..56672bd 100644
--- a/lib/libmtd.c
+++ b/lib/libmtd.c
@@ -195,7 +195,7 @@ int libmtd_read(const struct mtd_dev_info *mtd, int 
fd, int eb, int offs,
  	     void *buf, int len)
  {
  	int ret, rd = 0;
-	off_t seek;
+	loff_t seek;
   	ret = mtd_valid_erase_block(mtd, eb);
  	if (ret)
@@ -209,7 +209,7 @@ int libmtd_read(const struct mtd_dev_info *mtd, int 
fd, int eb, int offs,
  	}
   	/* Seek to the beginning of the eraseblock */
-	seek = (off_t)eb * mtd->eb_size + offs;
+	seek = (loff_t)eb * mtd->eb_size + offs;
  	if (lseek(fd, seek, SEEK_SET) != seek)
  		return sys_errmsg("cannot seek %s to offset %llu",
  				  mtd->node, (unsigned long long)seek);
@@ -229,7 +229,7 @@ int libmtd_write(const struct mtd_dev_info *mtd, int 
fd, int eb, int offs,
  	      void *buf, int len)
  {
  	int ret;
-	off_t seek;
+	loff_t seek;
   	ret = mtd_valid_erase_block(mtd, eb);
  	if (ret)
@@ -255,7 +255,7 @@ int libmtd_write(const struct mtd_dev_info *mtd, int 
fd, int eb, int offs,
  	}
   	/* Seek to the beginning of the eraseblock */
-	seek = (off_t)eb * mtd->eb_size + offs;
+	seek = (loff_t)eb * mtd->eb_size + offs;
  	if (lseek(fd, seek, SEEK_SET) != seek)
  		return sys_errmsg("cannot seek %s to offset %llu",
  				  mtd->node, (unsigned long long)seek);
@@ -326,7 +326,7 @@ int mtd_get_dev_info(const char *node, struct 
mtd_dev_info *mtd)
  		goto out_close;
  	}
  -	mtd->eb_cnt = ui.size / ui.erasesize;
+	mtd->eb_cnt = mtd_user_div_by_eb(ui.size, &ui);
   	switch(mtd->type) {
  	case MTD_ABSENT:
-- 
1.8.5.1



From d.lavnikevich at sam-solutions.net  Fri Mar  7 06:14:55 2014
From: d.lavnikevich at sam-solutions.net (Dmitry Lavnikevich)
Date: Fri, 7 Mar 2014 14:14:55 +0300
Subject: [PATCH 2/5] mtd: Support for 4GB partitions
In-Reply-To: <1394190783-12978-1-git-send-email-d.lavnikevich@sam-solutions.com>
References: <1394190783-12978-1-git-send-email-d.lavnikevich@sam-solutions.com>
Message-ID: <5319AA2F.5070604@sam-solutions.net>

This patch implements correct way of creating partitions on mtd
devices with size >= 4GB.

Signed-off-by: Dmitry Lavnikevich <d.lavnikevich at sam-solutions.com>
Signed-off-by: Grigory Milev <g.milev at sam-solutions.com>
---
  commands/partition.c    | 4 ++--
  drivers/mtd/partition.c | 4 ++--
  include/linux/mtd/mtd.h | 4 ++--
  3 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/commands/partition.c b/commands/partition.c
index f825722..44b91d1 100644
--- a/commands/partition.c
+++ b/commands/partition.c
@@ -59,11 +59,11 @@ static int mtd_part_do_parse_one(char *devname, 
const char *partstr,
  		size = SIZE_REMAINING;
  		end = (char *)partstr + 1;
  	} else {
-		size = strtoul_suffix(partstr, &end, 0);
+		size = strtoull_suffix(partstr, &end, 0);
  	}
   	if (*end == '@')
-		*offset = strtoul_suffix(end+1, &end, 0);
+		*offset = strtoull_suffix(end+1, &end, 0);
   	if (size == SIZE_REMAINING)
  		size = devsize - *offset;
diff --git a/drivers/mtd/partition.c b/drivers/mtd/partition.c
index 85f486d..1b8d36e 100644
--- a/drivers/mtd/partition.c
+++ b/drivers/mtd/partition.c
@@ -90,8 +90,8 @@ static int mtd_part_block_markbad(struct mtd_info 
*mtd, loff_t ofs)
  	return res;
  }
  -struct mtd_info *mtd_add_partition(struct mtd_info *mtd, off_t 
offset, size_t size,
-		unsigned long flags, const char *name)
+struct mtd_info *mtd_add_partition(struct mtd_info *mtd, off_t offset,
+		uint64_t size, unsigned long flags, const char *name)
  {
  	struct mtd_part *slave;
  	struct mtd_info *slave_mtd;
diff --git a/include/linux/mtd/mtd.h b/include/linux/mtd/mtd.h
index d337455..165bc88 100644
--- a/include/linux/mtd/mtd.h
+++ b/include/linux/mtd/mtd.h
@@ -277,8 +277,8 @@ struct mtd_notifier {
  	struct list_head list;
  };
  -struct mtd_info *mtd_add_partition(struct mtd_info *mtd, off_t 
offset, size_t size,
-		unsigned long flags, const char *name);
+struct mtd_info *mtd_add_partition(struct mtd_info *mtd, off_t offset,
+		uint64_t size, unsigned long flags, const char *name);
  void mtd_del_partition(struct mtd_info *mtd);
   extern void register_mtd_user (struct mtd_notifier *new);
-- 
1.8.5.1



From d.lavnikevich at sam-solutions.net  Fri Mar  7 06:15:04 2014
From: d.lavnikevich at sam-solutions.net (Dmitry Lavnikevich)
Date: Fri, 7 Mar 2014 14:15:04 +0300
Subject: [PATCH 3/5] ubi: Fix for creating ubi volumes with 64bit size
In-Reply-To: <1394190783-12978-1-git-send-email-d.lavnikevich@sam-solutions.com>
References: <1394190783-12978-1-git-send-email-d.lavnikevich@sam-solutions.com>
Message-ID: <5319AA38.20409@sam-solutions.net>

Since MTD is already supports >= 4GB device sizes it is better to
allow ubi valumes also be created of larger sizes.

Signed-off-by: Dmitry Lavnikevich <d.lavnikevich at sam-solutions.com>
Signed-off-by: Grigory Milev <g.milev at sam-solutions.com>
---
  commands/ubi.c         | 4 ++--
  drivers/mtd/ubi/cdev.c | 2 +-
  2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/commands/ubi.c b/commands/ubi.c
index 57ae790..8a409c2 100644
--- a/commands/ubi.c
+++ b/commands/ubi.c
@@ -15,12 +15,12 @@ static int do_ubimkvol(int argc, char *argv[])
  {
  	struct ubi_mkvol_req req;
  	int fd, ret;
-	size_t size;
+	uint64_t size;
   	if (argc != 4)
  		return COMMAND_ERROR_USAGE;
  -	size = strtoul_suffix(argv[3], NULL, 0);
+	size = strtoull_suffix(argv[3], NULL, 0);
  	req.name_len = min_t(int, strlen(argv[2]), UBI_VOL_NAME_MAX);
  	strncpy(req.name, argv[2], req.name_len);
  	req.name[req.name_len] = 0;
diff --git a/drivers/mtd/ubi/cdev.c b/drivers/mtd/ubi/cdev.c
index 129f2e2..b97739a 100644
--- a/drivers/mtd/ubi/cdev.c
+++ b/drivers/mtd/ubi/cdev.c
@@ -220,7 +220,7 @@ static int ubi_cdev_ioctl(struct cdev *cdev, int 
cmd, void *buf)
  		break;
  	case UBI_IOCMKVOL:
  		if (!req->bytes)
-			req->bytes = ubi->avail_pebs * ubi->leb_size;
+			req->bytes = (__s64)ubi->avail_pebs * ubi->leb_size;
  		return ubi_create_volume(ubi, req);
  	};
  -- 1.8.5.1



From d.lavnikevich at sam-solutions.net  Fri Mar  7 06:15:12 2014
From: d.lavnikevich at sam-solutions.net (Dmitry Lavnikevich)
Date: Fri, 7 Mar 2014 14:15:12 +0300
Subject: [PATCH 4/5] nand: mxs: Check for up to 4 NAND chips
In-Reply-To: <1394190783-12978-1-git-send-email-d.lavnikevich@sam-solutions.com>
References: <1394190783-12978-1-git-send-email-d.lavnikevich@sam-solutions.com>
Message-ID: <5319AA40.5060507@sam-solutions.net>

Since i.MX6 has only one R/B actual pin, if there are several R/B
signals (from different NAND chips) they must be connected to this
pin.

Signed-off-by: Dmitry Lavnikevich <d.lavnikevich at sam-solutions.com>
Signed-off-by: Grigory Milev <g.milev at sam-solutions.com>
---
  drivers/mtd/nand/nand_mxs.c | 11 +++++++++--
  1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/drivers/mtd/nand/nand_mxs.c b/drivers/mtd/nand/nand_mxs.c
index d1e4b57..237a423 100644
--- a/drivers/mtd/nand/nand_mxs.c
+++ b/drivers/mtd/nand/nand_mxs.c
@@ -33,6 +33,7 @@
  #include <dma/apbh-dma.h>
  #include <stmp-device.h>
  #include <asm/mmu.h>
+#include <mach/generic.h>
   #define	MX28_BLOCK_SFTRST				(1 << 31)
  #define	MX28_BLOCK_CLKGATE				(1 << 30)
@@ -427,7 +428,13 @@ static int mxs_nand_device_ready(struct mtd_info *mtd)
   	if (nand_info->version > GPMI_VERSION_TYPE_MX23) {
  		tmp = readl(gpmi_regs + GPMI_STAT);
-		tmp >>= (GPMI_STAT_READY_BUSY_OFFSET + nand_info->cur_chip);
+		/* i.MX6 has only one R/B actual pin, so if there are several
+		   R/B signals they must be all connected to this pin */
+		if (cpu_is_mx6())
+			tmp >>= GPMI_STAT_READY_BUSY_OFFSET;
+		else
+			tmp >>= (GPMI_STAT_READY_BUSY_OFFSET +
+					 nand_info->cur_chip);
  	} else {
  		tmp = readl(gpmi_regs + GPMI_DEBUG);
  		tmp >>= (GPMI_DEBUG_READY0_OFFSET + nand_info->cur_chip);
@@ -1304,7 +1311,7 @@ static int mxs_nand_probe(struct device_d *dev)
  	nand->ecc.strength	= 8;
   	/* first scan to find the device and get the page size */
-	err = nand_scan_ident(mtd, 1, NULL);
+	err = nand_scan_ident(mtd, 4, NULL);
  	if (err)
  		goto err2;
  -- 1.8.5.1



From d.lavnikevich at sam-solutions.net  Fri Mar  7 06:15:22 2014
From: d.lavnikevich at sam-solutions.net (Dmitry Lavnikevich)
Date: Fri, 7 Mar 2014 14:15:22 +0300
Subject: [PATCH 5/5] nand: mxs: Fix for calculating ecc strength on some types
 of NAND flash
In-Reply-To: <1394190783-12978-1-git-send-email-d.lavnikevich@sam-solutions.com>
References: <1394190783-12978-1-git-send-email-d.lavnikevich@sam-solutions.com>
Message-ID: <5319AA4A.2020704@sam-solutions.net>

Was tested on NAND with {writesize=4096, oobsize=224} and
{writesize=2048, oobsize=64}.

This patch will not break any NAND that was working
before. Implemented calculation way may be used for other NAND chips
with writesize == 2048 but oobsize != 64.

Signed-off-by: Dmitry Lavnikevich <d.lavnikevich at sam-solutions.com>
Signed-off-by: Grigory Milev <g.milev at sam-solutions.com>
---
  drivers/mtd/nand/nand_mxs.c | 21 +++++++++++++++++----
  1 file changed, 17 insertions(+), 4 deletions(-)

diff --git a/drivers/mtd/nand/nand_mxs.c b/drivers/mtd/nand/nand_mxs.c
index 237a423..b06b558 100644
--- a/drivers/mtd/nand/nand_mxs.c
+++ b/drivers/mtd/nand/nand_mxs.c
@@ -234,18 +234,31 @@ static uint32_t mxs_nand_aux_status_offset(void)
  static inline uint32_t mxs_nand_get_ecc_strength(uint32_t page_data_size,
  						uint32_t page_oob_size)
  {
+	int ecc_chunk_count = mxs_nand_ecc_chunk_cnt(page_data_size);
+	int ecc_strength = 0;
+	int gf_len = 13;  /* length of Galois Field for non-DDR nand */
+
+	/*
+	 * Possibly this if-else calculation may be removed since
+	 * ecc_strength calculated after it is taken from kernel driver
+	 * and therefore should work for all cases. But it was tested only
+	 * on devices with {data_size = 2046, oob_size = 64} and
+	 * {data_size = 4096, oob_size = 224} configuration.
+	 */
  	if (page_data_size == 2048)
  		return 8;
-
-	if (page_data_size == 4096) {
+	else if (page_data_size == 4096) {
  		if (page_oob_size == 128)
  			return 8;
-
  		if (page_oob_size == 218)
  			return 16;
  	}
  -	return 0;
+	ecc_strength = ((page_oob_size - MXS_NAND_METADATA_SIZE) * 8)
+		/ (gf_len * ecc_chunk_count);
+
+	/* We need the minor even number. */
+	return rounddown(ecc_strength, 2);
  }
   static inline uint32_t mxs_nand_get_mark_offset(uint32_t page_data_size,
-- 
1.8.5.1



From philippe.retornaz at epfl.ch  Fri Mar  7 13:14:55 2014
From: philippe.retornaz at epfl.ch (=?UTF-8?q?Philippe=20R=C3=A9tornaz?=)
Date: Fri,  7 Mar 2014 19:14:55 +0100
Subject: [PATCH 1/1] ARM: mx31moboard: Fix UPLL and SPLL initialisation
Message-ID: <1394216095-20377-1-git-send-email-philippe.retornaz@epfl.ch>

This copy what the previous bootloader was doing on this board.
It fixes USB host 1 clock error as its PHY clock is provided
by the i.MX31.

Signed-off-by: Philippe R?tornaz <philippe.retornaz at epfl.ch>
---
 arch/arm/boards/mx31moboard/lowlevel.c |    5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boards/mx31moboard/lowlevel.c b/arch/arm/boards/mx31moboard/lowlevel.c
index e9ffb74..2294c5a 100644
--- a/arch/arm/boards/mx31moboard/lowlevel.c
+++ b/arch/arm/boards/mx31moboard/lowlevel.c
@@ -59,9 +59,12 @@ static noinline __noreturn void mx31moboard_startup(void)
 	writel(IMX_PLL_PD(0) | IMX_PLL_MFD(0x33) |
 			IMX_PLL_MFI(0xa) | IMX_PLL_MFN(0x0C),
 			MX31_CCM_BASE_ADDR + MX31_CCM_MPCTL);
-	writel(IMX_PLL_PD(1) | IMX_PLL_MFD(0x43) | IMX_PLL_MFI(12) |
+	writel(IMX_PLL_PD(0) | IMX_PLL_MFD(9) | IMX_PLL_MFI(6) |
 			IMX_PLL_MFN(1), MX31_CCM_BASE_ADDR +
 			MX31_CCM_SPCTL);
+	writel(IMX_PLL_PD(1) | IMX_PLL_MFD(12) | IMX_PLL_MFI(9) |
+			IMX_PLL_MFN(3), MX31_CCM_BASE_ADDR +
+			MX31_CCM_UPCTL);
 
 	/*
 	 * Configure IOMUXC
-- 
1.7.9.5



From shc_work at mail.ru  Sat Mar  8 01:41:40 2014
From: shc_work at mail.ru (Alexander Shiyan)
Date: Sat, 8 Mar 2014 10:41:40 +0400
Subject: [PATCH 1/7] ARM: socfgpa: Remove redundant assignment
In-Reply-To: <20140217070909.GK17250@pengutronix.de>
References: <1392525650-5551-1-git-send-email-shc_work@mail.ru>
 <20140217070909.GK17250@pengutronix.de>
Message-ID: <20140308104140.3e7f9db4823b8fd62c0a631e@mail.ru>

On Mon, 17 Feb 2014 08:09:09 +0100
Sascha Hauer <s.hauer at pengutronix.de> wrote:

> On Sun, Feb 16, 2014 at 08:40:44AM +0400, Alexander Shiyan wrote:
> > Signed-off-by: Alexander Shiyan <shc_work at mail.ru>
> 
> Applied all except 6/7 which probably needs some adjustments.

It seems that the patches are lost.
I do not see them in the master branch.

-- 
Alexander Shiyan <shc_work at mail.ru>


From plagnioj at jcrosoft.com  Sat Mar  8 11:54:01 2014
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Sat, 8 Mar 2014 17:54:01 +0100
Subject: [PATCH 3/5] net: remove old nfs support
In-Reply-To: <20140306162100.GC17250@pengutronix.de>
References: <1393534812-30995-1-git-send-email-s.hauer@pengutronix.de>
 <1393534812-30995-4-git-send-email-s.hauer@pengutronix.de>
 <20140304040345.GP9671@ns203013.ovh.net>
 <20140306162100.GC17250@pengutronix.de>
Message-ID: <20140308165401.GA6478@ns203013.ovh.net>

On 17:21 Thu 06 Mar     , Sascha Hauer wrote:
> On Tue, Mar 04, 2014 at 05:03:45AM +0100, Jean-Christophe PLAGNIOL-VILLARD wrote:
> > On 22:00 Thu 27 Feb     , Sascha Hauer wrote:
> > > Now that we have the NFS as filesystem support for several releases
> > > remove the old command based NFS support.
> > > 
> > > Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
> > 
> > as the bootp is not fully supported on default env2 do not drop it
> 
> Ok for now, but I really want to get rid of it. Would a nfs wrapper
> command be ok?

no as the issue is the symlink as you need to change the mount path

so check it

When I've time I'll take a look for defautlenv2 to fix the bootp support

but untill we have defaultenv v1 I think we need to keep this cmd and tftp

Best Regards,
J.
> 
> Sascha
> 
> -- 
> Pengutronix e.K.                           |                             |
> Industrial Linux Solutions                 | http://www.pengutronix.de/  |
> Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
> Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From shc_work at mail.ru  Sun Mar  9 01:27:46 2014
From: shc_work at mail.ru (Alexander Shiyan)
Date: Sun,  9 Mar 2014 10:27:46 +0400
Subject: [PATCH] treewide: Kill empty remove() implementations
Message-ID: <1394346466-31156-1-git-send-email-shc_work@mail.ru>

Signed-off-by: Alexander Shiyan <shc_work at mail.ru>
---
 drivers/net/ar231x.c       | 6 ------
 drivers/net/at91_ether.c   | 5 -----
 drivers/net/designware.c   | 5 -----
 drivers/video/imx-ipu-fb.c | 5 -----
 drivers/video/imx.c        | 5 -----
 drivers/video/pxa.c        | 5 -----
 6 files changed, 31 deletions(-)

diff --git a/drivers/net/ar231x.c b/drivers/net/ar231x.c
index 5c09114..515de17 100644
--- a/drivers/net/ar231x.c
+++ b/drivers/net/ar231x.c
@@ -419,15 +419,9 @@ static int ar231x_eth_probe(struct device_d *dev)
 	return 0;
 }
 
-static void ar231x_eth_remove(struct device_d *dev)
-{
-
-}
-
 static struct driver_d ar231x_eth_driver = {
 	.name = "ar231x_eth",
 	.probe = ar231x_eth_probe,
-	.remove = ar231x_eth_remove,
 };
 
 static int ar231x_eth_driver_init(void)
diff --git a/drivers/net/at91_ether.c b/drivers/net/at91_ether.c
index 25924cf..bf2f957 100644
--- a/drivers/net/at91_ether.c
+++ b/drivers/net/at91_ether.c
@@ -357,13 +357,8 @@ static int at91_ether_probe(struct device_d *dev)
 	return 0;
 }
 
-static void at91_ether_remove(struct device_d *dev)
-{
-}
-
 static struct driver_d at91_ether_driver = {
 	.name = "at91_ether",
 	.probe = at91_ether_probe,
-	.remove = at91_ether_remove,
 };
 device_platform_driver(at91_ether_driver);
diff --git a/drivers/net/designware.c b/drivers/net/designware.c
index ecb4656..e706f54 100644
--- a/drivers/net/designware.c
+++ b/drivers/net/designware.c
@@ -477,10 +477,6 @@ static int dwc_ether_probe(struct device_d *dev)
 	return 0;
 }
 
-static void dwc_ether_remove(struct device_d *dev)
-{
-}
-
 static __maybe_unused struct of_device_id dwc_ether_compatible[] = {
 	{
 		.compatible = "snps,dwmac-3.70a",
@@ -493,7 +489,6 @@ static __maybe_unused struct of_device_id dwc_ether_compatible[] = {
 static struct driver_d dwc_ether_driver = {
 	.name = "designware_eth",
 	.probe = dwc_ether_probe,
-	.remove = dwc_ether_remove,
 	.of_compatible = DRV_OF_COMPAT(dwc_ether_compatible),
 };
 device_platform_driver(dwc_ether_driver);
diff --git a/drivers/video/imx-ipu-fb.c b/drivers/video/imx-ipu-fb.c
index 7276647..cd74b03 100644
--- a/drivers/video/imx-ipu-fb.c
+++ b/drivers/video/imx-ipu-fb.c
@@ -1047,14 +1047,9 @@ static int imxfb_probe(struct device_d *dev)
 	return ret;
 }
 
-static void imxfb_remove(struct device_d *dev)
-{
-}
-
 static struct driver_d imx3fb_driver = {
 	.name = "imx-ipu-fb",
 	.probe = imxfb_probe,
-	.remove = imxfb_remove,
 };
 device_platform_driver(imx3fb_driver);
 
diff --git a/drivers/video/imx.c b/drivers/video/imx.c
index 6e2d8d6..b2eb9fc 100644
--- a/drivers/video/imx.c
+++ b/drivers/video/imx.c
@@ -580,13 +580,8 @@ static int imxfb_probe(struct device_d *dev)
 	return 0;
 }
 
-static void imxfb_remove(struct device_d *dev)
-{
-}
-
 static struct driver_d imxfb_driver = {
 	.name		= "imxfb",
 	.probe		= imxfb_probe,
-	.remove		= imxfb_remove,
 };
 device_platform_driver(imxfb_driver);
diff --git a/drivers/video/pxa.c b/drivers/video/pxa.c
index 529190b..b4ce3a1 100644
--- a/drivers/video/pxa.c
+++ b/drivers/video/pxa.c
@@ -536,13 +536,8 @@ static int pxafb_probe(struct device_d *dev)
 	return 0;
 }
 
-static void pxafb_remove(struct device_d *dev)
-{
-}
-
 static struct driver_d pxafb_driver = {
 	.name	= "pxafb",
 	.probe	= pxafb_probe,
-	.remove	= pxafb_remove,
 };
 device_platform_driver(pxafb_driver);
-- 
1.8.3.2



From s.hauer at pengutronix.de  Mon Mar 10 03:08:37 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Mon, 10 Mar 2014 08:08:37 +0100
Subject: [PATCH v2 2/7] ARM: i.MX53: Add sata to devicetree
In-Reply-To: <1394188803-13456-2-git-send-email-eric@eukrea.com>
References: <20140210091152.GM17250@pengutronix.de>
 <1394188803-13456-1-git-send-email-eric@eukrea.com>
 <1394188803-13456-2-git-send-email-eric@eukrea.com>
Message-ID: <20140310070837.GF17250@pengutronix.de>

Hi Eric,

On Fri, Mar 07, 2014 at 11:39:58AM +0100, Eric B?nard wrote:
> Signed-off-by: Eric B?nard <eric at eukrea.com>
> ---
> v2: update the SATA entry to be compatible with the kernel, but do
>   not use the Linux-next dts. This means use plain numbers, but the
>   correct clock names.

It seems I already accidently applied v1 of this patch. Instead of this
one I merged a fixup patch. Please check the result in the -next branch.

Sascha

>   
>  arch/arm/dts/imx53.dtsi | 9 +++++++++
>  1 file changed, 9 insertions(+)
> 
> diff --git a/arch/arm/dts/imx53.dtsi b/arch/arm/dts/imx53.dtsi
> index 678547c..a28c4c7 100644
> --- a/arch/arm/dts/imx53.dtsi
> +++ b/arch/arm/dts/imx53.dtsi
> @@ -75,6 +75,15 @@
>  		interrupt-parent = <&tzic>;
>  		ranges;
>  
> +		sata: sata at 10000000 {
> +			compatible = "fsl,imx53-ahci";
> +			reg = <0x10000000 0x1000>;
> +			interrupts = <28>;
> +			clocks = <&clks 173>, <&clks 188>, <&clks 5>;
> +			clock-names = "sata_gate", "sata_ref", "ahb";
> +			status = "disabled";
> +		};
> +
>  		ipu: ipu at 18000000 {
>  			#crtc-cells = <1>;
>  			compatible = "fsl,imx53-ipu";
> -- 
> 1.8.3.1
> 
> 
> _______________________________________________
> barebox mailing list
> barebox at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/barebox

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From s.hauer at pengutronix.de  Mon Mar 10 03:09:57 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Mon, 10 Mar 2014 08:09:57 +0100
Subject: [PATCH v2 1/7] sata-imx: i.MX53, use the internal 120MHz clock
 by default
In-Reply-To: <1394188803-13456-1-git-send-email-eric@eukrea.com>
References: <20140210091152.GM17250@pengutronix.de>
 <1394188803-13456-1-git-send-email-eric@eukrea.com>
Message-ID: <20140310070957.GG17250@pengutronix.de>

On Fri, Mar 07, 2014 at 11:39:57AM +0100, Eric B?nard wrote:
> this allows SATA to work on i.MX53 QSB-R :
> barebox at Freescale i.MX53 Quick Start-R Board:/ ata0.probe=1
> imx-sata 10000000.sata: port 0: SATA link ok
> imx-sata 10000000.sata: port 0: Spinning up device...
> imx-sata 10000000.sata: port 0: ok.
> ata0: registered /dev/ata0
> 
> before this fix the log was :
> barebox at Freescale i.MX53 Quick Start-R Board:/ ata0.probe=1
> imx-sata 10000000.sata: port 0: SATA link timeout
> set parameter: Connection timed out
> 
> Signed-off-by: Eric B?nard <eric at eukrea.com>
> ---
>  drivers/ata/sata-imx.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/ata/sata-imx.c b/drivers/ata/sata-imx.c
> index b7bd110..450cf4f 100644
> --- a/drivers/ata/sata-imx.c
> +++ b/drivers/ata/sata-imx.c
> @@ -59,7 +59,7 @@ static int imx53_sata_init(struct imx_ahci *imx_ahci)
>  	 */
>  	val = readl(base + 0x180c);
>  	val &= (0x3 << 1);
> -	val |= (0x1 << 1);
> +	val |= (0x2 << 1);
>  	writel(val, base + 0x180c);

I haven't applied this yet. Have you tested this on the regular (not -R)
variant of the board? If not I'd like to do that before applying.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From s.hauer at pengutronix.de  Mon Mar 10 03:20:03 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Mon, 10 Mar 2014 08:20:03 +0100
Subject: [PATCH 1/5] mtd: Update internal API to support 64-bit device size
In-Reply-To: <5319AA25.5050803@sam-solutions.net>
References: <5319AA25.5050803@sam-solutions.net>
Message-ID: <20140310072003.GH17250@pengutronix.de>

Hi Dmitry,

On Fri, Mar 07, 2014 at 02:14:45PM +0300, Dmitry Lavnikevich wrote:
> MTD internal API presently uses 32-bit values to represent device
> size. This patch updates them to 64-bits but leaves the external API
> unchanged.
> 
> In general, changing from 32-bit to 64-bit values cause little
> or no changes to the majority of the code with the following
> exceptions:
>   - printk message formats;
>   - division and modulus of 64-bit values (mtd_div_by_wb,
>     mtd_div_by_eb may be used in some of such cases).
> 
> Was tested on phyFLEX i.MX6.
> 
> Signed-off-by: Dmitry Lavnikevich <d.lavnikevich at sam-solutions.com>
> Signed-off-by: Grigory Milev <g.milev at sam-solutions.com>

Your patches look all good. Unfortunately I can't apply them because
your mailer wraps lines.

> diff --git a/drivers/mtd/core.c b/drivers/mtd/core.c
> index 6db1c6d..7efb03c 100644
> --- a/drivers/mtd/core.c
> +++ b/drivers/mtd/core.c
> @@ -397,7 +397,7 @@ int add_mtd_device(struct mtd_info *mtd, char
> *devname, int device_id)
>  	mtd->cdev.mtd = mtd;
>   	if (IS_ENABLED(CONFIG_PARAMETER)) {
> -		dev_add_param_int_ro(&mtd->class_dev, "size", mtd->size, "%u");
> +		dev_add_param_int_ro(&mtd->class_dev, "size", mtd->size, "%llu");
>  		dev_add_param_int_ro(&mtd->class_dev, "erasesize",
> mtd->erasesize, "%u");

For example here.

>  	flash->mtd.read = m25p80_read;
>  diff --git a/drivers/mtd/devices/mtd_dataflash.c

Here is one space too much before 'diff'

> diff --git a/include/linux/mtd/mtd-abi.h b/include/linux/mtd/mtd-abi.h
> index 11d51e2..c1ba55b 100644
> --- a/include/linux/mtd/mtd-abi.h
> +++ b/include/linux/mtd/mtd-abi.h
> @@ -9,6 +9,8 @@
>   #ifndef DOXYGEN_SHOULD_SKIP_THIS
>  +#include <asm-generic/div64.h>
> +

Here also is one space too much.

Could you try resending it using git-send-email?

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
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From alex.aring at gmail.com  Mon Mar 10 04:02:15 2014
From: alex.aring at gmail.com (Alexander Aring)
Date: Mon, 10 Mar 2014 09:02:15 +0100
Subject: [PATCH 1/5] mtd: Update internal API to support 64-bit device size
In-Reply-To: <20140310072003.GH17250@pengutronix.de>
References: <5319AA25.5050803@sam-solutions.net>
 <20140310072003.GH17250@pengutronix.de>
Message-ID: <20140310080213.GA32061@x61s.Speedport_W_921V_1_24_000>

Hi Sascha,

we talked some time ago about >= 4GB mtd support. This patch series add
only a size for uint64_t. But then we also need to change

uint32_t master_offset;

in mtd_info to:

uint64_t master_offset;

otherwise we can't create mtd partitions with a uint64_t offset. Or I am
wrong with that? I mean... maybe they don't want to make a uint64_t
offset but we should do it right at first time.

- Alex


From eric at eukrea.com  Mon Mar 10 03:51:12 2014
From: eric at eukrea.com (Eric =?ISO-8859-1?B?QuluYXJk?=)
Date: Mon, 10 Mar 2014 08:51:12 +0100
Subject: [PATCH v2 1/7] sata-imx: i.MX53, use the internal 120MHz clock
 by default
In-Reply-To: <20140310070957.GG17250@pengutronix.de>
References: <20140210091152.GM17250@pengutronix.de>
 <1394188803-13456-1-git-send-email-eric@eukrea.com>
 <20140310070957.GG17250@pengutronix.de>
Message-ID: <20140310085112.55b969e5@e6520eb>

Hi Sascha,

Le Mon, 10 Mar 2014 08:09:57 +0100,
Sascha Hauer <s.hauer at pengutronix.de> a ?crit :

> On Fri, Mar 07, 2014 at 11:39:57AM +0100, Eric B?nard wrote:
> > this allows SATA to work on i.MX53 QSB-R :
> > barebox at Freescale i.MX53 Quick Start-R Board:/ ata0.probe=1
> > imx-sata 10000000.sata: port 0: SATA link ok
> > imx-sata 10000000.sata: port 0: Spinning up device...
> > imx-sata 10000000.sata: port 0: ok.
> > ata0: registered /dev/ata0
> > 
> > before this fix the log was :
> > barebox at Freescale i.MX53 Quick Start-R Board:/ ata0.probe=1
> > imx-sata 10000000.sata: port 0: SATA link timeout
> > set parameter: Connection timed out
> > 
> > Signed-off-by: Eric B?nard <eric at eukrea.com>
> > ---
> >  drivers/ata/sata-imx.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> > 
> > diff --git a/drivers/ata/sata-imx.c b/drivers/ata/sata-imx.c
> > index b7bd110..450cf4f 100644
> > --- a/drivers/ata/sata-imx.c
> > +++ b/drivers/ata/sata-imx.c
> > @@ -59,7 +59,7 @@ static int imx53_sata_init(struct imx_ahci *imx_ahci)
> >  	 */
> >  	val = readl(base + 0x180c);
> >  	val &= (0x3 << 1);
> > -	val |= (0x1 << 1);
> > +	val |= (0x2 << 1);
> >  	writel(val, base + 0x180c);
> 
> I haven't applied this yet. Have you tested this on the regular (not -R)
> variant of the board? If not I'd like to do that before applying.

I can try to test on an original QSB (with Dialog PMIC) but I don't see
why that would change as the difference between QSB and QSB-R is the
PMIC (Dialog to Freescale) and here we only change the clock source of
the SATA which has nothing to see with the PMIC.

Eric


From d.lavnikevich at sam-solutions.net  Mon Mar 10 07:37:01 2014
From: d.lavnikevich at sam-solutions.net (Dmitry Lavnikevich)
Date: Mon, 10 Mar 2014 14:37:01 +0300
Subject: [PATCH 1/5] mtd: Update internal API to support 64-bit device size
In-Reply-To: <20140310072003.GH17250@pengutronix.de>
References: <5319AA25.5050803@sam-solutions.net>
 <20140310072003.GH17250@pengutronix.de>
Message-ID: <531DA3DD.20507@sam-solutions.net>

Hello Sascha,

eyah, I've had some problems sending mails with git send-email
through my proxy so tried to use thunderbird to pass patches outside.
Which apparently did some improvisation on them :)

Anyway, I have fixed my sendmail and will resend patches soon.

Best regards,
Lavnikevich Dmitry

On 03/10/14 10:20, Sascha Hauer wrote:
> Hi Dmitry,
>
> On Fri, Mar 07, 2014 at 02:14:45PM +0300, Dmitry Lavnikevich wrote:
>> MTD internal API presently uses 32-bit values to represent device
>> size. This patch updates them to 64-bits but leaves the external API
>> unchanged.
>>
>> In general, changing from 32-bit to 64-bit values cause little
>> or no changes to the majority of the code with the following
>> exceptions:
>>    - printk message formats;
>>    - division and modulus of 64-bit values (mtd_div_by_wb,
>>      mtd_div_by_eb may be used in some of such cases).
>>
>> Was tested on phyFLEX i.MX6.
>>
>> Signed-off-by: Dmitry Lavnikevich <d.lavnikevich at sam-solutions.com>
>> Signed-off-by: Grigory Milev <g.milev at sam-solutions.com>
> Your patches look all good. Unfortunately I can't apply them because
> your mailer wraps lines.
>
>> diff --git a/drivers/mtd/core.c b/drivers/mtd/core.c
>> index 6db1c6d..7efb03c 100644
>> --- a/drivers/mtd/core.c
>> +++ b/drivers/mtd/core.c
>> @@ -397,7 +397,7 @@ int add_mtd_device(struct mtd_info *mtd, char
>> *devname, int device_id)
>>   	mtd->cdev.mtd = mtd;
>>    	if (IS_ENABLED(CONFIG_PARAMETER)) {
>> -		dev_add_param_int_ro(&mtd->class_dev, "size", mtd->size, "%u");
>> +		dev_add_param_int_ro(&mtd->class_dev, "size", mtd->size, "%llu");
>>   		dev_add_param_int_ro(&mtd->class_dev, "erasesize",
>> mtd->erasesize, "%u");
> For example here.
>
>>   	flash->mtd.read = m25p80_read;
>>   diff --git a/drivers/mtd/devices/mtd_dataflash.c
> Here is one space too much before 'diff'
>
>> diff --git a/include/linux/mtd/mtd-abi.h b/include/linux/mtd/mtd-abi.h
>> index 11d51e2..c1ba55b 100644
>> --- a/include/linux/mtd/mtd-abi.h
>> +++ b/include/linux/mtd/mtd-abi.h
>> @@ -9,6 +9,8 @@
>>    #ifndef DOXYGEN_SHOULD_SKIP_THIS
>>   +#include <asm-generic/div64.h>
>> +
> Here also is one space too much.
>
> Could you try resending it using git-send-email?
>
> Sascha
>



From d.lavnikevich at sam-solutions.com  Mon Mar 10 07:39:52 2014
From: d.lavnikevich at sam-solutions.com (Dmitry Lavnikevich)
Date: Mon, 10 Mar 2014 14:39:52 +0300
Subject: [PATCH 4/5] nand: mxs: Check for up to 4 NAND chips
In-Reply-To: <1394451593-3090-1-git-send-email-d.lavnikevich@sam-solutions.com>
References: <1394451593-3090-1-git-send-email-d.lavnikevich@sam-solutions.com>
Message-ID: <1394451593-3090-4-git-send-email-d.lavnikevich@sam-solutions.com>

Since i.MX6 has only one R/B actual pin, if there are several R/B
signals (from different NAND chips) they must be connected to this
pin.

Signed-off-by: Dmitry Lavnikevich <d.lavnikevich at sam-solutions.com>
Signed-off-by: Grigory Milev <g.milev at sam-solutions.com>
---
 drivers/mtd/nand/nand_mxs.c | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/drivers/mtd/nand/nand_mxs.c b/drivers/mtd/nand/nand_mxs.c
index d1e4b57..237a423 100644
--- a/drivers/mtd/nand/nand_mxs.c
+++ b/drivers/mtd/nand/nand_mxs.c
@@ -33,6 +33,7 @@
 #include <dma/apbh-dma.h>
 #include <stmp-device.h>
 #include <asm/mmu.h>
+#include <mach/generic.h>
 
 #define	MX28_BLOCK_SFTRST				(1 << 31)
 #define	MX28_BLOCK_CLKGATE				(1 << 30)
@@ -427,7 +428,13 @@ static int mxs_nand_device_ready(struct mtd_info *mtd)
 
 	if (nand_info->version > GPMI_VERSION_TYPE_MX23) {
 		tmp = readl(gpmi_regs + GPMI_STAT);
-		tmp >>= (GPMI_STAT_READY_BUSY_OFFSET + nand_info->cur_chip);
+		/* i.MX6 has only one R/B actual pin, so if there are several
+		   R/B signals they must be all connected to this pin */
+		if (cpu_is_mx6())
+			tmp >>= GPMI_STAT_READY_BUSY_OFFSET;
+		else
+			tmp >>= (GPMI_STAT_READY_BUSY_OFFSET +
+					 nand_info->cur_chip);
 	} else {
 		tmp = readl(gpmi_regs + GPMI_DEBUG);
 		tmp >>= (GPMI_DEBUG_READY0_OFFSET + nand_info->cur_chip);
@@ -1304,7 +1311,7 @@ static int mxs_nand_probe(struct device_d *dev)
 	nand->ecc.strength	= 8;
 
 	/* first scan to find the device and get the page size */
-	err = nand_scan_ident(mtd, 1, NULL);
+	err = nand_scan_ident(mtd, 4, NULL);
 	if (err)
 		goto err2;
 
-- 
1.9.0



From d.lavnikevich at sam-solutions.com  Mon Mar 10 07:39:50 2014
From: d.lavnikevich at sam-solutions.com (Dmitry Lavnikevich)
Date: Mon, 10 Mar 2014 14:39:50 +0300
Subject: [PATCH 2/5] mtd: Support for 4GB partitions
In-Reply-To: <1394451593-3090-1-git-send-email-d.lavnikevich@sam-solutions.com>
References: <1394451593-3090-1-git-send-email-d.lavnikevich@sam-solutions.com>
Message-ID: <1394451593-3090-2-git-send-email-d.lavnikevich@sam-solutions.com>

This patch implements correct way of creating partitions on mtd
devices with size >= 4GB.

Signed-off-by: Dmitry Lavnikevich <d.lavnikevich at sam-solutions.com>
Signed-off-by: Grigory Milev <g.milev at sam-solutions.com>
---
 commands/partition.c    | 4 ++--
 drivers/mtd/partition.c | 4 ++--
 include/linux/mtd/mtd.h | 4 ++--
 3 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/commands/partition.c b/commands/partition.c
index f825722..44b91d1 100644
--- a/commands/partition.c
+++ b/commands/partition.c
@@ -59,11 +59,11 @@ static int mtd_part_do_parse_one(char *devname, const char *partstr,
 		size = SIZE_REMAINING;
 		end = (char *)partstr + 1;
 	} else {
-		size = strtoul_suffix(partstr, &end, 0);
+		size = strtoull_suffix(partstr, &end, 0);
 	}
 
 	if (*end == '@')
-		*offset = strtoul_suffix(end+1, &end, 0);
+		*offset = strtoull_suffix(end+1, &end, 0);
 
 	if (size == SIZE_REMAINING)
 		size = devsize - *offset;
diff --git a/drivers/mtd/partition.c b/drivers/mtd/partition.c
index 85f486d..1b8d36e 100644
--- a/drivers/mtd/partition.c
+++ b/drivers/mtd/partition.c
@@ -90,8 +90,8 @@ static int mtd_part_block_markbad(struct mtd_info *mtd, loff_t ofs)
 	return res;
 }
 
-struct mtd_info *mtd_add_partition(struct mtd_info *mtd, off_t offset, size_t size,
-		unsigned long flags, const char *name)
+struct mtd_info *mtd_add_partition(struct mtd_info *mtd, off_t offset,
+		uint64_t size, unsigned long flags, const char *name)
 {
 	struct mtd_part *slave;
 	struct mtd_info *slave_mtd;
diff --git a/include/linux/mtd/mtd.h b/include/linux/mtd/mtd.h
index d337455..165bc88 100644
--- a/include/linux/mtd/mtd.h
+++ b/include/linux/mtd/mtd.h
@@ -277,8 +277,8 @@ struct mtd_notifier {
 	struct list_head list;
 };
 
-struct mtd_info *mtd_add_partition(struct mtd_info *mtd, off_t offset, size_t size,
-		unsigned long flags, const char *name);
+struct mtd_info *mtd_add_partition(struct mtd_info *mtd, off_t offset,
+		uint64_t size, unsigned long flags, const char *name);
 void mtd_del_partition(struct mtd_info *mtd);
 
 extern void register_mtd_user (struct mtd_notifier *new);
-- 
1.9.0



From d.lavnikevich at sam-solutions.com  Mon Mar 10 07:39:51 2014
From: d.lavnikevich at sam-solutions.com (Dmitry Lavnikevich)
Date: Mon, 10 Mar 2014 14:39:51 +0300
Subject: [PATCH 3/5] ubi: Fix for creating ubi volumes with 64bit size
In-Reply-To: <1394451593-3090-1-git-send-email-d.lavnikevich@sam-solutions.com>
References: <1394451593-3090-1-git-send-email-d.lavnikevich@sam-solutions.com>
Message-ID: <1394451593-3090-3-git-send-email-d.lavnikevich@sam-solutions.com>

Since MTD is already supports >= 4GB device sizes it is better to
allow ubi valumes also be created of larger sizes.

Signed-off-by: Dmitry Lavnikevich <d.lavnikevich at sam-solutions.com>
Signed-off-by: Grigory Milev <g.milev at sam-solutions.com>
---
 commands/ubi.c         | 4 ++--
 drivers/mtd/ubi/cdev.c | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/commands/ubi.c b/commands/ubi.c
index 57ae790..8a409c2 100644
--- a/commands/ubi.c
+++ b/commands/ubi.c
@@ -15,12 +15,12 @@ static int do_ubimkvol(int argc, char *argv[])
 {
 	struct ubi_mkvol_req req;
 	int fd, ret;
-	size_t size;
+	uint64_t size;
 
 	if (argc != 4)
 		return COMMAND_ERROR_USAGE;
 
-	size = strtoul_suffix(argv[3], NULL, 0);
+	size = strtoull_suffix(argv[3], NULL, 0);
 	req.name_len = min_t(int, strlen(argv[2]), UBI_VOL_NAME_MAX);
 	strncpy(req.name, argv[2], req.name_len);
 	req.name[req.name_len] = 0;
diff --git a/drivers/mtd/ubi/cdev.c b/drivers/mtd/ubi/cdev.c
index 129f2e2..b97739a 100644
--- a/drivers/mtd/ubi/cdev.c
+++ b/drivers/mtd/ubi/cdev.c
@@ -220,7 +220,7 @@ static int ubi_cdev_ioctl(struct cdev *cdev, int cmd, void *buf)
 		break;
 	case UBI_IOCMKVOL:
 		if (!req->bytes)
-			req->bytes = ubi->avail_pebs * ubi->leb_size;
+			req->bytes = (__s64)ubi->avail_pebs * ubi->leb_size;
 		return ubi_create_volume(ubi, req);
 	};
 
-- 
1.9.0



From d.lavnikevich at sam-solutions.com  Mon Mar 10 07:39:53 2014
From: d.lavnikevich at sam-solutions.com (Dmitry Lavnikevich)
Date: Mon, 10 Mar 2014 14:39:53 +0300
Subject: [PATCH 5/5] nand: mxs: Fix for calculating ecc strength on some types
 of NAND flash
In-Reply-To: <1394451593-3090-1-git-send-email-d.lavnikevich@sam-solutions.com>
References: <1394451593-3090-1-git-send-email-d.lavnikevich@sam-solutions.com>
Message-ID: <1394451593-3090-5-git-send-email-d.lavnikevich@sam-solutions.com>

Was tested on NAND with {writesize=4096, oobsize=224} and
{writesize=2048, oobsize=64}.

This patch will not break any NAND that was working
before. Implemented calculation way may be used for other NAND chips
with writesize == 2048 but oobsize != 64.

Signed-off-by: Dmitry Lavnikevich <d.lavnikevich at sam-solutions.com>
Signed-off-by: Grigory Milev <g.milev at sam-solutions.com>
---
 drivers/mtd/nand/nand_mxs.c | 21 +++++++++++++++++----
 1 file changed, 17 insertions(+), 4 deletions(-)

diff --git a/drivers/mtd/nand/nand_mxs.c b/drivers/mtd/nand/nand_mxs.c
index 237a423..b06b558 100644
--- a/drivers/mtd/nand/nand_mxs.c
+++ b/drivers/mtd/nand/nand_mxs.c
@@ -234,18 +234,31 @@ static uint32_t mxs_nand_aux_status_offset(void)
 static inline uint32_t mxs_nand_get_ecc_strength(uint32_t page_data_size,
 						uint32_t page_oob_size)
 {
+	int ecc_chunk_count = mxs_nand_ecc_chunk_cnt(page_data_size);
+	int ecc_strength = 0;
+	int gf_len = 13;  /* length of Galois Field for non-DDR nand */
+
+	/*
+	 * Possibly this if-else calculation may be removed since
+	 * ecc_strength calculated after it is taken from kernel driver
+	 * and therefore should work for all cases. But it was tested only
+	 * on devices with {data_size = 2046, oob_size = 64} and
+	 * {data_size = 4096, oob_size = 224} configuration.
+	 */
 	if (page_data_size == 2048)
 		return 8;
-
-	if (page_data_size == 4096) {
+	else if (page_data_size == 4096) {
 		if (page_oob_size == 128)
 			return 8;
-
 		if (page_oob_size == 218)
 			return 16;
 	}
 
-	return 0;
+	ecc_strength = ((page_oob_size - MXS_NAND_METADATA_SIZE) * 8)
+		/ (gf_len * ecc_chunk_count);
+
+	/* We need the minor even number. */
+	return rounddown(ecc_strength, 2);
 }
 
 static inline uint32_t mxs_nand_get_mark_offset(uint32_t page_data_size,
-- 
1.9.0



From d.lavnikevich at sam-solutions.com  Mon Mar 10 07:39:49 2014
From: d.lavnikevich at sam-solutions.com (Dmitry Lavnikevich)
Date: Mon, 10 Mar 2014 14:39:49 +0300
Subject: [PATCH 1/5] mtd: Update internal API to support 64-bit device size
Message-ID: <1394451593-3090-1-git-send-email-d.lavnikevich@sam-solutions.com>

MTD internal API presently uses 32-bit values to represent device
size. This patch updates them to 64-bits but leaves the external API
unchanged.

In general, changing from 32-bit to 64-bit values cause little
or no changes to the majority of the code with the following
exceptions:
  - printk message formats;
  - division and modulus of 64-bit values (mtd_div_by_wb,
    mtd_div_by_eb may be used in some of such cases).

Was tested on phyFLEX i.MX6.

Signed-off-by: Dmitry Lavnikevich <d.lavnikevich at sam-solutions.com>
Signed-off-by: Grigory Milev <g.milev at sam-solutions.com>
---
 commands/nandtest.c                 |  2 +-
 commands/partition.c                | 11 ++++++-----
 drivers/mtd/core.c                  |  2 +-
 drivers/mtd/devices/m25p80.c        |  5 +++--
 drivers/mtd/devices/mtd_dataflash.c |  2 +-
 drivers/mtd/mtdoob.c                |  2 +-
 drivers/mtd/mtdraw.c                |  2 +-
 include/linux/mtd/mtd-abi.h         | 12 +++++++++++-
 include/linux/mtd/mtd.h             |  9 ++++++++-
 lib/libmtd.c                        | 10 +++++-----
 10 files changed, 38 insertions(+), 19 deletions(-)

diff --git a/commands/nandtest.c b/commands/nandtest.c
index 0da5444..c64f244 100644
--- a/commands/nandtest.c
+++ b/commands/nandtest.c
@@ -277,7 +277,7 @@ static int do_nandtest(int argc, char *argv[])
 	}
 	if (length + flash_offset > meminfo.size) {
 		printf("Length 0x%08llx + offset 0x%08llx exceeds "
-				"device size 0x%08x\n", length,
+				"device size 0x%08llx\n", length,
 				flash_offset, meminfo.size);
 		goto err;
 	}
diff --git a/commands/partition.c b/commands/partition.c
index 6d37471..f825722 100644
--- a/commands/partition.c
+++ b/commands/partition.c
@@ -42,10 +42,11 @@
 #define PART_ADD_DEVNAME (1 << 0)
 
 static int mtd_part_do_parse_one(char *devname, const char *partstr,
-				 char **endp, unsigned long *offset,
-				 off_t devsize, size_t *retsize, unsigned int pflags)
+				 char **endp, loff_t *offset,
+				 loff_t devsize, size_t *retsize,
+				 unsigned int pflags)
 {
-	ulong size;
+	loff_t size;
 	char *end;
 	char buf[PATH_MAX] = {};
 	unsigned long flags = 0;
@@ -114,8 +115,8 @@ static int do_addpart(int argc, char *argv[])
 {
 	char *devname;
 	char *endp;
-	unsigned long offset = 0;
-	off_t devsize;
+	loff_t offset = 0;
+	loff_t devsize;
 	struct stat s;
 	int opt;
 	unsigned int flags = PART_ADD_DEVNAME;
diff --git a/drivers/mtd/core.c b/drivers/mtd/core.c
index 6db1c6d..7efb03c 100644
--- a/drivers/mtd/core.c
+++ b/drivers/mtd/core.c
@@ -397,7 +397,7 @@ int add_mtd_device(struct mtd_info *mtd, char *devname, int device_id)
 	mtd->cdev.mtd = mtd;
 
 	if (IS_ENABLED(CONFIG_PARAMETER)) {
-		dev_add_param_int_ro(&mtd->class_dev, "size", mtd->size, "%u");
+		dev_add_param_int_ro(&mtd->class_dev, "size", mtd->size, "%llu");
 		dev_add_param_int_ro(&mtd->class_dev, "erasesize", mtd->erasesize, "%u");
 		dev_add_param_int_ro(&mtd->class_dev, "writesize", mtd->oobsize, "%u");
 		dev_add_param_int_ro(&mtd->class_dev, "oobsize", mtd->oobsize, "%u");
diff --git a/drivers/mtd/devices/m25p80.c b/drivers/mtd/devices/m25p80.c
index 9594011..757a717 100644
--- a/drivers/mtd/devices/m25p80.c
+++ b/drivers/mtd/devices/m25p80.c
@@ -273,8 +273,9 @@ static int erase_sector(struct m25p *flash, u32 offset, u32 command)
 static int m25p80_erase(struct mtd_info *mtd, struct erase_info *instr)
 {
 	struct m25p *flash = mtd_to_m25p(mtd);
-	u32 addr, len;
+	u32 addr;
 	uint32_t rem;
+	uint64_t len;
 
 	dev_dbg(&flash->spi->dev, "%s at 0x%llx, len %lld\n",
 			__func__, (long long)instr->addr,
@@ -896,7 +897,7 @@ static int m25p_probe(struct device_d *dev)
 	flash->mtd.type = MTD_NORFLASH;
 	flash->mtd.writesize = 1;
 	flash->mtd.flags = MTD_CAP_NORFLASH;
-	flash->mtd.size = info->sector_size * info->n_sectors;
+	flash->mtd.size = (uint64_t)info->sector_size * info->n_sectors;
 	flash->mtd.erase = m25p80_erase;
 	flash->mtd.read = m25p80_read;
 
diff --git a/drivers/mtd/devices/mtd_dataflash.c b/drivers/mtd/devices/mtd_dataflash.c
index cdc0120..fa31b61 100644
--- a/drivers/mtd/devices/mtd_dataflash.c
+++ b/drivers/mtd/devices/mtd_dataflash.c
@@ -625,7 +625,7 @@ add_dataflash_otp(struct spi_device *spi, char *name,
 
 	device = &priv->mtd;
 	device->name = (pdata && pdata->name) ? pdata->name : "dataflash";
-	device->size = nr_pages * pagesize;
+	device->size = nr_pages * (uint64_t)pagesize;
 	device->erasesize = pagesize;
 	device->writesize = pagesize;
 	device->type = MTD_DATAFLASH;
diff --git a/drivers/mtd/mtdoob.c b/drivers/mtd/mtdoob.c
index 1e88b53..54888cd 100644
--- a/drivers/mtd/mtdoob.c
+++ b/drivers/mtd/mtdoob.c
@@ -78,7 +78,7 @@ static int add_mtdoob_device(struct mtd_info *mtd, char *devname, void **priv)
 
 	mtdoob = xzalloc(sizeof(*mtdoob));
 	mtdoob->cdev.ops = &mtd_ops_oob;
-	mtdoob->cdev.size = (mtd->size / mtd->writesize) * mtd->oobsize;
+	mtdoob->cdev.size = mtd_div_by_wb(mtd->size, mtd) * mtd->oobsize;
 	mtdoob->cdev.name = asprintf("%s_oob%d", devname, mtd->class_dev.id);
 	mtdoob->cdev.priv = mtdoob;
 	mtdoob->cdev.dev = &mtd->class_dev;
diff --git a/drivers/mtd/mtdraw.c b/drivers/mtd/mtdraw.c
index be34723..33ca05d 100644
--- a/drivers/mtd/mtdraw.c
+++ b/drivers/mtd/mtdraw.c
@@ -290,7 +290,7 @@ static int add_mtdraw_device(struct mtd_info *mtd, char *devname, void **priv)
 	mtdraw->mtd = mtd;
 
 	mtdraw->cdev.ops = (struct file_operations *)&mtd_raw_fops;
-	mtdraw->cdev.size = mtd->size / mtd->writesize *
+	mtdraw->cdev.size = mtd_div_by_wb(mtd->size, mtd) *
 		(mtd->writesize + mtd->oobsize);
 	mtdraw->cdev.name = asprintf("%s.raw", mtd->cdev.name);
 	mtdraw->cdev.priv = mtdraw;
diff --git a/include/linux/mtd/mtd-abi.h b/include/linux/mtd/mtd-abi.h
index 11d51e2..c1ba55b 100644
--- a/include/linux/mtd/mtd-abi.h
+++ b/include/linux/mtd/mtd-abi.h
@@ -9,6 +9,8 @@
 
 #ifndef DOXYGEN_SHOULD_SKIP_THIS
 
+#include <asm-generic/div64.h>
+
 struct erase_info_user {
 	uint32_t start;
 	uint32_t length;
@@ -73,7 +75,7 @@ enum {
 struct mtd_info_user {
 	uint8_t type;
 	uint32_t flags;
-	uint32_t size;	 // Total size of the MTD
+	uint64_t size;	 /* Total size of the MTD */
 	uint32_t erasesize;
 	uint32_t writesize;
 	uint32_t oobsize;   // Amount of OOB data per block (e.g. 16)
@@ -173,6 +175,14 @@ enum mtd_file_modes {
 	MTD_MODE_RAW,
 };
 
+
+static inline uint32_t mtd_user_div_by_eb(uint64_t sz,
+	struct mtd_info_user *mtd_user)
+{
+	do_div(sz, mtd_user->erasesize);
+	return sz;
+}
+
 #endif /* DOXYGEN_SHOULD_SKIP_THIS */
 
 #endif /* __MTD_ABI_H__ */
diff --git a/include/linux/mtd/mtd.h b/include/linux/mtd/mtd.h
index 402e497..d337455 100644
--- a/include/linux/mtd/mtd.h
+++ b/include/linux/mtd/mtd.h
@@ -86,7 +86,7 @@ struct mtd_oob_ops {
 struct mtd_info {
 	u_char type;
 	u_int32_t flags;
-	u_int32_t size;	 // Total size of the MTD
+	u_int64_t size;	 /* Total size of the MTD */
 
 	/* "Major" erase size for the device. Na?ve users may take this
 	 * to be the only erase size available, or may use the more detailed
@@ -253,6 +253,13 @@ static inline uint32_t mtd_mod_by_eb(uint64_t sz, struct mtd_info *mtd)
 {
 	return do_div(sz, mtd->erasesize);
 }
+
+static inline uint32_t mtd_div_by_wb(uint64_t sz, struct mtd_info *mtd)
+{
+	do_div(sz, mtd->writesize);
+	return sz;
+}
+
 	/* Kernel-side ioctl definitions */
 
 extern int add_mtd_device(struct mtd_info *mtd, char *devname, int device_id);
diff --git a/lib/libmtd.c b/lib/libmtd.c
index 1606b87..56672bd 100644
--- a/lib/libmtd.c
+++ b/lib/libmtd.c
@@ -195,7 +195,7 @@ int libmtd_read(const struct mtd_dev_info *mtd, int fd, int eb, int offs,
 	     void *buf, int len)
 {
 	int ret, rd = 0;
-	off_t seek;
+	loff_t seek;
 
 	ret = mtd_valid_erase_block(mtd, eb);
 	if (ret)
@@ -209,7 +209,7 @@ int libmtd_read(const struct mtd_dev_info *mtd, int fd, int eb, int offs,
 	}
 
 	/* Seek to the beginning of the eraseblock */
-	seek = (off_t)eb * mtd->eb_size + offs;
+	seek = (loff_t)eb * mtd->eb_size + offs;
 	if (lseek(fd, seek, SEEK_SET) != seek)
 		return sys_errmsg("cannot seek %s to offset %llu",
 				  mtd->node, (unsigned long long)seek);
@@ -229,7 +229,7 @@ int libmtd_write(const struct mtd_dev_info *mtd, int fd, int eb, int offs,
 	      void *buf, int len)
 {
 	int ret;
-	off_t seek;
+	loff_t seek;
 
 	ret = mtd_valid_erase_block(mtd, eb);
 	if (ret)
@@ -255,7 +255,7 @@ int libmtd_write(const struct mtd_dev_info *mtd, int fd, int eb, int offs,
 	}
 
 	/* Seek to the beginning of the eraseblock */
-	seek = (off_t)eb * mtd->eb_size + offs;
+	seek = (loff_t)eb * mtd->eb_size + offs;
 	if (lseek(fd, seek, SEEK_SET) != seek)
 		return sys_errmsg("cannot seek %s to offset %llu",
 				  mtd->node, (unsigned long long)seek);
@@ -326,7 +326,7 @@ int mtd_get_dev_info(const char *node, struct mtd_dev_info *mtd)
 		goto out_close;
 	}
 
-	mtd->eb_cnt = ui.size / ui.erasesize;
+	mtd->eb_cnt = mtd_user_div_by_eb(ui.size, &ui);
 
 	switch(mtd->type) {
 	case MTD_ABSENT:
-- 
1.9.0



From antonynpavlov at gmail.com  Mon Mar 10 17:34:33 2014
From: antonynpavlov at gmail.com (Antony Pavlov)
Date: Tue, 11 Mar 2014 01:34:33 +0400
Subject: [PATCH 0/8] ARM: initial support for TI DaVinci SoCs and virt2real
 board
Message-ID: <1394487281-10462-1-git-send-email-antonynpavlov@gmail.com>

Antony Pavlov (8):
  clocksource: add dummy software-only clocksource
  import _AC and UL macros from linux kernel
  ARM: initial support for TI DaVinci SoCs
  ARM: davinci: add DEBUG_LL support
  ARM: davinci: add documentation
  ARM: davinci: add virt2real board support
  ARM: virt2real: add documentation
  ARM: davinci: add virt2real_defconfig

 Documentation/boards.dox                      |  1 +
 arch/arm/Kconfig                              |  6 ++
 arch/arm/Makefile                             |  1 +
 arch/arm/boards/Makefile                      |  1 +
 arch/arm/boards/virt2real/Makefile            |  1 +
 arch/arm/boards/virt2real/board.c             | 49 ++++++++++++++
 arch/arm/boards/virt2real/lowlevel.c          | 34 ++++++++++
 arch/arm/boards/virt2real/virt2real.dox       | 41 ++++++++++++
 arch/arm/configs/virt2real_defconfig          | 39 +++++++++++
 arch/arm/include/asm/memory.h                 |  7 ++
 arch/arm/mach-arm.dox                         |  2 +
 arch/arm/mach-davinci/Kconfig                 | 16 +++++
 arch/arm/mach-davinci/Makefile                |  1 +
 arch/arm/mach-davinci/include/mach/debug_ll.h | 42 ++++++++++++
 arch/arm/mach-davinci/include/mach/hardware.h | 29 ++++++++
 arch/arm/mach-davinci/include/mach/serial.h   | 20 ++++++
 arch/arm/mach-davinci/include/mach/time.h     | 18 +++++
 arch/arm/mach-davinci/mach-davinci.dox        |  7 ++
 arch/arm/mach-davinci/time.c                  | 95 +++++++++++++++++++++++++++
 drivers/clocksource/Kconfig                   |  9 +++
 drivers/clocksource/Makefile                  |  1 +
 drivers/clocksource/dummy.c                   | 56 ++++++++++++++++
 include/linux/const.h                         | 27 ++++++++
 23 files changed, 503 insertions(+)
 create mode 100644 arch/arm/boards/virt2real/Makefile
 create mode 100644 arch/arm/boards/virt2real/board.c
 create mode 100644 arch/arm/boards/virt2real/lowlevel.c
 create mode 100644 arch/arm/boards/virt2real/virt2real.dox
 create mode 100644 arch/arm/configs/virt2real_defconfig
 create mode 100644 arch/arm/mach-davinci/Kconfig
 create mode 100644 arch/arm/mach-davinci/Makefile
 create mode 100644 arch/arm/mach-davinci/include/mach/debug_ll.h
 create mode 100644 arch/arm/mach-davinci/include/mach/hardware.h
 create mode 100644 arch/arm/mach-davinci/include/mach/serial.h
 create mode 100644 arch/arm/mach-davinci/include/mach/time.h
 create mode 100644 arch/arm/mach-davinci/mach-davinci.dox
 create mode 100644 arch/arm/mach-davinci/time.c
 create mode 100644 drivers/clocksource/dummy.c
 create mode 100644 include/linux/const.h

-- 
1.9.0



From antonynpavlov at gmail.com  Mon Mar 10 17:34:35 2014
From: antonynpavlov at gmail.com (Antony Pavlov)
Date: Tue, 11 Mar 2014 01:34:35 +0400
Subject: [PATCH 2/8] import _AC and UL macros from linux kernel
In-Reply-To: <1394487281-10462-1-git-send-email-antonynpavlov@gmail.com>
References: <1394487281-10462-1-git-send-email-antonynpavlov@gmail.com>
Message-ID: <1394487281-10462-3-git-send-email-antonynpavlov@gmail.com>

This macros are used in exported from linux TI DaVinci code.
Also this macros are used in MIPS cache support code.

Signed-off-by: Antony Pavlov <antonynpavlov at gmail.com>
---
 arch/arm/include/asm/memory.h |  7 +++++++
 include/linux/const.h         | 27 +++++++++++++++++++++++++++
 2 files changed, 34 insertions(+)

diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h
index 28afaa3..52114d0 100644
--- a/arch/arm/include/asm/memory.h
+++ b/arch/arm/include/asm/memory.h
@@ -3,6 +3,13 @@
 
 #include <memory.h>
 
+#include <linux/const.h>
+/*
+ * Allow for constants defined here to be used from assembly code
+ * by prepending the UL suffix only with actual C code compilation.
+ */
+#define UL(x) _AC(x, UL)
+
 static inline void arm_add_mem_device(const char* name, resource_size_t start,
 				    resource_size_t size)
 {
diff --git a/include/linux/const.h b/include/linux/const.h
new file mode 100644
index 0000000..c872bfd
--- /dev/null
+++ b/include/linux/const.h
@@ -0,0 +1,27 @@
+/* const.h: Macros for dealing with constants.  */
+
+#ifndef _LINUX_CONST_H
+#define _LINUX_CONST_H
+
+/* Some constant macros are used in both assembler and
+ * C code.  Therefore we cannot annotate them always with
+ * 'UL' and other type specifiers unilaterally.  We
+ * use the following macros to deal with this.
+ *
+ * Similarly, _AT() will cast an expression with a type in C, but
+ * leave it unchanged in asm.
+ */
+
+#ifdef __ASSEMBLY__
+#define _AC(X,Y)	X
+#define _AT(T,X)	X
+#else
+#define __AC(X,Y)	(X##Y)
+#define _AC(X,Y)	__AC(X,Y)
+#define _AT(T,X)	((T)(X))
+#endif
+
+#define _BITUL(x)	(_AC(1,UL) << (x))
+#define _BITULL(x)	(_AC(1,ULL) << (x))
+
+#endif /* !(_LINUX_CONST_H) */
-- 
1.9.0



From antonynpavlov at gmail.com  Mon Mar 10 17:34:34 2014
From: antonynpavlov at gmail.com (Antony Pavlov)
Date: Tue, 11 Mar 2014 01:34:34 +0400
Subject: [PATCH 1/8] clocksource: add dummy software-only clocksource
In-Reply-To: <1394487281-10462-1-git-send-email-antonynpavlov@gmail.com>
References: <1394487281-10462-1-git-send-email-antonynpavlov@gmail.com>
Message-ID: <1394487281-10462-2-git-send-email-antonynpavlov@gmail.com>

This driver is very handy for initial barebox porting.
It was used for running barebox on DiGiC2-based camera
and initial porting barebox to Loongson-1 and ar9331.

Signed-off-by: Antony Pavlov <antonynpavlov at gmail.com>
Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
Reported-by: Alexander Aring <alex.aring at gmail.com>
Reported-by: Alexander Shiyan <shc_work at mail.ru>
---
 drivers/clocksource/Kconfig  |  9 +++++++
 drivers/clocksource/Makefile |  1 +
 drivers/clocksource/dummy.c  | 56 ++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 66 insertions(+)

diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index 4ef25ec..f9e00ff 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -14,6 +14,15 @@ config CLOCKSOURCE_CLPS711X
 	bool
 	depends on ARCH_CLPS711X
 
+config CLOCKSOURCE_DUMMY
+	bool "Enable dummy software-only clocksource"
+	default n
+
+config CLOCKSOURCE_DUMMY_RATE
+	int "compile loglevel"
+	depends on CLOCKSOURCE_DUMMY
+	default 1000
+
 config CLOCKSOURCE_MVEBU
 	bool
 	depends on ARCH_MVEBU
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index 25b7f46..834a15d 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -2,6 +2,7 @@ obj-$(CONFIG_AMBA_SP804) += amba-sp804.o
 obj-$(CONFIG_ARM_SMP_TWD) += arm_smp_twd.o
 obj-$(CONFIG_CLOCKSOURCE_BCM2835) += bcm2835.o
 obj-$(CONFIG_CLOCKSOURCE_CLPS711X) += clps711x.o
+obj-$(CONFIG_CLOCKSOURCE_DUMMY)   += dummy.o
 obj-$(CONFIG_CLOCKSOURCE_MVEBU)   += mvebu.o
 obj-$(CONFIG_CLOCKSOURCE_NOMADIK) += nomadik.o
 obj-$(CONFIG_CLOCKSOURCE_ORION)   += orion.o
diff --git a/drivers/clocksource/dummy.c b/drivers/clocksource/dummy.c
new file mode 100644
index 0000000..154a8cd
--- /dev/null
+++ b/drivers/clocksource/dummy.c
@@ -0,0 +1,56 @@
+/*
+ * Copyright (C) 2013 Antony Pavlov <antonynpavlov at gmail.com>
+ *
+ * This file is part of barebox.
+ * See file CREDITS for list of people who contributed to this project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <common.h>
+#include <init.h>
+#include <clock.h>
+
+static uint64_t dummy_counter;
+
+static uint64_t dummy_cs_read(void)
+{
+	static int first;
+
+	if (!first) {
+		pr_warn("Warning: Using dummy clocksource\n");
+		first = 1;
+	}
+
+	dummy_counter += CONFIG_CLOCKSOURCE_DUMMY_RATE;
+
+	return dummy_counter;
+}
+
+static struct clocksource dummy_cs = {
+	.read	= dummy_cs_read,
+	.mask   = CLOCKSOURCE_MASK(32),
+};
+
+static int clocksource_init(void)
+{
+	dummy_counter = 0;
+
+	clocks_calc_mult_shift(&dummy_cs.mult, &dummy_cs.shift,
+		100000000, NSEC_PER_SEC, 10);
+
+	pr_debug("clocksource_init: mult=%08x, shift=%08x\n",
+			dummy_cs.mult, dummy_cs.shift);
+	init_clock(&dummy_cs);
+
+	return 0;
+}
+pure_initcall(clocksource_init);
-- 
1.9.0



From antonynpavlov at gmail.com  Mon Mar 10 17:34:37 2014
From: antonynpavlov at gmail.com (Antony Pavlov)
Date: Tue, 11 Mar 2014 01:34:37 +0400
Subject: [PATCH 4/8] ARM: davinci: add DEBUG_LL support
In-Reply-To: <1394487281-10462-1-git-send-email-antonynpavlov@gmail.com>
References: <1394487281-10462-1-git-send-email-antonynpavlov@gmail.com>
Message-ID: <1394487281-10462-5-git-send-email-antonynpavlov@gmail.com>

Signed-off-by: Antony Pavlov <antonynpavlov at gmail.com>
---
 arch/arm/Kconfig                              |  1 +
 arch/arm/mach-davinci/include/mach/debug_ll.h | 42 +++++++++++++++++++++++++++
 2 files changed, 43 insertions(+)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 42ff01b..407f27d 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -57,6 +57,7 @@ config ARCH_CLPS711X
 config ARCH_DAVINCI
 	bool "TI Davinci"
 	select CPU_ARM926T
+	select HAS_DEBUG_LL
 
 config ARCH_EP93XX
 	bool "Cirrus Logic EP93xx"
diff --git a/arch/arm/mach-davinci/include/mach/debug_ll.h b/arch/arm/mach-davinci/include/mach/debug_ll.h
new file mode 100644
index 0000000..587f408
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/debug_ll.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright (C) 2014 Antony Pavlov <antonynpavlov at gmail.com>
+ *
+ * This file is part of barebox.
+ * See file CREDITS for list of people who contributed to this project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+/** @file
+ *  This File contains declaration for early output support
+ */
+#ifndef __INCLUDE_ARCH_DEBUG_LL_H__
+#define __INCLUDE_ARCH_DEBUG_LL_H__
+
+#include <asm/io.h>
+#include <mach/serial.h>
+
+#define DEBUG_LL_UART_ADDR	DAVINCI_UART0_BASE
+#define DEBUG_LL_UART_RSHFT	2
+
+#define rbr		(0 << DEBUG_LL_UART_RSHFT)
+#define lsr		(5 << DEBUG_LL_UART_RSHFT)
+#define LSR_THRE	0x20	/* Xmit holding register empty */
+
+static inline void PUTC_LL(char ch)
+{
+	while (!(__raw_readb(DEBUG_LL_UART_ADDR + lsr) & LSR_THRE))
+		;
+
+	__raw_writeb(ch, DEBUG_LL_UART_ADDR + rbr);
+}
+
+#endif /* __INCLUDE_ARCH_DEBUG_LL_H__ */
-- 
1.9.0



From antonynpavlov at gmail.com  Mon Mar 10 17:34:36 2014
From: antonynpavlov at gmail.com (Antony Pavlov)
Date: Tue, 11 Mar 2014 01:34:36 +0400
Subject: [PATCH 3/8] ARM: initial support for TI DaVinci SoCs
In-Reply-To: <1394487281-10462-1-git-send-email-antonynpavlov@gmail.com>
References: <1394487281-10462-1-git-send-email-antonynpavlov@gmail.com>
Message-ID: <1394487281-10462-4-git-send-email-antonynpavlov@gmail.com>

This commit adds minimal support for the DaVinci DM365 SoCs
from Texas Instruments.

Signed-off-by: Antony Pavlov <antonynpavlov at gmail.com>
---
 arch/arm/Kconfig                              |  5 ++
 arch/arm/Makefile                             |  1 +
 arch/arm/mach-davinci/Kconfig                 |  7 ++
 arch/arm/mach-davinci/Makefile                |  1 +
 arch/arm/mach-davinci/include/mach/hardware.h | 29 ++++++++
 arch/arm/mach-davinci/include/mach/serial.h   | 20 ++++++
 arch/arm/mach-davinci/include/mach/time.h     | 18 +++++
 arch/arm/mach-davinci/time.c                  | 95 +++++++++++++++++++++++++++
 8 files changed, 176 insertions(+)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 21f9012..42ff01b 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -54,6 +54,10 @@ config ARCH_CLPS711X
 	select GPIOLIB
 	select MFD_SYSCON
 
+config ARCH_DAVINCI
+	bool "TI Davinci"
+	select CPU_ARM926T
+
 config ARCH_EP93XX
 	bool "Cirrus Logic EP93xx"
 	select CPU_ARM920T
@@ -188,6 +192,7 @@ source arch/arm/cpu/Kconfig
 source arch/arm/mach-at91/Kconfig
 source arch/arm/mach-bcm2835/Kconfig
 source arch/arm/mach-clps711x/Kconfig
+source arch/arm/mach-davinci/Kconfig
 source arch/arm/mach-ep93xx/Kconfig
 source arch/arm/mach-highbank/Kconfig
 source arch/arm/mach-imx/Kconfig
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 2bbba35..c1bd836 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -54,6 +54,7 @@ AFLAGS   += -include asm/unified.h -msoft-float $(AFLAGS_THUMB2)
 machine-$(CONFIG_ARCH_AT91)		:= at91
 machine-$(CONFIG_ARCH_BCM2835)		:= bcm2835
 machine-$(CONFIG_ARCH_CLPS711X)		:= clps711x
+machine-$(CONFIG_ARCH_DAVINCI)		:= davinci
 machine-$(CONFIG_ARCH_EP93XX)		:= ep93xx
 machine-$(CONFIG_ARCH_HIGHBANK)		:= highbank
 machine-$(CONFIG_ARCH_IMX)		:= imx
diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig
new file mode 100644
index 0000000..5677f8d
--- /dev/null
+++ b/arch/arm/mach-davinci/Kconfig
@@ -0,0 +1,7 @@
+if ARCH_DAVINCI
+
+config ARCH_TEXT_BASE
+	hex
+	default 0x82000000
+
+endif
diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile
new file mode 100644
index 0000000..b96d414
--- /dev/null
+++ b/arch/arm/mach-davinci/Makefile
@@ -0,0 +1 @@
+obj-y += time.o
diff --git a/arch/arm/mach-davinci/include/mach/hardware.h b/arch/arm/mach-davinci/include/mach/hardware.h
new file mode 100644
index 0000000..ea9f481
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/hardware.h
@@ -0,0 +1,29 @@
+/*
+ * Hardware definitions common to all DaVinci family processors
+ *
+ * Author: Kevin Hilman, Deep Root Systems, LLC
+ *
+ * 2007 (c) Deep Root Systems, LLC. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#include <asm/memory.h>
+
+/*
+ * Before you add anything to this file:
+ *
+ * This header is for defines common to ALL DaVinci family chips.
+ * Anything that is chip specific should go in <chipname>.h,
+ * and the chip/board init code should then explicitly include
+ * <chipname>.h
+ */
+/*
+ * I/O mapping
+ */
+#define IO_PHYS				UL(0x01c00000)
+
+#endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/mach-davinci/include/mach/serial.h b/arch/arm/mach-davinci/include/mach/serial.h
new file mode 100644
index 0000000..bc7449f
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/serial.h
@@ -0,0 +1,20 @@
+/*
+ * DaVinci serial device definitions
+ *
+ * Author: Kevin Hilman, MontaVista Software, Inc. <source at mvista.com>
+ *
+ * 2007 (c) MontaVista Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+#ifndef __ASM_ARCH_SERIAL_H
+#define __ASM_ARCH_SERIAL_H
+
+#include <mach/hardware.h>
+
+#define DAVINCI_UART0_BASE	(IO_PHYS + 0x20000)
+#define DAVINCI_UART1_BASE	(IO_PHYS + 0x20400)
+#define DAVINCI_UART2_BASE	(IO_PHYS + 0x20800)
+
+#endif /* __ASM_ARCH_SERIAL_H */
diff --git a/arch/arm/mach-davinci/include/mach/time.h b/arch/arm/mach-davinci/include/mach/time.h
new file mode 100644
index 0000000..741e90c
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/time.h
@@ -0,0 +1,18 @@
+/*
+ * Local header file for DaVinci time code.
+ *
+ * Author: Kevin Hilman, MontaVista Software, Inc. <source at mvista.com>
+ *
+ * 2007 (c) MontaVista Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+#ifndef __ARCH_ARM_MACH_DAVINCI_TIME_H
+#define __ARCH_ARM_MACH_DAVINCI_TIME_H
+
+#include <mach/hardware.h>
+
+#define DAVINCI_WDOG_BASE		(IO_PHYS + 0x21C00)
+
+#endif /* __ARCH_ARM_MACH_DAVINCI_TIME_H */
diff --git a/arch/arm/mach-davinci/time.c b/arch/arm/mach-davinci/time.c
new file mode 100644
index 0000000..1e00719
--- /dev/null
+++ b/arch/arm/mach-davinci/time.c
@@ -0,0 +1,95 @@
+/*
+ * DaVinci timer subsystem
+ *
+ * Author: Kevin Hilman, MontaVista Software, Inc. <source at mvista.com>
+ *
+ * 2007 (c) MontaVista Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+
+#include <common.h>
+#include <io.h>
+
+#include <mach/time.h>
+
+/* Timer register offsets */
+#define PID12			0x0
+#define TIM12			0x10
+#define TIM34			0x14
+#define PRD12			0x18
+#define PRD34			0x1c
+#define TCR			0x20
+#define TGCR			0x24
+#define WDTCR			0x28
+
+/* Timer register bitfields */
+#define TCR_ENAMODE_DISABLE          0x0
+#define TCR_ENAMODE_ONESHOT          0x1
+#define TCR_ENAMODE_PERIODIC         0x2
+#define TCR_ENAMODE_MASK             0x3
+
+#define TGCR_TIMMODE_SHIFT           2
+#define TGCR_TIMMODE_64BIT_GP        0x0
+#define TGCR_TIMMODE_32BIT_UNCHAINED 0x1
+#define TGCR_TIMMODE_64BIT_WDOG      0x2
+#define TGCR_TIMMODE_32BIT_CHAINED   0x3
+
+#define TGCR_TIM12RS_SHIFT           0
+#define TGCR_TIM34RS_SHIFT           1
+#define TGCR_RESET                   0x0
+#define TGCR_UNRESET                 0x1
+#define TGCR_RESET_MASK              0x3
+
+#define WDTCR_WDEN_SHIFT             14
+#define WDTCR_WDEN_DISABLE           0x0
+#define WDTCR_WDEN_ENABLE            0x1
+#define WDTCR_WDKEY_SHIFT            16
+#define WDTCR_WDKEY_SEQ0             0xa5c6
+#define WDTCR_WDKEY_SEQ1             0xda7e
+
+/* reset board using watchdog timer */
+void __noreturn reset_cpu(ulong addr)
+{
+	u32 tgcr, wdtcr;
+	void __iomem *base;
+
+	base = IOMEM(DAVINCI_WDOG_BASE);
+
+	/* disable, internal clock source */
+	__raw_writel(0, base + TCR);
+
+	/* reset timer, set mode to 64-bit watchdog, and unreset */
+	tgcr = 0;
+	__raw_writel(tgcr, base + TGCR);
+	tgcr = TGCR_TIMMODE_64BIT_WDOG << TGCR_TIMMODE_SHIFT;
+	tgcr |= (TGCR_UNRESET << TGCR_TIM12RS_SHIFT) |
+		(TGCR_UNRESET << TGCR_TIM34RS_SHIFT);
+	__raw_writel(tgcr, base + TGCR);
+
+	/* clear counter and period regs */
+	__raw_writel(0, base + TIM12);
+	__raw_writel(0, base + TIM34);
+	__raw_writel(0, base + PRD12);
+	__raw_writel(0, base + PRD34);
+
+	/* put watchdog in pre-active state */
+	wdtcr = __raw_readl(base + WDTCR);
+	wdtcr = (WDTCR_WDKEY_SEQ0 << WDTCR_WDKEY_SHIFT) |
+		(WDTCR_WDEN_ENABLE << WDTCR_WDEN_SHIFT);
+	__raw_writel(wdtcr, base + WDTCR);
+
+	/* put watchdog in active state */
+	wdtcr = (WDTCR_WDKEY_SEQ1 << WDTCR_WDKEY_SHIFT) |
+		(WDTCR_WDEN_ENABLE << WDTCR_WDEN_SHIFT);
+	__raw_writel(wdtcr, base + WDTCR);
+
+	/* write an invalid value to the WDKEY field to trigger
+	 * a watchdog reset */
+	wdtcr = 0x00004000;
+	__raw_writel(wdtcr, base + WDTCR);
+
+	unreachable();
+}
+EXPORT_SYMBOL(reset_cpu);
-- 
1.9.0



From antonynpavlov at gmail.com  Mon Mar 10 17:34:38 2014
From: antonynpavlov at gmail.com (Antony Pavlov)
Date: Tue, 11 Mar 2014 01:34:38 +0400
Subject: [PATCH 5/8] ARM: davinci: add documentation
In-Reply-To: <1394487281-10462-1-git-send-email-antonynpavlov@gmail.com>
References: <1394487281-10462-1-git-send-email-antonynpavlov@gmail.com>
Message-ID: <1394487281-10462-6-git-send-email-antonynpavlov@gmail.com>

Signed-off-by: Antony Pavlov <antonynpavlov at gmail.com>
---
 arch/arm/mach-arm.dox                  | 2 ++
 arch/arm/mach-davinci/mach-davinci.dox | 5 +++++
 2 files changed, 7 insertions(+)

diff --git a/arch/arm/mach-arm.dox b/arch/arm/mach-arm.dox
index 758df3f..1d2de48 100644
--- a/arch/arm/mach-arm.dox
+++ b/arch/arm/mach-arm.dox
@@ -54,6 +54,8 @@ For details on specific architectures:
 
 @subsection mach_arm_omap_info OMAP CPUs
 
+ at li @subpage dev_davinci_arch
+
 @li @subpage dev_omap_arch
 
 @subsection mach_arm_s3c24xx_info S3C24XX CPUs
diff --git a/arch/arm/mach-davinci/mach-davinci.dox b/arch/arm/mach-davinci/mach-davinci.dox
new file mode 100644
index 0000000..f0f3a92
--- /dev/null
+++ b/arch/arm/mach-davinci/mach-davinci.dox
@@ -0,0 +1,5 @@
+/** @page dev_davinci_arch TI DaVinci in barebox
+
+ at section davinci_boards DaVinci-based boards
+
+*/
-- 
1.9.0



From antonynpavlov at gmail.com  Mon Mar 10 17:34:40 2014
From: antonynpavlov at gmail.com (Antony Pavlov)
Date: Tue, 11 Mar 2014 01:34:40 +0400
Subject: [PATCH 7/8] ARM: virt2real: add documentation
In-Reply-To: <1394487281-10462-1-git-send-email-antonynpavlov@gmail.com>
References: <1394487281-10462-1-git-send-email-antonynpavlov@gmail.com>
Message-ID: <1394487281-10462-8-git-send-email-antonynpavlov@gmail.com>

Signed-off-by: Antony Pavlov <antonynpavlov at gmail.com>
---
 Documentation/boards.dox                |  1 +
 arch/arm/boards/virt2real/virt2real.dox | 41 +++++++++++++++++++++++++++++++++
 arch/arm/mach-davinci/mach-davinci.dox  |  2 ++
 3 files changed, 44 insertions(+)

diff --git a/Documentation/boards.dox b/Documentation/boards.dox
index 6bcc14f..9a14aee 100644
--- a/Documentation/boards.dox
+++ b/Documentation/boards.dox
@@ -43,6 +43,7 @@ ARM type:
 @li @subpage tny-a9263
 @li @subpage usb-a9g20-lpw
 @li @subpage usb-a9263
+ at li @subpage virt2real
 
 Blackfin type:
 
diff --git a/arch/arm/boards/virt2real/virt2real.dox b/arch/arm/boards/virt2real/virt2real.dox
new file mode 100644
index 0000000..fc38321
--- /dev/null
+++ b/arch/arm/boards/virt2real/virt2real.dox
@@ -0,0 +1,41 @@
+/** @page virt2real virt2real board
+
+virt2real is a is a miniature board for creation of WiFi
+or internet controllable smart devices.
+
+The board has
+ at li TI DaVinchi DM365 running at 300 MHz
+ at li 128 MiB DDR2 SDRAM;
+ at li 256 MiB NAND Flash Memory;
+ at li 2 x UART serial interfaces;
+ at li 2 x Ethernet interfaces;
+ at li 1 x USB interface;
+ at li microSD card slot.
+
+The board uses U-Boot as bootloader.
+
+Barebox mini-howto:
+
+1. Connect to the boards's UART0 (115200 8N1);
+Use J2.2 (GND), J2.4 (UART0_TXD), J2.6(UART0_RXD) pins.
+
+2. Turn board's power on;
+
+3. Wait 'Hit any key to stop autoboot' prompt and press the space key.
+
+4. Upload barebox.bin via Ymodem
+ at verbatim
+    virt2real ># loady
+ at endverbatim
+
+5. Run barebox
+ at verbatim
+    virt2real ># go 0x82000000
+ at endverbatim
+
+virt2real links:
+ at li http://virt2real.com/
+ at li http://wiki.virt2real.ru/
+ at li https://github.com/virt2real
+
+*/
diff --git a/arch/arm/mach-davinci/mach-davinci.dox b/arch/arm/mach-davinci/mach-davinci.dox
index f0f3a92..789eacc 100644
--- a/arch/arm/mach-davinci/mach-davinci.dox
+++ b/arch/arm/mach-davinci/mach-davinci.dox
@@ -2,4 +2,6 @@
 
 @section davinci_boards DaVinci-based boards
 
+ at li @subpage virt2real
+
 */
-- 
1.9.0



From antonynpavlov at gmail.com  Mon Mar 10 17:34:39 2014
From: antonynpavlov at gmail.com (Antony Pavlov)
Date: Tue, 11 Mar 2014 01:34:39 +0400
Subject: [PATCH 6/8] ARM: davinci: add virt2real board support
In-Reply-To: <1394487281-10462-1-git-send-email-antonynpavlov@gmail.com>
References: <1394487281-10462-1-git-send-email-antonynpavlov@gmail.com>
Message-ID: <1394487281-10462-7-git-send-email-antonynpavlov@gmail.com>

The virt2real microcontroller, or virturilka,
is a miniature board for creation of WiFi
or internet controllable smart devices.

See http://virt2real.com for details.

Signed-off-by: Antony Pavlov <antonynpavlov at gmail.com>
---
 arch/arm/boards/Makefile             |  1 +
 arch/arm/boards/virt2real/Makefile   |  1 +
 arch/arm/boards/virt2real/board.c    | 49 ++++++++++++++++++++++++++++++++++++
 arch/arm/boards/virt2real/lowlevel.c | 34 +++++++++++++++++++++++++
 arch/arm/mach-davinci/Kconfig        |  9 +++++++
 5 files changed, 94 insertions(+)

diff --git a/arch/arm/boards/Makefile b/arch/arm/boards/Makefile
index ffd6bb3..fdad359 100644
--- a/arch/arm/boards/Makefile
+++ b/arch/arm/boards/Makefile
@@ -98,4 +98,5 @@ obj-$(CONFIG_MACH_USB_A9263)			+= usb-a926x/
 obj-$(CONFIG_MACH_USB_A9G20)			+= usb-a926x/
 obj-$(CONFIG_MACH_VERSATILEPB)			+= versatile/
 obj-$(CONFIG_MACH_VEXPRESS)			+= vexpress/
+obj-$(CONFIG_MACH_VIRT2REAL)			+= virt2real/
 obj-$(CONFIG_MACH_ZEDBOARD)			+= avnet-zedboard/
diff --git a/arch/arm/boards/virt2real/Makefile b/arch/arm/boards/virt2real/Makefile
new file mode 100644
index 0000000..b2f44bb
--- /dev/null
+++ b/arch/arm/boards/virt2real/Makefile
@@ -0,0 +1 @@
+obj-y += lowlevel.o board.o
diff --git a/arch/arm/boards/virt2real/board.c b/arch/arm/boards/virt2real/board.c
new file mode 100644
index 0000000..da4b2fb
--- /dev/null
+++ b/arch/arm/boards/virt2real/board.c
@@ -0,0 +1,49 @@
+/*
+ * Copyright (C) 2014 Antony Pavlov <antonynpavlov at gmail.com>
+ *
+ * This file is part of barebox.
+ * See file CREDITS for list of people who contributed to this project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <common.h>
+#include <init.h>
+#include <sizes.h>
+#include <asm/memory.h>
+#include <ns16550.h>
+
+#include <mach/serial.h>
+
+static int davinci_init(void)
+{
+	arm_add_mem_device("ram0", 0x82000000, SZ_16M);
+
+	return 0;
+}
+mem_initcall(davinci_init);
+
+static struct NS16550_plat serial_plat = {
+	.clock = 24000000,
+	.shift = 2,
+};
+
+static int console_init(void)
+{
+	barebox_set_model("virt2real");
+	barebox_set_hostname("virt2real");
+
+	add_ns16550_device(DEVICE_ID_DYNAMIC, DAVINCI_UART0_BASE,
+		8 << serial_plat.shift, IORESOURCE_MEM_8BIT, &serial_plat);
+
+	return 0;
+}
+console_initcall(console_init);
diff --git a/arch/arm/boards/virt2real/lowlevel.c b/arch/arm/boards/virt2real/lowlevel.c
new file mode 100644
index 0000000..3c90d78
--- /dev/null
+++ b/arch/arm/boards/virt2real/lowlevel.c
@@ -0,0 +1,34 @@
+/*
+ * Copyright (C) 2014 Antony Pavlov <antonynpavlov at gmail.com>
+ *
+ * This file is part of barebox.
+ * See file CREDITS for list of people who contributed to this project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#define __LOWLEVEL_INIT__
+
+#include <common.h>
+#include <asm/barebox-arm.h>
+#include <asm/barebox-arm-head.h>
+#include <init.h>
+#include <sizes.h>
+
+#define VIRT2REAL_SRAM_BASE 0x82000000
+#define VIRT2REAL_SRAM_SIZE SZ_16M
+
+void __naked __bare_init barebox_arm_reset_vector(void)
+{
+	arm_cpu_lowlevel_init();
+
+	barebox_arm_entry(VIRT2REAL_SRAM_BASE, VIRT2REAL_SRAM_SIZE, 0);
+}
diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig
index 5677f8d..3165d50 100644
--- a/arch/arm/mach-davinci/Kconfig
+++ b/arch/arm/mach-davinci/Kconfig
@@ -4,4 +4,13 @@ config ARCH_TEXT_BASE
 	hex
 	default 0x82000000
 
+choice
+	prompt "Davinci Board type"
+
+config MACH_VIRT2REAL
+	bool "Virt2Real"
+	select HAVE_DEFAULT_ENVIRONMENT_NEW
+
+endchoice
+
 endif
-- 
1.9.0



From antonynpavlov at gmail.com  Mon Mar 10 17:34:41 2014
From: antonynpavlov at gmail.com (Antony Pavlov)
Date: Tue, 11 Mar 2014 01:34:41 +0400
Subject: [PATCH 8/8] ARM: davinci: add virt2real_defconfig
In-Reply-To: <1394487281-10462-1-git-send-email-antonynpavlov@gmail.com>
References: <1394487281-10462-1-git-send-email-antonynpavlov@gmail.com>
Message-ID: <1394487281-10462-9-git-send-email-antonynpavlov@gmail.com>

Signed-off-by: Antony Pavlov <antonynpavlov at gmail.com>
---
 arch/arm/configs/virt2real_defconfig | 39 ++++++++++++++++++++++++++++++++++++
 1 file changed, 39 insertions(+)

diff --git a/arch/arm/configs/virt2real_defconfig b/arch/arm/configs/virt2real_defconfig
new file mode 100644
index 0000000..3c3fce1
--- /dev/null
+++ b/arch/arm/configs/virt2real_defconfig
@@ -0,0 +1,39 @@
+CONFIG_ARCH_DAVINCI=y
+CONFIG_AEABI=y
+CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
+CONFIG_TEXT_BASE=0x82300000
+CONFIG_MALLOC_SIZE=0x200000
+CONFIG_MALLOC_TLSF=y
+CONFIG_PROMPT="virt2real: "
+CONFIG_LONGHELP=y
+CONFIG_GLOB=y
+CONFIG_HUSH_FANCY_PROMPT=y
+CONFIG_CMDLINE_EDITING=y
+CONFIG_AUTO_COMPLETE=y
+CONFIG_MENU=y
+CONFIG_PASSWORD=y
+CONFIG_PARTITION=y
+CONFIG_CMD_EDIT=y
+CONFIG_CMD_SLEEP=y
+CONFIG_CMD_EXPORT=y
+CONFIG_CMD_PRINTENV=y
+CONFIG_CMD_READLINE=y
+CONFIG_CMD_ECHO_E=y
+CONFIG_CMD_LOADB=y
+CONFIG_CMD_LOADY=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_IOMEM=y
+CONFIG_CMD_MM=y
+# CONFIG_CMD_BOOTM is not set
+# CONFIG_CMD_BOOTU is not set
+CONFIG_CMD_RESET=y
+CONFIG_CMD_GO=y
+CONFIG_CMD_OFTREE=y
+CONFIG_CMD_TIMEOUT=y
+CONFIG_CMD_PARTITION=y
+CONFIG_CMD_UNCOMPRESS=y
+CONFIG_DRIVER_SERIAL_NS16550=y
+# CONFIG_SPI is not set
+CONFIG_CLOCKSOURCE_DUMMY=y
+CONFIG_SHA1=y
+CONFIG_SHA256=y
-- 
1.9.0



From s.hauer at pengutronix.de  Tue Mar 11 01:29:22 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Tue, 11 Mar 2014 06:29:22 +0100
Subject: [PATCH 1/5] mtd: Update internal API to support 64-bit device size
In-Reply-To: <20140310080213.GA32061@x61s.Speedport_W_921V_1_24_000>
References: <5319AA25.5050803@sam-solutions.net>
 <20140310072003.GH17250@pengutronix.de>
 <20140310080213.GA32061@x61s.Speedport_W_921V_1_24_000>
Message-ID: <20140311052922.GI17250@pengutronix.de>

On Mon, Mar 10, 2014 at 09:02:15AM +0100, Alexander Aring wrote:
> Hi Sascha,
> 
> we talked some time ago about >= 4GB mtd support. This patch series add
> only a size for uint64_t. But then we also need to change

That even wasn't so long ago ;)

> 
> uint32_t master_offset;
> 
> in mtd_info to:
> 
> uint64_t master_offset;
> 
> otherwise we can't create mtd partitions with a uint64_t offset. Or I am
> wrong with that? I mean... maybe they don't want to make a uint64_t
> offset but we should do it right at first time.

Yes, right. We should make this uint64_t.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From s.hauer at pengutronix.de  Tue Mar 11 01:32:52 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Tue, 11 Mar 2014 06:32:52 +0100
Subject: [PATCH v2 1/7] sata-imx: i.MX53, use the internal 120MHz clock
 by default
In-Reply-To: <20140310085112.55b969e5@e6520eb>
References: <20140210091152.GM17250@pengutronix.de>
 <1394188803-13456-1-git-send-email-eric@eukrea.com>
 <20140310070957.GG17250@pengutronix.de>
 <20140310085112.55b969e5@e6520eb>
Message-ID: <20140311053252.GJ17250@pengutronix.de>

On Mon, Mar 10, 2014 at 08:51:12AM +0100, Eric B?nard wrote:
> Hi Sascha,
> 
> Le Mon, 10 Mar 2014 08:09:57 +0100,
> Sascha Hauer <s.hauer at pengutronix.de> a ?crit :
> 
> > On Fri, Mar 07, 2014 at 11:39:57AM +0100, Eric B?nard wrote:
> > > this allows SATA to work on i.MX53 QSB-R :
> > > barebox at Freescale i.MX53 Quick Start-R Board:/ ata0.probe=1
> > > imx-sata 10000000.sata: port 0: SATA link ok
> > > imx-sata 10000000.sata: port 0: Spinning up device...
> > > imx-sata 10000000.sata: port 0: ok.
> > > ata0: registered /dev/ata0
> > > 
> > > before this fix the log was :
> > > barebox at Freescale i.MX53 Quick Start-R Board:/ ata0.probe=1
> > > imx-sata 10000000.sata: port 0: SATA link timeout
> > > set parameter: Connection timed out
> > > 
> > > Signed-off-by: Eric B?nard <eric at eukrea.com>
> > > ---
> > >  drivers/ata/sata-imx.c | 2 +-
> > >  1 file changed, 1 insertion(+), 1 deletion(-)
> > > 
> > > diff --git a/drivers/ata/sata-imx.c b/drivers/ata/sata-imx.c
> > > index b7bd110..450cf4f 100644
> > > --- a/drivers/ata/sata-imx.c
> > > +++ b/drivers/ata/sata-imx.c
> > > @@ -59,7 +59,7 @@ static int imx53_sata_init(struct imx_ahci *imx_ahci)
> > >  	 */
> > >  	val = readl(base + 0x180c);
> > >  	val &= (0x3 << 1);
> > > -	val |= (0x1 << 1);
> > > +	val |= (0x2 << 1);
> > >  	writel(val, base + 0x180c);
> > 
> > I haven't applied this yet. Have you tested this on the regular (not -R)
> > variant of the board? If not I'd like to do that before applying.
> 
> I can try to test on an original QSB (with Dialog PMIC) but I don't see
> why that would change as the difference between QSB and QSB-R is the
> PMIC (Dialog to Freescale) and here we only change the clock source of
> the SATA which has nothing to see with the PMIC.

Yeah, you're probably right. I just wonder why we explicitly used the
external clock in the first place and if there's a reason to make this
configurable.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
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From alex.aring at gmail.com  Tue Mar 11 03:50:44 2014
From: alex.aring at gmail.com (Alexander Aring)
Date: Tue, 11 Mar 2014 08:50:44 +0100
Subject: [PATCH 1/5] mtd: Update internal API to support 64-bit device size
In-Reply-To: <20140311052922.GI17250@pengutronix.de>
References: <5319AA25.5050803@sam-solutions.net>
 <20140310072003.GH17250@pengutronix.de>
 <20140310080213.GA32061@x61s.Speedport_W_921V_1_24_000>
 <20140311052922.GI17250@pengutronix.de>
Message-ID: <20140311075043.GA4321@omega>

On Tue, Mar 11, 2014 at 06:29:22AM +0100, Sascha Hauer wrote:
> > offset but we should do it right at first time.
> 
> Yes, right. We should make this uint64_t.
> 

There are also more things which needs a uint64_t like the offset
parameter of libmtd_* functions. :-/

- Alex


From renaud.barbier at ge.com  Tue Mar 11 12:54:18 2014
From: renaud.barbier at ge.com (Renaud Barbier)
Date: Tue, 11 Mar 2014 16:54:18 +0000
Subject: [PATCH] ppc: P2020RDB: add persistent configuration support
Message-ID: <1394556858-27282-1-git-send-email-renaud.barbier@ge.com>

Add an environment partition and support commands to have persistent
boot configuration for Linux.

Signed-off-by: Renaud Barbier <renaud.barbier at ge.com>
---
 arch/ppc/boards/freescale-p2020rdb/env/bin/init |  2 ++
 arch/ppc/boards/freescale-p2020rdb/env/config   |  2 ++
 arch/ppc/boards/freescale-p2020rdb/p2020rdb.c   |  9 +++++----
 arch/ppc/configs/p2020rdb_defconfig             | 21 ++++++++++++++++++++-
 4 files changed, 29 insertions(+), 5 deletions(-)
 create mode 100644 arch/ppc/boards/freescale-p2020rdb/env/bin/init
 create mode 100644 arch/ppc/boards/freescale-p2020rdb/env/config

diff --git a/arch/ppc/boards/freescale-p2020rdb/env/bin/init b/arch/ppc/boards/freescale-p2020rdb/env/bin/init
new file mode 100644
index 0000000..4d7b03e
--- /dev/null
+++ b/arch/ppc/boards/freescale-p2020rdb/env/bin/init
@@ -0,0 +1,2 @@
+#!/bin/sh
+source /env/config
\ No newline at end of file
diff --git a/arch/ppc/boards/freescale-p2020rdb/env/config b/arch/ppc/boards/freescale-p2020rdb/env/config
new file mode 100644
index 0000000..23e0ba2
--- /dev/null
+++ b/arch/ppc/boards/freescale-p2020rdb/env/config
@@ -0,0 +1,2 @@
+#!/bin/sh
+export bootargs="root=/dev/nfs rw ip=bootp"
\ No newline at end of file
diff --git a/arch/ppc/boards/freescale-p2020rdb/p2020rdb.c b/arch/ppc/boards/freescale-p2020rdb/p2020rdb.c
index 4d2ff22..229ae41 100644
--- a/arch/ppc/boards/freescale-p2020rdb/p2020rdb.c
+++ b/arch/ppc/boards/freescale-p2020rdb/p2020rdb.c
@@ -83,7 +83,10 @@ struct i2c_platform_data i2cplat = {
 static int devices_init(void)
 {
 	add_cfi_flash_device(DEVICE_ID_DYNAMIC, CFG_FLASH_BASE, 16 << 20, 0);
-
+	devfs_add_partition("nor0", 0xf60000, 0x8000, DEVFS_PARTITION_FIXED,
+			"env0");
+	devfs_add_partition("nor0", 0xf80000, 0x80000, DEVFS_PARTITION_FIXED,
+			"self0");
 	add_generic_device("i2c-fsl", 0, NULL, I2C1_BASE_ADDR,
 			0x100, IORESOURCE_MEM, &i2cplat);
 	add_generic_device("i2c-fsl", 1, NULL, I2C2_BASE_ADDR,
@@ -92,8 +95,6 @@ static int devices_init(void)
 	fsl_eth_init(2, &gfar_info[0]);
 	fsl_eth_init(3, &gfar_info[1]);
 
-	devfs_add_partition("nor0", 0xf80000, 0x80000, DEVFS_PARTITION_FIXED,
-			    "self0");
 	return 0;
 }
 
@@ -106,7 +107,7 @@ static struct NS16550_plat serial_plat = {
 
 static int p2020_console_init(void)
 {
-	barebox_set_model("Freescale P2020 RDB");
+	barebox_set_model("Freescale P2020RDB");
 	barebox_set_hostname("p2020rdb");
 
 	serial_plat.clock = fsl_get_bus_freq(0);
diff --git a/arch/ppc/configs/p2020rdb_defconfig b/arch/ppc/configs/p2020rdb_defconfig
index 868c060..c34e48d 100644
--- a/arch/ppc/configs/p2020rdb_defconfig
+++ b/arch/ppc/configs/p2020rdb_defconfig
@@ -6,10 +6,25 @@ CONFIG_GLOB=y
 CONFIG_CMDLINE_EDITING=y
 CONFIG_AUTO_COMPLETE=y
 CONFIG_CMD_SLEEP=y
+CONFIG_CMD_PARTITION=y
+CONFIG_CMD_BOOTM_ZLIB=y
+CONFIG_CMD_BOOTM_BZLIB=y
+CONFIG_ZLIB=y
+CONFIG_BZLIB=y
+CONFIG_CMD_EDIT=y
+CONFIG_CMD_EXPORT=y
 CONFIG_CMD_FLASH=y
 CONFIG_CMD_RESET=y
 CONFIG_CMD_GO=y
+CONFIG_DEFAULT_ENVIRONMENT_GENERIC=n
+CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/ppc/boards/freescale-p2020rdb/env/"
+CONFIG_CMD_LOADENV=y
+CONFIG_CMD_PRINTENV=y
+CONFIG_CMD_SAVEENV=y
+CONFIG_CMD_READLINK=y
 CONFIG_FSL_ELBC=y
+CONFIG_CMD_TIMEOUT=y
+CONFIG_CMD_UNCOMPRESS=y
 CONFIG_DRIVER_CFI=y
 CONFIG_DRIVER_CFI_AMD=y
 CONFIG_DRIVER_CFI_INTEL=n
@@ -17,7 +32,7 @@ CONFIG_DRIVER_CFI_BANK_WIDTH_1=n
 CONFIG_DRIVER_CFI_BANK_WIDTH_2=y
 CONFIG_DRIVER_CFI_BANK_WIDTH_4=n
 CONFIG_MTD=y
-CONFIG_MALLOC_SIZE=0x200000
+CONFIG_MALLOC_SIZE=0x2800000
 CONFIG_BAUDRATE=115200
 CONFIG_DRIVER_SERIAL_NS16550=y
 CONFIG_RELOCATABLE=y
@@ -34,3 +49,7 @@ CONFIG_CMD_I2C=y
 CONFIG_CMD_MIITOOL=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_IOMEM=y
+CONFIG_CMD_VERSION=n
+CONFIG_OFTREE=y
+CONFIG_CMD_OFTREE_PROBE=y
+CONFIG_CMD_OFTREE=y
\ No newline at end of file
-- 
1.8.4.2



From d.lavnikevich at sam-solutions.com  Wed Mar 12 03:54:11 2014
From: d.lavnikevich at sam-solutions.com (Dmitry Lavnikevich)
Date: Wed, 12 Mar 2014 10:54:11 +0300
Subject: [PATCH] i.MX6: bbu: Barebox update support for NAND.
Message-ID: <1394610851-721-1-git-send-email-d.lavnikevich@sam-solutions.com>

This patch implements updating barebox on i.MX6 NAND. In userspace
similar task is performed by freescale kobs-ng utility.
To use this bbu profile nand handler should be registered in board
code with 'imx6_bbu_internal_nand_register_handler' function.

Signed-off-by: Dmitry Lavnikevich <d.lavnikevich at sam-solutions.com>
Signed-off-by: Grigory Milev <g.milev at sam-solutions.com>
---
 arch/arm/mach-imx/imx-bbu-internal.c       | 745 ++++++++++++++++++++++++++++-
 arch/arm/mach-imx/include/mach/bbu.h       |   9 +
 arch/arm/mach-imx/include/mach/imx6-regs.h |   1 +
 3 files changed, 747 insertions(+), 8 deletions(-)

diff --git a/arch/arm/mach-imx/imx-bbu-internal.c b/arch/arm/mach-imx/imx-bbu-internal.c
index 9861c07..4443575 100644
--- a/arch/arm/mach-imx/imx-bbu-internal.c
+++ b/arch/arm/mach-imx/imx-bbu-internal.c
@@ -16,28 +16,67 @@
  * GNU General Public License for more details.
  */
 
-#define IMX_INTERNAL_NAND_BBU
-
 #include <common.h>
+#include <command.h>
+#include <environment.h>
 #include <malloc.h>
-#include <bbu.h>
-#include <filetype.h>
+#include <nand.h>
+#include <sizes.h>
 #include <errno.h>
-#include <fs.h>
+#include <io.h>
 #include <fcntl.h>
-#include <sizes.h>
-#include <linux/mtd/mtd-abi.h>
-#include <linux/stat.h>
+#include <libbb.h>
+#include <fs.h>
 #include <ioctl.h>
 #include <mach/bbu.h>
 #include <mach/imx-flash-header.h>
 
+#include <linux/err.h>
+#include <linux/mtd/nand.h>
+
+#define GPMI_TIMING0				0x00000070
+#define	GPMI_TIMING0_ADDRESS_SETUP_MASK			(0xff << 16)
+#define	GPMI_TIMING0_ADDRESS_SETUP_OFFSET		16
+#define	GPMI_TIMING0_DATA_HOLD_MASK			(0xff << 8)
+#define	GPMI_TIMING0_DATA_HOLD_OFFSET			8
+#define	GPMI_TIMING0_DATA_SETUP_MASK			0xff
+#define	GPMI_TIMING0_DATA_SETUP_OFFSET			0
+
+#define BCH_FLASH0LAYOUT0			0x00000080
+#define	BCH_FLASHLAYOUT0_NBLOCKS_MASK			(0xff << 24)
+#define	BCH_FLASHLAYOUT0_NBLOCKS_OFFSET			24
+#define	BCH_FLASHLAYOUT0_META_SIZE_MASK			(0xff << 16)
+#define	BCH_FLASHLAYOUT0_META_SIZE_OFFSET		16
+#define	BCH_FLASHLAYOUT0_ECC0_MASK			(0x1f << 11)
+#define	BCH_FLASHLAYOUT0_ECC0_OFFSET			11
+#define	BCH_FLASHLAYOUT0_DATA0_SIZE_MASK		0x3ff
+#define	BCH_FLASHLAYOUT0_DATA0_SIZE_OFFSET		0
+
+#define BCH_FLASH0LAYOUT1			0x00000090
+#define	BCH_FLASHLAYOUT1_PAGE_SIZE_MASK			(0xffff << 16)
+#define	BCH_FLASHLAYOUT1_PAGE_SIZE_OFFSET		16
+#define	BCH_FLASHLAYOUT1_ECCN_MASK			(0x1f << 11)
+#define	BCH_FLASHLAYOUT1_ECCN_OFFSET			11
+#define	BCH_FLASHLAYOUT1_DATAN_SIZE_MASK		0x3ff
+#define	BCH_FLASHLAYOUT1_DATAN_SIZE_OFFSET		0
+
+#define ECC_BLOCK_SIZE 512
+#define SEARCH_EXPONENT 2
+#define PAGES_PER_STRIDE 64
+#define SEARCH_AREA_SIZE_IN_STRIDES (1 << SEARCH_EXPONENT)
+#define SEARCH_AREA_SIZE_IN_PAGES      \
+	(SEARCH_AREA_SIZE_IN_STRIDES * PAGES_PER_STRIDE)
+
+#define IMX_INTERNAL_NAND_BBU
+
 #define FLASH_HEADER_OFFSET_MMC		0x400
 
 #define IMX_INTERNAL_FLAG_NAND		(1 << 0)
 #define IMX_INTERNAL_FLAG_KEEP_DOSPART	(1 << 1)
 #define IMX_INTERNAL_FLAG_ERASE		(1 << 2)
 
+#define TYPICAL_NAND_READ_SIZE 2048
+
 struct imx_internal_bbu_handler {
 	struct bbu_handler handler;
 	const void *dcd;
@@ -48,6 +87,140 @@ struct imx_internal_bbu_handler {
 	unsigned long flags;
 };
 
+struct mx6_nand_timing {
+	u8 data_setup;
+	u8 data_hold;
+	u8 address_setup;
+	u8 dsample_time;
+	u8 nand_timing_state;
+	u8 tREA;
+	u8 tRLOH;
+	u8 tRHOH;
+};
+
+struct mx6_tm_timing2 {
+	u32 read_latency;
+	u32 preamble_delay;
+	u32 ce_delay;
+	u32 postamble_delay;
+	u32 cmd_add_pause;
+	u32 data_pause;
+};
+
+struct mx6_onfi {
+	u32 onfi_sync_enable;
+	u32 onfi_sync_speed;
+	u32 read_latency;
+	u32 ce_delay;
+	u32 preamble_delay;
+	u32 postamble_delay;
+	u32 cmdadd_pause;
+	u32 data_pause;
+	u32 busy_timeout;
+};
+
+struct mx6_fcb {
+	u32 checksum;
+	u32 fingerprint;
+	u32 version;
+	struct mx6_nand_timing timing;
+	u32 page_data_size;
+	u32 total_page_size;
+	u32 sectors_per_block;
+	u32 number_of_nands;	/* not used by ROM code */
+	u32 total_internal_die;	/* not used by ROM code */
+	u32 cell_type;		/* not used by ROM code */
+	u32 ecc_blockn_type;
+	u32 ecc_block0_size;
+	u32 ecc_blockn_size;
+	u32 ecc_block0_type;
+	u32 metadata_size;
+	u32 ecc_blocks_per_page;
+	u32 rsrvd[7];		 /* not used by ROM code */
+	u32 rsrvd_unspec[2]; /* not specified in datasheet */
+	u32 fw1_start_page;
+	u32 fw2_start_page;
+	u32 fw1_sectors;
+	u32 fw2_sectors;
+	u32 dbbt_search_area;
+	u32 bb_mark_byte;
+	u32 bb_mark_startbit;
+	u32 bb_mark_phys_offset;
+	/* p.442 */
+	u32 bch_type;
+	struct mx6_tm_timing2 timing2;
+	u32 tm_speed;
+	u32 tm_timing1_busy_timeout;
+	u32 disbbm;
+	u32 bbmark_spare_offset;
+	struct mx6_onfi onfi;
+	u32 disbb_search;
+};
+
+struct mx6_dbbt_header {
+	u32 checksum;
+	u32 fingerprint;
+	u32 version;
+	u32 number_bb;
+	u32 number_pages;
+	u8 spare[492];
+};
+
+struct mx6_bbtn {
+	uint32_t nand;
+	uint32_t number_bb;
+	/* Divide by 4 because of 32 bit words.  Subtract 2 because of the
+	 * 2 above 32 bit words.
+	 */
+	uint32_t bad_block[(TYPICAL_NAND_READ_SIZE / 4) - 2];
+};
+
+#define BF_VAL(v, bf)		(((v) & bf##_MASK) >> bf##_OFFSET)
+#define GETBIT(v, n)	(((v) >> (n)) & 0x1)
+
+static u8 calculate_parity_13_8(u8 d)
+{
+	u8 p = 0;
+
+	p |= (GETBIT(d, 6) ^ GETBIT(d, 5) ^
+		  GETBIT(d, 3) ^ GETBIT(d, 2)) << 0;
+	p |= (GETBIT(d, 7) ^ GETBIT(d, 5) ^
+		  GETBIT(d, 4) ^ GETBIT(d, 2) ^
+		  GETBIT(d, 1)) << 1;
+	p |= (GETBIT(d, 7) ^ GETBIT(d, 6) ^
+		  GETBIT(d, 5) ^ GETBIT(d, 1) ^
+		  GETBIT(d, 0)) << 2;
+	p |= (GETBIT(d, 7) ^ GETBIT(d, 4) ^
+		  GETBIT(d, 3) ^ GETBIT(d, 0)) << 3;
+	p |= (GETBIT(d, 6) ^ GETBIT(d, 4) ^
+		  GETBIT(d, 3) ^ GETBIT(d, 2) ^
+		  GETBIT(d, 1) ^ GETBIT(d, 0)) << 4;
+
+	return p;
+}
+
+static void encode_hamming_13_8(void *_src, void *_ecc, size_t size)
+{
+	int i;
+	u8 *src = _src;
+	u8 *ecc = _ecc;
+
+	for (i = 0; i < size; i++)
+		ecc[i] = calculate_parity_13_8(src[i]);
+}
+
+static u32 calc_chksum(void *buf, size_t size)
+{
+	u32 chksum = 0;
+	u8 *bp = buf;
+	size_t i;
+
+	for (i = 0; i < size; i++)
+		chksum += bp[i];
+
+	return ~chksum;
+}
+
 /*
  * Actually write an image to the target device, eventually keeping a
  * DOS partition table on the device
@@ -442,6 +615,544 @@ out_free_buf:
 }
 
 /*
+  Physical organisation of data in NAND flash:
+  metadata
+  payload chunk 0 (may be empty)
+  ecc for metadata + payload chunk 0
+  payload chunk 1
+  ecc for payload chunk 1
+...
+  payload chunk n
+  ecc for payload chunk n
+ */
+static int calc_bb_offset(struct mtd_info *mtd, struct mx6_fcb *fcb)
+{
+	int bb_mark_offset;
+	int chunk_data_size = fcb->ecc_blockn_size * 8;
+	int chunk_ecc_size = (fcb->ecc_blockn_type << 1) * 13;
+	int chunk_total_size = chunk_data_size + chunk_ecc_size;
+	int bb_mark_chunk, bb_mark_chunk_offs;
+
+	bb_mark_offset = (mtd->writesize - fcb->metadata_size) * 8;
+	if (fcb->ecc_block0_size == 0)
+		bb_mark_offset -= (fcb->ecc_block0_type << 1) * 13;
+
+	bb_mark_chunk = bb_mark_offset / chunk_total_size;
+	bb_mark_chunk_offs = bb_mark_offset -
+		(bb_mark_chunk * chunk_total_size);
+	if (bb_mark_chunk_offs > chunk_data_size) {
+		printf("Unsupported ECC layout; BB mark resides in ECC data: %u\n",
+			bb_mark_chunk_offs);
+		return -EINVAL;
+	}
+	bb_mark_offset -= bb_mark_chunk * chunk_ecc_size;
+	return bb_mark_offset;
+}
+
+static struct mx6_fcb *create_fcb(struct mtd_info *mtd, void *buf,
+	unsigned fw1_start_block, size_t fw_size, unsigned fw2_start_block)
+{
+	u32 fl0, fl1, t0;
+	int metadata_size;
+	int bb_mark_bit_offs;
+	struct mx6_fcb *fcb;
+	int fcb_offs;
+	void __iomem *bch_regs = dev_get_mem_region_by_name(mtd->parent, "bch");
+	void __iomem *gpmi_regs =
+		dev_get_mem_region_by_name(mtd->parent, "gpmi-nand");
+
+	fl0 = readl(bch_regs + BCH_FLASH0LAYOUT0);
+	fl1 = readl(bch_regs + BCH_FLASH0LAYOUT1);
+	t0 = readl(gpmi_regs + GPMI_TIMING0);
+	metadata_size = BF_VAL(fl0, BCH_FLASHLAYOUT0_META_SIZE);
+
+	fcb = buf + ALIGN(metadata_size, 4);
+	fcb_offs = (void *)fcb - buf;
+
+	memset(buf, 0x00, fcb_offs);
+	memset(fcb, 0x00, sizeof(*fcb));
+	memset(fcb + 1, 0xff, mtd->erasesize - fcb_offs - sizeof(*fcb));
+
+	strncpy((char *)&fcb->fingerprint, "FCB ", 4);
+	fcb->version = cpu_to_be32(1);
+
+	fcb->timing.data_setup = BF_VAL(t0, GPMI_TIMING0_DATA_SETUP);
+	fcb->timing.data_hold = BF_VAL(t0, GPMI_TIMING0_DATA_HOLD);
+	fcb->timing.address_setup = BF_VAL(t0, GPMI_TIMING0_ADDRESS_SETUP);
+
+	fcb->page_data_size = mtd->writesize;
+	fcb->total_page_size = mtd->writesize + mtd->oobsize;
+	fcb->sectors_per_block = mtd->erasesize / mtd->writesize;
+
+	/* Should be working without hardcode. Hardcoede values are
+	 * taken from kobs-ng
+	 */
+	fcb->ecc_block0_type = BF_VAL(fl0, BCH_FLASHLAYOUT0_ECC0);
+	fcb->ecc_blockn_type = BF_VAL(fl1, BCH_FLASHLAYOUT1_ECCN);
+	fcb->ecc_block0_size = ECC_BLOCK_SIZE;
+	fcb->ecc_blockn_size = ECC_BLOCK_SIZE;
+
+	fcb->metadata_size = BF_VAL(fl0, BCH_FLASHLAYOUT0_META_SIZE);
+	fcb->ecc_blocks_per_page = BF_VAL(fl0, BCH_FLASHLAYOUT0_NBLOCKS);
+
+	fcb->fw1_start_page = fw1_start_block / mtd->writesize;
+	/* Subtract safe guard page from number of fw sectors */
+	fcb->fw1_sectors = DIV_ROUND_UP(fw_size, mtd->writesize) - 1;
+	if (fw2_start_block) {
+		fcb->fw2_start_page = fw2_start_block / mtd->writesize;
+		fcb->fw2_sectors = fcb->fw1_sectors;
+	}
+
+	fcb->dbbt_search_area = SEARCH_AREA_SIZE_IN_PAGES;
+	fcb->number_of_nands = 0;    /* not used */
+	fcb->total_internal_die = 0; /* not used */
+	fcb->cell_type = 0;          /* not used */
+
+	/* p.442 */
+	fcb->bch_type = 0;
+	fcb->timing2.read_latency = 0;
+	fcb->timing2.preamble_delay = 0;
+	fcb->timing2.ce_delay = 0;
+	fcb->timing2.postamble_delay = 0;
+	fcb->timing2.cmd_add_pause = 0;
+	fcb->timing2.data_pause = 0;
+
+	fcb->tm_speed = 0;
+	fcb->tm_timing1_busy_timeout = 0;
+
+	bb_mark_bit_offs = calc_bb_offset(mtd, fcb);
+	if (bb_mark_bit_offs < 0)
+		return ERR_PTR(bb_mark_bit_offs);
+	fcb->bb_mark_byte = bb_mark_bit_offs / 8;
+	fcb->bb_mark_startbit = bb_mark_bit_offs % 8;
+	fcb->bb_mark_phys_offset = mtd->writesize;
+
+	fcb->checksum = calc_chksum(&fcb->fingerprint, 512 - 4);
+	return fcb;
+}
+
+static int erase_part(struct mtd_info *mtd)
+{
+	loff_t ofs;
+	int ret = 0;
+	struct erase_info erase_opts = {
+		.mtd = mtd,
+		.addr = 0,
+		.len = mtd->erasesize,
+		.callback = NULL,
+	};
+
+	for (ofs = 0; ofs < mtd->size; ofs += mtd->erasesize) {
+		ret = mtd_block_isbad(mtd, ofs);
+		if (ret > 0) {
+			printf("Warning: bad block at 0x%08llx. Skipping\n",
+				   ofs);
+			continue;
+		} else if (ret < 0) {
+			printf("Error: checking bad block at 0x%llx failed\n",
+				   ofs);
+			ret = 1;
+			goto err;
+		}
+
+		erase_opts.addr = ofs;
+		ret = mtd->erase(mtd, &erase_opts);
+		if (ret) {
+			printf("Error: failed to erase block at 0x%08llx\n",
+				   ofs);
+			return ret;
+		}
+	}
+
+err:
+
+	return ret;
+}
+
+static int write_fcb(struct mtd_info *mtd, void *buf, int block)
+{
+	int ret;
+	struct nand_chip *chip = mtd->priv;
+	int page = block / mtd->writesize;
+	uint32_t offset = 0;
+	int data_len = mtd->writesize;
+	struct erase_info erase_opts = {
+		.mtd = mtd,
+		.addr = block,
+		.len = mtd->erasesize,
+		.callback = NULL,
+	};
+
+	ret = mtd->erase(mtd, &erase_opts);
+	if (ret) {
+		printf("Failed to erase FCB block %08x\n", block);
+		return ret;
+	}
+
+	printf("Writing FCB to block %08x\n", block);
+	chip->select_chip(mtd, 0);
+	ret = chip->write_page(mtd, chip,
+						   offset, data_len,
+						   buf,
+						   0,
+						   page, 0, 1);
+
+	if (ret)
+		printf("Failed to write FCB to block %08x: %d\n", block, ret);
+
+	chip->select_chip(mtd, -1);
+	return ret;
+}
+
+static int write_image(struct mtd_info *mtd, void *buf, uint32_t addr,
+	uint32_t size)
+{
+	size_t retlen;
+	int ret = 0;
+	loff_t ofs = addr;
+	size_t ofs_img = 0;
+	uint32_t size_remain;
+	int write_size;
+
+	size_remain = size;
+	printf("Writing firmware to block %08x\n", addr);
+	while (size_remain > 0) {
+		write_size = min(size_remain, mtd->erasesize);
+
+		ret = mtd_block_isbad(mtd, ofs);
+		if (ret > 0) {
+			printf("Warning: bad block at 0x%08llx. Skipping\n",
+				   ofs);
+			ofs += mtd->erasesize;
+			continue;
+		} else if (ret < 0) {
+			printf("Error: checking bad block at 0x%llx failed\n",
+				   ofs);
+			ret = 1;
+			goto err;
+		}
+
+		ret = mtd_write(mtd, ofs, write_size, &retlen, buf + ofs_img);
+		if (ret) {
+			printf("Error: failed to write firmware block at0x%08llx\n",
+				   ofs);
+			ret = 1;
+			goto err;
+		}
+
+		ofs += mtd->erasesize;
+		ofs_img += mtd->erasesize;
+		size_remain -= write_size;
+	}
+
+err:
+
+	return ret;
+}
+
+static void *read_imagefile(struct mtd_info *mtd, const char *filename,
+	size_t *size)
+{
+	int fd;
+	struct stat s;
+	void *buf = NULL;
+
+	if (stat(filename, &s))
+		return NULL;
+
+	if (!size)
+		return NULL;
+
+	*size = ((size_t)s.st_size + mtd->writesize - 1) / mtd->writesize;
+	*size += 1;         /* Sage guard page */
+	*size *= mtd->writesize;
+
+	/* Safe guard page is added */
+	buf = xzalloc(*size);
+
+	fd = open(filename, O_RDONLY);
+	if (fd < 0)
+		goto err_out;
+
+	if (read(fd, buf, s.st_size) < s.st_size)
+		goto err_out1;
+
+	close(fd);
+
+	return buf;
+
+err_out1:
+	close(fd);
+err_out:
+	free(buf);
+
+	return NULL;
+}
+
+struct mx6_dbbt_header *create_dbbt(struct mtd_info *mtd,
+	struct mx6_bbtn **bbtn_out)
+{
+	int ret = 0;
+	int no, nrbad = 0;
+	loff_t ofs;
+	int num_of_eb;
+	struct mx6_dbbt_header *dbbt;
+	int bb_found;
+	struct mx6_bbtn *bbtn;
+	int badmax = ARRAY_SIZE(bbtn->bad_block);
+	int search_area_size_in_bytes =
+		SEARCH_AREA_SIZE_IN_PAGES * mtd->writesize;
+
+	dbbt = malloc(sizeof(*dbbt));
+	if (!dbbt) {
+		printf("Error: failed to allocate DBBT header\n");
+		ret = 1;
+		goto end;
+	}
+	memset(dbbt, 0, sizeof(*dbbt));
+	bbtn = malloc(TYPICAL_NAND_READ_SIZE);
+	if (!bbtn) {
+		printf("Error: failed to allocate BBTN\n");
+		ret = 1;
+		if (dbbt)
+			free(dbbt);
+		goto end;
+	}
+	*bbtn_out = bbtn;
+	memset(bbtn, 0, TYPICAL_NAND_READ_SIZE);
+
+	num_of_eb = mtd_div_by_eb(mtd->size, mtd);
+
+	strncpy((char *)&dbbt->fingerprint, "DBBT", 4);
+	dbbt->version = cpu_to_be32(1);
+	dbbt->number_pages = 1;
+
+	/* Compose BBTN */
+	nrbad = 0;
+	for (ofs = 0; ofs < mtd->size; ofs += mtd->erasesize) {
+		/* skip the two NCB areas (where ECC does not apply) */
+		if (ofs < search_area_size_in_bytes * 2)
+			continue;
+
+		no = mtd_div_by_eb(ofs, mtd);
+
+		bb_found = mtd_block_isbad(mtd, ofs);
+		if (bb_found < 0) {
+			printf("Error: checking bad block 0x%08llx failed\n",
+				   ofs);
+			ret = 1;
+			goto err;
+		}
+
+		/* not bad */
+		if (bb_found == 0)
+			continue;
+
+		if (nrbad < badmax)
+			bbtn->bad_block[nrbad++] = no;
+	}
+
+	bbtn->nand = 0;
+	bbtn->number_bb = nrbad;
+
+end:
+	return dbbt;
+
+err:
+	free(dbbt);
+	free(bbtn);
+
+	return 0;
+}
+
+static int write_dbbt(struct mtd_info *mtd, struct mx6_dbbt_header *dbbt,
+	void *buf, int addr, uint32_t size)
+{
+	size_t retlen;
+	int ret = 0;
+
+	memset(buf, 0, mtd->erasesize);
+	memcpy(buf, dbbt, sizeof(*dbbt));
+
+	printf("Writing DBBT to block %08x\n", addr);
+	ret = mtd_write(mtd, addr, mtd->writesize, &retlen, buf);
+	if (ret) {
+		printf("Error: failed to write DBBT by addr %08x: %d\n",
+			   addr, ret);
+		return 1;
+	}
+
+	return ret;
+}
+
+static int write_bbtn(struct mtd_info *mtd, struct mx6_bbtn *bbtn,
+	void *buf, int addr, uint32_t size)
+{
+	size_t retlen;
+	int ret = 0;
+
+	memset(buf, 0, mtd->erasesize);
+	memcpy(buf, bbtn, size);
+
+	printf("Writing BBTN to block %08x\n", addr);
+	ret = mtd_write(mtd, addr, mtd->writesize, &retlen, buf);
+	if (ret) {
+		printf("Error: failed to write BBTN by addr %08x: %d\n",
+			   addr, ret);
+		return 1;
+	}
+
+	return ret;
+}
+
+/*
+ * Update barebox on a v3 type internal boot (i.MX6)
+ *
+ * This constructs a FCB header and writes the firmware image to the
+ * device. It is based on code from bcb utility for i.MX28 and
+ * dedicated for handling NAND devices.
+ */
+static int imx_bbu_internal_v3_update(struct bbu_handler *handler,
+	struct bbu_data *data)
+{
+	int ret = 0;
+	int block;
+	int stride_size_in_bytes;
+	void *image;
+	void *buf;
+	struct mx6_fcb *fcb;
+	struct mx6_dbbt_header *dbbt = 0;
+	struct mx6_bbtn *bbtn = 0;
+	struct cdev *bcb_cdev = 0;
+	unsigned long fw1_offset = 0;
+	unsigned long fw2_offset = 0;
+	size_t fw_size;
+	struct mtd_info *mtd;
+	unsigned fcb_written = 0;
+	int max_boot_stream_in_bytes;
+	int search_area_size_in_bytes;
+	int i;
+
+	if (file_detect_type(data->image, data->len) != filetype_arm_barebox) {
+		if (!bbu_force(data, "Not an ARM barebox image")) {
+			ret = -EINVAL;
+			goto err_out;
+		}
+	}
+
+	ret = bbu_confirm(data);
+	if (ret)
+		goto err_out;
+
+	printf("updating to %s\n", data->devicefile);
+
+	if (!strncmp(data->devicefile, "/dev/", 5))
+		bcb_cdev = cdev_by_name(data->devicefile + 5);
+
+	if (!bcb_cdev) {
+		pr_err("%s: No NAND barebox device!\n", __func__);
+		ret = -ENODEV;
+		goto err_out;
+	}
+
+	mtd = bcb_cdev->mtd;
+
+	buf = malloc(mtd->erasesize);
+	if (!buf) {
+		ret = -ENOMEM;
+		goto err_out;
+	}
+
+	image = read_imagefile(mtd, data->imagefile, &fw_size);
+	if (!image) {
+		ret = -errno;
+		goto err_out1;
+	}
+
+	search_area_size_in_bytes =
+		(1 << SEARCH_EXPONENT) * PAGES_PER_STRIDE * mtd->writesize;
+	max_boot_stream_in_bytes =
+		(mtd->size - search_area_size_in_bytes * 2) / 2;
+
+	fw1_offset = 2 * search_area_size_in_bytes;
+	fw2_offset = fw1_offset + max_boot_stream_in_bytes;
+
+	fcb = create_fcb(mtd, buf, fw1_offset, fw_size, fw2_offset);
+	if (IS_ERR(fcb)) {
+		printf("Failed to initialize FCB: %ld\n", PTR_ERR(fcb));
+		ret = PTR_ERR(fcb);
+		goto err_out2;
+	}
+	encode_hamming_13_8(fcb, (void *)fcb + 512, 512);
+
+	dbbt = create_dbbt(mtd, &bbtn);
+	if (!dbbt)
+		goto err_out2;
+
+	erase_part(mtd);
+
+	block = bcb_cdev->offset;
+	for (fcb_written = 0; fcb_written < 4; fcb_written++) {
+
+		if (nand_isbad_bbt(mtd, block, false))
+			continue;
+
+		ret = write_fcb(mtd, buf, block);
+		if (ret) {
+			printf("Failed to write FCB to block %u\n", block);
+			goto err_out2;
+		}
+		block += mtd->erasesize;
+	}
+	ret = fcb_written ? 0 : -ENOSPC;
+	if (ret)
+		goto err_out2;
+
+	stride_size_in_bytes = PAGES_PER_STRIDE * mtd->writesize;
+	block = SEARCH_AREA_SIZE_IN_PAGES * mtd->writesize;
+	i = 0;
+	while (i < SEARCH_AREA_SIZE_IN_STRIDES) {
+		ret = write_dbbt(mtd, dbbt, buf, block, sizeof(*dbbt));
+		if (ret)
+			goto err_out2;
+
+		block += stride_size_in_bytes;
+		i++;
+	}
+
+	block = SEARCH_AREA_SIZE_IN_PAGES * mtd->writesize + 4 * mtd->writesize;
+	i = 0;
+	while (i < SEARCH_AREA_SIZE_IN_STRIDES) {
+		ret = write_bbtn(mtd, bbtn, buf, block, sizeof(*bbtn));
+		if (ret)
+			goto err_out2;
+
+		block += stride_size_in_bytes;
+		i++;
+	}
+
+	ret = write_image(mtd, image, fw1_offset, fw_size);
+	if (ret)
+		goto err_out2;
+	ret = write_image(mtd, image, fw2_offset, fw_size);
+	if (ret)
+		goto err_out2;
+
+err_out2:
+	if (dbbt)
+		free(dbbt);
+	if (bbtn)
+		free(bbtn);
+	free(image);
+
+err_out1:
+	free(buf);
+
+err_out:
+	return ret;
+}
+
+/*
  * On the i.MX53 the dcd data can contain several commands. Each of them must
  * have its length encoded into it. We can't express that during compile time,
  * so use this function if you are using multiple dcd commands and wish to
@@ -667,3 +1378,21 @@ int imx6_bbu_internal_spi_i2c_register_handler(const char *name, char *devicefil
 	return imx53_bbu_internal_spi_i2c_register_handler(name, devicefile,
 		flags, dcd, dcdsize, app_dest);
 }
+
+/*
+ * Register a i.MX6 internal boot update handler for NAND
+ * flashes. Implementation is adapted and ported from bcb utility for
+ * i.MX28.
+ */
+int imx6_bbu_internal_nand_register_handler(const char *name, char *devicefile,
+		unsigned long flags)
+{
+	struct imx_internal_bbu_handler *imx_handler;
+
+	imx_handler = __init_handler(name, NULL, flags);
+	imx_handler->handler.handler = imx_bbu_internal_v3_update;
+	imx_handler->flags = IMX_INTERNAL_FLAG_NAND;
+	imx_handler->handler.devicefile = devicefile;
+
+	return __register_handler(imx_handler);
+}
diff --git a/arch/arm/mach-imx/include/mach/bbu.h b/arch/arm/mach-imx/include/mach/bbu.h
index 3cd3b1e..b7306d7 100644
--- a/arch/arm/mach-imx/include/mach/bbu.h
+++ b/arch/arm/mach-imx/include/mach/bbu.h
@@ -33,6 +33,9 @@ int imx6_bbu_internal_spi_i2c_register_handler(const char *name, char *devicefil
 		unsigned long flags, struct imx_dcd_v2_entry *dcd, int dcdsize,
 		unsigned long app_dest);
 
+int imx6_bbu_internal_nand_register_handler(const char *name, char *devicefile,
+		unsigned long flags);
+
 #else
 
 static inline int imx51_bbu_internal_mmc_register_handler(const char *name, char *devicefile,
@@ -77,6 +80,12 @@ static inline int imx6_bbu_internal_spi_i2c_register_handler(const char *name, c
 	return -ENOSYS;
 }
 
+static inline int imx6_bbu_internal_nand_register_handler(const char *name,
+		char *devicefile, unsigned long flags)
+{
+	return -ENOSYS;
+}
+
 #endif
 
 #if defined(CONFIG_BAREBOX_UPDATE_IMX_EXTERNAL_NAND)
diff --git a/arch/arm/mach-imx/include/mach/imx6-regs.h b/arch/arm/mach-imx/include/mach/imx6-regs.h
index 833280a..9b04142 100644
--- a/arch/arm/mach-imx/include/mach/imx6-regs.h
+++ b/arch/arm/mach-imx/include/mach/imx6-regs.h
@@ -2,6 +2,7 @@
 #define __MACH_IMX6_REGS_H
 
 #define MX6_GPMI_BASE_ADDR		0x00112000
+#define MX6_BCH_BASE_ADDR		0x00114000
 
 #define MX6_AIPS1_ARB_BASE_ADDR		0x02000000
 #define MX6_AIPS2_ARB_BASE_ADDR		0x02100000
-- 
1.9.0



From s.trumtrar at pengutronix.de  Wed Mar 12 04:06:05 2014
From: s.trumtrar at pengutronix.de (Steffen Trumtrar)
Date: Wed, 12 Mar 2014 09:06:05 +0100
Subject: [PATCH] ARM: socfpga: socrates: fix ENTRY_FUNCTION
Message-ID: <1394611565-17600-1-git-send-email-s.trumtrar@pengutronix.de>

The commit
	ARM: Make ENTRY_FUNCTION more robust
changed the behaviour of the ENTRY_FUNCTION. For the Socrates the call to
__barebox_arm_head() was not removed. Do so now otherwise the Socrates will
not be able to boot barebox.

Signed-off-by: Steffen Trumtrar <s.trumtrar at pengutronix.de>
---
 arch/arm/boards/ebv-socrates/lowlevel.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/arch/arm/boards/ebv-socrates/lowlevel.c b/arch/arm/boards/ebv-socrates/lowlevel.c
index e93ae38..035df70 100644
--- a/arch/arm/boards/ebv-socrates/lowlevel.c
+++ b/arch/arm/boards/ebv-socrates/lowlevel.c
@@ -49,8 +49,6 @@ ENTRY_FUNCTION(start_socfpga_socrates, r0, r1, r2)
 {
 	uint32_t fdt;
 
-	__barebox_arm_head();
-
 	arm_cpu_lowlevel_init();
 
 	fdt = (uint32_t)__dtb_socfpga_cyclone5_socrates_start - get_runtime_offset();
-- 
1.9.0



From s.hauer at pengutronix.de  Wed Mar 12 16:28:15 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Wed, 12 Mar 2014 21:28:15 +0100
Subject: [PATCH 1/5] mtd: Update internal API to support 64-bit device size
In-Reply-To: <20140311075043.GA4321@omega>
References: <5319AA25.5050803@sam-solutions.net>
 <20140310072003.GH17250@pengutronix.de>
 <20140310080213.GA32061@x61s.Speedport_W_921V_1_24_000>
 <20140311052922.GI17250@pengutronix.de>
 <20140311075043.GA4321@omega>
Message-ID: <20140312202814.GK17250@pengutronix.de>

On Tue, Mar 11, 2014 at 08:50:44AM +0100, Alexander Aring wrote:
> On Tue, Mar 11, 2014 at 06:29:22AM +0100, Sascha Hauer wrote:
> > > offset but we should do it right at first time.
> > 
> > Yes, right. We should make this uint64_t.
> > 
> 
> There are also more things which needs a uint64_t like the offset
> parameter of libmtd_* functions. :-/

The libmtd functions should be 64bit already. The remaining bits are in
Dmitrys series.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From s.hauer at pengutronix.de  Wed Mar 12 16:28:48 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Wed, 12 Mar 2014 21:28:48 +0100
Subject: [PATCH 1/5] mtd: Update internal API to support 64-bit device size
In-Reply-To: <1394451593-3090-1-git-send-email-d.lavnikevich@sam-solutions.com>
References: <1394451593-3090-1-git-send-email-d.lavnikevich@sam-solutions.com>
Message-ID: <20140312202848.GL17250@pengutronix.de>

On Mon, Mar 10, 2014 at 02:39:49PM +0300, Dmitry Lavnikevich wrote:
> MTD internal API presently uses 32-bit values to represent device
> size. This patch updates them to 64-bits but leaves the external API
> unchanged.
> 
> In general, changing from 32-bit to 64-bit values cause little
> or no changes to the majority of the code with the following
> exceptions:
>   - printk message formats;
>   - division and modulus of 64-bit values (mtd_div_by_wb,
>     mtd_div_by_eb may be used in some of such cases).
> 
> Was tested on phyFLEX i.MX6.
>

changed master_offset to 64bit aswell and applied this series.

Thanks
 Sascha
 
> Signed-off-by: Dmitry Lavnikevich <d.lavnikevich at sam-solutions.com>
> Signed-off-by: Grigory Milev <g.milev at sam-solutions.com>
> ---
>  commands/nandtest.c                 |  2 +-
>  commands/partition.c                | 11 ++++++-----
>  drivers/mtd/core.c                  |  2 +-
>  drivers/mtd/devices/m25p80.c        |  5 +++--
>  drivers/mtd/devices/mtd_dataflash.c |  2 +-
>  drivers/mtd/mtdoob.c                |  2 +-
>  drivers/mtd/mtdraw.c                |  2 +-
>  include/linux/mtd/mtd-abi.h         | 12 +++++++++++-
>  include/linux/mtd/mtd.h             |  9 ++++++++-
>  lib/libmtd.c                        | 10 +++++-----
>  10 files changed, 38 insertions(+), 19 deletions(-)
> 
> diff --git a/commands/nandtest.c b/commands/nandtest.c
> index 0da5444..c64f244 100644
> --- a/commands/nandtest.c
> +++ b/commands/nandtest.c
> @@ -277,7 +277,7 @@ static int do_nandtest(int argc, char *argv[])
>  	}
>  	if (length + flash_offset > meminfo.size) {
>  		printf("Length 0x%08llx + offset 0x%08llx exceeds "
> -				"device size 0x%08x\n", length,
> +				"device size 0x%08llx\n", length,
>  				flash_offset, meminfo.size);
>  		goto err;
>  	}
> diff --git a/commands/partition.c b/commands/partition.c
> index 6d37471..f825722 100644
> --- a/commands/partition.c
> +++ b/commands/partition.c
> @@ -42,10 +42,11 @@
>  #define PART_ADD_DEVNAME (1 << 0)
>  
>  static int mtd_part_do_parse_one(char *devname, const char *partstr,
> -				 char **endp, unsigned long *offset,
> -				 off_t devsize, size_t *retsize, unsigned int pflags)
> +				 char **endp, loff_t *offset,
> +				 loff_t devsize, size_t *retsize,
> +				 unsigned int pflags)
>  {
> -	ulong size;
> +	loff_t size;
>  	char *end;
>  	char buf[PATH_MAX] = {};
>  	unsigned long flags = 0;
> @@ -114,8 +115,8 @@ static int do_addpart(int argc, char *argv[])
>  {
>  	char *devname;
>  	char *endp;
> -	unsigned long offset = 0;
> -	off_t devsize;
> +	loff_t offset = 0;
> +	loff_t devsize;
>  	struct stat s;
>  	int opt;
>  	unsigned int flags = PART_ADD_DEVNAME;
> diff --git a/drivers/mtd/core.c b/drivers/mtd/core.c
> index 6db1c6d..7efb03c 100644
> --- a/drivers/mtd/core.c
> +++ b/drivers/mtd/core.c
> @@ -397,7 +397,7 @@ int add_mtd_device(struct mtd_info *mtd, char *devname, int device_id)
>  	mtd->cdev.mtd = mtd;
>  
>  	if (IS_ENABLED(CONFIG_PARAMETER)) {
> -		dev_add_param_int_ro(&mtd->class_dev, "size", mtd->size, "%u");
> +		dev_add_param_int_ro(&mtd->class_dev, "size", mtd->size, "%llu");
>  		dev_add_param_int_ro(&mtd->class_dev, "erasesize", mtd->erasesize, "%u");
>  		dev_add_param_int_ro(&mtd->class_dev, "writesize", mtd->oobsize, "%u");
>  		dev_add_param_int_ro(&mtd->class_dev, "oobsize", mtd->oobsize, "%u");
> diff --git a/drivers/mtd/devices/m25p80.c b/drivers/mtd/devices/m25p80.c
> index 9594011..757a717 100644
> --- a/drivers/mtd/devices/m25p80.c
> +++ b/drivers/mtd/devices/m25p80.c
> @@ -273,8 +273,9 @@ static int erase_sector(struct m25p *flash, u32 offset, u32 command)
>  static int m25p80_erase(struct mtd_info *mtd, struct erase_info *instr)
>  {
>  	struct m25p *flash = mtd_to_m25p(mtd);
> -	u32 addr, len;
> +	u32 addr;
>  	uint32_t rem;
> +	uint64_t len;
>  
>  	dev_dbg(&flash->spi->dev, "%s at 0x%llx, len %lld\n",
>  			__func__, (long long)instr->addr,
> @@ -896,7 +897,7 @@ static int m25p_probe(struct device_d *dev)
>  	flash->mtd.type = MTD_NORFLASH;
>  	flash->mtd.writesize = 1;
>  	flash->mtd.flags = MTD_CAP_NORFLASH;
> -	flash->mtd.size = info->sector_size * info->n_sectors;
> +	flash->mtd.size = (uint64_t)info->sector_size * info->n_sectors;
>  	flash->mtd.erase = m25p80_erase;
>  	flash->mtd.read = m25p80_read;
>  
> diff --git a/drivers/mtd/devices/mtd_dataflash.c b/drivers/mtd/devices/mtd_dataflash.c
> index cdc0120..fa31b61 100644
> --- a/drivers/mtd/devices/mtd_dataflash.c
> +++ b/drivers/mtd/devices/mtd_dataflash.c
> @@ -625,7 +625,7 @@ add_dataflash_otp(struct spi_device *spi, char *name,
>  
>  	device = &priv->mtd;
>  	device->name = (pdata && pdata->name) ? pdata->name : "dataflash";
> -	device->size = nr_pages * pagesize;
> +	device->size = nr_pages * (uint64_t)pagesize;
>  	device->erasesize = pagesize;
>  	device->writesize = pagesize;
>  	device->type = MTD_DATAFLASH;
> diff --git a/drivers/mtd/mtdoob.c b/drivers/mtd/mtdoob.c
> index 1e88b53..54888cd 100644
> --- a/drivers/mtd/mtdoob.c
> +++ b/drivers/mtd/mtdoob.c
> @@ -78,7 +78,7 @@ static int add_mtdoob_device(struct mtd_info *mtd, char *devname, void **priv)
>  
>  	mtdoob = xzalloc(sizeof(*mtdoob));
>  	mtdoob->cdev.ops = &mtd_ops_oob;
> -	mtdoob->cdev.size = (mtd->size / mtd->writesize) * mtd->oobsize;
> +	mtdoob->cdev.size = mtd_div_by_wb(mtd->size, mtd) * mtd->oobsize;
>  	mtdoob->cdev.name = asprintf("%s_oob%d", devname, mtd->class_dev.id);
>  	mtdoob->cdev.priv = mtdoob;
>  	mtdoob->cdev.dev = &mtd->class_dev;
> diff --git a/drivers/mtd/mtdraw.c b/drivers/mtd/mtdraw.c
> index be34723..33ca05d 100644
> --- a/drivers/mtd/mtdraw.c
> +++ b/drivers/mtd/mtdraw.c
> @@ -290,7 +290,7 @@ static int add_mtdraw_device(struct mtd_info *mtd, char *devname, void **priv)
>  	mtdraw->mtd = mtd;
>  
>  	mtdraw->cdev.ops = (struct file_operations *)&mtd_raw_fops;
> -	mtdraw->cdev.size = mtd->size / mtd->writesize *
> +	mtdraw->cdev.size = mtd_div_by_wb(mtd->size, mtd) *
>  		(mtd->writesize + mtd->oobsize);
>  	mtdraw->cdev.name = asprintf("%s.raw", mtd->cdev.name);
>  	mtdraw->cdev.priv = mtdraw;
> diff --git a/include/linux/mtd/mtd-abi.h b/include/linux/mtd/mtd-abi.h
> index 11d51e2..c1ba55b 100644
> --- a/include/linux/mtd/mtd-abi.h
> +++ b/include/linux/mtd/mtd-abi.h
> @@ -9,6 +9,8 @@
>  
>  #ifndef DOXYGEN_SHOULD_SKIP_THIS
>  
> +#include <asm-generic/div64.h>
> +
>  struct erase_info_user {
>  	uint32_t start;
>  	uint32_t length;
> @@ -73,7 +75,7 @@ enum {
>  struct mtd_info_user {
>  	uint8_t type;
>  	uint32_t flags;
> -	uint32_t size;	 // Total size of the MTD
> +	uint64_t size;	 /* Total size of the MTD */
>  	uint32_t erasesize;
>  	uint32_t writesize;
>  	uint32_t oobsize;   // Amount of OOB data per block (e.g. 16)
> @@ -173,6 +175,14 @@ enum mtd_file_modes {
>  	MTD_MODE_RAW,
>  };
>  
> +
> +static inline uint32_t mtd_user_div_by_eb(uint64_t sz,
> +	struct mtd_info_user *mtd_user)
> +{
> +	do_div(sz, mtd_user->erasesize);
> +	return sz;
> +}
> +
>  #endif /* DOXYGEN_SHOULD_SKIP_THIS */
>  
>  #endif /* __MTD_ABI_H__ */
> diff --git a/include/linux/mtd/mtd.h b/include/linux/mtd/mtd.h
> index 402e497..d337455 100644
> --- a/include/linux/mtd/mtd.h
> +++ b/include/linux/mtd/mtd.h
> @@ -86,7 +86,7 @@ struct mtd_oob_ops {
>  struct mtd_info {
>  	u_char type;
>  	u_int32_t flags;
> -	u_int32_t size;	 // Total size of the MTD
> +	u_int64_t size;	 /* Total size of the MTD */
>  
>  	/* "Major" erase size for the device. Na?ve users may take this
>  	 * to be the only erase size available, or may use the more detailed
> @@ -253,6 +253,13 @@ static inline uint32_t mtd_mod_by_eb(uint64_t sz, struct mtd_info *mtd)
>  {
>  	return do_div(sz, mtd->erasesize);
>  }
> +
> +static inline uint32_t mtd_div_by_wb(uint64_t sz, struct mtd_info *mtd)
> +{
> +	do_div(sz, mtd->writesize);
> +	return sz;
> +}
> +
>  	/* Kernel-side ioctl definitions */
>  
>  extern int add_mtd_device(struct mtd_info *mtd, char *devname, int device_id);
> diff --git a/lib/libmtd.c b/lib/libmtd.c
> index 1606b87..56672bd 100644
> --- a/lib/libmtd.c
> +++ b/lib/libmtd.c
> @@ -195,7 +195,7 @@ int libmtd_read(const struct mtd_dev_info *mtd, int fd, int eb, int offs,
>  	     void *buf, int len)
>  {
>  	int ret, rd = 0;
> -	off_t seek;
> +	loff_t seek;
>  
>  	ret = mtd_valid_erase_block(mtd, eb);
>  	if (ret)
> @@ -209,7 +209,7 @@ int libmtd_read(const struct mtd_dev_info *mtd, int fd, int eb, int offs,
>  	}
>  
>  	/* Seek to the beginning of the eraseblock */
> -	seek = (off_t)eb * mtd->eb_size + offs;
> +	seek = (loff_t)eb * mtd->eb_size + offs;
>  	if (lseek(fd, seek, SEEK_SET) != seek)
>  		return sys_errmsg("cannot seek %s to offset %llu",
>  				  mtd->node, (unsigned long long)seek);
> @@ -229,7 +229,7 @@ int libmtd_write(const struct mtd_dev_info *mtd, int fd, int eb, int offs,
>  	      void *buf, int len)
>  {
>  	int ret;
> -	off_t seek;
> +	loff_t seek;
>  
>  	ret = mtd_valid_erase_block(mtd, eb);
>  	if (ret)
> @@ -255,7 +255,7 @@ int libmtd_write(const struct mtd_dev_info *mtd, int fd, int eb, int offs,
>  	}
>  
>  	/* Seek to the beginning of the eraseblock */
> -	seek = (off_t)eb * mtd->eb_size + offs;
> +	seek = (loff_t)eb * mtd->eb_size + offs;
>  	if (lseek(fd, seek, SEEK_SET) != seek)
>  		return sys_errmsg("cannot seek %s to offset %llu",
>  				  mtd->node, (unsigned long long)seek);
> @@ -326,7 +326,7 @@ int mtd_get_dev_info(const char *node, struct mtd_dev_info *mtd)
>  		goto out_close;
>  	}
>  
> -	mtd->eb_cnt = ui.size / ui.erasesize;
> +	mtd->eb_cnt = mtd_user_div_by_eb(ui.size, &ui);
>  
>  	switch(mtd->type) {
>  	case MTD_ABSENT:
> -- 
> 1.9.0
> 
> 
> _______________________________________________
> barebox mailing list
> barebox at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/barebox

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From s.hauer at pengutronix.de  Wed Mar 12 16:30:12 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Wed, 12 Mar 2014 21:30:12 +0100
Subject: [PATCH] ARM: socfpga: socrates: fix ENTRY_FUNCTION
In-Reply-To: <1394611565-17600-1-git-send-email-s.trumtrar@pengutronix.de>
References: <1394611565-17600-1-git-send-email-s.trumtrar@pengutronix.de>
Message-ID: <20140312203012.GM17250@pengutronix.de>

On Wed, Mar 12, 2014 at 09:06:05AM +0100, Steffen Trumtrar wrote:
> The commit
> 	ARM: Make ENTRY_FUNCTION more robust
> changed the behaviour of the ENTRY_FUNCTION. For the Socrates the call to
> __barebox_arm_head() was not removed. Do so now otherwise the Socrates will
> not be able to boot barebox.
> 
> Signed-off-by: Steffen Trumtrar <s.trumtrar at pengutronix.de>

Applied, thanks

Sascha

> ---
>  arch/arm/boards/ebv-socrates/lowlevel.c | 2 --
>  1 file changed, 2 deletions(-)
> 
> diff --git a/arch/arm/boards/ebv-socrates/lowlevel.c b/arch/arm/boards/ebv-socrates/lowlevel.c
> index e93ae38..035df70 100644
> --- a/arch/arm/boards/ebv-socrates/lowlevel.c
> +++ b/arch/arm/boards/ebv-socrates/lowlevel.c
> @@ -49,8 +49,6 @@ ENTRY_FUNCTION(start_socfpga_socrates, r0, r1, r2)
>  {
>  	uint32_t fdt;
>  
> -	__barebox_arm_head();
> -
>  	arm_cpu_lowlevel_init();
>  
>  	fdt = (uint32_t)__dtb_socfpga_cyclone5_socrates_start - get_runtime_offset();
> -- 
> 1.9.0
> 
> 
> _______________________________________________
> barebox mailing list
> barebox at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/barebox
> 

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From alex.aring at gmail.com  Wed Mar 12 16:51:46 2014
From: alex.aring at gmail.com (Alexander Aring)
Date: Wed, 12 Mar 2014 21:51:46 +0100
Subject: [PATCH 1/5] mtd: Update internal API to support 64-bit device size
In-Reply-To: <20140312202848.GL17250@pengutronix.de>
References: <1394451593-3090-1-git-send-email-d.lavnikevich@sam-solutions.com>
 <20140312202848.GL17250@pengutronix.de>
Message-ID: <20140312205144.GA8051@x61s.Speedport_W_921V_1_24_000>

Hi Sascha,

On Wed, Mar 12, 2014 at 09:28:48PM +0100, Sascha Hauer wrote:
> On Mon, Mar 10, 2014 at 02:39:49PM +0300, Dmitry Lavnikevich wrote:
> > MTD internal API presently uses 32-bit values to represent device
> > size. This patch updates them to 64-bits but leaves the external API
> > unchanged.
> > 
> > In general, changing from 32-bit to 64-bit values cause little
> > or no changes to the majority of the code with the following
> > exceptions:
> >   - printk message formats;
> >   - division and modulus of 64-bit values (mtd_div_by_wb,
> >     mtd_div_by_eb may be used in some of such cases).
> > 
> > Was tested on phyFLEX i.MX6.
> >
> 
> changed master_offset to 64bit aswell and applied this series.
> 
ok, cool!

But.. damn it there is still a ugly comment in lib/libmtd.c:

"NOTE: No support for 64 bit sizes yet!"

hehe. :-)

- Alex


From s.hauer at pengutronix.de  Wed Mar 12 16:50:41 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Wed, 12 Mar 2014 21:50:41 +0100
Subject: [PATCH 1/8] clocksource: add dummy software-only clocksource
In-Reply-To: <1394487281-10462-2-git-send-email-antonynpavlov@gmail.com>
References: <1394487281-10462-1-git-send-email-antonynpavlov@gmail.com>
 <1394487281-10462-2-git-send-email-antonynpavlov@gmail.com>
Message-ID: <20140312205041.GN17250@pengutronix.de>

On Tue, Mar 11, 2014 at 01:34:34AM +0400, Antony Pavlov wrote:
> This driver is very handy for initial barebox porting.
> It was used for running barebox on DiGiC2-based camera
> and initial porting barebox to Loongson-1 and ar9331.
> 
> Signed-off-by: Antony Pavlov <antonynpavlov at gmail.com>
> Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
> Reported-by: Alexander Aring <alex.aring at gmail.com>
> Reported-by: Alexander Shiyan <shc_work at mail.ru>
> ---
>  drivers/clocksource/Kconfig  |  9 +++++++
>  drivers/clocksource/Makefile |  1 +
>  drivers/clocksource/dummy.c  | 56 ++++++++++++++++++++++++++++++++++++++++++++
>  3 files changed, 66 insertions(+)
> 
> diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
> index 4ef25ec..f9e00ff 100644
> --- a/drivers/clocksource/Kconfig
> +++ b/drivers/clocksource/Kconfig
> @@ -14,6 +14,15 @@ config CLOCKSOURCE_CLPS711X
>  	bool
>  	depends on ARCH_CLPS711X
>  
> +config CLOCKSOURCE_DUMMY
> +	bool "Enable dummy software-only clocksource"
> +	default n

You can drop the default n, no is the default already. Could you add
some help text mentioning that this clocksource is for early bringup
only and doesn't provide correct timing?

> +
> +config CLOCKSOURCE_DUMMY_RATE
> +	int "compile loglevel"

copy/paste ;) ?

Sascha


-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From s.hauer at pengutronix.de  Wed Mar 12 16:53:13 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Wed, 12 Mar 2014 21:53:13 +0100
Subject: [PATCH 1/5] mtd: Update internal API to support 64-bit device size
In-Reply-To: <20140312205144.GA8051@x61s.Speedport_W_921V_1_24_000>
References: <1394451593-3090-1-git-send-email-d.lavnikevich@sam-solutions.com>
 <20140312202848.GL17250@pengutronix.de>
 <20140312205144.GA8051@x61s.Speedport_W_921V_1_24_000>
Message-ID: <20140312205313.GO17250@pengutronix.de>

On Wed, Mar 12, 2014 at 09:51:46PM +0100, Alexander Aring wrote:
> Hi Sascha,
> 
> On Wed, Mar 12, 2014 at 09:28:48PM +0100, Sascha Hauer wrote:
> > On Mon, Mar 10, 2014 at 02:39:49PM +0300, Dmitry Lavnikevich wrote:
> > > MTD internal API presently uses 32-bit values to represent device
> > > size. This patch updates them to 64-bits but leaves the external API
> > > unchanged.
> > > 
> > > In general, changing from 32-bit to 64-bit values cause little
> > > or no changes to the majority of the code with the following
> > > exceptions:
> > >   - printk message formats;
> > >   - division and modulus of 64-bit values (mtd_div_by_wb,
> > >     mtd_div_by_eb may be used in some of such cases).
> > > 
> > > Was tested on phyFLEX i.MX6.
> > >
> > 
> > changed master_offset to 64bit aswell and applied this series.
> > 
> ok, cool!
> 
> But.. damn it there is still a ugly comment in lib/libmtd.c:
> 
> "NOTE: No support for 64 bit sizes yet!"

Maybe this should be removed by somebody who has tested this code with
devices > 4GB. I don't have the hardware for this.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From festevam at gmail.com  Wed Mar 12 21:14:23 2014
From: festevam at gmail.com (Fabio Estevam)
Date: Wed, 12 Mar 2014 22:14:23 -0300
Subject: [PATCH] ARM: i.MX25: freescale-mx25-3stack: Remove USBH2 pin setting
Message-ID: <1394673263-32510-1-git-send-email-festevam@gmail.com>

From: Fabio Estevam <fabio.estevam at freescale.com>

mx25-3stack only uses USBH1 and USBOTG, so remove USBH2 related pin setting.

Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>
---
 arch/arm/boards/freescale-mx25-3ds/3stack.c | 15 ---------------
 1 file changed, 15 deletions(-)

diff --git a/arch/arm/boards/freescale-mx25-3ds/3stack.c b/arch/arm/boards/freescale-mx25-3ds/3stack.c
index f000010..f2f838f 100644
--- a/arch/arm/boards/freescale-mx25-3ds/3stack.c
+++ b/arch/arm/boards/freescale-mx25-3ds/3stack.c
@@ -180,21 +180,6 @@ static iomux_v3_cfg_t imx25_pads[] = {
 	MX25_PAD_UART1_TXD__UART1_TXD,
 	MX25_PAD_UART1_RTS__UART1_RTS,
 	MX25_PAD_UART1_CTS__UART1_CTS,
-	/* USBH2 */
-	MX25_PAD_D9__USBH2_PWR,
-	MX25_PAD_D8__USBH2_OC,
-	MX25_PAD_LD0__USBH2_CLK,
-	MX25_PAD_LD1__USBH2_DIR,
-	MX25_PAD_LD2__USBH2_STP,
-	MX25_PAD_LD3__USBH2_NXT,
-	MX25_PAD_LD4__USBH2_DATA0,
-	MX25_PAD_LD5__USBH2_DATA1,
-	MX25_PAD_LD6__USBH2_DATA2,
-	MX25_PAD_LD7__USBH2_DATA3,
-	MX25_PAD_HSYNC__USBH2_DATA4,
-	MX25_PAD_VSYNC__USBH2_DATA5,
-	MX25_PAD_LSCLK__USBH2_DATA6,
-	MX25_PAD_OE_ACD__USBH2_DATA7,
 	/* i2c */
 	MX25_PAD_I2C1_CLK__I2C1_CLK,
 	MX25_PAD_I2C1_DAT__I2C1_DAT,
-- 
1.8.1.2



From xobs at kosagi.com  Wed Mar 12 22:04:35 2014
From: xobs at kosagi.com (Sean Cross)
Date: Thu, 13 Mar 2014 10:04:35 +0800
Subject: Porting barebox to Novena: misc questions
Message-ID: <53211233.5070806@kosagi.com>

Hi,

I've finally managed to get U-Boot's SPL to configure DDR3 and load
barebox off of a FAT partition on an i.MX6DL.  I also have a barebox
build with most features turned on, and I'm running into a number of
problems.  barebox is able to load a zImage off of the FAT partition,
set up ATAGs, and jump to it.  So I have the basics done.  But there are
lots of little things that aren't working.

When I boot without an Ethernet cable plugged in, the "timeout" command
takes a very long time to complete.  It generally freezes at "Hit any
key to stop autoboot:  3" and tends to ignore input for around ten
seconds.  How can I prevent this from happening, short of compiling out
FEC support?

The "usb" command just hangs the system.  It should at least detect the
other ASIX Ethernet port.  I have &usbh1 configured identically to
sabrelite.  Is there something else I need to configure?

The "usbserial" command returns "usbserial: No such device".  Like usb,
I have &usbotg configured the same as sabrelite.  It doesn't work with
dr_mode set to either "host" or "otg".

How can I pass the correct ram size to Linux?  The comment on
barebox_arm_entry() notes that "[memsize] doesn't necessarily have to be
the full SDRAM", and indeed I notice that barebox hangs if I pass it the
full 3840 MB passed from U-Boot.  So I'm currently limiting it to 1GB in
my start_imx6dl_kosagi_novena_6dl routine.  Do I need to somehow add the
remainder as another bank somewhere?  Or modify the bank size in my
kosagi_novena_init() in board.c?

Finally, I was unable to get barebox to boot with MMU support.  For some
reason it kept trying to allocate memory just outside of allocated RAM.
 Is there any benefit to running with the MMU enabled on i.MX6?


Sean


From antonynpavlov at gmail.com  Thu Mar 13 01:09:28 2014
From: antonynpavlov at gmail.com (Antony Pavlov)
Date: Thu, 13 Mar 2014 09:09:28 +0400
Subject: [PATCH 1/8] clocksource: add dummy software-only clocksource
In-Reply-To: <20140312205041.GN17250@pengutronix.de>
References: <1394487281-10462-1-git-send-email-antonynpavlov@gmail.com>
 <1394487281-10462-2-git-send-email-antonynpavlov@gmail.com>
 <20140312205041.GN17250@pengutronix.de>
Message-ID: <20140313090928.5da682507706b31ca2e38b54@gmail.com>

On Wed, 12 Mar 2014 21:50:41 +0100
Sascha Hauer <s.hauer at pengutronix.de> wrote:

> On Tue, Mar 11, 2014 at 01:34:34AM +0400, Antony Pavlov wrote:
> > This driver is very handy for initial barebox porting.
> > It was used for running barebox on DiGiC2-based camera
> > and initial porting barebox to Loongson-1 and ar9331.
> > 
> > Signed-off-by: Antony Pavlov <antonynpavlov at gmail.com>
> > Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
> > Reported-by: Alexander Aring <alex.aring at gmail.com>
> > Reported-by: Alexander Shiyan <shc_work at mail.ru>
> > ---
> >  drivers/clocksource/Kconfig  |  9 +++++++
> >  drivers/clocksource/Makefile |  1 +
> >  drivers/clocksource/dummy.c  | 56 ++++++++++++++++++++++++++++++++++++++++++++
> >  3 files changed, 66 insertions(+)
> > 
> > diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
> > index 4ef25ec..f9e00ff 100644
> > --- a/drivers/clocksource/Kconfig
> > +++ b/drivers/clocksource/Kconfig
> > @@ -14,6 +14,15 @@ config CLOCKSOURCE_CLPS711X
> >  	bool
> >  	depends on ARCH_CLPS711X
> >  
> > +config CLOCKSOURCE_DUMMY
> > +	bool "Enable dummy software-only clocksource"
> > +	default n
> 
> You can drop the default n, no is the default already. Could you add
> some help text mentioning that this clocksource is for early bringup
> only and doesn't provide correct timing?

Ok, I'll write a help text.

Yesterday I got working davinci hardware clocksource :)
So I have no dependency on dummy clocksource for Davinci. 

What is about the rest of davinci patches?

> > +
> > +config CLOCKSOURCE_DUMMY_RATE
> > +	int "compile loglevel"
> 
> copy/paste ;) ?

:)

--?
Best regards,
? Antony Pavlov


From s.hauer at pengutronix.de  Thu Mar 13 02:35:25 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Thu, 13 Mar 2014 07:35:25 +0100
Subject: [PATCH 1/8] clocksource: add dummy software-only clocksource
In-Reply-To: <20140313090928.5da682507706b31ca2e38b54@gmail.com>
References: <1394487281-10462-1-git-send-email-antonynpavlov@gmail.com>
 <1394487281-10462-2-git-send-email-antonynpavlov@gmail.com>
 <20140312205041.GN17250@pengutronix.de>
 <20140313090928.5da682507706b31ca2e38b54@gmail.com>
Message-ID: <20140313063525.GP17250@pengutronix.de>

On Thu, Mar 13, 2014 at 09:09:28AM +0400, Antony Pavlov wrote:
> On Wed, 12 Mar 2014 21:50:41 +0100
> Sascha Hauer <s.hauer at pengutronix.de> wrote:
> 
> > On Tue, Mar 11, 2014 at 01:34:34AM +0400, Antony Pavlov wrote:
> > > This driver is very handy for initial barebox porting.
> > > It was used for running barebox on DiGiC2-based camera
> > > and initial porting barebox to Loongson-1 and ar9331.
> > > 
> > > Signed-off-by: Antony Pavlov <antonynpavlov at gmail.com>
> > > Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
> > > Reported-by: Alexander Aring <alex.aring at gmail.com>
> > > Reported-by: Alexander Shiyan <shc_work at mail.ru>
> > > ---
> > >  drivers/clocksource/Kconfig  |  9 +++++++
> > >  drivers/clocksource/Makefile |  1 +
> > >  drivers/clocksource/dummy.c  | 56 ++++++++++++++++++++++++++++++++++++++++++++
> > >  3 files changed, 66 insertions(+)
> > > 
> > > diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
> > > index 4ef25ec..f9e00ff 100644
> > > --- a/drivers/clocksource/Kconfig
> > > +++ b/drivers/clocksource/Kconfig
> > > @@ -14,6 +14,15 @@ config CLOCKSOURCE_CLPS711X
> > >  	bool
> > >  	depends on ARCH_CLPS711X
> > >  
> > > +config CLOCKSOURCE_DUMMY
> > > +	bool "Enable dummy software-only clocksource"
> > > +	default n
> > 
> > You can drop the default n, no is the default already. Could you add
> > some help text mentioning that this clocksource is for early bringup
> > only and doesn't provide correct timing?
> 
> Ok, I'll write a help text.
> 
> Yesterday I got working davinci hardware clocksource :)
> So I have no dependency on dummy clocksource for Davinci. 
> 
> What is about the rest of davinci patches?

The rest looks fine, although I would prefer of cause if you used
devicetree for probing devices.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From s.hauer at pengutronix.de  Thu Mar 13 02:54:58 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Thu, 13 Mar 2014 07:54:58 +0100
Subject: [PATCH] i.MX6: bbu: Barebox update support for NAND.
In-Reply-To: <1394610851-721-1-git-send-email-d.lavnikevich@sam-solutions.com>
References: <1394610851-721-1-git-send-email-d.lavnikevich@sam-solutions.com>
Message-ID: <20140313065458.GQ17250@pengutronix.de>

Hi Dmitry,

On Wed, Mar 12, 2014 at 10:54:11AM +0300, Dmitry Lavnikevich wrote:
> This patch implements updating barebox on i.MX6 NAND. In userspace
> similar task is performed by freescale kobs-ng utility.
> To use this bbu profile nand handler should be registered in board
> code with 'imx6_bbu_internal_nand_register_handler' function.

I have the very same patch in the queue, it seems we have duplicated
some work. As this version has some shortcomings I'll post my version as
an alternative implementation. Also I'll try your version on a board I
have here on which my version doesn't work (which is the reason I
haven't posted my patch yet)

> +static int erase_part(struct mtd_info *mtd)
> +{
> +	loff_t ofs;
> +	int ret = 0;
> +	struct erase_info erase_opts = {
> +		.mtd = mtd,
> +		.addr = 0,
> +		.len = mtd->erasesize,
> +		.callback = NULL,
> +	};
> +
> +	for (ofs = 0; ofs < mtd->size; ofs += mtd->erasesize) {
> +		ret = mtd_block_isbad(mtd, ofs);
> +		if (ret > 0) {
> +			printf("Warning: bad block at 0x%08llx. Skipping\n",
> +				   ofs);
> +			continue;

This is not worth issueing a warning. Bad blocks just happen.

> +		} else if (ret < 0) {
> +			printf("Error: checking bad block at 0x%llx failed\n",
> +				   ofs);
> +			ret = 1;
> +			goto err;
> +		}
> +
> +		erase_opts.addr = ofs;
> +		ret = mtd->erase(mtd, &erase_opts);

You should use mtd_erase and friends rather than dereferencing struct
mtd_info.

> +	buf = malloc(mtd->erasesize);
> +	if (!buf) {
> +		ret = -ENOMEM;
> +		goto err_out;
> +	}
> +
> +	image = read_imagefile(mtd, data->imagefile, &fw_size);
> +	if (!image) {
> +		ret = -errno;
> +		goto err_out1;
> +	}

No Need to read the image, data->image contains a pointer to it.

> +
> +	search_area_size_in_bytes =
> +		(1 << SEARCH_EXPONENT) * PAGES_PER_STRIDE * mtd->writesize;
> +	max_boot_stream_in_bytes =
> +		(mtd->size - search_area_size_in_bytes * 2) / 2;
> +
> +	fw1_offset = 2 * search_area_size_in_bytes;
> +	fw2_offset = fw1_offset + max_boot_stream_in_bytes;
> +
> +	fcb = create_fcb(mtd, buf, fw1_offset, fw_size, fw2_offset);
> +	if (IS_ERR(fcb)) {
> +		printf("Failed to initialize FCB: %ld\n", PTR_ERR(fcb));
> +		ret = PTR_ERR(fcb);
> +		goto err_out2;
> +	}
> +	encode_hamming_13_8(fcb, (void *)fcb + 512, 512);
> +
> +	dbbt = create_dbbt(mtd, &bbtn);
> +	if (!dbbt)
> +		goto err_out2;
> +
> +	erase_part(mtd);

Error checking?

> +
> +	block = bcb_cdev->offset;
> +	for (fcb_written = 0; fcb_written < 4; fcb_written++) {
> +
> +		if (nand_isbad_bbt(mtd, block, false))
> +			continue;
> +
> +		ret = write_fcb(mtd, buf, block);
> +		if (ret) {
> +			printf("Failed to write FCB to block %u\n", block);
> +			goto err_out2;
> +		}
> +		block += mtd->erasesize;
> +	}
> +	ret = fcb_written ? 0 : -ENOSPC;
> +	if (ret)
> +		goto err_out2;
> +
> +	stride_size_in_bytes = PAGES_PER_STRIDE * mtd->writesize;
> +	block = SEARCH_AREA_SIZE_IN_PAGES * mtd->writesize;
> +	i = 0;
> +	while (i < SEARCH_AREA_SIZE_IN_STRIDES) {
> +		ret = write_dbbt(mtd, dbbt, buf, block, sizeof(*dbbt));
> +		if (ret)
> +			goto err_out2;
> +
> +		block += stride_size_in_bytes;
> +		i++;
> +	}
> +
> +	block = SEARCH_AREA_SIZE_IN_PAGES * mtd->writesize + 4 * mtd->writesize;
> +	i = 0;
> +	while (i < SEARCH_AREA_SIZE_IN_STRIDES) {
> +		ret = write_bbtn(mtd, bbtn, buf, block, sizeof(*bbtn));
> +		if (ret)
> +			goto err_out2;
> +
> +		block += stride_size_in_bytes;
> +		i++;
> +	}
> +
> +	ret = write_image(mtd, image, fw1_offset, fw_size);
> +	if (ret)
> +		goto err_out2;
> +	ret = write_image(mtd, image, fw2_offset, fw_size);
> +	if (ret)
> +		goto err_out2;

This doesn't seem to take bad blocks into account. What happens when the
first firmware image gets bigger due to bad blocks? It will be
overwritten by the 2nd image.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From s.hauer at pengutronix.de  Thu Mar 13 03:38:17 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Thu, 13 Mar 2014 08:38:17 +0100
Subject: Porting barebox to Novena: misc questions
In-Reply-To: <53211233.5070806@kosagi.com>
References: <53211233.5070806@kosagi.com>
Message-ID: <20140313073817.GR17250@pengutronix.de>

Hi Sean,

On Thu, Mar 13, 2014 at 10:04:35AM +0800, Sean Cross wrote:
> Hi,
> 
> I've finally managed to get U-Boot's SPL to configure DDR3 and load
> barebox off of a FAT partition on an i.MX6DL.  I also have a barebox
> build with most features turned on, and I'm running into a number of
> problems.  barebox is able to load a zImage off of the FAT partition,
> set up ATAGs, and jump to it.  So I have the basics done.  But there are
> lots of little things that aren't working.
> 
> When I boot without an Ethernet cable plugged in, the "timeout" command
> takes a very long time to complete.  It generally freezes at "Hit any
> key to stop autoboot:  3" and tends to ignore input for around ten
> seconds.  How can I prevent this from happening, short of compiling out
> FEC support?

Are you trying to start from network without a cable plugged in? When I
start from network without a cable I get:

running /env/bin/init...

Hit m for menu or any other key to stop autoboot:  1
blspec: blspec_scan_directory: net loader/entries
booting net
dhcp failed: Network is down
dhcp: Network is down

It indeed takes some seconds until we are sure that the link is down.
That timeout could be reduced, but we must give the phy some time to
bring up the link.

Or does this happen when you are not trying to boot from network at all?
That shouldn't happen. If it does, maybe some automount command triggers
network accesses.

> 
> The "usb" command just hangs the system.  It should at least detect the
> other ASIX Ethernet port.  I have &usbh1 configured identically to
> sabrelite.  Is there something else I need to configure?

This usually means the phys are not configured correctly. Are you
probing from devicetree?

> 
> The "usbserial" command returns "usbserial: No such device".  Like usb,
> I have &usbotg configured the same as sabrelite.  It doesn't work with
> dr_mode set to either "host" or "otg".

Ok, from devicetree it seems. I can say that there shouldn't be any bugs
in the common usb code preventing your devices from being probed. It
normally boils down to some usbmisc register setting being wrong.

> 
> How can I pass the correct ram size to Linux?  The comment on
> barebox_arm_entry() notes that "[memsize] doesn't necessarily have to be
> the full SDRAM", and indeed I notice that barebox hangs if I pass it the
> full 3840 MB passed from U-Boot.  So I'm currently limiting it to 1GB in
> my start_imx6dl_kosagi_novena_6dl routine.  Do I need to somehow add the
> remainder as another bank somewhere?  Or modify the bank size in my
> kosagi_novena_init() in board.c?

If you probe from devicetree the correct amount of memory is taken from
there. If that doesn't work (dynamic amount of memory for example) you
can set the memory in the devicetree to 0 and call arm_add_mem_device
instead.

> 
> Finally, I was unable to get barebox to boot with MMU support.  For some
> reason it kept trying to allocate memory just outside of allocated RAM.

This is related to the wrong memory setup. That should be solved when
you get that straight.

>  Is there any benefit to running with the MMU enabled on i.MX6?

Definitely, yes. barebox runs much faster with MMU enabled.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From D.Lavnikevich at sam-solutions.com  Thu Mar 13 03:50:09 2014
From: D.Lavnikevich at sam-solutions.com (Dmitry Lavnikevich)
Date: Thu, 13 Mar 2014 10:50:09 +0300
Subject: [PATCH] i.MX6: bbu: Barebox update support for NAND.
In-Reply-To: <20140313065458.GQ17250@pengutronix.de>
References: <1394610851-721-1-git-send-email-d.lavnikevich@sam-solutions.com>,
 <20140313065458.GQ17250@pengutronix.de>
Message-ID: <3B3B9EB30064F7469B76B9A505C487384D3D33637A@s246.sam-solutions.net>

Hi Sascha,

thanks for the remarks. Currently I'm ill at home and don't have access to
any hardware, so I will make this corrections if there will be need when
I will come to work.

Best regards,
Lavnikevich Dmitry
________________________________________
From: Sascha Hauer [s.hauer at pengutronix.de]
Sent: Thursday, March 13, 2014 9:54 AM
To: Dmitry Lavnikevich
Cc: barebox at lists.infradead.org; Grigory Milev
Subject: Re: [PATCH] i.MX6: bbu: Barebox update support for NAND.

Hi Dmitry,

On Wed, Mar 12, 2014 at 10:54:11AM +0300, Dmitry Lavnikevich wrote:
> This patch implements updating barebox on i.MX6 NAND. In userspace
> similar task is performed by freescale kobs-ng utility.
> To use this bbu profile nand handler should be registered in board
> code with 'imx6_bbu_internal_nand_register_handler' function.

I have the very same patch in the queue, it seems we have duplicated
some work. As this version has some shortcomings I'll post my version as
an alternative implementation. Also I'll try your version on a board I
have here on which my version doesn't work (which is the reason I
haven't posted my patch yet)

> +static int erase_part(struct mtd_info *mtd)
> +{
> +     loff_t ofs;
> +     int ret = 0;
> +     struct erase_info erase_opts = {
> +             .mtd = mtd,
> +             .addr = 0,
> +             .len = mtd->erasesize,
> +             .callback = NULL,
> +     };
> +
> +     for (ofs = 0; ofs < mtd->size; ofs += mtd->erasesize) {
> +             ret = mtd_block_isbad(mtd, ofs);
> +             if (ret > 0) {
> +                     printf("Warning: bad block at 0x%08llx. Skipping\n",
> +                                ofs);
> +                     continue;

This is not worth issueing a warning. Bad blocks just happen.

> +             } else if (ret < 0) {
> +                     printf("Error: checking bad block at 0x%llx failed\n",
> +                                ofs);
> +                     ret = 1;
> +                     goto err;
> +             }
> +
> +             erase_opts.addr = ofs;
> +             ret = mtd->erase(mtd, &erase_opts);

You should use mtd_erase and friends rather than dereferencing struct
mtd_info.

> +     buf = malloc(mtd->erasesize);
> +     if (!buf) {
> +             ret = -ENOMEM;
> +             goto err_out;
> +     }
> +
> +     image = read_imagefile(mtd, data->imagefile, &fw_size);
> +     if (!image) {
> +             ret = -errno;
> +             goto err_out1;
> +     }

No Need to read the image, data->image contains a pointer to it.

> +
> +     search_area_size_in_bytes =
> +             (1 << SEARCH_EXPONENT) * PAGES_PER_STRIDE * mtd->writesize;
> +     max_boot_stream_in_bytes =
> +             (mtd->size - search_area_size_in_bytes * 2) / 2;
> +
> +     fw1_offset = 2 * search_area_size_in_bytes;
> +     fw2_offset = fw1_offset + max_boot_stream_in_bytes;
> +
> +     fcb = create_fcb(mtd, buf, fw1_offset, fw_size, fw2_offset);
> +     if (IS_ERR(fcb)) {
> +             printf("Failed to initialize FCB: %ld\n", PTR_ERR(fcb));
> +             ret = PTR_ERR(fcb);
> +             goto err_out2;
> +     }
> +     encode_hamming_13_8(fcb, (void *)fcb + 512, 512);
> +
> +     dbbt = create_dbbt(mtd, &bbtn);
> +     if (!dbbt)
> +             goto err_out2;
> +
> +     erase_part(mtd);

Error checking?

> +
> +     block = bcb_cdev->offset;
> +     for (fcb_written = 0; fcb_written < 4; fcb_written++) {
> +
> +             if (nand_isbad_bbt(mtd, block, false))
> +                     continue;
> +
> +             ret = write_fcb(mtd, buf, block);
> +             if (ret) {
> +                     printf("Failed to write FCB to block %u\n", block);
> +                     goto err_out2;
> +             }
> +             block += mtd->erasesize;
> +     }
> +     ret = fcb_written ? 0 : -ENOSPC;
> +     if (ret)
> +             goto err_out2;
> +
> +     stride_size_in_bytes = PAGES_PER_STRIDE * mtd->writesize;
> +     block = SEARCH_AREA_SIZE_IN_PAGES * mtd->writesize;
> +     i = 0;
> +     while (i < SEARCH_AREA_SIZE_IN_STRIDES) {
> +             ret = write_dbbt(mtd, dbbt, buf, block, sizeof(*dbbt));
> +             if (ret)
> +                     goto err_out2;
> +
> +             block += stride_size_in_bytes;
> +             i++;
> +     }
> +
> +     block = SEARCH_AREA_SIZE_IN_PAGES * mtd->writesize + 4 * mtd->writesize;
> +     i = 0;
> +     while (i < SEARCH_AREA_SIZE_IN_STRIDES) {
> +             ret = write_bbtn(mtd, bbtn, buf, block, sizeof(*bbtn));
> +             if (ret)
> +                     goto err_out2;
> +
> +             block += stride_size_in_bytes;
> +             i++;
> +     }
> +
> +     ret = write_image(mtd, image, fw1_offset, fw_size);
> +     if (ret)
> +             goto err_out2;
> +     ret = write_image(mtd, image, fw2_offset, fw_size);
> +     if (ret)
> +             goto err_out2;

This doesn't seem to take bad blocks into account. What happens when the
first firmware image gets bigger due to bad blocks? It will be
overwritten by the 2nd image.

Sascha

--
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

From xobs at kosagi.com  Thu Mar 13 06:18:44 2014
From: xobs at kosagi.com (Sean Cross)
Date: Thu, 13 Mar 2014 18:18:44 +0800
Subject: Porting barebox to Novena: misc questions
In-Reply-To: <20140313073817.GR17250@pengutronix.de>
References: <53211233.5070806@kosagi.com>
 <20140313073817.GR17250@pengutronix.de>
Message-ID: <53218604.6080702@kosagi.com>

On 13/3/14 3:38 PM, Sascha Hauer wrote:
> Hi Sean,
> 
> On Thu, Mar 13, 2014 at 10:04:35AM +0800, Sean Cross wrote:
>> Hi,
>>
>> I've finally managed to get U-Boot's SPL to configure DDR3 and load
>> barebox off of a FAT partition on an i.MX6DL.  I also have a barebox
>> build with most features turned on, and I'm running into a number of
>> problems.  barebox is able to load a zImage off of the FAT partition,
>> set up ATAGs, and jump to it.  So I have the basics done.  But there are
>> lots of little things that aren't working.
>>
>> When I boot without an Ethernet cable plugged in, the "timeout" command
>> takes a very long time to complete.  It generally freezes at "Hit any
>> key to stop autoboot:  3" and tends to ignore input for around ten
>> seconds.  How can I prevent this from happening, short of compiling out
>> FEC support?
> 
> Are you trying to start from network without a cable plugged in? When I
> start from network without a cable I get:
> 
> running /env/bin/init...
> 
> Hit m for menu or any other key to stop autoboot:  1
> blspec: blspec_scan_directory: net loader/entries
> booting net
> dhcp failed: Network is down
> dhcp: Network is down
> 
> It indeed takes some seconds until we are sure that the link is down.
> That timeout could be reduced, but we must give the phy some time to
> bring up the link.
> 
> Or does this happen when you are not trying to boot from network at all?
> That shouldn't happen. If it does, maybe some automount command triggers
> network accesses.

This was caused by the default environment I imported.  It set
"ip=dhcp", which I guess caused it to try and obtain an address.  I've
set it to "ip=none" for now, and the problem has gone away.

>> The "usb" command just hangs the system.  It should at least detect the
>> other ASIX Ethernet port.  I have &usbh1 configured identically to
>> sabrelite.  Is there something else I need to configure?
> 
> This usually means the phys are not configured correctly. Are you
> probing from devicetree?

I am probing from devicetree.  I don't see phys mentioned anywhere
except in the imx6qdl.dtsi file, which means that in theory there
shouldn't be anything for me to modify.

>>
>> The "usbserial" command returns "usbserial: No such device".  Like usb,
>> I have &usbotg configured the same as sabrelite.  It doesn't work with
>> dr_mode set to either "host" or "otg".
> 
> Ok, from devicetree it seems. I can say that there shouldn't be any bugs
> in the common usb code preventing your devices from being probed. It
> normally boils down to some usbmisc register setting being wrong.

I don't see any usbmisc register mentioned in any of the board bringup
files.  The first time I run usbserial it says "No such device", and
subsequent runs cause it to print out "Invalid argument".

>> How can I pass the correct ram size to Linux?  The comment on
>> barebox_arm_entry() notes that "[memsize] doesn't necessarily have to be
>> the full SDRAM", and indeed I notice that barebox hangs if I pass it the
>> full 3840 MB passed from U-Boot.  So I'm currently limiting it to 1GB in
>> my start_imx6dl_kosagi_novena_6dl routine.  Do I need to somehow add the
>> remainder as another bank somewhere?  Or modify the bank size in my
>> kosagi_novena_init() in board.c?
> 
> If you probe from devicetree the correct amount of memory is taken from
> there. If that doesn't work (dynamic amount of memory for example) you
> can set the memory in the devicetree to 0 and call arm_add_mem_device
> instead.

Thank you.  Now I've got the full memory amount showing up.

>> Finally, I was unable to get barebox to boot with MMU support.  For some
>> reason it kept trying to allocate memory just outside of allocated RAM.
> 
> This is related to the wrong memory setup. That should be solved when
> you get that straight.
> 
>>  Is there any benefit to running with the MMU enabled on i.MX6?
> 
> Definitely, yes. barebox runs much faster with MMU enabled.

If I enable the MMU but disable early MMU, it hangs with this error:

Board: Kosagi i.MX6DL Novena Board
detected i.MX6 DualLite revision 1.1
ERROR: out of memory

[<5062e9ed>] (unwind_backtrace+0x1/0x74) from [<5061c525>] (panic+0x1d/0x34)
[<5061c525>] (panic+0x1d/0x34) from [<5061cc27>] (xmemalign+0xf/0x14)
[<5061cc27>] (xmemalign+0xf/0x14) from [<5062f687>] (mmu_init+0x16b/0x1f8)
[<5062f687>] (mmu_init+0x16b/0x1f8) from [<50600797>]
(start_barebox+0x1b/0xd0)
[<50600797>] (start_barebox+0x1b/0xd0) from [<5062efcd>] (__start+0x91/0xa4)
[<5062efcd>] (__start+0x91/0xa4) from [<50600005>]
(__bare_init_start+0x1/0xc)
### ERROR ### Please RESET the board ###

If I also enable early MMU, it hangs much much earlier.  When I dug into
it, it looked like it was trying to place a TTB just outside of the
allocated memory region, for some reason.

This is with me passing SZ_1G to barebox_arm_entry().  If I pass
something small like SZ_64M, it hangs completely.  If I instead pass it
SZ_128M, it works just fine, but of course the MMU still doesn't work.


Sean


From renaud.barbier at ge.com  Thu Mar 13 14:09:57 2014
From: renaud.barbier at ge.com (Renaud Barbier)
Date: Thu, 13 Mar 2014 18:09:57 +0000
Subject: [PATCH 0/6] ppc: add Freescale P1022DS board support
Message-ID: <1394734204-8181-1-git-send-email-renaud.barbier@ge.com>

Addition of Freescale P1022DS platform and DDR3 support.

Patches based on import of existing U-Boot code with modifications
limited to code cleanup, and making DDR2 and DDR3 support co-existent.

Renaud Barbier (6):
  ppc: add SoC support for Freescale P1022
  common: DDR3 SPD verification support
  ppc: mpc8xxx: add DDR3 support
  ppc: add Freescale P1022DS board support
  ppc: mpc85xx:gianfar: add stashing support
  ppc: P1022DS: update Kconfig and Makefile

 arch/ppc/Makefile                                  |   1 +
 arch/ppc/boards/freescale-p1022ds/Makefile         |   5 +
 arch/ppc/boards/freescale-p1022ds/config.h         |  55 +++
 arch/ppc/boards/freescale-p1022ds/ddr.c            | 126 ++++++
 arch/ppc/boards/freescale-p1022ds/env/bin/init     |   2 +
 arch/ppc/boards/freescale-p1022ds/env/config       |   2 +
 arch/ppc/boards/freescale-p1022ds/ics307_clk.c     |  46 +++
 arch/ppc/boards/freescale-p1022ds/law.c            |  27 ++
 arch/ppc/boards/freescale-p1022ds/p1022ds.c        | 181 +++++++++
 arch/ppc/boards/freescale-p1022ds/p1022ds.h        |  14 +
 arch/ppc/boards/freescale-p1022ds/tlb.c            |  59 +++
 arch/ppc/boards/freescale-p2020rdb/config.h        |   2 -
 arch/ppc/boards/geip-da923rc/config.h              |   1 -
 arch/ppc/configs/p1022ds_defconfig                 |  53 +++
 arch/ppc/cpu-85xx/start.S                          |   2 +-
 arch/ppc/ddr-8xxx/Makefile                         |   4 +-
 arch/ppc/ddr-8xxx/common_timing_params.h           |   2 +
 arch/ppc/ddr-8xxx/ctrl_regs.c                      | 429 +++++++++++++++++++--
 arch/ppc/ddr-8xxx/ddr.h                            |  15 +-
 arch/ppc/ddr-8xxx/ddr2_dimm_params.c               |   9 +-
 arch/ppc/ddr-8xxx/ddr3_dimm_params.c               | 193 +++++++++
 .../ppc/ddr-8xxx/{ddr2_setctrl.c => ddr_setctrl.c} |  44 ++-
 arch/ppc/ddr-8xxx/lc_common_dimm_params.c          | 103 +++--
 arch/ppc/ddr-8xxx/main.c                           |  12 +-
 arch/ppc/ddr-8xxx/options.c                        |  58 ++-
 arch/ppc/include/asm/fsl_ddr_dimm_params.h         |   9 +
 arch/ppc/include/asm/fsl_ddr_sdram.h               |  35 +-
 arch/ppc/include/asm/fsl_lbc.h                     |   3 +
 arch/ppc/include/asm/processor.h                   |   1 +
 arch/ppc/mach-mpc85xx/Kconfig                      |  36 +-
 arch/ppc/mach-mpc85xx/cpuid.c                      |   1 +
 arch/ppc/mach-mpc85xx/fdt.c                        |   8 +
 .../ppc/mach-mpc85xx/include/mach/config_mpc85xx.h |   9 +
 arch/ppc/mach-mpc85xx/include/mach/immap_85xx.h    |  34 +-
 common/ddr_spd.c                                   |  24 ++
 include/ddr_spd.h                                  | 116 ++++++
 36 files changed, 1606 insertions(+), 115 deletions(-)
 create mode 100644 arch/ppc/boards/freescale-p1022ds/Makefile
 create mode 100644 arch/ppc/boards/freescale-p1022ds/config.h
 create mode 100644 arch/ppc/boards/freescale-p1022ds/ddr.c
 create mode 100644 arch/ppc/boards/freescale-p1022ds/env/bin/init
 create mode 100644 arch/ppc/boards/freescale-p1022ds/env/config
 create mode 100644 arch/ppc/boards/freescale-p1022ds/ics307_clk.c
 create mode 100644 arch/ppc/boards/freescale-p1022ds/law.c
 create mode 100644 arch/ppc/boards/freescale-p1022ds/p1022ds.c
 create mode 100644 arch/ppc/boards/freescale-p1022ds/p1022ds.h
 create mode 100644 arch/ppc/boards/freescale-p1022ds/tlb.c
 create mode 100644 arch/ppc/configs/p1022ds_defconfig
 create mode 100644 arch/ppc/ddr-8xxx/ddr3_dimm_params.c
 rename arch/ppc/ddr-8xxx/{ddr2_setctrl.c => ddr_setctrl.c} (53%)

--
1.8.4.2



From renaud.barbier at ge.com  Thu Mar 13 14:09:59 2014
From: renaud.barbier at ge.com (Renaud Barbier)
Date: Thu, 13 Mar 2014 18:09:59 +0000
Subject: [PATCH 2/6] common: DDR3 SPD verification support
In-Reply-To: <1394734204-8181-1-git-send-email-renaud.barbier@ge.com>
References: <1394734204-8181-1-git-send-email-renaud.barbier@ge.com>
Message-ID: <1394734204-8181-3-git-send-email-renaud.barbier@ge.com>

Add DDR3 SPD verification support for use by the PPC 8xxx DDR driver.

This is based on the equivalent files from U-Boot version git-be937b5.

Signed-off-by: Renaud Barbier <renaud.barbier at ge.com>
---
 common/ddr_spd.c  |  24 +++++++++++
 include/ddr_spd.h | 116 ++++++++++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 140 insertions(+)

diff --git a/common/ddr_spd.c b/common/ddr_spd.c
index c8b73ff..ea0b529 100644
--- a/common/ddr_spd.c
+++ b/common/ddr_spd.c
@@ -7,6 +7,7 @@
  */
 
 #include <common.h>
+#include <crc.h>
 #include <ddr_spd.h>
 
 uint32_t ddr2_spd_checksum_pass(const struct ddr2_spd_eeprom_s *spd)
@@ -37,3 +38,26 @@ uint32_t ddr2_spd_checksum_pass(const struct ddr2_spd_eeprom_s *spd)
 error:
 	return 1;
 }
+
+uint32_t ddr3_spd_checksum_pass(const struct ddr3_spd_eeprom_s *spd)
+{
+	char crc_lsb, crc_msb;
+	int csum16, len;
+
+	/*
+	 * SPD byte0[7] - CRC coverage
+	 * 0 = CRC covers bytes 0~125
+	 * 1 = CRC covers bytes 0~116
+	 */
+
+	len = !(spd->info_size_crc & 0x80) ? 126 : 117;
+	csum16 = cyg_crc16((char *)spd, len);
+
+	crc_lsb = (char) (csum16 & 0xff);
+	crc_msb = (char) (csum16 >> 8);
+
+	if (spd->crc[0] != crc_lsb || spd->crc[1] != crc_msb)
+		return 1;
+
+	return 0;
+}
diff --git a/include/ddr_spd.h b/include/ddr_spd.h
index c8762a2..fc03bac 100644
--- a/include/ddr_spd.h
+++ b/include/ddr_spd.h
@@ -114,13 +114,126 @@ struct ddr2_spd_eeprom_s {
 	uint8_t mdate[2];    /* 93 Manufacturing Date */
 	uint8_t sernum[4];   /* 95 Assembly Serial Number */
 	uint8_t mspec[27];   /* 99-127 Manufacturer Specific Data */
+};
+
+struct ddr3_spd_eeprom_s {
+	/* General Section: Bytes 0-59 */
+	uint8_t info_size_crc;   /*  0 # bytes written into serial memory,
+					     CRC coverage */
+	uint8_t spd_rev;         /*  1 Total # bytes of SPD mem device */
+	uint8_t mem_type;        /*  2 Key Byte / Fundamental mem type */
+	uint8_t module_type;     /*  3 Key Byte / Module Type */
+	uint8_t density_banks;   /*  4 SDRAM Density and Banks */
+	uint8_t addressing;      /*  5 SDRAM Addressing */
+	uint8_t module_vdd;      /*  6 Module nominal voltage, VDD */
+	uint8_t organization;    /*  7 Module Organization */
+	uint8_t bus_width;       /*  8 Module Memory Bus Width */
+	uint8_t ftb_div;         /*  9 Fine Timebase (FTB)
+					     Dividend / Divisor */
+	uint8_t mtb_dividend;    /* 10 Medium Timebase (MTB) Dividend */
+	uint8_t mtb_divisor;     /* 11 Medium Timebase (MTB) Divisor */
+	uint8_t tck_min;         /* 12 SDRAM Minimum Cycle Time */
+	uint8_t res_13;          /* 13 Reserved */
+	uint8_t caslat_lsb;      /* 14 CAS Latencies Supported,
+					     Least Significant Byte */
+	uint8_t caslat_msb;      /* 15 CAS Latencies Supported,
+					     Most Significant Byte */
+	uint8_t taa_min;         /* 16 Min CAS Latency Time */
+	uint8_t twr_min;         /* 17 Min Write REcovery Time */
+	uint8_t trcd_min;        /* 18 Min RAS# to CAS# Delay Time */
+	uint8_t trrd_min;        /* 19 Min Row Active to
+					     Row Active Delay Time */
+	uint8_t trp_min;         /* 20 Min Row Precharge Delay Time */
+	uint8_t tras_trc_ext;    /* 21 Upper Nibbles for tRAS and tRC */
+	uint8_t tras_min_lsb;    /* 22 Min Active to Precharge
+					     Delay Time */
+	uint8_t trc_min_lsb;     /* 23 Min Active to Active/Refresh
+					     Delay Time, LSB */
+	uint8_t trfc_min_lsb;    /* 24 Min Refresh Recovery Delay Time */
+	uint8_t trfc_min_msb;    /* 25 Min Refresh Recovery Delay Time */
+	uint8_t twtr_min;        /* 26 Min Internal Write to
+					     Read Command Delay Time */
+	uint8_t trtp_min;        /* 27 Min Internal Read to Precharge
+					     Command Delay Time */
+	uint8_t tfaw_msb;        /* 28 Upper Nibble for tFAW */
+	uint8_t tfaw_min;        /* 29 Min Four Activate Window
+					     Delay Time*/
+	uint8_t opt_features;    /* 30 SDRAM Optional Features */
+	uint8_t therm_ref_opt;   /* 31 SDRAM Thermal and Refresh Opts */
+	uint8_t therm_sensor;    /* 32 Module Thermal Sensor */
+	uint8_t device_type;     /* 33 SDRAM device type */
+	int8_t fine_tck_min;     /* 34 Fine offset for tCKmin */
+	int8_t fine_taa_min;     /* 35 Fine offset for tAAmin */
+	int8_t fine_trcd_min;    /* 36 Fine offset for tRCDmin */
+	int8_t fine_trp_min;     /* 37 Fine offset for tRPmin */
+	int8_t fine_trc_min;     /* 38 Fine offset for tRCmin */
+	uint8_t res_39_59[21];   /* 39-59 Reserved, General Section */
+
+	/* Module-Specific Section: Bytes 60-116 */
+	union {
+		struct {
+			/* 60 (Unbuffered) Module Nominal Height */
+			uint8_t mod_height;
+			/* 61 (Unbuffered) Module Maximum Thickness */
+			uint8_t mod_thickness;
+			/* 62 (Unbuffered) Reference Raw Card Used */
+			uint8_t ref_raw_card;
+			/* 63 (Unbuffered) Address Mapping from
+			      Edge Connector to DRAM */
+			uint8_t addr_mapping;
+			/* 64-116 (Unbuffered) Reserved */
+			uint8_t res_64_116[53];
+		} unbuffered;
+		struct {
+			/* 60 (Registered) Module Nominal Height */
+			uint8_t mod_height;
+			/* 61 (Registered) Module Maximum Thickness */
+			uint8_t mod_thickness;
+			/* 62 (Registered) Reference Raw Card Used */
+			uint8_t ref_raw_card;
+			/* 63 DIMM Module Attributes */
+			uint8_t modu_attr;
+			/* 64 RDIMM Thermal Heat Spreader Solution */
+			uint8_t thermal;
+			/* 65 Register Manufacturer ID Code, LSB */
+			uint8_t reg_id_lo;
+			/* 66 Register Manufacturer ID Code, MSB */
+			uint8_t reg_id_hi;
+			/* 67 Register Revision Number */
+			uint8_t reg_rev;
+			/* 68 Register Type */
+			uint8_t reg_type;
+			/* 69-76 RC1,3,5..15 (MS Nib.)/RC0,2,4..14 (LS Nib.) */
+			uint8_t rcw[8];
+		} registered;
+		uint8_t uc[57]; /* 60-116 Module-Specific Section */
+	} mod_section;
+
+	/* Unique Module ID: Bytes 117-125 */
+	uint8_t mmid_lsb;        /* 117 Module MfgID Code LSB - JEP-106 */
+	uint8_t mmid_msb;        /* 118 Module MfgID Code MSB - JEP-106 */
+	uint8_t mloc;            /* 119 Mfg Location */
+	uint8_t mdate[2];        /* 120-121 Mfg Date */
+	uint8_t sernum[4];       /* 122-125 Module Serial Number */
+
+	/* CRC: Bytes 126-127 */
+	uint8_t crc[2];          /* 126-127 SPD CRC */
 
+	/* Other Manufacturer Fields and User Space: Bytes 128-255 */
+	uint8_t mpart[18];       /* 128-145 Mfg's Module Part Number */
+	uint8_t mrev[2];         /* 146-147 Module Revision Code */
+	uint8_t dmid_lsb;        /* 148 DRAM MfgID Code LSB - JEP-106 */
+	uint8_t dmid_msb;        /* 149 DRAM MfgID Code MSB - JEP-106 */
+	uint8_t msd[26];         /* 150-175 Mfg's Specific Data */
+	uint8_t cust[80];        /* 176-255 Open for Customer Use */
 };
 
+extern uint32_t ddr3_spd_checksum_pass(const struct ddr3_spd_eeprom_s *spd);
 extern uint32_t ddr2_spd_checksum_pass(const struct ddr2_spd_eeprom_s *spd);
 
 /* * Byte 2 Fundamental Memory Types. */
 #define SPD_MEMTYPE_DDR2	(0x08)
+#define SPD_MEMTYPE_DDR3	(0x0B)
 
 /* DIMM Type for DDR2 SPD (according to v1.3) */
 #define DDR2_SPD_DIMMTYPE_RDIMM		(0x01)
@@ -132,4 +245,7 @@ extern uint32_t ddr2_spd_checksum_pass(const struct ddr2_spd_eeprom_s *spd);
 #define DDR2_SPD_DIMMTYPE_MINI_RDIMM	(0x10)
 #define DDR2_SPD_DIMMTYPE_MINI_UDIMM	(0x20)
 
+/* Byte 3 Key Byte / Module Type for DDR3 SPD */
+#define DDR3_SPD_MODULETYPE_MASK	(0x0F)
+#define DDR3_SPD_MODULETYPE_UDIMM	(0x02)
 #endif /* _DDR_SPD_H_ */
-- 
1.8.4.2



From renaud.barbier at ge.com  Thu Mar 13 14:09:58 2014
From: renaud.barbier at ge.com (Renaud Barbier)
Date: Thu, 13 Mar 2014 18:09:58 +0000
Subject: [PATCH 1/6] ppc: add SoC support for Freescale P1022
In-Reply-To: <1394734204-8181-1-git-send-email-renaud.barbier@ge.com>
References: <1394734204-8181-1-git-send-email-renaud.barbier@ge.com>
Message-ID: <1394734204-8181-2-git-send-email-renaud.barbier@ge.com>

CPU, DDR, and LBC definitions are added to support the Freescale P1022.

Signed-off-by: Renaud Barbier <renaud.barbier at ge.com>
---
 arch/ppc/include/asm/fsl_lbc.h                     |  3 ++
 arch/ppc/include/asm/processor.h                   |  1 +
 arch/ppc/mach-mpc85xx/cpuid.c                      |  1 +
 .../ppc/mach-mpc85xx/include/mach/config_mpc85xx.h |  9 ++++++
 arch/ppc/mach-mpc85xx/include/mach/immap_85xx.h    | 34 ++++++++++++++++++++--
 5 files changed, 45 insertions(+), 3 deletions(-)

diff --git a/arch/ppc/include/asm/fsl_lbc.h b/arch/ppc/include/asm/fsl_lbc.h
index a59725c..27d194e 100644
--- a/arch/ppc/include/asm/fsl_lbc.h
+++ b/arch/ppc/include/asm/fsl_lbc.h
@@ -25,8 +25,10 @@
 #define BR_PS_8				0x00000800	/* Port Size 8 bit */
 #define BR_PS_16			0x00001000	/* Port Size 16 bit */
 #define BR_PS_32			0x00001800	/* Port Size 32 bit */
+#define BR_DECC_SHIFT			9
 #define BR_V				0x00000001
 #define BR_V_SHIFT			0
+#define BR_MS_FCM			0x00000020
 #define BR_MS_UPMA			0x00000080
 
 /* Convert an address into the right format for the BR registers */
@@ -61,6 +63,7 @@
 #define FSL_LBC_MDR_OFFSET	0x88
 #define FSL_LBC_LTESR_OFFSET	0xB0
 #define FSL_LBC_LTEIR_OFFSET	0xB8
+#define FSL_LBC_LBCR_OFFSET	0xD0
 
 #define MxMR_MAD_MSK		0x0000003f /* Machine Address Mask         */
 #define MxMR_GPL_x4DIS		0x00040000 /* GPL_A4 Ouput Line Disable    */
diff --git a/arch/ppc/include/asm/processor.h b/arch/ppc/include/asm/processor.h
index 819babb..c9633fe 100644
--- a/arch/ppc/include/asm/processor.h
+++ b/arch/ppc/include/asm/processor.h
@@ -867,6 +867,7 @@
 #define SVR_8641	0x8090
 #define SVR_8544	0x803401
 #define SVR_8544_E	0x803C01
+#define SVR_P1022	0x80E600
 #define SVR_P2020	0x80E200
 #define SVR_P2020_E	0x80EA00
 
diff --git a/arch/ppc/mach-mpc85xx/cpuid.c b/arch/ppc/mach-mpc85xx/cpuid.c
index 8094978..21892e3 100644
--- a/arch/ppc/mach-mpc85xx/cpuid.c
+++ b/arch/ppc/mach-mpc85xx/cpuid.c
@@ -29,6 +29,7 @@
 struct cpu_type cpu_type_list[] = {
 	CPU_TYPE_ENTRY(8544, 8544, 1),
 	CPU_TYPE_ENTRY(8544, 8544_E, 1),
+	CPU_TYPE_ENTRY(P1022, P1022, 2),
 	CPU_TYPE_ENTRY(P2020, P2020, 2),
 	CPU_TYPE_ENTRY(P2020, P2020_E, 2),
 };
diff --git a/arch/ppc/mach-mpc85xx/include/mach/config_mpc85xx.h b/arch/ppc/mach-mpc85xx/include/mach/config_mpc85xx.h
index 27358e8..f9d8299 100644
--- a/arch/ppc/mach-mpc85xx/include/mach/config_mpc85xx.h
+++ b/arch/ppc/mach-mpc85xx/include/mach/config_mpc85xx.h
@@ -39,6 +39,15 @@
 #define FSL_ERRATUM_A005125
 #define PPC_E500_DEBUG_TLB 0
 
+#elif defined(CONFIG_P1022)
+#define MAX_CPUS		2
+#define FSL_NUM_LAWS		12
+#define FSL_NUM_TSEC		2
+#define FSL_SEC_COMPAT		2
+#define PPC_E500_DEBUG_TLB	2
+#define FSL_TSECV2
+#define FSL_ERRATUM_A005125
+
 #else
 #error Processor type not defined for this platform
 #endif
diff --git a/arch/ppc/mach-mpc85xx/include/mach/immap_85xx.h b/arch/ppc/mach-mpc85xx/include/mach/immap_85xx.h
index d5a9c97..87bc5c7 100644
--- a/arch/ppc/mach-mpc85xx/include/mach/immap_85xx.h
+++ b/arch/ppc/mach-mpc85xx/include/mach/immap_85xx.h
@@ -36,7 +36,7 @@
 
 #define MPC85xx_GPIO_OFFSET	0xf000
 #define MPC85xx_L2_OFFSET	0x20000
-#ifdef CONFIG_TSECV2
+#ifdef FSL_TSECV2
 #define TSEC1_OFFSET		0xB0000
 #else
 #define TSEC1_OFFSET		0x24000
@@ -75,6 +75,11 @@
 #define MPC85xx_DDR_CS1_CONFIG_OFFSET		0x084
 #define MPC85xx_DDR_CS2_CONFIG_OFFSET		0x088
 #define MPC85xx_DDR_CS3_CONFIG_OFFSET		0x08c
+/* Chip Select 0, 1, 2, 3 Configuration 2 */
+#define MPC85xx_DDR_CS0_CONFIG_2_OFFSET		0x0c0
+#define MPC85xx_DDR_CS1_CONFIG_2_OFFSET		0x0c4
+#define MPC85xx_DDR_CS2_CONFIG_2_OFFSET		0x0c8
+#define MPC85xx_DDR_CS3_CONFIG_2_OFFSET		0x0cc
 /* SDRAM Timing Configuration 0, 1, 2, 3 */
 #define MPC85xx_DDR_TIMING_CFG_3_OFFSET		0x100
 #define MPC85xx_DDR_TIMING_CFG_0_OFFSET		0x104
@@ -97,9 +102,30 @@
 /* training init and extended addr */
 #define MPC85xx_DDR_SDRAM_INIT_ADDR_OFFSET	0x148
 #define MPC85xx_DDR_SDRAM_INIT_ADDR_EXT_OFFSET	0x14c
+/* SDRAM Timing Configuration 4,5 */
+#define MPC85xx_DDR_TIMING_CFG_4_OFFSET		0x160
+#define MPC85xx_DDR_TIMING_CFG_5_OFFSET		0x164
+/* DDR ZQ calibration control */
+#define MPC85xx_DDR_ZQ_CNTL_OFFSET		0x170
+/* DDR write leveling control */
+#define MPC85xx_DDR_WRLVL_CNTL_OFFSET		0x174
+/* Self Refresh Counter */
+#define MPC85xx_DDR_SR_CNTL_OFFSET		0x17c
+/* DDR SDRAM Register Control Word */
+#define MPC85xx_DDR_SDRAM_RCW_1_OFFSET		0x180
+#define MPC85xx_DDR_SDRAM_RCW_2_OFFSET		0x184
+/* DDR write leveling control */
+#define MPC85xx_DDR_WRLVL_CNTL_2_OFFSET		0x190
+#define MPC85xx_DDR_WRLVL_CNTL_3_OFFSET		0x194
+/* DDR Control Driver */
+#define MPC85xx_DDR_DDRCDR1_OFFSET		0xb28
+#define MPC85xx_DDR_DDRCDR2_OFFSET		0xb2c
 /* DDR IP block revision */
-#define MPC85xx_DDR_IP_REV1_OFFSET	0xbf8
-#define MPC85xx_DDR_IP_REV2_OFFSET	0xbfc
+#define MPC85xx_DDR_IP_REV1_OFFSET		0xbf8
+#define MPC85xx_DDR_IP_REV2_OFFSET		0xbfc
+/* Memory Error Disable */
+#define MPC85xx_DDR_ERR_DISABLE_OFFSET		0xe44
+#define MPC85xx_DDR_ERR_INT_EN_OFFSET		0xe48
 
 #define DDR_OFF(REGNAME)	(MPC85xx_DDR_##REGNAME##_OFFSET)
 
@@ -147,6 +173,8 @@
 #define		MPC85xx_PORPLLSR_DDR_RATIO_SHIFT	9
 #define MPC85xx_GUTS_PORDEVSR2_OFFSET	0x14
 #define		MPC85xx_PORDEVSR2_SEC_CFG		0x00000080
+#define MPC85xx_GUTS_PMUXCR_OFFSET	0x60
+#define MPC85xx_GUTS_PMUXCR2_OFFSET	0x64
 #define MPC85xx_GUTS_DEVDISR_OFFSET	0x70
 #define		MPC85xx_DEVDISR_TB0	0x00004000
 #define		MPC85xx_DEVDISR_TB1	0x00001000
-- 
1.8.4.2



From renaud.barbier at ge.com  Thu Mar 13 14:10:01 2014
From: renaud.barbier at ge.com (Renaud Barbier)
Date: Thu, 13 Mar 2014 18:10:01 +0000
Subject: [PATCH 4/6] ppc: add Freescale P1022DS board support
In-Reply-To: <1394734204-8181-1-git-send-email-renaud.barbier@ge.com>
References: <1394734204-8181-1-git-send-email-renaud.barbier@ge.com>
Message-ID: <1394734204-8181-5-git-send-email-renaud.barbier@ge.com>

Add support for the Freescale P1022DS. Driver support is limited to:
 - I2C
 - Ethernet
 - Serial
 - NOR flash
 - PIXIS FPGA

System clock configuration is read from the FPGA but has only been
tested using a 133MHz system clock and 100MHz DDR clock.

Boot arguments are defined in the environment to boot over NFS with
a console configured at 115200 bauds.

Enabling branch prediction is moved from board support to the platform
support for all boards as it is a CPU feature.

Some the code is from U-Boot version git-be937b5.

Signed-off-by: Renaud Barbier <renaud.barbier at ge.com>
---
 arch/ppc/boards/freescale-p1022ds/Makefile     |   5 +
 arch/ppc/boards/freescale-p1022ds/config.h     |  55 ++++++++
 arch/ppc/boards/freescale-p1022ds/ddr.c        | 126 +++++++++++++++++
 arch/ppc/boards/freescale-p1022ds/env/bin/init |   2 +
 arch/ppc/boards/freescale-p1022ds/env/config   |   2 +
 arch/ppc/boards/freescale-p1022ds/ics307_clk.c |  46 +++++++
 arch/ppc/boards/freescale-p1022ds/law.c        |  27 ++++
 arch/ppc/boards/freescale-p1022ds/p1022ds.c    | 181 +++++++++++++++++++++++++
 arch/ppc/boards/freescale-p1022ds/p1022ds.h    |  14 ++
 arch/ppc/boards/freescale-p1022ds/tlb.c        |  59 ++++++++
 arch/ppc/boards/freescale-p2020rdb/config.h    |   2 -
 arch/ppc/boards/geip-da923rc/config.h          |   1 -
 arch/ppc/configs/p1022ds_defconfig             |  53 ++++++++
 arch/ppc/cpu-85xx/start.S                      |   2 +-
 arch/ppc/mach-mpc85xx/Kconfig                  |   4 +
 15 files changed, 575 insertions(+), 4 deletions(-)
 create mode 100644 arch/ppc/boards/freescale-p1022ds/Makefile
 create mode 100644 arch/ppc/boards/freescale-p1022ds/config.h
 create mode 100644 arch/ppc/boards/freescale-p1022ds/ddr.c
 create mode 100644 arch/ppc/boards/freescale-p1022ds/env/bin/init
 create mode 100644 arch/ppc/boards/freescale-p1022ds/env/config
 create mode 100644 arch/ppc/boards/freescale-p1022ds/ics307_clk.c
 create mode 100644 arch/ppc/boards/freescale-p1022ds/law.c
 create mode 100644 arch/ppc/boards/freescale-p1022ds/p1022ds.c
 create mode 100644 arch/ppc/boards/freescale-p1022ds/p1022ds.h
 create mode 100644 arch/ppc/boards/freescale-p1022ds/tlb.c
 create mode 100644 arch/ppc/configs/p1022ds_defconfig

diff --git a/arch/ppc/boards/freescale-p1022ds/Makefile b/arch/ppc/boards/freescale-p1022ds/Makefile
new file mode 100644
index 0000000..e9b59d5
--- /dev/null
+++ b/arch/ppc/boards/freescale-p1022ds/Makefile
@@ -0,0 +1,5 @@
+obj-y	+= p1022ds.o
+obj-y	+= law.o
+obj-y	+= tlb.o
+obj-y	+= ddr.o
+obj-y	+= ics307_clk.o
diff --git a/arch/ppc/boards/freescale-p1022ds/config.h b/arch/ppc/boards/freescale-p1022ds/config.h
new file mode 100644
index 0000000..666b9ff
--- /dev/null
+++ b/arch/ppc/boards/freescale-p1022ds/config.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright 2009-2011 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#ifndef __ASSEMBLY__
+extern unsigned long ics307_clk_freq(unsigned int reg);
+#endif
+#define CFG_SYS_CLK_FREQ	ics307_clk_freq(25)
+#define CFG_DDR_CLK_FREQ	ics307_clk_freq(28)
+
+#define CFG_CHIP_SELECTS_PER_CTRL	 2
+
+/*
+ * Memory map
+ *
+ * 0x0000_0000	0x7fff_ffff	DDR		2G cacheable
+ *
+ * Localbus non-cacheable
+ * 0xe800_0000	0xefff_ffff	FLASH		128M non-cacheable
+ * 0xffdf_0000	0xffdf_0fff	PIXIS		4K Cacheable
+ * 0xffd0_0000	0xffd0_3fff	L1 for stack	16K Cacheable TLB0
+ */
+#define CFG_SDRAM_BASE		0x00000000
+
+#define CFG_CCSRBAR_DEFAULT	0xff700000
+#define CFG_CCSRBAR		0xffe00000
+#define CFG_CCSRBAR_PHYS	CFG_CCSRBAR
+#define CFG_IMMR		CFG_CCSRBAR
+
+#define CFG_INIT_RAM_ADDR	0xffd00000
+#define CFG_INIT_RAM_SIZE	0x00004000
+#define CFG_INIT_BI_SIZE	0x00000100
+#define CFG_INIT_SP_OFFSET	(CFG_INIT_RAM_SIZE - CFG_INIT_BI_SIZE)
+
+#define CFG_BOOT_BLOCK		0xe0000000
+#define CFG_BOOT_BLOCK_PHYS	CFG_BOOT_BLOCK
+#define CFG_FLASH_BASE		0xe8000000
+#define CFG_FLASH_BASE_PHYS	CFG_FLASH_BASE
+#define CFG_PIXIS_BASE		0xffdf0000
+#define CFG_PIXIS_BASE_PHYS	CFG_PIXIS_BASE
+
+#endif /* __CONFIG_H */
diff --git a/arch/ppc/boards/freescale-p1022ds/ddr.c b/arch/ppc/boards/freescale-p1022ds/ddr.c
new file mode 100644
index 0000000..1944518
--- /dev/null
+++ b/arch/ppc/boards/freescale-p1022ds/ddr.c
@@ -0,0 +1,126 @@
+/*
+ * Copyright 2010 Freescale Semiconductor, Inc.
+ * Authors: Srikanth Srinivasan <srikanth.srinivasan at freescale.com>
+ *          Timur Tabi <timur at freescale.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <init.h>
+#include <mach/fsl_i2c.h>
+#include <mach/immap_85xx.h>
+#include <mach/clock.h>
+#include <asm/io.h>
+#include <asm/fsl_lbc.h>
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
+#include "p1022ds.h"
+
+static const u8 spd_addr = 0x51;
+
+int fsl_ddr_board_info(struct ddr_board_info_s *info)
+{
+	/*
+	 * Early mapping is needed to access the clock
+	 * parameters in the FPGA.
+	 */
+	p1022ds_lbc_early_init();
+
+	info->fsl_ddr_ver = 0;
+	info->ddr_base = IOMEM(MPC85xx_DDR_ADDR);
+	/* Actual number of chip select used */
+	info->cs_per_ctrl = CFG_CHIP_SELECTS_PER_CTRL;
+	info->dimm_slots_per_ctrl = 1;
+	info->i2c_bus = 1;
+	info->i2c_slave = 0x7f;
+	info->i2c_speed = 400000;
+	info->i2c_base = IOMEM(I2C2_BASE_ADDR);
+	info->spd_i2c_addr = &spd_addr;
+
+	return 0;
+}
+
+struct board_specific_parameters {
+	u32 n_ranks;
+	u32 datarate_mhz_high;
+	u32 clk_adjust;		/* Range: 0-8 */
+	u32 cpo;		/* Range: 2-31 */
+	u32 write_data_delay;	/* Range: 0-6 */
+	u32 force_2t;
+};
+
+/*
+ * This table contains all valid speeds we want to override with board
+ * specific parameters. datarate_mhz_high values need to be in ascending order
+ * for each n_ranks group.
+ */
+static const struct board_specific_parameters dimm0[] = {
+	/*
+	 * memory controller 0
+	 *   num|  hi|  clk| cpo|wrdata|2T
+	 * ranks| mhz|adjst|    | delay|
+	 */
+	{ 1, 549, 5, 31, 3, 0 },
+	{ 1, 850, 5, 31, 5, 0 },
+	{ 2, 549, 5, 31, 3, 0 },
+	{ 2, 850, 5, 31, 5, 0 },
+	{ }
+};
+
+void fsl_ddr_board_options(struct memctl_options_s *popts,
+		struct dimm_params_s *pdimm)
+{
+	const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
+	unsigned long ddr_freq;
+	uint32_t i;
+
+	for (i = 0; i < popts->board_info->cs_per_ctrl; i++) {
+		popts->cs_local_opts[i].odt_rd_cfg = 0;
+		popts->cs_local_opts[i].odt_wr_cfg = 1;
+		popts->cs_local_opts[i].odt_rtt_wr = DDR3_RTT_OFF;
+	}
+	popts->cs_local_opts[0].odt_rtt_norm = DDR3_RTT_40_OHM;
+	popts->cs_local_opts[1].odt_rtt_norm = DDR3_RTT_OFF;
+
+	pbsp = dimm0;
+
+	ddr_freq = fsl_get_ddr_freq(0) / 1000000;
+	/*
+	 * To have optimal parameters specific to the board, do a fine
+	 * adjustment of DDR parameters depending on the DDR data rate.
+	 */
+	while (pbsp->datarate_mhz_high) {
+		if (pbsp->n_ranks == pdimm->n_ranks) {
+			if (ddr_freq <= pbsp->datarate_mhz_high) {
+				popts->clk_adjust = pbsp->clk_adjust;
+				popts->cpo_override = pbsp->cpo;
+				popts->write_data_delay =
+					pbsp->write_data_delay;
+				popts->twoT_en = pbsp->force_2t;
+				goto found;
+			}
+			pbsp_highest = pbsp;
+		}
+		pbsp++;
+	}
+
+	/* Use highest parameters if none were found */
+	if (pbsp_highest) {
+		popts->clk_adjust = pbsp->clk_adjust;
+		popts->cpo_override = pbsp->cpo;
+		popts->write_data_delay = pbsp->write_data_delay;
+		popts->twoT_en = pbsp->force_2t;
+	}
+
+found:
+	popts->half_strength_driver_enable = 1;
+
+	/* Per AN4039, enable ZQ calibration. */
+	popts->zq_en = 1;
+
+	popts->auto_self_refresh_en = 1;
+	popts->sr_it = 0xb;
+
+	popts->dll_rst_dis = 1;
+}
diff --git a/arch/ppc/boards/freescale-p1022ds/env/bin/init b/arch/ppc/boards/freescale-p1022ds/env/bin/init
new file mode 100644
index 0000000..c0e04c1
--- /dev/null
+++ b/arch/ppc/boards/freescale-p1022ds/env/bin/init
@@ -0,0 +1,2 @@
+#!/bin/sh
+source /env/config
diff --git a/arch/ppc/boards/freescale-p1022ds/env/config b/arch/ppc/boards/freescale-p1022ds/env/config
new file mode 100644
index 0000000..bffd868
--- /dev/null
+++ b/arch/ppc/boards/freescale-p1022ds/env/config
@@ -0,0 +1,2 @@
+#!/bin/sh
+export bootargs="root=/dev/nfs rw ip=bootp console=ttyS0,115200"
\ No newline at end of file
diff --git a/arch/ppc/boards/freescale-p1022ds/ics307_clk.c b/arch/ppc/boards/freescale-p1022ds/ics307_clk.c
new file mode 100644
index 0000000..f7c5bbd
--- /dev/null
+++ b/arch/ppc/boards/freescale-p1022ds/ics307_clk.c
@@ -0,0 +1,46 @@
+/*
+ * Copyright 2010-2011 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+
+/* decode S[0-2] to Output Divider (OD) */
+static u8 ics307_s_to_od[] = {
+	10, 2, 8, 4, 5, 7, 3, 6
+};
+
+/* Calculate frequency being generated by ICS307-02 clock chip. */
+unsigned long ics307_clk_freq(unsigned int reg)
+{
+	const unsigned long input_freq = 33333000;
+	void __iomem *fpga_base = IOMEM(CFG_PIXIS_BASE);
+	unsigned char cw0, cw1, cw2;
+	unsigned long vdw, rdw, od, freq;
+
+	cw0 = in_8(fpga_base + reg);
+	cw1 = in_8(fpga_base + reg + 1);
+	cw2 = in_8(fpga_base + reg + 2);
+	vdw = ((cw1 << 1) & 0x1fe) + ((cw2 >> 7) & 1);
+	rdw = cw2 & 0x7f;
+	od = ics307_s_to_od[cw0 & 0x7];
+	/*
+	 * CLK1 Freq = Input Frequency * 2 * (VDW + 8) / ((RDW + 2) * OD)
+	 *
+	 * cw0:  C1 C0 TTL F1 F0 S2 S1 S0
+	 * cw1:  V8 V7 V6 V5 V4 V3 V2 V1
+	 * cw2:  V0 R6 R5 R4 R3 R2 R1 R0
+	 *
+	 * R6:R0 = Reference Divider Word (RDW)
+	 * V8:V0 = VCO Divider Word (VDW)
+	 * S2:S0 = Output Divider Select (OD)
+	 * F1:F0 = Function of CLK2 Output
+	 * TTL = duty cycle
+	 * C1:C0 = internal load capacitance for crystal
+	 */
+	freq = input_freq * 2 * (vdw + 8) / ((rdw + 2) * od);
+
+	return freq;
+}
diff --git a/arch/ppc/boards/freescale-p1022ds/law.c b/arch/ppc/boards/freescale-p1022ds/law.c
new file mode 100644
index 0000000..167937a
--- /dev/null
+++ b/arch/ppc/boards/freescale-p1022ds/law.c
@@ -0,0 +1,27 @@
+/*
+ * Copyright 2009-2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+
+struct law_entry law_table[] = {
+	FSL_SET_LAW(CFG_BOOT_BLOCK_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+	FSL_SET_LAW(CFG_PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/arch/ppc/boards/freescale-p1022ds/p1022ds.c b/arch/ppc/boards/freescale-p1022ds/p1022ds.c
new file mode 100644
index 0000000..c800064
--- /dev/null
+++ b/arch/ppc/boards/freescale-p1022ds/p1022ds.c
@@ -0,0 +1,181 @@
+/*
+ * Copyright 2014 GE Intelligent Platforms, Inc.
+ * Copyright 2009-2011 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <common.h>
+#include <init.h>
+#include <driver.h>
+#include <ns16550.h>
+#include <net.h>
+#include <types.h>
+#include <i2c/i2c.h>
+#include <partition.h>
+#include <memory.h>
+#include <asm/cache.h>
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_law.h>
+#include <mach/mpc85xx.h>
+#include <mach/mmu.h>
+#include <mach/immap_85xx.h>
+#include <mach/gianfar.h>
+#include <mach/clock.h>
+#include <mach/early_udelay.h>
+
+/* Define attributes for eTSEC1 and eTSEC2 */
+static struct gfar_info_struct gfar_info[] = {
+	{
+		.phyaddr = 1,
+		.tbiana = 0,
+		.tbicr = 0,
+		.mdiobus_tbi = 0,
+	},
+	{
+		.phyaddr = 2,
+		.tbiana = 0,
+		.tbicr = 0,
+		.mdiobus_tbi = 0,
+	},
+};
+
+struct i2c_platform_data i2cplat[] = {
+	{ .bitrate = 400000, },
+	{ .bitrate = 400000, },
+};
+
+void p1022ds_lbc_early_init(void)
+{
+	void __iomem *gur = IOMEM(MPC85xx_GUTS_ADDR);
+	void __iomem *lbc = LBC_BASE_ADDR;
+
+	/* Set the local bus monitor timeout value to the maximum */
+	clrsetbits_be32(lbc + FSL_LBC_LBCR_OFFSET, 0xff0f, 0xf);
+	/* Set the pin muxing to enable ETSEC2. */
+	clrbits_be32(gur + MPC85xx_GUTS_PMUXCR2_OFFSET, 0x001f8000);
+	/* Set pmuxcr to allow both i2c1 and i2c2 */
+	setbits_be32(gur + MPC85xx_GUTS_PMUXCR_OFFSET, 0x1000);
+
+	/* Map the boot flash and FPGA */
+	fsl_set_lbc_br(0, BR_PHYS_ADDR(CFG_FLASH_BASE_PHYS) | BR_PS_16 | BR_V);
+	fsl_set_lbc_or(0, 0xf8000ff7);
+	fsl_set_lbc_br(2, BR_PHYS_ADDR(CFG_PIXIS_BASE_PHYS) | BR_PS_8 | BR_V);
+	fsl_set_lbc_or(2, 0xffff8ff7);
+}
+
+static void board_eth_init(void)
+{
+	struct i2c_adapter *adapter;
+	struct i2c_client client;
+	char mac[6];
+	int ret, ix;
+
+	adapter = i2c_get_adapter(1);
+	client.addr = 0x57;
+	client.adapter = adapter;
+
+	for (ix = 0; ix < 2; ix++) {
+		int mac_offset;
+
+		mac_offset = 0x42 + (sizeof(mac) * ix);
+		ret = i2c_read_reg(&client, mac_offset, mac, sizeof(mac));
+		if (ret != sizeof(mac))
+			pr_err("Fail to retrieve MAC address\n");
+		else
+			eth_register_ethaddr(ix, mac);
+	}
+
+	fsl_eth_init(1, &gfar_info[0]);
+	fsl_eth_init(2, &gfar_info[1]);
+}
+
+static int p1022ds_devices_init(void)
+{
+	add_cfi_flash_device(DEVICE_ID_DYNAMIC, CFG_FLASH_BASE, 128 << 20, 0);
+	devfs_add_partition("nor0", 0x7f80000, 0x80000, DEVFS_PARTITION_FIXED,
+				    "self0");
+	devfs_add_partition("nor0", 0x7f00000, 0x10000, DEVFS_PARTITION_FIXED,
+				    "env0");
+	add_generic_device("i2c-fsl", 0, NULL, I2C1_BASE_ADDR, 0x100,
+			IORESOURCE_MEM, &i2cplat[0]);
+	add_generic_device("i2c-fsl", 1, NULL, I2C2_BASE_ADDR, 0x100,
+			IORESOURCE_MEM, &i2cplat[1]);
+
+	board_eth_init();
+
+	return 0;
+}
+
+device_initcall(p1022ds_devices_init);
+
+static struct NS16550_plat serial_plat = {
+	.clock = 0,
+	.shift = 0,
+};
+
+static int p1022ds_console_init(void)
+{
+	barebox_set_model("Freescale P1022DS");
+	barebox_set_hostname("p1022ds");
+
+	serial_plat.clock = fsl_get_bus_freq(0);
+	add_ns16550_device(DEVICE_ID_DYNAMIC, CFG_IMMR + 0x4500, 16,
+			   IORESOURCE_MEM_8BIT, &serial_plat);
+	return 0;
+}
+
+console_initcall(p1022ds_console_init);
+
+static int p1022ds_mem_init(void)
+{
+	barebox_add_memory_bank("ram0", 0x0, fsl_get_effective_memsize());
+	return 0;
+}
+
+mem_initcall(p1022ds_mem_init);
+
+static int p1022ds_board_init_r(void)
+{
+	void __iomem *fpga = IOMEM(CFG_PIXIS_BASE);
+	const uint32_t flashbase = CFG_BOOT_BLOCK;
+	const u8 flash_esel = e500_find_tlb_idx((void *)flashbase, 1);
+
+	/* Enable SPI */
+	out_8(fpga + 8, (in_8(fpga + 8) & ~(0xc0)) | (0x80));
+
+	/* Map the NAND flash */
+	fsl_set_lbc_br(1, BR_PHYS_ADDR(0xff800000) | BR_PS_8 |
+			(2 << BR_DECC_SHIFT) | BR_MS_FCM | BR_V);
+	fsl_set_lbc_or(1, 0xffff8796);
+
+	/* Flush d-cache and invalidate i-cache of any FLASH data */
+	flush_dcache();
+	invalidate_icache();
+
+	/* invalidate existing TLB entry for flash */
+	e500_disable_tlb(flash_esel);
+
+	/*
+	 * Remap Boot flash region to caching-inhibited
+	 * so that flash can be erased properly.
+	 */
+	e500_set_tlb(1, flashbase, CFG_BOOT_BLOCK_PHYS,
+			MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+			0, flash_esel, BOOKE_PAGESZ_256M, 1);
+
+	fsl_l2_cache_init();
+
+	return 0;
+}
+
+core_initcall(p1022ds_board_init_r);
diff --git a/arch/ppc/boards/freescale-p1022ds/p1022ds.h b/arch/ppc/boards/freescale-p1022ds/p1022ds.h
new file mode 100644
index 0000000..cbc2aca
--- /dev/null
+++ b/arch/ppc/boards/freescale-p1022ds/p1022ds.h
@@ -0,0 +1,14 @@
+/*
+ * Copyright 2014 GE Intelligent Platforms, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+void p1022ds_lbc_early_init(void);
diff --git a/arch/ppc/boards/freescale-p1022ds/tlb.c b/arch/ppc/boards/freescale-p1022ds/tlb.c
new file mode 100644
index 0000000..86ab43a
--- /dev/null
+++ b/arch/ppc/boards/freescale-p1022ds/tlb.c
@@ -0,0 +1,59 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <common.h>
+#include <mach/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+	/* TLB 0 - for temp stack in cache */
+	FSL_SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR,
+			  MAS3_SX | MAS3_SW | MAS3_SR, 0,
+			  0, 0, BOOKE_PAGESZ_4K, 0),
+	FSL_SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + (4 * 1024),
+			  CFG_INIT_RAM_ADDR + (4 * 1024),
+			  MAS3_SX | MAS3_SW | MAS3_SR, 0,
+			  0, 0, BOOKE_PAGESZ_4K, 0),
+	FSL_SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + (8 * 1024),
+			  CFG_INIT_RAM_ADDR + (8 * 1024),
+			  MAS3_SX | MAS3_SW | MAS3_SR, 0,
+			  0, 0, BOOKE_PAGESZ_4K, 0),
+	FSL_SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + (12 * 1024),
+			  CFG_INIT_RAM_ADDR + (12 * 1024),
+			  MAS3_SX | MAS3_SW | MAS3_SR, 0,
+			  0, 0, BOOKE_PAGESZ_4K, 0),
+
+	/* TLB 1 */
+	/* *I*** - Covers boot page */
+	FSL_SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
+			  MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+			  0, 0, BOOKE_PAGESZ_4K, 1),
+
+	/* *I*G* - CCSRBAR */
+	FSL_SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS,
+			  MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+			  0, 1, BOOKE_PAGESZ_1M, 1),
+
+	/* W**G* - Flash/promjet, localbus */
+	/* This will be changed to *I*G* after relocation to RAM. */
+	FSL_SET_TLB_ENTRY(1, CFG_BOOT_BLOCK, CFG_BOOT_BLOCK_PHYS,
+			  MAS3_SX | MAS3_SR, MAS2_M | MAS2_W | MAS2_G,
+			  0, 2, BOOKE_PAGESZ_256M, 1),
+
+	FSL_SET_TLB_ENTRY(1, CFG_PIXIS_BASE, CFG_PIXIS_BASE_PHYS,
+			  MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+			  0, 7, BOOKE_PAGESZ_4K, 1),
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/arch/ppc/boards/freescale-p2020rdb/config.h b/arch/ppc/boards/freescale-p2020rdb/config.h
index c6d3216..e607ee7 100644
--- a/arch/ppc/boards/freescale-p2020rdb/config.h
+++ b/arch/ppc/boards/freescale-p2020rdb/config.h
@@ -30,8 +30,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CFG_SYS_CLK_FREQ	get_board_sys_clk(0)
 #define CFG_DDR_CLK_FREQ	66666666
 
-#define CFG_BTB			/* toggle branch predition */
-
 /*
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
diff --git a/arch/ppc/boards/geip-da923rc/config.h b/arch/ppc/boards/geip-da923rc/config.h
index 6e8684f..3895324 100644
--- a/arch/ppc/boards/geip-da923rc/config.h
+++ b/arch/ppc/boards/geip-da923rc/config.h
@@ -18,7 +18,6 @@
 #define __CONFIG_H
 
 #define CFG_SYS_CLK_FREQ	66666666
-#define CFG_BTB			/* toggle branch prediction */
 
 #define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT
 #define CFG_CHIP_SELECTS_PER_CTRL   1
diff --git a/arch/ppc/configs/p1022ds_defconfig b/arch/ppc/configs/p1022ds_defconfig
new file mode 100644
index 0000000..878286b
--- /dev/null
+++ b/arch/ppc/configs/p1022ds_defconfig
@@ -0,0 +1,53 @@
+CONFIG_ARCH_MPC85XX=y
+CONFIG_P1022DS=y
+CONFIG_P1022=y
+CONFIG_LONGHELP=y
+CONFIG_GLOB=y
+CONFIG_CMDLINE_EDITING=y
+CONFIG_AUTO_COMPLETE=y
+CONFIG_CMD_BOOTM_ZLIB=y
+CONFIG_CMD_BOOTM_BZLIB=y
+CONFIG_CMD_BOOTM_VERBOSE=y
+CONFIG_ZLIB=y
+CONFIG_BZLIB=y
+CONFIG_CMD_EDIT=y
+CONFIG_CMD_SLEEP=y
+CONFIG_CMD_FLASH=y
+CONFIG_CMD_RESET=y
+CONFIG_CMD_GO=y
+CONFIG_DEFAULT_ENVIRONMENT_GENERIC=n
+CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/ppc/boards/freescale-p1022ds/env/"
+CONFIG_CMD_LOADENV=y
+CONFIG_CMD_PRINTENV=y
+CONFIG_CMD_SAVEENV=y
+CONFIG_FSL_ELBC=y
+CONFIG_DRIVER_CFI=y
+CONFIG_DRIVER_CFI_AMD=y
+CONFIG_DRIVER_CFI_INTEL=n
+CONFIG_DRIVER_CFI_BANK_WIDTH_1=n
+CONFIG_DRIVER_CFI_BANK_WIDTH_2=y
+CONFIG_DRIVER_CFI_BANK_WIDTH_4=n
+CONFIG_MTD=y
+CONFIG_MTD_WRITE=y
+CONFIG_MALLOC_SIZE=0x4000000
+CONFIG_BAUDRATE=115200
+CONFIG_DRIVER_SERIAL_NS16550=y
+CONFIG_RELOCATABLE=y
+CONFIG_DRIVER_NET_GIANFAR=y
+CONFIG_NET=y
+CONFIG_NET_PING=y
+CONFIG_FS_TFTP=y
+CONFIG_NET_TFTP=y
+CONFIG_CMD_TFTP=y
+CONFIG_PING=y
+CONFIG_I2C=y
+CONFIG_I2C_IMX=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MIITOOL=y
+CONFIG_CMD_EXPORT=y
+CONFIG_OFTREE=y
+CONFIG_CMD_OFTREE_PROBE=y
+CONFIG_CMD_OFTREE=y
+CONFIG_CMD_BAREBOX_UPDATE=y
+CONFIG_CMD_IOMEM=y
+CONFIG_CMD_MEMTEST=y
diff --git a/arch/ppc/cpu-85xx/start.S b/arch/ppc/cpu-85xx/start.S
index 57f007b..514fd8c 100644
--- a/arch/ppc/cpu-85xx/start.S
+++ b/arch/ppc/cpu-85xx/start.S
@@ -172,7 +172,7 @@ _start_e500:
 	mtspr	HID1,r0
 
 	/* Enable Branch Prediction */
-#if defined(CFG_BTB)
+#if defined(CONFIG_BTB)
 	lis	r0,BUCSR_ENABLE at h
 	ori	r0,r0,BUCSR_ENABLE at l
 	mtspr	SPRN_BUCSR,r0
diff --git a/arch/ppc/mach-mpc85xx/Kconfig b/arch/ppc/mach-mpc85xx/Kconfig
index 74bad76..d02cf9b 100644
--- a/arch/ppc/mach-mpc85xx/Kconfig
+++ b/arch/ppc/mach-mpc85xx/Kconfig
@@ -3,6 +3,10 @@ if ARCH_MPC85XX
 config MMU
 	default y if CMD_MEMTEST
 
+config BTB
+	bool
+	default y if P2020RDB || P1022DS || DA923RC
+
 config TEXT_BASE
 	hex
 	default 0xeff80000 if P2020RDB
-- 
1.8.4.2



From renaud.barbier at ge.com  Thu Mar 13 14:10:02 2014
From: renaud.barbier at ge.com (Renaud Barbier)
Date: Thu, 13 Mar 2014 18:10:02 +0000
Subject: [PATCH 5/7] ppc: mpc85xx: add stashing support
In-Reply-To: <1394734204-8181-1-git-send-email-renaud.barbier@ge.com>
References: <1394734204-8181-1-git-send-email-renaud.barbier@ge.com>
Message-ID: <1394734204-8181-6-git-send-email-renaud.barbier@ge.com>

The eTSEC 2.0 devices found on the 85xx family of SoCs support stashing
buffer descriptors in the L2 cache. This updates the device tree fixup
for these devices to ensure that the stashing related properties used
by Linux are initialised correctly.

Signed-off-by: Renaud Barbier <renaud.barbier at ge.com>
---
 arch/ppc/mach-mpc85xx/fdt.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/ppc/mach-mpc85xx/fdt.c b/arch/ppc/mach-mpc85xx/fdt.c
index b1da144..1a2d780 100644
--- a/arch/ppc/mach-mpc85xx/fdt.c
+++ b/arch/ppc/mach-mpc85xx/fdt.c
@@ -54,6 +54,14 @@ static void fdt_add_enet_stashing(void *fdt)
 		of_property_write_u32(node, "rx-stash-idx", 0);
 		node = of_find_compatible_node(node, NULL, "gianfar");
 	}
+
+	node = of_find_compatible_node(fdt, NULL, "fsl,etsec2");
+	while (node) {
+		of_set_property(node, "bd-stash", NULL, 0, 1);
+		of_property_write_u32(node, "rx-stash-len", 96);
+		of_property_write_u32(node, "rx-stash-idx", 0);
+		node = of_find_compatible_node(node, NULL, "fsl,etsec2");
+	}
 }
 
 static int fdt_stdout_setup(struct device_node *blob)
-- 
1.8.4.2



From renaud.barbier at ge.com  Thu Mar 13 14:10:03 2014
From: renaud.barbier at ge.com (Renaud Barbier)
Date: Thu, 13 Mar 2014 18:10:03 +0000
Subject: [PATCH 5/6] ppc: mpc85xx:gianfar: add stashing support
In-Reply-To: <1394734204-8181-1-git-send-email-renaud.barbier@ge.com>
References: <1394734204-8181-1-git-send-email-renaud.barbier@ge.com>
Message-ID: <1394734204-8181-7-git-send-email-renaud.barbier@ge.com>

The eTSEC 2.0 devices found on the 85xx family of SoCs support stashing
buffer descriptors in the L2 cache. This updates the device tree fixup
for these devices to ensure that the stashing related properties used
by Linux are initialised correctly.

Signed-off-by: Renaud Barbier <renaud.barbier at ge.com>
---
 arch/ppc/mach-mpc85xx/fdt.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/ppc/mach-mpc85xx/fdt.c b/arch/ppc/mach-mpc85xx/fdt.c
index b1da144..1a2d780 100644
--- a/arch/ppc/mach-mpc85xx/fdt.c
+++ b/arch/ppc/mach-mpc85xx/fdt.c
@@ -54,6 +54,14 @@ static void fdt_add_enet_stashing(void *fdt)
 		of_property_write_u32(node, "rx-stash-idx", 0);
 		node = of_find_compatible_node(node, NULL, "gianfar");
 	}
+
+	node = of_find_compatible_node(fdt, NULL, "fsl,etsec2");
+	while (node) {
+		of_set_property(node, "bd-stash", NULL, 0, 1);
+		of_property_write_u32(node, "rx-stash-len", 96);
+		of_property_write_u32(node, "rx-stash-idx", 0);
+		node = of_find_compatible_node(node, NULL, "fsl,etsec2");
+	}
 }
 
 static int fdt_stdout_setup(struct device_node *blob)
-- 
1.8.4.2



From renaud.barbier at ge.com  Thu Mar 13 14:10:00 2014
From: renaud.barbier at ge.com (Renaud Barbier)
Date: Thu, 13 Mar 2014 18:10:00 +0000
Subject: [PATCH 3/6] ppc: mpc8xxx: add DDR3 support
In-Reply-To: <1394734204-8181-1-git-send-email-renaud.barbier@ge.com>
References: <1394734204-8181-1-git-send-email-renaud.barbier@ge.com>
Message-ID: <1394734204-8181-4-git-send-email-renaud.barbier@ge.com>

Add DDR3 support into the MPC8xxx DDR driver.

To avoid confusion, the function set_ddr_sdram_mode is renamed
set_ddr2_sdram_mode.

Checking for errors is simplified in the DDR2 DIMM parameters
computation to be consistent with DDR3.

This code is derived from the files found in directory drivers/ddr/fsl
from U-Boot version git-be937b5.

Signed-off-by: Renaud Barbier <renaud.barbier at ge.com>
---
 arch/ppc/ddr-8xxx/Makefile                         |   4 +-
 arch/ppc/ddr-8xxx/common_timing_params.h           |   2 +
 arch/ppc/ddr-8xxx/ctrl_regs.c                      | 429 +++++++++++++++++++--
 arch/ppc/ddr-8xxx/ddr.h                            |  15 +-
 arch/ppc/ddr-8xxx/ddr2_dimm_params.c               |   9 +-
 arch/ppc/ddr-8xxx/ddr3_dimm_params.c               | 193 +++++++++
 .../ppc/ddr-8xxx/{ddr2_setctrl.c => ddr_setctrl.c} |  44 ++-
 arch/ppc/ddr-8xxx/lc_common_dimm_params.c          | 103 +++--
 arch/ppc/ddr-8xxx/main.c                           |  12 +-
 arch/ppc/ddr-8xxx/options.c                        |  58 ++-
 arch/ppc/include/asm/fsl_ddr_dimm_params.h         |   9 +
 arch/ppc/include/asm/fsl_ddr_sdram.h               |  35 +-
 12 files changed, 813 insertions(+), 100 deletions(-)
 create mode 100644 arch/ppc/ddr-8xxx/ddr3_dimm_params.c
 rename arch/ppc/ddr-8xxx/{ddr2_setctrl.c => ddr_setctrl.c} (53%)

diff --git a/arch/ppc/ddr-8xxx/Makefile b/arch/ppc/ddr-8xxx/Makefile
index 54cb7ce..43ae3a4 100644
--- a/arch/ppc/ddr-8xxx/Makefile
+++ b/arch/ppc/ddr-8xxx/Makefile
@@ -1,2 +1,4 @@
 obj-y	+=  	main.o util.o ctrl_regs.o options.o lc_common_dimm_params.o
-obj-$(CONFIG_FSL_DDR2)	+= ddr2_dimm_params.o ddr2_setctrl.o
+obj-y	+=	ddr_setctrl.o
+obj-$(CONFIG_FSL_DDR2)	+= ddr2_dimm_params.o
+obj-$(CONFIG_FSL_DDR3)	+= ddr3_dimm_params.o
diff --git a/arch/ppc/ddr-8xxx/common_timing_params.h b/arch/ppc/ddr-8xxx/common_timing_params.h
index b262193..85a1e28 100644
--- a/arch/ppc/ddr-8xxx/common_timing_params.h
+++ b/arch/ppc/ddr-8xxx/common_timing_params.h
@@ -23,6 +23,7 @@ struct common_timing_params_s {
 	uint32_t tRRD_ps;	/* maximum = 63750 ps */
 	uint32_t tRC_ps;	/* maximum = 254 ns + .75 ns = 254750 ps */
 	uint32_t refresh_rate_ps;
+	uint32_t extended_op_srt;
 	uint32_t tIS_ps;	/* byte 32, spd->ca_setup */
 	uint32_t tIH_ps;	/* byte 33, spd->ca_hold */
 	uint32_t tDS_ps;	/* byte 34, spd->data_setup */
@@ -36,6 +37,7 @@ struct common_timing_params_s {
 	uint32_t additive_latency;
 	uint32_t all_DIMMs_burst_lengths_bitmask;
 	uint32_t all_DIMMs_registered;
+	uint32_t all_DIMMs_unbuffered;
 	uint32_t all_DIMMs_ECC_capable;
 	uint64_t total_mem;
 	uint64_t base_address;
diff --git a/arch/ppc/ddr-8xxx/ctrl_regs.c b/arch/ppc/ddr-8xxx/ctrl_regs.c
index 1abc826..e3d43ab 100644
--- a/arch/ppc/ddr-8xxx/ctrl_regs.c
+++ b/arch/ppc/ddr-8xxx/ctrl_regs.c
@@ -8,7 +8,7 @@
  */
 
 /*
- * Generic driver for Freescale DDR2 memory controller.
+ * Generic driver for Freescale DDR2/DDR3 memory controller.
  * Based on code from spd_sdram.c
  * Author: James Yang [at freescale.com]
  */
@@ -17,6 +17,33 @@
 #include <asm/fsl_ddr_sdram.h>
 #include "ddr.h"
 
+static uint32_t compute_cas_write_latency(void)
+{
+	uint32_t  cwl;
+	const uint32_t mclk_ps = get_memory_clk_period_ps();
+
+	if (mclk_ps >= 2500)
+		cwl = 5;
+	else if (mclk_ps >= 1875)
+		cwl = 6;
+	else if (mclk_ps >= 1500)
+		cwl = 7;
+	else if (mclk_ps >= 1250)
+		cwl = 8;
+	else if (mclk_ps >= 1070)
+		cwl = 9;
+	else if (mclk_ps >= 935)
+		cwl = 10;
+	else if (mclk_ps >= 833)
+		cwl = 11;
+	else if (mclk_ps >= 750)
+		cwl = 12;
+	else
+		cwl = 12;
+
+	return cwl;
+}
+
 static void set_csn_config(int dimm_number, int i,
 			   struct fsl_ddr_cfg_regs_s *ddr,
 			   const struct memctl_options_s *popts,
@@ -81,40 +108,91 @@ static void set_csn_config(int dimm_number, int i,
 }
 
 static void set_timing_cfg_0(struct fsl_ddr_cfg_regs_s *ddr,
-			     const struct memctl_options_s *popts)
+			     const struct memctl_options_s *popts,
+			     const struct dimm_params_s *dimm)
 {
-	uint32_t trwt_mclk = 0;
-
-	if (popts->trwt_override)
-		trwt_mclk = popts->trwt;
+	uint32_t trwt_mclk = 0, twrt_mclk = 0, act_pd_exit_mclk,
+		 pre_pd_exit_mclk, taxpd_mclk, tmrd_mclk, txp,
+		 data_rate = fsl_get_ddr_freq(0);
+
+	if (popts->sdram_type == SDRAM_TYPE_DDR2) {
+		act_pd_exit_mclk = popts->txard;
+		pre_pd_exit_mclk = popts->txp;
+		taxpd_mclk = popts->taxpd;
+		tmrd_mclk = popts->tmrd;
+	} else {
+		/*
+		 * tXARD is not part of the DDR3 specification, use the
+		 * parameter txp instead of it. That is:
+		 * txp=max(3nCK, 7.5ns).  As well, use tAXPD=1.
+		 */
+		txp = max_t(uint32_t, (get_memory_clk_period_ps() * 3), 7500);
+		data_rate = fsl_get_ddr_freq(0);
+		tmrd_mclk = 4;
+
+		/* for faster clock, need more time for data setup */
+		if (popts->trwt_override)
+			trwt_mclk = popts->trwt;
+		else if (data_rate / 1000000 > 1800)
+			trwt_mclk = 2;
+		else
+			trwt_mclk = 0;
+
+		if (data_rate / 1000000 > 1150)
+			twrt_mclk = 1;
+		else
+			twrt_mclk = 0;
+
+		taxpd_mclk = 1;
+		if (popts->dynamic_power == 0) {
+			act_pd_exit_mclk = 1;
+			pre_pd_exit_mclk = 1;
+		} else {
+			/* act_pd_exit_mclk = tXARD, see above */
+			act_pd_exit_mclk = picos_to_mclk(txp);
+			/* Mode register MR0[A12] is '1' - fast exit */
+			pre_pd_exit_mclk = act_pd_exit_mclk;
+		}
+	}
 
 	ddr->timing_cfg_0 = (((trwt_mclk & 0x3) << 30)
-			     | ((popts->txard & 0x7) << 20)
-			     | ((popts->txp & 0xF) << 16)
-			     | ((popts->taxpd & 0xf) << 8)
-			     | ((popts->tmrd & 0xf) << 0));
+			     | ((twrt_mclk & 0x3) << 28)
+			     | ((act_pd_exit_mclk & 0xf) << 20)
+			     | ((pre_pd_exit_mclk & 0xf) << 16)
+			     | ((taxpd_mclk & 0xf) << 8)
+			     | ((tmrd_mclk & 0x1f) << 0)
+			     );
 }
 
 static void set_timing_cfg_3(struct fsl_ddr_cfg_regs_s *ddr,
+			     const struct memctl_options_s *popts,
 			     const struct common_timing_params_s *dimm,
-			     uint32_t cas_latency)
+			     uint32_t cas_latency, uint32_t additive_latency)
 {
-	uint32_t ext_pretoact, ext_acttopre, ext_acttorw, ext_refrec;
+	uint32_t ext_pretoact, ext_acttopre, ext_acttorw, ext_refrec, ext_wrrec;
 
 	ext_pretoact = picos_to_mclk(dimm->tRP_ps) >> 4;
 	ext_acttopre = picos_to_mclk(dimm->tRAS_ps) >> 4;
 	ext_acttorw = picos_to_mclk(dimm->tRCD_ps) >> 4;
 	cas_latency = ((cas_latency << 1) - 1) >> 4;
+	additive_latency = additive_latency >> 4;
 	ext_refrec = (picos_to_mclk(dimm->tRFC_ps) - 8) >> 4;
+	/* ext_wrrec only deals with 16 clock and above, or 14 with OTF */
+	ext_wrrec = (picos_to_mclk(dimm->tWR_ps) +
+			(popts->otf_burst_chop_en ? 2 : 0)) >> 4;
 
 	ddr->timing_cfg_3 = (((ext_pretoact & 0x1) << 28)
-			     | ((ext_acttopre & 0x2) << 24)
+			     | ((ext_acttopre & 0x3) << 24)
 			     | ((ext_acttorw & 0x1) << 22)
 			     | ((ext_refrec & 0x1F) << 16)
-			     | ((cas_latency & 0x3) << 12));
+			     | ((cas_latency & 0x3) << 12)
+			     | ((additive_latency & 0x1) << 10)
+			     | ((ext_wrrec & 0x1) << 8)
+			     );
 }
 
 static void set_timing_cfg_1(struct fsl_ddr_cfg_regs_s *ddr,
+			     const struct memctl_options_s *popts,
 			     const struct common_timing_params_s *dimm,
 			     uint32_t cas_latency)
 {
@@ -152,10 +230,19 @@ static void set_timing_cfg_1(struct fsl_ddr_cfg_regs_s *ddr,
 	wrrec_mclk = picos_to_mclk(dimm->tWR_ps);
 	if (wrrec_mclk <= 16)
 		wrrec_mclk = wrrec_table[wrrec_mclk - 1];
+	if (popts->otf_burst_chop_en)
+		wrrec_mclk += 2;
 
 	wrtord_mclk = picos_to_mclk(dimm->tWTR_ps);
-	if (wrtord_mclk < 2)
-		wrtord_mclk = 2;
+	if (popts->sdram_type == SDRAM_TYPE_DDR2) {
+		wrtord_mclk = max_t(uint32_t, wrtord_mclk, 2);
+	} else {
+		wrtord_mclk = max_t(uint32_t, wrtord_mclk, 4);
+		acttoact_mclk = max_t(uint32_t, acttoact_mclk, 4);
+	}
+
+	if (popts->otf_burst_chop_en)
+		wrtord_mclk += 2;
 
 	ddr->timing_cfg_1 = (((pretoact_mclk & 0x0F) << 28)
 			     | ((acttopre_mclk & 0x0F) << 24)
@@ -176,11 +263,16 @@ static void set_timing_cfg_2(struct fsl_ddr_cfg_regs_s *ddr,
 
 	cpo = popts->cpo_override;
 	rd_to_pre = picos_to_mclk(dimm->tRTP_ps);
-	if (rd_to_pre < 2)
-		rd_to_pre = 2;
+	if (popts->sdram_type == SDRAM_TYPE_DDR2) {
+		cas_latency = cas_latency - 1;
+		rd_to_pre = max_t(uint32_t, rd_to_pre, 2);
+	} else {
+		cas_latency = compute_cas_write_latency();
+		rd_to_pre = max_t(uint32_t, rd_to_pre, 4);
+	}
 
-	if (additive_latency)
-		rd_to_pre += additive_latency;
+	if (popts->otf_burst_chop_en)
+		rd_to_pre += 2;
 
 	wr_data_delay = popts->write_data_delay;
 	cke_pls = picos_to_mclk(popts->tCKE_clock_pulse_width_ps);
@@ -188,7 +280,7 @@ static void set_timing_cfg_2(struct fsl_ddr_cfg_regs_s *ddr,
 
 	ddr->timing_cfg_2 = (((additive_latency & 0xf) << 28)
 			     | ((cpo & 0x1f) << 23)
-			     | (((cas_latency - 1) & 0xf) << 19)
+			     | ((cas_latency & 0xf) << 19)
 			     | ((rd_to_pre & 7) << 13)
 			     | ((wr_data_delay & 7) << 10)
 			     | ((cke_pls & 0x7) << 6)
@@ -199,7 +291,8 @@ static void set_ddr_sdram_cfg(struct fsl_ddr_cfg_regs_s *ddr,
 			      const struct memctl_options_s *popts,
 			      const struct common_timing_params_s *dimm)
 {
-	uint32_t mem_en, sren, ecc_en, sdram_type, dyn_pwr, dbw, twoT_en, hse;
+	uint32_t mem_en, sren, ecc_en, sdram_type, dyn_pwr, dbw, twoT_en, hse,
+		 threet_en, eight_be = 0;
 
 	mem_en = 1;
 	sren = popts->self_refresh_in_sleep;
@@ -208,15 +301,16 @@ static void set_ddr_sdram_cfg(struct fsl_ddr_cfg_regs_s *ddr,
 	else
 		ecc_en = 0;
 
-	if (popts->sdram_type)
-		sdram_type = popts->sdram_type;
-	else
-		sdram_type = FSL_SDRAM_TYPE;
-
+	sdram_type = popts->sdram_type;
 	twoT_en = popts->twoT_en;
 	dyn_pwr = popts->dynamic_power;
 	dbw = popts->data_bus_width;
 	hse = popts->half_strength_driver_enable;
+	threet_en = popts->threet_en;
+
+	if (sdram_type == SDRAM_TYPE_DDR3)
+		if ((popts->burst_length == DDR_BL8) || (dbw == 1))
+			eight_be = 1;
 
 	ddr->ddr_sdram_cfg = (((mem_en & 0x1) << 31)
 			      | ((sren & 0x1) << 30)
@@ -224,6 +318,8 @@ static void set_ddr_sdram_cfg(struct fsl_ddr_cfg_regs_s *ddr,
 			      | ((sdram_type & 0x7) << 24)
 			      | ((dyn_pwr & 0x1) << 21)
 			      | ((dbw & 0x3) << 19)
+			      | ((eight_be & 0x1) << 18)
+			      | ((threet_en & 0x1) << 16)
 			      | ((twoT_en & 0x1) << 15)
 			      | ((hse & 0x1) << 3));
 }
@@ -232,7 +328,8 @@ static void set_ddr_sdram_cfg_2(struct fsl_ddr_cfg_regs_s *ddr,
 				const struct memctl_options_s *popts)
 {
 	struct ddr_board_info_s *bi = popts->board_info;
-	uint32_t i, dll_rst_dis, dqs_cfg, odt_cfg = 0, num_pr, d_init = 0;
+	uint32_t i, dll_rst_dis, dqs_cfg, odt_cfg = 0, num_pr, d_init = 0,
+		 obc_cfg = 0, x4_en, md_en = 0, rcw_en = 0;
 
 	dll_rst_dis = popts->dll_rst_dis;
 	dqs_cfg = popts->DQS_config;
@@ -256,11 +353,48 @@ static void set_ddr_sdram_cfg_2(struct fsl_ddr_cfg_regs_s *ddr,
 		ddr->ddr_data_init = popts->data_init;
 	}
 
+	if (popts->sdram_type == SDRAM_TYPE_DDR3) {
+		obc_cfg = popts->otf_burst_chop_en;
+		md_en = popts->mirrored_dimm;
+	}
+
+	x4_en = popts->x4_en ? 1 : 0;
+
 	ddr->ddr_sdram_cfg_2 = (((dll_rst_dis & 0x1) << 29)
 				| ((dqs_cfg & 0x3) << 26)
 				| ((odt_cfg & 0x3) << 21)
 				| ((num_pr & 0xf) << 12)
-				| ((d_init & 0x1) << 4));
+				| (x4_en << 10)
+				| ((obc_cfg & 0x1) << 6)
+				| ((d_init & 0x1) << 4)
+				| ((rcw_en & 0x1) << 2)
+				| ((md_en & 0x1) << 0)
+				);
+}
+
+static void set_ddr_sdram_mode_2(struct fsl_ddr_cfg_regs_s *ddr,
+				const struct memctl_options_s *popts,
+				const struct common_timing_params_s *dimm)
+{
+	uint16_t esdmode2;
+	uint32_t rtt_wr, srt = 0, cwl;
+
+	cwl = compute_cas_write_latency() - 5;
+
+	if (popts->rtt_override)
+		rtt_wr = popts->rtt_wr_override_value;
+	else
+		rtt_wr = popts->cs_local_opts[0].odt_rtt_wr;
+
+	if (dimm->extended_op_srt)
+		srt = dimm->extended_op_srt;
+
+	esdmode2 = (((rtt_wr & 0x3) << 9)
+		    | ((srt & 0x1) << 7)
+		    | ((cwl & 0x7) << 3)
+		    );
+
+	ddr->ddr_sdram_mode_2 = (esdmode2 & 0xffff) << 16;
 }
 
 static void
@@ -277,12 +411,107 @@ set_ddr_sdram_interval(struct fsl_ddr_cfg_regs_s *ddr,
 	ddr->ddr_sdram_interval = (((refint & 0xFFFF) << 16)
 				   | ((bstopre & 0x3FFF) << 0));
 }
+void set_ddr3_sdram_mode(struct fsl_ddr_cfg_regs_s *ddr,
+			       const struct memctl_options_s *popts,
+			       const struct common_timing_params_s *dimm,
+			       uint32_t cas_latency, uint32_t additive_latency)
+{
+	uint16_t esdmode, sdmode;
+	/* Mode Register - MR1 */
+	uint32_t rtt, al;
+	/* Mode Register - MR0 */
+	uint32_t dll_on, wr = 0, dll_rst, mode, caslat = 4, bt, bl, wr_mclk;
+	/*
+	 * DDR_SDRAM_MODE doesn't support 9,11,13,15
+	 * Please refer JEDEC Standard No. 79-3E for Mode Register MR0
+	 * for this table
+	 */
+	static const u8 wr_table[] = {1, 2, 3, 4, 5, 5, 6, 6, 7, 7, 0, 0};
+	uint8_t cas_latency_table[] = { /* From 5 to 16 clocks */
+		0x2, 0x4, 0x6, 0x8, 0xa, 0xc, 0xe, 0x1, 0x3, 0x5, 0x7, 0x9,
+	};
+	const unsigned int mclk_ps = get_memory_clk_period_ps();
+
+	if (popts->rtt_override)
+		rtt = popts->rtt_override_value;
+	else
+		rtt = popts->cs_local_opts[0].odt_rtt_norm;
+
+	if (additive_latency == (cas_latency - 1))
+		al = 1;
+	else if (additive_latency == (cas_latency - 2))
+		al = 2;
+	else
+		al = 0;
+
+	/*
+	 * The esdmode value will also be used for writing
+	 * MR1 during write leveling for DDR3, although the
+	 * bits specifically related to the write leveling
+	 * scheme will be handled automatically by the DDR
+	 * controller. So wrlvl_en is set to 0 here.
+	 */
+	esdmode = (((rtt & 0x4) << 7)
+		   | ((rtt & 0x2) << 5)
+		   | ((al & 0x3) << 3)
+		   | ((rtt & 0x1) << 2)
+		   );
 
-static void set_ddr_sdram_mode(struct fsl_ddr_cfg_regs_s *ddr,
+	/*
+	 * DLL control for precharge PD
+	 * 0=slow exit DLL off (tXPDLL)
+	 * 1=fast exit DLL on (tXP)
+	 */
+	dll_on = 1;
+
+	wr_mclk = (dimm->tWR_ps + mclk_ps - 1) / mclk_ps;
+	if (wr_mclk <= 16)
+		wr = wr_table[wr_mclk - 5];
+
+	dll_rst = 0;	/* dll no reset */
+	mode = 0;	/* normal mode */
+
+	/* look up table to get the cas latency bits */
+	if (cas_latency >= 5 && cas_latency <= 16)
+		caslat = cas_latency_table[cas_latency - 5];
+
+	/* BT: Burst Type (0=Nibble Sequential, 1=Interleaved) */
+	bt = 0;
+
+	switch (popts->burst_length) {
+	case DDR_BL8:
+		bl = 0;
+		break;
+	case DDR_OTF:
+		bl = 1;
+		break;
+	case DDR_BC4:
+		bl = 2;
+		break;
+	default:
+		bl = 1;
+		break;
+	}
+
+	sdmode = (((dll_on & 0x1) << 12)
+		  | ((wr & 0x7) << 9)
+		  | ((dll_rst & 0x1) << 8)
+		  | ((mode & 0x1) << 7)
+		  | (((caslat >> 1) & 0x7) << 4)
+		  | ((bt & 0x1) << 3)
+		  | ((caslat & 1) << 2)
+		  | ((bl & 0x3) << 0)
+		  );
+
+	ddr->ddr_sdram_mode = (((esdmode & 0xffff) << 16)
+			       | ((sdmode & 0xffff) << 0)
+			       );
+}
+
+void set_ddr2_sdram_mode(struct fsl_ddr_cfg_regs_s *ddr,
 			       const struct memctl_options_s *popts,
 			       const struct common_timing_params_s *dimm,
-			       uint32_t cas_latency,
-			       uint32_t additive_latency)
+			       uint32_t cas_latency, uint32_t additive_latency)
 {
 	uint16_t esdmode, sdmode;
 	uint32_t dqs_en, rtt, al, wr, bl;
@@ -342,6 +571,19 @@ static void set_ddr_sdram_mode(struct fsl_ddr_cfg_regs_s *ddr,
 			       | ((sdmode & 0xFFFF) << 0));
 }
 
+void set_ddrx_sdram_mode(struct fsl_ddr_cfg_regs_s *ddr,
+			       const struct memctl_options_s *popts,
+			       const struct common_timing_params_s *dimm,
+			       uint32_t cas_latency, uint32_t additive_latency)
+{
+	if (popts->sdram_type == SDRAM_TYPE_DDR2)
+		set_ddr2_sdram_mode(ddr, popts, dimm, cas_latency,
+				additive_latency);
+	else
+		set_ddr3_sdram_mode(ddr, popts, dimm, cas_latency,
+				additive_latency);
+}
+
 uint32_t check_fsl_memctl_config_regs(const struct fsl_ddr_cfg_regs_s *ddr)
 {
 	/*
@@ -355,6 +597,98 @@ uint32_t check_fsl_memctl_config_regs(const struct fsl_ddr_cfg_regs_s *ddr)
 	return 0;
 }
 
+static void set_timing_cfg_4(struct fsl_ddr_cfg_regs_s *ddr,
+		const struct memctl_options_s *popts)
+{
+	uint32_t rrt = 0, wwt = 0, dll_lock = 1;
+
+	if (popts->burst_length != DDR_BL8)
+		rrt = wwt = 2;
+
+	ddr->timing_cfg_4 = (((rrt & 0xf) << 20)
+			     | ((wwt & 0xf) << 16)
+			     | (dll_lock & 0x3)
+			     );
+}
+
+static void set_timing_cfg_5(struct fsl_ddr_cfg_regs_s *ddr,
+				const struct memctl_options_s *popts,
+				uint32_t cas_latency)
+{
+	uint32_t rodt_on, rodt_off = 4, wodt_on = 1, wodt_off = 4;
+
+	/* rodt_on = timing_cfg_1[caslat] - timing_cfg_2[wrlat] + 1 */
+	rodt_on = cas_latency - ((ddr->timing_cfg_2 & 0x00780000) >> 19) + 1;
+
+	ddr->timing_cfg_5 = (((rodt_on & 0x1f) << 24)
+			     | ((rodt_off & 0x7) << 20)
+			     | ((wodt_on & 0x1f) << 12)
+			     | ((wodt_off & 0x7) << 8)
+			     );
+}
+
+static void set_ddr_zq_cntl(struct fsl_ddr_cfg_regs_s *ddr, uint32_t zq_en)
+{
+	uint32_t zqinit = 0, zqoper = 0, zqcs = 0;
+
+	if (zq_en) {
+		zqinit = 9;
+		zqoper = 8;
+		zqcs = 6;
+	}
+
+	ddr->ddr_zq_cntl = (((zq_en & 0x1) << 31)
+			    | ((zqinit & 0xf) << 24)
+			    | ((zqoper & 0xf) << 16)
+			    | ((zqcs & 0xf) << 8)
+			    );
+}
+
+static void set_ddr_wrlvl_cntl(struct fsl_ddr_cfg_regs_s *ddr,
+		uint32_t wrlvl_en, const struct memctl_options_s *popts)
+{
+	uint32_t wrlvl_mrd = 0, wrlvl_odten = 0, wrlvl_dqsen = 0,
+		 wrlvl_wlr = 0, wrlvl_start = 0, wrlvl_smpl = 0;
+
+	/* Enable write leveling for DDR3 due to fly-by topology */
+	if (wrlvl_en) {
+		wrlvl_mrd = 0x6;
+		wrlvl_odten = 0x7;
+		wrlvl_dqsen = 0x5;
+		/*
+		 * Write leveling sample time at least need 6 clocks
+		 * higher than tWLO to allow enough time for progagation
+		 * delay and sampling the prime data bits.
+		 */
+		wrlvl_smpl = 0xf;
+		/*
+		 * Write leveling repetition time. At least tWLO + 6 clocks
+		 * Set it to 64
+		 */
+		wrlvl_wlr = 0x6;
+		/*
+		 * Write leveling start time
+		 * The value use for the DQS_ADJUST for the first sample
+		 * when write leveling is enabled. It probably needs to be
+		 * overriden per platform.
+		 */
+		wrlvl_start = 0x8;
+		if (popts->wrlvl_override) {
+			wrlvl_smpl = popts->wrlvl_sample;
+			wrlvl_start = popts->wrlvl_start;
+		}
+	}
+
+	ddr->ddr_wrlvl_cntl = (((wrlvl_en & 0x1) << 31)
+			       | ((wrlvl_mrd & 0x7) << 24)
+			       | ((wrlvl_odten & 0x7) << 20)
+			       | ((wrlvl_dqsen & 0x7) << 16)
+			       | ((wrlvl_smpl & 0xf) << 12)
+			       | ((wrlvl_wlr & 0x7) << 8)
+			       | ((wrlvl_start & 0x1f) << 0)
+			       );
+}
+
 uint32_t
 compute_fsl_memctl_config_regs(const struct memctl_options_s *popts,
 			       struct fsl_ddr_cfg_regs_s *ddr,
@@ -364,7 +698,7 @@ compute_fsl_memctl_config_regs(const struct memctl_options_s *popts,
 {
 	struct ddr_board_info_s *binfo = popts->board_info;
 	uint32_t cas_latency, additive_latency, i, cs_per_dimm,
-		 dimm_number;
+		 dimm_number, zq_en, wrlvl_en, sr_it = 0;
 	uint64_t ea, sa, rank_density;
 
 	if (dimm == NULL)
@@ -383,6 +717,9 @@ compute_fsl_memctl_config_regs(const struct memctl_options_s *popts,
 	else
 		additive_latency = dimm->additive_latency;
 
+	if (popts->auto_self_refresh_en)
+		sr_it = popts->sr_it;
+
 	/* Chip Select Memory Bounds (CSn_BNDS) */
 	for (i = 0; i < binfo->cs_per_ctrl; i++) {
 		cs_per_dimm = binfo->cs_per_ctrl / binfo->dimm_slots_per_ctrl;
@@ -405,21 +742,37 @@ compute_fsl_memctl_config_regs(const struct memctl_options_s *popts,
 		sa >>= 24;
 		ea >>= 24;
 
-		ddr->cs[i].bnds = (((sa & 0xFFF) << 16) | ((ea & 0xFFF) << 0));
+		ddr->cs[i].bnds =
+			(((sa & 0xffff) << 16) | ((ea & 0xffff) << 0));
 		set_csn_config(dimm_number, i, ddr, popts, dimmp);
 	}
 
-	set_timing_cfg_0(ddr, popts);
-	set_timing_cfg_3(ddr, dimm, cas_latency);
-	set_timing_cfg_1(ddr, dimm, cas_latency);
+	set_timing_cfg_0(ddr, popts, dimmp);
+	set_timing_cfg_3(ddr, popts, dimm, cas_latency, additive_latency);
+	set_timing_cfg_1(ddr, popts, dimm, cas_latency);
 	set_timing_cfg_2(ddr, popts, dimm, cas_latency, additive_latency);
+
+	ddr->ddr_cdr1 = popts->ddr_cdr1;
+	ddr->ddr_cdr1 = popts->ddr_cdr2;
+
 	set_ddr_sdram_cfg(ddr, popts, dimm);
 	set_ddr_sdram_cfg_2(ddr, popts);
-	set_ddr_sdram_mode(ddr, popts, dimm, cas_latency, additive_latency);
+	set_ddrx_sdram_mode(ddr, popts, dimm, cas_latency, additive_latency);
+	if (popts->sdram_type == SDRAM_TYPE_DDR3) {
+		set_ddr_sdram_mode_2(ddr, popts, dimm);
+		set_timing_cfg_4(ddr, popts);
+		set_timing_cfg_5(ddr, popts, cas_latency);
+		zq_en = (popts->zq_en) ? 1 : 0;
+		set_ddr_zq_cntl(ddr, zq_en);
+		wrlvl_en = (popts->wrlvl_en) ? 1 : 0;
+		set_ddr_wrlvl_cntl(ddr, wrlvl_en, popts);
+	}
 	set_ddr_sdram_interval(ddr, popts, dimm);
 
 	ddr->ddr_data_init = popts->data_init;
 	ddr->ddr_sdram_clk_cntl = (popts->clk_adjust & 0xF) << 23;
 
+	ddr->ddr_sr_cntr = (sr_it & 0xf) << 16;
+
 	return check_fsl_memctl_config_regs(ddr);
 }
diff --git a/arch/ppc/ddr-8xxx/ddr.h b/arch/ppc/ddr-8xxx/ddr.h
index 6574500..2ef87f2 100644
--- a/arch/ppc/ddr-8xxx/ddr.h
+++ b/arch/ppc/ddr-8xxx/ddr.h
@@ -47,6 +47,17 @@ struct fsl_ddr_cfg_regs_s {
 	uint32_t ddr_sdram_clk_cntl;
 	uint32_t ddr_init_addr;
 	uint32_t ddr_init_ext_addr;
+	uint32_t timing_cfg_4;
+	uint32_t timing_cfg_5;
+	uint32_t ddr_zq_cntl;
+	uint32_t ddr_wrlvl_cntl;
+	uint32_t ddr_wrlvl_cntl_2;
+	uint32_t ddr_wrlvl_cntl_3;
+	uint32_t ddr_sr_cntr;
+	uint32_t ddr_sdram_rcw_1;
+	uint32_t ddr_sdram_rcw_2;
+	uint32_t ddr_cdr1;
+	uint32_t ddr_cdr2;
 	uint32_t err_disable;
 	uint32_t err_int_en;
 	uint32_t debug[32];
@@ -82,8 +93,8 @@ uint32_t compute_fsl_memctl_config_regs(
 uint32_t compute_dimm_parameters(
 		const generic_spd_eeprom_t *spdin,
 		struct dimm_params_s *pdimm);
-uint32_t compute_lowest_common_dimm_parameters(
-		const struct dimm_params_s *dimm_params,
+void compute_lowest_common_dimm_parameters(
+		const struct fsl_ddr_info_s *pinfo,
 		struct common_timing_params_s *outpdimm,
 		uint32_t number_of_dimms);
 uint32_t populate_memctl_options(
diff --git a/arch/ppc/ddr-8xxx/ddr2_dimm_params.c b/arch/ppc/ddr-8xxx/ddr2_dimm_params.c
index b36a888..cc7f3fa 100644
--- a/arch/ppc/ddr-8xxx/ddr2_dimm_params.c
+++ b/arch/ppc/ddr-8xxx/ddr2_dimm_params.c
@@ -193,17 +193,12 @@ compute_dimm_parameters(const generic_spd_eeprom_t *spdin,
 	const struct ddr2_spd_eeprom_s *spd = spdin;
 	uint32_t retval;
 
-	if (!spd->mem_type) {
-		memset(pdimm, 0, sizeof(struct dimm_params_s));
-		goto error;
-	}
-
 	if (spd->mem_type != SPD_MEMTYPE_DDR2)
 		goto error;
 
 	retval = ddr2_spd_checksum_pass(spd);
 	if (retval)
-		goto spd_err;
+		goto error;
 
 	/*
 	 * The part name in ASCII in the SPD EEPROM is not null terminated.
@@ -298,6 +293,4 @@ compute_dimm_parameters(const generic_spd_eeprom_t *spdin,
 	return 0;
 error:
 	return 1;
-spd_err:
-	return 2;
 }
diff --git a/arch/ppc/ddr-8xxx/ddr3_dimm_params.c b/arch/ppc/ddr-8xxx/ddr3_dimm_params.c
new file mode 100644
index 0000000..d510c5b
--- /dev/null
+++ b/arch/ppc/ddr-8xxx/ddr3_dimm_params.c
@@ -0,0 +1,193 @@
+/*
+ * Copyright 2008-2012 Freescale Semiconductor, Inc.
+ *	Dave Liu <daveliu at freescale.com>
+ *
+ * calculate the organization and timing parameter
+ * from ddr3 spd, please refer to the spec
+ * JEDEC standard No.21-C 4_01_02_11R18.pdf
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <asm/fsl_ddr_sdram.h>
+#include "ddr.h"
+
+/*
+ * Calculate the Density of each Physical Rank.
+ * Returned size is in bytes.
+ *
+ * each rank size =
+ * sdram capacity(bit) / 8 * primary bus width / sdram width
+ *
+ * where: sdram capacity  = spd byte4[3:0]
+ *        primary bus width = spd byte8[2:0]
+ *        sdram width = spd byte7[2:0]
+ *
+ * SPD byte4 - sdram density and banks
+ *	bit[3:0]	size(bit)	size(byte)
+ *	0000		256Mb		32MB
+ *	0001		512Mb		64MB
+ *	0010		1Gb		128MB
+ *	0011		2Gb		256MB
+ *	0100		4Gb		512MB
+ *	0101		8Gb		1GB
+ *	0110		16Gb		2GB
+ *
+ * SPD byte8 - module memory bus width
+ *	bit[2:0]	primary bus width
+ *	000		8bits
+ *	001		16bits
+ *	010		32bits
+ *	011		64bits
+ *
+ * SPD byte7 - module organiztion
+ *	bit[2:0]	sdram device width
+ *	000		4bits
+ *	001		8bits
+ *	010		16bits
+ *	011		32bits
+ */
+static uint64_t compute_ranksize(const struct ddr3_spd_eeprom_s *spd)
+{
+	uint64_t bsize;
+	int sdram_cap_bsize = 0, prim_bus_width = 0, sdram_width = 0;
+
+	if ((spd->density_banks & 0xf) < 7)
+		sdram_cap_bsize = (spd->density_banks & 0xf) + 28;
+	if ((spd->bus_width & 0x7) < 4)
+		prim_bus_width = (spd->bus_width & 0x7) + 3;
+	if ((spd->organization & 0x7) < 4)
+		sdram_width = (spd->organization & 0x7) + 2;
+
+	bsize = 1ULL << (sdram_cap_bsize - 3 + prim_bus_width - sdram_width);
+
+	return bsize;
+}
+
+/*
+ * compute_dimm_parameters for DDR3 SPD
+ *
+ * Compute DIMM parameters based upon the SPD information in spd.
+ * Writes the results to the dimm_params_s structure pointed by pdimm.
+ *
+ */
+uint32_t
+compute_dimm_parameters(const generic_spd_eeprom_t *spdin,
+		struct dimm_params_s *pdimm)
+{
+	const struct ddr3_spd_eeprom_s *spd = spdin;
+	uint32_t retval, mtb_ps;
+	int ftb_tmp;
+
+	if (spd->mem_type != SPD_MEMTYPE_DDR3)
+		goto error;
+
+	retval = ddr3_spd_checksum_pass(spd);
+	if (retval)
+		goto error;
+
+	memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
+	if ((spd->info_size_crc & 0xf) > 1)
+		memcpy(pdimm->mpart, spd->mpart, sizeof(pdimm->mpart) - 1);
+
+	/* DIMM organization parameters */
+	pdimm->n_ranks = ((spd->organization >> 3) & 0x7) + 1;
+	pdimm->rank_density = compute_ranksize(spd);
+	pdimm->capacity = pdimm->n_ranks * pdimm->rank_density;
+	pdimm->data_width = pdimm->primary_sdram_width + pdimm->ec_sdram_width;
+	pdimm->primary_sdram_width = 1 << (3 + (spd->bus_width & 0x7));
+	if ((spd->bus_width >> 3) & 0x3)
+		pdimm->ec_sdram_width = 8;
+	else
+		pdimm->ec_sdram_width = 0;
+	pdimm->device_width = 1 << ((spd->organization & 0x7) + 2);
+
+	/* These are the types defined by the JEDEC DDR3 SPD spec */
+	pdimm->mirrored_dimm = 0;
+	pdimm->registered_dimm = 0;
+	switch (spd->module_type & DDR3_SPD_MODULETYPE_MASK) {
+	case DDR3_SPD_MODULETYPE_UDIMM:
+		/* Unbuffered DIMMs */
+		if (spd->mod_section.unbuffered.addr_mapping & 0x1)
+			pdimm->mirrored_dimm = 1;
+		break;
+
+	default:
+		goto error;
+	}
+
+	/* SDRAM device parameters */
+	pdimm->n_row_addr = ((spd->addressing >> 3) & 0x7) + 12;
+	pdimm->n_col_addr = (spd->addressing & 0x7) + 9;
+	pdimm->n_banks_per_sdram_device =
+			8 << ((spd->density_banks >> 4) & 0x7);
+
+	/*
+	 * The SPD spec does not define an ECC bit. The DIMM is considered
+	 * to have ECC capability if the extension bus exists.
+	 */
+	if (pdimm->ec_sdram_width)
+		pdimm->edc_config = 0x02;
+	else
+		pdimm->edc_config = 0x00;
+
+	/*
+	 * The SPD spec does not define the burst length byte.
+	 * but the DDR3 spec defines BL8 and BC4, on bit 3 and
+	 * bit 2.
+	 */
+	pdimm->burst_lengths_bitmask = 0x0c;
+	pdimm->row_density = __ilog2(pdimm->rank_density);
+
+	mtb_ps = (spd->mtb_dividend * 1000) / spd->mtb_divisor;
+	pdimm->mtb_ps = mtb_ps;
+
+	ftb_tmp = spd->ftb_div & 0xf0;
+	pdimm->ftb_10th_ps = ((ftb_tmp >> 4) * 10) / ftb_tmp;
+
+	pdimm->tCKmin_X_ps = spd->tck_min * mtb_ps +
+		(spd->fine_tck_min * ftb_tmp) / 10;
+	pdimm->caslat_X  = ((spd->caslat_msb << 8) | spd->caslat_lsb) << 4;
+
+	pdimm->taa_ps = spd->taa_min * mtb_ps +
+		(spd->fine_taa_min * ftb_tmp) / 10;
+
+	pdimm->tRCD_ps = spd->trcd_min * mtb_ps +
+		(spd->fine_trcd_min * ftb_tmp) / 10;
+
+	pdimm->tRP_ps = spd->trp_min * mtb_ps +
+		(spd->fine_trp_min * ftb_tmp) / 10;
+	pdimm->tRAS_ps = (((spd->tras_trc_ext & 0xf) << 8) | spd->tras_min_lsb)
+			* mtb_ps;
+	pdimm->tWR_ps = spd->twr_min * mtb_ps;
+	pdimm->tWTR_ps = spd->twtr_min * mtb_ps;
+	pdimm->tRFC_ps = ((spd->trfc_min_msb << 8) | spd->trfc_min_lsb)
+			* mtb_ps;
+	pdimm->tRRD_ps = spd->trrd_min * mtb_ps;
+	pdimm->tRC_ps = (((spd->tras_trc_ext & 0xf0) << 4) | spd->trc_min_lsb);
+	pdimm->tRC_ps *= mtb_ps;
+	pdimm->tRC_ps += (spd->fine_trc_min * ftb_tmp) / 10;
+
+	pdimm->tRTP_ps = spd->trtp_min * mtb_ps;
+
+	/*
+	 * Average periodic refresh interval
+	 * tREFI = 7.8 us at normal temperature range
+	 *       = 3.9 us at ext temperature range
+	 */
+	pdimm->refresh_rate_ps = 7800000;
+	if ((spd->therm_ref_opt & 0x1) && !(spd->therm_ref_opt & 0x2)) {
+		pdimm->refresh_rate_ps = 3900000;
+		pdimm->extended_op_srt = 1;
+	}
+
+	pdimm->tfaw_ps = (((spd->tfaw_msb & 0xf) << 8) | spd->tfaw_min)
+			* mtb_ps;
+
+	return 0;
+error:
+	return 1;
+}
diff --git a/arch/ppc/ddr-8xxx/ddr2_setctrl.c b/arch/ppc/ddr-8xxx/ddr_setctrl.c
similarity index 53%
rename from arch/ppc/ddr-8xxx/ddr2_setctrl.c
rename to arch/ppc/ddr-8xxx/ddr_setctrl.c
index 14571b0..115fb42 100644
--- a/arch/ppc/ddr-8xxx/ddr2_setctrl.c
+++ b/arch/ppc/ddr-8xxx/ddr_setctrl.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2008 Freescale Semiconductor, Inc.
+ * Copyright 2008-2011 Freescale Semiconductor, Inc.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License
@@ -10,12 +10,13 @@
 #include <config.h>
 #include <asm/io.h>
 #include <asm/fsl_ddr_sdram.h>
+#include <asm/processor.h>
 #include <mach/early_udelay.h>
 #include "ddr.h"
 
 int fsl_ddr_set_memctl_regs(const struct fsl_ddr_info_s *info)
 {
-	uint32_t i;
+	uint32_t i, temp_sdram_cfg;
 	void __iomem *ddr;
 	const struct fsl_ddr_cfg_regs_s *regs;
 
@@ -29,6 +30,9 @@ int fsl_ddr_set_memctl_regs(const struct fsl_ddr_info_s *info)
 		out_be32(ddr + DDR_OFF(CS0_BNDS) + (i << 3), regs->cs[i].bnds);
 		out_be32(ddr + DDR_OFF(CS0_CONFIG) + (i << 2),
 				regs->cs[i].config);
+		if (info->memctl_opts.sdram_type == SDRAM_TYPE_DDR3)
+			out_be32(ddr + DDR_OFF(CS0_CONFIG_2) + (i << 2),
+					regs->cs[i].config_2);
 	}
 
 	out_be32(ddr + DDR_OFF(TIMING_CFG_3), regs->timing_cfg_3);
@@ -45,12 +49,40 @@ int fsl_ddr_set_memctl_regs(const struct fsl_ddr_info_s *info)
 	out_be32(ddr + DDR_OFF(SDRAM_INIT_ADDR), regs->ddr_init_addr);
 	out_be32(ddr + DDR_OFF(SDRAM_INIT_ADDR_EXT), regs->ddr_init_ext_addr);
 
-	early_udelay(200);
-	asm volatile("sync;isync");
+	if (info->memctl_opts.sdram_type == SDRAM_TYPE_DDR3) {
+		out_be32(ddr + DDR_OFF(TIMING_CFG_4), regs->timing_cfg_4);
+		out_be32(ddr + DDR_OFF(TIMING_CFG_5), regs->timing_cfg_5);
+		out_be32(ddr + DDR_OFF(ZQ_CNTL), regs->ddr_zq_cntl);
+		out_be32(ddr + DDR_OFF(WRLVL_CNTL), regs->ddr_wrlvl_cntl);
+
+		if (regs->ddr_wrlvl_cntl_2)
+			out_be32(ddr + DDR_OFF(WRLVL_CNTL_2),
+					regs->ddr_wrlvl_cntl_2);
+		if (regs->ddr_wrlvl_cntl_3)
+			out_be32(ddr + DDR_OFF(WRLVL_CNTL_3),
+					regs->ddr_wrlvl_cntl_3);
+
+		out_be32(ddr + DDR_OFF(SR_CNTL), regs->ddr_sr_cntr);
+		out_be32(ddr + DDR_OFF(SDRAM_RCW_1), regs->ddr_sdram_rcw_1);
+		out_be32(ddr + DDR_OFF(SDRAM_RCW_2), regs->ddr_sdram_rcw_2);
+		out_be32(ddr + DDR_OFF(DDRCDR1), regs->ddr_cdr1);
+		out_be32(ddr + DDR_OFF(DDRCDR2), regs->ddr_cdr2);
+	}
 
-	out_be32(ddr + DDR_OFF(SDRAM_CFG), regs->ddr_sdram_cfg);
+	out_be32(ddr + DDR_OFF(ERR_DISABLE), regs->err_disable);
+	out_be32(ddr + DDR_OFF(ERR_INT_EN), regs->err_int_en);
+
+	temp_sdram_cfg = regs->ddr_sdram_cfg;
+	temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN);
+	out_be32(ddr + DDR_OFF(SDRAM_CFG), temp_sdram_cfg);
+
+	early_udelay(500);
+	/* Make sure all instructions are completed before enabling memory.*/
+	asm volatile("sync;isync");
+	temp_sdram_cfg = in_be32(ddr + DDR_OFF(SDRAM_CFG)) & ~SDRAM_CFG_BI;
+	out_be32(ddr + DDR_OFF(SDRAM_CFG), temp_sdram_cfg | SDRAM_CFG_MEM_EN);
+	asm volatile("sync;isync");
 
-	/* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done.  */
 	while (in_be32(ddr + DDR_OFF(SDRAM_CFG_2)) & SDRAM_CFG2_D_INIT)
 		early_udelay(10000);
 
diff --git a/arch/ppc/ddr-8xxx/lc_common_dimm_params.c b/arch/ppc/ddr-8xxx/lc_common_dimm_params.c
index a1addb0..9d90fb7 100644
--- a/arch/ppc/ddr-8xxx/lc_common_dimm_params.c
+++ b/arch/ppc/ddr-8xxx/lc_common_dimm_params.c
@@ -12,6 +12,36 @@
 
 #include "ddr.h"
 
+static uint32_t
+compute_cas_latency_ddr3(const struct dimm_params_s *dimm_params,
+			 uint32_t number_of_dimms)
+{
+	uint32_t i, taamin_ps = 0, tckmin_x_ps = 0, common_caslat,
+		 caslat_actual, retry = 16;
+	const uint32_t mclk_ps = get_memory_clk_period_ps();
+
+	/* compute the common CAS latency supported between slots */
+	common_caslat = dimm_params[0].caslat_X;
+	for (i = 1; i < number_of_dimms; i++) {
+		if (dimm_params[i].n_ranks)
+			common_caslat &= dimm_params[i].caslat_X;
+	}
+
+	for (i = 0; i < number_of_dimms; i++) {
+		taamin_ps = max(taamin_ps, dimm_params[i].taa_ps);
+		tckmin_x_ps = max(tckmin_x_ps, dimm_params[i].tCKmin_X_ps);
+	}
+
+	caslat_actual = (taamin_ps + mclk_ps - 1) / mclk_ps;
+	/* check if the dimms support the CAS latency */
+	while (!(common_caslat & (1 << caslat_actual)) && retry > 0) {
+		caslat_actual++;
+		retry--;
+	}
+
+	return caslat_actual;
+}
+
 static unsigned int common_burst_length(
 		const struct dimm_params_s *dimm_params,
 		const unsigned int number_of_dimms)
@@ -22,7 +52,6 @@ static unsigned int common_burst_length(
 	for (i = 0; i < number_of_dimms; i++)
 		if (dimm_params[i].n_ranks)
 			temp &= dimm_params[i].burst_lengths_bitmask;
-
 	return temp;
 }
 
@@ -115,16 +144,17 @@ static unsigned int compute_lowest_caslat(
  * whose parameters have been computed into the array pointed to
  * by dimm_params.
  */
-unsigned int
-compute_lowest_common_dimm_parameters(const struct dimm_params_s *dimm,
+void compute_lowest_common_dimm_parameters(const struct fsl_ddr_info_s *pinfo,
 				      struct common_timing_params_s *out,
 				      const unsigned int number_of_dimms)
 {
-	const uint32_t mclk_ps = get_memory_clk_period_ps();
 	uint32_t temp1, i;
 	struct common_timing_params_s tmp = {0};
+	const struct dimm_params_s *dimm = pinfo->dimm_params;
+	const struct memctl_options_s *popts = &pinfo->memctl_opts;
 
 	tmp.tCKmax_ps = 0xFFFFFFFF;
+	tmp.extended_op_srt = 1;
 	temp1 = 0;
 	for (i = 0; i < number_of_dimms; i++) {
 		if (dimm[i].n_ranks == 0) {
@@ -157,58 +187,69 @@ compute_lowest_common_dimm_parameters(const struct dimm_params_s *dimm,
 		tmp.tQHS_ps = max(tmp.tQHS_ps, dimm[i].tQHS_ps);
 		tmp.refresh_rate_ps = max(tmp.refresh_rate_ps,
 				dimm[i].refresh_rate_ps);
+		tmp.extended_op_srt = min(tmp.extended_op_srt,
+					dimm[i].extended_op_srt);
 		/* Find maximum tDQSQ_max_ps to find slowest timing. */
 		tmp.tDQSQ_max_ps = max(tmp.tDQSQ_max_ps, dimm[i].tDQSQ_max_ps);
 	}
 	tmp.ndimms_present = number_of_dimms - temp1;
 
 	if (temp1 == number_of_dimms)
-		return 0;
+		return;
 
 	temp1 = common_burst_length(dimm, number_of_dimms);
 	tmp.all_DIMMs_burst_lengths_bitmask = temp1;
-	tmp.all_DIMMs_registered = 0;
 
-	tmp.lowest_common_SPD_caslat = compute_lowest_caslat(dimm,
-			number_of_dimms);
-	/*
-	 * Compute a common 'de-rated' CAS latency.
-	 *
-	 * The strategy here is to find the *highest* de-rated cas latency
-	 * with the assumption that all of the DIMMs will support a de-rated
-	 * CAS latency higher than or equal to their lowest de-rated value.
-	 */
-	temp1 = 0;
-	for (i = 0; i < number_of_dimms; i++)
-		temp1 = max(temp1, dimm[i].caslat_lowest_derated);
-	tmp.highest_common_derated_caslat = temp1;
+	/* Support only unbuffered DIMMs */
+	tmp.all_DIMMs_registered = 0;
+	tmp.all_DIMMs_unbuffered = 1;
+
+	if (popts->sdram_type == SDRAM_TYPE_DDR3) {
+		tmp.lowest_common_SPD_caslat = compute_cas_latency_ddr3(dimm,
+				number_of_dimms);
+	} else {
+		tmp.lowest_common_SPD_caslat = compute_lowest_caslat(dimm,
+				number_of_dimms);
+		/*
+		 * Compute a common 'de-rated' CAS latency.
+		 *
+		 * The strategy here is to find the *highest* de-rated cas
+		 * latency with the assumption that all of the DIMMs will
+		 * support a de-rated CAS latency higher than or equal to
+		 * their lowest de-rated value.
+		 */
+		temp1 = 0;
+		for (i = 0; i < number_of_dimms; i++)
+			temp1 = max(temp1, dimm[i].caslat_lowest_derated);
+		tmp.highest_common_derated_caslat = temp1;
+	}
 
 	temp1 = 1;
 	for (i = 0; i < number_of_dimms; i++)
-		if (dimm[i].n_ranks &&
-		    !(dimm[i].edc_config & EDC_ECC)) {
+		if (dimm[i].n_ranks && !(dimm[i].edc_config & EDC_ECC)) {
 			temp1 = 0;
 			break;
 		}
 	tmp.all_DIMMs_ECC_capable = temp1;
 
-	if (mclk_ps > tmp.tCKmax_max_ps)
-		return 1;
-
 	/*
 	 * AL must be less or equal to tRCD. Typically, AL would
 	 * be AL = tRCD - 1;
 	 *
 	 * When ODT read or write is enabled the sum of CAS latency +
 	 * additive latency must be at least 3 cycles.
-	 *
 	 */
-	if ((tmp.lowest_common_SPD_caslat < 4) && (picos_to_mclk(tmp.tRCD_ps) >
-				tmp.lowest_common_SPD_caslat))
-		tmp.additive_latency = picos_to_mclk(tmp.tRCD_ps) -
-			tmp.lowest_common_SPD_caslat;
+	tmp.additive_latency = 0;
+	if (popts->sdram_type == SDRAM_TYPE_DDR2) {
+		if ((tmp.lowest_common_SPD_caslat < 4) &&
+			(picos_to_mclk(tmp.tRCD_ps) >
+			tmp.lowest_common_SPD_caslat))
+			tmp.additive_latency = picos_to_mclk(tmp.tRCD_ps) -
+					tmp.lowest_common_SPD_caslat;
+
+		if (mclk_to_picos(tmp.additive_latency) > tmp.tRCD_ps)
+			tmp.additive_latency = picos_to_mclk(tmp.tRCD_ps);
+	}
 
 	memcpy(out, &tmp, sizeof(struct common_timing_params_s));
-
-	return 0;
 }
diff --git a/arch/ppc/ddr-8xxx/main.c b/arch/ppc/ddr-8xxx/main.c
index 6e4a02d..99b877b 100644
--- a/arch/ppc/ddr-8xxx/main.c
+++ b/arch/ppc/ddr-8xxx/main.c
@@ -15,6 +15,7 @@
 #include <common.h>
 #include <config.h>
 #include <asm/fsl_law.h>
+#include <asm/fsl_ddr_sdram.h>
 #include "ddr.h"
 
 static int get_spd(generic_spd_eeprom_t *spd,
@@ -143,6 +144,14 @@ static uint32_t compute_dimm_param(struct fsl_ddr_info_s *pinfo, uint32_t ndimm)
 	generic_spd_eeprom_t *spd;
 	uint32_t i, retval;
 
+	spd = &(pinfo->spd_installed_dimms[0]);
+	if (spd->mem_type == SPD_MEMTYPE_DDR3)
+		pinfo->memctl_opts.sdram_type = SDRAM_TYPE_DDR3;
+	else if (spd->mem_type == SPD_MEMTYPE_DDR2)
+		pinfo->memctl_opts.sdram_type = SDRAM_TYPE_DDR2;
+	else
+		return 1;
+
 	for (i = 0; i < ndimm; i++) {
 		spd = &(pinfo->spd_installed_dimms[i]);
 		pdimm = &(pinfo->dimm_params[i]);
@@ -185,8 +194,7 @@ uint64_t fsl_ddr_compute(struct fsl_ddr_info_s *pinfo)
 	 * STEP 3: Compute a common set of timing parameters
 	 * suitable for all of the DIMMs on each memory controller
 	 */
-	compute_lowest_common_dimm_parameters(pinfo->dimm_params,
-			timing_params, ndimm);
+	compute_lowest_common_dimm_parameters(pinfo, timing_params, ndimm);
 
 	/* STEP 4:  Gather configuration requirements from user */
 	populate_memctl_options(timing_params->all_DIMMs_registered,
diff --git a/arch/ppc/ddr-8xxx/options.c b/arch/ppc/ddr-8xxx/options.c
index 9ce2bc1..ccf5d5e 100644
--- a/arch/ppc/ddr-8xxx/options.c
+++ b/arch/ppc/ddr-8xxx/options.c
@@ -46,18 +46,42 @@ uint32_t populate_memctl_options(int all_DIMMs_registered,
 	 * 0 = 64-bit, 1 = 32-bit, 2 = 16-bit
 	 */
 	if (pdimm->n_ranks != 0) {
-		if ((pdimm->data_width >= 64) && (pdimm->data_width <= 72))
-			popts->data_bus_width = 0;
-		else if ((pdimm->data_width >= 32) &&
-			(pdimm->data_width <= 40))
-			popts->data_bus_width = 1;
-		else
-			panic("data width %u is invalid!\n",
-					pdimm->data_width);
+		if (popts->sdram_type == SDRAM_TYPE_DDR3) {
+			if (pdimm[0].primary_sdram_width == 64)
+				popts->data_bus_width = 0;
+			else if (pdimm[0].primary_sdram_width == 32)
+				popts->data_bus_width = 1;
+			else if (pdimm[0].primary_sdram_width == 16)
+				popts->data_bus_width = 2;
+			else
+				hang();
+		} else {
+			if ((pdimm->data_width >= 64) &&
+			      (pdimm->data_width <= 72))
+				popts->data_bus_width = 0;
+			else if ((pdimm->data_width >= 32) &&
+				(pdimm->data_width <= 40))
+				popts->data_bus_width = 1;
+			else
+				hang();
+		}
+	}
+
+	if (popts->sdram_type == SDRAM_TYPE_DDR3) {
+		if (popts->data_bus_width == 0) {
+			popts->otf_burst_chop_en = 1;
+			popts->burst_length = DDR_OTF;
+		} else {
+			/* 32-bit or 16-bit bus */
+			popts->otf_burst_chop_en = 0;
+			popts->burst_length = DDR_BL8;
+		}
+		popts->mirrored_dimm = pdimm[0].mirrored_dimm;
+	} else {
+		/* Must be a burst length of 4 for DDR2 */
+		popts->burst_length = DDR_BL4;
 	}
 
-	/* Must be a burst length of 4 for DD2 */
-	popts->burst_length = DDR_BL4;
 	/* Decide whether to use the computed de-rated latency */
 	popts->use_derated_caslat = 0;
 
@@ -70,6 +94,7 @@ uint32_t populate_memctl_options(int all_DIMMs_registered,
 	 *	- how much time you want to spend playing around
 	 */
 	popts->twoT_en = 0;
+	popts->threet_en = 0;
 
 	/*
 	 * Default BSTTOPRE precharge interval
@@ -90,7 +115,18 @@ uint32_t populate_memctl_options(int all_DIMMs_registered,
 	 * The default value below would work for x4/x8 wide memory.
 	 *
 	 */
-	popts->tFAW_window_four_activates_ps = 37500;
+	if (popts->sdram_type == SDRAM_TYPE_DDR2) {
+		popts->tFAW_window_four_activates_ps = 37500;
+	} else {
+		/*
+		 * Due to ddr3 dimm fly-by topology, enable write leveling
+		 * to meet the tQDSS under different loading.
+		 */
+		popts->tFAW_window_four_activates_ps = pdimm[0].tfaw_ps;
+		popts->wrlvl_en = 1;
+		popts->zq_en = 1;
+		popts->wrlvl_override = 0;
+	}
 
 	/*
 	 * Default powerdown exit timings.
diff --git a/arch/ppc/include/asm/fsl_ddr_dimm_params.h b/arch/ppc/include/asm/fsl_ddr_dimm_params.h
index 73c239b..9e6f6b4 100644
--- a/arch/ppc/include/asm/fsl_ddr_dimm_params.h
+++ b/arch/ppc/include/asm/fsl_ddr_dimm_params.h
@@ -21,6 +21,8 @@ struct dimm_params_s {
 	uint32_t primary_sdram_width;
 	uint32_t ec_sdram_width;
 	uint32_t registered_dimm;
+	uint32_t device_width;
+	/* SDRAM device parameters */
 	uint32_t n_row_addr;
 	uint32_t n_col_addr;
 	uint32_t edc_config;		/* 0 = none, 1 = parity, 2 = ECC */
@@ -28,6 +30,11 @@ struct dimm_params_s {
 	uint32_t burst_lengths_bitmask;	/* BL=4 bit 2, BL=8 = bit 3 */
 	uint32_t row_density;
 	uint64_t base_address;
+	uint32_t mirrored_dimm;
+	uint32_t mtb_ps;
+	uint32_t ftb_10th_ps;
+	uint32_t taa_ps;
+	uint32_t tfaw_ps;
 	/* SDRAM clock periods */
 	uint32_t tCKmin_X_ps;
 	uint32_t tCKmin_X_minus_1_ps;
@@ -48,6 +55,7 @@ struct dimm_params_s {
 	uint32_t tRRD_ps;	/* maximum = 63750 ps */
 	uint32_t tRC_ps;	/* maximum = 254 ns + .75 ns = 254750 ps */
 	uint32_t refresh_rate_ps;
+	uint32_t extended_op_srt;
 	uint32_t tIS_ps;	/* byte 32, spd->ca_setup */
 	uint32_t tIH_ps;	/* byte 33, spd->ca_hold */
 	uint32_t tDS_ps;	/* byte 34, spd->data_setup */
@@ -55,6 +63,7 @@ struct dimm_params_s {
 	uint32_t tRTP_ps;	/* byte 38, spd->trtp */
 	uint32_t tDQSQ_max_ps;	/* byte 44, spd->tdqsq */
 	uint32_t tQHS_ps;	/* byte 45, spd->tqhs */
+	uint32_t rcw[16];
 };
 
 #endif
diff --git a/arch/ppc/include/asm/fsl_ddr_sdram.h b/arch/ppc/include/asm/fsl_ddr_sdram.h
index 444bcbc..8d3bd71 100644
--- a/arch/ppc/include/asm/fsl_ddr_sdram.h
+++ b/arch/ppc/include/asm/fsl_ddr_sdram.h
@@ -19,17 +19,26 @@
 #define SDRAM_TYPE_DDR3    7
 
 #define DDR_BL4	4
+#define DDR_BC4	DDR_BL4
+#define DDR_OTF	6
 #define DDR_BL8	8
 
 #define DDR2_RTT_OFF		0
 #define DDR2_RTT_75_OHM		1
 #define DDR2_RTT_150_OHM	2
 #define DDR2_RTT_50_OHM		3
+#define DDR3_RTT_OFF		0
+#define DDR3_RTT_40_OHM		3
 
-#if defined(CONFIG_FSL_DDR2)
 #define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR	(3)
+#if defined(CONFIG_FSL_DDR2)
 typedef struct ddr2_spd_eeprom_s generic_spd_eeprom_t;
 #define FSL_SDRAM_TYPE	SDRAM_TYPE_DDR2
+#elif defined(CONFIG_FSL_DDR3)
+typedef struct ddr3_spd_eeprom_s generic_spd_eeprom_t;
+#define FSL_SDRAM_TYPE	SDRAM_TYPE_DDR3
+#else
+#error "Undefined or unknown DDR type"
 #endif
 
 #define FSL_DDR_ODT_NEVER		0x0
@@ -121,6 +130,10 @@ struct memctl_options_s {
 	uint32_t dynamic_power;
 	uint32_t data_bus_width;
 	uint32_t burst_length;
+	uint32_t otf_burst_chop_en;
+	uint32_t mirrored_dimm;
+	uint32_t ap_en;
+	uint32_t x4_en;
 	/* Global Timing Parameters */
 	uint32_t cas_latency_override;
 	uint32_t cas_latency_override_value;
@@ -130,16 +143,36 @@ struct memctl_options_s {
 	uint32_t clk_adjust;
 	uint32_t cpo_override;
 	uint32_t write_data_delay;
+	/* Write leveling */
+	uint32_t wrlvl_override;
+	uint32_t wrlvl_sample;
+	uint32_t wrlvl_start;
+	uint32_t wrlvl_ctl_2;
+	uint32_t wrlvl_ctl_3;
 	uint32_t half_strength_driver_enable;
 	uint32_t twoT_en;
+	uint32_t threet_en;
 	uint32_t bstopre;
 	uint32_t tCKE_clock_pulse_width_ps;
 	uint32_t tFAW_window_four_activates_ps;
 	/* Rtt impedance */
 	uint32_t rtt_override;
 	uint32_t rtt_override_value;
+	uint32_t rtt_wr_override_value;
 	/* Automatic self refresh */
 	uint32_t auto_self_refresh_en;
+	uint32_t sr_it;
+	/* ZQ calibration */
+	uint32_t zq_en;
+	/* Write leveling */
+	uint32_t wrlvl_en;
+	/* RCW override for RDIMM */
+	uint32_t rcw_override;
+	uint32_t rcw_1;
+	uint32_t rcw_2;
+	/* control register 1 */
+	uint32_t ddr_cdr1;
+	uint32_t ddr_cdr2;
 	/* read-to-write turnaround */
 	uint32_t trwt_override;
 	uint32_t trwt;
-- 
1.8.4.2



From renaud.barbier at ge.com  Thu Mar 13 14:10:04 2014
From: renaud.barbier at ge.com (Renaud Barbier)
Date: Thu, 13 Mar 2014 18:10:04 +0000
Subject: [PATCH 6/6] ppc: P1022DS: update Kconfig and Makefile
In-Reply-To: <1394734204-8181-1-git-send-email-renaud.barbier@ge.com>
References: <1394734204-8181-1-git-send-email-renaud.barbier@ge.com>
Message-ID: <1394734204-8181-8-git-send-email-renaud.barbier@ge.com>

Kconfig and make files are updated to build the Freescale P1022DS
image.

Signed-off-by: Renaud Barbier <renaud.barbier at ge.com>
---
 arch/ppc/Makefile             |  1 +
 arch/ppc/mach-mpc85xx/Kconfig | 32 ++++++++++++++++++++++++--------
 2 files changed, 25 insertions(+), 8 deletions(-)

diff --git a/arch/ppc/Makefile b/arch/ppc/Makefile
index 87be193..b9b355a 100644
--- a/arch/ppc/Makefile
+++ b/arch/ppc/Makefile
@@ -13,6 +13,7 @@ endif
 
 board-$(CONFIG_MACH_PHYCORE_MPC5200B_TINY)	:= pcm030
 board-$(CONFIG_P2020RDB)			:= freescale-p2020rdb
+board-$(CONFIG_P1022DS)				:= freescale-p1022ds
 board-$(CONFIG_DA923RC)				:= geip-da923rc
 
 machine-$(CONFIG_ARCH_MPC5200)			:= mpc5xxx
diff --git a/arch/ppc/mach-mpc85xx/Kconfig b/arch/ppc/mach-mpc85xx/Kconfig
index d02cf9b..ec5f04c 100644
--- a/arch/ppc/mach-mpc85xx/Kconfig
+++ b/arch/ppc/mach-mpc85xx/Kconfig
@@ -1,7 +1,7 @@
 if ARCH_MPC85XX
 
 config MMU
-	default y if CMD_MEMTEST
+	default y
 
 config BTB
 	bool
@@ -9,13 +9,13 @@ config BTB
 
 config TEXT_BASE
 	hex
-	default 0xeff80000 if P2020RDB
+	default 0xeff80000 if P2020RDB || P1022DS
 	default 0xfff80000 if DA923RC
 
 config RESET_VECTOR_ADDRESS
 	hex
 	default 0xfffffffc if DA923RC
-	default 0xeffffffc if P2020RDB
+	default 0xeffffffc if P2020RDB || P1022DS
 
 config MPC85xx
 	bool
@@ -37,6 +37,11 @@ config P2020RDB
 	help
 	  Say Y here if you are using the Freescale P2020RDB
 
+config P1022DS
+	bool "P1022DS"
+	help
+	  Say Y here if you are using the Freescale P1022DS
+
 config DA923RC
 	bool "DA923RC"
 	help
@@ -44,22 +49,33 @@ config DA923RC
 endchoice
 endif
 
+config FSL_ELBC
+	bool
+	default y if P2020RDB || P1022DS
+
+config DDR_SPD
+	bool
+	select CRC16
+	default y if DA923RC || P1022DS
+
 if P2020RDB
 config P2020
 	bool
 	default y
+endif
 
-config FSL_ELBC
+if P1022DS
+config P1022
 	bool
 	default y
-endif
 
-if DA923RC
-config MPC8544
+config FSL_DDR3
 	bool
 	default y
+endif
 
-config DDR_SPD
+if DA923RC
+config MPC8544
 	bool
 	default y
 
-- 
1.8.4.2



From raespi at icid.cu  Thu Mar 13 15:32:23 2014
From: raespi at icid.cu (raespi)
Date: Thu, 13 Mar 2014 15:32:23 -0400
Subject: problem booting with Micron MT29F8G08ABABAWP ...
Message-ID: <532207C7.9020206@icid.cu>

Hi ... I'm using barebox 2014.02.0 to boot with a clone of the mini2440 
board using the MT29F8G08ABABAWP NAND.

I'm getting the following error:

barebox 2014.02.0 #1 Thu Mar 13 15:28:57 CDT 2014

Board: <NULL>
nand: ONFI param page 0 valid
nand: ONFI flash detected
nand: NAND device: Manufacturer ID: 0x2c, Chip ID: 0x38 (Micron 
MT29F8G08ABABAWP), 1024
nand: No oob scheme defined for oobsize 224
BUG: failure at drivers/mtd/nand/nand_base.c:3357/nand_scan_tail()!
BUG!
no stack data available
DIVN_UPLL0
MPLLVal [M:61h,P:1h,S:2h]
CLKDIVN:7h

After this poing the board gets resetted back to the original point.  I 
can never get to the barebox prompt.

Any ideas on how to fix this ??

Thanks in advance ...



From plagnioj at jcrosoft.com  Thu Mar 13 15:42:52 2014
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Thu, 13 Mar 2014 20:42:52 +0100
Subject: Porting barebox to Novena: misc questions
In-Reply-To: <20140313073817.GR17250@pengutronix.de>
References: <53211233.5070806@kosagi.com>
 <20140313073817.GR17250@pengutronix.de>
Message-ID: <20140313194252.GB6478@ns203013.ovh.net>

On 08:38 Thu 13 Mar     , Sascha Hauer wrote:
> Hi Sean,
> 
> On Thu, Mar 13, 2014 at 10:04:35AM +0800, Sean Cross wrote:
> > Hi,
> > 
> > I've finally managed to get U-Boot's SPL to configure DDR3 and load
> > barebox off of a FAT partition on an i.MX6DL.  I also have a barebox
> > build with most features turned on, and I'm running into a number of
> > problems.  barebox is able to load a zImage off of the FAT partition,
> > set up ATAGs, and jump to it.  So I have the basics done.  But there are
> > lots of little things that aren't working.
> > 
> > When I boot without an Ethernet cable plugged in, the "timeout" command
> > takes a very long time to complete.  It generally freezes at "Hit any
> > key to stop autoboot:  3" and tends to ignore input for around ten
> > seconds.  How can I prevent this from happening, short of compiling out
> > FEC support?
> 
> Are you trying to start from network without a cable plugged in? When I
> start from network without a cable I get:
> 
> running /env/bin/init...
> 
> Hit m for menu or any other key to stop autoboot:  1
> blspec: blspec_scan_directory: net loader/entries
> booting net
> dhcp failed: Network is down
> dhcp: Network is down
> 

I get the same issue on Calao USB keys

this is quite anoying

can we fix it

Best Regards,
J.
> It indeed takes some seconds until we are sure that the link is down.
> That timeout could be reduced, but we must give the phy some time to
> bring up the link.
> 
> Or does this happen when you are not trying to boot from network at all?
> That shouldn't happen. If it does, maybe some automount command triggers
> network accesses.
> 
> > 
> > The "usb" command just hangs the system.  It should at least detect the
> > other ASIX Ethernet port.  I have &usbh1 configured identically to
> > sabrelite.  Is there something else I need to configure?
> 
> This usually means the phys are not configured correctly. Are you
> probing from devicetree?
> 
> > 
> > The "usbserial" command returns "usbserial: No such device".  Like usb,
> > I have &usbotg configured the same as sabrelite.  It doesn't work with
> > dr_mode set to either "host" or "otg".
> 
> Ok, from devicetree it seems. I can say that there shouldn't be any bugs
> in the common usb code preventing your devices from being probed. It
> normally boils down to some usbmisc register setting being wrong.
> 
> > 
> > How can I pass the correct ram size to Linux?  The comment on
> > barebox_arm_entry() notes that "[memsize] doesn't necessarily have to be
> > the full SDRAM", and indeed I notice that barebox hangs if I pass it the
> > full 3840 MB passed from U-Boot.  So I'm currently limiting it to 1GB in
> > my start_imx6dl_kosagi_novena_6dl routine.  Do I need to somehow add the
> > remainder as another bank somewhere?  Or modify the bank size in my
> > kosagi_novena_init() in board.c?
> 
> If you probe from devicetree the correct amount of memory is taken from
> there. If that doesn't work (dynamic amount of memory for example) you
> can set the memory in the devicetree to 0 and call arm_add_mem_device
> instead.
> 
> > 
> > Finally, I was unable to get barebox to boot with MMU support.  For some
> > reason it kept trying to allocate memory just outside of allocated RAM.
> 
> This is related to the wrong memory setup. That should be solved when
> you get that straight.
> 
> >  Is there any benefit to running with the MMU enabled on i.MX6?
> 
> Definitely, yes. barebox runs much faster with MMU enabled.
> 
> Sascha
> 
> -- 
> Pengutronix e.K.                           |                             |
> Industrial Linux Solutions                 | http://www.pengutronix.de/  |
> Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
> Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |
> 
> _______________________________________________
> barebox mailing list
> barebox at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/barebox


From eric at eukrea.com  Thu Mar 13 16:28:10 2014
From: eric at eukrea.com (Eric =?ISO-8859-1?B?QuluYXJk?=)
Date: Thu, 13 Mar 2014 21:28:10 +0100
Subject: problem booting with Micron MT29F8G08ABABAWP ...
In-Reply-To: <532207C7.9020206@icid.cu>
References: <532207C7.9020206@icid.cu>
Message-ID: <20140313212810.4179d0c2@e6520eb>

Hi,

Le Thu, 13 Mar 2014 15:32:23 -0400,
raespi <raespi at icid.cu> a ?crit :
> Hi ... I'm using barebox 2014.02.0 to boot with a clone of the mini2440 
> board using the MT29F8G08ABABAWP NAND.
> 
> I'm getting the following error:
> 
> barebox 2014.02.0 #1 Thu Mar 13 15:28:57 CDT 2014
> 
> Board: <NULL>
> nand: ONFI param page 0 valid
> nand: ONFI flash detected
> nand: NAND device: Manufacturer ID: 0x2c, Chip ID: 0x38 (Micron 
> MT29F8G08ABABAWP), 1024
> nand: No oob scheme defined for oobsize 224
> BUG: failure at drivers/mtd/nand/nand_base.c:3357/nand_scan_tail()!
> BUG!
> no stack data available
> DIVN_UPLL0
> MPLLVal [M:61h,P:1h,S:2h]
> CLKDIVN:7h
> 
> After this poing the board gets resetted back to the original point.  I 
> can never get to the barebox prompt.
> 
> Any ideas on how to fix this ??
> 
you may need to add support for 4k+224 page size to your nand
controller.
For example this was done for i.MX in comit
632c45795065e6a7471ab82be38e808eb6204341

Eric


From s.hauer at pengutronix.de  Thu Mar 13 16:27:20 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Thu, 13 Mar 2014 21:27:20 +0100
Subject: Porting barebox to Novena: misc questions
In-Reply-To: <53218604.6080702@kosagi.com>
References: <53211233.5070806@kosagi.com>
 <20140313073817.GR17250@pengutronix.de>
 <53218604.6080702@kosagi.com>
Message-ID: <20140313202719.GS17250@pengutronix.de>

On Thu, Mar 13, 2014 at 06:18:44PM +0800, Sean Cross wrote:
> On 13/3/14 3:38 PM, Sascha Hauer wrote:
> > Hi Sean,
> > 
> > On Thu, Mar 13, 2014 at 10:04:35AM +0800, Sean Cross wrote:
> >> Hi,
> >>
> >> I've finally managed to get U-Boot's SPL to configure DDR3 and load
> >> barebox off of a FAT partition on an i.MX6DL.  I also have a barebox
> >> build with most features turned on, and I'm running into a number of
> >> problems.  barebox is able to load a zImage off of the FAT partition,
> >> set up ATAGs, and jump to it.  So I have the basics done.  But there are
> >> lots of little things that aren't working.
> >>
> >> When I boot without an Ethernet cable plugged in, the "timeout" command
> >> takes a very long time to complete.  It generally freezes at "Hit any
> >> key to stop autoboot:  3" and tends to ignore input for around ten
> >> seconds.  How can I prevent this from happening, short of compiling out
> >> FEC support?
> > 
> > Are you trying to start from network without a cable plugged in? When I
> > start from network without a cable I get:
> > 
> > running /env/bin/init...
> > 
> > Hit m for menu or any other key to stop autoboot:  1
> > blspec: blspec_scan_directory: net loader/entries
> > booting net
> > dhcp failed: Network is down
> > dhcp: Network is down
> > 
> > It indeed takes some seconds until we are sure that the link is down.
> > That timeout could be reduced, but we must give the phy some time to
> > bring up the link.
> > 
> > Or does this happen when you are not trying to boot from network at all?
> > That shouldn't happen. If it does, maybe some automount command triggers
> > network accesses.
> 
> This was caused by the default environment I imported.  It set
> "ip=dhcp", which I guess caused it to try and obtain an address.  I've
> set it to "ip=none" for now, and the problem has gone away.
> 
> >> The "usb" command just hangs the system.  It should at least detect the
> >> other ASIX Ethernet port.  I have &usbh1 configured identically to
> >> sabrelite.  Is there something else I need to configure?
> > 
> > This usually means the phys are not configured correctly. Are you
> > probing from devicetree?
> 
> I am probing from devicetree.  I don't see phys mentioned anywhere
> except in the imx6qdl.dtsi file, which means that in theory there
> shouldn't be anything for me to modify.

I can try to reproduce this tomorrow on a sabrelite board.

> Board: Kosagi i.MX6DL Novena Board
> detected i.MX6 DualLite revision 1.1
> ERROR: out of memory
> 
> [<5062e9ed>] (unwind_backtrace+0x1/0x74) from [<5061c525>] (panic+0x1d/0x34)
> [<5061c525>] (panic+0x1d/0x34) from [<5061cc27>] (xmemalign+0xf/0x14)
> [<5061cc27>] (xmemalign+0xf/0x14) from [<5062f687>] (mmu_init+0x16b/0x1f8)
> [<5062f687>] (mmu_init+0x16b/0x1f8) from [<50600797>]
> (start_barebox+0x1b/0xd0)
> [<50600797>] (start_barebox+0x1b/0xd0) from [<5062efcd>] (__start+0x91/0xa4)
> [<5062efcd>] (__start+0x91/0xa4) from [<50600005>]
> (__bare_init_start+0x1/0xc)
> ### ERROR ### Please RESET the board ###
> 
> If I also enable early MMU, it hangs much much earlier.  When I dug into
> it, it looked like it was trying to place a TTB just outside of the
> allocated memory region, for some reason.
> 
> This is with me passing SZ_1G to barebox_arm_entry().  If I pass
> something small like SZ_64M, it hangs completely.  If I instead pass it
> SZ_128M, it works just fine, but of course the MMU still doesn't work.

I suspect you have some memory setting that doesn't work in your
.config. Could you post it? Particularly the addresses in your backtrace
are outside the reachable memory (0x10000000 + 1GiB = 0x50000000). This
should not happen. Do you have CONFIG_RELOCATABLE enabled? If not, make
sure CONFIG_ARCH_TEXT_BASE is inside the memory you pass to
barebox_arm_entry(). Otherwise the autodetection for usable malloc area
space might produce wrong results.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From s.hauer at pengutronix.de  Thu Mar 13 16:30:10 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Thu, 13 Mar 2014 21:30:10 +0100
Subject: Porting barebox to Novena: misc questions
In-Reply-To: <20140313194252.GB6478@ns203013.ovh.net>
References: <53211233.5070806@kosagi.com>
 <20140313073817.GR17250@pengutronix.de>
 <20140313194252.GB6478@ns203013.ovh.net>
Message-ID: <20140313203009.GT17250@pengutronix.de>

On Thu, Mar 13, 2014 at 08:42:52PM +0100, Jean-Christophe PLAGNIOL-VILLARD wrote:
> On 08:38 Thu 13 Mar     , Sascha Hauer wrote:
> > Hi Sean,
> > 
> > On Thu, Mar 13, 2014 at 10:04:35AM +0800, Sean Cross wrote:
> > > Hi,
> > > 
> > > I've finally managed to get U-Boot's SPL to configure DDR3 and load
> > > barebox off of a FAT partition on an i.MX6DL.  I also have a barebox
> > > build with most features turned on, and I'm running into a number of
> > > problems.  barebox is able to load a zImage off of the FAT partition,
> > > set up ATAGs, and jump to it.  So I have the basics done.  But there are
> > > lots of little things that aren't working.
> > > 
> > > When I boot without an Ethernet cable plugged in, the "timeout" command
> > > takes a very long time to complete.  It generally freezes at "Hit any
> > > key to stop autoboot:  3" and tends to ignore input for around ten
> > > seconds.  How can I prevent this from happening, short of compiling out
> > > FEC support?
> > 
> > Are you trying to start from network without a cable plugged in? When I
> > start from network without a cable I get:
> > 
> > running /env/bin/init...
> > 
> > Hit m for menu or any other key to stop autoboot:  1
> > blspec: blspec_scan_directory: net loader/entries
> > booting net
> > dhcp failed: Network is down
> > dhcp: Network is down
> > 
> 
> I get the same issue on Calao USB keys
> 
> this is quite anoying
> 
> can we fix it

Well if we try booting from network then we have to wait until it's
clear that there's no link.

It may be that I don't understand the actual problem or issue.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From eric at eukrea.com  Thu Mar 13 16:43:07 2014
From: eric at eukrea.com (Eric =?ISO-8859-1?B?QuluYXJk?=)
Date: Thu, 13 Mar 2014 21:43:07 +0100
Subject: Porting barebox to Novena: misc questions
In-Reply-To: <53211233.5070806@kosagi.com>
References: <53211233.5070806@kosagi.com>
Message-ID: <20140313214307.54dbdad8@e6520eb>

Hi,

Le Thu, 13 Mar 2014 10:04:35 +0800,
Sean Cross <xobs at kosagi.com> a ?crit :
> I've finally managed to get U-Boot's SPL to configure DDR3 and load
> barebox off of a FAT partition on an i.MX6DL.  I also have a barebox
> build with most features turned on, and I'm running into a number of
> problems.  barebox is able to load a zImage off of the FAT partition,
> set up ATAGs, and jump to it.  So I have the basics done.  But there are
> lots of little things that aren't working.
> 
> When I boot without an Ethernet cable plugged in, the "timeout" command
> takes a very long time to complete.  It generally freezes at "Hit any
> key to stop autoboot:  3" and tends to ignore input for around ten
> seconds.  How can I prevent this from happening, short of compiling out
> FEC support?
> 
that's very similar to what I reported here :
http://lists.infradead.org/pipermail/barebox/2014-February/018005.html

I didn't yet had time to investigate more based on Sascha's answer but
that's on my todo list.

Eric


From cristiano_dealti at hotmail.com  Thu Mar 13 16:44:08 2014
From: cristiano_dealti at hotmail.com (Cristiano De Alti)
Date: Thu, 13 Mar 2014 20:44:08 +0000 (UTC)
Subject: i.MX21 ADS NAND flash bad blocks scan. Barebox vs Linux
Message-ID: <loom.20140313T212720-896@post.gmane.org>

Hi,
  I'm probably posting to the wrong list since this is Linux issue.
I'm still trying to revive this old board.

This board has a 64MBi Samsung NAND flash that is detected both by Barebox
(recent snapshot) and Linux 3.4.77.

The issue is that, while the bad blocks scan takes a negligible time on
Barebox, it takes 10 minutes to complete on Linux.
They both detect block 0 as a bad block. This is strange since it is
guaranteed to be good by the manufacturer but I've read the OOB data with
barebox and it's marked ad bad. I found this board in the lab and don't know
how it was used before.

Barebox code, nand_imx.c, and Linux code, mxc_nand.c, are similar but not
identical of course. I also think that Linux code was contributed by
Pengutronix so this is the reason I'm asking here.

I've enabled debug statements in Linux code and added my own statements.
As said, scan completes, everything looks OK but it is very slow.

Maybe someone has an idea.

Ciao





From s.hauer at pengutronix.de  Thu Mar 13 17:26:24 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Thu, 13 Mar 2014 22:26:24 +0100
Subject: Porting barebox to Novena: misc questions
In-Reply-To: <20140313214307.54dbdad8@e6520eb>
References: <53211233.5070806@kosagi.com>
 <20140313214307.54dbdad8@e6520eb>
Message-ID: <20140313212623.GV17250@pengutronix.de>

On Thu, Mar 13, 2014 at 09:43:07PM +0100, Eric B?nard wrote:
> Hi,
> 
> Le Thu, 13 Mar 2014 10:04:35 +0800,
> Sean Cross <xobs at kosagi.com> a ?crit :
> > I've finally managed to get U-Boot's SPL to configure DDR3 and load
> > barebox off of a FAT partition on an i.MX6DL.  I also have a barebox
> > build with most features turned on, and I'm running into a number of
> > problems.  barebox is able to load a zImage off of the FAT partition,
> > set up ATAGs, and jump to it.  So I have the basics done.  But there are
> > lots of little things that aren't working.
> > 
> > When I boot without an Ethernet cable plugged in, the "timeout" command
> > takes a very long time to complete.  It generally freezes at "Hit any
> > key to stop autoboot:  3" and tends to ignore input for around ten
> > seconds.  How can I prevent this from happening, short of compiling out
> > FEC support?
> > 
> that's very similar to what I reported here :
> http://lists.infradead.org/pipermail/barebox/2014-February/018005.html
> 
> I didn't yet had time to investigate more based on Sascha's answer but
> that's on my todo list.

Ok, got it. The following fixes this. Looking at the netconsole it seems
some love is needed. Right now it only seems to work when port and ip
are set in the right order.

Sascha

--------------8<----------------------------------

>From e4616cba4ec41ebc0d9e0419fd094984209ddbd1 Mon Sep 17 00:00:00 2001
From: Sascha Hauer <s.hauer at pengutronix.de>
Date: Thu, 13 Mar 2014 22:09:47 +0100
Subject: [PATCH] netconsole: bail out when no connection is opened

When no connection is opened we should not call into
the networking stack. Otherwise it can happen that we
delay further execution until the network stack detected
a link (or timed out bringing the link up).

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 net/netconsole.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/net/netconsole.c b/net/netconsole.c
index 2ab19de..86a68e1 100644
--- a/net/netconsole.c
+++ b/net/netconsole.c
@@ -81,6 +81,9 @@ static int nc_getc(struct console_device *cdev)
 					struct nc_priv, cdev);
 	unsigned char c;
 
+	if (!priv->con)
+		return 0;
+
 	while (!kfifo_len(priv->fifo))
 		net_poll();
 
@@ -94,6 +97,9 @@ static int nc_tstc(struct console_device *cdev)
 	struct nc_priv *priv = container_of(cdev,
 					struct nc_priv, cdev);
 
+	if (!priv->con)
+		return 0;
+
 	if (priv->busy)
 		return kfifo_len(priv->fifo) ? 1 : 0;
 
-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From plagnioj at jcrosoft.com  Thu Mar 13 23:03:56 2014
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Fri, 14 Mar 2014 04:03:56 +0100
Subject: Porting barebox to Novena: misc questions
In-Reply-To: <20140313203009.GT17250@pengutronix.de>
References: <53211233.5070806@kosagi.com>
 <20140313073817.GR17250@pengutronix.de>
 <20140313194252.GB6478@ns203013.ovh.net>
 <20140313203009.GT17250@pengutronix.de>
Message-ID: <20140314030356.GC6478@ns203013.ovh.net>

On 21:30 Thu 13 Mar     , Sascha Hauer wrote:
> On Thu, Mar 13, 2014 at 08:42:52PM +0100, Jean-Christophe PLAGNIOL-VILLARD wrote:
> > On 08:38 Thu 13 Mar     , Sascha Hauer wrote:
> > > Hi Sean,
> > > 
> > > On Thu, Mar 13, 2014 at 10:04:35AM +0800, Sean Cross wrote:
> > > > Hi,
> > > > 
> > > > I've finally managed to get U-Boot's SPL to configure DDR3 and load
> > > > barebox off of a FAT partition on an i.MX6DL.  I also have a barebox
> > > > build with most features turned on, and I'm running into a number of
> > > > problems.  barebox is able to load a zImage off of the FAT partition,
> > > > set up ATAGs, and jump to it.  So I have the basics done.  But there are
> > > > lots of little things that aren't working.
> > > > 
> > > > When I boot without an Ethernet cable plugged in, the "timeout" command
> > > > takes a very long time to complete.  It generally freezes at "Hit any
> > > > key to stop autoboot:  3" and tends to ignore input for around ten
> > > > seconds.  How can I prevent this from happening, short of compiling out
> > > > FEC support?
> > > 
> > > Are you trying to start from network without a cable plugged in? When I
> > > start from network without a cable I get:
> > > 
> > > running /env/bin/init...
> > > 
> > > Hit m for menu or any other key to stop autoboot:  1
> > > blspec: blspec_scan_directory: net loader/entries
> > > booting net
> > > dhcp failed: Network is down
> > > dhcp: Network is down
> > > 
> > 
> > I get the same issue on Calao USB keys
> > 
> > this is quite anoying
> > 
> > can we fix it
> 
> Well if we try booting from network then we have to wait until it's
> clear that there's no link.
> 
> It may be that I don't understand the actual problem or issue.

I do agree if you try to boot on the network we have to wait the xs of timeout

The problem is that you have now a timeout even beofre the autoboot timeout
and even before to try to boot

I did not investigate further but the problem is there

Best Regards,
J.
> 
> Sascha
> 
> -- 
> Pengutronix e.K.                           |                             |
> Industrial Linux Solutions                 | http://www.pengutronix.de/  |
> Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
> Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From plagnioj at jcrosoft.com  Thu Mar 13 23:13:51 2014
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Fri, 14 Mar 2014 04:13:51 +0100
Subject: Porting barebox to Novena: misc questions
In-Reply-To: <20140313212623.GV17250@pengutronix.de>
References: <53211233.5070806@kosagi.com> <20140313214307.54dbdad8@e6520eb>
 <20140313212623.GV17250@pengutronix.de>
Message-ID: <20140314031351.GD6478@ns203013.ovh.net>

On 22:26 Thu 13 Mar     , Sascha Hauer wrote:
> On Thu, Mar 13, 2014 at 09:43:07PM +0100, Eric B?nard wrote:
> > Hi,
> > 
> > Le Thu, 13 Mar 2014 10:04:35 +0800,
> > Sean Cross <xobs at kosagi.com> a ?crit :
> > > I've finally managed to get U-Boot's SPL to configure DDR3 and load
> > > barebox off of a FAT partition on an i.MX6DL.  I also have a barebox
> > > build with most features turned on, and I'm running into a number of
> > > problems.  barebox is able to load a zImage off of the FAT partition,
> > > set up ATAGs, and jump to it.  So I have the basics done.  But there are
> > > lots of little things that aren't working.
> > > 
> > > When I boot without an Ethernet cable plugged in, the "timeout" command
> > > takes a very long time to complete.  It generally freezes at "Hit any
> > > key to stop autoboot:  3" and tends to ignore input for around ten
> > > seconds.  How can I prevent this from happening, short of compiling out
> > > FEC support?
> > > 
> > that's very similar to what I reported here :
> > http://lists.infradead.org/pipermail/barebox/2014-February/018005.html
> > 
> > I didn't yet had time to investigate more based on Sascha's answer but
> > that's on my todo list.
> 
> Ok, got it. The following fixes this. Looking at the netconsole it seems
> some love is needed. Right now it only seems to work when port and ip
> are set in the right order.

I'm going to give a try on it too later this week

Best Regards,
J.
> 
> Sascha
> 
> --------------8<----------------------------------
> 
> From e4616cba4ec41ebc0d9e0419fd094984209ddbd1 Mon Sep 17 00:00:00 2001
> From: Sascha Hauer <s.hauer at pengutronix.de>
> Date: Thu, 13 Mar 2014 22:09:47 +0100
> Subject: [PATCH] netconsole: bail out when no connection is opened
> 
> When no connection is opened we should not call into
> the networking stack. Otherwise it can happen that we
> delay further execution until the network stack detected
> a link (or timed out bringing the link up).
> 
> Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
> ---
>  net/netconsole.c | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/net/netconsole.c b/net/netconsole.c
> index 2ab19de..86a68e1 100644
> --- a/net/netconsole.c
> +++ b/net/netconsole.c
> @@ -81,6 +81,9 @@ static int nc_getc(struct console_device *cdev)
>  					struct nc_priv, cdev);
>  	unsigned char c;
>  
> +	if (!priv->con)
> +		return 0;
> +
>  	while (!kfifo_len(priv->fifo))
>  		net_poll();
>  
> @@ -94,6 +97,9 @@ static int nc_tstc(struct console_device *cdev)
>  	struct nc_priv *priv = container_of(cdev,
>  					struct nc_priv, cdev);
>  
> +	if (!priv->con)
> +		return 0;
> +
>  	if (priv->busy)
>  		return kfifo_len(priv->fifo) ? 1 : 0;
>  
> -- 
> Pengutronix e.K.                           |                             |
> Industrial Linux Solutions                 | http://www.pengutronix.de/  |
> Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
> Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |
> 
> _______________________________________________
> barebox mailing list
> barebox at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/barebox


From xobs at kosagi.com  Thu Mar 13 23:35:12 2014
From: xobs at kosagi.com (Sean Cross)
Date: Fri, 14 Mar 2014 11:35:12 +0800
Subject: Porting barebox to Novena: misc questions
In-Reply-To: <20140313202719.GS17250@pengutronix.de>
References: <53211233.5070806@kosagi.com>
 <20140313073817.GR17250@pengutronix.de> <53218604.6080702@kosagi.com>
 <20140313202719.GS17250@pengutronix.de>
Message-ID: <532278F0.1040409@kosagi.com>

On 14/3/14 4:27 AM, Sascha Hauer wrote:
> On Thu, Mar 13, 2014 at 06:18:44PM +0800, Sean Cross wrote:
>> On 13/3/14 3:38 PM, Sascha Hauer wrote:
>>> Hi Sean,
>>>
>>> On Thu, Mar 13, 2014 at 10:04:35AM +0800, Sean Cross wrote:
>>>> The "usb" command just hangs the system.  It should at least detect the
>>>> other ASIX Ethernet port.  I have &usbh1 configured identically to
>>>> sabrelite.  Is there something else I need to configure?
>>>
>>> This usually means the phys are not configured correctly. Are you
>>> probing from devicetree?
>>
>> I am probing from devicetree.  I don't see phys mentioned anywhere
>> except in the imx6qdl.dtsi file, which means that in theory there
>> shouldn't be anything for me to modify.
> 
> I can try to reproduce this tomorrow on a sabrelite board.
> 
>> Board: Kosagi i.MX6DL Novena Board
>> detected i.MX6 DualLite revision 1.1
>> ERROR: out of memory
>>
>> [<5062e9ed>] (unwind_backtrace+0x1/0x74) from [<5061c525>] (panic+0x1d/0x34)
>> [<5061c525>] (panic+0x1d/0x34) from [<5061cc27>] (xmemalign+0xf/0x14)
>> [<5061cc27>] (xmemalign+0xf/0x14) from [<5062f687>] (mmu_init+0x16b/0x1f8)
>> [<5062f687>] (mmu_init+0x16b/0x1f8) from [<50600797>]
>> (start_barebox+0x1b/0xd0)
>> [<50600797>] (start_barebox+0x1b/0xd0) from [<5062efcd>] (__start+0x91/0xa4)
>> [<5062efcd>] (__start+0x91/0xa4) from [<50600005>]
>> (__bare_init_start+0x1/0xc)
>> ### ERROR ### Please RESET the board ###
>>
>> If I also enable early MMU, it hangs much much earlier.  When I dug into
>> it, it looked like it was trying to place a TTB just outside of the
>> allocated memory region, for some reason.
>>
>> This is with me passing SZ_1G to barebox_arm_entry().  If I pass
>> something small like SZ_64M, it hangs completely.  If I instead pass it
>> SZ_128M, it works just fine, but of course the MMU still doesn't work.
> 
> I suspect you have some memory setting that doesn't work in your
> .config. Could you post it? Particularly the addresses in your backtrace
> are outside the reachable memory (0x10000000 + 1GiB = 0x50000000). This
> should not happen. Do you have CONFIG_RELOCATABLE enabled? If not, make
> sure CONFIG_ARCH_TEXT_BASE is inside the memory you pass to
> barebox_arm_entry(). Otherwise the autodetection for usable malloc area
> space might produce wrong results.

You're on the right track.  Earlier on I started calling
barebox_arm_entry(0x10000000 + 0x800000, SZ_1G, fdt), because otherwise
it would fail in mysterious ways.  Now that I've got ram passing working
correctly, I've set it back to 0x10000000, and I'm able to get further.
 I've also increased the MALLOC_SIZE from 8MB to 64MB, which has made
some out-of-memory errors go away.

Now, it gets much further, even with CONFIG_MMU_EARLY enabled.  Now it
crashes with an error that I see SabreSD was getting at one point, but
I'm not sure how they resolved it:

Board: Kosagi i.MX6DL Novena Board
detected i.MX6 DualLite revision 1.1
BUG: failure at arch/arm/cpu/mmu.c:122/find_pte()!
BUG!
[<4fa2e9cd>] (unwind_backtrace+0x1/0x74) from [<4fa1c525>] (panic+0x1d/0x34)
[<4fa1c525>] (panic+0x1d/0x34) from [<4fa2f485>] (remap_range+0x29/0x88)
[<4fa2f485>] (remap_range+0x29/0x88) from [<4fa2f751>]
(dma_alloc_coherent+0x2d/0x34)
[<4fa2f751>] (dma_alloc_coherent+0x2d/0x34) from [<4fa0d689>]
(ehci_register+0x41/0xa8)
[<4fa0d689>] (ehci_register+0x41/0xa8) from [<4fa0936f>]
(imx_chipidea_probe+0x123/0x168)
[<4fa0936f>] (imx_chipidea_probe+0x123/0x168) from [<4fa07de7>]
(platform_probe+0x9/0xa)
[<4fa07de7>] (platform_probe+0x9/0xa) from [<4fa07bf9>]
(device_probe+0x11/0x44)
[<4fa07bf9>] (device_probe+0x11/0x44) from [<4fa07c53>]
(match.part.3+0x27/0x30)
[<4fa07c53>] (match.part.3+0x27/0x30) from [<4fa07cb5>]
(register_driver+0x59/0x74)
[<4fa07cb5>] (register_driver+0x59/0x74) from [<4fa00797>]
(start_barebox+0x1b/0xd0)
[<4fa00797>] (start_barebox+0x1b/0xd0) from [<4fa2efbd>] (__start+0xa1/0xb4)
[<4fa2efbd>] (__start+0xa1/0xb4) from [<4fa00005>]
(__bare_init_start+0x1/0xc)
### ERROR ### Please RESET the board ###

It's nice to see a USB error message in there -- it makes me think the
two problems might be related.  However, USB still doesn't work with the
MMU disabled, even after fixing the RAM addresses.

Here is the contents of my .config file:

#
# Automatically generated file; DO NOT EDIT.
# Barebox/arm 2014.03.0 Configuration
#
CONFIG_ARM=y
CONFIG_ARM_LINUX=y

#
# System Type
#
# CONFIG_BUILTIN_DTB is not set
# CONFIG_ARCH_AT91 is not set
# CONFIG_ARCH_BCM2835 is not set
# CONFIG_ARCH_CLPS711X is not set
# CONFIG_ARCH_EP93XX is not set
# CONFIG_ARCH_HIGHBANK is not set
CONFIG_ARCH_IMX=y
# CONFIG_ARCH_MVEBU is not set
# CONFIG_ARCH_MXS is not set
# CONFIG_ARCH_NETX is not set
# CONFIG_ARCH_NOMADIK is not set
# CONFIG_ARCH_OMAP is not set
# CONFIG_ARCH_PXA is not set
# CONFIG_ARCH_SOCFPGA is not set
# CONFIG_ARCH_S3C24xx is not set
# CONFIG_ARCH_S5PCxx is not set
# CONFIG_ARCH_S3C64xx is not set
# CONFIG_ARCH_VERSATILE is not set
# CONFIG_ARCH_VEXPRESS is not set
# CONFIG_ARCH_TEGRA is not set
# CONFIG_ARCH_ZYNQ is not set

#
# Processor Type
#
CONFIG_CPU_32=y
CONFIG_CPU_V7=y
CONFIG_CPU_32v7=y

#
# processor features
#
# CONFIG_BOOT_ENDIANNESS_SWITCH is not set
CONFIG_ARCH_TEXT_BASE=0x00908400
CONFIG_BAREBOX_MAX_IMAGE_SIZE=0xffffffff
CONFIG_ARCH_IMX_IMXIMAGE=y

#
# Freescale i.MX System-on-Chip
#
CONFIG_ARCH_IMX6=y
CONFIG_IMX_MULTI_BOARDS=y
# CONFIG_MACH_TX25 is not set
# CONFIG_MACH_EFIKA_MX_SMARTBOOK is not set
# CONFIG_MACH_FREESCALE_MX51_PDK is not set
# CONFIG_MACH_FREESCALE_MX53_LOCO is not set
# CONFIG_MACH_TQMA53 is not set
# CONFIG_MACH_FREESCALE_MX53_VMX53 is not set
# CONFIG_MACH_PHYTEC_PFLA02 is not set
# CONFIG_MACH_DFI_FS700_M60 is not set
# CONFIG_MACH_GUF_SANTARO is not set
# CONFIG_MACH_REALQ7 is not set
# CONFIG_MACH_GK802 is not set
CONFIG_MACH_KOSAGI_NOVENA=y
# CONFIG_MACH_TQMA6X is not set
# CONFIG_MACH_SABRELITE is not set
# CONFIG_MACH_SABRESD is not set
# CONFIG_MACH_NITROGEN6X is not set
# CONFIG_MACH_SOLIDRUN_HUMMINGBOARD is not set
# CONFIG_MACH_UDOO is not set

#
# Board specific settings
#

#
# i.MX specific settings
#
CONFIG_ARCH_IMX_USBLOADER=y
# CONFIG_IMX_IIM is not set
CONFIG_IMX_OCOTP=y
CONFIG_ARM_ASM_UNIFIED=y
CONFIG_AEABI=y
CONFIG_THUMB2_BAREBOX=y
# CONFIG_ARM_BOARD_APPEND_ATAG is not set

#
# Arm specific settings
#
CONFIG_CMD_ARM_CPUINFO=y
CONFIG_CMD_ARM_MMUINFO=y
# CONFIG_CPU_V7_DCACHE_SKIP is not set
CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
CONFIG_ARM_EXCEPTIONS=y
CONFIG_ARM_UNWIND=y
CONFIG_DEFCONFIG_LIST="$ARCH_DEFCONFIG"
CONFIG_GREGORIAN_CALENDER=y
CONFIG_HAS_KALLSYMS=y
CONFIG_HAS_MODULES=y
CONFIG_CMD_MEMORY=y
CONFIG_ENV_HANDLING=y
CONFIG_GENERIC_GPIO=y
CONFIG_BOOTM=y
CONFIG_BLOCK=y
CONFIG_BLOCK_WRITE=y
CONFIG_FILETYPE=y
CONFIG_BINFMT=y
CONFIG_UIMAGE=y
CONFIG_GLOBALVAR=y
CONFIG_STDDEV=y
CONFIG_BAREBOX_UPDATE=y

#
# General Settings
#
CONFIG_LOCALVERSION=""
CONFIG_LOCALVERSION_AUTO=y
CONFIG_BANNER=y
CONFIG_MEMINFO=y
CONFIG_ENVIRONMENT_VARIABLES=y

#
# memory layout
#
CONFIG_HAVE_PBL_IMAGE=y
CONFIG_HAVE_PBL_MULTI_IMAGES=y
CONFIG_HAVE_IMAGE_COMPRESSION=y
CONFIG_PBL_IMAGE=y
CONFIG_PBL_MULTI_IMAGES=y
CONFIG_PBL_RELOCATABLE=y
CONFIG_IMAGE_COMPRESSION=y
# CONFIG_IMAGE_COMPRESSION_LZ4 is not set
CONFIG_IMAGE_COMPRESSION_LZO=y
# CONFIG_IMAGE_COMPRESSION_GZIP is not set
# CONFIG_IMAGE_COMPRESSION_NONE is not set
CONFIG_MMU=y
CONFIG_MMU_EARLY=y
CONFIG_HAVE_CONFIGURABLE_TEXT_BASE=y
CONFIG_TEXT_BASE=0x17800000
CONFIG_BAREBOX_MAX_PBL_SIZE=0xffffffff
CONFIG_BAREBOX_MAX_BARE_INIT_SIZE=0xffffffff
CONFIG_STACK_SIZE=0x400000
CONFIG_MALLOC_SIZE=0x4000000
CONFIG_BROKEN=y
CONFIG_EXPERIMENTAL=y
# CONFIG_MALLOC_DLMALLOC is not set
CONFIG_MALLOC_TLSF=y
# CONFIG_MODULES is not set
CONFIG_KALLSYMS=y
CONFIG_RELOCATABLE=y
# CONFIG_PANIC_HANG is not set
CONFIG_PROMPT="barebox:"
CONFIG_BAUDRATE=115200
CONFIG_LONGHELP=y
CONFIG_CBSIZE=128
CONFIG_SHELL_HUSH=y
# CONFIG_SHELL_SIMPLE is not set
# CONFIG_SHELL_NONE is not set
CONFIG_GLOB=y
CONFIG_GLOB_SORT=y
CONFIG_PROMPT_HUSH_PS2="> "
CONFIG_HUSH_FANCY_PROMPT=y
CONFIG_HUSH_GETOPT=y
CONFIG_CMDLINE_EDITING=y
CONFIG_AUTO_COMPLETE=y
CONFIG_MENU=y
CONFIG_PASSWORD=y
CONFIG_PASSWORD_DEFAULT=""
CONFIG_PASSWD_SUM_MD5=y
# CONFIG_PASSWD_SUM_SHA1 is not set
# CONFIG_PASSWD_SUM_SHA256 is not set
CONFIG_DYNAMIC_CRC_TABLE=y
CONFIG_ERRNO_MESSAGES=y
CONFIG_TIMESTAMP=y
CONFIG_BLSPEC=y
CONFIG_KERNEL_INSTALL_TARGET=y
CONFIG_CONSOLE_FULL=y
# CONFIG_CONSOLE_SIMPLE is not set
# CONFIG_CONSOLE_NONE is not set
# CONFIG_CONSOLE_ACTIVATE_FIRST is not set
CONFIG_CONSOLE_ACTIVATE_ALL=y
# CONFIG_CONSOLE_ACTIVATE_NONE is not set
CONFIG_PARTITION=y
CONFIG_PARTITION_DISK=y
CONFIG_PARTITION_DISK_DOS=y
CONFIG_PARTITION_DISK_EFI=y
CONFIG_PARTITION_DISK_EFI_GPT_NO_FORCE=y
CONFIG_PARTITION_DISK_EFI_GPT_COMPARE=y
CONFIG_DEFAULT_ENVIRONMENT=y
# CONFIG_DEFAULT_COMPRESSION_GZIP is not set
CONFIG_DEFAULT_COMPRESSION_LZO=y
# CONFIG_DEFAULT_COMPRESSION_NONE is not set
CONFIG_HAVE_DEFAULT_ENVIRONMENT_NEW=y
CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y
CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW_DFU=y
CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/kosagi-novena/env"
CONFIG_BAREBOXENV_TARGET=y
CONFIG_BAREBOXCRC32_TARGET=y
CONFIG_POLLER=y
CONFIG_RESET_SOURCE=y

#
# Debugging
#
CONFIG_COMPILE_LOGLEVEL=6
CONFIG_DEFAULT_LOGLEVEL=7
# CONFIG_DEBUG_INFO is not set
# CONFIG_DEBUG_LL is not set
CONFIG_DEBUG_IMX_UART_PORT=1
# CONFIG_DEBUG_INITCALLS is not set
CONFIG_HAS_DEBUG_LL=y
CONFIG_COMMAND_SUPPORT=y
# CONFIG_HAS_POWEROFF is not set

#
# commands
#

#
# scripting
#
CONFIG_CMD_EDIT=y
CONFIG_CMD_SLEEP=y
CONFIG_CMD_MSLEEP=y
CONFIG_CMD_SAVEENV=y
CONFIG_CMD_LOADENV=y
CONFIG_CMD_EXPORT=y
CONFIG_CMD_PRINTENV=y
CONFIG_CMD_READLINE=y
CONFIG_CMD_READF=y
CONFIG_CMD_LET=y
CONFIG_CMD_TRUE=y
CONFIG_CMD_FALSE=y
CONFIG_CMD_MENU=y
CONFIG_CMD_MENU_MANAGEMENT=y
CONFIG_CMD_LOGIN=y
CONFIG_CMD_PASSWD=y
# CONFIG_PASSWD_MODE_HIDE is not set
CONFIG_PASSWD_MODE_STAR=y
# CONFIG_PASSWD_MODE_CLEAR is not set
CONFIG_CMD_TIME=y
CONFIG_CMD_GLOBAL=y

#
# file commands
#
CONFIG_CMD_LS=y
CONFIG_CMD_RM=y
CONFIG_CMD_CAT=y
CONFIG_CMD_MKDIR=y
CONFIG_CMD_RMDIR=y
CONFIG_CMD_CP=y
CONFIG_CMD_PWD=y
CONFIG_CMD_CD=y
CONFIG_CMD_MOUNT=y
CONFIG_CMD_UMOUNT=y
CONFIG_CMD_AUTOMOUNT=y
CONFIG_CMD_BASENAME=y
CONFIG_CMD_DIRNAME=y
CONFIG_CMD_LN=y
CONFIG_CMD_READLINK=y
CONFIG_CMD_FILETYPE=y

#
# console
#
CONFIG_CMD_CLEAR=y
CONFIG_CMD_ECHO=y
CONFIG_CMD_ECHO_E=y

#
# memory
#
CONFIG_CMD_LOADB=y
CONFIG_CMD_LOADY=y
CONFIG_CMD_LOADS=y
CONFIG_CMD_SAVES=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_IOMEM=y
CONFIG_CMD_MD=y
CONFIG_CMD_MW=y
CONFIG_CMD_MM=y
CONFIG_CMD_MEMCMP=y
CONFIG_CMD_MEMCPY=y
CONFIG_CMD_MEMSET=y
CONFIG_CMD_CRC=y
CONFIG_CMD_CRC_CMP=y
CONFIG_CMD_DIGEST=y
CONFIG_CMD_MD5SUM=y
CONFIG_CMD_SHA1SUM=y
CONFIG_CMD_SHA256SUM=y
CONFIG_CMD_SHA224SUM=y

#
# flash
#
CONFIG_CMD_FLASH=y

#
# booting
#
CONFIG_CMD_BOOTM=y
CONFIG_CMD_BOOTM_SHOW_TYPE=y
CONFIG_CMD_BOOTM_VERBOSE=y
CONFIG_CMD_BOOTM_INITRD=y
CONFIG_CMD_BOOTM_OFTREE=y
CONFIG_CMD_BOOTM_OFTREE_UIMAGE=y
CONFIG_CMD_BOOTM_AIMAGE=y
CONFIG_CMD_UIMAGE=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_BOOTU=y
CONFIG_FLEXIBLE_BOOTARGS=y
CONFIG_CMD_BOOT=y
CONFIG_CMD_RESET=y
CONFIG_CMD_GO=y
CONFIG_CMD_OFTREE=y
CONFIG_CMD_OF_PROPERTY=y
CONFIG_CMD_OF_NODE=y

#
# testing
#
CONFIG_CMD_MEMTEST=y

#
# video command
#
CONFIG_CMD_SPLASH=y
CONFIG_CMD_BAREBOX_UPDATE=y
CONFIG_CMD_TIMEOUT=y
CONFIG_CMD_PARTITION=y
CONFIG_CMD_TEST=y
CONFIG_CMD_VERSION=y
CONFIG_CMD_HELP=y
CONFIG_CMD_MAGICVAR=y
CONFIG_CMD_MAGICVAR_HELP=y
CONFIG_CMD_DEVINFO=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_UNCOMPRESS=y
CONFIG_CMD_I2C=y
CONFIG_CMD_SPI=y
CONFIG_CMD_LED=y
CONFIG_CMD_LED_TRIGGER=y
CONFIG_CMD_USB=y
CONFIG_CMD_CLK=y
CONFIG_CMD_DETECT=y
CONFIG_CMD_WD=y
CONFIG_CMD_WD_DEFAULT_TIMOUT=0
CONFIG_NET=y
CONFIG_NET_DHCP=y
CONFIG_NET_NFS=y
CONFIG_NET_PING=y
CONFIG_NET_NETCONSOLE=y
CONFIG_NET_RESOLV=y
CONFIG_NET_IFUP=y
CONFIG_NET_CMD_IFUP=y

#
# Drivers
#
CONFIG_OFTREE=y
CONFIG_OFTREE_MEM_GENERIC=y
CONFIG_DTC=y
CONFIG_OFDEVICE=y
CONFIG_OF_NET=y
CONFIG_OF_GPIO=y
CONFIG_OF_BAREBOX_DRIVERS=y

#
# serial drivers
#
# CONFIG_DRIVER_SERIAL_ARM_DCC is not set
CONFIG_DRIVER_SERIAL_IMX=y
# CONFIG_DRIVER_SERIAL_NS16550 is not set
# CONFIG_DRIVER_SERIAL_CADENCE is not set
CONFIG_ARCH_HAS_FEC_IMX=y

#
# Network drivers
#
# CONFIG_DRIVER_NET_CALXEDA_XGMAC is not set
# CONFIG_DRIVER_NET_DESIGNWARE is not set
# CONFIG_DRIVER_NET_ETHOC is not set
# CONFIG_DRIVER_NET_FEC_IMX is not set
# CONFIG_DRIVER_NET_KS8851_MLL is not set
# CONFIG_DRIVER_NET_MICREL is not set
# CONFIG_DRIVER_NET_SMC911X is not set
# CONFIG_DRIVER_NET_SMC91111 is not set

#
# phylib
#
# CONFIG_NET_USB is not set

#
# SPI drivers
#
CONFIG_SPI=y
CONFIG_DRIVER_SPI_IMX=y
CONFIG_DRIVER_SPI_IMX_2_3=y
CONFIG_I2C=y
CONFIG_I2C_ALGOBIT=y

#
# I2C Hardware Bus support
#
CONFIG_I2C_GPIO=y
CONFIG_I2C_IMX=y
# CONFIG_MTD is not set
CONFIG_DISK=y
CONFIG_DISK_WRITE=y

#
# drive types
#
CONFIG_DISK_ATA=y
CONFIG_DISK_AHCI=y
CONFIG_DISK_AHCI_IMX=y

#
# interface types
#
# CONFIG_DISK_INTF_PLATFORM_IDE is not set
CONFIG_USB=y
CONFIG_USB_IMX_CHIPIDEA=y
CONFIG_USB_IMX_PHY=y
CONFIG_USB_EHCI=y
CONFIG_USB_ULPI=y
CONFIG_USB_STORAGE=y
CONFIG_USB_HAVE_GADGET_DRIVER=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_DUALSPEED=y
CONFIG_USB_GADGET_DRIVER_ARC=y

#
# USB Gadget drivers
#
CONFIG_USB_GADGET_DFU=y
CONFIG_USB_GADGET_SERIAL=y
CONFIG_VIDEO=y
CONFIG_DRIVER_VIDEO_SIMPLEFB=y
CONFIG_MCI=y

#
# --- Feature list ---
#
CONFIG_MCI_STARTUP=y
CONFIG_MCI_INFO=y
CONFIG_MCI_WRITE=y
CONFIG_MCI_MMC_BOOT_PARTITIONS=y

#
# --- MCI host drivers ---
#
# CONFIG_MCI_DW is not set
CONFIG_MCI_IMX_ESDHC=y
# CONFIG_MCI_IMX_ESDHC_PIO is not set
# CONFIG_MCI_SPI is not set
CONFIG_HAVE_CLK=y
CONFIG_CLKDEV_LOOKUP=y
CONFIG_COMMON_CLK=y

#
# MFD
#
# CONFIG_MFD_LP3972 is not set
# CONFIG_MFD_MC13XXX is not set
# CONFIG_MFD_MC34704 is not set
# CONFIG_MFD_MC9SDZ60 is not set
CONFIG_MFD_STMPE=y
CONFIG_MFD_SYSCON=y
# CONFIG_MFD_TWL4030 is not set
# CONFIG_MFD_TWL6030 is not set

#
# Misc devices
#
CONFIG_JTAG=y
CONFIG_SRAM=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
CONFIG_LED_PWM=y
CONFIG_LED_GPIO_OF=y
# CONFIG_LED_GPIO_RGB is not set
# CONFIG_LED_GPIO_BICOLOR is not set
CONFIG_LED_TRIGGERS=y

#
# EEPROM support
#
# CONFIG_EEPROM_AT25 is not set
# CONFIG_EEPROM_AT24 is not set

#
# Input device support
#
CONFIG_KEYBOARD_GPIO=y
# CONFIG_KEYBOARD_IMX_KEYPAD is not set
# CONFIG_KEYBOARD_QT1070 is not set
CONFIG_WATCHDOG_IMX_RESET_SOURCE=y
CONFIG_WATCHDOG=y
CONFIG_WATCHDOG_IMX=y
CONFIG_PWM=y
CONFIG_PWM_IMX=y

#
# DMA support
#
CONFIG_MXS_APBH_DMA=y
CONFIG_GPIOLIB=y

#
# GPIO
#
CONFIG_GPIO_GENERIC=y
CONFIG_GPIO_GENERIC_PLATFORM=y
CONFIG_GPIO_IMX=y
# CONFIG_GPIO_OMAP is not set
CONFIG_GPIO_STMPE=y
# CONFIG_GPIO_DESIGNWARE is not set
# CONFIG_W1 is not set
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX_IOMUX_V3=y
CONFIG_PINCTRL_SINGLE=y

#
# Bus devices
#
CONFIG_IMX_WEIM=y

#
# Filesystem support
#
CONFIG_FS=y
CONFIG_FS_AUTOMOUNT=y
CONFIG_FS_CRAMFS=y
CONFIG_FS_EXT4=y
CONFIG_FS_RAMFS=y
CONFIG_FS_DEVFS=y
# CONFIG_FS_TFTP is not set
# CONFIG_FS_NFS is not set
CONFIG_FS_FAT=y
CONFIG_FS_FAT_WRITE=y
CONFIG_FS_FAT_LFN=y
# CONFIG_FS_BPKFS is not set
CONFIG_FS_UIMAGEFS=y

#
# Library routines
#
CONFIG_PARAMETER=y
CONFIG_UNCOMPRESS=y
CONFIG_ZLIB=y
# CONFIG_BZLIB is not set
# CONFIG_LZ4_DECOMPRESS is not set
# CONFIG_GENERIC_FIND_NEXT_BIT is not set
CONFIG_PROCESS_ESCAPE_SEQUENCE=y
CONFIG_LZO_DECOMPRESS=y
CONFIG_QSORT=y
CONFIG_XYMODEM=y
CONFIG_STMP_DEVICE=y

#
# Library gui routines
#
CONFIG_IMAGE_RENDERER=y
CONFIG_BMP=y
# CONFIG_PNG is not set
CONFIG_CRC32=y
CONFIG_CRC16=y
CONFIG_DIGEST=y
CONFIG_MD5=y
CONFIG_SHA1=y
CONFIG_SHA224=y
CONFIG_SHA256=y



From s.hauer at pengutronix.de  Fri Mar 14 04:18:53 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 14 Mar 2014 09:18:53 +0100
Subject: [PATCH] ARM: MMU: Add some debugging aids and hints
Message-ID: <1394785133-21262-1-git-send-email-s.hauer@pengutronix.de>

- If we have no memory registered in mmu_init() it's a critical bug.
  panic in this case.
- If we do not have a ttb when dma_alloc_coherent or remap_range is
  called it's also a critical bug. Panic in this case.
- if find_pte is called with an address outside our memory banks dump
  the memory banks and the address to give more clue what went wrong.

Also add some hints what might went wrong to the code.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/cpu/mmu.c | 57 ++++++++++++++++++++++++++++++++++++++++++++++++++++--
 1 file changed, 55 insertions(+), 2 deletions(-)

diff --git a/arch/arm/cpu/mmu.c b/arch/arm/cpu/mmu.c
index fae83f3..84daa3d 100644
--- a/arch/arm/cpu/mmu.c
+++ b/arch/arm/cpu/mmu.c
@@ -92,6 +92,17 @@ uint32_t mmu_get_pte_uncached_flags()
 	return pte_flags_uncached;
 }
 
+static void arm_mmu_not_initialized_error(void)
+{
+	/*
+	 * This means:
+	 * - one of the MMU functions like dma_alloc_coherent
+	 *   or remap_range is called too early, before the MMU is initialized
+	 * - Or the MMU initialization has failed earlier
+	 */
+	panic("MMU not initialized\n");
+}
+
 /*
  * Create a second level translation table for the given virtual address.
  * We initially create a flat uncached mapping on it.
@@ -104,6 +115,9 @@ static u32 *arm_create_pte(unsigned long virt)
 
 	table = memalign(0x400, 0x400);
 
+	if (!ttb)
+		arm_mmu_not_initialized_error();
+
 	ttb[virt >> 20] = (unsigned long)table | PMD_TYPE_TABLE;
 
 	for (i = 0; i < 256; i++) {
@@ -118,8 +132,26 @@ static u32 *find_pte(unsigned long adr)
 {
 	u32 *table;
 
-	if ((ttb[adr >> 20] & PMD_TYPE_MASK) != PMD_TYPE_TABLE)
+	if (!ttb)
+		arm_mmu_not_initialized_error();
+
+	if ((ttb[adr >> 20] & PMD_TYPE_MASK) != PMD_TYPE_TABLE) {
+		struct memory_bank *bank;
+		int i = 0;
+
+		/*
+		 * This should only be called for page mapped memory inside our
+		 * memory banks. It's a bug to call it with section mapped memory
+		 * locations.
+		 */
+		pr_crit("%s: TTB for address 0x%08lx is not of type table\n",
+				__func__, adr);
+		pr_crit("Memory banks:\n");
+		for_each_memory_bank(bank)
+			pr_crit("#%d 0x%08lx - 0x%08lx\n", i, bank->start,
+					bank->start + bank->size - 1);
 		BUG();
+	}
 
 	/* find the coarse page table base address */
 	table = (u32 *)(ttb[adr >> 20] & ~0x3ff);
@@ -268,6 +300,15 @@ static int mmu_init(void)
 	struct memory_bank *bank;
 	int i;
 
+	if (list_empty(&memory_banks))
+		/*
+		 * If you see this it means you have no memory registered.
+		 * This can be done either with arm_add_mem_device() in an
+		 * initcall prior to mmu_initcall or via devicetree in the
+		 * memory node.
+		 */
+		panic("MMU: No memory bank found! Cannot continue\n");
+
 	arm_set_cache_functions();
 
 	if (cpu_architecture() >= CPU_ARCH_ARMv7) {
@@ -279,13 +320,25 @@ static int mmu_init(void)
 	}
 
 	if (get_cr() & CR_M) {
+		/*
+		 * Early MMU code has already enabled the MMU. We assume a
+		 * flat 1:1 section mapping in this case.
+		 */
 		asm volatile ("mrc  p15,0,%0,c2,c0,0" : "=r"(ttb));
 
 		/* Clear unpredictable bits [13:0] */
 		ttb = (unsigned long *)((unsigned long)ttb & ~0x3fff);
 
 		if (!request_sdram_region("ttb", (unsigned long)ttb, SZ_16K))
-			pr_err("Error: Can't request SDRAM region for ttb at %p\n", ttb);
+			/*
+			 * This can mean that:
+			 * - the early MMU code has put the ttb into a place
+			 *   which we don't have inside our available memory
+			 * - Somebody else has occupied the ttb region which means
+			 *   the ttb will get corrupted.
+			 */
+			pr_crit("Critical Error: Can't request SDRAM region for ttb at %p\n",
+					ttb);
 	} else {
 		ttb = memalign(0x10000, 0x4000);
 	}
-- 
1.9.0



From s.hauer at pengutronix.de  Fri Mar 14 04:22:52 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 14 Mar 2014 09:22:52 +0100
Subject: Porting barebox to Novena: misc questions
In-Reply-To: <532278F0.1040409@kosagi.com>
References: <53211233.5070806@kosagi.com>
 <20140313073817.GR17250@pengutronix.de>
 <53218604.6080702@kosagi.com>
 <20140313202719.GS17250@pengutronix.de>
 <532278F0.1040409@kosagi.com>
Message-ID: <20140314082252.GW17250@pengutronix.de>

On Fri, Mar 14, 2014 at 11:35:12AM +0800, Sean Cross wrote:
> On 14/3/14 4:27 AM, Sascha Hauer wrote:
> > On Thu, Mar 13, 2014 at 06:18:44PM +0800, Sean Cross wrote:
> >> On 13/3/14 3:38 PM, Sascha Hauer wrote:
> >>> Hi Sean,
> >>>
> >>> On Thu, Mar 13, 2014 at 10:04:35AM +0800, Sean Cross wrote:
> >>>> The "usb" command just hangs the system.  It should at least detect the
> >>>> other ASIX Ethernet port.  I have &usbh1 configured identically to
> >>>> sabrelite.  Is there something else I need to configure?
> >>>
> >>> This usually means the phys are not configured correctly. Are you
> >>> probing from devicetree?
> >>
> >> I am probing from devicetree.  I don't see phys mentioned anywhere
> >> except in the imx6qdl.dtsi file, which means that in theory there
> >> shouldn't be anything for me to modify.
> > 
> > I can try to reproduce this tomorrow on a sabrelite board.
> > 
> >> Board: Kosagi i.MX6DL Novena Board
> >> detected i.MX6 DualLite revision 1.1
> >> ERROR: out of memory
> >>
> >> [<5062e9ed>] (unwind_backtrace+0x1/0x74) from [<5061c525>] (panic+0x1d/0x34)
> >> [<5061c525>] (panic+0x1d/0x34) from [<5061cc27>] (xmemalign+0xf/0x14)
> >> [<5061cc27>] (xmemalign+0xf/0x14) from [<5062f687>] (mmu_init+0x16b/0x1f8)
> >> [<5062f687>] (mmu_init+0x16b/0x1f8) from [<50600797>]
> >> (start_barebox+0x1b/0xd0)
> >> [<50600797>] (start_barebox+0x1b/0xd0) from [<5062efcd>] (__start+0x91/0xa4)
> >> [<5062efcd>] (__start+0x91/0xa4) from [<50600005>]
> >> (__bare_init_start+0x1/0xc)
> >> ### ERROR ### Please RESET the board ###
> >>
> >> If I also enable early MMU, it hangs much much earlier.  When I dug into
> >> it, it looked like it was trying to place a TTB just outside of the
> >> allocated memory region, for some reason.
> >>
> >> This is with me passing SZ_1G to barebox_arm_entry().  If I pass
> >> something small like SZ_64M, it hangs completely.  If I instead pass it
> >> SZ_128M, it works just fine, but of course the MMU still doesn't work.
> > 
> > I suspect you have some memory setting that doesn't work in your
> > .config. Could you post it? Particularly the addresses in your backtrace
> > are outside the reachable memory (0x10000000 + 1GiB = 0x50000000). This
> > should not happen. Do you have CONFIG_RELOCATABLE enabled? If not, make
> > sure CONFIG_ARCH_TEXT_BASE is inside the memory you pass to
> > barebox_arm_entry(). Otherwise the autodetection for usable malloc area
> > space might produce wrong results.
> 
> You're on the right track.  Earlier on I started calling
> barebox_arm_entry(0x10000000 + 0x800000, SZ_1G, fdt), because otherwise
> it would fail in mysterious ways.  Now that I've got ram passing working
> correctly, I've set it back to 0x10000000, and I'm able to get further.
>  I've also increased the MALLOC_SIZE from 8MB to 64MB, which has made
> some out-of-memory errors go away.
> 
> Now, it gets much further, even with CONFIG_MMU_EARLY enabled.  Now it
> crashes with an error that I see SabreSD was getting at one point, but
> I'm not sure how they resolved it:
> 
> Board: Kosagi i.MX6DL Novena Board
> detected i.MX6 DualLite revision 1.1
> BUG: failure at arch/arm/cpu/mmu.c:122/find_pte()!
> BUG!

This can mean that dma_alloc_coherent() is called too early, before
mmu_init(). That's quite unlikely since the chipidea probe is in
device_initcall, way after mmu_initcall. Other possibility is that
mmu_init failed due to missing memory banks.

Please apply "ARM: MMU: Add some debugging aids and hints" I just sent
to the list. It adds more sanity checks and hopefully gives more clue
what is wrong.

> CONFIG_PBL_IMAGE=y
> CONFIG_PBL_MULTI_IMAGES=y
> CONFIG_PBL_RELOCATABLE=y
> CONFIG_IMAGE_COMPRESSION=y
> # CONFIG_IMAGE_COMPRESSION_LZ4 is not set
> CONFIG_IMAGE_COMPRESSION_LZO=y
> # CONFIG_IMAGE_COMPRESSION_GZIP is not set
> # CONFIG_IMAGE_COMPRESSION_NONE is not set
> CONFIG_MMU=y
> CONFIG_MMU_EARLY=y
> CONFIG_HAVE_CONFIGURABLE_TEXT_BASE=y
> CONFIG_TEXT_BASE=0x17800000
> CONFIG_BAREBOX_MAX_PBL_SIZE=0xffffffff
> CONFIG_BAREBOX_MAX_BARE_INIT_SIZE=0xffffffff
> CONFIG_STACK_SIZE=0x400000

This is too much 0x8000 should be enough.

> CONFIG_MALLOC_SIZE=0x4000000

You can also set this to 0x0 in which case barebox will pick a memory
region inside available SDRAM.

Your stack size / malloc size settings shouldn't make problems though.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From s.hauer at pengutronix.de  Fri Mar 14 06:10:03 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 14 Mar 2014 11:10:03 +0100
Subject: [PATCH] ifup: set serverip to provided value when doing dhcp
Message-ID: <1394791803-20192-1-git-send-email-s.hauer@pengutronix.de>

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 net/ifup.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/net/ifup.c b/net/ifup.c
index 3b89ce1..7b63136 100644
--- a/net/ifup.c
+++ b/net/ifup.c
@@ -95,6 +95,9 @@ int ifup(const char *name, unsigned flags)
 		ret = run_command("dhcp");
 		if (ret)
 			goto out;
+		ret = eth_set_param(dev, "serverip");
+		if (ret)
+			goto out;
 	} else if (!strcmp(ip, "static")) {
 		for (i = 0; i < ARRAY_SIZE(vars); i++) {
 			ret = eth_set_param(dev, vars[i]);
-- 
1.9.0



From s.hauer at pengutronix.de  Fri Mar 14 06:11:48 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 14 Mar 2014 11:11:48 +0100
Subject: [PATCH] splash: Print error message when no renderer is found
Message-ID: <1394791908-22061-1-git-send-email-s.hauer@pengutronix.de>

the splash command silently fails when no renderer is found for
an image type. Print an error message in this case.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 lib/gui/image_renderer.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/lib/gui/image_renderer.c b/lib/gui/image_renderer.c
index 78e5777..9c92983 100644
--- a/lib/gui/image_renderer.c
+++ b/lib/gui/image_renderer.c
@@ -23,6 +23,8 @@ static struct image_renderer *get_renderer(void* buf, size_t bufsize)
 			return ir;
 	}
 
+	printf("No renderer found for filetype %s\n", file_type_to_string(type));
+
 	return NULL;
 }
 
-- 
1.9.0



From s.hauer at pengutronix.de  Fri Mar 14 09:30:16 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 14 Mar 2014 14:30:16 +0100
Subject: [PATCH 2/6] ARM: pfla02: Drop unnecessary compilation of flash headers
In-Reply-To: <1394803820-29277-1-git-send-email-s.hauer@pengutronix.de>
References: <1394803820-29277-1-git-send-email-s.hauer@pengutronix.de>
Message-ID: <1394803820-29277-3-git-send-email-s.hauer@pengutronix.de>

They are unused.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/boards/phytec-phyflex-imx6/Makefile | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/arch/arm/boards/phytec-phyflex-imx6/Makefile b/arch/arm/boards/phytec-phyflex-imx6/Makefile
index 93e7308..01c7a25 100644
--- a/arch/arm/boards/phytec-phyflex-imx6/Makefile
+++ b/arch/arm/boards/phytec-phyflex-imx6/Makefile
@@ -1,5 +1,2 @@
 obj-y += board.o
-obj-y += flash-header-phytec-pfla02-1gib.dcd.o flash-header-phytec-pfla02-2gib.dcd.o
-extra-y += flash-header-phytec-pfla02-1gib.dcd.S flash-header-phytec-pfla02-2gib.dcd.S
-extra-y += flash-header-phytec-pfla02-1gib.dcd flash-header-phytec-pfla02-2gib.dcd
 lwl-y += lowlevel.o
-- 
1.9.0



From s.hauer at pengutronix.de  Fri Mar 14 09:30:15 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 14 Mar 2014 14:30:15 +0100
Subject: [PATCH 1/6] ARM: i.MX6Q: Fix IOMUXC GPR1 bit 21 (ENET_CLK_SEL)
In-Reply-To: <1394803820-29277-1-git-send-email-s.hauer@pengutronix.de>
References: <1394803820-29277-1-git-send-email-s.hauer@pengutronix.de>
Message-ID: <1394803820-29277-2-git-send-email-s.hauer@pengutronix.de>

From: Philipp Zabel <p.zabel at pengutronix.de>

This bit selects whether the ENET_REF_CLK is sourced from the internal
ENET PLL (ANATOP), or from an external clock source connected to the
GPIO_16 pad.

Signed-off-by: Philipp Zabel <p.zabel at pengutronix.de>
---
 include/mfd/imx6q-iomuxc-gpr.h | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/include/mfd/imx6q-iomuxc-gpr.h b/include/mfd/imx6q-iomuxc-gpr.h
index db43d59..53efc63 100644
--- a/include/mfd/imx6q-iomuxc-gpr.h
+++ b/include/mfd/imx6q-iomuxc-gpr.h
@@ -103,9 +103,9 @@
 #define IMX6Q_GPR1_EXC_MON_MASK			BIT(22)
 #define IMX6Q_GPR1_EXC_MON_OKAY			0x0
 #define IMX6Q_GPR1_EXC_MON_SLVE			BIT(22)
-#define IMX6Q_GPR1_MIPI_IPU2_SEL_MASK		BIT(21)
-#define IMX6Q_GPR1_MIPI_IPU2_SEL_GASKET		0x0
-#define IMX6Q_GPR1_MIPI_IPU2_SEL_IOMUX		BIT(21)
+#define IMX6Q_GPR1_ENET_CLK_SEL_MASK		BIT(21)
+#define IMX6Q_GPR1_ENET_CLK_SEL_PAD		0
+#define IMX6Q_GPR1_ENET_CLK_SEL_ANATOP		BIT(21)
 #define IMX6Q_GPR1_MIPI_IPU1_MUX_MASK		BIT(20)
 #define IMX6Q_GPR1_MIPI_IPU1_MUX_GASKET		0x0
 #define IMX6Q_GPR1_MIPI_IPU1_MUX_IOMUX		BIT(20)
-- 
1.9.0



From s.hauer at pengutronix.de  Fri Mar 14 09:30:14 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 14 Mar 2014 14:30:14 +0100
Subject: Phytec phyFLEX i.MX6 patches
Message-ID: <1394803820-29277-1-git-send-email-s.hauer@pengutronix.de>

The following adds support for more board variants of the Phytec
phyFLEX i.MX6 board along with some fixes.

Sascha

----------------------------------------------------------------
Christian Hemp (4):
      ARM: pfla02: add 4GB version
      ARM: pfla02: Set ODT to recommended setting
      ARM: pfla02: Add support for DualLite and Solo core
      ARM: pfla02: Set new ethernet phy tx timings

Philipp Zabel (1):
      ARM: i.MX6Q: Fix IOMUXC GPR1 bit 21 (ENET_CLK_SEL)

Sascha Hauer (1):
      ARM: pfla02: Drop unnecessary compilation of flash headers

 arch/arm/boards/phytec-phyflex-imx6/Makefile       |   3 -
 arch/arm/boards/phytec-phyflex-imx6/board.c        |  26 ++-
 .../flash-header-phytec-pfla02-1gib.imxcfg         |   2 +-
 .../flash-header-phytec-pfla02-2gib.imxcfg         |   2 +-
 .../flash-header-phytec-pfla02-4gib.imxcfg         |   6 +
 .../flash-header-phytec-pfla02.h                   |   6 +-
 .../flash-header-phytec-pfla02dl-1gib.imxcfg       |   6 +
 .../flash-header-phytec-pfla02dl.h                 |  95 ++++++++++
 .../flash-header-phytec-pfla02s-512mb.imxcfg       |   6 +
 arch/arm/boards/phytec-phyflex-imx6/lowlevel.c     |  47 +++++
 arch/arm/dts/Makefile                              |   4 +-
 arch/arm/dts/imx6dl-phytec-pbab01.dts              |  29 +++
 arch/arm/dts/imx6dl-phytec-pfla02.dtsi             |  41 ++++
 arch/arm/dts/imx6q-phytec-pbab01.dts               |  23 +--
 arch/arm/dts/imx6q-phytec-pfla02.dtsi              | 207 +--------------------
 arch/arm/dts/imx6qdl-phytec-pbab01.dtsi            |  43 +++++
 arch/arm/dts/imx6qdl-phytec-pfla02.dtsi            | 171 +++++++++++++++++
 arch/arm/dts/imx6s-phytec-pbab01.dts               |  25 +++
 arch/arm/dts/imx6s-phytec-pfla02.dtsi              |  22 +++
 arch/arm/mach-imx/Kconfig                          |   2 +-
 images/Makefile.imx                                |  18 ++
 include/mfd/imx6q-iomuxc-gpr.h                     |   6 +-
 22 files changed, 549 insertions(+), 241 deletions(-)
 create mode 100644 arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02-4gib.imxcfg
 create mode 100644 arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02dl-1gib.imxcfg
 create mode 100644 arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02dl.h
 create mode 100644 arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02s-512mb.imxcfg
 create mode 100644 arch/arm/dts/imx6dl-phytec-pbab01.dts
 create mode 100644 arch/arm/dts/imx6dl-phytec-pfla02.dtsi
 create mode 100644 arch/arm/dts/imx6qdl-phytec-pbab01.dtsi
 create mode 100644 arch/arm/dts/imx6qdl-phytec-pfla02.dtsi
 create mode 100644 arch/arm/dts/imx6s-phytec-pbab01.dts
 create mode 100644 arch/arm/dts/imx6s-phytec-pfla02.dtsi


From s.hauer at pengutronix.de  Fri Mar 14 09:30:20 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 14 Mar 2014 14:30:20 +0100
Subject: [PATCH 6/6] ARM: pfla02: Set new ethernet phy tx timings
In-Reply-To: <1394803820-29277-1-git-send-email-s.hauer@pengutronix.de>
References: <1394803820-29277-1-git-send-email-s.hauer@pengutronix.de>
Message-ID: <1394803820-29277-7-git-send-email-s.hauer@pengutronix.de>

From: Christian Hemp <c.hemp at phytec.de>

TX_CLK line is approx. 54mm longer than other TX lines which adds
a delay of 0.36ns. RGMII need a delay of min. 1.0ns. This mean we have to add
a delay of 0.64ns. We choose 0.78 to have a little gap. This can be done by
setting GTX pad skew value to 11100
 => Set register 2.8 (RGMII Clock Pad Skew) to 0x038F.

Signed-off-by: Christian Hemp <c.hemp at phytec.de>
---
 arch/arm/boards/phytec-phyflex-imx6/board.c | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/arch/arm/boards/phytec-phyflex-imx6/board.c b/arch/arm/boards/phytec-phyflex-imx6/board.c
index f510407..3db88da 100644
--- a/arch/arm/boards/phytec-phyflex-imx6/board.c
+++ b/arch/arm/boards/phytec-phyflex-imx6/board.c
@@ -21,6 +21,9 @@
 #include <gpio.h>
 #include <init.h>
 #include <of.h>
+#include <fec.h>
+
+#include <linux/micrel_phy.h>
 
 #include <mach/imx6.h>
 
@@ -36,6 +39,21 @@ static int eth_phy_reset(void)
 	return 0;
 }
 
+static void mmd_write_reg(struct phy_device *dev, int device, int reg, int val)
+{
+	phy_write(dev, 0x0d, device);
+	phy_write(dev, 0x0e, reg);
+	phy_write(dev, 0x0d, (1 << 14) | device);
+	phy_write(dev, 0x0e, val);
+}
+
+static int ksz9031rn_phy_fixup(struct phy_device *dev)
+{
+	mmd_write_reg(dev, 2, 8, 0x039F);
+
+	return 0;
+}
+
 static int phytec_pfla02_init(void)
 {
 	if (!of_machine_is_compatible("phytec,imx6q-pfla02") &&
@@ -44,6 +62,8 @@ static int phytec_pfla02_init(void)
 		return 0;
 
 	eth_phy_reset();
+	phy_register_fixup_for_uid(PHY_ID_KSZ9031, MICREL_PHY_ID_MASK,
+					   ksz9031rn_phy_fixup);
 
 	return 0;
 }
-- 
1.9.0



From s.hauer at pengutronix.de  Fri Mar 14 09:30:17 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 14 Mar 2014 14:30:17 +0100
Subject: [PATCH 3/6] ARM: pfla02: add 4GB version
In-Reply-To: <1394803820-29277-1-git-send-email-s.hauer@pengutronix.de>
References: <1394803820-29277-1-git-send-email-s.hauer@pengutronix.de>
Message-ID: <1394803820-29277-4-git-send-email-s.hauer@pengutronix.de>

From: Christian Hemp <c.hemp at phytec.de>

Signed-off-by: Christian Hemp <c.hemp at phytec.de>
---
 .../flash-header-phytec-pfla02-1gib.imxcfg                |  2 +-
 .../flash-header-phytec-pfla02-2gib.imxcfg                |  2 +-
 .../flash-header-phytec-pfla02-4gib.imxcfg                |  6 ++++++
 .../phytec-phyflex-imx6/flash-header-phytec-pfla02.h      |  2 +-
 arch/arm/boards/phytec-phyflex-imx6/lowlevel.c            | 15 +++++++++++++++
 images/Makefile.imx                                       |  6 ++++++
 6 files changed, 30 insertions(+), 3 deletions(-)
 create mode 100644 arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02-4gib.imxcfg

diff --git a/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02-1gib.imxcfg b/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02-1gib.imxcfg
index 524ebca..d73207c 100644
--- a/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02-1gib.imxcfg
+++ b/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02-1gib.imxcfg
@@ -1,5 +1,5 @@
 
-#define SETUP_1GIB_2GIB			\
+#define SETUP_1GIB_2GIB_4GIB		\
 	wm 32 0x021b0040 0x00000017;	\
 	wm 32 0x021b0000 0xc21a0000
 
diff --git a/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02-2gib.imxcfg b/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02-2gib.imxcfg
index bf6e0ab..2291b71 100644
--- a/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02-2gib.imxcfg
+++ b/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02-2gib.imxcfg
@@ -1,5 +1,5 @@
 
-#define SETUP_1GIB_2GIB			\
+#define SETUP_1GIB_2GIB_4GIB		\
 	wm 32 0x021b0040 0x00000027;	\
 	wm 32 0x021b0000 0xC31A0000
 
diff --git a/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02-4gib.imxcfg b/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02-4gib.imxcfg
new file mode 100644
index 0000000..c6dc775
--- /dev/null
+++ b/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02-4gib.imxcfg
@@ -0,0 +1,6 @@
+
+#define SETUP_1GIB_2GIB_4GIB             \
+        wm 32 0x021b0040 0x00000047;    \
+        wm 32 0x021b0000 0xC41A0000
+
+#include "flash-header-phytec-pfla02.h"
diff --git a/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02.h b/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02.h
index b90f7cb..138ae36 100644
--- a/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02.h
+++ b/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02.h
@@ -60,7 +60,7 @@ wm 32 0x021b0030 0x005b0e21
 wm 32 0x021b0008 0x09444040
 wm 32 0x021b0004 0x00025576
 
-SETUP_1GIB_2GIB
+SETUP_1GIB_2GIB_4GIB
 
 wm 32 0x021b001c 0x04088032
 wm 32 0x021b001c 0x0408803a
diff --git a/arch/arm/boards/phytec-phyflex-imx6/lowlevel.c b/arch/arm/boards/phytec-phyflex-imx6/lowlevel.c
index 6422bc4..c0b0c87 100644
--- a/arch/arm/boards/phytec-phyflex-imx6/lowlevel.c
+++ b/arch/arm/boards/phytec-phyflex-imx6/lowlevel.c
@@ -86,3 +86,18 @@ ENTRY_FUNCTION(start_phytec_pbab01_2gib, r0, r1, r2)
 
 	barebox_arm_entry(0x10000000, SZ_2G, fdt);
 }
+
+ENTRY_FUNCTION(start_phytec_pbab01_4gib, r0, r1, r2)
+{
+	uint32_t fdt;
+
+	__barebox_arm_head();
+
+	arm_cpu_lowlevel_init();
+
+	arm_setup_stack(0x00920000 - 8);
+
+	fdt = (uint32_t)__dtb_imx6q_phytec_pbab01_start - get_runtime_offset();
+
+	barebox_arm_entry(0x10000000, 0xEFFFFFF8, fdt);
+}
diff --git a/images/Makefile.imx b/images/Makefile.imx
index 5b650de..29cec43 100644
--- a/images/Makefile.imx
+++ b/images/Makefile.imx
@@ -82,6 +82,12 @@ CFG_start_imx6q_mba6x.pblx.imximg = $(board)/tqma6x/flash-header-tqma6q.imxcfg
 FILE_barebox-tq-tqma6q-mba6x.img = start_imx6q_mba6x.pblx.imximg
 image-$(CONFIG_MACH_TQMA6X) += barebox-tq-tqma6q-mba6x.img
 
+pblx-$(CONFIG_MACH_PHYTEC_PFLA02) += start_phytec_pbab01_4gib
+CFG_start_phytec_pbab01_4gib.pblx.imximg = $(board)/phytec-phyflex-imx6/flash-header-phytec-pfla02-4gib.imxcfg
+imximage-$(CONFIG_MACH_PHYTEC_PFLA02) += start_phytec_pbab01_4gib.pblx.imximg
+FILE_barebox-phytec-pbab01-4gib.img = start_phytec_pbab01_4gib.pblx.imximg
+image-$(CONFIG_MACH_PHYTEC_PFLA02) += barebox-phytec-pbab01-4gib.img
+
 pblx-$(CONFIG_MACH_PHYTEC_PFLA02) += start_phytec_pbab01_2gib
 CFG_start_phytec_pbab01_2gib.pblx.imximg = $(board)/phytec-phyflex-imx6/flash-header-phytec-pfla02-2gib.imxcfg
 FILE_barebox-phytec-pbab01-2gib.img = start_phytec_pbab01_2gib.pblx.imximg
-- 
1.9.0



From s.hauer at pengutronix.de  Fri Mar 14 09:30:18 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 14 Mar 2014 14:30:18 +0100
Subject: [PATCH 4/6] ARM: pfla02: Set ODT to recommended setting
In-Reply-To: <1394803820-29277-1-git-send-email-s.hauer@pengutronix.de>
References: <1394803820-29277-1-git-send-email-s.hauer@pengutronix.de>
Message-ID: <1394803820-29277-5-git-send-email-s.hauer@pengutronix.de>

From: Christian Hemp <c.hemp at phytec.de>

Change the ODT values to  0x11117 (Recommended from Freescale)
see App note AN4579 "i.MX 6 Series Thermal Management Guidelines"

Signed-off-by: Christian Hemp <c.hemp at phytec.de>
Signed-off-by: Philipp Zabel <p.zabel at pengutronix.de>
---
 arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02.h b/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02.h
index 138ae36..fd09054 100644
--- a/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02.h
+++ b/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02.h
@@ -75,8 +75,8 @@ wm 32 0x021b001c 0x04008048
 wm 32 0x021b0800 0xa1380003
 wm 32 0x021b4800 0xa1380003
 wm 32 0x021b0020 0x00005800
-wm 32 0x021b0818 0x00022227
-wm 32 0x021b4818 0x00022227
+wm 32 0x021b0818 0x00011117
+wm 32 0x021b4818 0x00011117
 wm 32 0x021b083c 0x433c033f
 wm 32 0x021b0840 0x033e033d
 wm 32 0x021b483c 0x43490351
-- 
1.9.0



From s.hauer at pengutronix.de  Fri Mar 14 09:30:19 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 14 Mar 2014 14:30:19 +0100
Subject: [PATCH 5/6] ARM: pfla02: Add support for DualLite and Solo core
In-Reply-To: <1394803820-29277-1-git-send-email-s.hauer@pengutronix.de>
References: <1394803820-29277-1-git-send-email-s.hauer@pengutronix.de>
Message-ID: <1394803820-29277-6-git-send-email-s.hauer@pengutronix.de>

From: Christian Hemp <c.hemp at phytec.de>

Signed-off-by: Christian Hemp <c.hemp at phytec.de>
Signed-off-by: Philipp Zabel <p.zabel at pengutronix.de>
---
 arch/arm/boards/phytec-phyflex-imx6/board.c        |   6 +-
 .../flash-header-phytec-pfla02dl-1gib.imxcfg       |   6 +
 .../flash-header-phytec-pfla02dl.h                 |  95 ++++++++++
 .../flash-header-phytec-pfla02s-512mb.imxcfg       |   6 +
 arch/arm/boards/phytec-phyflex-imx6/lowlevel.c     |  32 ++++
 arch/arm/dts/Makefile                              |   4 +-
 arch/arm/dts/imx6dl-phytec-pbab01.dts              |  29 +++
 arch/arm/dts/imx6dl-phytec-pfla02.dtsi             |  41 ++++
 arch/arm/dts/imx6q-phytec-pbab01.dts               |  23 +--
 arch/arm/dts/imx6q-phytec-pfla02.dtsi              | 207 +--------------------
 arch/arm/dts/imx6qdl-phytec-pbab01.dtsi            |  43 +++++
 arch/arm/dts/imx6qdl-phytec-pfla02.dtsi            | 171 +++++++++++++++++
 arch/arm/dts/imx6s-phytec-pbab01.dts               |  25 +++
 arch/arm/dts/imx6s-phytec-pfla02.dtsi              |  22 +++
 arch/arm/mach-imx/Kconfig                          |   2 +-
 images/Makefile.imx                                |  12 ++
 16 files changed, 494 insertions(+), 230 deletions(-)
 create mode 100644 arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02dl-1gib.imxcfg
 create mode 100644 arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02dl.h
 create mode 100644 arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02s-512mb.imxcfg
 create mode 100644 arch/arm/dts/imx6dl-phytec-pbab01.dts
 create mode 100644 arch/arm/dts/imx6dl-phytec-pfla02.dtsi
 create mode 100644 arch/arm/dts/imx6qdl-phytec-pbab01.dtsi
 create mode 100644 arch/arm/dts/imx6qdl-phytec-pfla02.dtsi
 create mode 100644 arch/arm/dts/imx6s-phytec-pbab01.dts
 create mode 100644 arch/arm/dts/imx6s-phytec-pfla02.dtsi

diff --git a/arch/arm/boards/phytec-phyflex-imx6/board.c b/arch/arm/boards/phytec-phyflex-imx6/board.c
index e9bd168..f510407 100644
--- a/arch/arm/boards/phytec-phyflex-imx6/board.c
+++ b/arch/arm/boards/phytec-phyflex-imx6/board.c
@@ -38,7 +38,9 @@ static int eth_phy_reset(void)
 
 static int phytec_pfla02_init(void)
 {
-	if (!of_machine_is_compatible("phytec,imx6q-pfla02"))
+	if (!of_machine_is_compatible("phytec,imx6q-pfla02") &&
+			!of_machine_is_compatible("phytec,imx6dl-pfla02") &&
+			!of_machine_is_compatible("phytec,imx6s-pfla02"))
 		return 0;
 
 	eth_phy_reset();
@@ -49,7 +51,7 @@ device_initcall(phytec_pfla02_init);
 
 static int phytec_pfla02_core_init(void)
 {
-	if (!of_machine_is_compatible("phytec,imx6q-pfla02"))
+	if (!of_machine_is_compatible("phytec,imx6x-pbab01"))
 		return 0;
 
 	imx6_init_lowlevel();
diff --git a/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02dl-1gib.imxcfg b/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02dl-1gib.imxcfg
new file mode 100644
index 0000000..e5a7292
--- /dev/null
+++ b/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02dl-1gib.imxcfg
@@ -0,0 +1,6 @@
+
+#define SETUP_S_DL_512MB_1GB		\
+	wm 32 0x021b0040 0x00000017;	\
+	wm 32 0x021b0000 0xc21a0000
+
+#include "flash-header-phytec-pfla02dl.h"
diff --git a/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02dl.h b/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02dl.h
new file mode 100644
index 0000000..0f83bc9
--- /dev/null
+++ b/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02dl.h
@@ -0,0 +1,95 @@
+soc imx6
+loadaddr 0x20000000
+dcdofs 0x400
+
+wm 32 0x020e04bc 0x00000030
+wm 32 0x020e04c0 0x00000030
+wm 32 0x020e04c4 0x00000030
+wm 32 0x020e04c8 0x00000030
+wm 32 0x020e04cc 0x00000030
+wm 32 0x020e04d0 0x00000030
+wm 32 0x020e04d4 0x00000030
+wm 32 0x020e04d8 0x00000030
+wm 32 0x020e0470 0x00020030
+wm 32 0x020e0474 0x00020030
+wm 32 0x020e0478 0x00020030
+wm 32 0x020e047c 0x00020030
+wm 32 0x020e0480 0x00020030
+wm 32 0x020e0484 0x00020030
+wm 32 0x020e0488 0x00020030
+wm 32 0x020e048c 0x00020030
+wm 32 0x020e0464 0x00020030
+wm 32 0x020e0490 0x00020030
+wm 32 0x020e04ac 0x00020030
+wm 32 0x020e04b0 0x00020030
+wm 32 0x020e0494 0x00020030
+wm 32 0x020e04a4 0x00003000
+wm 32 0x020e04a8 0x00003000
+wm 32 0x020e04a0 0x00000000
+wm 32 0x020e04b4 0x00003030
+wm 32 0x020e04b8 0x00003030
+wm 32 0x020e0764 0x00000030
+wm 32 0x020e0770 0x00000030
+wm 32 0x020e0778 0x00000030
+wm 32 0x020e077c 0x00000030
+wm 32 0x020e0780 0x00000030
+wm 32 0x020e0784 0x00000030
+wm 32 0x020e078c 0x00000030
+wm 32 0x020e0748 0x00000030
+wm 32 0x020e074c 0x00000030
+wm 32 0x020e0750 0x00020000
+wm 32 0x020e0754 0x00000000
+wm 32 0x020e0760 0x00020000
+wm 32 0x020e076c 0x00000030
+wm 32 0x020e0774 0x000c0000
+wm 32 0x021b081c 0x33333333
+wm 32 0x021b0820 0x33333333
+wm 32 0x021b0824 0x33333333
+wm 32 0x021b0828 0x33333333
+wm 32 0x021b481c 0x33333333
+wm 32 0x021b4820 0x33333333
+wm 32 0x021b4824 0x33333333
+wm 32 0x021b4828 0x33333333
+wm 32 0x021b0018 0x00081740
+wm 32 0x021b001c 0x00008000
+wm 32 0x021b000c 0x555a7975
+wm 32 0x021b0010 0xff538e64
+wm 32 0x021b0014 0x01ff00db
+wm 32 0x021b002c 0x000026d2
+wm 32 0x021b0030 0x005b0e21
+wm 32 0x021b0008 0x09444040
+wm 32 0x021b0004 0x00025576
+
+SETUP_S_DL_512MB_1GB
+
+wm 32 0x021b001c 0x04088032
+wm 32 0x021b001c 0x0408803a
+wm 32 0x021b001c 0x00008033
+wm 32 0x021b001c 0x0000803b
+wm 32 0x021b001c 0x00428031
+wm 32 0x021b001c 0x00428039
+wm 32 0x021b001c 0x09408030
+wm 32 0x021b001c 0x09408038
+wm 32 0x021b001c 0x04008040
+wm 32 0x021b001c 0x04008048
+wm 32 0x021b0800 0xa1380003
+wm 32 0x021b4800 0xa1380003
+wm 32 0x021b0020 0x00005800
+wm 32 0x021b0818 0x00011117
+wm 32 0x021b4818 0x00011117
+wm 32 0x021b083c 0x422D0230
+wm 32 0x021b0840 0x022F022E
+wm 32 0x021b483c 0x4237023D
+wm 32 0x021b4840 0x02340224
+wm 32 0x021b0848 0x38333135
+wm 32 0x021b4848 0x36353338
+wm 32 0x021b0850 0x2E2E332C
+wm 32 0x021b4850 0x3727382F
+wm 32 0x021b080c 0x000C000D
+wm 32 0x021b0810 0x0018001A
+wm 32 0x021b480c 0x00270023
+wm 32 0x021b4810 0x002F002D
+wm 32 0x021b08b8 0x00000800
+wm 32 0x021b48b8 0x00000800
+wm 32 0x021b001c 0x00000000
+wm 32 0x021b0404 0x00011006
diff --git a/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02s-512mb.imxcfg b/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02s-512mb.imxcfg
new file mode 100644
index 0000000..3116e36
--- /dev/null
+++ b/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02s-512mb.imxcfg
@@ -0,0 +1,6 @@
+
+#define SETUP_S_DL_512MB_1GB		\
+	wm 32 0x021b0040 0x00000017;	\
+	wm 32 0x021b0000 0x83190000
+
+#include "flash-header-phytec-pfla02dl.h"
diff --git a/arch/arm/boards/phytec-phyflex-imx6/lowlevel.c b/arch/arm/boards/phytec-phyflex-imx6/lowlevel.c
index c0b0c87..fb7b186 100644
--- a/arch/arm/boards/phytec-phyflex-imx6/lowlevel.c
+++ b/arch/arm/boards/phytec-phyflex-imx6/lowlevel.c
@@ -54,6 +54,8 @@ static inline void setup_uart(void)
 }
 
 extern char __dtb_imx6q_phytec_pbab01_start[];
+extern char __dtb_imx6dl_phytec_pbab01_start[];
+extern char __dtb_imx6s_phytec_pbab01_start[];
 
 ENTRY_FUNCTION(start_phytec_pbab01_1gib, r0, r1, r2)
 {
@@ -101,3 +103,33 @@ ENTRY_FUNCTION(start_phytec_pbab01_4gib, r0, r1, r2)
 
 	barebox_arm_entry(0x10000000, 0xEFFFFFF8, fdt);
 }
+
+ENTRY_FUNCTION(start_phytec_pbab01dl_1gib, r0, r1, r2)
+{
+        uint32_t fdt;
+
+        __barebox_arm_head();
+
+        arm_cpu_lowlevel_init();
+
+        arm_setup_stack(0x00920000 - 8);
+
+	fdt = (uint32_t)__dtb_imx6dl_phytec_pbab01_start - get_runtime_offset();
+
+        barebox_arm_entry(0x10000000, SZ_1G, fdt);
+}
+
+ENTRY_FUNCTION(start_phytec_pbab01s_512mb, r0, r1, r2)
+{
+	uint32_t fdt;
+
+	__barebox_arm_head();
+
+	arm_cpu_lowlevel_init();
+
+	arm_setup_stack(0x00920000 - 8);
+
+	fdt = (uint32_t)__dtb_imx6s_phytec_pbab01_start - get_runtime_offset();
+
+	barebox_arm_entry(0x10000000, SZ_512M, fdt);
+}
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 6bac3b9..4c9c149 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -20,7 +20,9 @@ dtb-$(CONFIG_ARCH_IMX6) += imx6q-gk802.dtb \
 	imx6q-sabresd.dtb \
 	imx6dl-mba6x.dtb \
 	imx6q-mba6x.dtb \
+	imx6dl-phytec-pbab01.dtb \
 	imx6q-phytec-pbab01.dtb \
+	imx6s-phytec-pbab01.dtb \
 	imx6dl-hummingboard.dtb \
 	imx6q-guf-santaro.dtb \
 	imx6q-nitrogen6x.dtb \
@@ -43,7 +45,7 @@ pbl-$(CONFIG_MACH_FREESCALE_MX53_LOCO) += imx53-qsb.dtb.o imx53-qsrb.dtb.o
 pbl-$(CONFIG_MACH_FREESCALE_MX53_VMX53) += imx53-voipac-bsb.dtb.o
 pbl-$(CONFIG_MACH_DFI_FS700_M60) += imx6q-dfi-fs700-m60-6q.dtb.o imx6dl-dfi-fs700-m60-6s.dtb.o
 pbl-$(CONFIG_MACH_PCM051) += am335x-phytec-phycore.dtb.o
-pbl-$(CONFIG_MACH_PHYTEC_PFLA02) += imx6q-phytec-pbab01.dtb.o
+pbl-$(CONFIG_MACH_PHYTEC_PFLA02) += imx6s-phytec-pbab01.dtb.o imx6dl-phytec-pbab01.dtb.o imx6q-phytec-pbab01.dtb.o
 pbl-$(CONFIG_MACH_REALQ7) += imx6q-dmo-edmqmx6.dtb.o
 pbl-$(CONFIG_MACH_SOLIDRUN_CUBOX) += dove-cubox-bb.dtb.o
 pbl-$(CONFIG_MACH_GK802) += imx6q-gk802.dtb.o
diff --git a/arch/arm/dts/imx6dl-phytec-pbab01.dts b/arch/arm/dts/imx6dl-phytec-pbab01.dts
new file mode 100644
index 0000000..0e90c47
--- /dev/null
+++ b/arch/arm/dts/imx6dl-phytec-pbab01.dts
@@ -0,0 +1,29 @@
+/*
+ * Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+
+#include "imx6dl-phytec-pfla02.dtsi"
+#include "imx6qdl-phytec-pbab01.dtsi"
+
+/ {
+	model = "Phytec phyFLEX-i.MX6 Duallite Carrier-Board";
+	compatible = "phytec,imx6x-pbab01", "phytec,imx6dl-pfla02", "fsl,imx6dl";
+
+	chosen {
+		linux,stdout-path = &uart4;
+
+		environment at 0 {
+			compatible = "barebox,environment";
+			device-path = &flash, "partname:barebox-environment";
+		};
+	};
+};
diff --git a/arch/arm/dts/imx6dl-phytec-pfla02.dtsi b/arch/arm/dts/imx6dl-phytec-pfla02.dtsi
new file mode 100644
index 0000000..fa3a49a
--- /dev/null
+++ b/arch/arm/dts/imx6dl-phytec-pfla02.dtsi
@@ -0,0 +1,41 @@
+/*
+ * Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include "imx6dl.dtsi"
+#include "imx6qdl-phytec-pfla02.dtsi"
+
+/ {
+	model = "Phytec phyFLEX-i.MX6 Dual Lite";
+	compatible = "phytec,imx6dl-pfla02", "fsl,imx6dl";
+
+	memory {
+		reg = <0x10000000 0x40000000>;
+	};
+};
+
+&ecspi3 {
+	status = "okay";
+};
+
+&flash {
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        partition at 0 {
+                label = "barebox";
+                reg = <0x0 0x80000>;
+        };
+
+        partition at 1 {
+                label = "barebox-environment";
+                reg = <0x80000 0x10000>;
+        };
+};
diff --git a/arch/arm/dts/imx6q-phytec-pbab01.dts b/arch/arm/dts/imx6q-phytec-pbab01.dts
index b35b2e5..26046e0 100644
--- a/arch/arm/dts/imx6q-phytec-pbab01.dts
+++ b/arch/arm/dts/imx6q-phytec-pbab01.dts
@@ -11,10 +11,11 @@
 
 /dts-v1/;
 #include "imx6q-phytec-pfla02.dtsi"
+#include "imx6qdl-phytec-pbab01.dtsi"
 
 / {
 	model = "Phytec phyFLEX-i.MX6 Quad Carrier-Board";
-	compatible = "phytec,imx6q-pbab01", "phytec,imx6q-pfla02", "fsl,imx6q";
+	compatible = "phytec,imx6x-pbab01", "phytec,imx6q-pfla02", "fsl,imx6q";
 
 	chosen {
 		linux,stdout-path = &uart4;
@@ -25,23 +26,3 @@
 		};
 	};
 };
-
-&fec {
-	status = "okay";
-};
-
-&uart1 {
-	status = "okay";
-};
-
-&uart4 {
-	status = "okay";
-};
-
-&usdhc2 {
-	status = "okay";
-};
-
-&usdhc3 {
-	status = "okay";
-};
diff --git a/arch/arm/dts/imx6q-phytec-pfla02.dtsi b/arch/arm/dts/imx6q-phytec-pfla02.dtsi
index 402eee8..781a90a 100644
--- a/arch/arm/dts/imx6q-phytec-pfla02.dtsi
+++ b/arch/arm/dts/imx6q-phytec-pfla02.dtsi
@@ -10,9 +10,10 @@
  */
 
 #include "imx6q.dtsi"
+#include "imx6qdl-phytec-pfla02.dtsi"
 
 / {
-	model = "Phytec phyFLEX-i.MX6 Ouad";
+	model = "Phytec phyFLEX-i.MX6 Quad";
 	compatible = "phytec,imx6q-pfla02", "fsl,imx6q";
 
 	memory {
@@ -21,165 +22,7 @@
 };
 
 &ecspi3 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_ecspi3>;
 	status = "okay";
-	fsl,spi-num-chipselects = <1>;
-	cs-gpios = <&gpio4 24 0>;
-
-	flash: m25p80 at 0 {
-		compatible = "m25p80";
-		spi-max-frequency = <20000000>;
-		reg = <0>;
-	};
-};
-
-&i2c1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_i2c1>;
-	status = "okay";
-
-	eeprom at 50 {
-		compatible = "atmel,24c32";
-		reg = <0x50>;
-	};
-
-	pmic at 58 {
-		compatible = "dialog,da9063";
-		reg = <0x58>;
-		interrupt-parent = <&gpio4>;
-		interrupts = <17 0x8>; /* active-low GPIO4_17 */
-
-		regulators {
-			vddcore_reg: bcore1 {
-				regulator-min-microvolt = <730000>;
-				regulator-max-microvolt = <1380000>;
-				regulator-always-on;
-			};
-
-			vddsoc_reg: bcore2 {
-				regulator-min-microvolt = <730000>;
-				regulator-max-microvolt = <1380000>;
-				regulator-always-on;
-			};
-
-			vdd_ddr3_reg: bpro {
-				regulator-min-microvolt = <1500000>;
-				regulator-max-microvolt = <1500000>;
-				regulator-always-on;
-			};
-
-			vdd_3v3_reg: bperi {
-				regulator-min-microvolt = <3300000>;
-				regulator-max-microvolt = <3300000>;
-				regulator-always-on;
-			};
-
-			vdd_buckmem_reg: bmem {
-				regulator-min-microvolt = <3300000>;
-				regulator-max-microvolt = <3300000>;
-				regulator-always-on;
-			};
-
-			vdd_eth_reg: bio {
-				regulator-min-microvolt = <1200000>;
-				regulator-max-microvolt = <1200000>;
-				regulator-always-on;
-			};
-
-			vdd_eth_io_reg: ldo4 {
-				regulator-min-microvolt = <2500000>;
-				regulator-max-microvolt = <2500000>;
-				regulator-always-on;
-			};
-
-			vdd_mx6_snvs_reg: ldo5 {
-				regulator-min-microvolt = <3000000>;
-				regulator-max-microvolt = <3000000>;
-				regulator-always-on;
-			};
-
-			vdd_3v3_pmic_io_reg: ldo6 {
-				regulator-min-microvolt = <3300000>;
-				regulator-max-microvolt = <3300000>;
-				regulator-always-on;
-			};
-
-			vdd_sd0_reg: ldo9 {
-				regulator-min-microvolt = <3300000>;
-				regulator-max-microvolt = <3300000>;
-			};
-
-			vdd_sd1_reg: ldo10 {
-				regulator-min-microvolt = <3300000>;
-				regulator-max-microvolt = <3300000>;
-			};
-
-			vdd_mx6_high_reg: ldo11 {
-				regulator-min-microvolt = <3000000>;
-				regulator-max-microvolt = <3000000>;
-				regulator-always-on;
-			};
-		};
-	};
-};
-
-&iomuxc {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_hog>;
-
-	imx6q-phytec-pfla02 {
-		pinctrl_hog: hoggrp {
-			fsl,pins = <
-				MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000
-				MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x80000000 /* SPI NOR chipselect */
-				MX6QDL_PAD_DI0_PIN15__GPIO4_IO17  0x80000000 /* PMIC interrupt */
-			>;
-		};
-
-		pinctrl_ecspi3: ecspi3grp {
-			fsl,pins = <MX6QDL_ECSPI3_PINGRP1>;
-		};
-
-		pinctrl_enet: enetgrp {
-			fsl,pins = <MX6QDL_ENET_PINGRP3>;
-		};
-
-		pinctrl_gpmi_nand: gpmigrp {
-			fsl,pins = <MX6QDL_GPMI_NAND_PINGRP1>;
-		};
-
-		pinctrl_i2c1: i2c1grp {
-			fsl,pins = <MX6QDL_I2C1_PINGRP1>;
-		};
-
-		pinctrl_uart4: uart4grp {
-			fsl,pins = <MX6QDL_UART4_PINGRP1>;
-		};
-
-		pinctrl_usdhc2: usdhc2grp {
-			fsl,pins = <MX6QDL_USDHC2_PINGRP_D4>;
-		};
-
-		pinctrl_usdhc3: usdhc3grp {
-			fsl,pins = <MX6QDL_USDHC3_PINGRP_D4>;
-		};
-
-		pinctrl_usdhc3_cdwp: usdhc3cdwp {
-			fsl,pins = <
-				MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000
-				MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000
-			>;
-		};
-	};
-};
-
-&fec {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_enet>;
-	phy-mode = "rgmii";
-	phy-reset-gpios = <&gpio3 23 0>;
-	status = "disabled";
 };
 
 &flash {
@@ -196,49 +39,3 @@
 		reg = <0x80000 0x10000>;
 	};
 };
-
-&gpmi {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_gpmi_nand>;
-	nand-on-flash-bbt;
-	status = "okay";
-	#address-cells = <1>;
-	#size-cells = <1>;
-
-	partition at 0 {
-		label = "barebox";
-		reg = <0x0 0x200000>;
-	};
-
-	partition at 1 {
-		label = "ubi";
-		reg = <0x200000 0x3fe00000>;
-	};
-};
-
-&ocotp {
-	barebox,provide-mac-address = <&fec 0x620>;
-};
-
-&uart4 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_uart4>;
-	status = "disabled";
-};
-
-&usdhc2 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_usdhc2>;
-	cd-gpios = <&gpio1 4 0>;
-	wp-gpios = <&gpio1 2 0>;
-	status = "disabled";
-};
-
-&usdhc3 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_usdhc3
-		     &pinctrl_usdhc3_cdwp>;
-        cd-gpios = <&gpio1 27 0>;
-        wp-gpios = <&gpio1 29 0>;
-        status = "disabled";
-};
diff --git a/arch/arm/dts/imx6qdl-phytec-pbab01.dtsi b/arch/arm/dts/imx6qdl-phytec-pbab01.dtsi
new file mode 100644
index 0000000..8f5dea7
--- /dev/null
+++ b/arch/arm/dts/imx6qdl-phytec-pbab01.dtsi
@@ -0,0 +1,43 @@
+/*
+ * Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/ {
+	chosen {
+		environment at 0 {
+			compatible = "barebox,environment";
+			device-path = &flash, "partname:barebox-environment";
+		};
+	};
+};
+
+&fec {
+	status = "okay";
+};
+
+&ocotp {
+	barebox,provide-mac-address = <&fec 0x620>;
+};
+
+&uart1 {
+	status = "okay";
+};
+
+&uart4 {
+	status = "okay";
+};
+
+&usdhc2 {
+	status = "okay";
+};
+
+&usdhc3 {
+	status = "okay";
+};
diff --git a/arch/arm/dts/imx6qdl-phytec-pfla02.dtsi b/arch/arm/dts/imx6qdl-phytec-pfla02.dtsi
new file mode 100644
index 0000000..d1eb9d0
--- /dev/null
+++ b/arch/arm/dts/imx6qdl-phytec-pfla02.dtsi
@@ -0,0 +1,171 @@
+/*
+ * Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+&ecspi3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_ecspi3>;
+	status = "disabled";
+	fsl,spi-num-chipselects = <1>;
+	cs-gpios = <&gpio4 24 0>;
+
+	flash: m25p80 at 0 {
+		compatible = "m25p80";
+		spi-max-frequency = <20000000>;
+	};
+};
+
+&fec {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_enet>;
+	phy-mode = "rgmii";
+	phy-reset-gpios = <&gpio3 23 0>;
+	status = "disabled";
+};
+
+&gpmi {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_gpmi_nand>;
+	nand-on-flash-bbt;
+	status = "okay";
+};
+
+&iomuxc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_hog>;
+
+	ecspi3 {
+		pinctrl_ecspi3: ecspi3grp {
+			fsl,pins = <
+				MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
+				MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
+				MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
+				MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x80000000 /* SPI NOR chipselect */
+				MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x80000000
+			>;
+		};
+	};
+
+	enet {
+		pinctrl_enet: enetgrp {
+			fsl,pins = <
+				MX6QDL_PAD_ENET_MDIO__ENET_MDIO       0x1b0b0
+				MX6QDL_PAD_ENET_MDC__ENET_MDC         0x1b0b0
+				MX6QDL_PAD_RGMII_TXC__RGMII_TXC       0x1b0b0
+				MX6QDL_PAD_RGMII_TD0__RGMII_TD0       0x1b0b0
+				MX6QDL_PAD_RGMII_TD1__RGMII_TD1       0x1b0b0
+				MX6QDL_PAD_RGMII_TD2__RGMII_TD2       0x1b0b0
+				MX6QDL_PAD_RGMII_TD3__RGMII_TD3       0x1b0b0
+				MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
+				MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK  0x1b0b0
+				MX6QDL_PAD_RGMII_RXC__RGMII_RXC       0x1b0b0
+				MX6QDL_PAD_RGMII_RD0__RGMII_RD0       0x1b0b0
+				MX6QDL_PAD_RGMII_RD1__RGMII_RD1       0x1b0b0
+				MX6QDL_PAD_RGMII_RD2__RGMII_RD2       0x1b0b0
+				MX6QDL_PAD_RGMII_RD3__RGMII_RD3       0x1b0b0
+				MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
+				MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN     0x1b0b0
+			>;
+		};
+	};
+
+	gpmi-nand {
+		pinctrl_gpmi_nand: gpmi-nand {
+			fsl,pins = <
+				MX6QDL_PAD_NANDF_CLE__NAND_CLE     0xb0b1
+				MX6QDL_PAD_NANDF_ALE__NAND_ALE     0xb0b1
+				MX6QDL_PAD_NANDF_WP_B__NAND_WP_B   0xb0b1
+				MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
+				MX6QDL_PAD_NANDF_CS0__NAND_CE0_B   0xb0b1
+				MX6QDL_PAD_NANDF_CS1__NAND_CE1_B   0xb0b1
+				MX6QDL_PAD_NANDF_CS2__NAND_CE2_B   0xb0b1
+				MX6QDL_PAD_NANDF_CS3__NAND_CE3_B   0xb0b1
+				MX6QDL_PAD_SD4_CMD__NAND_RE_B      0xb0b1
+				MX6QDL_PAD_SD4_CLK__NAND_WE_B      0xb0b1
+				MX6QDL_PAD_NANDF_D0__NAND_DATA00   0xb0b1
+				MX6QDL_PAD_NANDF_D1__NAND_DATA01   0xb0b1
+				MX6QDL_PAD_NANDF_D2__NAND_DATA02   0xb0b1
+				MX6QDL_PAD_NANDF_D3__NAND_DATA03   0xb0b1
+				MX6QDL_PAD_NANDF_D4__NAND_DATA04   0xb0b1
+				MX6QDL_PAD_NANDF_D5__NAND_DATA05   0xb0b1
+				MX6QDL_PAD_NANDF_D6__NAND_DATA06   0xb0b1
+				MX6QDL_PAD_NANDF_D7__NAND_DATA07   0xb0b1
+				MX6QDL_PAD_SD4_DAT0__NAND_DQS      0x00b1
+			>;
+		};
+	};
+
+	hog {
+		pinctrl_hog: hoggrp {
+			fsl,pins = <
+				MX6QDL_PAD_EIM_D23__GPIO3_IO23  0x80000000
+			>;
+		};
+	};
+
+	uart4 {
+		pinctrl_uart4: uart4grp {
+			fsl,pins = <
+				MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
+				MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
+			>;
+		};
+	};
+
+	usdhc2 {
+		pinctrl_usdhc2: usdhc2grp {
+			fsl,pins = <
+				MX6QDL_PAD_SD2_CMD__SD2_CMD    0x17059
+				MX6QDL_PAD_SD2_CLK__SD2_CLK    0x10059
+				MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
+				MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
+				MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
+				MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
+			>;
+		};
+	};
+
+	usdhc3 {
+		pinctrl_usdhc3: usdhc3grp {
+			fsl,pins = <
+				MX6QDL_PAD_SD3_CMD__SD3_CMD    0x17059
+				MX6QDL_PAD_SD3_CLK__SD3_CLK    0x10059
+				MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
+				MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
+				MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
+				MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
+				MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000
+				MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000
+			>;
+		};
+	};
+};
+
+&uart4 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart4>;
+	status = "disabled";
+};
+
+&usdhc2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc2>;
+	cd-gpios = <&gpio1 4 0>;
+	wp-gpios = <&gpio1 2 0>;
+	status = "disabled";
+};
+
+&usdhc3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usdhc3>;
+        cd-gpios = <&gpio1 27 0>;
+        wp-gpios = <&gpio1 29 0>;
+        status = "disabled";
+};
diff --git a/arch/arm/dts/imx6s-phytec-pbab01.dts b/arch/arm/dts/imx6s-phytec-pbab01.dts
new file mode 100644
index 0000000..95841de
--- /dev/null
+++ b/arch/arm/dts/imx6s-phytec-pbab01.dts
@@ -0,0 +1,25 @@
+/*
+ * Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+
+#include "imx6s-phytec-pfla02.dtsi"
+#include "imx6qdl-phytec-pbab01.dtsi"
+
+/ {
+	model = "Phytec phyFLEX-i.MX6 Single Carrier-Board";
+	compatible = "phytec,imx6x-pbab01", "phytec,imx6s-pfla02", "fsl,imx6dl";
+
+	chosen {
+		linux,stdout-path = &uart4;
+
+	};
+};
diff --git a/arch/arm/dts/imx6s-phytec-pfla02.dtsi b/arch/arm/dts/imx6s-phytec-pfla02.dtsi
new file mode 100644
index 0000000..8322426
--- /dev/null
+++ b/arch/arm/dts/imx6s-phytec-pfla02.dtsi
@@ -0,0 +1,22 @@
+/*
+ * Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include "imx6dl.dtsi"
+#include "imx6qdl-phytec-pfla02.dtsi"
+
+/ {
+	model = "Phytec phyFLEX-i.MX6 Single";
+	compatible = "phytec,imx6s-pfla02", "fsl,imx6dl";
+
+	memory {
+		reg = <0x10000000 0x20000000>;
+	};
+};
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index b7e7533..4d7d999 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -202,7 +202,7 @@ config MACH_FREESCALE_MX53_VMX53
 	  module equipped with a Freescale i.MX53 Processor
 
 config MACH_PHYTEC_PFLA02
-	bool "Phytec phyFLEX-i.MX6 Ouad"
+	bool "Phytec phyFLEX-i.MX6"
 	select ARCH_IMX6
 
 config MACH_DFI_FS700_M60
diff --git a/images/Makefile.imx b/images/Makefile.imx
index 29cec43..6eee4a2 100644
--- a/images/Makefile.imx
+++ b/images/Makefile.imx
@@ -98,6 +98,18 @@ CFG_start_phytec_pbab01_1gib.pblx.imximg = $(board)/phytec-phyflex-imx6/flash-he
 FILE_barebox-phytec-pbab01-1gib.img = start_phytec_pbab01_1gib.pblx.imximg
 image-$(CONFIG_MACH_PHYTEC_PFLA02) += barebox-phytec-pbab01-1gib.img
 
+pblx-$(CONFIG_MACH_PHYTEC_PFLA02) += start_phytec_pbab01dl_1gib
+CFG_start_phytec_pbab01dl_1gib.pblx.imximg = $(board)/phytec-phyflex-imx6/flash-header-phytec-pfla02dl-1gib.imxcfg
+imximage-$(CONFIG_MACH_PHYTEC_PFLA02) += start_phytec_pbab01dl_1gib.pblx.imximg
+FILE_barebox-phytec-pbab01dl-1gib.img = start_phytec_pbab01dl_1gib.pblx.imximg
+image-$(CONFIG_MACH_PHYTEC_PFLA02) += barebox-phytec-pbab01dl-1gib.img
+
+pblx-$(CONFIG_MACH_PHYTEC_PFLA02) += start_phytec_pbab01s_512mb
+CFG_start_phytec_pbab01s_512mb.pblx.imximg = $(board)/phytec-phyflex-imx6/flash-header-phytec-pfla02s-512mb.imxcfg
+imximage-$(CONFIG_MACH_PHYTEC_PFLA02) += start_phytec_pbab01s_512mb.pblx.imximg
+FILE_barebox-phytec-pbab01s-512mb.img = start_phytec_pbab01s_512mb.pblx.imximg
+image-$(CONFIG_MACH_PHYTEC_PFLA02) += barebox-phytec-pbab01s-512mb.img
+
 pblx-$(CONFIG_MACH_DFI_FS700_M60) += start_imx6dl_dfi_fs700_m60_6s
 CFG_start_imx6dl_dfi_fs700_m60_6s.pblx.imximg = $(board)/dfi-fs700-m60/flash-header-fs700-m60-6s.imxcfg
 FILE_barebox-dfi-fs700-m60-6s.img = start_imx6dl_dfi_fs700_m60_6s.pblx.imximg
-- 
1.9.0



From s.hauer at pengutronix.de  Fri Mar 14 10:32:23 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 14 Mar 2014 15:32:23 +0100
Subject: [PATCH 03/29] ARM: dts: i.MX6: Add IPU aliases
In-Reply-To: <1394807569-23620-1-git-send-email-s.hauer@pengutronix.de>
References: <1394807569-23620-1-git-send-email-s.hauer@pengutronix.de>
Message-ID: <1394807569-23620-4-git-send-email-s.hauer@pengutronix.de>

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/dts/imx6q.dtsi   | 1 +
 arch/arm/dts/imx6qdl.dtsi | 1 +
 2 files changed, 2 insertions(+)

diff --git a/arch/arm/dts/imx6q.dtsi b/arch/arm/dts/imx6q.dtsi
index 52a9a2b..f9378fa 100644
--- a/arch/arm/dts/imx6q.dtsi
+++ b/arch/arm/dts/imx6q.dtsi
@@ -16,6 +16,7 @@
 / {
 	aliases {
 		spi4 = &ecspi5;
+		ipu1 = &ipu2;
 	};
 
 	cpus {
diff --git a/arch/arm/dts/imx6qdl.dtsi b/arch/arm/dts/imx6qdl.dtsi
index 70424d2..5160db4 100644
--- a/arch/arm/dts/imx6qdl.dtsi
+++ b/arch/arm/dts/imx6qdl.dtsi
@@ -45,6 +45,7 @@
 		spi3 = &ecspi4;
 		usbphy0 = &usbphy1;
 		usbphy1 = &usbphy2;
+		ipu0 = &ipu1;
 	};
 
 	intc: interrupt-controller at 00a01000 {
-- 
1.9.0



From s.hauer at pengutronix.de  Fri Mar 14 10:32:24 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 14 Mar 2014 15:32:24 +0100
Subject: [PATCH 04/29] ARM: dts: i.MX6: Add HDMI nodes
In-Reply-To: <1394807569-23620-1-git-send-email-s.hauer@pengutronix.de>
References: <1394807569-23620-1-git-send-email-s.hauer@pengutronix.de>
Message-ID: <1394807569-23620-5-git-send-email-s.hauer@pengutronix.de>

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/dts/imx6q.dtsi   |  4 ++++
 arch/arm/dts/imx6qdl.dtsi | 11 +++++++++++
 2 files changed, 15 insertions(+)

diff --git a/arch/arm/dts/imx6q.dtsi b/arch/arm/dts/imx6q.dtsi
index f9378fa..2b8ec43 100644
--- a/arch/arm/dts/imx6q.dtsi
+++ b/arch/arm/dts/imx6q.dtsi
@@ -158,6 +158,10 @@
 	};
 };
 
+&hdmi {
+	compatible = "fsl,imx6q-hdmi";
+};
+
 &ldb {
 	clocks = <&clks 33>, <&clks 34>,
 		 <&clks 39>, <&clks 40>, <&clks 41>, <&clks 42>,
diff --git a/arch/arm/dts/imx6qdl.dtsi b/arch/arm/dts/imx6qdl.dtsi
index 5160db4..8dfd7de 100644
--- a/arch/arm/dts/imx6qdl.dtsi
+++ b/arch/arm/dts/imx6qdl.dtsi
@@ -665,6 +665,17 @@
 				};
 			};
 
+			hdmi: hdmi at 0120000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				reg = <0x00120000 0x9000>;
+				interrupts = <0 115 0x04>;
+				gpr = <&gpr>;
+				clocks = <&clks 123>, <&clks 124>;
+				clock-names = "iahb", "isfr";
+				status = "disabled";
+			};
+
 			dcic1: dcic at 020e4000 {
 				reg = <0x020e4000 0x4000>;
 				interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
-- 
1.9.0



From s.hauer at pengutronix.de  Fri Mar 14 10:32:25 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 14 Mar 2014 15:32:25 +0100
Subject: [PATCH 05/29] ARM: dts: i.MX53: Fix IPU register size
In-Reply-To: <1394807569-23620-1-git-send-email-s.hauer@pengutronix.de>
References: <1394807569-23620-1-git-send-email-s.hauer@pengutronix.de>
Message-ID: <1394807569-23620-6-git-send-email-s.hauer@pengutronix.de>

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/dts/imx53.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/dts/imx53.dtsi b/arch/arm/dts/imx53.dtsi
index 91659b8..c3fac43 100644
--- a/arch/arm/dts/imx53.dtsi
+++ b/arch/arm/dts/imx53.dtsi
@@ -87,7 +87,7 @@
 		ipu: ipu at 18000000 {
 			#crtc-cells = <1>;
 			compatible = "fsl,imx53-ipu";
-			reg = <0x18000000 0x080000000>;
+			reg = <0x18000000 0x08000000>;
 			interrupts = <11 10>;
 			clocks = <&clks 59>, <&clks 110>, <&clks 61>;
 			clock-names = "bus", "di0", "di1";
-- 
1.9.0



From s.hauer at pengutronix.de  Fri Mar 14 10:32:27 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 14 Mar 2014 15:32:27 +0100
Subject: [PATCH 07/29] i2c: implement of_find_i2c_adapter_by_node
In-Reply-To: <1394807569-23620-1-git-send-email-s.hauer@pengutronix.de>
References: <1394807569-23620-1-git-send-email-s.hauer@pengutronix.de>
Message-ID: <1394807569-23620-8-git-send-email-s.hauer@pengutronix.de>

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 drivers/i2c/i2c.c | 11 +++++++++++
 include/i2c/i2c.h |  1 +
 2 files changed, 12 insertions(+)

diff --git a/drivers/i2c/i2c.c b/drivers/i2c/i2c.c
index e289a35..9873957 100644
--- a/drivers/i2c/i2c.c
+++ b/drivers/i2c/i2c.c
@@ -405,6 +405,17 @@ struct i2c_adapter *i2c_get_adapter(int busnum)
 	return NULL;
 }
 
+struct i2c_adapter *of_find_i2c_adapter_by_node(struct device_node *node)
+{
+	struct i2c_adapter *adap;
+
+	list_for_each_entry(adap, &adapter_list, list)
+		if (adap->dev.device_node == node)
+			return adap;
+
+	return NULL;
+}
+
 /**
  * i2c_add_numbered_adapter - declare i2c adapter, use static bus number
  * @adapter: the adapter to register (with adap->nr initialized)
diff --git a/include/i2c/i2c.h b/include/i2c/i2c.h
index 81e5daa..f89fefb 100644
--- a/include/i2c/i2c.h
+++ b/include/i2c/i2c.h
@@ -133,6 +133,7 @@ static inline int i2c_register_board_info(int busnum,
 #endif
 extern int i2c_add_numbered_adapter(struct i2c_adapter *adapter);
 struct i2c_adapter *i2c_get_adapter(int busnum);
+struct i2c_adapter *of_find_i2c_adapter_by_node(struct device_node *node);
 
 /* For devices that use several addresses, use i2c_new_dummy() to make
  * client handles for the extra addresses.
-- 
1.9.0



From s.hauer at pengutronix.de  Fri Mar 14 10:32:26 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 14 Mar 2014 15:32:26 +0100
Subject: [PATCH 06/29] i2c: i.MX: move to earlier initcall
In-Reply-To: <1394807569-23620-1-git-send-email-s.hauer@pengutronix.de>
References: <1394807569-23620-1-git-send-email-s.hauer@pengutronix.de>
Message-ID: <1394807569-23620-7-git-send-email-s.hauer@pengutronix.de>

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 drivers/i2c/busses/i2c-imx.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/i2c/busses/i2c-imx.c b/drivers/i2c/busses/i2c-imx.c
index f657c28..6b39047 100644
--- a/drivers/i2c/busses/i2c-imx.c
+++ b/drivers/i2c/busses/i2c-imx.c
@@ -587,4 +587,4 @@ static struct driver_d i2c_fsl_driver = {
 	.name	= DRIVER_NAME,
 	.of_compatible = DRV_OF_COMPAT(imx_i2c_dt_ids),
 };
-device_platform_driver(i2c_fsl_driver);
+coredevice_platform_driver(i2c_fsl_driver);
-- 
1.9.0



From s.hauer at pengutronix.de  Fri Mar 14 10:32:21 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 14 Mar 2014 15:32:21 +0100
Subject: [PATCH 01/29] err.h: Add PTR_ERR_OR_ZERO from kernel
In-Reply-To: <1394807569-23620-1-git-send-email-s.hauer@pengutronix.de>
References: <1394807569-23620-1-git-send-email-s.hauer@pengutronix.de>
Message-ID: <1394807569-23620-2-git-send-email-s.hauer@pengutronix.de>

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 include/linux/err.h | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/include/linux/err.h b/include/linux/err.h
index 19fb70d..ed563f2 100644
--- a/include/linux/err.h
+++ b/include/linux/err.h
@@ -52,6 +52,14 @@ static inline void *ERR_CAST(const void *ptr)
 	return (void *) ptr;
 }
 
+static inline int __must_check PTR_ERR_OR_ZERO(__force const void *ptr)
+{
+	if (IS_ERR(ptr))
+		return PTR_ERR(ptr);
+	else
+		return 0;
+}
+
 #endif
 
 #endif /* _LINUX_ERR_H */
-- 
1.9.0



From s.hauer at pengutronix.de  Fri Mar 14 10:32:28 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 14 Mar 2014 15:32:28 +0100
Subject: [PATCH 08/29] clk: implement clk_round_rate
In-Reply-To: <1394807569-23620-1-git-send-email-s.hauer@pengutronix.de>
References: <1394807569-23620-1-git-send-email-s.hauer@pengutronix.de>
Message-ID: <1394807569-23620-9-git-send-email-s.hauer@pengutronix.de>

Instead of returning just the current rate implement clk_round_rate
properly.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 drivers/clk/clk.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index 31d73c0..c67b2f4 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -104,9 +104,19 @@ unsigned long clk_get_rate(struct clk *clk)
 
 long clk_round_rate(struct clk *clk, unsigned long rate)
 {
+	unsigned long parent_rate = 0;
+	struct clk *parent;
+
 	if (IS_ERR(clk))
 		return 0;
 
+	parent = clk_get_parent(clk);
+	if (parent)
+		parent_rate = clk_get_rate(parent);
+
+	if (clk->ops->round_rate)
+		return clk->ops->round_rate(clk, rate, &parent_rate);
+
 	return clk_get_rate(clk);
 }
 
-- 
1.9.0



From s.hauer at pengutronix.de  Fri Mar 14 10:32:40 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 14 Mar 2014 15:32:40 +0100
Subject: [PATCH 20/29] video: introduce struct display_timings
In-Reply-To: <1394807569-23620-1-git-send-email-s.hauer@pengutronix.de>
References: <1394807569-23620-1-git-send-email-s.hauer@pengutronix.de>
Message-ID: <1394807569-23620-21-git-send-email-s.hauer@pengutronix.de>

And use it inside struct fb_info. This struct has the advantage
that the supported modes can be passed around in a single pointer.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 drivers/video/atmel_lcdfb_core.c |  4 ++--
 drivers/video/fb.c               | 20 +++++++++++---------
 drivers/video/imx-ipu-fb.c       |  4 ++--
 drivers/video/imx.c              |  6 +++---
 drivers/video/omap.c             |  4 ++--
 drivers/video/s3c24xx.c          |  4 ++--
 drivers/video/sdl.c              |  4 ++--
 drivers/video/stm.c              |  4 ++--
 include/fb.h                     | 16 ++++++++++++++--
 9 files changed, 40 insertions(+), 26 deletions(-)

diff --git a/drivers/video/atmel_lcdfb_core.c b/drivers/video/atmel_lcdfb_core.c
index bed540d..4c912cc 100644
--- a/drivers/video/atmel_lcdfb_core.c
+++ b/drivers/video/atmel_lcdfb_core.c
@@ -269,8 +269,8 @@ int atmel_lcdc_register(struct device_d *dev, struct atmel_lcdfb_devdata *data)
 	info = &sinfo->info;
 	info->priv = sinfo;
 	info->fbops = &atmel_lcdc_ops;
-	info->mode_list = pdata->mode_list;
-	info->num_modes = pdata->num_modes;
+	info->modes.modes = pdata->mode_list;
+	info->modes.num_modes = pdata->num_modes;
 	info->mode = &info->mode_list[0];
 	info->xres = info->mode->xres;
 	info->yres = info->mode->yres;
diff --git a/drivers/video/fb.c b/drivers/video/fb.c
index c36b9ad..e614d77 100644
--- a/drivers/video/fb.c
+++ b/drivers/video/fb.c
@@ -53,6 +53,7 @@ static int fb_setup_mode(struct device_d *dev, struct param_d *param,
 		const char *val)
 {
 	struct fb_info *info = dev->priv;
+	struct display_timings *dt;
 	int mode, ret;
 
 	if (info->enabled != 0)
@@ -61,14 +62,15 @@ static int fb_setup_mode(struct device_d *dev, struct param_d *param,
 	if (!val)
 		return dev_param_set_generic(dev, param, NULL);
 
-	for (mode = 0; mode < info->num_modes; mode++) {
-		if (!strcmp(info->mode_list[mode].name, val))
+	dt = &info->modes;
+	for (mode = 0; mode < dt->num_modes; mode++) {
+		if (!strcmp(dt->modes[mode].name, val))
 			break;
 	}
-	if (mode >= info->num_modes)
+	if (mode >= dt->num_modes)
 		return -EINVAL;
 
-	info->mode = &info->mode_list[mode];
+	info->mode = &dt->modes[mode];
 
 	info->xres = info->mode->xres;
 	info->yres = info->mode->yres;
@@ -105,13 +107,13 @@ static void fb_info(struct device_d *dev)
 	struct fb_info *info = dev->priv;
 	int i;
 
-	if (!info->num_modes)
+	if (!info->modes.num_modes)
 		return;
 
 	printf("available modes:\n");
 
-	for (i = 0; i < info->num_modes; i++) {
-		struct fb_videomode *mode = &info->mode_list[i];
+	for (i = 0; i < info->modes.num_modes; i++) {
+		struct fb_videomode *mode = &info->modes.modes[i];
 
 		printf("%-10s %dx%d@%d\n", mode->name,
 				mode->xres, mode->yres, mode->refresh);
@@ -155,10 +157,10 @@ int register_framebuffer(struct fb_info *info)
 	dev_add_param_bool(dev, "enable", fb_enable_set, NULL,
 			&info->p_enable, info);
 
-	if (info->num_modes && (info->mode_list != NULL) &&
+	if (info->modes.num_modes &&
 			(info->fbops->fb_activate_var != NULL)) {
 		dev_add_param(dev, "mode_name", fb_setup_mode, NULL, 0);
-		dev_set_param(dev, "mode_name", info->mode_list[0].name);
+		dev_set_param(dev, "mode_name", info->modes.modes[0].name);
 	}
 
 	ret = devfs_create(&info->cdev);
diff --git a/drivers/video/imx-ipu-fb.c b/drivers/video/imx-ipu-fb.c
index 7276647..0ee2b26 100644
--- a/drivers/video/imx-ipu-fb.c
+++ b/drivers/video/imx-ipu-fb.c
@@ -1007,8 +1007,8 @@ static int imxfb_probe(struct device_d *dev)
 	fbi->disable_fractional_divider = pdata->disable_fractional_divider;
 	info->priv = fbi;
 	info->fbops = &imxfb_ops;
-	info->num_modes = pdata->num_modes;
-	info->mode_list = pdata->mode;
+	info->modes.modes = pdata->mode;
+	info->modes.num_modes = pdata->num_modes;
 
 	imxfb_init_info(info, pdata->mode, pdata->bpp);
 
diff --git a/drivers/video/imx.c b/drivers/video/imx.c
index 05c6105..1dd6511 100644
--- a/drivers/video/imx.c
+++ b/drivers/video/imx.c
@@ -294,7 +294,7 @@ static int imxfb_activate_var(struct fb_info *info)
 	u32 pcr;
 	int i;
 
-	for (i = 0; i < info->num_modes; i++) {
+	for (i = 0; i < info->modes.num_modes; i++) {
 		if (!strcmp(fbi->mode[i].mode.name, mode->name)) {
 			fbi->pcr = fbi->mode[i].pcr;
 			break;
@@ -551,8 +551,8 @@ static int imxfb_probe(struct device_d *dev)
 	fbi->enable = pdata->enable;
 	fbi->dev = dev;
 	info->priv = fbi;
-	info->mode_list = mode_list;
-	info->num_modes = pdata->num_modes;
+	info->modes.modes = mode_list;
+	info->modes.num_modes = pdata->num_modes;
 	info->mode = &pdata->mode->mode;
 	info->xres = pdata->mode->mode.xres;
 	info->yres = pdata->mode->mode.yres;
diff --git a/drivers/video/omap.c b/drivers/video/omap.c
index 487aca6..485cc75 100644
--- a/drivers/video/omap.c
+++ b/drivers/video/omap.c
@@ -467,8 +467,8 @@ static int omapfb_probe(struct device_d *dev)
 	for (i = 0; i < pdata->num_displays; ++i)
 		fbi->video_modes[i] = pdata->displays[i].mode;
 
-	info->mode_list = fbi->video_modes;
-	info->num_modes = pdata->num_displays;
+	info->modes.modes = fbi->video_modes;
+	info->modes.num_modes = pdata->num_displays;
 
 	info->priv = fbi;
 	info->fbops = &omapfb_ops;
diff --git a/drivers/video/s3c24xx.c b/drivers/video/s3c24xx.c
index c3e05c6..cf45376 100644
--- a/drivers/video/s3c24xx.c
+++ b/drivers/video/s3c24xx.c
@@ -376,8 +376,8 @@ static int s3cfb_probe(struct device_d *hw_dev)
 	hw_dev->priv = &fbi;
 
 	/* add runtime video info */
-	fbi.info.mode_list = pdata->mode_list;
-	fbi.info.num_modes = pdata->mode_cnt;
+	fbi.info.modes.modes = pdata->mode_list;
+	fbi.info.modes.num_modes = pdata->mode_cnt;
 	fbi.info.mode = &fbi.info.mode_list[1];
 	fbi.info.xres = fbi.info.mode->xres;
 	fbi.info.yres = fbi.info.mode->yres;
diff --git a/drivers/video/sdl.c b/drivers/video/sdl.c
index 8dec5e5..a568340 100644
--- a/drivers/video/sdl.c
+++ b/drivers/video/sdl.c
@@ -37,8 +37,8 @@ static int sdlfb_probe(struct device_d *dev)
 		return -EIO;
 
 	fb = xzalloc(sizeof(*fb));
-	fb->mode_list = fb->mode = dev->platform_data;
-	fb->num_modes = 1;
+	fb->modes.modes = fb->mode = dev->platform_data;
+	fb->modes.num_modes = 1;
 	fb->bits_per_pixel = 4 << 3;
 	fb->xres = fb->mode->xres;
 	fb->yres = fb->mode->yres;
diff --git a/drivers/video/stm.c b/drivers/video/stm.c
index fdeaf9c..b20e552 100644
--- a/drivers/video/stm.c
+++ b/drivers/video/stm.c
@@ -499,8 +499,8 @@ static int stmfb_probe(struct device_d *hw_dev)
 	clk_enable(fbi.clk);
 
 	/* add runtime video info */
-	fbi.info.mode_list = pdata->mode_list;
-	fbi.info.num_modes = pdata->mode_cnt;
+	fbi.info.modes.modes = pdata->mode_list;
+	fbi.info.modes.num_modes = pdata->mode_cnt;
 	fbi.info.mode = &fbi.info.mode_list[0];
 	fbi.info.xres = fbi.info.mode->xres;
 	fbi.info.yres = fbi.info.mode->yres;
diff --git a/include/fb.h b/include/fb.h
index 22fa9b1..1cc352b 100644
--- a/include/fb.h
+++ b/include/fb.h
@@ -77,10 +77,22 @@ struct fb_ops {
 	int (*fb_activate_var)(struct fb_info *info);
 };
 
+/*
+ * This describes all timing settings a display provides.
+ * The native_mode is the default setting for this display.
+ * Drivers that can handle multiple videomodes should work with this struct and
+ * convert each entry to the desired end result.
+ */
+struct display_timings {
+	unsigned int native_mode;
+
+	unsigned int num_modes;
+	struct fb_videomode *modes;
+};
+
 struct fb_info {
 	struct fb_videomode *mode;
-	struct fb_videomode *mode_list;
-	unsigned num_modes;
+	struct display_timings modes;
 
 	struct fb_ops *fbops;
 	struct device_d dev;		/* This is this fb device */
-- 
1.9.0



From s.hauer at pengutronix.de  Fri Mar 14 10:32:39 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 14 Mar 2014 15:32:39 +0100
Subject: [PATCH 19/29] ARM: i.MX6: Add video clocks
In-Reply-To: <1394807569-23620-1-git-send-email-s.hauer@pengutronix.de>
References: <1394807569-23620-1-git-send-email-s.hauer@pengutronix.de>
Message-ID: <1394807569-23620-20-git-send-email-s.hauer@pengutronix.de>

This adds the IPU, LVDS and HDMI clocks. As these are many, depend
on the IPU driver being compiled in.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/mach-imx/clk-imx6.c               | 153 ++++++++++++++++++++++++++++-
 arch/arm/mach-imx/clk.h                    |   6 ++
 arch/arm/mach-imx/include/mach/imx6-regs.h |   3 +
 3 files changed, 158 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-imx/clk-imx6.c b/arch/arm/mach-imx/clk-imx6.c
index db16bb5..518fc00 100644
--- a/arch/arm/mach-imx/clk-imx6.c
+++ b/arch/arm/mach-imx/clk-imx6.c
@@ -19,6 +19,8 @@
 #include <linux/clkdev.h>
 #include <linux/err.h>
 #include <mach/imx6-regs.h>
+#include <mach/revision.h>
+#include <mach/imx6.h>
 
 #include "clk.h"
 
@@ -84,8 +86,10 @@ enum mx6q_clks {
 	usdhc4, vdo_axi, vpu_axi, cko1, pll1_sys, pll2_bus, pll3_usb_otg,
 	pll4_audio, pll5_video, pll8_mlb, pll7_usb_host, pll6_enet, ssi1_ipg,
 	ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2, ldb_di0_div_3_5, ldb_di1_div_3_5,
-	sata_ref, pcie_ref, sata_ref_100m, pcie_ref_125m, enet_ref,
-	clk_max
+	sata_ref, sata_ref_100m, pcie_ref, pcie_ref_125m, enet_ref, usbphy1_gate,
+	usbphy2_gate, pll4_post_div, pll5_post_div, pll5_video_div, eim_slow,
+	spdif, cko2_sel, cko2_podf, cko2, cko, vdoa, pll4_audio_div,
+	lvds1_sel, lvds2_sel, lvds1_gate, lvds2_gate, clk_max
 };
 
 static struct clk *clks[clk_max];
@@ -171,6 +175,62 @@ static const char *cko1_sels[] = {
 	"pll4_audio",
 };
 
+static const char *ipu_sels[] = {
+	"mmdc_ch0_axi_podf",
+	"pll2_pfd2_396m",
+	"pll3_120m",
+	"pll3_pfd1_540m",
+};
+
+static const char *ldb_di_sels[] = {
+	"pll5_video_div",
+	"pll2_pfd0_352m",
+	"pll2_pfd2_396m",
+	"mmdc_ch1_axi_podf",
+	"pll3_usb_otg",
+};
+
+static const char *ipu_di_pre_sels[] = {
+	"mmdc_ch0_axi",
+	"pll3_usb_otg",
+	"pll5_video_div",
+	"pll2_pfd0_352m",
+	"pll2_pfd2_396m",
+	"pll3_pfd1_540m",
+};
+
+static const char *ipu1_di0_sels[] = {
+	"ipu1_di0_pre",
+	"dummy",
+	"dummy",
+	"ldb_di0_podf",
+	"ldb_di1_podf",
+};
+
+static const char *ipu1_di1_sels[] = {
+	"ipu1_di1_pre",
+	"dummy",
+	"dummy",
+	"ldb_di0_podf",
+	"ldb_di1_podf",
+};
+
+static const char *ipu2_di0_sels[] = {
+	"ipu2_di0_pre",
+	"dummy",
+	"dummy",
+	"ldb_di0_podf",
+	"ldb_di1_podf",
+};
+
+static const char *ipu2_di1_sels[] = {
+	"ipu2_di1_pre",
+	"dummy",
+	"dummy",
+	"ldb_di0_podf",
+	"ldb_di1_podf",
+};
+
 static struct clk_div_table clk_enet_ref_table[] = {
 	{ .val = 0, .div = 20, },
 	{ .val = 1, .div = 10, },
@@ -179,6 +239,86 @@ static struct clk_div_table clk_enet_ref_table[] = {
 	{ },
 };
 
+static struct clk_div_table post_div_table[] = {
+	{ .val = 2, .div = 1, },
+	{ .val = 1, .div = 2, },
+	{ .val = 0, .div = 4, },
+	{ /* sentinel */ }
+};
+
+static struct clk_div_table video_div_table[] = {
+	{ .val = 0, .div = 1, },
+	{ .val = 1, .div = 2, },
+	{ .val = 2, .div = 1, },
+	{ .val = 3, .div = 4, },
+	{ /* sentinel */ }
+};
+
+static void imx6_add_video_clks(void __iomem *anab, void __iomem *cb)
+{
+	clks[pll5_post_div] = imx_clk_divider_table("pll5_post_div", "pll5_video", anab + 0xa0, 19, 2, post_div_table);
+	clks[pll5_video_div] = imx_clk_divider_table("pll5_video_div", "pll5_post_div", anab + 0x170, 30, 2, video_div_table);
+
+	clks[ipu1_sel]         = imx_clk_mux("ipu1_sel",         cb + 0x3c, 9,  2, ipu_sels,          ARRAY_SIZE(ipu_sels));
+	clks[ipu2_sel]         = imx_clk_mux("ipu2_sel",         cb + 0x3c, 14, 2, ipu_sels,          ARRAY_SIZE(ipu_sels));
+	clks[ldb_di0_sel]      = imx_clk_mux_p("ldb_di0_sel",      cb + 0x2c, 9,  3, ldb_di_sels,       ARRAY_SIZE(ldb_di_sels));
+	clks[ldb_di1_sel]      = imx_clk_mux_p("ldb_di1_sel",      cb + 0x2c, 12, 3, ldb_di_sels,       ARRAY_SIZE(ldb_di_sels));
+	clks[ipu1_di0_pre_sel] = imx_clk_mux_p("ipu1_di0_pre_sel", cb + 0x34, 6,  3, ipu_di_pre_sels,   ARRAY_SIZE(ipu_di_pre_sels));
+	clks[ipu1_di1_pre_sel] = imx_clk_mux_p("ipu1_di1_pre_sel", cb + 0x34, 15, 3, ipu_di_pre_sels,   ARRAY_SIZE(ipu_di_pre_sels));
+	clks[ipu2_di0_pre_sel] = imx_clk_mux_p("ipu2_di0_pre_sel", cb + 0x38, 6,  3, ipu_di_pre_sels,   ARRAY_SIZE(ipu_di_pre_sels));
+	clks[ipu2_di1_pre_sel] = imx_clk_mux_p("ipu2_di1_pre_sel", cb + 0x38, 15, 3, ipu_di_pre_sels,   ARRAY_SIZE(ipu_di_pre_sels));
+	clks[ipu1_di0_sel]     = imx_clk_mux_p("ipu1_di0_sel",     cb + 0x34, 0,  3, ipu1_di0_sels,     ARRAY_SIZE(ipu1_di0_sels));
+	clks[ipu1_di1_sel]     = imx_clk_mux_p("ipu1_di1_sel",     cb + 0x34, 9,  3, ipu1_di1_sels,     ARRAY_SIZE(ipu1_di1_sels));
+	clks[ipu2_di0_sel]     = imx_clk_mux_p("ipu2_di0_sel",     cb + 0x38, 0,  3, ipu2_di0_sels,     ARRAY_SIZE(ipu2_di0_sels));
+	clks[ipu2_di1_sel]     = imx_clk_mux_p("ipu2_di1_sel",     cb + 0x38, 9,  3, ipu2_di1_sels,     ARRAY_SIZE(ipu2_di1_sels));
+
+	clks[ipu1_podf]        = imx_clk_divider("ipu1_podf",        "ipu1_sel",          cb + 0x3c, 11, 3);
+	clks[ipu2_podf]        = imx_clk_divider("ipu2_podf",        "ipu2_sel",          cb + 0x3c, 16, 3);
+	clks[ldb_di0_div_3_5]  = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7);
+	clks[ldb_di0_podf]     = imx_clk_divider("ldb_di0_podf", "ldb_di0_div_3_5", cb + 0x20, 10, 1);
+	clks[ldb_di1_div_3_5]  = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7);
+	clks[ldb_di1_podf]     = imx_clk_divider("ldb_di1_podf", "ldb_di1_div_3_5", cb + 0x20, 11, 1);
+	clks[ipu1_di0_pre]     = imx_clk_divider("ipu1_di0_pre",     "ipu1_di0_pre_sel",  cb + 0x34, 3,  3);
+	clks[ipu1_di1_pre]     = imx_clk_divider("ipu1_di1_pre",     "ipu1_di1_pre_sel",  cb + 0x34, 12, 3);
+	clks[ipu2_di0_pre]     = imx_clk_divider("ipu2_di0_pre",     "ipu2_di0_pre_sel",  cb + 0x38, 3,  3);
+	clks[ipu2_di1_pre]     = imx_clk_divider("ipu2_di1_pre",     "ipu2_di1_pre_sel",  cb + 0x38, 12, 3);
+
+	clkdev_add_physbase(clks[ipu1_podf], MX6_IPU1_BASE_ADDR, "bus");
+	clkdev_add_physbase(clks[ipu1_di0_sel], MX6_IPU1_BASE_ADDR, "di0");
+	clkdev_add_physbase(clks[ipu1_di1_sel], MX6_IPU1_BASE_ADDR, "di1");
+	clkdev_add_physbase(clks[ipu2_podf], MX6_IPU2_BASE_ADDR, "bus");
+	clkdev_add_physbase(clks[ipu2_di0_sel], MX6_IPU2_BASE_ADDR, "di0");
+	clkdev_add_physbase(clks[ipu2_di1_sel], MX6_IPU2_BASE_ADDR, "di1");
+
+	clkdev_add_physbase(clks[ldb_di0_sel], 0x020e0008, "di0_pll");
+	clkdev_add_physbase(clks[ldb_di1_sel], 0x020e0008, "di1_pll");
+	clkdev_add_physbase(clks[ipu1_di0_sel], 0x020e0008, "di0_sel");
+	clkdev_add_physbase(clks[ipu1_di1_sel], 0x020e0008, "di1_sel");
+	clkdev_add_physbase(clks[ipu2_di0_sel], 0x020e0008, "di2_sel");
+	clkdev_add_physbase(clks[ipu2_di1_sel], 0x020e0008, "di3_sel");
+	clkdev_add_physbase(clks[ldb_di0], 0x020e0008, "di0");
+	clkdev_add_physbase(clks[ldb_di1], 0x020e0008, "di1");
+	clkdev_add_physbase(clks[ahb], 0x00120000, "iahb");
+	clkdev_add_physbase(clks[pll3_pfd1_540m], 0x00120000, "isfr");
+
+	clk_set_parent(clks[ipu1_di0_sel], clks[ipu1_di0_pre]);
+	clk_set_parent(clks[ipu1_di1_sel], clks[ipu1_di1_pre]);
+	clk_set_parent(clks[ipu2_di0_sel], clks[ipu2_di0_pre]);
+	clk_set_parent(clks[ipu2_di1_sel], clks[ipu2_di1_pre]);
+
+	clk_set_parent(clks[ipu1_di0_pre_sel], clks[pll5_video_div]);
+	clk_set_parent(clks[ipu1_di1_pre_sel], clks[pll5_video_div]);
+	clk_set_parent(clks[ipu2_di0_pre_sel], clks[pll5_video_div]);
+	clk_set_parent(clks[ipu2_di1_pre_sel], clks[pll5_video_div]);
+
+	if ((imx_silicon_revision() != IMX_CHIP_REV_1_0) ||
+	    cpu_is_mx6dl()) {
+		clk_set_parent(clks[ldb_di0_sel], clks[pll5_video_div]);
+		clk_set_parent(clks[ldb_di1_sel], clks[pll5_video_div]);
+	}
+
+}
+
 static int imx6_ccm_probe(struct device_d *dev)
 {
 	void __iomem *base, *anatop_base, *ccm_base;
@@ -281,7 +421,6 @@ static int imx6_ccm_probe(struct device_d *dev)
 	clks[arm]               = imx_clk_busy_divider("arm",               "pll1_sw",     base + 0x10, 0,   3,   base + 0x48, 16);
 	clks[ahb]               = imx_clk_busy_divider("ahb",               "periph",      base + 0x14, 10,  3,   base + 0x48, 1);
 
-
 	clkdev_add_physbase(clks[uart_serial_podf], MX6_UART1_BASE_ADDR, NULL);
 	clkdev_add_physbase(clks[uart_serial_podf], MX6_UART2_BASE_ADDR, NULL);
 	clkdev_add_physbase(clks[uart_serial_podf], MX6_UART3_BASE_ADDR, NULL);
@@ -310,10 +449,16 @@ static int imx6_ccm_probe(struct device_d *dev)
 	clkdev_add_physbase(clks[ipg_per], MX6_PWM3_BASE_ADDR, "per");
 	clkdev_add_physbase(clks[ipg_per], MX6_PWM4_BASE_ADDR, "per");
 
+	if (IS_ENABLED(CONFIG_DRIVER_VIDEO_IMX_IPUV3))
+		imx6_add_video_clks(anatop_base, ccm_base);
+
 	writel(0xffffffff, ccm_base + CCGR0);
 	writel(0xf0ffffff, ccm_base + CCGR1); /* gate GPU3D, GPU2D */
 	writel(0xffffffff, ccm_base + CCGR2);
-	writel(0x3fff0000, ccm_base + CCGR3); /* gate OpenVG, LDB, IPU1, IPU2 */
+	if (IS_ENABLED(CONFIG_DRIVER_VIDEO_IMX_IPUV3))
+		writel(0xffffffff, ccm_base + CCGR3); /* gate OpenVG */
+	else
+		writel(0x3fffffff, ccm_base + CCGR3); /* gate OpenVG, LDB, IPU1, IPU2 */
 	writel(0xffffffff, ccm_base + CCGR4);
 	writel(0xffffffff, ccm_base + CCGR5);
 	writel(0xffff3fff, ccm_base + CCGR6); /* gate VPU */
diff --git a/arch/arm/mach-imx/clk.h b/arch/arm/mach-imx/clk.h
index d83266b..32a02db 100644
--- a/arch/arm/mach-imx/clk.h
+++ b/arch/arm/mach-imx/clk.h
@@ -27,6 +27,12 @@ static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg,
 	return clk_mux(name, reg, shift, width, parents, num_parents, 0);
 }
 
+static inline struct clk *imx_clk_mux_p(const char *name, void __iomem *reg,
+		u8 shift, u8 width, const char **parents, u8 num_parents)
+{
+	return clk_mux(name, reg, shift, width, parents, num_parents, CLK_SET_RATE_PARENT);
+}
+
 static inline struct clk *imx_clk_gate(const char *name, const char *parent,
 		void __iomem *reg, u8 shift)
 {
diff --git a/arch/arm/mach-imx/include/mach/imx6-regs.h b/arch/arm/mach-imx/include/mach/imx6-regs.h
index 833280a..facbe51 100644
--- a/arch/arm/mach-imx/include/mach/imx6-regs.h
+++ b/arch/arm/mach-imx/include/mach/imx6-regs.h
@@ -26,6 +26,9 @@
 #define MX6_SPBA_BASE_ADDR              (MX6_ATZ1_BASE_ADDR + 0x3C000)
 #define MX6_VPU_BASE_ADDR               (MX6_ATZ1_BASE_ADDR + 0x40000)
 
+#define MX6_IPU1_BASE_ADDR		0x02400000
+#define MX6_IPU2_BASE_ADDR		0x02800000
+
 /* ATZ#1- On Platform */
 #define MX6_AIPS1_ON_BASE_ADDR          (MX6_ATZ1_BASE_ADDR + 0x7C000)
 
-- 
1.9.0



From s.hauer at pengutronix.de  Fri Mar 14 10:32:49 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 14 Mar 2014 15:32:49 +0100
Subject: [PATCH 29/29] ARM: update imx_v7_defconfig
In-Reply-To: <1394807569-23620-1-git-send-email-s.hauer@pengutronix.de>
References: <1394807569-23620-1-git-send-email-s.hauer@pengutronix.de>
Message-ID: <1394807569-23620-30-git-send-email-s.hauer@pengutronix.de>

- Enable loadenv command
- Enable mtd/NAND/UBI/UBIFS support
- Enable IPUv3 support
- Enable splash support

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/configs/imx_v7_defconfig | 26 ++++++++++++++++++++++++--
 1 file changed, 24 insertions(+), 2 deletions(-)

diff --git a/arch/arm/configs/imx_v7_defconfig b/arch/arm/configs/imx_v7_defconfig
index e821061..f29c968 100644
--- a/arch/arm/configs/imx_v7_defconfig
+++ b/arch/arm/configs/imx_v7_defconfig
@@ -12,9 +12,11 @@ CONFIG_MACH_REALQ7=y
 CONFIG_MACH_GK802=y
 CONFIG_MACH_TQMA6X=y
 CONFIG_MACH_SABRELITE=y
+CONFIG_MACH_SABRESD=y
 CONFIG_MACH_NITROGEN6X=y
 CONFIG_MACH_SOLIDRUN_HUMMINGBOARD=y
 CONFIG_MACH_UDOO=y
+CONFIG_MACH_VARISCITE_MX6=y
 CONFIG_IMX_IIM=y
 CONFIG_IMX_IIM_FUSE_BLOW=y
 CONFIG_IMX_OCOTP=y
@@ -41,9 +43,11 @@ CONFIG_CMD_EDIT=y
 CONFIG_CMD_SLEEP=y
 CONFIG_CMD_MSLEEP=y
 CONFIG_CMD_SAVEENV=y
+CONFIG_CMD_LOADENV=y
 CONFIG_CMD_EXPORT=y
 CONFIG_CMD_PRINTENV=y
 CONFIG_CMD_READLINE=y
+CONFIG_CMD_READF=y
 CONFIG_CMD_LET=y
 CONFIG_CMD_MENU=y
 CONFIG_CMD_MENU_MANAGEMENT=y
@@ -72,6 +76,7 @@ CONFIG_CMD_OFTREE=y
 CONFIG_CMD_OF_PROPERTY=y
 CONFIG_CMD_OF_NODE=y
 CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_SPLASH=y
 CONFIG_CMD_BAREBOX_UPDATE=y
 CONFIG_CMD_TIMEOUT=y
 CONFIG_CMD_PARTITION=y
@@ -94,8 +99,8 @@ CONFIG_NET_NETCONSOLE=y
 CONFIG_NET_RESOLV=y
 CONFIG_OFDEVICE=y
 CONFIG_OF_BAREBOX_DRIVERS=y
-CONFIG_AT803X_PHY=y
 CONFIG_DRIVER_NET_FEC_IMX=y
+CONFIG_AT803X_PHY=y
 CONFIG_NET_USB=y
 CONFIG_NET_USB_ASIX=y
 CONFIG_NET_USB_SMSC95XX=y
@@ -107,6 +112,13 @@ CONFIG_MTD_RAW_DEVICE=y
 CONFIG_MTD_DATAFLASH=y
 CONFIG_MTD_M25P80=y
 CONFIG_MTD_SST25L=y
+CONFIG_NAND=y
+CONFIG_NAND_ALLOW_ERASE_BAD=y
+CONFIG_NAND_IMX=y
+CONFIG_NAND_IMX_BBM=y
+CONFIG_NAND_MXS=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_FASTMAP=y
 CONFIG_DISK_AHCI=y
 CONFIG_DISK_AHCI_IMX=y
 CONFIG_DISK_INTF_PLATFORM_IDE=y
@@ -118,6 +130,12 @@ CONFIG_USB_ULPI=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DFU=y
+CONFIG_VIDEO=y
+CONFIG_DRIVER_VIDEO_IMX_IPUV3=y
+CONFIG_DRIVER_VIDEO_IMX_IPUV3_LVDS=y
+CONFIG_DRIVER_VIDEO_IMX_IPUV3_HDMI=y
+CONFIG_DRIVER_VIDEO_SIMPLEFB=y
+CONFIG_DRIVER_VIDEO_EDID=y
 CONFIG_MCI=y
 CONFIG_MCI_MMC_BOOT_PARTITIONS=y
 CONFIG_MCI_IMX_ESDHC=y
@@ -133,6 +151,9 @@ CONFIG_EEPROM_AT24=y
 CONFIG_KEYBOARD_GPIO=y
 CONFIG_WATCHDOG=y
 CONFIG_WATCHDOG_IMX=y
+CONFIG_PWM=y
+CONFIG_PWM_IMX=y
+CONFIG_MXS_APBH_DMA=y
 CONFIG_GPIO_STMPE=y
 CONFIG_FS_EXT4=y
 CONFIG_FS_TFTP=y
@@ -140,4 +161,5 @@ CONFIG_FS_NFS=y
 CONFIG_FS_FAT=y
 CONFIG_FS_FAT_WRITE=y
 CONFIG_FS_FAT_LFN=y
-CONFIG_LZO_DECOMPRESS=y
+CONFIG_FS_UBIFS=y
+CONFIG_FS_UBIFS_COMPRESSION_LZO=y
-- 
1.9.0



From s.hauer at pengutronix.de  Fri Mar 14 10:32:36 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 14 Mar 2014 15:32:36 +0100
Subject: [PATCH 16/29] clk: clk-fixed-factor: add set_rate/round_rate callbacks
In-Reply-To: <1394807569-23620-1-git-send-email-s.hauer@pengutronix.de>
References: <1394807569-23620-1-git-send-email-s.hauer@pengutronix.de>
Message-ID: <1394807569-23620-17-git-send-email-s.hauer@pengutronix.de>

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 drivers/clk/clk-fixed-factor.c | 30 ++++++++++++++++++++++++++++++
 1 file changed, 30 insertions(+)

diff --git a/drivers/clk/clk-fixed-factor.c b/drivers/clk/clk-fixed-factor.c
index df0d2f3..cb531b1 100644
--- a/drivers/clk/clk-fixed-factor.c
+++ b/drivers/clk/clk-fixed-factor.c
@@ -35,7 +35,37 @@ static unsigned long clk_fixed_factor_recalc_rate(struct clk *clk,
 	return (parent_rate / f->div) * f->mult;
 }
 
+static long clk_factor_round_rate(struct clk *clk, unsigned long rate,
+		unsigned long *prate)
+{
+	struct clk_fixed_factor *fix = container_of(clk, struct clk_fixed_factor, clk);
+
+	if (clk->flags & CLK_SET_RATE_PARENT) {
+		unsigned long best_parent;
+
+		best_parent = (rate / fix->mult) * fix->div;
+		*prate = clk_round_rate(clk_get_parent(clk), best_parent);
+	}
+
+	return (*prate / fix->div) * fix->mult;
+}
+
+static int clk_factor_set_rate(struct clk *clk, unsigned long rate,
+		unsigned long parent_rate)
+{
+	struct clk_fixed_factor *fix = container_of(clk, struct clk_fixed_factor, clk);
+
+	if (clk->flags & CLK_SET_RATE_PARENT) {
+		printk("%s: %ld -> parent %ld\n", __func__, rate, rate * fix->div / fix->mult);
+		return clk_set_rate(clk_get_parent(clk), rate * fix->div / fix->mult);
+	}
+
+	return 0;
+}
+
 static struct clk_ops clk_fixed_factor_ops = {
+	.set_rate = clk_factor_set_rate,
+	.round_rate = clk_factor_round_rate,
 	.recalc_rate = clk_fixed_factor_recalc_rate,
 };
 
-- 
1.9.0



From s.hauer at pengutronix.de  Fri Mar 14 10:32:31 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 14 Mar 2014 15:32:31 +0100
Subject: [PATCH 11/29] clk: clk-fixed-factor: pass flags to initializers
In-Reply-To: <1394807569-23620-1-git-send-email-s.hauer@pengutronix.de>
References: <1394807569-23620-1-git-send-email-s.hauer@pengutronix.de>
Message-ID: <1394807569-23620-12-git-send-email-s.hauer@pengutronix.de>

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/mach-imx/clk.h        | 2 +-
 drivers/clk/clk-fixed-factor.c | 3 ++-
 drivers/clk/mvebu/common.c     | 2 +-
 drivers/clk/mxs/clk.h          | 2 +-
 include/linux/clk.h            | 3 ++-
 5 files changed, 7 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-imx/clk.h b/arch/arm/mach-imx/clk.h
index 072af55..54f04ed 100644
--- a/arch/arm/mach-imx/clk.h
+++ b/arch/arm/mach-imx/clk.h
@@ -10,7 +10,7 @@ static inline struct clk *imx_clk_divider(const char *name, const char *parent,
 static inline struct clk *imx_clk_fixed_factor(const char *name,
 		const char *parent, unsigned int mult, unsigned int div)
 {
-	return clk_fixed_factor(name, parent, mult, div);
+	return clk_fixed_factor(name, parent, mult, div, 0);
 }
 
 static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg,
diff --git a/drivers/clk/clk-fixed-factor.c b/drivers/clk/clk-fixed-factor.c
index f0ecbd3..df0d2f3 100644
--- a/drivers/clk/clk-fixed-factor.c
+++ b/drivers/clk/clk-fixed-factor.c
@@ -40,7 +40,7 @@ static struct clk_ops clk_fixed_factor_ops = {
 };
 
 struct clk *clk_fixed_factor(const char *name,
-		const char *parent, unsigned int mult, unsigned int div)
+		const char *parent, unsigned int mult, unsigned int div, unsigned flags)
 {
 	struct clk_fixed_factor *f = xzalloc(sizeof(*f));
 	int ret;
@@ -50,6 +50,7 @@ struct clk *clk_fixed_factor(const char *name,
 	f->parent = parent;
 	f->clk.ops = &clk_fixed_factor_ops;
 	f->clk.name = name;
+	f->clk.flags = flags;
 	f->clk.parent_names = &f->parent;
 	f->clk.num_parents = 1;
 
diff --git a/drivers/clk/mvebu/common.c b/drivers/clk/mvebu/common.c
index aa1e8f6..658ce3e 100644
--- a/drivers/clk/mvebu/common.c
+++ b/drivers/clk/mvebu/common.c
@@ -87,7 +87,7 @@ int mvebu_coreclk_probe(struct device_d *dev)
 					      2+n, &rclk_name);
 		desc->get_clk_ratio(base, desc->ratios[n].id, &mult, &div);
 		clk_data.clks[2+n] = clk_fixed_factor(rclk_name, cpuclk_name,
-						mult, div);
+						mult, div, 0);
 		WARN_ON(IS_ERR(clk_data.clks[2+n]));
 	};
 
diff --git a/drivers/clk/mxs/clk.h b/drivers/clk/mxs/clk.h
index 168fa58..7bab7b5 100644
--- a/drivers/clk/mxs/clk.h
+++ b/drivers/clk/mxs/clk.h
@@ -46,7 +46,7 @@ static inline struct clk *mxs_clk_mux(const char *name, void __iomem *reg,
 static inline struct clk *mxs_clk_fixed_factor(const char *name,
 		const char *parent_name, unsigned int mult, unsigned int div)
 {
-	return clk_fixed_factor(name, parent_name, mult, div);
+	return clk_fixed_factor(name, parent_name, mult, div, 0);
 }
 
 #endif /* __MXS_CLK_H */
diff --git a/include/linux/clk.h b/include/linux/clk.h
index 21edfab..e65a62a 100644
--- a/include/linux/clk.h
+++ b/include/linux/clk.h
@@ -249,7 +249,8 @@ struct clk *clk_divider_table(const char *name,
 		const char *parent, void __iomem *reg, u8 shift, u8 width,
 		const struct clk_div_table *table);
 struct clk *clk_fixed_factor(const char *name,
-		const char *parent, unsigned int mult, unsigned int div);
+		const char *parent, unsigned int mult, unsigned int div,
+		unsigned flags);
 
 struct clk *clk_mux_alloc(const char *name, void __iomem *reg,
 		u8 shift, u8 width, const char **parents, u8 num_parents,
-- 
1.9.0



From s.hauer at pengutronix.de  Fri Mar 14 10:32:45 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 14 Mar 2014 15:32:45 +0100
Subject: [PATCH 25/29] video: Add kernel fourcc defines
In-Reply-To: <1394807569-23620-1-git-send-email-s.hauer@pengutronix.de>
References: <1394807569-23620-1-git-send-email-s.hauer@pengutronix.de>
Message-ID: <1394807569-23620-26-git-send-email-s.hauer@pengutronix.de>

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 include/video/fourcc.h | 261 +++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 261 insertions(+)
 create mode 100644 include/video/fourcc.h

diff --git a/include/video/fourcc.h b/include/video/fourcc.h
new file mode 100644
index 0000000..322142c
--- /dev/null
+++ b/include/video/fourcc.h
@@ -0,0 +1,261 @@
+#ifndef __VIDEO_FOURCC_H
+#define __VIDEO_FOURCC_H
+
+/*  Four-character-code (FOURCC) */
+#define v4l2_fourcc(a, b, c, d)\
+	((__u32)(a) | ((__u32)(b) << 8) | ((__u32)(c) << 16) | ((__u32)(d) << 24))
+
+/*      Pixel format         FOURCC                          depth  Description  */
+
+/* RGB formats */
+#define V4L2_PIX_FMT_RGB332  v4l2_fourcc('R', 'G', 'B', '1') /*  8  RGB-3-3-2     */
+#define V4L2_PIX_FMT_RGB444  v4l2_fourcc('R', '4', '4', '4') /* 16  xxxxrrrr ggggbbbb */
+#define V4L2_PIX_FMT_RGB555  v4l2_fourcc('R', 'G', 'B', 'O') /* 16  RGB-5-5-5     */
+#define V4L2_PIX_FMT_RGB565  v4l2_fourcc('R', 'G', 'B', 'P') /* 16  RGB-5-6-5     */
+#define V4L2_PIX_FMT_RGB555X v4l2_fourcc('R', 'G', 'B', 'Q') /* 16  RGB-5-5-5 BE  */
+#define V4L2_PIX_FMT_RGB565X v4l2_fourcc('R', 'G', 'B', 'R') /* 16  RGB-5-6-5 BE  */
+#define V4L2_PIX_FMT_BGR666  v4l2_fourcc('B', 'G', 'R', 'H') /* 18  BGR-6-6-6	  */
+#define V4L2_PIX_FMT_BGR24   v4l2_fourcc('B', 'G', 'R', '3') /* 24  BGR-8-8-8     */
+#define V4L2_PIX_FMT_RGB24   v4l2_fourcc('R', 'G', 'B', '3') /* 24  RGB-8-8-8     */
+#define V4L2_PIX_FMT_BGR32   v4l2_fourcc('B', 'G', 'R', '4') /* 32  BGR-8-8-8-8   */
+#define V4L2_PIX_FMT_RGB32   v4l2_fourcc('R', 'G', 'B', '4') /* 32  RGB-8-8-8-8   */
+
+/* Grey formats */
+#define V4L2_PIX_FMT_GREY    v4l2_fourcc('G', 'R', 'E', 'Y') /*  8  Greyscale     */
+#define V4L2_PIX_FMT_Y4      v4l2_fourcc('Y', '0', '4', ' ') /*  4  Greyscale     */
+#define V4L2_PIX_FMT_Y6      v4l2_fourcc('Y', '0', '6', ' ') /*  6  Greyscale     */
+#define V4L2_PIX_FMT_Y10     v4l2_fourcc('Y', '1', '0', ' ') /* 10  Greyscale     */
+#define V4L2_PIX_FMT_Y12     v4l2_fourcc('Y', '1', '2', ' ') /* 12  Greyscale     */
+#define V4L2_PIX_FMT_Y16     v4l2_fourcc('Y', '1', '6', ' ') /* 16  Greyscale     */
+
+/* Grey bit-packed formats */
+#define V4L2_PIX_FMT_Y10BPACK    v4l2_fourcc('Y', '1', '0', 'B') /* 10  Greyscale bit-packed */
+
+/* Palette formats */
+#define V4L2_PIX_FMT_PAL8    v4l2_fourcc('P', 'A', 'L', '8') /*  8  8-bit palette */
+
+/* Chrominance formats */
+#define V4L2_PIX_FMT_UV8     v4l2_fourcc('U', 'V', '8', ' ') /*  8  UV 4:4 */
+
+/* Luminance+Chrominance formats */
+#define V4L2_PIX_FMT_YVU410  v4l2_fourcc('Y', 'V', 'U', '9') /*  9  YVU 4:1:0     */
+#define V4L2_PIX_FMT_YVU420  v4l2_fourcc('Y', 'V', '1', '2') /* 12  YVU 4:2:0     */
+#define V4L2_PIX_FMT_YUYV    v4l2_fourcc('Y', 'U', 'Y', 'V') /* 16  YUV 4:2:2     */
+#define V4L2_PIX_FMT_YYUV    v4l2_fourcc('Y', 'Y', 'U', 'V') /* 16  YUV 4:2:2     */
+#define V4L2_PIX_FMT_YVYU    v4l2_fourcc('Y', 'V', 'Y', 'U') /* 16 YVU 4:2:2 */
+#define V4L2_PIX_FMT_UYVY    v4l2_fourcc('U', 'Y', 'V', 'Y') /* 16  YUV 4:2:2     */
+#define V4L2_PIX_FMT_VYUY    v4l2_fourcc('V', 'Y', 'U', 'Y') /* 16  YUV 4:2:2     */
+#define V4L2_PIX_FMT_YUV422P v4l2_fourcc('4', '2', '2', 'P') /* 16  YVU422 planar */
+#define V4L2_PIX_FMT_YUV411P v4l2_fourcc('4', '1', '1', 'P') /* 16  YVU411 planar */
+#define V4L2_PIX_FMT_Y41P    v4l2_fourcc('Y', '4', '1', 'P') /* 12  YUV 4:1:1     */
+#define V4L2_PIX_FMT_YUV444  v4l2_fourcc('Y', '4', '4', '4') /* 16  xxxxyyyy uuuuvvvv */
+#define V4L2_PIX_FMT_YUV555  v4l2_fourcc('Y', 'U', 'V', 'O') /* 16  YUV-5-5-5     */
+#define V4L2_PIX_FMT_YUV565  v4l2_fourcc('Y', 'U', 'V', 'P') /* 16  YUV-5-6-5     */
+#define V4L2_PIX_FMT_YUV32   v4l2_fourcc('Y', 'U', 'V', '4') /* 32  YUV-8-8-8-8   */
+#define V4L2_PIX_FMT_YUV410  v4l2_fourcc('Y', 'U', 'V', '9') /*  9  YUV 4:1:0     */
+#define V4L2_PIX_FMT_YUV420  v4l2_fourcc('Y', 'U', '1', '2') /* 12  YUV 4:2:0     */
+#define V4L2_PIX_FMT_HI240   v4l2_fourcc('H', 'I', '2', '4') /*  8  8-bit color   */
+#define V4L2_PIX_FMT_HM12    v4l2_fourcc('H', 'M', '1', '2') /*  8  YUV 4:2:0 16x16 macroblocks */
+#define V4L2_PIX_FMT_M420    v4l2_fourcc('M', '4', '2', '0') /* 12  YUV 4:2:0 2 lines y, 1 line uv interleaved */
+
+/* two planes -- one Y, one Cr + Cb interleaved  */
+#define V4L2_PIX_FMT_NV12    v4l2_fourcc('N', 'V', '1', '2') /* 12  Y/CbCr 4:2:0  */
+#define V4L2_PIX_FMT_NV21    v4l2_fourcc('N', 'V', '2', '1') /* 12  Y/CrCb 4:2:0  */
+#define V4L2_PIX_FMT_NV16    v4l2_fourcc('N', 'V', '1', '6') /* 16  Y/CbCr 4:2:2  */
+#define V4L2_PIX_FMT_NV61    v4l2_fourcc('N', 'V', '6', '1') /* 16  Y/CrCb 4:2:2  */
+#define V4L2_PIX_FMT_NV24    v4l2_fourcc('N', 'V', '2', '4') /* 24  Y/CbCr 4:4:4  */
+#define V4L2_PIX_FMT_NV42    v4l2_fourcc('N', 'V', '4', '2') /* 24  Y/CrCb 4:4:4  */
+
+/* two non contiguous planes - one Y, one Cr + Cb interleaved  */
+#define V4L2_PIX_FMT_NV12M   v4l2_fourcc('N', 'M', '1', '2') /* 12  Y/CbCr 4:2:0  */
+#define V4L2_PIX_FMT_NV21M   v4l2_fourcc('N', 'M', '2', '1') /* 21  Y/CrCb 4:2:0  */
+#define V4L2_PIX_FMT_NV16M   v4l2_fourcc('N', 'M', '1', '6') /* 16  Y/CbCr 4:2:2  */
+#define V4L2_PIX_FMT_NV61M   v4l2_fourcc('N', 'M', '6', '1') /* 16  Y/CrCb 4:2:2  */
+#define V4L2_PIX_FMT_NV12MT  v4l2_fourcc('T', 'M', '1', '2') /* 12  Y/CbCr 4:2:0 64x32 macroblocks */
+#define V4L2_PIX_FMT_NV12MT_16X16 v4l2_fourcc('V', 'M', '1', '2') /* 12  Y/CbCr 4:2:0 16x16 macroblocks */
+
+/* three non contiguous planes - Y, Cb, Cr */
+#define V4L2_PIX_FMT_YUV420M v4l2_fourcc('Y', 'M', '1', '2') /* 12  YUV420 planar */
+#define V4L2_PIX_FMT_YVU420M v4l2_fourcc('Y', 'M', '2', '1') /* 12  YVU420 planar */
+
+/* Bayer formats - see http://www.siliconimaging.com/RGB%20Bayer.htm */
+#define V4L2_PIX_FMT_SBGGR8  v4l2_fourcc('B', 'A', '8', '1') /*  8  BGBG.. GRGR.. */
+#define V4L2_PIX_FMT_SGBRG8  v4l2_fourcc('G', 'B', 'R', 'G') /*  8  GBGB.. RGRG.. */
+#define V4L2_PIX_FMT_SGRBG8  v4l2_fourcc('G', 'R', 'B', 'G') /*  8  GRGR.. BGBG.. */
+#define V4L2_PIX_FMT_SRGGB8  v4l2_fourcc('R', 'G', 'G', 'B') /*  8  RGRG.. GBGB.. */
+#define V4L2_PIX_FMT_SBGGR10 v4l2_fourcc('B', 'G', '1', '0') /* 10  BGBG.. GRGR.. */
+#define V4L2_PIX_FMT_SGBRG10 v4l2_fourcc('G', 'B', '1', '0') /* 10  GBGB.. RGRG.. */
+#define V4L2_PIX_FMT_SGRBG10 v4l2_fourcc('B', 'A', '1', '0') /* 10  GRGR.. BGBG.. */
+#define V4L2_PIX_FMT_SRGGB10 v4l2_fourcc('R', 'G', '1', '0') /* 10  RGRG.. GBGB.. */
+#define V4L2_PIX_FMT_SBGGR12 v4l2_fourcc('B', 'G', '1', '2') /* 12  BGBG.. GRGR.. */
+#define V4L2_PIX_FMT_SGBRG12 v4l2_fourcc('G', 'B', '1', '2') /* 12  GBGB.. RGRG.. */
+#define V4L2_PIX_FMT_SGRBG12 v4l2_fourcc('B', 'A', '1', '2') /* 12  GRGR.. BGBG.. */
+#define V4L2_PIX_FMT_SRGGB12 v4l2_fourcc('R', 'G', '1', '2') /* 12  RGRG.. GBGB.. */
+	/* 10bit raw bayer a-law compressed to 8 bits */
+#define V4L2_PIX_FMT_SBGGR10ALAW8 v4l2_fourcc('a', 'B', 'A', '8')
+#define V4L2_PIX_FMT_SGBRG10ALAW8 v4l2_fourcc('a', 'G', 'A', '8')
+#define V4L2_PIX_FMT_SGRBG10ALAW8 v4l2_fourcc('a', 'g', 'A', '8')
+#define V4L2_PIX_FMT_SRGGB10ALAW8 v4l2_fourcc('a', 'R', 'A', '8')
+	/* 10bit raw bayer DPCM compressed to 8 bits */
+#define V4L2_PIX_FMT_SBGGR10DPCM8 v4l2_fourcc('b', 'B', 'A', '8')
+#define V4L2_PIX_FMT_SGBRG10DPCM8 v4l2_fourcc('b', 'G', 'A', '8')
+#define V4L2_PIX_FMT_SGRBG10DPCM8 v4l2_fourcc('B', 'D', '1', '0')
+#define V4L2_PIX_FMT_SRGGB10DPCM8 v4l2_fourcc('b', 'R', 'A', '8')
+	/*
+	 * 10bit raw bayer, expanded to 16 bits
+	 * xxxxrrrrrrrrrrxxxxgggggggggg xxxxggggggggggxxxxbbbbbbbbbb...
+	 */
+#define V4L2_PIX_FMT_SBGGR16 v4l2_fourcc('B', 'Y', 'R', '2') /* 16  BGBG.. GRGR.. */
+
+/* compressed formats */
+#define V4L2_PIX_FMT_MJPEG    v4l2_fourcc('M', 'J', 'P', 'G') /* Motion-JPEG   */
+#define V4L2_PIX_FMT_JPEG     v4l2_fourcc('J', 'P', 'E', 'G') /* JFIF JPEG     */
+#define V4L2_PIX_FMT_DV       v4l2_fourcc('d', 'v', 's', 'd') /* 1394          */
+#define V4L2_PIX_FMT_MPEG     v4l2_fourcc('M', 'P', 'E', 'G') /* MPEG-1/2/4 Multiplexed */
+#define V4L2_PIX_FMT_H264     v4l2_fourcc('H', '2', '6', '4') /* H264 with start codes */
+#define V4L2_PIX_FMT_H264_NO_SC v4l2_fourcc('A', 'V', 'C', '1') /* H264 without start codes */
+#define V4L2_PIX_FMT_H264_MVC v4l2_fourcc('M', '2', '6', '4') /* H264 MVC */
+#define V4L2_PIX_FMT_H263     v4l2_fourcc('H', '2', '6', '3') /* H263          */
+#define V4L2_PIX_FMT_MPEG1    v4l2_fourcc('M', 'P', 'G', '1') /* MPEG-1 ES     */
+#define V4L2_PIX_FMT_MPEG2    v4l2_fourcc('M', 'P', 'G', '2') /* MPEG-2 ES     */
+#define V4L2_PIX_FMT_MPEG4    v4l2_fourcc('M', 'P', 'G', '4') /* MPEG-4 part 2 ES */
+#define V4L2_PIX_FMT_XVID     v4l2_fourcc('X', 'V', 'I', 'D') /* Xvid           */
+#define V4L2_PIX_FMT_VC1_ANNEX_G v4l2_fourcc('V', 'C', '1', 'G') /* SMPTE 421M Annex G compliant stream */
+#define V4L2_PIX_FMT_VC1_ANNEX_L v4l2_fourcc('V', 'C', '1', 'L') /* SMPTE 421M Annex L compliant stream */
+#define V4L2_PIX_FMT_VP8      v4l2_fourcc('V', 'P', '8', '0') /* VP8 */
+
+/*  Vendor-specific formats   */
+#define V4L2_PIX_FMT_CPIA1    v4l2_fourcc('C', 'P', 'I', 'A') /* cpia1 YUV */
+#define V4L2_PIX_FMT_WNVA     v4l2_fourcc('W', 'N', 'V', 'A') /* Winnov hw compress */
+#define V4L2_PIX_FMT_SN9C10X  v4l2_fourcc('S', '9', '1', '0') /* SN9C10x compression */
+#define V4L2_PIX_FMT_SN9C20X_I420 v4l2_fourcc('S', '9', '2', '0') /* SN9C20x YUV 4:2:0 */
+#define V4L2_PIX_FMT_PWC1     v4l2_fourcc('P', 'W', 'C', '1') /* pwc older webcam */
+#define V4L2_PIX_FMT_PWC2     v4l2_fourcc('P', 'W', 'C', '2') /* pwc newer webcam */
+#define V4L2_PIX_FMT_ET61X251 v4l2_fourcc('E', '6', '2', '5') /* ET61X251 compression */
+#define V4L2_PIX_FMT_SPCA501  v4l2_fourcc('S', '5', '0', '1') /* YUYV per line */
+#define V4L2_PIX_FMT_SPCA505  v4l2_fourcc('S', '5', '0', '5') /* YYUV per line */
+#define V4L2_PIX_FMT_SPCA508  v4l2_fourcc('S', '5', '0', '8') /* YUVY per line */
+#define V4L2_PIX_FMT_SPCA561  v4l2_fourcc('S', '5', '6', '1') /* compressed GBRG bayer */
+#define V4L2_PIX_FMT_PAC207   v4l2_fourcc('P', '2', '0', '7') /* compressed BGGR bayer */
+#define V4L2_PIX_FMT_MR97310A v4l2_fourcc('M', '3', '1', '0') /* compressed BGGR bayer */
+#define V4L2_PIX_FMT_JL2005BCD v4l2_fourcc('J', 'L', '2', '0') /* compressed RGGB bayer */
+#define V4L2_PIX_FMT_SN9C2028 v4l2_fourcc('S', 'O', 'N', 'X') /* compressed GBRG bayer */
+#define V4L2_PIX_FMT_SQ905C   v4l2_fourcc('9', '0', '5', 'C') /* compressed RGGB bayer */
+#define V4L2_PIX_FMT_PJPG     v4l2_fourcc('P', 'J', 'P', 'G') /* Pixart 73xx JPEG */
+#define V4L2_PIX_FMT_OV511    v4l2_fourcc('O', '5', '1', '1') /* ov511 JPEG */
+#define V4L2_PIX_FMT_OV518    v4l2_fourcc('O', '5', '1', '8') /* ov518 JPEG */
+#define V4L2_PIX_FMT_STV0680  v4l2_fourcc('S', '6', '8', '0') /* stv0680 bayer */
+#define V4L2_PIX_FMT_TM6000   v4l2_fourcc('T', 'M', '6', '0') /* tm5600/tm60x0 */
+#define V4L2_PIX_FMT_CIT_YYVYUY v4l2_fourcc('C', 'I', 'T', 'V') /* one line of Y then 1 line of VYUY */
+#define V4L2_PIX_FMT_KONICA420  v4l2_fourcc('K', 'O', 'N', 'I') /* YUV420 planar in blocks of 256 pixels */
+#define V4L2_PIX_FMT_JPGL	v4l2_fourcc('J', 'P', 'G', 'L') /* JPEG-Lite */
+#define V4L2_PIX_FMT_SE401      v4l2_fourcc('S', '4', '0', '1') /* se401 janggu compressed rgb */
+#define V4L2_PIX_FMT_S5C_UYVY_JPG v4l2_fourcc('S', '5', 'C', 'I') /* S5C73M3 interleaved UYVY/JPEG */
+
+#define fourcc_code(a, b, c, d) ((__u32)(a) | ((__u32)(b) << 8) | \
+				 ((__u32)(c) << 16) | ((__u32)(d) << 24))
+
+#define DRM_FORMAT_BIG_ENDIAN (1<<31) /* format is big endian instead of little endian */
+
+/* color index */
+#define DRM_FORMAT_C8		fourcc_code('C', '8', ' ', ' ') /* [7:0] C */
+
+/* 8 bpp RGB */
+#define DRM_FORMAT_RGB332	fourcc_code('R', 'G', 'B', '8') /* [7:0] R:G:B 3:3:2 */
+#define DRM_FORMAT_BGR233	fourcc_code('B', 'G', 'R', '8') /* [7:0] B:G:R 2:3:3 */
+
+/* 16 bpp RGB */
+#define DRM_FORMAT_XRGB4444	fourcc_code('X', 'R', '1', '2') /* [15:0] x:R:G:B 4:4:4:4 little endian */
+#define DRM_FORMAT_XBGR4444	fourcc_code('X', 'B', '1', '2') /* [15:0] x:B:G:R 4:4:4:4 little endian */
+#define DRM_FORMAT_RGBX4444	fourcc_code('R', 'X', '1', '2') /* [15:0] R:G:B:x 4:4:4:4 little endian */
+#define DRM_FORMAT_BGRX4444	fourcc_code('B', 'X', '1', '2') /* [15:0] B:G:R:x 4:4:4:4 little endian */
+
+#define DRM_FORMAT_ARGB4444	fourcc_code('A', 'R', '1', '2') /* [15:0] A:R:G:B 4:4:4:4 little endian */
+#define DRM_FORMAT_ABGR4444	fourcc_code('A', 'B', '1', '2') /* [15:0] A:B:G:R 4:4:4:4 little endian */
+#define DRM_FORMAT_RGBA4444	fourcc_code('R', 'A', '1', '2') /* [15:0] R:G:B:A 4:4:4:4 little endian */
+#define DRM_FORMAT_BGRA4444	fourcc_code('B', 'A', '1', '2') /* [15:0] B:G:R:A 4:4:4:4 little endian */
+
+#define DRM_FORMAT_XRGB1555	fourcc_code('X', 'R', '1', '5') /* [15:0] x:R:G:B 1:5:5:5 little endian */
+#define DRM_FORMAT_XBGR1555	fourcc_code('X', 'B', '1', '5') /* [15:0] x:B:G:R 1:5:5:5 little endian */
+#define DRM_FORMAT_RGBX5551	fourcc_code('R', 'X', '1', '5') /* [15:0] R:G:B:x 5:5:5:1 little endian */
+#define DRM_FORMAT_BGRX5551	fourcc_code('B', 'X', '1', '5') /* [15:0] B:G:R:x 5:5:5:1 little endian */
+
+#define DRM_FORMAT_ARGB1555	fourcc_code('A', 'R', '1', '5') /* [15:0] A:R:G:B 1:5:5:5 little endian */
+#define DRM_FORMAT_ABGR1555	fourcc_code('A', 'B', '1', '5') /* [15:0] A:B:G:R 1:5:5:5 little endian */
+#define DRM_FORMAT_RGBA5551	fourcc_code('R', 'A', '1', '5') /* [15:0] R:G:B:A 5:5:5:1 little endian */
+#define DRM_FORMAT_BGRA5551	fourcc_code('B', 'A', '1', '5') /* [15:0] B:G:R:A 5:5:5:1 little endian */
+
+#define DRM_FORMAT_RGB565	fourcc_code('R', 'G', '1', '6') /* [15:0] R:G:B 5:6:5 little endian */
+#define DRM_FORMAT_BGR565	fourcc_code('B', 'G', '1', '6') /* [15:0] B:G:R 5:6:5 little endian */
+
+/* 24 bpp RGB */
+#define DRM_FORMAT_RGB888	fourcc_code('R', 'G', '2', '4') /* [23:0] R:G:B little endian */
+#define DRM_FORMAT_BGR888	fourcc_code('B', 'G', '2', '4') /* [23:0] B:G:R little endian */
+
+/* 32 bpp RGB */
+#define DRM_FORMAT_XRGB8888	fourcc_code('X', 'R', '2', '4') /* [31:0] x:R:G:B 8:8:8:8 little endian */
+#define DRM_FORMAT_XBGR8888	fourcc_code('X', 'B', '2', '4') /* [31:0] x:B:G:R 8:8:8:8 little endian */
+#define DRM_FORMAT_RGBX8888	fourcc_code('R', 'X', '2', '4') /* [31:0] R:G:B:x 8:8:8:8 little endian */
+#define DRM_FORMAT_BGRX8888	fourcc_code('B', 'X', '2', '4') /* [31:0] B:G:R:x 8:8:8:8 little endian */
+
+#define DRM_FORMAT_ARGB8888	fourcc_code('A', 'R', '2', '4') /* [31:0] A:R:G:B 8:8:8:8 little endian */
+#define DRM_FORMAT_ABGR8888	fourcc_code('A', 'B', '2', '4') /* [31:0] A:B:G:R 8:8:8:8 little endian */
+#define DRM_FORMAT_RGBA8888	fourcc_code('R', 'A', '2', '4') /* [31:0] R:G:B:A 8:8:8:8 little endian */
+#define DRM_FORMAT_BGRA8888	fourcc_code('B', 'A', '2', '4') /* [31:0] B:G:R:A 8:8:8:8 little endian */
+
+#define DRM_FORMAT_XRGB2101010	fourcc_code('X', 'R', '3', '0') /* [31:0] x:R:G:B 2:10:10:10 little endian */
+#define DRM_FORMAT_XBGR2101010	fourcc_code('X', 'B', '3', '0') /* [31:0] x:B:G:R 2:10:10:10 little endian */
+#define DRM_FORMAT_RGBX1010102	fourcc_code('R', 'X', '3', '0') /* [31:0] R:G:B:x 10:10:10:2 little endian */
+#define DRM_FORMAT_BGRX1010102	fourcc_code('B', 'X', '3', '0') /* [31:0] B:G:R:x 10:10:10:2 little endian */
+
+#define DRM_FORMAT_ARGB2101010	fourcc_code('A', 'R', '3', '0') /* [31:0] A:R:G:B 2:10:10:10 little endian */
+#define DRM_FORMAT_ABGR2101010	fourcc_code('A', 'B', '3', '0') /* [31:0] A:B:G:R 2:10:10:10 little endian */
+#define DRM_FORMAT_RGBA1010102	fourcc_code('R', 'A', '3', '0') /* [31:0] R:G:B:A 10:10:10:2 little endian */
+#define DRM_FORMAT_BGRA1010102	fourcc_code('B', 'A', '3', '0') /* [31:0] B:G:R:A 10:10:10:2 little endian */
+
+/* packed YCbCr */
+#define DRM_FORMAT_YUYV		fourcc_code('Y', 'U', 'Y', 'V') /* [31:0] Cr0:Y1:Cb0:Y0 8:8:8:8 little endian */
+#define DRM_FORMAT_YVYU		fourcc_code('Y', 'V', 'Y', 'U') /* [31:0] Cb0:Y1:Cr0:Y0 8:8:8:8 little endian */
+#define DRM_FORMAT_UYVY		fourcc_code('U', 'Y', 'V', 'Y') /* [31:0] Y1:Cr0:Y0:Cb0 8:8:8:8 little endian */
+#define DRM_FORMAT_VYUY		fourcc_code('V', 'Y', 'U', 'Y') /* [31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little endian */
+
+#define DRM_FORMAT_AYUV		fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */
+
+/*
+ * 2 plane YCbCr
+ * index 0 = Y plane, [7:0] Y
+ * index 1 = Cr:Cb plane, [15:0] Cr:Cb little endian
+ * or
+ * index 1 = Cb:Cr plane, [15:0] Cb:Cr little endian
+ */
+#define DRM_FORMAT_NV12		fourcc_code('N', 'V', '1', '2') /* 2x2 subsampled Cr:Cb plane */
+#define DRM_FORMAT_NV21		fourcc_code('N', 'V', '2', '1') /* 2x2 subsampled Cb:Cr plane */
+#define DRM_FORMAT_NV16		fourcc_code('N', 'V', '1', '6') /* 2x1 subsampled Cr:Cb plane */
+#define DRM_FORMAT_NV61		fourcc_code('N', 'V', '6', '1') /* 2x1 subsampled Cb:Cr plane */
+#define DRM_FORMAT_NV24		fourcc_code('N', 'V', '2', '4') /* non-subsampled Cr:Cb plane */
+#define DRM_FORMAT_NV42		fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */
+
+/* special NV12 tiled format */
+#define DRM_FORMAT_NV12MT	fourcc_code('T', 'M', '1', '2') /* 2x2 subsampled Cr:Cb plane 64x32 macroblocks */
+
+/*
+ * 3 plane YCbCr
+ * index 0: Y plane, [7:0] Y
+ * index 1: Cb plane, [7:0] Cb
+ * index 2: Cr plane, [7:0] Cr
+ * or
+ * index 1: Cr plane, [7:0] Cr
+ * index 2: Cb plane, [7:0] Cb
+ */
+#define DRM_FORMAT_YUV410	fourcc_code('Y', 'U', 'V', '9') /* 4x4 subsampled Cb (1) and Cr (2) planes */
+#define DRM_FORMAT_YVU410	fourcc_code('Y', 'V', 'U', '9') /* 4x4 subsampled Cr (1) and Cb (2) planes */
+#define DRM_FORMAT_YUV411	fourcc_code('Y', 'U', '1', '1') /* 4x1 subsampled Cb (1) and Cr (2) planes */
+#define DRM_FORMAT_YVU411	fourcc_code('Y', 'V', '1', '1') /* 4x1 subsampled Cr (1) and Cb (2) planes */
+#define DRM_FORMAT_YUV420	fourcc_code('Y', 'U', '1', '2') /* 2x2 subsampled Cb (1) and Cr (2) planes */
+#define DRM_FORMAT_YVU420	fourcc_code('Y', 'V', '1', '2') /* 2x2 subsampled Cr (1) and Cb (2) planes */
+#define DRM_FORMAT_YUV422	fourcc_code('Y', 'U', '1', '6') /* 2x1 subsampled Cb (1) and Cr (2) planes */
+#define DRM_FORMAT_YVU422	fourcc_code('Y', 'V', '1', '6') /* 2x1 subsampled Cr (1) and Cb (2) planes */
+#define DRM_FORMAT_YUV444	fourcc_code('Y', 'U', '2', '4') /* non-subsampled Cb (1) and Cr (2) planes */
+#define DRM_FORMAT_YVU444	fourcc_code('Y', 'V', '2', '4') /* non-subsampled Cr (1) and Cb (2) planes */
+
+#endif /* __VIDEO_FOURCC_H */
-- 
1.9.0



From s.hauer at pengutronix.de  Fri Mar 14 10:32:29 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 14 Mar 2014 15:32:29 +0100
Subject: [PATCH 09/29] clk: clk-mux: pass clk flags from initializers
In-Reply-To: <1394807569-23620-1-git-send-email-s.hauer@pengutronix.de>
References: <1394807569-23620-1-git-send-email-s.hauer@pengutronix.de>
Message-ID: <1394807569-23620-10-git-send-email-s.hauer@pengutronix.de>

struct clk has a flags field, let the clk-mux initializers set this
field.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/mach-imx/clk.h        | 2 +-
 drivers/clk/clk-mux.c          | 8 +++++---
 drivers/clk/mxs/clk.h          | 2 +-
 drivers/clk/tegra/clk-periph.c | 2 +-
 include/linux/clk.h            | 6 ++++--
 5 files changed, 12 insertions(+), 8 deletions(-)

diff --git a/arch/arm/mach-imx/clk.h b/arch/arm/mach-imx/clk.h
index 4a7298d..8e218fb 100644
--- a/arch/arm/mach-imx/clk.h
+++ b/arch/arm/mach-imx/clk.h
@@ -16,7 +16,7 @@ static inline struct clk *imx_clk_fixed_factor(const char *name,
 static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg,
 		u8 shift, u8 width, const char **parents, u8 num_parents)
 {
-	return clk_mux(name, reg, shift, width, parents, num_parents);
+	return clk_mux(name, reg, shift, width, parents, num_parents, 0);
 }
 
 static inline struct clk *imx_clk_gate(const char *name, const char *parent,
diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c
index b22bdd1..9dcd39c 100644
--- a/drivers/clk/clk-mux.c
+++ b/drivers/clk/clk-mux.c
@@ -56,7 +56,8 @@ static struct clk_ops clk_mux_ops = {
 };
 
 struct clk *clk_mux_alloc(const char *name, void __iomem *reg,
-		u8 shift, u8 width, const char **parents, u8 num_parents)
+		u8 shift, u8 width, const char **parents, u8 num_parents,
+		unsigned flags)
 {
 	struct clk_mux *m = xzalloc(sizeof(*m));
 
@@ -65,6 +66,7 @@ struct clk *clk_mux_alloc(const char *name, void __iomem *reg,
 	m->width = width;
 	m->clk.ops = &clk_mux_ops;
 	m->clk.name = name;
+	m->clk.flags = flags;
 	m->clk.parent_names = parents;
 	m->clk.num_parents = num_parents;
 
@@ -79,12 +81,12 @@ void clk_mux_free(struct clk *clk_mux)
 }
 
 struct clk *clk_mux(const char *name, void __iomem *reg,
-		u8 shift, u8 width, const char **parents, u8 num_parents)
+		u8 shift, u8 width, const char **parents, u8 num_parents, unsigned flags)
 {
 	struct clk *m;
 	int ret;
 
-	m = clk_mux_alloc(name, reg, shift, width, parents, num_parents);
+	m = clk_mux_alloc(name, reg, shift, width, parents, num_parents, flags);
 
 	ret = clk_register(m);
 	if (ret) {
diff --git a/drivers/clk/mxs/clk.h b/drivers/clk/mxs/clk.h
index b4fcfa0..3db38b4 100644
--- a/drivers/clk/mxs/clk.h
+++ b/drivers/clk/mxs/clk.h
@@ -40,7 +40,7 @@ static inline struct clk *mxs_clk_gate(const char *name,
 static inline struct clk *mxs_clk_mux(const char *name, void __iomem *reg,
 		u8 shift, u8 width, const char **parent_names, int num_parents)
 {
-	return clk_mux(name, reg, shift, width, parent_names, num_parents);
+	return clk_mux(name, reg, shift, width, parent_names, num_parents, 0);
 }
 
 static inline struct clk *mxs_clk_fixed_factor(const char *name,
diff --git a/drivers/clk/tegra/clk-periph.c b/drivers/clk/tegra/clk-periph.c
index e969495..0b9c8dc 100644
--- a/drivers/clk/tegra/clk-periph.c
+++ b/drivers/clk/tegra/clk-periph.c
@@ -140,7 +140,7 @@ struct clk *_tegra_clk_register_periph(const char *name,
 	}
 
 	periph->mux = clk_mux_alloc(NULL, clk_base + reg_offset, 30, 2,
-				    parent_names, num_parents);
+				    parent_names, num_parents, 0);
 	if (!periph->mux)
 		goto out_mux;
 
diff --git a/include/linux/clk.h b/include/linux/clk.h
index af38c72..439e88c 100644
--- a/include/linux/clk.h
+++ b/include/linux/clk.h
@@ -252,10 +252,12 @@ struct clk *clk_fixed_factor(const char *name,
 		const char *parent, unsigned int mult, unsigned int div);
 
 struct clk *clk_mux_alloc(const char *name, void __iomem *reg,
-		u8 shift, u8 width, const char **parents, u8 num_parents);
+		u8 shift, u8 width, const char **parents, u8 num_parents,
+		unsigned flags);
 void clk_mux_free(struct clk *clk_mux);
 struct clk *clk_mux(const char *name, void __iomem *reg,
-		u8 shift, u8 width, const char **parents, u8 num_parents);
+		u8 shift, u8 width, const char **parents, u8 num_parents,
+		unsigned flags);
 
 struct clk *clk_gate_alloc(const char *name, const char *parent,
 		void __iomem *reg, u8 shift);
-- 
1.9.0



From s.hauer at pengutronix.de  Fri Mar 14 10:32:30 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 14 Mar 2014 15:32:30 +0100
Subject: [PATCH 10/29] clk: clk-gate: pass flags to initializers
In-Reply-To: <1394807569-23620-1-git-send-email-s.hauer@pengutronix.de>
References: <1394807569-23620-1-git-send-email-s.hauer@pengutronix.de>
Message-ID: <1394807569-23620-11-git-send-email-s.hauer@pengutronix.de>

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/mach-imx/clk.h        |  2 +-
 drivers/clk/clk-gate.c         | 11 ++++++-----
 drivers/clk/mvebu/common.c     |  2 +-
 drivers/clk/mxs/clk.h          |  2 +-
 drivers/clk/tegra/clk-periph.c |  2 +-
 include/linux/clk.h            |  6 +++---
 6 files changed, 13 insertions(+), 12 deletions(-)

diff --git a/arch/arm/mach-imx/clk.h b/arch/arm/mach-imx/clk.h
index 8e218fb..072af55 100644
--- a/arch/arm/mach-imx/clk.h
+++ b/arch/arm/mach-imx/clk.h
@@ -22,7 +22,7 @@ static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg,
 static inline struct clk *imx_clk_gate(const char *name, const char *parent,
 		void __iomem *reg, u8 shift)
 {
-	return clk_gate(name, parent, reg, shift);
+	return clk_gate(name, parent, reg, shift, 0);
 }
 
 struct clk *imx_clk_pllv1(const char *name, const char *parent,
diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c
index baec855..f356de7 100644
--- a/drivers/clk/clk-gate.c
+++ b/drivers/clk/clk-gate.c
@@ -83,7 +83,7 @@ static struct clk_ops clk_gate_ops = {
 };
 
 struct clk *clk_gate_alloc(const char *name, const char *parent,
-		void __iomem *reg, u8 shift)
+		void __iomem *reg, u8 shift, unsigned flags)
 {
 	struct clk_gate *g = xzalloc(sizeof(*g));
 
@@ -92,6 +92,7 @@ struct clk *clk_gate_alloc(const char *name, const char *parent,
 	g->shift = shift;
 	g->clk.ops = &clk_gate_ops;
 	g->clk.name = name;
+	g->clk.flags = flags;
 	g->clk.parent_names = &g->parent;
 	g->clk.num_parents = 1;
 
@@ -106,12 +107,12 @@ void clk_gate_free(struct clk *clk_gate)
 }
 
 struct clk *clk_gate(const char *name, const char *parent, void __iomem *reg,
-		u8 shift)
+		u8 shift, unsigned flags)
 {
 	struct clk *g;
 	int ret;
 
-	g = clk_gate_alloc(name , parent, reg, shift);
+	g = clk_gate_alloc(name , parent, reg, shift, flags);
 
 	ret = clk_register(g);
 	if (ret) {
@@ -123,12 +124,12 @@ struct clk *clk_gate(const char *name, const char *parent, void __iomem *reg,
 }
 
 struct clk *clk_gate_inverted(const char *name, const char *parent,
-		void __iomem *reg, u8 shift)
+		void __iomem *reg, u8 shift, unsigned flags)
 {
 	struct clk *clk;
 	struct clk_gate *g;
 
-	clk = clk_gate(name, parent, reg, shift);
+	clk = clk_gate(name, parent, reg, shift, flags);
 	if (IS_ERR(clk))
 		return clk;
 
diff --git a/drivers/clk/mvebu/common.c b/drivers/clk/mvebu/common.c
index 37cc156..aa1e8f6 100644
--- a/drivers/clk/mvebu/common.c
+++ b/drivers/clk/mvebu/common.c
@@ -188,7 +188,7 @@ int mvebu_clk_gating_probe(struct device_d *dev)
 			(desc[n].parent) ? desc[n].parent : default_parent;
 		gate->bit_idx = desc[n].bit_idx;
 		gate->clk = clk_gate(desc[n].name, parent,
-				base, desc[n].bit_idx);
+				base, desc[n].bit_idx, 0);
 		WARN_ON(IS_ERR(gate->clk));
 	}
 
diff --git a/drivers/clk/mxs/clk.h b/drivers/clk/mxs/clk.h
index 3db38b4..168fa58 100644
--- a/drivers/clk/mxs/clk.h
+++ b/drivers/clk/mxs/clk.h
@@ -34,7 +34,7 @@ static inline struct clk *mxs_clk_fixed(const char *name, int rate)
 static inline struct clk *mxs_clk_gate(const char *name,
 			const char *parent_name, void __iomem *reg, u8 shift)
 {
-	return clk_gate_inverted(name, parent_name, reg, shift);
+	return clk_gate_inverted(name, parent_name, reg, shift, 0);
 }
 
 static inline struct clk *mxs_clk_mux(const char *name, void __iomem *reg,
diff --git a/drivers/clk/tegra/clk-periph.c b/drivers/clk/tegra/clk-periph.c
index 0b9c8dc..c970f63 100644
--- a/drivers/clk/tegra/clk-periph.c
+++ b/drivers/clk/tegra/clk-periph.c
@@ -145,7 +145,7 @@ struct clk *_tegra_clk_register_periph(const char *name,
 		goto out_mux;
 
 	periph->gate = clk_gate_alloc(NULL, NULL, clk_base + 0x10 +
-				      ((id >> 3) & 0xc), id & 0x1f);
+				      ((id >> 3) & 0xc), id & 0x1f, 0);
 	if (!periph->gate)
 		goto out_gate;
 
diff --git a/include/linux/clk.h b/include/linux/clk.h
index 439e88c..21edfab 100644
--- a/include/linux/clk.h
+++ b/include/linux/clk.h
@@ -260,12 +260,12 @@ struct clk *clk_mux(const char *name, void __iomem *reg,
 		unsigned flags);
 
 struct clk *clk_gate_alloc(const char *name, const char *parent,
-		void __iomem *reg, u8 shift);
+		void __iomem *reg, u8 shift, unsigned flags);
 void clk_gate_free(struct clk *clk_gate);
 struct clk *clk_gate(const char *name, const char *parent, void __iomem *reg,
-		u8 shift);
+		u8 shift, unsigned flags);
 struct clk *clk_gate_inverted(const char *name, const char *parent, void __iomem *reg,
-		u8 shift);
+		u8 shift, unsigned flags);
 int clk_is_enabled(struct clk *clk);
 
 int clk_is_enabled_always(struct clk *clk);
-- 
1.9.0



From s.hauer at pengutronix.de  Fri Mar 14 10:32:20 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 14 Mar 2014 15:32:20 +0100
Subject: i.MX IPUv3 support
Message-ID: <1394807569-23620-1-git-send-email-s.hauer@pengutronix.de>

This series adds i.MX IPUv3 support for barebox. There are several things
to prepare for this since we need clk parent rate changing and several
additional clocks. Currently supported are LVDS and HDMI displays. This
also adds Variscite VAR-SOM-MX6 support on which the IPU support was
tested. I may rework some of the commit messages next week but I wanted
to have this series posted before the weekend.

Sascha


  ARM: MMU: Add some debugging aids and hints (2014-03-14 15:25:11 +0100)

are available in the git repository at:

  git://git.pengutronix.de/git/barebox.git imx-ipu-v3

for you to fetch changes up to f37d7bbaf03a220bd61ceb0e59dbc8b84a27a9dd:

  ARM: update imx_v7_defconfig (2014-03-14 15:25:21 +0100)

----------------------------------------------------------------
Sascha Hauer (29):
      err.h: Add PTR_ERR_OR_ZERO from kernel
      ARM: i.MX6: Add initial variscite VAR-SOM-MX6 CPU support
      ARM: dts: i.MX6: Add IPU aliases
      ARM: dts: i.MX6: Add HDMI nodes
      ARM: dts: i.MX53: Fix IPU register size
      i2c: i.MX: move to earlier initcall
      i2c: implement of_find_i2c_adapter_by_node
      clk: implement clk_round_rate
      clk: clk-mux: pass clk flags from initializers
      clk: clk-gate: pass flags to initializers
      clk: clk-fixed-factor: pass flags to initializers
      clk: clk-divider: pass flags to initializers
      clk: introduce CLK_SET_RATE_PARENT flag
      clk: clk-divider: sync with kernel code
      clk: let clk-divider handle the table based divider aswell
      clk: clk-fixed-factor: add set_rate/round_rate callbacks
      clk: Add parent round/set rate for mux and gate
      ARM: i.MX: introduce clk parent rate changes
      ARM: i.MX6: Add video clocks
      video: introduce struct display_timings
      video: rework mode_name parameter setting
      video: Add display timing from devicetree helper
      video: Add edid support
      ARM i.MX6q: Mark VPU and IPU AXI transfers as cacheable, increase IPU priority
      video: Add kernel fourcc defines
      video: Add i.MX IPUv3 support
      video: i.MX IPUv3: Add lvds bridge support
      video: i.MX IPUv3: Add hdmi support
      ARM: update imx_v7_defconfig

 arch/arm/boards/Makefile                           |    1 +
 arch/arm/boards/variscite-mx6/Makefile             |    3 +
 arch/arm/boards/variscite-mx6/board.c              |  135 ++
 .../variscite-mx6/flash-header-variscite.imxcfg    |   86 ++
 arch/arm/boards/variscite-mx6/lowlevel.c           |   74 ++
 arch/arm/configs/imx_v7_defconfig                  |   26 +-
 arch/arm/dts/Makefile                              |    4 +-
 arch/arm/dts/imx53.dtsi                            |    2 +-
 arch/arm/dts/imx6q-var-custom.dts                  |  149 +++
 arch/arm/dts/imx6q-var-som.dtsi                    |   99 ++
 arch/arm/dts/imx6q.dtsi                            |    5 +
 arch/arm/dts/imx6qdl.dtsi                          |   12 +
 arch/arm/mach-imx/Kconfig                          |    6 +
 arch/arm/mach-imx/clk-imx6.c                       |  155 ++-
 arch/arm/mach-imx/clk.h                            |   22 +-
 arch/arm/mach-imx/imx6.c                           |   19 +
 arch/arm/mach-imx/include/mach/imx6-regs.h         |    3 +
 drivers/clk/Makefile                               |    2 +-
 drivers/clk/clk-divider-table.c                    |  119 --
 drivers/clk/clk-divider.c                          |  234 +++-
 drivers/clk/clk-fixed-factor.c                     |   33 +-
 drivers/clk/clk-gate.c                             |   13 +-
 drivers/clk/clk-mux.c                              |   10 +-
 drivers/clk/clk.c                                  |   30 +
 drivers/clk/mvebu/common.c                         |    4 +-
 drivers/clk/mxs/clk.h                              |    6 +-
 drivers/clk/tegra/clk-periph.c                     |    4 +-
 drivers/i2c/busses/i2c-imx.c                       |    2 +-
 drivers/i2c/i2c.c                                  |   11 +
 drivers/video/Kconfig                              |    8 +
 drivers/video/Makefile                             |    3 +
 drivers/video/atmel_lcdfb_core.c                   |    4 +-
 drivers/video/edid.c                               |  909 ++++++++++++++
 drivers/video/edid.h                               |  138 +++
 drivers/video/fb.c                                 |  113 +-
 drivers/video/imx-ipu-fb.c                         |    4 +-
 drivers/video/imx-ipu-v3/Kconfig                   |   14 +
 drivers/video/imx-ipu-v3/Makefile                  |    5 +
 drivers/video/imx-ipu-v3/imx-hdmi.c                | 1297 ++++++++++++++++++++
 drivers/video/imx-ipu-v3/imx-hdmi.h                | 1032 ++++++++++++++++
 drivers/video/imx-ipu-v3/imx-ipu-v3.h              |  344 ++++++
 drivers/video/imx-ipu-v3/imx-ldb.c                 |  310 +++++
 drivers/video/imx-ipu-v3/ipu-common.c              |  836 +++++++++++++
 drivers/video/imx-ipu-v3/ipu-dc.c                  |  392 ++++++
 drivers/video/imx-ipu-v3/ipu-di.c                  |  762 ++++++++++++
 drivers/video/imx-ipu-v3/ipu-dmfc.c                |  397 ++++++
 drivers/video/imx-ipu-v3/ipu-dp.c                  |  313 +++++
 drivers/video/imx-ipu-v3/ipu-prv.h                 |  204 +++
 drivers/video/imx-ipu-v3/ipufb.c                   |  353 ++++++
 drivers/video/imx-ipu-v3/ipuv3-plane.c             |  239 ++++
 drivers/video/imx-ipu-v3/ipuv3-plane.h             |   51 +
 drivers/video/imx.c                                |    6 +-
 drivers/video/of_display_timing.c                  |  238 ++++
 drivers/video/omap.c                               |    4 +-
 drivers/video/s3c24xx.c                            |    4 +-
 drivers/video/sdl.c                                |    4 +-
 drivers/video/stm.c                                |    4 +-
 images/Makefile.imx                                |    5 +
 include/fb.h                                       |   43 +-
 include/i2c/i2c.h                                  |    1 +
 include/linux/clk.h                                |   31 +-
 include/linux/err.h                                |    8 +
 include/mfd/imx6q-iomuxc-gpr.h                     |   18 +
 include/video/fourcc.h                             |  261 ++++
 64 files changed, 9382 insertions(+), 242 deletions(-)
 create mode 100644 arch/arm/boards/variscite-mx6/Makefile
 create mode 100644 arch/arm/boards/variscite-mx6/board.c
 create mode 100644 arch/arm/boards/variscite-mx6/flash-header-variscite.imxcfg
 create mode 100644 arch/arm/boards/variscite-mx6/lowlevel.c
 create mode 100644 arch/arm/dts/imx6q-var-custom.dts
 create mode 100644 arch/arm/dts/imx6q-var-som.dtsi
 delete mode 100644 drivers/clk/clk-divider-table.c
 create mode 100644 drivers/video/edid.c
 create mode 100644 drivers/video/edid.h
 create mode 100644 drivers/video/imx-ipu-v3/Kconfig
 create mode 100644 drivers/video/imx-ipu-v3/Makefile
 create mode 100644 drivers/video/imx-ipu-v3/imx-hdmi.c
 create mode 100644 drivers/video/imx-ipu-v3/imx-hdmi.h
 create mode 100644 drivers/video/imx-ipu-v3/imx-ipu-v3.h
 create mode 100644 drivers/video/imx-ipu-v3/imx-ldb.c
 create mode 100644 drivers/video/imx-ipu-v3/ipu-common.c
 create mode 100644 drivers/video/imx-ipu-v3/ipu-dc.c
 create mode 100644 drivers/video/imx-ipu-v3/ipu-di.c
 create mode 100644 drivers/video/imx-ipu-v3/ipu-dmfc.c
 create mode 100644 drivers/video/imx-ipu-v3/ipu-dp.c
 create mode 100644 drivers/video/imx-ipu-v3/ipu-prv.h
 create mode 100644 drivers/video/imx-ipu-v3/ipufb.c
 create mode 100644 drivers/video/imx-ipu-v3/ipuv3-plane.c
 create mode 100644 drivers/video/imx-ipu-v3/ipuv3-plane.h
 create mode 100644 drivers/video/of_display_timing.c
 create mode 100644 include/video/fourcc.h


From s.hauer at pengutronix.de  Fri Mar 14 10:32:33 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 14 Mar 2014 15:32:33 +0100
Subject: [PATCH 13/29] clk: introduce CLK_SET_RATE_PARENT flag
In-Reply-To: <1394807569-23620-1-git-send-email-s.hauer@pengutronix.de>
References: <1394807569-23620-1-git-send-email-s.hauer@pengutronix.de>
Message-ID: <1394807569-23620-14-git-send-email-s.hauer@pengutronix.de>

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 include/linux/clk.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/include/linux/clk.h b/include/linux/clk.h
index 7e5010a..2704b0f 100644
--- a/include/linux/clk.h
+++ b/include/linux/clk.h
@@ -196,6 +196,9 @@ static inline int clk_set_rate(struct clk *clk, unsigned long rate)
 #endif
 
 #ifdef CONFIG_COMMON_CLK
+
+#define CLK_SET_RATE_PARENT     (1 << 0) /* propagate rate change up one level */
+
 struct clk_ops {
 	int		(*enable)(struct clk *clk);
 	void		(*disable)(struct clk *clk);
-- 
1.9.0



From s.hauer at pengutronix.de  Fri Mar 14 10:32:38 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 14 Mar 2014 15:32:38 +0100
Subject: [PATCH 18/29] ARM: i.MX: introduce clk parent rate changes
In-Reply-To: <1394807569-23620-1-git-send-email-s.hauer@pengutronix.de>
References: <1394807569-23620-1-git-send-email-s.hauer@pengutronix.de>
Message-ID: <1394807569-23620-19-git-send-email-s.hauer@pengutronix.de>

Let dividers and gates change the parent rates.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/mach-imx/clk-imx6.c |  2 +-
 arch/arm/mach-imx/clk.h      | 14 +++++++++++---
 2 files changed, 12 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-imx/clk-imx6.c b/arch/arm/mach-imx/clk-imx6.c
index 8d78a18..db16bb5 100644
--- a/arch/arm/mach-imx/clk-imx6.c
+++ b/arch/arm/mach-imx/clk-imx6.c
@@ -214,7 +214,7 @@ static int imx6_ccm_probe(struct device_d *dev)
 	clks[sata_ref_100m] = imx_clk_gate("sata_ref_100m", "sata_ref", base + 0xe0, 20);
 	clks[pcie_ref_125m] = imx_clk_gate("pcie_ref_125m", "pcie_ref", base + 0xe0, 19);
 
-	clks[enet_ref] = clk_divider_table("enet_ref", "pll6_enet", base + 0xe0, 0, 2, clk_enet_ref_table, 0);
+	clks[enet_ref] = imx_clk_divider_table("enet_ref", "pll6_enet", base + 0xe0, 0, 2, clk_enet_ref_table);
 
 	/*                                name               parent_name         reg          idx */
 	clks[pll2_pfd0_352m] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus",     base + 0x100, 0);
diff --git a/arch/arm/mach-imx/clk.h b/arch/arm/mach-imx/clk.h
index cdafad1..d83266b 100644
--- a/arch/arm/mach-imx/clk.h
+++ b/arch/arm/mach-imx/clk.h
@@ -4,13 +4,21 @@
 static inline struct clk *imx_clk_divider(const char *name, const char *parent,
 		void __iomem *reg, u8 shift, u8 width)
 {
-	return clk_divider(name, parent, reg, shift, width, 0);
+	return clk_divider(name, parent, reg, shift, width, CLK_SET_RATE_PARENT);
+}
+
+static inline struct clk *imx_clk_divider_table(const char *name,
+		const char *parent, void __iomem *reg, u8 shift, u8 width,
+		const struct clk_div_table *table)
+{
+	return clk_divider_table(name, parent, reg, shift, width, table,
+			CLK_SET_RATE_PARENT);
 }
 
 static inline struct clk *imx_clk_fixed_factor(const char *name,
 		const char *parent, unsigned int mult, unsigned int div)
 {
-	return clk_fixed_factor(name, parent, mult, div, 0);
+	return clk_fixed_factor(name, parent, mult, div, CLK_SET_RATE_PARENT);
 }
 
 static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg,
@@ -22,7 +30,7 @@ static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg,
 static inline struct clk *imx_clk_gate(const char *name, const char *parent,
 		void __iomem *reg, u8 shift)
 {
-	return clk_gate(name, parent, reg, shift, 0);
+	return clk_gate(name, parent, reg, shift, CLK_SET_RATE_PARENT);
 }
 
 struct clk *imx_clk_pllv1(const char *name, const char *parent,
-- 
1.9.0



From s.hauer at pengutronix.de  Fri Mar 14 10:32:44 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 14 Mar 2014 15:32:44 +0100
Subject: [PATCH 24/29] ARM i.MX6q: Mark VPU and IPU AXI transfers as cacheable,
 increase IPU priority
In-Reply-To: <1394807569-23620-1-git-send-email-s.hauer@pengutronix.de>
References: <1394807569-23620-1-git-send-email-s.hauer@pengutronix.de>
Message-ID: <1394807569-23620-25-git-send-email-s.hauer@pengutronix.de>

This is needed so that the IPU framebuffer scanout cannot be
starved by VPU or GPU activity.
Some boards like the SabreLite and SabreSD seem to set this in
the DCD already, but the documented register reset values do not
contain the necessary settings.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/mach-imx/imx6.c       | 19 +++++++++++++++++++
 include/mfd/imx6q-iomuxc-gpr.h | 18 ++++++++++++++++++
 2 files changed, 37 insertions(+)

diff --git a/arch/arm/mach-imx/imx6.c b/arch/arm/mach-imx/imx6.c
index 304b1c0..e14ce90 100644
--- a/arch/arm/mach-imx/imx6.c
+++ b/arch/arm/mach-imx/imx6.c
@@ -15,6 +15,7 @@
 #include <common.h>
 #include <io.h>
 #include <sizes.h>
+#include <mfd/imx6q-iomuxc-gpr.h>
 #include <mach/imx6.h>
 #include <mach/generic.h>
 #include <mach/revision.h>
@@ -28,7 +29,9 @@ void imx6_init_lowlevel(void)
 {
 	void __iomem *aips1 = (void *)MX6_AIPS1_ON_BASE_ADDR;
 	void __iomem *aips2 = (void *)MX6_AIPS2_ON_BASE_ADDR;
+	void __iomem *iomux = (void *)MX6_IOMUXC_BASE_ADDR;
 	int is_imx6q = __imx6_cpu_type() == IMX6_CPUTYPE_IMX6Q;
+	uint32_t val;
 
 	/*
 	 * Set all MPROTx to be non-bufferable, trusted for R/W,
@@ -87,6 +90,22 @@ void imx6_init_lowlevel(void)
 			BM_ANADIG_PFD_528_PFD0_CLKGATE,
 			MX6_ANATOP_BASE_ADDR + HW_ANADIG_PFD_528_CLR);
 
+	val = readl(iomux + IOMUXC_GPR4);
+	val |= IMX6Q_GPR4_VPU_WR_CACHE_SEL | IMX6Q_GPR4_VPU_RD_CACHE_SEL |
+		IMX6Q_GPR4_VPU_P_WR_CACHE_VAL | IMX6Q_GPR4_VPU_P_RD_CACHE_VAL_MASK |
+		IMX6Q_GPR4_IPU_WR_CACHE_CTL | IMX6Q_GPR4_IPU_RD_CACHE_CTL;
+	writel(val, iomux + IOMUXC_GPR4);
+
+	/* Increase IPU read QoS priority */
+	val = readl(iomux + IOMUXC_GPR6);
+	val &= ~(IMX6Q_GPR6_IPU1_ID00_RD_QOS_MASK | IMX6Q_GPR6_IPU1_ID01_RD_QOS_MASK);
+	val |= (0xf << 16) | (0x7 << 20);
+	writel(val, iomux + IOMUXC_GPR6);
+
+	val = readl(iomux + IOMUXC_GPR7);
+	val &= ~(IMX6Q_GPR7_IPU2_ID00_RD_QOS_MASK | IMX6Q_GPR7_IPU2_ID01_RD_QOS_MASK);
+	val |= (0xf << 16) | (0x7 << 20);
+	writel(val, iomux + IOMUXC_GPR7);
 }
 
 int imx6_init(void)
diff --git a/include/mfd/imx6q-iomuxc-gpr.h b/include/mfd/imx6q-iomuxc-gpr.h
index db43d59..59c86dd 100644
--- a/include/mfd/imx6q-iomuxc-gpr.h
+++ b/include/mfd/imx6q-iomuxc-gpr.h
@@ -241,6 +241,24 @@
 
 #define IMX6Q_GPR5_L2_CLK_STOP			BIT(8)
 
+#define IMX6Q_GPR6_IPU1_ID00_WR_QOS_MASK	(0xf << 0)
+#define IMX6Q_GPR6_IPU1_ID01_WR_QOS_MASK	(0xf << 4)
+#define IMX6Q_GPR6_IPU1_ID10_WR_QOS_MASK	(0xf << 8)
+#define IMX6Q_GPR6_IPU1_ID11_WR_QOS_MASK	(0xf << 12)
+#define IMX6Q_GPR6_IPU1_ID00_RD_QOS_MASK	(0xf << 16)
+#define IMX6Q_GPR6_IPU1_ID01_RD_QOS_MASK	(0xf << 20)
+#define IMX6Q_GPR6_IPU1_ID10_RD_QOS_MASK	(0xf << 24)
+#define IMX6Q_GPR6_IPU1_ID11_RD_QOS_MASK	(0xf << 28)
+
+#define IMX6Q_GPR7_IPU2_ID00_WR_QOS_MASK	(0xf << 0)
+#define IMX6Q_GPR7_IPU2_ID01_WR_QOS_MASK	(0xf << 4)
+#define IMX6Q_GPR7_IPU2_ID10_WR_QOS_MASK	(0xf << 8)
+#define IMX6Q_GPR7_IPU2_ID11_WR_QOS_MASK	(0xf << 12)
+#define IMX6Q_GPR7_IPU2_ID00_RD_QOS_MASK	(0xf << 16)
+#define IMX6Q_GPR7_IPU2_ID01_RD_QOS_MASK	(0xf << 20)
+#define IMX6Q_GPR7_IPU2_ID10_RD_QOS_MASK	(0xf << 24)
+#define IMX6Q_GPR7_IPU2_ID11_RD_QOS_MASK	(0xf << 28)
+
 #define IMX6Q_GPR9_TZASC2_BYP			BIT(1)
 #define IMX6Q_GPR9_TZASC1_BYP			BIT(0)
 
-- 
1.9.0



From s.hauer at pengutronix.de  Fri Mar 14 10:32:41 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 14 Mar 2014 15:32:41 +0100
Subject: [PATCH 21/29] video: rework mode_name parameter setting
In-Reply-To: <1394807569-23620-1-git-send-email-s.hauer@pengutronix.de>
References: <1394807569-23620-1-git-send-email-s.hauer@pengutronix.de>
Message-ID: <1394807569-23620-22-git-send-email-s.hauer@pengutronix.de>

We have dev_add_param_enum() now, so use it for the mode_name
setting. Also drop the special case for single mode framebuffers,
just add the mode_name parameter for this case aswell.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 drivers/video/fb.c | 107 ++++++++++++++++++++++++++++++++++++-----------------
 include/fb.h       |   2 +
 2 files changed, 76 insertions(+), 33 deletions(-)

diff --git a/drivers/video/fb.c b/drivers/video/fb.c
index e614d77..d7a3d3c 100644
--- a/drivers/video/fb.c
+++ b/drivers/video/fb.c
@@ -49,34 +49,42 @@ static int fb_enable_set(struct param_d *param, void *priv)
 	return 0;
 }
 
-static int fb_setup_mode(struct device_d *dev, struct param_d *param,
-		const char *val)
+static struct fb_videomode *fb_num_to_mode(struct fb_info *info, int num)
 {
-	struct fb_info *info = dev->priv;
-	struct display_timings *dt;
-	int mode, ret;
+	int num_modes;
+
+	num_modes = info->modes.num_modes;
+
+	if (num >= num_modes)
+		return NULL;
+
+	return &info->modes.modes[num];
+}
+
+static int fb_setup_mode(struct fb_info *info)
+{
+	struct device_d *dev = &info->dev;
+	int ret;
+	struct fb_videomode *mode;
 
 	if (info->enabled != 0)
 		return -EPERM;
 
-	if (!val)
-		return dev_param_set_generic(dev, param, NULL);
-
-	dt = &info->modes;
-	for (mode = 0; mode < dt->num_modes; mode++) {
-		if (!strcmp(dt->modes[mode].name, val))
-			break;
-	}
-	if (mode >= dt->num_modes)
+	mode = fb_num_to_mode(info, info->current_mode);
+	if (!mode)
 		return -EINVAL;
 
-	info->mode = &dt->modes[mode];
+	info->mode = mode;
 
 	info->xres = info->mode->xres;
 	info->yres = info->mode->yres;
 	info->line_length = 0;
 
-	ret = info->fbops->fb_activate_var(info);
+	if (info->fbops->fb_activate_var) {
+		ret = info->fbops->fb_activate_var(info);
+		if (ret)
+			return ret;
+	}
 
 	if (!info->line_length)
 		info->line_length = info->xres * (info->bits_per_pixel >> 3);
@@ -87,13 +95,24 @@ static int fb_setup_mode(struct device_d *dev, struct param_d *param,
 		dev->resource[0].start = (resource_size_t)info->screen_base;
 		info->cdev.size = info->line_length * info->yres;
 		dev->resource[0].end = dev->resource[0].start + info->cdev.size - 1;
-		dev_param_set_generic(dev, param, val);
 	} else
 		info->cdev.size = 0;
 
 	return ret;
 }
 
+static int fb_set_modename(struct param_d *param, void *priv)
+{
+	struct fb_info *info = priv;
+	int ret;
+
+	ret = fb_setup_mode(info);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
 static struct file_operations fb_ops = {
 	.read	= mem_read,
 	.write	= mem_write,
@@ -102,22 +121,27 @@ static struct file_operations fb_ops = {
 	.ioctl	= fb_ioctl,
 };
 
-static void fb_info(struct device_d *dev)
+static void fb_print_mode(struct fb_videomode *mode)
+{
+	printf("%-20s %dx%d@%d\n", mode->name,
+			mode->xres, mode->yres, mode->refresh);
+}
+
+static void fb_print_modes(struct display_timings *modes)
 {
-	struct fb_info *info = dev->priv;
 	int i;
 
-	if (!info->modes.num_modes)
-		return;
+	for (i = 0; i < modes->num_modes; i++)
+		fb_print_mode(&modes->modes[i]);
+}
+
+static void fb_info(struct device_d *dev)
+{
+	struct fb_info *info = dev->priv;
 
 	printf("available modes:\n");
 
-	for (i = 0; i < info->modes.num_modes; i++) {
-		struct fb_videomode *mode = &info->modes.modes[i];
-
-		printf("%-10s %dx%d@%d\n", mode->name,
-				mode->xres, mode->yres, mode->refresh);
-	}
+	fb_print_modes(&info->modes);
 
 	printf("\n");
 }
@@ -126,10 +150,20 @@ int register_framebuffer(struct fb_info *info)
 {
 	int id = get_free_deviceid("fb");
 	struct device_d *dev;
-	int ret;
+	int ret, num_modes, i;
+	const char **names;
 
 	dev = &info->dev;
 
+	/*
+	 * If info->mode is set at this point it's the only mode
+	 * the fb supports. move it over to the modes list.
+	 */
+	if (info->mode) {
+		info->modes.modes = info->mode;
+		info->modes.num_modes = 1;
+	}
+
 	if (!info->line_length)
 		info->line_length = info->xres * (info->bits_per_pixel >> 3);
 
@@ -157,11 +191,18 @@ int register_framebuffer(struct fb_info *info)
 	dev_add_param_bool(dev, "enable", fb_enable_set, NULL,
 			&info->p_enable, info);
 
-	if (info->modes.num_modes &&
-			(info->fbops->fb_activate_var != NULL)) {
-		dev_add_param(dev, "mode_name", fb_setup_mode, NULL, 0);
-		dev_set_param(dev, "mode_name", info->modes.modes[0].name);
-	}
+	num_modes = info->modes.num_modes;
+
+	names = xzalloc(sizeof(char *) * num_modes);
+
+	for (i = 0; i < info->modes.num_modes; i++)
+		names[i] = info->modes.modes[i].name;
+
+	dev_add_param_enum(dev, "mode_name", fb_set_modename, NULL, &info->current_mode, names, num_modes, info);
+
+	info->mode = fb_num_to_mode(info, 0);
+
+	fb_setup_mode(info);
 
 	ret = devfs_create(&info->cdev);
 	if (ret)
diff --git a/include/fb.h b/include/fb.h
index 1cc352b..91d3fe4 100644
--- a/include/fb.h
+++ b/include/fb.h
@@ -94,6 +94,8 @@ struct fb_info {
 	struct fb_videomode *mode;
 	struct display_timings modes;
 
+	int current_mode;
+
 	struct fb_ops *fbops;
 	struct device_d dev;		/* This is this fb device */
 
-- 
1.9.0



From s.hauer at pengutronix.de  Fri Mar 14 10:32:37 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 14 Mar 2014 15:32:37 +0100
Subject: [PATCH 17/29] clk: Add parent round/set rate for mux and gate
In-Reply-To: <1394807569-23620-1-git-send-email-s.hauer@pengutronix.de>
References: <1394807569-23620-1-git-send-email-s.hauer@pengutronix.de>
Message-ID: <1394807569-23620-18-git-send-email-s.hauer@pengutronix.de>

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 drivers/clk/clk-gate.c |  2 ++
 drivers/clk/clk-mux.c  |  2 ++
 drivers/clk/clk.c      | 20 ++++++++++++++++++++
 include/linux/clk.h    |  4 ++++
 4 files changed, 28 insertions(+)

diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c
index f356de7..b298b19 100644
--- a/drivers/clk/clk-gate.c
+++ b/drivers/clk/clk-gate.c
@@ -77,6 +77,8 @@ static int clk_gate_is_enabled(struct clk *clk)
 }
 
 static struct clk_ops clk_gate_ops = {
+	.set_rate = clk_parent_set_rate,
+	.round_rate = clk_parent_round_rate,
 	.enable = clk_gate_enable,
 	.disable = clk_gate_disable,
 	.is_enabled = clk_gate_is_enabled,
diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c
index 9dcd39c..4ce86f4 100644
--- a/drivers/clk/clk-mux.c
+++ b/drivers/clk/clk-mux.c
@@ -51,6 +51,8 @@ static int clk_mux_set_parent(struct clk *clk, u8 idx)
 }
 
 static struct clk_ops clk_mux_ops = {
+	.set_rate = clk_parent_set_rate,
+	.round_rate = clk_parent_round_rate,
 	.get_parent = clk_mux_get_parent,
 	.set_parent = clk_mux_set_parent,
 };
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index c67b2f4..0d25941 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -259,11 +259,31 @@ int clk_is_enabled(struct clk *clk)
 	return clk_is_enabled(clk);
 }
 
+/*
+ * Generic struct clk_ops callbacks
+ */
 int clk_is_enabled_always(struct clk *clk)
 {
 	return 1;
 }
 
+long clk_parent_round_rate(struct clk *clk, unsigned long rate,
+				unsigned long *prate)
+{
+	if (!(clk->flags & CLK_SET_RATE_PARENT))
+		return *prate;
+
+	return clk_round_rate(clk_get_parent(clk), rate);
+}
+
+int clk_parent_set_rate(struct clk *clk, unsigned long rate,
+				unsigned long parent_rate)
+{
+	if (!(clk->flags & CLK_SET_RATE_PARENT))
+		return 0;
+	return clk_set_rate(clk_get_parent(clk), rate);
+}
+
 #if defined(CONFIG_OFTREE) && defined(CONFIG_COMMON_CLK_OF_PROVIDER)
 /**
  * struct of_clk_provider - Clock provider registration structure
diff --git a/include/linux/clk.h b/include/linux/clk.h
index 71b0466..07b27cf 100644
--- a/include/linux/clk.h
+++ b/include/linux/clk.h
@@ -276,6 +276,10 @@ struct clk *clk_gate_inverted(const char *name, const char *parent, void __iomem
 int clk_is_enabled(struct clk *clk);
 
 int clk_is_enabled_always(struct clk *clk);
+long clk_parent_round_rate(struct clk *clk, unsigned long rate,
+				unsigned long *prate);
+int clk_parent_set_rate(struct clk *clk, unsigned long rate,
+				unsigned long parent_rate);
 
 int clk_register(struct clk *clk);
 
-- 
1.9.0



From s.hauer at pengutronix.de  Fri Mar 14 10:32:43 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 14 Mar 2014 15:32:43 +0100
Subject: [PATCH 23/29] video: Add edid support
In-Reply-To: <1394807569-23620-1-git-send-email-s.hauer@pengutronix.de>
References: <1394807569-23620-1-git-send-email-s.hauer@pengutronix.de>
Message-ID: <1394807569-23620-24-git-send-email-s.hauer@pengutronix.de>

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 drivers/video/Kconfig  |   6 +
 drivers/video/Makefile |   1 +
 drivers/video/edid.c   | 909 +++++++++++++++++++++++++++++++++++++++++++++++++
 drivers/video/edid.h   | 138 ++++++++
 drivers/video/fb.c     |  14 +-
 include/fb.h           |  11 +-
 6 files changed, 1075 insertions(+), 4 deletions(-)
 create mode 100644 drivers/video/edid.c
 create mode 100644 drivers/video/edid.h

diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 5539266..2bab957 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -84,4 +84,10 @@ config DRIVER_VIDEO_SIMPLEFB
 	  Add support for setting up the kernel's simple framebuffer driver
 	  based on the active barebox framebuffer.
 
+config DRIVER_VIDEO_EDID
+	bool "Add EDID support"
+	help
+	  This enabled support for reading and parsing EDID data from an attached
+	  monitor.
+
 endif
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index d36d83d..a332848 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -1,4 +1,5 @@
 obj-$(CONFIG_VIDEO) += fb.o
+obj-$(CONFIG_DRIVER_VIDEO_EDID) += edid.o
 obj-$(CONFIG_OFDEVICE) += of_display_timing.o
 
 obj-$(CONFIG_DRIVER_VIDEO_ATMEL) += atmel_lcdfb.o atmel_lcdfb_core.o
diff --git a/drivers/video/edid.c b/drivers/video/edid.c
new file mode 100644
index 0000000..828c361
--- /dev/null
+++ b/drivers/video/edid.c
@@ -0,0 +1,909 @@
+/*
+ * drivers/video/edid.c
+ *
+ * Copyright (C) 2002 James Simmons <jsimmons at users.sf.net>
+ *
+ * Credits:
+ *
+ * The EDID Parser is a conglomeration from the following sources:
+ *
+ *   1. SciTech SNAP Graphics Architecture
+ *      Copyright (C) 1991-2002 SciTech Software, Inc. All rights reserved.
+ *
+ *   2. XFree86 4.3.0, interpret_edid.c
+ *      Copyright 1998 by Egbert Eich <Egbert.Eich at Physik.TU-Darmstadt.DE>
+ *
+ *   3. John Fremlin <vii at users.sourceforge.net> and
+ *      Ani Joshi <ajoshi at unixbox.com>
+ *
+ * Generalized Timing Formula is derived from:
+ *
+ *      GTF Spreadsheet by Andy Morrish (1/5/97)
+ *      available at http://www.vesa.org
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file COPYING in the main directory of this archive
+ * for more details.
+ *
+ */
+
+#define pr_fmt(fmt)  "EDID: " fmt
+
+#include <common.h>
+#include <fb.h>
+#include <malloc.h>
+#include <i2c/i2c.h>
+
+#include "edid.h"
+
+#define FBMON_FIX_HEADER  1
+#define FBMON_FIX_INPUT   2
+#define FBMON_FIX_TIMINGS 3
+
+struct broken_edid {
+	u8  manufacturer[4];
+	u32 model;
+	u32 fix;
+};
+
+static const unsigned char edid_v1_header[] = { 0x00, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0x00
+};
+
+static int edid_is_serial_block(unsigned char *block)
+{
+	if ((block[0] == 0x00) && (block[1] == 0x00) &&
+	    (block[2] == 0x00) && (block[3] == 0xff) &&
+	    (block[4] == 0x00))
+		return 1;
+	else
+		return 0;
+}
+
+static int edid_is_ascii_block(unsigned char *block)
+{
+	if ((block[0] == 0x00) && (block[1] == 0x00) &&
+	    (block[2] == 0x00) && (block[3] == 0xfe) &&
+	    (block[4] == 0x00))
+		return 1;
+	else
+		return 0;
+}
+
+static int edid_is_limits_block(unsigned char *block)
+{
+	if ((block[0] == 0x00) && (block[1] == 0x00) &&
+	    (block[2] == 0x00) && (block[3] == 0xfd) &&
+	    (block[4] == 0x00))
+		return 1;
+	else
+		return 0;
+}
+
+static int edid_is_monitor_block(unsigned char *block)
+{
+	if ((block[0] == 0x00) && (block[1] == 0x00) &&
+	    (block[2] == 0x00) && (block[3] == 0xfc) &&
+	    (block[4] == 0x00))
+		return 1;
+	else
+		return 0;
+}
+
+static int edid_is_timing_block(unsigned char *block)
+{
+	if ((block[0] != 0x00) || (block[1] != 0x00) ||
+	    (block[2] != 0x00) || (block[4] != 0x00))
+		return 1;
+	else
+		return 0;
+}
+
+static int check_edid(unsigned char *edid)
+{
+	unsigned char *block = edid + ID_MANUFACTURER_NAME, manufacturer[4];
+	unsigned char *b;
+	u32 model;
+	int i, fix = 0, ret = 0;
+
+	manufacturer[0] = ((block[0] & 0x7c) >> 2) + '@';
+	manufacturer[1] = ((block[0] & 0x03) << 3) +
+		((block[1] & 0xe0) >> 5) + '@';
+	manufacturer[2] = (block[1] & 0x1f) + '@';
+	manufacturer[3] = 0;
+	model = block[2] + (block[3] << 8);
+
+	switch (fix) {
+	case FBMON_FIX_HEADER:
+		for (i = 0; i < 8; i++) {
+			if (edid[i] != edid_v1_header[i]) {
+				ret = fix;
+				break;
+			}
+		}
+		break;
+	case FBMON_FIX_INPUT:
+		b = edid + EDID_STRUCT_DISPLAY;
+		/* Only if display is GTF capable will
+		   the input type be reset to analog */
+		if (b[4] & 0x01 && b[0] & 0x80)
+			ret = fix;
+		break;
+	case FBMON_FIX_TIMINGS:
+		b = edid + DETAILED_TIMING_DESCRIPTIONS_START;
+		ret = fix;
+
+		for (i = 0; i < 4; i++) {
+			if (edid_is_limits_block(b)) {
+				ret = 0;
+				break;
+			}
+
+			b += DETAILED_TIMING_DESCRIPTION_SIZE;
+		}
+
+		break;
+	}
+
+	if (ret)
+		printk("fbmon: The EDID Block of "
+		       "Manufacturer: %s Model: 0x%x is known to "
+		       "be broken,\n",  manufacturer, model);
+
+	return ret;
+}
+
+static void fix_edid(unsigned char *edid, int fix)
+{
+	int i;
+	unsigned char *b, csum = 0;
+
+	switch (fix) {
+	case FBMON_FIX_HEADER:
+		printk("fbmon: trying a header reconstruct\n");
+		memcpy(edid, edid_v1_header, 8);
+		break;
+	case FBMON_FIX_INPUT:
+		printk("fbmon: trying to fix input type\n");
+		b = edid + EDID_STRUCT_DISPLAY;
+		b[0] &= ~0x80;
+		edid[127] += 0x80;
+		break;
+	case FBMON_FIX_TIMINGS:
+		printk("fbmon: trying to fix monitor timings\n");
+		b = edid + DETAILED_TIMING_DESCRIPTIONS_START;
+		for (i = 0; i < 4; i++) {
+			if (!(edid_is_serial_block(b) ||
+			      edid_is_ascii_block(b) ||
+			      edid_is_monitor_block(b) ||
+			      edid_is_timing_block(b))) {
+				b[0] = 0x00;
+				b[1] = 0x00;
+				b[2] = 0x00;
+				b[3] = 0xfd;
+				b[4] = 0x00;
+				b[5] = 60;   /* vfmin */
+				b[6] = 60;   /* vfmax */
+				b[7] = 30;   /* hfmin */
+				b[8] = 75;   /* hfmax */
+				b[9] = 17;   /* pixclock - 170 MHz*/
+				b[10] = 0;   /* GTF */
+				break;
+			}
+
+			b += DETAILED_TIMING_DESCRIPTION_SIZE;
+		}
+
+		for (i = 0; i < EDID_LENGTH - 1; i++)
+			csum += edid[i];
+
+		edid[127] = 256 - csum;
+		break;
+	}
+}
+
+static int edid_checksum(unsigned char *edid)
+{
+	unsigned char csum = 0, all_null = 0;
+	int i, err = 0, fix = check_edid(edid);
+
+	if (fix)
+		fix_edid(edid, fix);
+
+	for (i = 0; i < EDID_LENGTH; i++) {
+		csum += edid[i];
+		all_null |= edid[i];
+	}
+
+	if (csum == 0x00 && all_null) {
+		/* checksum passed, everything's good */
+		err = 1;
+	}
+
+	return err;
+}
+
+static int edid_check_header(unsigned char *edid)
+{
+	int i, err = 1, fix = check_edid(edid);
+
+	if (fix)
+		fix_edid(edid, fix);
+
+	for (i = 0; i < 8; i++) {
+		if (edid[i] != edid_v1_header[i])
+			err = 0;
+	}
+
+	return err;
+}
+
+/*
+ * VESA Generalized Timing Formula (GTF)
+ */
+
+#define FLYBACK                     550
+#define V_FRONTPORCH                1
+#define H_OFFSET                    40
+#define H_SCALEFACTOR               20
+#define H_BLANKSCALE                128
+#define H_GRADIENT                  600
+#define C_VAL                       30
+#define M_VAL                       300
+
+struct __fb_timings {
+	u32 dclk;
+	u32 hfreq;
+	u32 vfreq;
+	u32 hactive;
+	u32 vactive;
+	u32 hblank;
+	u32 vblank;
+	u32 htotal;
+	u32 vtotal;
+};
+
+/**
+ * fb_get_vblank - get vertical blank time
+ * @hfreq: horizontal freq
+ *
+ * DESCRIPTION:
+ * vblank = right_margin + vsync_len + left_margin
+ *
+ *    given: right_margin = 1 (V_FRONTPORCH)
+ *           vsync_len    = 3
+ *           flyback      = 550
+ *
+ *                          flyback * hfreq
+ *           left_margin  = --------------- - vsync_len
+ *                           1000000
+ */
+static u32 fb_get_vblank(u32 hfreq)
+{
+	u32 vblank;
+
+	vblank = (hfreq * FLYBACK)/1000;
+	vblank = (vblank + 500)/1000;
+	return (vblank + V_FRONTPORCH);
+}
+
+/**
+ * fb_get_hblank_by_freq - get horizontal blank time given hfreq
+ * @hfreq: horizontal freq
+ * @xres: horizontal resolution in pixels
+ *
+ * DESCRIPTION:
+ *
+ *           xres * duty_cycle
+ * hblank = ------------------
+ *           100 - duty_cycle
+ *
+ * duty cycle = percent of htotal assigned to inactive display
+ * duty cycle = C - (M/Hfreq)
+ *
+ * where: C = ((offset - scale factor) * blank_scale)
+ *            -------------------------------------- + scale factor
+ *                        256
+ *        M = blank_scale * gradient
+ *
+ */
+static u32 fb_get_hblank_by_hfreq(u32 hfreq, u32 xres)
+{
+	u32 c_val, m_val, duty_cycle, hblank;
+
+	c_val = (((H_OFFSET - H_SCALEFACTOR) * H_BLANKSCALE)/256 +
+		 H_SCALEFACTOR) * 1000;
+	m_val = (H_BLANKSCALE * H_GRADIENT)/256;
+	m_val = (m_val * 1000000)/hfreq;
+	duty_cycle = c_val - m_val;
+	hblank = (xres * duty_cycle)/(100000 - duty_cycle);
+	return (hblank);
+}
+
+/**
+ * int_sqrt - rough approximation to sqrt
+ * @x: integer of which to calculate the sqrt
+ *
+ * A very rough approximation to the sqrt() function.
+ */
+unsigned long int_sqrt(unsigned long x)
+{
+	unsigned long b, m, y = 0;
+
+	if (x <= 1)
+		return x;
+
+	m = 1UL << (BITS_PER_LONG - 2);
+	while (m != 0) {
+		b = y + m;
+		y >>= 1;
+
+		if (x >= b) {
+			x -= b;
+			y += m;
+		}
+		m >>= 2;
+	}
+
+	return y;
+}
+EXPORT_SYMBOL(int_sqrt);
+
+/**
+ * fb_get_hfreq - estimate hsync
+ * @vfreq: vertical refresh rate
+ * @yres: vertical resolution
+ *
+ * DESCRIPTION:
+ *
+ *          (yres + front_port) * vfreq * 1000000
+ * hfreq = -------------------------------------
+ *          (1000000 - (vfreq * FLYBACK)
+ *
+ */
+
+static u32 fb_get_hfreq(u32 vfreq, u32 yres)
+{
+	u32 divisor, hfreq;
+
+	divisor = (1000000 - (vfreq * FLYBACK))/1000;
+	hfreq = (yres + V_FRONTPORCH) * vfreq  * 1000;
+	return (hfreq/divisor);
+}
+
+static void fb_timings_vfreq(struct __fb_timings *timings)
+{
+	timings->hfreq = fb_get_hfreq(timings->vfreq, timings->vactive);
+	timings->vblank = fb_get_vblank(timings->hfreq);
+	timings->vtotal = timings->vactive + timings->vblank;
+	timings->hblank = fb_get_hblank_by_hfreq(timings->hfreq,
+						 timings->hactive);
+	timings->htotal = timings->hactive + timings->hblank;
+	timings->dclk = timings->htotal * timings->hfreq;
+}
+
+/*
+ * fb_get_mode - calculates video mode using VESA GTF
+ * @flags: if: 0 - maximize vertical refresh rate
+ *             1 - vrefresh-driven calculation;
+ *             2 - hscan-driven calculation;
+ *             3 - pixelclock-driven calculation;
+ * @val: depending on @flags, ignored, vrefresh, hsync or pixelclock
+ * @var: pointer to fb_var_screeninfo
+ * @info: pointer to fb_info
+ *
+ * DESCRIPTION:
+ * Calculates video mode based on monitor specs using VESA GTF.
+ * The GTF is best for VESA GTF compliant monitors but is
+ * specifically formulated to work for older monitors as well.
+ *
+ * If @flag==0, the function will attempt to maximize the
+ * refresh rate.  Otherwise, it will calculate timings based on
+ * the flag and accompanying value.
+ *
+ * If FB_IGNOREMON bit is set in @flags, monitor specs will be
+ * ignored and @var will be filled with the calculated timings.
+ *
+ * All calculations are based on the VESA GTF Spreadsheet
+ * available at VESA's public ftp (http://www.vesa.org).
+ *
+ * NOTES:
+ * The timings generated by the GTF will be different from VESA
+ * DMT.  It might be a good idea to keep a table of standard
+ * VESA modes as well.  The GTF may also not work for some displays,
+ * such as, and especially, analog TV.
+ *
+ * REQUIRES:
+ * A valid info->monspecs, otherwise 'safe numbers' will be used.
+ */
+int fb_get_mode(int flags, u32 val, struct fb_videomode *var)
+{
+	struct __fb_timings *timings;
+	u32 interlace = 1, dscan = 1;
+	u32 hfmin, hfmax, vfmin, vfmax, dclkmin, dclkmax, err = 0;
+
+	timings = xzalloc(sizeof(struct __fb_timings));
+
+	/*
+	 * If monspecs are invalid, use values that are enough
+	 * for 640x480 at 60
+	 */
+	hfmin = 29000; hfmax = 30000;
+	vfmin = 60; vfmax = 60;
+	dclkmin = 0; dclkmax = 25000000;
+
+	timings->hactive = var->xres;
+	timings->vactive = var->yres;
+	if (var->vmode & FB_VMODE_INTERLACED) {
+		timings->vactive /= 2;
+		interlace = 2;
+	}
+	if (var->vmode & FB_VMODE_DOUBLE) {
+		timings->vactive *= 2;
+		dscan = 2;
+	}
+
+	/* vrefresh driven */
+	timings->vfreq = val;
+	fb_timings_vfreq(timings);
+
+	if (timings->dclk)
+		var->pixclock = KHZ2PICOS(timings->dclk / 1000);
+	var->hsync_len = (timings->htotal * 8) / 100;
+	var->right_margin = (timings->hblank / 2) - var->hsync_len;
+	var->left_margin = timings->hblank - var->right_margin -
+		var->hsync_len;
+	var->vsync_len = (3 * interlace) / dscan;
+	var->lower_margin = (1 * interlace) / dscan;
+	var->upper_margin = (timings->vblank * interlace) / dscan -
+		(var->vsync_len + var->lower_margin);
+
+	free(timings);
+	return err;
+}
+
+static void calc_mode_timings(int xres, int yres, int refresh,
+			      struct fb_videomode *mode)
+{
+	mode->xres = xres;
+	mode->yres = yres;
+	mode->refresh = refresh;
+	fb_get_mode(0, refresh, mode);
+	mode->name = asprintf("%dx%d@%d-calc", mode->xres, mode->yres, mode->refresh);
+	pr_debug("      %s\n", mode->name);
+}
+
+const struct fb_videomode vesa_modes[] = {
+	/* 0 640x350-85 VESA */
+	{ NULL, 85, 640, 350, 31746,  96, 32, 60, 32, 64, 3,
+	  FB_SYNC_HOR_HIGH_ACT, FB_VMODE_NONINTERLACED, 0},
+	/* 1 640x400-85 VESA */
+	{ NULL, 85, 640, 400, 31746,  96, 32, 41, 01, 64, 3,
+	  FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED, 0 },
+	/* 2 720x400-85 VESA */
+	{ NULL, 85, 721, 400, 28169, 108, 36, 42, 01, 72, 3,
+	  FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED, 0 },
+	/* 3 640x480-60 VESA */
+	{ NULL, 60, 640, 480, 39682,  48, 16, 33, 10, 96, 2,
+	  0, FB_VMODE_NONINTERLACED, 0 },
+	/* 4 640x480-72 VESA */
+	{ NULL, 72, 640, 480, 31746, 128, 24, 29, 9, 40, 2,
+	  0, FB_VMODE_NONINTERLACED, 0 },
+	/* 5 640x480-75 VESA */
+	{ NULL, 75, 640, 480, 31746, 120, 16, 16, 01, 64, 3,
+	  0, FB_VMODE_NONINTERLACED, 0 },
+	/* 6 640x480-85 VESA */
+	{ NULL, 85, 640, 480, 27777, 80, 56, 25, 01, 56, 3,
+	  0, FB_VMODE_NONINTERLACED, 0 },
+	/* 7 800x600-56 VESA */
+	{ NULL, 56, 800, 600, 27777, 128, 24, 22, 01, 72, 2,
+	  FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+	  FB_VMODE_NONINTERLACED, 0 },
+	/* 8 800x600-60 VESA */
+	{ NULL, 60, 800, 600, 25000, 88, 40, 23, 01, 128, 4,
+	  FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+	  FB_VMODE_NONINTERLACED, 0 },
+	/* 9 800x600-72 VESA */
+	{ NULL, 72, 800, 600, 20000, 64, 56, 23, 37, 120, 6,
+	  FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+	  FB_VMODE_NONINTERLACED, 0 },
+	/* 10 800x600-75 VESA */
+	{ NULL, 75, 800, 600, 20202, 160, 16, 21, 01, 80, 3,
+	  FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+	  FB_VMODE_NONINTERLACED, 0 },
+	/* 11 800x600-85 VESA */
+	{ NULL, 85, 800, 600, 17761, 152, 32, 27, 01, 64, 3,
+	  FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+	  FB_VMODE_NONINTERLACED, 0 },
+        /* 12 1024x768i-43 VESA */
+	{ NULL, 43, 1024, 768, 22271, 56, 8, 41, 0, 176, 8,
+	  FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+	  FB_VMODE_INTERLACED, 0 },
+	/* 13 1024x768-60 VESA */
+	{ NULL, 60, 1024, 768, 15384, 160, 24, 29, 3, 136, 6,
+	  0, FB_VMODE_NONINTERLACED, 0 },
+	/* 14 1024x768-70 VESA */
+	{ NULL, 70, 1024, 768, 13333, 144, 24, 29, 3, 136, 6,
+	  0, FB_VMODE_NONINTERLACED, 0 },
+	/* 15 1024x768-75 VESA */
+	{ NULL, 75, 1024, 768, 12690, 176, 16, 28, 1, 96, 3,
+	  FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+	  FB_VMODE_NONINTERLACED, 0 },
+	/* 16 1024x768-85 VESA */
+	{ NULL, 85, 1024, 768, 10582, 208, 48, 36, 1, 96, 3,
+	  FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+	  FB_VMODE_NONINTERLACED, 0 },
+	/* 17 1152x864-75 VESA */
+	{ NULL, 75, 1152, 864, 9259, 256, 64, 32, 1, 128, 3,
+	  FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+	  FB_VMODE_NONINTERLACED, 0 },
+	/* 18 1280x960-60 VESA */
+	{ NULL, 60, 1280, 960, 9259, 312, 96, 36, 1, 112, 3,
+	  FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+	  FB_VMODE_NONINTERLACED, 0 },
+	/* 19 1280x960-85 VESA */
+	{ NULL, 85, 1280, 960, 6734, 224, 64, 47, 1, 160, 3,
+	  FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+	  FB_VMODE_NONINTERLACED, 0 },
+	/* 20 1280x1024-60 VESA */
+	{ NULL, 60, 1280, 1024, 9259, 248, 48, 38, 1, 112, 3,
+	  FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+	  FB_VMODE_NONINTERLACED, 0 },
+	/* 21 1280x1024-75 VESA */
+	{ NULL, 75, 1280, 1024, 7407, 248, 16, 38, 1, 144, 3,
+	  FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+	  FB_VMODE_NONINTERLACED, 0 },
+	/* 22 1280x1024-85 VESA */
+	{ NULL, 85, 1280, 1024, 6349, 224, 64, 44, 1, 160, 3,
+	  FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+	  FB_VMODE_NONINTERLACED, 0 },
+	/* 23 1600x1200-60 VESA */
+	{ NULL, 60, 1600, 1200, 6172, 304, 64, 46, 1, 192, 3,
+	  FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+	  FB_VMODE_NONINTERLACED, 0 },
+	/* 24 1600x1200-65 VESA */
+	{ NULL, 65, 1600, 1200, 5698, 304,  64, 46, 1, 192, 3,
+	  FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+	  FB_VMODE_NONINTERLACED, 0 },
+	/* 25 1600x1200-70 VESA */
+	{ NULL, 70, 1600, 1200, 5291, 304, 64, 46, 1, 192, 3,
+	  FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+	  FB_VMODE_NONINTERLACED, 0 },
+	/* 26 1600x1200-75 VESA */
+	{ NULL, 75, 1600, 1200, 4938, 304, 64, 46, 1, 192, 3,
+	  FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+	  FB_VMODE_NONINTERLACED, 0 },
+	/* 27 1600x1200-85 VESA */
+	{ NULL, 85, 1600, 1200, 4357, 304, 64, 46, 1, 192, 3,
+	  FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+	  FB_VMODE_NONINTERLACED, 0 },
+	/* 28 1792x1344-60 VESA */
+	{ NULL, 60, 1792, 1344, 4882, 328, 128, 46, 1, 200, 3,
+	  FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED, 0 },
+	/* 29 1792x1344-75 VESA */
+	{ NULL, 75, 1792, 1344, 3831, 352, 96, 69, 1, 216, 3,
+	  FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED, 0 },
+	/* 30 1856x1392-60 VESA */
+	{ NULL, 60, 1856, 1392, 4580, 352, 96, 43, 1, 224, 3,
+	  FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED, 0 },
+	/* 31 1856x1392-75 VESA */
+	{ NULL, 75, 1856, 1392, 3472, 352, 128, 104, 1, 224, 3,
+	  FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED, 0 },
+	/* 32 1920x1440-60 VESA */
+	{ NULL, 60, 1920, 1440, 4273, 344, 128, 56, 1, 200, 3,
+	  FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED, 0 },
+	/* 33 1920x1440-75 VESA */
+	{ NULL, 75, 1920, 1440, 3367, 352, 144, 56, 1, 224, 3,
+	  FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED, 0 },
+};
+
+#define VESA_MODEDB_SIZE ARRAY_SIZE(vesa_modes)
+
+static void add_vesa_mode(struct fb_videomode *mode, int num)
+{
+	*mode = vesa_modes[num];
+	mode->name = asprintf("%dx%d@%d-vesa", mode->xres, mode->yres, mode->refresh);
+	pr_debug("      %s\n", mode->name);
+}
+
+static int get_est_timing(unsigned char *block, struct fb_videomode *mode)
+{
+	int num = 0;
+	unsigned char c;
+
+	c = block[0];
+	if (c & 0x80)
+		calc_mode_timings(720, 400, 70, &mode[num++]);
+	if (c & 0x40)
+		calc_mode_timings(720, 400, 88, &mode[num++]);
+	if (c & 0x20)
+		add_vesa_mode(&mode[num++], 3);
+	if (c & 0x10)
+		calc_mode_timings(640, 480, 67, &mode[num++]);
+	if (c & 0x08)
+		add_vesa_mode(&mode[num++], 4);
+	if (c & 0x04)
+		add_vesa_mode(&mode[num++], 5);
+	if (c & 0x02)
+		add_vesa_mode(&mode[num++], 7);
+	if (c & 0x01)
+		add_vesa_mode(&mode[num++], 8);
+
+	c = block[1];
+	if (c & 0x80)
+		add_vesa_mode(&mode[num++], 9);
+	if (c & 0x40)
+		add_vesa_mode(&mode[num++], 10);
+	if (c & 0x20)
+		calc_mode_timings(832, 624, 75, &mode[num++]);
+	if (c & 0x10)
+		add_vesa_mode(&mode[num++], 12);
+	if (c & 0x08)
+		add_vesa_mode(&mode[num++], 13);
+	if (c & 0x04)
+		add_vesa_mode(&mode[num++], 14);
+	if (c & 0x02)
+		add_vesa_mode(&mode[num++], 15);
+	if (c & 0x01)
+		add_vesa_mode(&mode[num++], 21);
+	c = block[2];
+
+	if (c & 0x80)
+		add_vesa_mode(&mode[num++], 17);
+
+	pr_debug("      Manufacturer's mask: %x\n",c & 0x7F);
+	return num;
+}
+
+static int get_std_timing(unsigned char *block, struct fb_videomode *mode,
+		int ver, int rev)
+{
+	int xres, yres = 0, refresh, ratio, i;
+
+	xres = (block[0] + 31) * 8;
+	if (xres <= 256)
+		return 0;
+
+	ratio = (block[1] & 0xc0) >> 6;
+	switch (ratio) {
+	case 0:
+		/* in EDID 1.3 the meaning of 0 changed to 16:10 (prior 1:1) */
+		if (ver < 1 || (ver == 1 && rev < 3))
+			yres = xres;
+		else
+			yres = (xres * 10) / 16;
+		break;
+	case 1:
+		yres = (xres * 3) / 4;
+		break;
+	case 2:
+		yres = (xres * 4) / 5;
+		break;
+	case 3:
+		yres = (xres * 9) / 16;
+		break;
+	}
+	refresh = (block[1] & 0x3f) + 60;
+
+	for (i = 0; i < VESA_MODEDB_SIZE; i++) {
+		if (vesa_modes[i].xres == xres &&
+		    vesa_modes[i].yres == yres &&
+		    vesa_modes[i].refresh == refresh) {
+			add_vesa_mode(mode, i);
+			return 1;
+		}
+	}
+
+	calc_mode_timings(xres, yres, refresh, mode);
+
+	return 1;
+}
+
+static int get_dst_timing(unsigned char *block,
+			  struct fb_videomode *mode, int ver, int rev)
+{
+	int j, num = 0;
+
+	for (j = 0; j < 6; j++, block += STD_TIMING_DESCRIPTION_SIZE)
+		num += get_std_timing(block, &mode[num], ver, rev);
+
+	return num;
+}
+
+static void get_detailed_timing(unsigned char *block,
+				struct fb_videomode *mode)
+{
+	mode->xres = H_ACTIVE;
+	mode->yres = V_ACTIVE;
+	mode->pixclock = PIXEL_CLOCK;
+	mode->pixclock /= 1000;
+	mode->pixclock = KHZ2PICOS(mode->pixclock);
+	mode->right_margin = H_SYNC_OFFSET;
+	mode->left_margin = (H_ACTIVE + H_BLANKING) -
+		(H_ACTIVE + H_SYNC_OFFSET + H_SYNC_WIDTH);
+	mode->upper_margin = V_BLANKING - V_SYNC_OFFSET -
+		V_SYNC_WIDTH;
+	mode->lower_margin = V_SYNC_OFFSET;
+	mode->hsync_len = H_SYNC_WIDTH;
+	mode->vsync_len = V_SYNC_WIDTH;
+	if (HSYNC_POSITIVE)
+		mode->sync |= FB_SYNC_HOR_HIGH_ACT;
+	if (VSYNC_POSITIVE)
+		mode->sync |= FB_SYNC_VERT_HIGH_ACT;
+	mode->refresh = PIXEL_CLOCK/((H_ACTIVE + H_BLANKING) *
+				     (V_ACTIVE + V_BLANKING));
+	if (INTERLACED) {
+		mode->yres *= 2;
+		mode->upper_margin *= 2;
+		mode->lower_margin *= 2;
+		mode->vsync_len *= 2;
+		mode->vmode |= FB_VMODE_INTERLACED;
+	}
+
+	pr_debug("      %d MHz ",  PIXEL_CLOCK/1000000);
+	pr_debug("%d %d %d %d ", H_ACTIVE, H_ACTIVE + H_SYNC_OFFSET,
+	       H_ACTIVE + H_SYNC_OFFSET + H_SYNC_WIDTH, H_ACTIVE + H_BLANKING);
+	pr_debug("%d %d %d %d ", V_ACTIVE, V_ACTIVE + V_SYNC_OFFSET,
+	       V_ACTIVE + V_SYNC_OFFSET + V_SYNC_WIDTH, V_ACTIVE + V_BLANKING);
+	pr_debug("%sHSync %sVSync\n", (HSYNC_POSITIVE) ? "+" : "-",
+	       (VSYNC_POSITIVE) ? "+" : "-");
+
+	mode->name = asprintf("%dx%d@%d", mode->xres, mode->yres, mode->refresh);
+}
+
+/**
+ * edid_to_display_timings - create video mode database
+ * @edid: EDID data
+ * @dbsize: database size
+ *
+ * RETURNS: struct fb_videomode, @dbsize contains length of database
+ *
+ * DESCRIPTION:
+ * This function builds a mode database using the contents of the EDID
+ * data
+ */
+int edid_to_display_timings(struct display_timings *timings, unsigned char *edid)
+{
+	struct fb_videomode *mode;
+	unsigned char *block;
+	int num = 0, i, first = 1;
+	int ver, rev, ret;
+
+	ver = edid[EDID_STRUCT_VERSION];
+	rev = edid[EDID_STRUCT_REVISION];
+
+	mode = xzalloc(50 * sizeof(struct fb_videomode));
+
+	if (!edid_checksum(edid) ||
+	    !edid_check_header(edid)) {
+		ret = -EINVAL;
+		goto out;
+	}
+
+	pr_debug("   Detailed Timings\n");
+	block = edid + DETAILED_TIMING_DESCRIPTIONS_START;
+	for (i = 0; i < 4; i++, block+= DETAILED_TIMING_DESCRIPTION_SIZE) {
+		if (!(block[0] == 0x00 && block[1] == 0x00)) {
+			get_detailed_timing(block, &mode[num]);
+			if (first) {
+				first = 0;
+			}
+			num++;
+		}
+	}
+
+	pr_debug("   Supported VESA Modes\n");
+	block = edid + ESTABLISHED_TIMING_1;
+	num += get_est_timing(block, &mode[num]);
+
+	pr_debug("   Standard Timings\n");
+	block = edid + STD_TIMING_DESCRIPTIONS_START;
+	for (i = 0; i < STD_TIMING; i++, block += STD_TIMING_DESCRIPTION_SIZE)
+		num += get_std_timing(block, &mode[num], ver, rev);
+
+	block = edid + DETAILED_TIMING_DESCRIPTIONS_START;
+	for (i = 0; i < 4; i++, block+= DETAILED_TIMING_DESCRIPTION_SIZE) {
+		if (block[0] == 0x00 && block[1] == 0x00 && block[3] == 0xfa)
+			num += get_dst_timing(block + 5, &mode[num], ver, rev);
+	}
+
+	/* Yikes, EDID data is totally useless */
+	if (!num) {
+		free(mode);
+		return -EINVAL;
+	}
+
+	timings->num_modes = num;
+	timings->modes = mode;
+
+	return 0;
+out:
+	free(timings);
+	free(mode);
+	return ret;
+}
+
+#define DDC_ADDR	0x50
+#define DDC_SEGMENT_ADDR 0x30
+
+/**
+ * Get EDID information via I2C.
+ *
+ * \param adapter : i2c device adaptor
+ * \param buf     : EDID data buffer to be filled
+ * \param len     : EDID data buffer length
+ * \return 0 on success or -1 on failure.
+ *
+ * Try to fetch EDID information by calling i2c driver function.
+ */
+static int
+edid_do_read_i2c(struct i2c_adapter *adapter, unsigned char *buf,
+		      int block, int len)
+{
+	unsigned char start = block * EDID_LENGTH;
+	unsigned char segment = block >> 1;
+	unsigned char xfers = segment ? 3 : 2;
+	int ret, retries = 5;
+
+	/* The core i2c driver will automatically retry the transfer if the
+	 * adapter reports EAGAIN. However, we find that bit-banging transfers
+	 * are susceptible to errors under a heavily loaded machine and
+	 * generate spurious NAKs and timeouts. Retrying the transfer
+	 * of the individual block a few times seems to overcome this.
+	 */
+	do {
+		struct i2c_msg msgs[] = {
+			{
+				.addr	= DDC_SEGMENT_ADDR,
+				.flags	= 0,
+				.len	= 1,
+				.buf	= &segment,
+			}, {
+				.addr	= DDC_ADDR,
+				.flags	= 0,
+				.len	= 1,
+				.buf	= &start,
+			}, {
+				.addr	= DDC_ADDR,
+				.flags	= I2C_M_RD,
+				.len	= len,
+				.buf	= buf,
+			}
+		};
+
+	/*
+	 * Avoid sending the segment addr to not upset non-compliant ddc
+	 * monitors.
+	 */
+		ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers);
+	} while (ret != xfers && --retries);
+
+	return ret == xfers ? 0 : -1;
+}
+
+void *edid_read_i2c(struct i2c_adapter *adapter)
+{
+	u8 *block;
+
+	block = xmalloc(EDID_LENGTH);
+
+	if (edid_do_read_i2c(adapter, block, 0, EDID_LENGTH))
+		goto out;
+
+	return block;
+out:
+	free(block);
+
+	return NULL;
+}
+
+void fb_edid_add_modes(struct fb_info *info)
+{
+	if (info->edid_i2c_adapter)
+		info->edid_data = edid_read_i2c(info->edid_i2c_adapter);
+
+	if (!info->edid_data)
+		return;
+
+	edid_to_display_timings(&info->edid_modes, info->edid_data);
+}
diff --git a/drivers/video/edid.h b/drivers/video/edid.h
new file mode 100644
index 0000000..006d9f2
--- /dev/null
+++ b/drivers/video/edid.h
@@ -0,0 +1,138 @@
+/*
+ * drivers/video/edid.h - EDID/DDC Header
+ *
+ * Based on:
+ *   1. XFree86 4.3.0, edid.h
+ *      Copyright 1998 by Egbert Eich <Egbert.Eich at Physik.TU-Darmstadt.DE>
+ *
+ *   2. John Fremlin <vii at users.sourceforge.net> and
+ *      Ani Joshi <ajoshi at unixbox.com>
+ *
+ * DDC is a Trademark of VESA (Video Electronics Standard Association).
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file COPYING in the main directory of this archive
+ * for more details.
+*/
+
+#ifndef __EDID_H__
+#define __EDID_H__
+
+#define EDID_LENGTH				0x80
+#define EDID_HEADER				0x00
+#define EDID_HEADER_END				0x07
+
+#define ID_MANUFACTURER_NAME			0x08
+#define ID_MANUFACTURER_NAME_END		0x09
+#define ID_MODEL				0x0a
+
+#define ID_SERIAL_NUMBER			0x0c
+
+#define MANUFACTURE_WEEK			0x10
+#define MANUFACTURE_YEAR			0x11
+
+#define EDID_STRUCT_VERSION			0x12
+#define EDID_STRUCT_REVISION			0x13
+
+#define EDID_STRUCT_DISPLAY                     0x14
+
+#define DPMS_FLAGS				0x18
+#define ESTABLISHED_TIMING_1			0x23
+#define ESTABLISHED_TIMING_2			0x24
+#define MANUFACTURERS_TIMINGS			0x25
+
+/* standard timings supported */
+#define STD_TIMING                              8
+#define STD_TIMING_DESCRIPTION_SIZE             2
+#define STD_TIMING_DESCRIPTIONS_START           0x26
+
+#define DETAILED_TIMING_DESCRIPTIONS_START	0x36
+#define DETAILED_TIMING_DESCRIPTION_SIZE	18
+#define NO_DETAILED_TIMING_DESCRIPTIONS		4
+
+#define DETAILED_TIMING_DESCRIPTION_1		0x36
+#define DETAILED_TIMING_DESCRIPTION_2		0x48
+#define DETAILED_TIMING_DESCRIPTION_3		0x5a
+#define DETAILED_TIMING_DESCRIPTION_4		0x6c
+
+#define DESCRIPTOR_DATA				5
+
+#define UPPER_NIBBLE( x ) \
+        (((128|64|32|16) & (x)) >> 4)
+
+#define LOWER_NIBBLE( x ) \
+        ((1|2|4|8) & (x))
+
+#define COMBINE_HI_8LO( hi, lo ) \
+        ( (((unsigned)hi) << 8) | (unsigned)lo )
+
+#define COMBINE_HI_4LO( hi, lo ) \
+        ( (((unsigned)hi) << 4) | (unsigned)lo )
+
+#define PIXEL_CLOCK_LO     (unsigned)block[ 0 ]
+#define PIXEL_CLOCK_HI     (unsigned)block[ 1 ]
+#define PIXEL_CLOCK	   (COMBINE_HI_8LO( PIXEL_CLOCK_HI,PIXEL_CLOCK_LO )*10000)
+#define H_ACTIVE_LO        (unsigned)block[ 2 ]
+#define H_BLANKING_LO      (unsigned)block[ 3 ]
+#define H_ACTIVE_HI        UPPER_NIBBLE( (unsigned)block[ 4 ] )
+#define H_ACTIVE           COMBINE_HI_8LO( H_ACTIVE_HI, H_ACTIVE_LO )
+#define H_BLANKING_HI      LOWER_NIBBLE( (unsigned)block[ 4 ] )
+#define H_BLANKING         COMBINE_HI_8LO( H_BLANKING_HI, H_BLANKING_LO )
+
+#define V_ACTIVE_LO        (unsigned)block[ 5 ]
+#define V_BLANKING_LO      (unsigned)block[ 6 ]
+#define V_ACTIVE_HI        UPPER_NIBBLE( (unsigned)block[ 7 ] )
+#define V_ACTIVE           COMBINE_HI_8LO( V_ACTIVE_HI, V_ACTIVE_LO )
+#define V_BLANKING_HI      LOWER_NIBBLE( (unsigned)block[ 7 ] )
+#define V_BLANKING         COMBINE_HI_8LO( V_BLANKING_HI, V_BLANKING_LO )
+
+#define H_SYNC_OFFSET_LO   (unsigned)block[ 8 ]
+#define H_SYNC_WIDTH_LO    (unsigned)block[ 9 ]
+
+#define V_SYNC_OFFSET_LO   UPPER_NIBBLE( (unsigned)block[ 10 ] )
+#define V_SYNC_WIDTH_LO    LOWER_NIBBLE( (unsigned)block[ 10 ] )
+
+#define V_SYNC_WIDTH_HI    ((unsigned)block[ 11 ] & (1|2))
+#define V_SYNC_OFFSET_HI   (((unsigned)block[ 11 ] & (4|8)) >> 2)
+
+#define H_SYNC_WIDTH_HI    (((unsigned)block[ 11 ] & (16|32)) >> 4)
+#define H_SYNC_OFFSET_HI   (((unsigned)block[ 11 ] & (64|128)) >> 6)
+
+#define V_SYNC_WIDTH       COMBINE_HI_4LO( V_SYNC_WIDTH_HI, V_SYNC_WIDTH_LO )
+#define V_SYNC_OFFSET      COMBINE_HI_4LO( V_SYNC_OFFSET_HI, V_SYNC_OFFSET_LO )
+
+#define H_SYNC_WIDTH       COMBINE_HI_8LO( H_SYNC_WIDTH_HI, H_SYNC_WIDTH_LO )
+#define H_SYNC_OFFSET      COMBINE_HI_8LO( H_SYNC_OFFSET_HI, H_SYNC_OFFSET_LO )
+
+#define H_SIZE_LO          (unsigned)block[ 12 ]
+#define V_SIZE_LO          (unsigned)block[ 13 ]
+
+#define H_SIZE_HI          UPPER_NIBBLE( (unsigned)block[ 14 ] )
+#define V_SIZE_HI          LOWER_NIBBLE( (unsigned)block[ 14 ] )
+
+#define H_SIZE             COMBINE_HI_8LO( H_SIZE_HI, H_SIZE_LO )
+#define V_SIZE             COMBINE_HI_8LO( V_SIZE_HI, V_SIZE_LO )
+
+#define H_BORDER           (unsigned)block[ 15 ]
+#define V_BORDER           (unsigned)block[ 16 ]
+
+#define FLAGS              (unsigned)block[ 17 ]
+
+#define INTERLACED         (FLAGS&128)
+#define SYNC_TYPE          (FLAGS&3<<3)	/* bits 4,3 */
+#define SYNC_SEPARATE      (3<<3)
+#define HSYNC_POSITIVE     (FLAGS & 4)
+#define VSYNC_POSITIVE     (FLAGS & 2)
+
+#define V_MIN_RATE              block[ 5 ]
+#define V_MAX_RATE              block[ 6 ]
+#define H_MIN_RATE              block[ 7 ]
+#define H_MAX_RATE              block[ 8 ]
+#define MAX_PIXEL_CLOCK         (((int)block[ 9 ]) * 10)
+#define GTF_SUPPORT		block[10]
+
+#define DPMS_ACTIVE_OFF		(1 << 5)
+#define DPMS_SUSPEND		(1 << 6)
+#define DPMS_STANDBY		(1 << 7)
+
+#endif /* __EDID_H__ */
diff --git a/drivers/video/fb.c b/drivers/video/fb.c
index d7a3d3c..2c8b8eb 100644
--- a/drivers/video/fb.c
+++ b/drivers/video/fb.c
@@ -53,11 +53,14 @@ static struct fb_videomode *fb_num_to_mode(struct fb_info *info, int num)
 {
 	int num_modes;
 
-	num_modes = info->modes.num_modes;
+	num_modes = info->modes.num_modes + info->edid_modes.num_modes;
 
 	if (num >= num_modes)
 		return NULL;
 
+	if (num >= info->modes.num_modes)
+		return &info->edid_modes.modes[num - info->modes.num_modes];
+
 	return &info->modes.modes[num];
 }
 
@@ -142,6 +145,7 @@ static void fb_info(struct device_d *dev)
 	printf("available modes:\n");
 
 	fb_print_modes(&info->modes);
+	fb_print_modes(&info->edid_modes);
 
 	printf("\n");
 }
@@ -191,13 +195,17 @@ int register_framebuffer(struct fb_info *info)
 	dev_add_param_bool(dev, "enable", fb_enable_set, NULL,
 			&info->p_enable, info);
 
-	num_modes = info->modes.num_modes;
+	if (IS_ENABLED(CONFIG_DRIVER_VIDEO_EDID))
+		fb_edid_add_modes(info);
+
+	num_modes = info->modes.num_modes + info->edid_modes.num_modes;
 
 	names = xzalloc(sizeof(char *) * num_modes);
 
 	for (i = 0; i < info->modes.num_modes; i++)
 		names[i] = info->modes.modes[i].name;
-
+	for (i = 0; i < info->edid_modes.num_modes; i++)
+		names[i + info->modes.num_modes] = info->edid_modes.modes[i].name;
 	dev_add_param_enum(dev, "mode_name", fb_set_modename, NULL, &info->current_mode, names, num_modes, info);
 
 	info->mode = fb_num_to_mode(info, 0);
diff --git a/include/fb.h b/include/fb.h
index 8d255c0..7829a0f 100644
--- a/include/fb.h
+++ b/include/fb.h
@@ -100,12 +100,18 @@ struct display_timings {
 	struct fb_videomode *modes;
 };
 
+struct i2c_adapter;
+
 struct fb_info {
 	struct fb_videomode *mode;
 	struct display_timings modes;
 
 	int current_mode;
 
+	void *edid_data;
+	struct i2c_adapter *edid_i2c_adapter;
+	struct display_timings edid_modes;
+
 	struct fb_ops *fbops;
 	struct device_d dev;		/* This is this fb device */
 
@@ -149,5 +155,8 @@ extern struct bus_type fb_bus;
 
 int fb_register_simplefb(struct fb_info *info);
 
-#endif /* __FB_H */
+int edid_to_display_timings(struct display_timings *, unsigned char *edid);
+void *edid_read_i2c(struct i2c_adapter *adapter);
+void fb_edid_add_modes(struct fb_info *info);
 
+#endif /* __FB_H */
-- 
1.9.0



From s.hauer at pengutronix.de  Fri Mar 14 10:32:47 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 14 Mar 2014 15:32:47 +0100
Subject: [PATCH 27/29] video: i.MX IPUv3: Add lvds bridge support
In-Reply-To: <1394807569-23620-1-git-send-email-s.hauer@pengutronix.de>
References: <1394807569-23620-1-git-send-email-s.hauer@pengutronix.de>
Message-ID: <1394807569-23620-28-git-send-email-s.hauer@pengutronix.de>

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 drivers/video/imx-ipu-v3/Kconfig   |   3 +
 drivers/video/imx-ipu-v3/Makefile  |   1 +
 drivers/video/imx-ipu-v3/imx-ldb.c | 310 +++++++++++++++++++++++++++++++++++++
 3 files changed, 314 insertions(+)
 create mode 100644 drivers/video/imx-ipu-v3/imx-ldb.c

diff --git a/drivers/video/imx-ipu-v3/Kconfig b/drivers/video/imx-ipu-v3/Kconfig
index 84ef363..e83158a 100644
--- a/drivers/video/imx-ipu-v3/Kconfig
+++ b/drivers/video/imx-ipu-v3/Kconfig
@@ -5,4 +5,7 @@ config DRIVER_VIDEO_IMX_IPUV3
 
 if DRIVER_VIDEO_IMX_IPUV3
 
+config DRIVER_VIDEO_IMX_IPUV3_LVDS
+	bool "IPUv3 LVDS support"
+
 endif
diff --git a/drivers/video/imx-ipu-v3/Makefile b/drivers/video/imx-ipu-v3/Makefile
index 0edc1a4..e2ff43d 100644
--- a/drivers/video/imx-ipu-v3/Makefile
+++ b/drivers/video/imx-ipu-v3/Makefile
@@ -1,3 +1,4 @@
 obj-$(CONFIG_DRIVER_VIDEO_IMX_IPUV3) += ipu-common.o ipu-dmfc.o ipu-di.o
 obj-$(CONFIG_DRIVER_VIDEO_IMX_IPUV3) += ipu-dp.o ipuv3-plane.o ipufb.o
 obj-$(CONFIG_DRIVER_VIDEO_IMX_IPUV3) += ipu-dc.o
+obj-$(CONFIG_DRIVER_VIDEO_IMX_IPUV3_LVDS) += imx-ldb.o
diff --git a/drivers/video/imx-ipu-v3/imx-ldb.c b/drivers/video/imx-ipu-v3/imx-ldb.c
new file mode 100644
index 0000000..7367fbe
--- /dev/null
+++ b/drivers/video/imx-ipu-v3/imx-ldb.c
@@ -0,0 +1,310 @@
+/*
+ * i.MX drm driver - parallel display implementation
+ *
+ * Copyright (C) 2012 Sascha Hauer, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#include <common.h>
+#include <fb.h>
+#include <io.h>
+#include <driver.h>
+#include <malloc.h>
+#include <errno.h>
+#include <init.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <asm-generic/div64.h>
+#include <linux/clk.h>
+#include <mach/imx6-regs.h>
+#include <mach/imx53-regs.h>
+
+#include "imx-ipu-v3.h"
+#include "ipuv3-plane.h"
+
+#define LDB_CH0_MODE_EN_TO_DI0		(1 << 0)
+#define LDB_CH0_MODE_EN_TO_DI1		(3 << 0)
+#define LDB_CH0_MODE_EN_MASK		(3 << 0)
+#define LDB_CH1_MODE_EN_TO_DI0		(1 << 2)
+#define LDB_CH1_MODE_EN_TO_DI1		(3 << 2)
+#define LDB_CH1_MODE_EN_MASK		(3 << 2)
+#define LDB_SPLIT_MODE_EN		(1 << 4)
+#define LDB_DATA_WIDTH_CH0_24		(1 << 5)
+#define LDB_BIT_MAP_CH0_JEIDA		(1 << 6)
+#define LDB_DATA_WIDTH_CH1_24		(1 << 7)
+#define LDB_BIT_MAP_CH1_JEIDA		(1 << 8)
+#define LDB_DI0_VS_POL_ACT_LOW		(1 << 9)
+#define LDB_DI1_VS_POL_ACT_LOW		(1 << 10)
+#define LDB_BGREF_RMODE_INT		(1 << 15)
+
+struct imx_ldb;
+
+struct imx_ldb_channel {
+	struct imx_ldb *ldb;
+	int chno;
+	int mode_valid;
+	struct display_timings *modes;
+	struct ipu_output output;
+};
+
+struct imx_ldb_data {
+	void __iomem *base;
+	int (*prepare)(struct imx_ldb_channel *imx_ldb_ch, int di);
+	unsigned ipu_mask;
+};
+
+struct imx_ldb {
+	struct device_d *dev;
+	u32 interface_pix_fmt;
+	int mode_valid;
+	struct imx_ldb_channel channel[2];
+	u32 ldb_ctrl;
+	void __iomem *base;
+	const struct imx_ldb_data *soc_data;
+};
+
+enum {
+	LVDS_BIT_MAP_SPWG,
+	LVDS_BIT_MAP_JEIDA
+};
+
+static const char * const imx_ldb_bit_mappings[] = {
+	[LVDS_BIT_MAP_SPWG]  = "spwg",
+	[LVDS_BIT_MAP_JEIDA] = "jeida",
+};
+
+static const int of_get_data_mapping(struct device_node *np)
+{
+	const char *bm;
+	int ret, i;
+
+	ret = of_property_read_string(np, "fsl,data-mapping", &bm);
+	if (ret < 0)
+		return ret;
+
+	for (i = 0; i < ARRAY_SIZE(imx_ldb_bit_mappings); i++)
+		if (!strcasecmp(bm, imx_ldb_bit_mappings[i]))
+			return i;
+
+	return -EINVAL;
+}
+
+static int imx_ldb_prepare(struct ipu_output *output, struct fb_videomode *mode, int di)
+{
+	struct imx_ldb_channel *imx_ldb_ch = container_of(output, struct imx_ldb_channel, output);
+	struct imx_ldb *ldb = imx_ldb_ch->ldb;
+
+	if (PICOS2KHZ(mode->pixclock) > 85000) {
+		dev_warn(ldb->dev,
+			 "%s: mode exceeds 85 MHz pixel clock\n", __func__);
+	}
+
+	ldb->soc_data->prepare(imx_ldb_ch, di);
+
+	/* FIXME - assumes straight connections DI0 --> CH0, DI1 --> CH1 */
+	if (imx_ldb_ch == &ldb->channel[0]) {
+		if (mode->sync & FB_SYNC_VERT_HIGH_ACT)
+			ldb->ldb_ctrl |= LDB_DI0_VS_POL_ACT_LOW;
+		else
+			ldb->ldb_ctrl &= ~LDB_DI0_VS_POL_ACT_LOW;
+	}
+
+	if (imx_ldb_ch == &ldb->channel[1]) {
+		if (mode->sync & FB_SYNC_VERT_HIGH_ACT)
+			ldb->ldb_ctrl |= LDB_DI1_VS_POL_ACT_LOW;
+		else
+			ldb->ldb_ctrl &= ~LDB_DI1_VS_POL_ACT_LOW;
+	}
+
+	if (imx_ldb_ch == &ldb->channel[0]) {
+		ldb->ldb_ctrl &= ~LDB_CH0_MODE_EN_MASK;
+		ldb->ldb_ctrl |= LDB_CH0_MODE_EN_TO_DI0;
+	}
+
+	if (imx_ldb_ch == &ldb->channel[1]) {
+		ldb->ldb_ctrl &= ~LDB_CH1_MODE_EN_MASK;
+		ldb->ldb_ctrl |= LDB_CH1_MODE_EN_TO_DI1;
+	}
+
+	writel(ldb->ldb_ctrl, ldb->base);
+
+	return 0;
+}
+
+static int imx6q_ldb_prepare(struct imx_ldb_channel *imx_ldb_ch, int di)
+{
+	struct clk *diclk, *ldbclk;
+	struct imx_ldb *ldb = imx_ldb_ch->ldb;
+	int ret, ipuno, dino;
+	char *clkname;
+	void __iomem *gpr3 = (void *)MX6_IOMUXC_BASE_ADDR + 0xc;
+	uint32_t val;
+	int shift;
+
+	ipuno = ((di >> 1) & 1) + 1;
+	dino = di & 0x1;
+
+	clkname = asprintf("ipu%d_di%d_sel", ipuno, dino);
+	diclk = clk_lookup(clkname);
+	free(clkname);
+	if (IS_ERR(diclk)) {
+		dev_err(ldb->dev, "failed to get di clk: %s\n", strerror(PTR_ERR(diclk)));
+		return PTR_ERR(diclk);
+	}
+
+	clkname = asprintf("ldb_di%d_podf", imx_ldb_ch->chno);
+	ldbclk = clk_lookup(clkname);
+	free(clkname);
+	if (IS_ERR(ldbclk)) {
+		dev_err(ldb->dev, "failed to get ldb clk: %s\n", strerror(PTR_ERR(ldbclk)));
+		return PTR_ERR(ldbclk);
+	}
+
+	ret = clk_set_parent(diclk, ldbclk);
+	if (ret) {
+		dev_err(ldb->dev, "failed to set display clock parent: %s\n", strerror(-ret));
+		return ret;
+	}
+printk("%s: %d\n", __func__, di);
+	val = readl(gpr3);
+	shift = (imx_ldb_ch->chno == 0) ? 6 : 8;
+	val &= ~(3 << shift);
+	val |= di << shift;
+	writel(val, gpr3);
+
+	return 0;
+}
+
+static int imx53_ldb_prepare(struct imx_ldb_channel *imx_ldb_ch, int di)
+{
+	return -ENOSYS;
+}
+
+static struct imx_ldb_data imx_ldb_data_imx6q = {
+	.base = (void *)MX6_IOMUXC_BASE_ADDR + 0x8,
+	.prepare = imx6q_ldb_prepare,
+	.ipu_mask = 0xf,
+};
+
+static struct imx_ldb_data imx_ldb_data_imx53 = {
+	.base = (void *)MX53_IOMUXC_BASE_ADDR + 0x8,
+	.prepare = imx53_ldb_prepare,
+	.ipu_mask = 0x3,
+};
+
+static struct ipu_output_ops imx_ldb_ops = {
+	.prepare = imx_ldb_prepare,
+};
+
+static int imx_ldb_probe(struct device_d *dev)
+{
+	struct device_node *np = dev->device_node;
+	struct device_node *child;
+	struct imx_ldb *imx_ldb;
+	int ret, i;
+	int dual = 0;
+	int datawidth;
+	int mapping;
+	const struct imx_ldb_data *devtype;
+
+	ret = dev_get_drvdata(dev, (unsigned long *)&devtype);
+	if (ret)
+		return ret;
+
+	imx_ldb = xzalloc(sizeof(*imx_ldb));
+	imx_ldb->base = devtype->base;
+	imx_ldb->soc_data = devtype;
+
+	for_each_child_of_node(np, child) {
+		struct imx_ldb_channel *channel;
+
+		ret = of_property_read_u32(child, "reg", &i);
+		if (ret || i < 0 || i > 1)
+			return -EINVAL;
+
+		if (dual && i > 0) {
+			dev_warn(dev, "dual-channel mode, ignoring second output\n");
+			continue;
+		}
+
+		if (!of_device_is_available(child))
+			continue;
+
+		channel = &imx_ldb->channel[i];
+		channel->ldb = imx_ldb;
+		channel->chno = i;
+
+		ret = of_property_read_u32(child, "fsl,data-width", &datawidth);
+		if (ret)
+			datawidth = 0;
+		else if (datawidth != 18 && datawidth != 24)
+			return -EINVAL;
+
+		mapping = of_get_data_mapping(child);
+		switch (mapping) {
+		case LVDS_BIT_MAP_SPWG:
+			if (datawidth == 24) {
+				if (i == 0 || dual)
+					imx_ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH0_24;
+				if (i == 1 || dual)
+					imx_ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH1_24;
+			}
+			break;
+		case LVDS_BIT_MAP_JEIDA:
+			if (datawidth == 18) {
+				dev_err(dev, "JEIDA standard only supported in 24 bit\n");
+				return -EINVAL;
+			}
+			if (i == 0 || dual)
+				imx_ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH0_24 | LDB_BIT_MAP_CH0_JEIDA;
+			if (i == 1 || dual)
+				imx_ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH1_24 | LDB_BIT_MAP_CH1_JEIDA;
+			break;
+		default:
+			dev_err(dev, "data mapping not specified or invalid\n");
+			return -EINVAL;
+		}
+
+		channel->output.ops = &imx_ldb_ops;
+		channel->output.di_clkflags = IPU_DI_CLKMODE_EXT | IPU_DI_CLKMODE_SYNC;
+		channel->output.out_pixel_fmt = (datawidth == 24) ?
+			V4L2_PIX_FMT_RGB24 : V4L2_PIX_FMT_BGR666;
+		channel->output.modes = of_get_display_timings(child);
+		channel->output.name = asprintf("ldb-%d", i);
+		channel->output.ipu_mask = devtype->ipu_mask;
+
+		ipu_register_output(&channel->output);
+	}
+
+	return 0;
+}
+
+static struct of_device_id imx_ldb_dt_ids[] = {
+	{ .compatible = "fsl,imx6q-ldb", (unsigned long)&imx_ldb_data_imx6q},
+	{ .compatible = "fsl,imx53-ldb", (unsigned long)&imx_ldb_data_imx53},
+	{ /* sentinel */ }
+};
+
+static struct driver_d imx_ldb_driver = {
+	.probe		= imx_ldb_probe,
+	.of_compatible	= imx_ldb_dt_ids,
+	.name		= "imx-ldb",
+};
+device_platform_driver(imx_ldb_driver);
+
+MODULE_DESCRIPTION("i.MX LVDS display driver");
+MODULE_AUTHOR("Sascha Hauer, Pengutronix");
+MODULE_LICENSE("GPL");
-- 
1.9.0



From s.hauer at pengutronix.de  Fri Mar 14 10:32:48 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 14 Mar 2014 15:32:48 +0100
Subject: [PATCH 28/29] video: i.MX IPUv3: Add hdmi support
In-Reply-To: <1394807569-23620-1-git-send-email-s.hauer@pengutronix.de>
References: <1394807569-23620-1-git-send-email-s.hauer@pengutronix.de>
Message-ID: <1394807569-23620-29-git-send-email-s.hauer@pengutronix.de>

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 drivers/video/imx-ipu-v3/Kconfig    |    3 +
 drivers/video/imx-ipu-v3/Makefile   |    1 +
 drivers/video/imx-ipu-v3/imx-hdmi.c | 1297 +++++++++++++++++++++++++++++++++++
 drivers/video/imx-ipu-v3/imx-hdmi.h | 1032 ++++++++++++++++++++++++++++
 4 files changed, 2333 insertions(+)
 create mode 100644 drivers/video/imx-ipu-v3/imx-hdmi.c
 create mode 100644 drivers/video/imx-ipu-v3/imx-hdmi.h

diff --git a/drivers/video/imx-ipu-v3/Kconfig b/drivers/video/imx-ipu-v3/Kconfig
index e83158a..3d656e5 100644
--- a/drivers/video/imx-ipu-v3/Kconfig
+++ b/drivers/video/imx-ipu-v3/Kconfig
@@ -8,4 +8,7 @@ if DRIVER_VIDEO_IMX_IPUV3
 config DRIVER_VIDEO_IMX_IPUV3_LVDS
 	bool "IPUv3 LVDS support"
 
+config DRIVER_VIDEO_IMX_IPUV3_HDMI
+	bool "IPUv3 HDMI support"
+
 endif
diff --git a/drivers/video/imx-ipu-v3/Makefile b/drivers/video/imx-ipu-v3/Makefile
index e2ff43d..2bc0aec 100644
--- a/drivers/video/imx-ipu-v3/Makefile
+++ b/drivers/video/imx-ipu-v3/Makefile
@@ -2,3 +2,4 @@ obj-$(CONFIG_DRIVER_VIDEO_IMX_IPUV3) += ipu-common.o ipu-dmfc.o ipu-di.o
 obj-$(CONFIG_DRIVER_VIDEO_IMX_IPUV3) += ipu-dp.o ipuv3-plane.o ipufb.o
 obj-$(CONFIG_DRIVER_VIDEO_IMX_IPUV3) += ipu-dc.o
 obj-$(CONFIG_DRIVER_VIDEO_IMX_IPUV3_LVDS) += imx-ldb.o
+obj-$(CONFIG_DRIVER_VIDEO_IMX_IPUV3_HDMI) += imx-hdmi.o
diff --git a/drivers/video/imx-ipu-v3/imx-hdmi.c b/drivers/video/imx-ipu-v3/imx-hdmi.c
new file mode 100644
index 0000000..4f46288
--- /dev/null
+++ b/drivers/video/imx-ipu-v3/imx-hdmi.c
@@ -0,0 +1,1297 @@
+/*
+ * Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * SH-Mobile High-Definition Multimedia Interface (HDMI) driver
+ * for SLISHDMI13T and SLIPHDMIT IP cores
+ *
+ * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski at gmx.de>
+ */
+#include <common.h>
+#include <fb.h>
+#include <io.h>
+#include <driver.h>
+#include <malloc.h>
+#include <errno.h>
+#include <init.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <asm-generic/div64.h>
+#include <linux/clk.h>
+#include <i2c/i2c.h>
+#include <mach/imx6-regs.h>
+#include <mach/imx53-regs.h>
+
+#include "imx-ipu-v3.h"
+#include "ipuv3-plane.h"
+#include "imx-hdmi.h"
+
+#define HDMI_EDID_LEN		512
+
+#define RGB			0
+#define YCBCR444		1
+#define YCBCR422_16BITS		2
+#define YCBCR422_8BITS		3
+#define XVYCC444		4
+
+enum hdmi_colorimetry {
+	HDMI_COLORIMETRY_NONE,
+	HDMI_COLORIMETRY_ITU_601,
+	HDMI_COLORIMETRY_ITU_709,
+	HDMI_COLORIMETRY_EXTENDED,
+};
+
+enum hdmi_datamap {
+	RGB444_8B = 0x01,
+	RGB444_10B = 0x03,
+	RGB444_12B = 0x05,
+	RGB444_16B = 0x07,
+	YCbCr444_8B = 0x09,
+	YCbCr444_10B = 0x0B,
+	YCbCr444_12B = 0x0D,
+	YCbCr444_16B = 0x0F,
+	YCbCr422_8B = 0x16,
+	YCbCr422_10B = 0x14,
+	YCbCr422_12B = 0x12,
+};
+
+enum imx_hdmi_devtype {
+	IMX6Q_HDMI,
+	IMX6DL_HDMI,
+};
+
+static const u16 csc_coeff_default[3][4] = {
+	{ 0x2000, 0x0000, 0x0000, 0x0000 },
+	{ 0x0000, 0x2000, 0x0000, 0x0000 },
+	{ 0x0000, 0x0000, 0x2000, 0x0000 }
+};
+
+static const u16 csc_coeff_rgb_out_eitu601[3][4] = {
+	{ 0x2000, 0x6926, 0x74fd, 0x010e },
+	{ 0x2000, 0x2cdd, 0x0000, 0x7e9a },
+	{ 0x2000, 0x0000, 0x38b4, 0x7e3b }
+};
+
+static const u16 csc_coeff_rgb_out_eitu709[3][4] = {
+	{ 0x2000, 0x7106, 0x7a02, 0x00a7 },
+	{ 0x2000, 0x3264, 0x0000, 0x7e6d },
+	{ 0x2000, 0x0000, 0x3b61, 0x7e25 }
+};
+
+static const u16 csc_coeff_rgb_in_eitu601[3][4] = {
+	{ 0x2591, 0x1322, 0x074b, 0x0000 },
+	{ 0x6535, 0x2000, 0x7acc, 0x0200 },
+	{ 0x6acd, 0x7534, 0x2000, 0x0200 }
+};
+
+static const u16 csc_coeff_rgb_in_eitu709[3][4] = {
+	{ 0x2dc5, 0x0d9b, 0x049e, 0x0000 },
+	{ 0x62f0, 0x2000, 0x7d11, 0x0200 },
+	{ 0x6756, 0x78ab, 0x2000, 0x0200 }
+};
+
+struct hdmi_vmode {
+	bool mdvi;
+	bool mhsyncpolarity;
+	bool mvsyncpolarity;
+	bool minterlaced;
+	bool mdataenablepolarity;
+
+	unsigned int mpixelclock;
+	unsigned int mpixelrepetitioninput;
+	unsigned int mpixelrepetitionoutput;
+};
+
+struct hdmi_data_info {
+	unsigned int enc_in_format;
+	unsigned int enc_out_format;
+	unsigned int enc_color_depth;
+	unsigned int colorimetry;
+	unsigned int pix_repet_factor;
+	unsigned int hdcp_enable;
+	struct hdmi_vmode video_mode;
+};
+
+struct imx_hdmi {
+	enum imx_hdmi_devtype dev_type;
+	struct device_d *dev;
+	struct clk *isfr_clk;
+	struct clk *iahb_clk;
+
+	bool connected;
+
+	struct hdmi_data_info hdmi_data;
+	int vic;
+
+	u8 edid[HDMI_EDID_LEN];
+	bool cable_plugin;
+
+	bool phy_enabled;
+
+	struct regmap *regmap;
+	struct i2c_adapter *ddc;
+	void __iomem *regs;
+
+	unsigned int sample_rate;
+	int ratio;
+
+	struct ipu_output output;
+};
+
+static void imx_hdmi_set_ipu_di_mux(struct imx_hdmi *hdmi, int ipu_di)
+{
+	void __iomem *gpr3 = (void *)MX6_IOMUXC_BASE_ADDR + 0xc;
+	uint32_t val;
+
+	dev_info(hdmi->dev, "setup hdmi mux to %d\n", ipu_di);
+
+	val = readl(gpr3);
+	val &= ~(3 << 2);
+	val |= ipu_di << 2;
+	writel(val, gpr3);
+}
+
+static inline void hdmi_writeb(struct imx_hdmi *hdmi, u8 val, int offset)
+{
+	writeb(val, hdmi->regs + offset);
+}
+
+static inline u8 hdmi_readb(struct imx_hdmi *hdmi, int offset)
+{
+	return readb(hdmi->regs + offset);
+}
+
+static void hdmi_modb(struct imx_hdmi *hdmi, u8 data, u8 mask, unsigned reg)
+{
+	u8 val = hdmi_readb(hdmi, reg) & ~mask;
+	val |= data & mask;
+	hdmi_writeb(hdmi, val, reg);
+}
+
+static void hdmi_mask_writeb(struct imx_hdmi *hdmi, u8 data, unsigned int reg,
+		      u8 shift, u8 mask)
+{
+	hdmi_modb(hdmi, data << shift, mask, reg);
+}
+
+static void hdmi_set_clock_regenerator_n(struct imx_hdmi *hdmi,
+					 unsigned int value)
+{
+	hdmi_writeb(hdmi, value & 0xff, HDMI_AUD_N1);
+	hdmi_writeb(hdmi, (value >> 8) & 0xff, HDMI_AUD_N2);
+	hdmi_writeb(hdmi, (value >> 16) & 0x0f, HDMI_AUD_N3);
+
+	/* nshift factor = 0 */
+	hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3);
+}
+
+static void hdmi_regenerate_cts(struct imx_hdmi *hdmi, unsigned int cts)
+{
+	/* Must be set/cleared first */
+	hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
+
+	hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1);
+	hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2);
+	hdmi_writeb(hdmi, ((cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK) |
+		    HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
+}
+
+static unsigned int hdmi_compute_n(unsigned int freq, unsigned long pixel_clk,
+				   unsigned int ratio)
+{
+	unsigned int n = (128 * freq) / 1000;
+
+	switch (freq) {
+	case 32000:
+		if (pixel_clk == 25170000)
+			n = (ratio == 150) ? 9152 : 4576;
+		else if (pixel_clk == 27020000)
+			n = (ratio == 150) ? 8192 : 4096;
+		else if (pixel_clk == 74170000 || pixel_clk == 148350000)
+			n = 11648;
+		else
+			n = 4096;
+		break;
+
+	case 44100:
+		if (pixel_clk == 25170000)
+			n = 7007;
+		else if (pixel_clk == 74170000)
+			n = 17836;
+		else if (pixel_clk == 148350000)
+			n = (ratio == 150) ? 17836 : 8918;
+		else
+			n = 6272;
+		break;
+
+	case 48000:
+		if (pixel_clk == 25170000)
+			n = (ratio == 150) ? 9152 : 6864;
+		else if (pixel_clk == 27020000)
+			n = (ratio == 150) ? 8192 : 6144;
+		else if (pixel_clk == 74170000)
+			n = 11648;
+		else if (pixel_clk == 148350000)
+			n = (ratio == 150) ? 11648 : 5824;
+		else
+			n = 6144;
+		break;
+
+	case 88200:
+		n = hdmi_compute_n(44100, pixel_clk, ratio) * 2;
+		break;
+
+	case 96000:
+		n = hdmi_compute_n(48000, pixel_clk, ratio) * 2;
+		break;
+
+	case 176400:
+		n = hdmi_compute_n(44100, pixel_clk, ratio) * 4;
+		break;
+
+	case 192000:
+		n = hdmi_compute_n(48000, pixel_clk, ratio) * 4;
+		break;
+
+	default:
+		break;
+	}
+
+	return n;
+}
+
+static unsigned int hdmi_compute_cts(unsigned int freq, unsigned long pixel_clk,
+				     unsigned int ratio)
+{
+	unsigned int cts = 0;
+
+	pr_debug("%s: freq: %d pixel_clk: %ld ratio: %d\n", __func__, freq,
+		 pixel_clk, ratio);
+
+	switch (freq) {
+	case 32000:
+		if (pixel_clk == 297000000) {
+			cts = 222750;
+			break;
+		}
+	case 48000:
+	case 96000:
+	case 192000:
+		switch (pixel_clk) {
+		case 25200000:
+		case 27000000:
+		case 54000000:
+		case 74250000:
+		case 148500000:
+			cts = pixel_clk / 1000;
+			break;
+		case 297000000:
+			cts = 247500;
+			break;
+		/*
+		 * All other TMDS clocks are not supported by
+		 * DWC_hdmi_tx. The TMDS clocks divided or
+		 * multiplied by 1,001 coefficients are not
+		 * supported.
+		 */
+		default:
+			break;
+		}
+		break;
+	case 44100:
+	case 88200:
+	case 176400:
+		switch (pixel_clk) {
+		case 25200000:
+			cts = 28000;
+			break;
+		case 27000000:
+			cts = 30000;
+			break;
+		case 54000000:
+			cts = 60000;
+			break;
+		case 74250000:
+			cts = 82500;
+			break;
+		case 148500000:
+			cts = 165000;
+			break;
+		case 297000000:
+			cts = 247500;
+			break;
+		default:
+			break;
+		}
+		break;
+	default:
+		break;
+	}
+	if (ratio == 100)
+		return cts;
+	else
+		return (cts * ratio) / 100;
+}
+
+static void hdmi_set_clk_regenerator(struct imx_hdmi *hdmi,
+	unsigned long pixel_clk)
+{
+	unsigned int clk_n, clk_cts;
+
+	clk_n = hdmi_compute_n(hdmi->sample_rate, pixel_clk,
+			       hdmi->ratio);
+	clk_cts = hdmi_compute_cts(hdmi->sample_rate, pixel_clk,
+				   hdmi->ratio);
+
+	if (!clk_cts) {
+		dev_dbg(hdmi->dev, "%s: pixel clock not supported: %lu\n",
+			 __func__, pixel_clk);
+		return;
+	}
+
+	dev_dbg(hdmi->dev, "%s: samplerate=%d  ratio=%d  pixelclk=%lu  N=%d cts=%d\n",
+		__func__, hdmi->sample_rate, hdmi->ratio,
+		pixel_clk, clk_n, clk_cts);
+
+	hdmi_set_clock_regenerator_n(hdmi, clk_n);
+	hdmi_regenerate_cts(hdmi, clk_cts);
+}
+
+static void hdmi_init_clk_regenerator(struct imx_hdmi *hdmi)
+{
+	hdmi_set_clk_regenerator(hdmi, 74250000);
+}
+
+/*
+ * this submodule is responsible for the video data synchronization.
+ * for example, for RGB 4:4:4 input, the data map is defined as
+ *			pin{47~40} <==> R[7:0]
+ *			pin{31~24} <==> G[7:0]
+ *			pin{15~8}  <==> B[7:0]
+ */
+static void hdmi_video_sample(struct imx_hdmi *hdmi)
+{
+	int color_format = 0;
+	u8 val;
+
+	if (hdmi->hdmi_data.enc_in_format == RGB) {
+		if (hdmi->hdmi_data.enc_color_depth == 8)
+			color_format = 0x01;
+		else if (hdmi->hdmi_data.enc_color_depth == 10)
+			color_format = 0x03;
+		else if (hdmi->hdmi_data.enc_color_depth == 12)
+			color_format = 0x05;
+		else if (hdmi->hdmi_data.enc_color_depth == 16)
+			color_format = 0x07;
+		else
+			return;
+	} else if (hdmi->hdmi_data.enc_in_format == YCBCR444) {
+		if (hdmi->hdmi_data.enc_color_depth == 8)
+			color_format = 0x09;
+		else if (hdmi->hdmi_data.enc_color_depth == 10)
+			color_format = 0x0B;
+		else if (hdmi->hdmi_data.enc_color_depth == 12)
+			color_format = 0x0D;
+		else if (hdmi->hdmi_data.enc_color_depth == 16)
+			color_format = 0x0F;
+		else
+			return;
+	} else if (hdmi->hdmi_data.enc_in_format == YCBCR422_8BITS) {
+		if (hdmi->hdmi_data.enc_color_depth == 8)
+			color_format = 0x16;
+		else if (hdmi->hdmi_data.enc_color_depth == 10)
+			color_format = 0x14;
+		else if (hdmi->hdmi_data.enc_color_depth == 12)
+			color_format = 0x12;
+		else
+			return;
+	}
+
+	val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE |
+		((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) &
+		HDMI_TX_INVID0_VIDEO_MAPPING_MASK);
+	hdmi_writeb(hdmi, val, HDMI_TX_INVID0);
+
+	/* Enable TX stuffing: When DE is inactive, fix the output data to 0 */
+	val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE |
+		HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE |
+		HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE;
+	hdmi_writeb(hdmi, val, HDMI_TX_INSTUFFING);
+	hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA0);
+	hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA1);
+	hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA0);
+	hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA1);
+	hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA0);
+	hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA1);
+}
+
+static int is_color_space_conversion(struct imx_hdmi *hdmi)
+{
+	return (hdmi->hdmi_data.enc_in_format !=
+		hdmi->hdmi_data.enc_out_format);
+}
+
+static int is_color_space_decimation(struct imx_hdmi *hdmi)
+{
+	return ((hdmi->hdmi_data.enc_out_format == YCBCR422_8BITS) &&
+		(hdmi->hdmi_data.enc_in_format == RGB ||
+		hdmi->hdmi_data.enc_in_format == YCBCR444));
+}
+
+static int is_color_space_interpolation(struct imx_hdmi *hdmi)
+{
+	return ((hdmi->hdmi_data.enc_in_format == YCBCR422_8BITS) &&
+		(hdmi->hdmi_data.enc_out_format == RGB ||
+		hdmi->hdmi_data.enc_out_format == YCBCR444));
+}
+
+static void imx_hdmi_update_csc_coeffs(struct imx_hdmi *hdmi)
+{
+	const u16 (*csc_coeff)[3][4] = &csc_coeff_default;
+	unsigned i;
+	u32 csc_scale = 1;
+
+	if (is_color_space_conversion(hdmi)) {
+		if (hdmi->hdmi_data.enc_out_format == RGB) {
+			if (hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_601)
+				csc_coeff = &csc_coeff_rgb_out_eitu601;
+			else
+				csc_coeff = &csc_coeff_rgb_out_eitu709;
+		} else if (hdmi->hdmi_data.enc_in_format == RGB) {
+			if (hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_601)
+				csc_coeff = &csc_coeff_rgb_in_eitu601;
+			else
+				csc_coeff = &csc_coeff_rgb_in_eitu709;
+			csc_scale = 0;
+		}
+	}
+
+	/* The CSC registers are sequential, alternating MSB then LSB */
+	for (i = 0; i < ARRAY_SIZE(csc_coeff_default[0]); i++) {
+		u16 coeff_a = (*csc_coeff)[0][i];
+		u16 coeff_b = (*csc_coeff)[1][i];
+		u16 coeff_c = (*csc_coeff)[2][i];
+
+		hdmi_writeb(hdmi, coeff_a & 0xff, HDMI_CSC_COEF_A1_LSB + i * 2);
+		hdmi_writeb(hdmi, coeff_a >> 8, HDMI_CSC_COEF_A1_MSB + i * 2);
+		hdmi_writeb(hdmi, coeff_b & 0xff, HDMI_CSC_COEF_B1_LSB + i * 2);
+		hdmi_writeb(hdmi, coeff_b >> 8, HDMI_CSC_COEF_B1_MSB + i * 2);
+		hdmi_writeb(hdmi, coeff_c & 0xff, HDMI_CSC_COEF_C1_LSB + i * 2);
+		hdmi_writeb(hdmi, coeff_c >> 8, HDMI_CSC_COEF_C1_MSB + i * 2);
+	}
+
+	hdmi_modb(hdmi, csc_scale, HDMI_CSC_SCALE_CSCSCALE_MASK,
+		  HDMI_CSC_SCALE);
+}
+
+static void hdmi_video_csc(struct imx_hdmi *hdmi)
+{
+	int color_depth = 0;
+	int interpolation = HDMI_CSC_CFG_INTMODE_DISABLE;
+	int decimation = 0;
+
+	/* YCC422 interpolation to 444 mode */
+	if (is_color_space_interpolation(hdmi))
+		interpolation = HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1;
+	else if (is_color_space_decimation(hdmi))
+		decimation = HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3;
+
+	if (hdmi->hdmi_data.enc_color_depth == 8)
+		color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP;
+	else if (hdmi->hdmi_data.enc_color_depth == 10)
+		color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP;
+	else if (hdmi->hdmi_data.enc_color_depth == 12)
+		color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP;
+	else if (hdmi->hdmi_data.enc_color_depth == 16)
+		color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP;
+	else
+		return;
+
+	/* Configure the CSC registers */
+	hdmi_writeb(hdmi, interpolation | decimation, HDMI_CSC_CFG);
+	hdmi_modb(hdmi, color_depth, HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK,
+		  HDMI_CSC_SCALE);
+
+	imx_hdmi_update_csc_coeffs(hdmi);
+}
+
+/*
+ * HDMI video packetizer is used to packetize the data.
+ * for example, if input is YCC422 mode or repeater is used,
+ * data should be repacked this module can be bypassed.
+ */
+static void hdmi_video_packetize(struct imx_hdmi *hdmi)
+{
+	unsigned int color_depth = 0;
+	unsigned int remap_size = HDMI_VP_REMAP_YCC422_16bit;
+	unsigned int output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_PP;
+	struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data;
+	u8 val, vp_conf;
+
+	if (hdmi_data->enc_out_format == RGB
+		|| hdmi_data->enc_out_format == YCBCR444) {
+		if (!hdmi_data->enc_color_depth)
+			output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
+		else if (hdmi_data->enc_color_depth == 8) {
+			color_depth = 4;
+			output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
+		} else if (hdmi_data->enc_color_depth == 10)
+			color_depth = 5;
+		else if (hdmi_data->enc_color_depth == 12)
+			color_depth = 6;
+		else if (hdmi_data->enc_color_depth == 16)
+			color_depth = 7;
+		else
+			return;
+	} else if (hdmi_data->enc_out_format == YCBCR422_8BITS) {
+		if (!hdmi_data->enc_color_depth ||
+		    hdmi_data->enc_color_depth == 8)
+			remap_size = HDMI_VP_REMAP_YCC422_16bit;
+		else if (hdmi_data->enc_color_depth == 10)
+			remap_size = HDMI_VP_REMAP_YCC422_20bit;
+		else if (hdmi_data->enc_color_depth == 12)
+			remap_size = HDMI_VP_REMAP_YCC422_24bit;
+		else
+			return;
+		output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422;
+	} else
+		return;
+
+	/* set the packetizer registers */
+	val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) &
+		HDMI_VP_PR_CD_COLOR_DEPTH_MASK) |
+		((hdmi_data->pix_repet_factor <<
+		HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET) &
+		HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK);
+	hdmi_writeb(hdmi, val, HDMI_VP_PR_CD);
+
+	hdmi_modb(hdmi, HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE,
+		  HDMI_VP_STUFF_PR_STUFFING_MASK, HDMI_VP_STUFF);
+
+	/* Data from pixel repeater block */
+	if (hdmi_data->pix_repet_factor > 1) {
+		vp_conf = HDMI_VP_CONF_PR_EN_ENABLE |
+			  HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER;
+	} else { /* data from packetizer block */
+		vp_conf = HDMI_VP_CONF_PR_EN_DISABLE |
+			  HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER;
+	}
+
+	hdmi_modb(hdmi, vp_conf,
+		  HDMI_VP_CONF_PR_EN_MASK |
+		  HDMI_VP_CONF_BYPASS_SELECT_MASK, HDMI_VP_CONF);
+
+	hdmi_modb(hdmi, 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET,
+		  HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, HDMI_VP_STUFF);
+
+	hdmi_writeb(hdmi, remap_size, HDMI_VP_REMAP);
+
+	if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_PP) {
+		vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
+			  HDMI_VP_CONF_PP_EN_ENABLE |
+			  HDMI_VP_CONF_YCC422_EN_DISABLE;
+	} else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422) {
+		vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
+			  HDMI_VP_CONF_PP_EN_DISABLE |
+			  HDMI_VP_CONF_YCC422_EN_ENABLE;
+	} else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS) {
+		vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE |
+			  HDMI_VP_CONF_PP_EN_DISABLE |
+			  HDMI_VP_CONF_YCC422_EN_DISABLE;
+	} else {
+		return;
+	}
+
+	hdmi_modb(hdmi, vp_conf,
+		  HDMI_VP_CONF_BYPASS_EN_MASK | HDMI_VP_CONF_PP_EN_ENMASK |
+		  HDMI_VP_CONF_YCC422_EN_MASK, HDMI_VP_CONF);
+
+	hdmi_modb(hdmi, HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE |
+			HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE,
+		  HDMI_VP_STUFF_PP_STUFFING_MASK |
+		  HDMI_VP_STUFF_YCC422_STUFFING_MASK, HDMI_VP_STUFF);
+
+	hdmi_modb(hdmi, output_select, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK,
+		  HDMI_VP_CONF);
+}
+
+static inline void hdmi_phy_test_clear(struct imx_hdmi *hdmi,
+						unsigned char bit)
+{
+	hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLR_OFFSET,
+		  HDMI_PHY_TST0_TSTCLR_MASK, HDMI_PHY_TST0);
+}
+
+static inline void hdmi_phy_test_enable(struct imx_hdmi *hdmi,
+						unsigned char bit)
+{
+	hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTEN_OFFSET,
+		  HDMI_PHY_TST0_TSTEN_MASK, HDMI_PHY_TST0);
+}
+
+static inline void hdmi_phy_test_clock(struct imx_hdmi *hdmi,
+						unsigned char bit)
+{
+	hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLK_OFFSET,
+		  HDMI_PHY_TST0_TSTCLK_MASK, HDMI_PHY_TST0);
+}
+
+static inline void hdmi_phy_test_din(struct imx_hdmi *hdmi,
+						unsigned char bit)
+{
+	hdmi_writeb(hdmi, bit, HDMI_PHY_TST1);
+}
+
+static inline void hdmi_phy_test_dout(struct imx_hdmi *hdmi,
+						unsigned char bit)
+{
+	hdmi_writeb(hdmi, bit, HDMI_PHY_TST2);
+}
+
+static bool hdmi_phy_wait_i2c_done(struct imx_hdmi *hdmi, int msec)
+{
+	unsigned char val = 0;
+	val = hdmi_readb(hdmi, HDMI_IH_I2CMPHY_STAT0) & 0x3;
+	while (!val) {
+		udelay(1000);
+		if (msec-- == 0)
+			return false;
+		val = hdmi_readb(hdmi, HDMI_IH_I2CMPHY_STAT0) & 0x3;
+	}
+	return true;
+}
+
+static void __hdmi_phy_i2c_write(struct imx_hdmi *hdmi, unsigned short data,
+			      unsigned char addr)
+{
+	hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0);
+	hdmi_writeb(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR);
+	hdmi_writeb(hdmi, (unsigned char)(data >> 8),
+		HDMI_PHY_I2CM_DATAO_1_ADDR);
+	hdmi_writeb(hdmi, (unsigned char)(data >> 0),
+		HDMI_PHY_I2CM_DATAO_0_ADDR);
+	hdmi_writeb(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE,
+		HDMI_PHY_I2CM_OPERATION_ADDR);
+	hdmi_phy_wait_i2c_done(hdmi, 1000);
+}
+
+static int hdmi_phy_i2c_write(struct imx_hdmi *hdmi, unsigned short data,
+				     unsigned char addr)
+{
+	__hdmi_phy_i2c_write(hdmi, data, addr);
+	return 0;
+}
+
+static void imx_hdmi_phy_enable_power(struct imx_hdmi *hdmi, u8 enable)
+{
+	hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
+			 HDMI_PHY_CONF0_PDZ_OFFSET,
+			 HDMI_PHY_CONF0_PDZ_MASK);
+}
+
+static void imx_hdmi_phy_enable_tmds(struct imx_hdmi *hdmi, u8 enable)
+{
+	hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
+			 HDMI_PHY_CONF0_ENTMDS_OFFSET,
+			 HDMI_PHY_CONF0_ENTMDS_MASK);
+}
+
+static void imx_hdmi_phy_gen2_pddq(struct imx_hdmi *hdmi, u8 enable)
+{
+	hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
+			 HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET,
+			 HDMI_PHY_CONF0_GEN2_PDDQ_MASK);
+}
+
+static void imx_hdmi_phy_gen2_txpwron(struct imx_hdmi *hdmi, u8 enable)
+{
+	hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
+			 HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET,
+			 HDMI_PHY_CONF0_GEN2_TXPWRON_MASK);
+}
+
+static void imx_hdmi_phy_sel_data_en_pol(struct imx_hdmi *hdmi, u8 enable)
+{
+	hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
+			 HDMI_PHY_CONF0_SELDATAENPOL_OFFSET,
+			 HDMI_PHY_CONF0_SELDATAENPOL_MASK);
+}
+
+static void imx_hdmi_phy_sel_interface_control(struct imx_hdmi *hdmi, u8 enable)
+{
+	hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
+			 HDMI_PHY_CONF0_SELDIPIF_OFFSET,
+			 HDMI_PHY_CONF0_SELDIPIF_MASK);
+}
+
+enum {
+	RES_8,
+	RES_10,
+	RES_12,
+	RES_MAX,
+};
+
+struct mpll_config {
+	unsigned long mpixelclock;
+	struct {
+		u16 cpce;
+		u16 gmp;
+	} res[RES_MAX];
+};
+
+static const struct mpll_config mpll_config[] = {
+	{
+		45250000, {
+			{ 0x01e0, 0x0000 },
+			{ 0x21e1, 0x0000 },
+			{ 0x41e2, 0x0000 }
+		},
+	}, {
+		92500000, {
+			{ 0x0140, 0x0005 },
+			{ 0x2141, 0x0005 },
+			{ 0x4142, 0x0005 },
+		},
+	}, {
+		148500000, {
+			{ 0x00a0, 0x000a },
+			{ 0x20a1, 0x000a },
+			{ 0x40a2, 0x000a },
+		},
+	}, {
+		~0UL, {
+			{ 0x00a0, 0x000a },
+			{ 0x2001, 0x000f },
+			{ 0x4002, 0x000f },
+		},
+	}
+};
+
+struct curr_ctrl {
+	unsigned long mpixelclock;
+	u16 curr[RES_MAX];
+};
+
+static const struct curr_ctrl curr_ctrl[] = {
+	/*	pixelclk     bpp8    bpp10   bpp12 */
+	{
+		 54000000, { 0x091c, 0x091c, 0x06dc },
+	}, {
+		 58400000, { 0x091c, 0x06dc, 0x06dc },
+	}, {
+		 72000000, { 0x06dc, 0x06dc, 0x091c },
+	}, {
+		 74250000, { 0x06dc, 0x0b5c, 0x091c },
+	}, {
+		118800000, { 0x091c, 0x091c, 0x06dc },
+	}, {
+		216000000, { 0x06dc, 0x0b5c, 0x091c },
+	}
+};
+
+static int hdmi_phy_configure(struct imx_hdmi *hdmi, unsigned char prep,
+			      unsigned char res, int cscon)
+{
+	unsigned res_idx, i;
+	u8 val, msec;
+
+	if (prep)
+		return -EINVAL;
+
+	switch (res) {
+	case 0:	/* color resolution 0 is 8 bit colour depth */
+	case 8:
+		res_idx = RES_8;
+		break;
+	case 10:
+		res_idx = RES_10;
+		break;
+	case 12:
+		res_idx = RES_12;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	/* Enable csc path */
+	if (cscon)
+		val = HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH;
+	else
+		val = HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS;
+
+	hdmi_writeb(hdmi, val, HDMI_MC_FLOWCTRL);
+
+	/* gen2 tx power off */
+	imx_hdmi_phy_gen2_txpwron(hdmi, 0);
+
+	/* gen2 pddq */
+	imx_hdmi_phy_gen2_pddq(hdmi, 1);
+
+	/* PHY reset */
+	hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_DEASSERT, HDMI_MC_PHYRSTZ);
+	hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_ASSERT, HDMI_MC_PHYRSTZ);
+
+	hdmi_writeb(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST);
+
+	hdmi_phy_test_clear(hdmi, 1);
+	hdmi_writeb(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2,
+			HDMI_PHY_I2CM_SLAVE_ADDR);
+	hdmi_phy_test_clear(hdmi, 0);
+
+	/* PLL/MPLL Cfg - always match on final entry */
+	for (i = 0; i < ARRAY_SIZE(mpll_config) - 1; i++)
+		if (hdmi->hdmi_data.video_mode.mpixelclock <=
+		    mpll_config[i].mpixelclock)
+			break;
+
+	hdmi_phy_i2c_write(hdmi, mpll_config[i].res[res_idx].cpce, 0x06);
+	hdmi_phy_i2c_write(hdmi, mpll_config[i].res[res_idx].gmp, 0x15);
+
+	for (i = 0; i < ARRAY_SIZE(curr_ctrl); i++)
+		if (hdmi->hdmi_data.video_mode.mpixelclock <=
+		    curr_ctrl[i].mpixelclock)
+			break;
+
+	if (i >= ARRAY_SIZE(curr_ctrl)) {
+		dev_err(hdmi->dev,
+				"Pixel clock %d - unsupported by HDMI\n",
+				hdmi->hdmi_data.video_mode.mpixelclock);
+		return -EINVAL;
+	}
+
+	/* CURRCTRL */
+	hdmi_phy_i2c_write(hdmi, curr_ctrl[i].curr[res_idx], 0x10);
+
+	hdmi_phy_i2c_write(hdmi, 0x0000, 0x13);  /* PLLPHBYCTRL */
+	hdmi_phy_i2c_write(hdmi, 0x0006, 0x17);
+	/* RESISTANCE TERM 133Ohm Cfg */
+	hdmi_phy_i2c_write(hdmi, 0x0005, 0x19);  /* TXTERM */
+	/* PREEMP Cgf 0.00 */
+	hdmi_phy_i2c_write(hdmi, 0x800d, 0x09);  /* CKSYMTXCTRL */
+	/* TX/CK LVL 10 */
+	hdmi_phy_i2c_write(hdmi, 0x01ad, 0x0E);  /* VLEVCTRL */
+	/* REMOVE CLK TERM */
+	hdmi_phy_i2c_write(hdmi, 0x8000, 0x05);  /* CKCALCTRL */
+
+	imx_hdmi_phy_enable_power(hdmi, 1);
+
+	/* toggle TMDS enable */
+	imx_hdmi_phy_enable_tmds(hdmi, 0);
+	imx_hdmi_phy_enable_tmds(hdmi, 1);
+
+	/* gen2 tx power on */
+	imx_hdmi_phy_gen2_txpwron(hdmi, 1);
+	imx_hdmi_phy_gen2_pddq(hdmi, 0);
+
+	/*Wait for PHY PLL lock */
+	msec = 5;
+	do {
+		val = hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK;
+		if (!val)
+			break;
+
+		if (msec == 0) {
+			dev_err(hdmi->dev, "PHY PLL not locked\n");
+			return -ETIMEDOUT;
+		}
+
+		udelay(1000);
+		msec--;
+	} while (1);
+
+	return 0;
+}
+
+static int imx_hdmi_phy_init(struct imx_hdmi *hdmi)
+{
+	int i, ret;
+	bool cscon = false;
+
+	/*check csc whether needed activated in HDMI mode */
+	cscon = (is_color_space_conversion(hdmi) &&
+			!hdmi->hdmi_data.video_mode.mdvi);
+
+	/* HDMI Phy spec says to do the phy initialization sequence twice */
+	for (i = 0; i < 2; i++) {
+		imx_hdmi_phy_sel_data_en_pol(hdmi, 1);
+		imx_hdmi_phy_sel_interface_control(hdmi, 0);
+		imx_hdmi_phy_enable_tmds(hdmi, 0);
+		imx_hdmi_phy_enable_power(hdmi, 0);
+
+		/* Enable CSC */
+		ret = hdmi_phy_configure(hdmi, 0, 8, cscon);
+		if (ret)
+			return ret;
+	}
+
+	hdmi->phy_enabled = true;
+	return 0;
+}
+
+static void hdmi_tx_hdcp_config(struct imx_hdmi *hdmi)
+{
+	u8 de;
+
+	if (hdmi->hdmi_data.video_mode.mdataenablepolarity)
+		de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH;
+	else
+		de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_LOW;
+
+	/* disable rx detect */
+	hdmi_modb(hdmi, HDMI_A_HDCPCFG0_RXDETECT_DISABLE,
+		  HDMI_A_HDCPCFG0_RXDETECT_MASK, HDMI_A_HDCPCFG0);
+
+	hdmi_modb(hdmi, de, HDMI_A_VIDPOLCFG_DATAENPOL_MASK, HDMI_A_VIDPOLCFG);
+
+	hdmi_modb(hdmi, HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE,
+		  HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK, HDMI_A_HDCPCFG1);
+}
+
+static void imx_hdmi_phy_disable(struct imx_hdmi *hdmi)
+{
+	if (!hdmi->phy_enabled)
+		return;
+
+	imx_hdmi_phy_enable_tmds(hdmi, 0);
+	imx_hdmi_phy_enable_power(hdmi, 0);
+
+	hdmi->phy_enabled = false;
+}
+
+/* HDMI Initialization Step B.4 */
+static void imx_hdmi_enable_video_path(struct imx_hdmi *hdmi)
+{
+	u8 clkdis;
+
+	/* control period minimum duration */
+	hdmi_writeb(hdmi, 12, HDMI_FC_CTRLDUR);
+	hdmi_writeb(hdmi, 32, HDMI_FC_EXCTRLDUR);
+	hdmi_writeb(hdmi, 1, HDMI_FC_EXCTRLSPAC);
+
+	/* Set to fill TMDS data channels */
+	hdmi_writeb(hdmi, 0x0B, HDMI_FC_CH0PREAM);
+	hdmi_writeb(hdmi, 0x16, HDMI_FC_CH1PREAM);
+	hdmi_writeb(hdmi, 0x21, HDMI_FC_CH2PREAM);
+
+	/* Enable pixel clock and tmds data path */
+	clkdis = 0x7F;
+	clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE;
+	hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
+
+	clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
+	hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
+
+	/* Enable csc path */
+	if (is_color_space_conversion(hdmi)) {
+		clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE;
+		hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
+	}
+}
+
+/* Workaround to clear the overflow condition */
+static void imx_hdmi_clear_overflow(struct imx_hdmi *hdmi)
+{
+	int count;
+	u8 val;
+
+	/* TMDS software reset */
+	hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ);
+
+	val = hdmi_readb(hdmi, HDMI_FC_INVIDCONF);
+	if (hdmi->dev_type == IMX6DL_HDMI) {
+		hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF);
+		return;
+	}
+
+	for (count = 0; count < 4; count++)
+		hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF);
+}
+
+static int imx_hdmi_setup(struct imx_hdmi *hdmi, struct fb_videomode *mode)
+{
+	int ret;
+
+	hdmi->vic = 0;
+
+	dev_dbg(hdmi->dev, "Non-CEA mode used in HDMI\n");
+	hdmi->hdmi_data.video_mode.mdvi = true;
+
+	hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_709;
+	hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0;
+	hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0;
+
+	/* TODO: Get input format from IPU (via FB driver interface) */
+	hdmi->hdmi_data.enc_in_format = RGB;
+
+	hdmi->hdmi_data.enc_out_format = RGB;
+
+	hdmi->hdmi_data.enc_color_depth = 8;
+	hdmi->hdmi_data.pix_repet_factor = 0;
+	hdmi->hdmi_data.hdcp_enable = 0;
+	hdmi->hdmi_data.video_mode.mdataenablepolarity = true;
+
+	/* HDMI Initializateion Step B.2 */
+	ret = imx_hdmi_phy_init(hdmi);
+	if (ret)
+		return ret;
+
+	/* HDMI Initialization Step B.3 */
+	imx_hdmi_enable_video_path(hdmi);
+
+	/* not for DVI mode */
+	dev_dbg(hdmi->dev, "%s DVI mode\n", __func__);
+
+	hdmi_video_packetize(hdmi);
+	hdmi_video_csc(hdmi);
+	hdmi_video_sample(hdmi);
+	hdmi_tx_hdcp_config(hdmi);
+
+	imx_hdmi_clear_overflow(hdmi);
+
+	return 0;
+}
+
+static void initialize_hdmi_ih_mutes(struct imx_hdmi *hdmi)
+{
+	u8 ih_mute;
+
+	/*
+	 * Boot up defaults are:
+	 * HDMI_IH_MUTE   = 0x03 (disabled)
+	 * HDMI_IH_MUTE_* = 0x00 (enabled)
+	 *
+	 * Disable top level interrupt bits in HDMI block
+	 */
+	ih_mute = hdmi_readb(hdmi, HDMI_IH_MUTE) |
+		  HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
+		  HDMI_IH_MUTE_MUTE_ALL_INTERRUPT;
+
+	hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
+
+	/* by default mask all interrupts */
+	hdmi_writeb(hdmi, 0xff, HDMI_VP_MASK);
+	hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK0);
+	hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK1);
+	hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK2);
+	hdmi_writeb(hdmi, 0xff, HDMI_PHY_MASK0);
+	hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_INT_ADDR);
+	hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_CTLINT_ADDR);
+	hdmi_writeb(hdmi, 0xff, HDMI_AUD_INT);
+	hdmi_writeb(hdmi, 0xff, HDMI_AUD_SPDIFINT);
+	hdmi_writeb(hdmi, 0xff, HDMI_AUD_HBR_MASK);
+	hdmi_writeb(hdmi, 0xff, HDMI_GP_MASK);
+	hdmi_writeb(hdmi, 0xff, HDMI_A_APIINTMSK);
+	hdmi_writeb(hdmi, 0xff, HDMI_CEC_MASK);
+	hdmi_writeb(hdmi, 0xff, HDMI_I2CM_INT);
+	hdmi_writeb(hdmi, 0xff, HDMI_I2CM_CTLINT);
+
+	/* Disable interrupts in the IH_MUTE_* registers */
+	hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT0);
+	hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT1);
+	hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT2);
+	hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AS_STAT0);
+	hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_PHY_STAT0);
+	hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CM_STAT0);
+	hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_CEC_STAT0);
+	hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_VP_STAT0);
+	hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CMPHY_STAT0);
+	hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AHBDMAAUD_STAT0);
+
+	/* Enable top level interrupt bits in HDMI block */
+	ih_mute &= ~(HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
+		    HDMI_IH_MUTE_MUTE_ALL_INTERRUPT);
+	hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
+}
+
+struct imx_hdmi_data {
+	unsigned ipu_mask;
+	enum imx_hdmi_devtype devtype;
+};
+
+static struct imx_hdmi_data imx6q_hdmi_data = {
+	.ipu_mask = 0xf,
+	.devtype = IMX6Q_HDMI,
+};
+
+static struct imx_hdmi_data imx6dl_hdmi_data = {
+	.ipu_mask = 0x3,
+	.devtype = IMX6DL_HDMI,
+};
+
+static struct of_device_id imx_hdmi_dt_ids[] = {
+	{
+		.compatible = "fsl,imx6q-hdmi",
+		.data = (unsigned long)&imx6q_hdmi_data,
+	}, {
+		.compatible = "fsl,imx6dl-hdmi",
+		.data = (unsigned long)&imx6dl_hdmi_data,
+	}, {
+		/* sentinel */
+	}
+};
+
+static int imx_hdmi_prepare(struct ipu_output *output, struct fb_videomode *mode, int di)
+{
+	struct imx_hdmi *hdmi = container_of(output, struct imx_hdmi, output);
+
+	imx_hdmi_set_ipu_di_mux(hdmi, di);
+
+	return 0;
+}
+
+static int imx_hdmi_commit(struct ipu_output *output, struct fb_videomode *mode, int di)
+{
+	struct imx_hdmi *hdmi = container_of(output, struct imx_hdmi, output);
+
+	imx_hdmi_setup(hdmi, mode);
+
+	return 0;
+}
+
+static int imx_hdmi_disable(struct ipu_output *output)
+{
+	struct imx_hdmi *hdmi = container_of(output, struct imx_hdmi, output);
+
+	imx_hdmi_phy_disable(hdmi);
+
+	return 0;
+}
+
+static struct ipu_output_ops imx_hdmi_ops = {
+	.prepare = imx_hdmi_prepare,
+	.enable = imx_hdmi_commit,
+	.disable = imx_hdmi_disable,
+};
+
+static int imx_hdmi_probe(struct device_d *dev)
+{
+	struct device_node *np = dev->device_node;
+	struct device_node *ddc_node;
+	struct imx_hdmi *hdmi;
+	int ret;
+	const struct imx_hdmi_data *devtype;
+
+	ret = dev_get_drvdata(dev, (unsigned long *)&devtype);
+	if (ret)
+		return ret;
+
+	hdmi = xzalloc(sizeof(*hdmi));
+
+	hdmi->dev = dev;
+	hdmi->connected = 0;
+	hdmi->sample_rate = 48000;
+	hdmi->ratio = 100;
+
+	ret = dev_get_drvdata(dev, (unsigned long *)&hdmi->dev_type);
+	if (ret)
+		return ret;
+
+	ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0);
+	if (ddc_node) {
+		hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node);
+		if (!hdmi->ddc)
+			dev_dbg(hdmi->dev, "failed to read ddc node\n");
+	} else {
+		dev_dbg(hdmi->dev, "no ddc property found\n");
+	}
+
+	ddc_node = NULL;
+
+	hdmi->regs = dev_request_mem_region(dev, 0);
+	if (!hdmi->regs)
+		return -EBUSY;
+
+	hdmi->isfr_clk = clk_get(hdmi->dev, "isfr");
+	if (IS_ERR(hdmi->isfr_clk)) {
+		ret = PTR_ERR(hdmi->isfr_clk);
+		dev_err(dev,
+			"Unable to get HDMI isfr clk: %d\n", ret);
+		return ret;
+	}
+
+	ret = clk_enable(hdmi->isfr_clk);
+	if (ret)
+		return ret;
+
+	hdmi->iahb_clk = clk_get(hdmi->dev, "iahb");
+	if (IS_ERR(hdmi->iahb_clk)) {
+		ret = PTR_ERR(hdmi->iahb_clk);
+		dev_err(dev,
+			"Unable to get HDMI iahb clk: %d\n", ret);
+		goto err_isfr;
+	}
+
+	ret = clk_enable(hdmi->iahb_clk);
+	if (ret)
+		goto err_isfr;
+
+	/* Product and revision IDs */
+	dev_info(dev,
+		"Detected HDMI controller 0x%x:0x%x:0x%x:0x%x\n",
+		hdmi_readb(hdmi, HDMI_DESIGN_ID),
+		hdmi_readb(hdmi, HDMI_REVISION_ID),
+		hdmi_readb(hdmi, HDMI_PRODUCT_ID0),
+		hdmi_readb(hdmi, HDMI_PRODUCT_ID1));
+
+	initialize_hdmi_ih_mutes(hdmi);
+
+	/*
+	 * To prevent overflows in HDMI_IH_FC_STAT2, set the clk regenerator
+	 * N and cts values before enabling phy
+	 */
+	hdmi_init_clk_regenerator(hdmi);
+
+	/*
+	 * Configure registers related to HDMI interrupt
+	 * generation before registering IRQ.
+	 */
+	hdmi_writeb(hdmi, HDMI_PHY_HPD, HDMI_PHY_POL0);
+
+	/* Clear Hotplug interrupts */
+	hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD, HDMI_IH_PHY_STAT0);
+
+	hdmi_writeb(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL,
+		    HDMI_PHY_I2CM_INT_ADDR);
+
+	hdmi_writeb(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL |
+		    HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL,
+		    HDMI_PHY_I2CM_CTLINT_ADDR);
+
+	/* enable cable hot plug irq */
+	hdmi_writeb(hdmi, (u8)~HDMI_PHY_HPD, HDMI_PHY_MASK0);
+
+	/* Unmute interrupts */
+	hdmi_writeb(hdmi, ~HDMI_IH_PHY_STAT0_HPD, HDMI_IH_MUTE_PHY_STAT0);
+
+	hdmi->output.ops = &imx_hdmi_ops;
+	hdmi->output.di_clkflags = IPU_DI_CLKMODE_EXT | IPU_DI_CLKMODE_SYNC;
+	hdmi->output.out_pixel_fmt = V4L2_PIX_FMT_RGB24;
+	hdmi->output.name = asprintf("hdmi-0");
+	hdmi->output.ipu_mask = devtype->ipu_mask;
+	hdmi->output.edid_i2c_adapter = hdmi->ddc;
+	hdmi->output.modes = of_get_display_timings(np);
+
+	ipu_register_output(&hdmi->output);
+
+	return 0;
+
+err_isfr:
+	clk_disable(hdmi->isfr_clk);
+
+	return ret;
+}
+
+static struct driver_d imx_hdmi_driver = {
+	.probe		= imx_hdmi_probe,
+	.of_compatible	= imx_hdmi_dt_ids,
+	.name		= "imx-hdmi",
+};
+device_platform_driver(imx_hdmi_driver);
+
+MODULE_AUTHOR("Sascha Hauer <s.hauer at pengutronix.de>");
+MODULE_DESCRIPTION("i.MX6 HDMI transmitter driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/video/imx-ipu-v3/imx-hdmi.h b/drivers/video/imx-ipu-v3/imx-hdmi.h
new file mode 100644
index 0000000..39b6776
--- /dev/null
+++ b/drivers/video/imx-ipu-v3/imx-hdmi.h
@@ -0,0 +1,1032 @@
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __IMX_HDMI_H__
+#define __IMX_HDMI_H__
+
+/* Identification Registers */
+#define HDMI_DESIGN_ID                          0x0000
+#define HDMI_REVISION_ID                        0x0001
+#define HDMI_PRODUCT_ID0                        0x0002
+#define HDMI_PRODUCT_ID1                        0x0003
+#define HDMI_CONFIG0_ID                         0x0004
+#define HDMI_CONFIG1_ID                         0x0005
+#define HDMI_CONFIG2_ID                         0x0006
+#define HDMI_CONFIG3_ID                         0x0007
+
+/* Interrupt Registers */
+#define HDMI_IH_FC_STAT0                        0x0100
+#define HDMI_IH_FC_STAT1                        0x0101
+#define HDMI_IH_FC_STAT2                        0x0102
+#define HDMI_IH_AS_STAT0                        0x0103
+#define HDMI_IH_PHY_STAT0                       0x0104
+#define HDMI_IH_I2CM_STAT0                      0x0105
+#define HDMI_IH_CEC_STAT0                       0x0106
+#define HDMI_IH_VP_STAT0                        0x0107
+#define HDMI_IH_I2CMPHY_STAT0                   0x0108
+#define HDMI_IH_AHBDMAAUD_STAT0                 0x0109
+
+#define HDMI_IH_MUTE_FC_STAT0                   0x0180
+#define HDMI_IH_MUTE_FC_STAT1                   0x0181
+#define HDMI_IH_MUTE_FC_STAT2                   0x0182
+#define HDMI_IH_MUTE_AS_STAT0                   0x0183
+#define HDMI_IH_MUTE_PHY_STAT0                  0x0184
+#define HDMI_IH_MUTE_I2CM_STAT0                 0x0185
+#define HDMI_IH_MUTE_CEC_STAT0                  0x0186
+#define HDMI_IH_MUTE_VP_STAT0                   0x0187
+#define HDMI_IH_MUTE_I2CMPHY_STAT0              0x0188
+#define HDMI_IH_MUTE_AHBDMAAUD_STAT0            0x0189
+#define HDMI_IH_MUTE                            0x01FF
+
+/* Video Sample Registers */
+#define HDMI_TX_INVID0                          0x0200
+#define HDMI_TX_INSTUFFING                      0x0201
+#define HDMI_TX_GYDATA0                         0x0202
+#define HDMI_TX_GYDATA1                         0x0203
+#define HDMI_TX_RCRDATA0                        0x0204
+#define HDMI_TX_RCRDATA1                        0x0205
+#define HDMI_TX_BCBDATA0                        0x0206
+#define HDMI_TX_BCBDATA1                        0x0207
+
+/* Video Packetizer Registers */
+#define HDMI_VP_STATUS                          0x0800
+#define HDMI_VP_PR_CD                           0x0801
+#define HDMI_VP_STUFF                           0x0802
+#define HDMI_VP_REMAP                           0x0803
+#define HDMI_VP_CONF                            0x0804
+#define HDMI_VP_STAT                            0x0805
+#define HDMI_VP_INT                             0x0806
+#define HDMI_VP_MASK                            0x0807
+#define HDMI_VP_POL                             0x0808
+
+/* Frame Composer Registers */
+#define HDMI_FC_INVIDCONF                       0x1000
+#define HDMI_FC_INHACTV0                        0x1001
+#define HDMI_FC_INHACTV1                        0x1002
+#define HDMI_FC_INHBLANK0                       0x1003
+#define HDMI_FC_INHBLANK1                       0x1004
+#define HDMI_FC_INVACTV0                        0x1005
+#define HDMI_FC_INVACTV1                        0x1006
+#define HDMI_FC_INVBLANK                        0x1007
+#define HDMI_FC_HSYNCINDELAY0                   0x1008
+#define HDMI_FC_HSYNCINDELAY1                   0x1009
+#define HDMI_FC_HSYNCINWIDTH0                   0x100A
+#define HDMI_FC_HSYNCINWIDTH1                   0x100B
+#define HDMI_FC_VSYNCINDELAY                    0x100C
+#define HDMI_FC_VSYNCINWIDTH                    0x100D
+#define HDMI_FC_INFREQ0                         0x100E
+#define HDMI_FC_INFREQ1                         0x100F
+#define HDMI_FC_INFREQ2                         0x1010
+#define HDMI_FC_CTRLDUR                         0x1011
+#define HDMI_FC_EXCTRLDUR                       0x1012
+#define HDMI_FC_EXCTRLSPAC                      0x1013
+#define HDMI_FC_CH0PREAM                        0x1014
+#define HDMI_FC_CH1PREAM                        0x1015
+#define HDMI_FC_CH2PREAM                        0x1016
+#define HDMI_FC_AVICONF3                        0x1017
+#define HDMI_FC_GCP                             0x1018
+#define HDMI_FC_AVICONF0                        0x1019
+#define HDMI_FC_AVICONF1                        0x101A
+#define HDMI_FC_AVICONF2                        0x101B
+#define HDMI_FC_AVIVID                          0x101C
+#define HDMI_FC_AVIETB0                         0x101D
+#define HDMI_FC_AVIETB1                         0x101E
+#define HDMI_FC_AVISBB0                         0x101F
+#define HDMI_FC_AVISBB1                         0x1020
+#define HDMI_FC_AVIELB0                         0x1021
+#define HDMI_FC_AVIELB1                         0x1022
+#define HDMI_FC_AVISRB0                         0x1023
+#define HDMI_FC_AVISRB1                         0x1024
+#define HDMI_FC_AUDICONF0                       0x1025
+#define HDMI_FC_AUDICONF1                       0x1026
+#define HDMI_FC_AUDICONF2                       0x1027
+#define HDMI_FC_AUDICONF3                       0x1028
+#define HDMI_FC_VSDIEEEID0                      0x1029
+#define HDMI_FC_VSDSIZE                         0x102A
+#define HDMI_FC_VSDIEEEID1                      0x1030
+#define HDMI_FC_VSDIEEEID2                      0x1031
+#define HDMI_FC_VSDPAYLOAD0                     0x1032
+#define HDMI_FC_VSDPAYLOAD1                     0x1033
+#define HDMI_FC_VSDPAYLOAD2                     0x1034
+#define HDMI_FC_VSDPAYLOAD3                     0x1035
+#define HDMI_FC_VSDPAYLOAD4                     0x1036
+#define HDMI_FC_VSDPAYLOAD5                     0x1037
+#define HDMI_FC_VSDPAYLOAD6                     0x1038
+#define HDMI_FC_VSDPAYLOAD7                     0x1039
+#define HDMI_FC_VSDPAYLOAD8                     0x103A
+#define HDMI_FC_VSDPAYLOAD9                     0x103B
+#define HDMI_FC_VSDPAYLOAD10                    0x103C
+#define HDMI_FC_VSDPAYLOAD11                    0x103D
+#define HDMI_FC_VSDPAYLOAD12                    0x103E
+#define HDMI_FC_VSDPAYLOAD13                    0x103F
+#define HDMI_FC_VSDPAYLOAD14                    0x1040
+#define HDMI_FC_VSDPAYLOAD15                    0x1041
+#define HDMI_FC_VSDPAYLOAD16                    0x1042
+#define HDMI_FC_VSDPAYLOAD17                    0x1043
+#define HDMI_FC_VSDPAYLOAD18                    0x1044
+#define HDMI_FC_VSDPAYLOAD19                    0x1045
+#define HDMI_FC_VSDPAYLOAD20                    0x1046
+#define HDMI_FC_VSDPAYLOAD21                    0x1047
+#define HDMI_FC_VSDPAYLOAD22                    0x1048
+#define HDMI_FC_VSDPAYLOAD23                    0x1049
+#define HDMI_FC_SPDVENDORNAME0                  0x104A
+#define HDMI_FC_SPDVENDORNAME1                  0x104B
+#define HDMI_FC_SPDVENDORNAME2                  0x104C
+#define HDMI_FC_SPDVENDORNAME3                  0x104D
+#define HDMI_FC_SPDVENDORNAME4                  0x104E
+#define HDMI_FC_SPDVENDORNAME5                  0x104F
+#define HDMI_FC_SPDVENDORNAME6                  0x1050
+#define HDMI_FC_SPDVENDORNAME7                  0x1051
+#define HDMI_FC_SDPPRODUCTNAME0                 0x1052
+#define HDMI_FC_SDPPRODUCTNAME1                 0x1053
+#define HDMI_FC_SDPPRODUCTNAME2                 0x1054
+#define HDMI_FC_SDPPRODUCTNAME3                 0x1055
+#define HDMI_FC_SDPPRODUCTNAME4                 0x1056
+#define HDMI_FC_SDPPRODUCTNAME5                 0x1057
+#define HDMI_FC_SDPPRODUCTNAME6                 0x1058
+#define HDMI_FC_SDPPRODUCTNAME7                 0x1059
+#define HDMI_FC_SDPPRODUCTNAME8                 0x105A
+#define HDMI_FC_SDPPRODUCTNAME9                 0x105B
+#define HDMI_FC_SDPPRODUCTNAME10                0x105C
+#define HDMI_FC_SDPPRODUCTNAME11                0x105D
+#define HDMI_FC_SDPPRODUCTNAME12                0x105E
+#define HDMI_FC_SDPPRODUCTNAME13                0x105F
+#define HDMI_FC_SDPPRODUCTNAME14                0x1060
+#define HDMI_FC_SPDPRODUCTNAME15                0x1061
+#define HDMI_FC_SPDDEVICEINF                    0x1062
+#define HDMI_FC_AUDSCONF                        0x1063
+#define HDMI_FC_AUDSSTAT                        0x1064
+#define HDMI_FC_DATACH0FILL                     0x1070
+#define HDMI_FC_DATACH1FILL                     0x1071
+#define HDMI_FC_DATACH2FILL                     0x1072
+#define HDMI_FC_CTRLQHIGH                       0x1073
+#define HDMI_FC_CTRLQLOW                        0x1074
+#define HDMI_FC_ACP0                            0x1075
+#define HDMI_FC_ACP28                           0x1076
+#define HDMI_FC_ACP27                           0x1077
+#define HDMI_FC_ACP26                           0x1078
+#define HDMI_FC_ACP25                           0x1079
+#define HDMI_FC_ACP24                           0x107A
+#define HDMI_FC_ACP23                           0x107B
+#define HDMI_FC_ACP22                           0x107C
+#define HDMI_FC_ACP21                           0x107D
+#define HDMI_FC_ACP20                           0x107E
+#define HDMI_FC_ACP19                           0x107F
+#define HDMI_FC_ACP18                           0x1080
+#define HDMI_FC_ACP17                           0x1081
+#define HDMI_FC_ACP16                           0x1082
+#define HDMI_FC_ACP15                           0x1083
+#define HDMI_FC_ACP14                           0x1084
+#define HDMI_FC_ACP13                           0x1085
+#define HDMI_FC_ACP12                           0x1086
+#define HDMI_FC_ACP11                           0x1087
+#define HDMI_FC_ACP10                           0x1088
+#define HDMI_FC_ACP9                            0x1089
+#define HDMI_FC_ACP8                            0x108A
+#define HDMI_FC_ACP7                            0x108B
+#define HDMI_FC_ACP6                            0x108C
+#define HDMI_FC_ACP5                            0x108D
+#define HDMI_FC_ACP4                            0x108E
+#define HDMI_FC_ACP3                            0x108F
+#define HDMI_FC_ACP2                            0x1090
+#define HDMI_FC_ACP1                            0x1091
+#define HDMI_FC_ISCR1_0                         0x1092
+#define HDMI_FC_ISCR1_16                        0x1093
+#define HDMI_FC_ISCR1_15                        0x1094
+#define HDMI_FC_ISCR1_14                        0x1095
+#define HDMI_FC_ISCR1_13                        0x1096
+#define HDMI_FC_ISCR1_12                        0x1097
+#define HDMI_FC_ISCR1_11                        0x1098
+#define HDMI_FC_ISCR1_10                        0x1099
+#define HDMI_FC_ISCR1_9                         0x109A
+#define HDMI_FC_ISCR1_8                         0x109B
+#define HDMI_FC_ISCR1_7                         0x109C
+#define HDMI_FC_ISCR1_6                         0x109D
+#define HDMI_FC_ISCR1_5                         0x109E
+#define HDMI_FC_ISCR1_4                         0x109F
+#define HDMI_FC_ISCR1_3                         0x10A0
+#define HDMI_FC_ISCR1_2                         0x10A1
+#define HDMI_FC_ISCR1_1                         0x10A2
+#define HDMI_FC_ISCR2_15                        0x10A3
+#define HDMI_FC_ISCR2_14                        0x10A4
+#define HDMI_FC_ISCR2_13                        0x10A5
+#define HDMI_FC_ISCR2_12                        0x10A6
+#define HDMI_FC_ISCR2_11                        0x10A7
+#define HDMI_FC_ISCR2_10                        0x10A8
+#define HDMI_FC_ISCR2_9                         0x10A9
+#define HDMI_FC_ISCR2_8                         0x10AA
+#define HDMI_FC_ISCR2_7                         0x10AB
+#define HDMI_FC_ISCR2_6                         0x10AC
+#define HDMI_FC_ISCR2_5                         0x10AD
+#define HDMI_FC_ISCR2_4                         0x10AE
+#define HDMI_FC_ISCR2_3                         0x10AF
+#define HDMI_FC_ISCR2_2                         0x10B0
+#define HDMI_FC_ISCR2_1                         0x10B1
+#define HDMI_FC_ISCR2_0                         0x10B2
+#define HDMI_FC_DATAUTO0                        0x10B3
+#define HDMI_FC_DATAUTO1                        0x10B4
+#define HDMI_FC_DATAUTO2                        0x10B5
+#define HDMI_FC_DATMAN                          0x10B6
+#define HDMI_FC_DATAUTO3                        0x10B7
+#define HDMI_FC_RDRB0                           0x10B8
+#define HDMI_FC_RDRB1                           0x10B9
+#define HDMI_FC_RDRB2                           0x10BA
+#define HDMI_FC_RDRB3                           0x10BB
+#define HDMI_FC_RDRB4                           0x10BC
+#define HDMI_FC_RDRB5                           0x10BD
+#define HDMI_FC_RDRB6                           0x10BE
+#define HDMI_FC_RDRB7                           0x10BF
+#define HDMI_FC_STAT0                           0x10D0
+#define HDMI_FC_INT0                            0x10D1
+#define HDMI_FC_MASK0                           0x10D2
+#define HDMI_FC_POL0                            0x10D3
+#define HDMI_FC_STAT1                           0x10D4
+#define HDMI_FC_INT1                            0x10D5
+#define HDMI_FC_MASK1                           0x10D6
+#define HDMI_FC_POL1                            0x10D7
+#define HDMI_FC_STAT2                           0x10D8
+#define HDMI_FC_INT2                            0x10D9
+#define HDMI_FC_MASK2                           0x10DA
+#define HDMI_FC_POL2                            0x10DB
+#define HDMI_FC_PRCONF                          0x10E0
+
+#define HDMI_FC_GMD_STAT                        0x1100
+#define HDMI_FC_GMD_EN                          0x1101
+#define HDMI_FC_GMD_UP                          0x1102
+#define HDMI_FC_GMD_CONF                        0x1103
+#define HDMI_FC_GMD_HB                          0x1104
+#define HDMI_FC_GMD_PB0                         0x1105
+#define HDMI_FC_GMD_PB1                         0x1106
+#define HDMI_FC_GMD_PB2                         0x1107
+#define HDMI_FC_GMD_PB3                         0x1108
+#define HDMI_FC_GMD_PB4                         0x1109
+#define HDMI_FC_GMD_PB5                         0x110A
+#define HDMI_FC_GMD_PB6                         0x110B
+#define HDMI_FC_GMD_PB7                         0x110C
+#define HDMI_FC_GMD_PB8                         0x110D
+#define HDMI_FC_GMD_PB9                         0x110E
+#define HDMI_FC_GMD_PB10                        0x110F
+#define HDMI_FC_GMD_PB11                        0x1110
+#define HDMI_FC_GMD_PB12                        0x1111
+#define HDMI_FC_GMD_PB13                        0x1112
+#define HDMI_FC_GMD_PB14                        0x1113
+#define HDMI_FC_GMD_PB15                        0x1114
+#define HDMI_FC_GMD_PB16                        0x1115
+#define HDMI_FC_GMD_PB17                        0x1116
+#define HDMI_FC_GMD_PB18                        0x1117
+#define HDMI_FC_GMD_PB19                        0x1118
+#define HDMI_FC_GMD_PB20                        0x1119
+#define HDMI_FC_GMD_PB21                        0x111A
+#define HDMI_FC_GMD_PB22                        0x111B
+#define HDMI_FC_GMD_PB23                        0x111C
+#define HDMI_FC_GMD_PB24                        0x111D
+#define HDMI_FC_GMD_PB25                        0x111E
+#define HDMI_FC_GMD_PB26                        0x111F
+#define HDMI_FC_GMD_PB27                        0x1120
+
+#define HDMI_FC_DBGFORCE                        0x1200
+#define HDMI_FC_DBGAUD0CH0                      0x1201
+#define HDMI_FC_DBGAUD1CH0                      0x1202
+#define HDMI_FC_DBGAUD2CH0                      0x1203
+#define HDMI_FC_DBGAUD0CH1                      0x1204
+#define HDMI_FC_DBGAUD1CH1                      0x1205
+#define HDMI_FC_DBGAUD2CH1                      0x1206
+#define HDMI_FC_DBGAUD0CH2                      0x1207
+#define HDMI_FC_DBGAUD1CH2                      0x1208
+#define HDMI_FC_DBGAUD2CH2                      0x1209
+#define HDMI_FC_DBGAUD0CH3                      0x120A
+#define HDMI_FC_DBGAUD1CH3                      0x120B
+#define HDMI_FC_DBGAUD2CH3                      0x120C
+#define HDMI_FC_DBGAUD0CH4                      0x120D
+#define HDMI_FC_DBGAUD1CH4                      0x120E
+#define HDMI_FC_DBGAUD2CH4                      0x120F
+#define HDMI_FC_DBGAUD0CH5                      0x1210
+#define HDMI_FC_DBGAUD1CH5                      0x1211
+#define HDMI_FC_DBGAUD2CH5                      0x1212
+#define HDMI_FC_DBGAUD0CH6                      0x1213
+#define HDMI_FC_DBGAUD1CH6                      0x1214
+#define HDMI_FC_DBGAUD2CH6                      0x1215
+#define HDMI_FC_DBGAUD0CH7                      0x1216
+#define HDMI_FC_DBGAUD1CH7                      0x1217
+#define HDMI_FC_DBGAUD2CH7                      0x1218
+#define HDMI_FC_DBGTMDS0                        0x1219
+#define HDMI_FC_DBGTMDS1                        0x121A
+#define HDMI_FC_DBGTMDS2                        0x121B
+
+/* HDMI Source PHY Registers */
+#define HDMI_PHY_CONF0                          0x3000
+#define HDMI_PHY_TST0                           0x3001
+#define HDMI_PHY_TST1                           0x3002
+#define HDMI_PHY_TST2                           0x3003
+#define HDMI_PHY_STAT0                          0x3004
+#define HDMI_PHY_INT0                           0x3005
+#define HDMI_PHY_MASK0                          0x3006
+#define HDMI_PHY_POL0                           0x3007
+
+/* HDMI Master PHY Registers */
+#define HDMI_PHY_I2CM_SLAVE_ADDR                0x3020
+#define HDMI_PHY_I2CM_ADDRESS_ADDR              0x3021
+#define HDMI_PHY_I2CM_DATAO_1_ADDR              0x3022
+#define HDMI_PHY_I2CM_DATAO_0_ADDR              0x3023
+#define HDMI_PHY_I2CM_DATAI_1_ADDR              0x3024
+#define HDMI_PHY_I2CM_DATAI_0_ADDR              0x3025
+#define HDMI_PHY_I2CM_OPERATION_ADDR            0x3026
+#define HDMI_PHY_I2CM_INT_ADDR                  0x3027
+#define HDMI_PHY_I2CM_CTLINT_ADDR               0x3028
+#define HDMI_PHY_I2CM_DIV_ADDR                  0x3029
+#define HDMI_PHY_I2CM_SOFTRSTZ_ADDR             0x302a
+#define HDMI_PHY_I2CM_SS_SCL_HCNT_1_ADDR        0x302b
+#define HDMI_PHY_I2CM_SS_SCL_HCNT_0_ADDR        0x302c
+#define HDMI_PHY_I2CM_SS_SCL_LCNT_1_ADDR        0x302d
+#define HDMI_PHY_I2CM_SS_SCL_LCNT_0_ADDR        0x302e
+#define HDMI_PHY_I2CM_FS_SCL_HCNT_1_ADDR        0x302f
+#define HDMI_PHY_I2CM_FS_SCL_HCNT_0_ADDR        0x3030
+#define HDMI_PHY_I2CM_FS_SCL_LCNT_1_ADDR        0x3031
+#define HDMI_PHY_I2CM_FS_SCL_LCNT_0_ADDR        0x3032
+
+/* Audio Sampler Registers */
+#define HDMI_AUD_CONF0                          0x3100
+#define HDMI_AUD_CONF1                          0x3101
+#define HDMI_AUD_INT                            0x3102
+#define HDMI_AUD_CONF2                          0x3103
+#define HDMI_AUD_N1                             0x3200
+#define HDMI_AUD_N2                             0x3201
+#define HDMI_AUD_N3                             0x3202
+#define HDMI_AUD_CTS1                           0x3203
+#define HDMI_AUD_CTS2                           0x3204
+#define HDMI_AUD_CTS3                           0x3205
+#define HDMI_AUD_INPUTCLKFS                     0x3206
+#define HDMI_AUD_SPDIFINT			0x3302
+#define HDMI_AUD_CONF0_HBR                      0x3400
+#define HDMI_AUD_HBR_STATUS                     0x3401
+#define HDMI_AUD_HBR_INT                        0x3402
+#define HDMI_AUD_HBR_POL                        0x3403
+#define HDMI_AUD_HBR_MASK                       0x3404
+
+/*
+ * Generic Parallel Audio Interface Registers
+ * Not used as GPAUD interface is not enabled in hw
+ */
+#define HDMI_GP_CONF0                           0x3500
+#define HDMI_GP_CONF1                           0x3501
+#define HDMI_GP_CONF2                           0x3502
+#define HDMI_GP_STAT                            0x3503
+#define HDMI_GP_INT                             0x3504
+#define HDMI_GP_MASK                            0x3505
+#define HDMI_GP_POL                             0x3506
+
+/* Audio DMA Registers */
+#define HDMI_AHB_DMA_CONF0                      0x3600
+#define HDMI_AHB_DMA_START                      0x3601
+#define HDMI_AHB_DMA_STOP                       0x3602
+#define HDMI_AHB_DMA_THRSLD                     0x3603
+#define HDMI_AHB_DMA_STRADDR0                   0x3604
+#define HDMI_AHB_DMA_STRADDR1                   0x3605
+#define HDMI_AHB_DMA_STRADDR2                   0x3606
+#define HDMI_AHB_DMA_STRADDR3                   0x3607
+#define HDMI_AHB_DMA_STPADDR0                   0x3608
+#define HDMI_AHB_DMA_STPADDR1                   0x3609
+#define HDMI_AHB_DMA_STPADDR2                   0x360a
+#define HDMI_AHB_DMA_STPADDR3                   0x360b
+#define HDMI_AHB_DMA_BSTADDR0                   0x360c
+#define HDMI_AHB_DMA_BSTADDR1                   0x360d
+#define HDMI_AHB_DMA_BSTADDR2                   0x360e
+#define HDMI_AHB_DMA_BSTADDR3                   0x360f
+#define HDMI_AHB_DMA_MBLENGTH0                  0x3610
+#define HDMI_AHB_DMA_MBLENGTH1                  0x3611
+#define HDMI_AHB_DMA_STAT                       0x3612
+#define HDMI_AHB_DMA_INT                        0x3613
+#define HDMI_AHB_DMA_MASK                       0x3614
+#define HDMI_AHB_DMA_POL                        0x3615
+#define HDMI_AHB_DMA_CONF1                      0x3616
+#define HDMI_AHB_DMA_BUFFSTAT                   0x3617
+#define HDMI_AHB_DMA_BUFFINT                    0x3618
+#define HDMI_AHB_DMA_BUFFMASK                   0x3619
+#define HDMI_AHB_DMA_BUFFPOL                    0x361a
+
+/* Main Controller Registers */
+#define HDMI_MC_SFRDIV                          0x4000
+#define HDMI_MC_CLKDIS                          0x4001
+#define HDMI_MC_SWRSTZ                          0x4002
+#define HDMI_MC_OPCTRL                          0x4003
+#define HDMI_MC_FLOWCTRL                        0x4004
+#define HDMI_MC_PHYRSTZ                         0x4005
+#define HDMI_MC_LOCKONCLOCK                     0x4006
+#define HDMI_MC_HEACPHY_RST                     0x4007
+
+/* Color Space  Converter Registers */
+#define HDMI_CSC_CFG                            0x4100
+#define HDMI_CSC_SCALE                          0x4101
+#define HDMI_CSC_COEF_A1_MSB                    0x4102
+#define HDMI_CSC_COEF_A1_LSB                    0x4103
+#define HDMI_CSC_COEF_A2_MSB                    0x4104
+#define HDMI_CSC_COEF_A2_LSB                    0x4105
+#define HDMI_CSC_COEF_A3_MSB                    0x4106
+#define HDMI_CSC_COEF_A3_LSB                    0x4107
+#define HDMI_CSC_COEF_A4_MSB                    0x4108
+#define HDMI_CSC_COEF_A4_LSB                    0x4109
+#define HDMI_CSC_COEF_B1_MSB                    0x410A
+#define HDMI_CSC_COEF_B1_LSB                    0x410B
+#define HDMI_CSC_COEF_B2_MSB                    0x410C
+#define HDMI_CSC_COEF_B2_LSB                    0x410D
+#define HDMI_CSC_COEF_B3_MSB                    0x410E
+#define HDMI_CSC_COEF_B3_LSB                    0x410F
+#define HDMI_CSC_COEF_B4_MSB                    0x4110
+#define HDMI_CSC_COEF_B4_LSB                    0x4111
+#define HDMI_CSC_COEF_C1_MSB                    0x4112
+#define HDMI_CSC_COEF_C1_LSB                    0x4113
+#define HDMI_CSC_COEF_C2_MSB                    0x4114
+#define HDMI_CSC_COEF_C2_LSB                    0x4115
+#define HDMI_CSC_COEF_C3_MSB                    0x4116
+#define HDMI_CSC_COEF_C3_LSB                    0x4117
+#define HDMI_CSC_COEF_C4_MSB                    0x4118
+#define HDMI_CSC_COEF_C4_LSB                    0x4119
+
+/* HDCP Encryption Engine Registers */
+#define HDMI_A_HDCPCFG0                         0x5000
+#define HDMI_A_HDCPCFG1                         0x5001
+#define HDMI_A_HDCPOBS0                         0x5002
+#define HDMI_A_HDCPOBS1                         0x5003
+#define HDMI_A_HDCPOBS2                         0x5004
+#define HDMI_A_HDCPOBS3                         0x5005
+#define HDMI_A_APIINTCLR                        0x5006
+#define HDMI_A_APIINTSTAT                       0x5007
+#define HDMI_A_APIINTMSK                        0x5008
+#define HDMI_A_VIDPOLCFG                        0x5009
+#define HDMI_A_OESSWCFG                         0x500A
+#define HDMI_A_TIMER1SETUP0                     0x500B
+#define HDMI_A_TIMER1SETUP1                     0x500C
+#define HDMI_A_TIMER2SETUP0                     0x500D
+#define HDMI_A_TIMER2SETUP1                     0x500E
+#define HDMI_A_100MSCFG                         0x500F
+#define HDMI_A_2SCFG0                           0x5010
+#define HDMI_A_2SCFG1                           0x5011
+#define HDMI_A_5SCFG0                           0x5012
+#define HDMI_A_5SCFG1                           0x5013
+#define HDMI_A_SRMVERLSB                        0x5014
+#define HDMI_A_SRMVERMSB                        0x5015
+#define HDMI_A_SRMCTRL                          0x5016
+#define HDMI_A_SFRSETUP                         0x5017
+#define HDMI_A_I2CHSETUP                        0x5018
+#define HDMI_A_INTSETUP                         0x5019
+#define HDMI_A_PRESETUP                         0x501A
+#define HDMI_A_SRM_BASE                         0x5020
+
+/* CEC Engine Registers */
+#define HDMI_CEC_CTRL                           0x7D00
+#define HDMI_CEC_STAT                           0x7D01
+#define HDMI_CEC_MASK                           0x7D02
+#define HDMI_CEC_POLARITY                       0x7D03
+#define HDMI_CEC_INT                            0x7D04
+#define HDMI_CEC_ADDR_L                         0x7D05
+#define HDMI_CEC_ADDR_H                         0x7D06
+#define HDMI_CEC_TX_CNT                         0x7D07
+#define HDMI_CEC_RX_CNT                         0x7D08
+#define HDMI_CEC_TX_DATA0                       0x7D10
+#define HDMI_CEC_TX_DATA1                       0x7D11
+#define HDMI_CEC_TX_DATA2                       0x7D12
+#define HDMI_CEC_TX_DATA3                       0x7D13
+#define HDMI_CEC_TX_DATA4                       0x7D14
+#define HDMI_CEC_TX_DATA5                       0x7D15
+#define HDMI_CEC_TX_DATA6                       0x7D16
+#define HDMI_CEC_TX_DATA7                       0x7D17
+#define HDMI_CEC_TX_DATA8                       0x7D18
+#define HDMI_CEC_TX_DATA9                       0x7D19
+#define HDMI_CEC_TX_DATA10                      0x7D1a
+#define HDMI_CEC_TX_DATA11                      0x7D1b
+#define HDMI_CEC_TX_DATA12                      0x7D1c
+#define HDMI_CEC_TX_DATA13                      0x7D1d
+#define HDMI_CEC_TX_DATA14                      0x7D1e
+#define HDMI_CEC_TX_DATA15                      0x7D1f
+#define HDMI_CEC_RX_DATA0                       0x7D20
+#define HDMI_CEC_RX_DATA1                       0x7D21
+#define HDMI_CEC_RX_DATA2                       0x7D22
+#define HDMI_CEC_RX_DATA3                       0x7D23
+#define HDMI_CEC_RX_DATA4                       0x7D24
+#define HDMI_CEC_RX_DATA5                       0x7D25
+#define HDMI_CEC_RX_DATA6                       0x7D26
+#define HDMI_CEC_RX_DATA7                       0x7D27
+#define HDMI_CEC_RX_DATA8                       0x7D28
+#define HDMI_CEC_RX_DATA9                       0x7D29
+#define HDMI_CEC_RX_DATA10                      0x7D2a
+#define HDMI_CEC_RX_DATA11                      0x7D2b
+#define HDMI_CEC_RX_DATA12                      0x7D2c
+#define HDMI_CEC_RX_DATA13                      0x7D2d
+#define HDMI_CEC_RX_DATA14                      0x7D2e
+#define HDMI_CEC_RX_DATA15                      0x7D2f
+#define HDMI_CEC_LOCK                           0x7D30
+#define HDMI_CEC_WKUPCTRL                       0x7D31
+
+/* I2C Master Registers (E-DDC) */
+#define HDMI_I2CM_SLAVE                         0x7E00
+#define HDMI_I2CMESS                            0x7E01
+#define HDMI_I2CM_DATAO                         0x7E02
+#define HDMI_I2CM_DATAI                         0x7E03
+#define HDMI_I2CM_OPERATION                     0x7E04
+#define HDMI_I2CM_INT                           0x7E05
+#define HDMI_I2CM_CTLINT                        0x7E06
+#define HDMI_I2CM_DIV                           0x7E07
+#define HDMI_I2CM_SEGADDR                       0x7E08
+#define HDMI_I2CM_SOFTRSTZ                      0x7E09
+#define HDMI_I2CM_SEGPTR                        0x7E0A
+#define HDMI_I2CM_SS_SCL_HCNT_1_ADDR            0x7E0B
+#define HDMI_I2CM_SS_SCL_HCNT_0_ADDR            0x7E0C
+#define HDMI_I2CM_SS_SCL_LCNT_1_ADDR            0x7E0D
+#define HDMI_I2CM_SS_SCL_LCNT_0_ADDR            0x7E0E
+#define HDMI_I2CM_FS_SCL_HCNT_1_ADDR            0x7E0F
+#define HDMI_I2CM_FS_SCL_HCNT_0_ADDR            0x7E10
+#define HDMI_I2CM_FS_SCL_LCNT_1_ADDR            0x7E11
+#define HDMI_I2CM_FS_SCL_LCNT_0_ADDR            0x7E12
+
+enum {
+/* IH_FC_INT2 field values */
+	HDMI_IH_FC_INT2_OVERFLOW_MASK = 0x03,
+	HDMI_IH_FC_INT2_LOW_PRIORITY_OVERFLOW = 0x02,
+	HDMI_IH_FC_INT2_HIGH_PRIORITY_OVERFLOW = 0x01,
+
+/* IH_FC_STAT2 field values */
+	HDMI_IH_FC_STAT2_OVERFLOW_MASK = 0x03,
+	HDMI_IH_FC_STAT2_LOW_PRIORITY_OVERFLOW = 0x02,
+	HDMI_IH_FC_STAT2_HIGH_PRIORITY_OVERFLOW = 0x01,
+
+/* IH_PHY_STAT0 field values */
+	HDMI_IH_PHY_STAT0_RX_SENSE3 = 0x20,
+	HDMI_IH_PHY_STAT0_RX_SENSE2 = 0x10,
+	HDMI_IH_PHY_STAT0_RX_SENSE1 = 0x8,
+	HDMI_IH_PHY_STAT0_RX_SENSE0 = 0x4,
+	HDMI_IH_PHY_STAT0_TX_PHY_LOCK = 0x2,
+	HDMI_IH_PHY_STAT0_HPD = 0x1,
+
+/* IH_MUTE_I2CMPHY_STAT0 field values */
+	HDMI_IH_MUTE_I2CMPHY_STAT0_I2CMPHYDONE = 0x2,
+	HDMI_IH_MUTE_I2CMPHY_STAT0_I2CMPHYERROR = 0x1,
+
+/* IH_AHBDMAAUD_STAT0 field values */
+	HDMI_IH_AHBDMAAUD_STAT0_ERROR = 0x20,
+	HDMI_IH_AHBDMAAUD_STAT0_LOST = 0x10,
+	HDMI_IH_AHBDMAAUD_STAT0_RETRY = 0x08,
+	HDMI_IH_AHBDMAAUD_STAT0_DONE = 0x04,
+	HDMI_IH_AHBDMAAUD_STAT0_BUFFFULL = 0x02,
+	HDMI_IH_AHBDMAAUD_STAT0_BUFFEMPTY = 0x01,
+
+/* IH_MUTE_FC_STAT2 field values */
+	HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK = 0x03,
+	HDMI_IH_MUTE_FC_STAT2_LOW_PRIORITY_OVERFLOW = 0x02,
+	HDMI_IH_MUTE_FC_STAT2_HIGH_PRIORITY_OVERFLOW = 0x01,
+
+/* IH_MUTE_AHBDMAAUD_STAT0 field values */
+	HDMI_IH_MUTE_AHBDMAAUD_STAT0_ERROR = 0x20,
+	HDMI_IH_MUTE_AHBDMAAUD_STAT0_LOST = 0x10,
+	HDMI_IH_MUTE_AHBDMAAUD_STAT0_RETRY = 0x08,
+	HDMI_IH_MUTE_AHBDMAAUD_STAT0_DONE = 0x04,
+	HDMI_IH_MUTE_AHBDMAAUD_STAT0_BUFFFULL = 0x02,
+	HDMI_IH_MUTE_AHBDMAAUD_STAT0_BUFFEMPTY = 0x01,
+
+/* IH_MUTE field values */
+	HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT = 0x2,
+	HDMI_IH_MUTE_MUTE_ALL_INTERRUPT = 0x1,
+
+/* TX_INVID0 field values */
+	HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_MASK = 0x80,
+	HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_ENABLE = 0x80,
+	HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE = 0x00,
+	HDMI_TX_INVID0_VIDEO_MAPPING_MASK = 0x1F,
+	HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET = 0,
+
+/* TX_INSTUFFING field values */
+	HDMI_TX_INSTUFFING_BDBDATA_STUFFING_MASK = 0x4,
+	HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE = 0x4,
+	HDMI_TX_INSTUFFING_BDBDATA_STUFFING_DISABLE = 0x0,
+	HDMI_TX_INSTUFFING_RCRDATA_STUFFING_MASK = 0x2,
+	HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE = 0x2,
+	HDMI_TX_INSTUFFING_RCRDATA_STUFFING_DISABLE = 0x0,
+	HDMI_TX_INSTUFFING_GYDATA_STUFFING_MASK = 0x1,
+	HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE = 0x1,
+	HDMI_TX_INSTUFFING_GYDATA_STUFFING_DISABLE = 0x0,
+
+/* VP_PR_CD field values */
+	HDMI_VP_PR_CD_COLOR_DEPTH_MASK = 0xF0,
+	HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET = 4,
+	HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK = 0x0F,
+	HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET = 0,
+
+/* VP_STUFF field values */
+	HDMI_VP_STUFF_IDEFAULT_PHASE_MASK = 0x20,
+	HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET = 5,
+	HDMI_VP_STUFF_IFIX_PP_TO_LAST_MASK = 0x10,
+	HDMI_VP_STUFF_IFIX_PP_TO_LAST_OFFSET = 4,
+	HDMI_VP_STUFF_ICX_GOTO_P0_ST_MASK = 0x8,
+	HDMI_VP_STUFF_ICX_GOTO_P0_ST_OFFSET = 3,
+	HDMI_VP_STUFF_YCC422_STUFFING_MASK = 0x4,
+	HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE = 0x4,
+	HDMI_VP_STUFF_YCC422_STUFFING_DIRECT_MODE = 0x0,
+	HDMI_VP_STUFF_PP_STUFFING_MASK = 0x2,
+	HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE = 0x2,
+	HDMI_VP_STUFF_PP_STUFFING_DIRECT_MODE = 0x0,
+	HDMI_VP_STUFF_PR_STUFFING_MASK = 0x1,
+	HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE = 0x1,
+	HDMI_VP_STUFF_PR_STUFFING_DIRECT_MODE = 0x0,
+
+/* VP_CONF field values */
+	HDMI_VP_CONF_BYPASS_EN_MASK = 0x40,
+	HDMI_VP_CONF_BYPASS_EN_ENABLE = 0x40,
+	HDMI_VP_CONF_BYPASS_EN_DISABLE = 0x00,
+	HDMI_VP_CONF_PP_EN_ENMASK = 0x20,
+	HDMI_VP_CONF_PP_EN_ENABLE = 0x20,
+	HDMI_VP_CONF_PP_EN_DISABLE = 0x00,
+	HDMI_VP_CONF_PR_EN_MASK = 0x10,
+	HDMI_VP_CONF_PR_EN_ENABLE = 0x10,
+	HDMI_VP_CONF_PR_EN_DISABLE = 0x00,
+	HDMI_VP_CONF_YCC422_EN_MASK = 0x8,
+	HDMI_VP_CONF_YCC422_EN_ENABLE = 0x8,
+	HDMI_VP_CONF_YCC422_EN_DISABLE = 0x0,
+	HDMI_VP_CONF_BYPASS_SELECT_MASK = 0x4,
+	HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER = 0x4,
+	HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER = 0x0,
+	HDMI_VP_CONF_OUTPUT_SELECTOR_MASK = 0x3,
+	HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS = 0x3,
+	HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422 = 0x1,
+	HDMI_VP_CONF_OUTPUT_SELECTOR_PP = 0x0,
+
+/* VP_REMAP field values */
+	HDMI_VP_REMAP_MASK = 0x3,
+	HDMI_VP_REMAP_YCC422_24bit = 0x2,
+	HDMI_VP_REMAP_YCC422_20bit = 0x1,
+	HDMI_VP_REMAP_YCC422_16bit = 0x0,
+
+/* FC_INVIDCONF field values */
+	HDMI_FC_INVIDCONF_HDCP_KEEPOUT_MASK = 0x80,
+	HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE = 0x80,
+	HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE = 0x00,
+	HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_MASK = 0x40,
+	HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH = 0x40,
+	HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW = 0x00,
+	HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_MASK = 0x20,
+	HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH = 0x20,
+	HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW = 0x00,
+	HDMI_FC_INVIDCONF_DE_IN_POLARITY_MASK = 0x10,
+	HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH = 0x10,
+	HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW = 0x00,
+	HDMI_FC_INVIDCONF_DVI_MODEZ_MASK = 0x8,
+	HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE = 0x8,
+	HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE = 0x0,
+	HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_MASK = 0x2,
+	HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH = 0x2,
+	HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW = 0x0,
+	HDMI_FC_INVIDCONF_IN_I_P_MASK = 0x1,
+	HDMI_FC_INVIDCONF_IN_I_P_INTERLACED = 0x1,
+	HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE = 0x0,
+
+/* FC_AUDICONF0 field values */
+	HDMI_FC_AUDICONF0_CC_OFFSET = 4,
+	HDMI_FC_AUDICONF0_CC_MASK = 0x70,
+	HDMI_FC_AUDICONF0_CT_OFFSET = 0,
+	HDMI_FC_AUDICONF0_CT_MASK = 0xF,
+
+/* FC_AUDICONF1 field values */
+	HDMI_FC_AUDICONF1_SS_OFFSET = 3,
+	HDMI_FC_AUDICONF1_SS_MASK = 0x18,
+	HDMI_FC_AUDICONF1_SF_OFFSET = 0,
+	HDMI_FC_AUDICONF1_SF_MASK = 0x7,
+
+/* FC_AUDICONF3 field values */
+	HDMI_FC_AUDICONF3_LFEPBL_OFFSET = 5,
+	HDMI_FC_AUDICONF3_LFEPBL_MASK = 0x60,
+	HDMI_FC_AUDICONF3_DM_INH_OFFSET = 4,
+	HDMI_FC_AUDICONF3_DM_INH_MASK = 0x10,
+	HDMI_FC_AUDICONF3_LSV_OFFSET = 0,
+	HDMI_FC_AUDICONF3_LSV_MASK = 0xF,
+
+/* FC_AUDSCHNLS0 field values */
+	HDMI_FC_AUDSCHNLS0_CGMSA_OFFSET = 4,
+	HDMI_FC_AUDSCHNLS0_CGMSA_MASK = 0x30,
+	HDMI_FC_AUDSCHNLS0_COPYRIGHT_OFFSET = 0,
+	HDMI_FC_AUDSCHNLS0_COPYRIGHT_MASK = 0x01,
+
+/* FC_AUDSCHNLS3-6 field values */
+	HDMI_FC_AUDSCHNLS3_OIEC_CH0_OFFSET = 0,
+	HDMI_FC_AUDSCHNLS3_OIEC_CH0_MASK = 0x0f,
+	HDMI_FC_AUDSCHNLS3_OIEC_CH1_OFFSET = 4,
+	HDMI_FC_AUDSCHNLS3_OIEC_CH1_MASK = 0xf0,
+	HDMI_FC_AUDSCHNLS4_OIEC_CH2_OFFSET = 0,
+	HDMI_FC_AUDSCHNLS4_OIEC_CH2_MASK = 0x0f,
+	HDMI_FC_AUDSCHNLS4_OIEC_CH3_OFFSET = 4,
+	HDMI_FC_AUDSCHNLS4_OIEC_CH3_MASK = 0xf0,
+
+	HDMI_FC_AUDSCHNLS5_OIEC_CH0_OFFSET = 0,
+	HDMI_FC_AUDSCHNLS5_OIEC_CH0_MASK = 0x0f,
+	HDMI_FC_AUDSCHNLS5_OIEC_CH1_OFFSET = 4,
+	HDMI_FC_AUDSCHNLS5_OIEC_CH1_MASK = 0xf0,
+	HDMI_FC_AUDSCHNLS6_OIEC_CH2_OFFSET = 0,
+	HDMI_FC_AUDSCHNLS6_OIEC_CH2_MASK = 0x0f,
+	HDMI_FC_AUDSCHNLS6_OIEC_CH3_OFFSET = 4,
+	HDMI_FC_AUDSCHNLS6_OIEC_CH3_MASK = 0xf0,
+
+/* HDMI_FC_AUDSCHNLS7 field values */
+	HDMI_FC_AUDSCHNLS7_ACCURACY_OFFSET = 4,
+	HDMI_FC_AUDSCHNLS7_ACCURACY_MASK = 0x30,
+
+/* HDMI_FC_AUDSCHNLS8 field values */
+	HDMI_FC_AUDSCHNLS8_ORIGSAMPFREQ_MASK = 0xf0,
+	HDMI_FC_AUDSCHNLS8_ORIGSAMPFREQ_OFFSET = 4,
+	HDMI_FC_AUDSCHNLS8_WORDLEGNTH_MASK = 0x0f,
+	HDMI_FC_AUDSCHNLS8_WORDLEGNTH_OFFSET = 0,
+
+/* FC_AUDSCONF field values */
+	HDMI_FC_AUDSCONF_AUD_PACKET_SAMPFIT_MASK = 0xF0,
+	HDMI_FC_AUDSCONF_AUD_PACKET_SAMPFIT_OFFSET = 4,
+	HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_MASK = 0x1,
+	HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_OFFSET = 0,
+	HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT1 = 0x1,
+	HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT0 = 0x0,
+
+/* FC_STAT2 field values */
+	HDMI_FC_STAT2_OVERFLOW_MASK = 0x03,
+	HDMI_FC_STAT2_LOW_PRIORITY_OVERFLOW = 0x02,
+	HDMI_FC_STAT2_HIGH_PRIORITY_OVERFLOW = 0x01,
+
+/* FC_INT2 field values */
+	HDMI_FC_INT2_OVERFLOW_MASK = 0x03,
+	HDMI_FC_INT2_LOW_PRIORITY_OVERFLOW = 0x02,
+	HDMI_FC_INT2_HIGH_PRIORITY_OVERFLOW = 0x01,
+
+/* FC_MASK2 field values */
+	HDMI_FC_MASK2_OVERFLOW_MASK = 0x03,
+	HDMI_FC_MASK2_LOW_PRIORITY_OVERFLOW = 0x02,
+	HDMI_FC_MASK2_HIGH_PRIORITY_OVERFLOW = 0x01,
+
+/* FC_PRCONF field values */
+	HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK = 0xF0,
+	HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET = 4,
+	HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK = 0x0F,
+	HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET = 0,
+
+/* FC_AVICONF0-FC_AVICONF3 field values */
+	HDMI_FC_AVICONF0_PIX_FMT_MASK = 0x03,
+	HDMI_FC_AVICONF0_PIX_FMT_RGB = 0x00,
+	HDMI_FC_AVICONF0_PIX_FMT_YCBCR422 = 0x01,
+	HDMI_FC_AVICONF0_PIX_FMT_YCBCR444 = 0x02,
+	HDMI_FC_AVICONF0_ACTIVE_FMT_MASK = 0x40,
+	HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT = 0x40,
+	HDMI_FC_AVICONF0_ACTIVE_FMT_NO_INFO = 0x00,
+	HDMI_FC_AVICONF0_BAR_DATA_MASK = 0x0C,
+	HDMI_FC_AVICONF0_BAR_DATA_NO_DATA = 0x00,
+	HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR = 0x04,
+	HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR = 0x08,
+	HDMI_FC_AVICONF0_BAR_DATA_VERT_HORIZ_BAR = 0x0C,
+	HDMI_FC_AVICONF0_SCAN_INFO_MASK = 0x30,
+	HDMI_FC_AVICONF0_SCAN_INFO_OVERSCAN = 0x10,
+	HDMI_FC_AVICONF0_SCAN_INFO_UNDERSCAN = 0x20,
+	HDMI_FC_AVICONF0_SCAN_INFO_NODATA = 0x00,
+
+	HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_MASK = 0x0F,
+	HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_USE_CODED = 0x08,
+	HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_4_3 = 0x09,
+	HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_16_9 = 0x0A,
+	HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_14_9 = 0x0B,
+	HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_MASK = 0x30,
+	HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_NO_DATA = 0x00,
+	HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_4_3 = 0x10,
+	HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_16_9 = 0x20,
+	HDMI_FC_AVICONF1_COLORIMETRY_MASK = 0xC0,
+	HDMI_FC_AVICONF1_COLORIMETRY_NO_DATA = 0x00,
+	HDMI_FC_AVICONF1_COLORIMETRY_SMPTE = 0x40,
+	HDMI_FC_AVICONF1_COLORIMETRY_ITUR = 0x80,
+	HDMI_FC_AVICONF1_COLORIMETRY_EXTENDED_INFO = 0xC0,
+
+	HDMI_FC_AVICONF2_SCALING_MASK = 0x03,
+	HDMI_FC_AVICONF2_SCALING_NONE = 0x00,
+	HDMI_FC_AVICONF2_SCALING_HORIZ = 0x01,
+	HDMI_FC_AVICONF2_SCALING_VERT = 0x02,
+	HDMI_FC_AVICONF2_SCALING_HORIZ_VERT = 0x03,
+	HDMI_FC_AVICONF2_RGB_QUANT_MASK = 0x0C,
+	HDMI_FC_AVICONF2_RGB_QUANT_DEFAULT = 0x00,
+	HDMI_FC_AVICONF2_RGB_QUANT_LIMITED_RANGE = 0x04,
+	HDMI_FC_AVICONF2_RGB_QUANT_FULL_RANGE = 0x08,
+	HDMI_FC_AVICONF2_EXT_COLORIMETRY_MASK = 0x70,
+	HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC601 = 0x00,
+	HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC709 = 0x10,
+	HDMI_FC_AVICONF2_EXT_COLORIMETRY_SYCC601 = 0x20,
+	HDMI_FC_AVICONF2_EXT_COLORIMETRY_ADOBE_YCC601 = 0x30,
+	HDMI_FC_AVICONF2_EXT_COLORIMETRY_ADOBE_RGB = 0x40,
+	HDMI_FC_AVICONF2_IT_CONTENT_MASK = 0x80,
+	HDMI_FC_AVICONF2_IT_CONTENT_NO_DATA = 0x00,
+	HDMI_FC_AVICONF2_IT_CONTENT_VALID = 0x80,
+
+	HDMI_FC_AVICONF3_IT_CONTENT_TYPE_MASK = 0x03,
+	HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GRAPHICS = 0x00,
+	HDMI_FC_AVICONF3_IT_CONTENT_TYPE_PHOTO = 0x01,
+	HDMI_FC_AVICONF3_IT_CONTENT_TYPE_CINEMA = 0x02,
+	HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GAME = 0x03,
+	HDMI_FC_AVICONF3_QUANT_RANGE_MASK = 0x0C,
+	HDMI_FC_AVICONF3_QUANT_RANGE_LIMITED = 0x00,
+	HDMI_FC_AVICONF3_QUANT_RANGE_FULL = 0x04,
+
+/* FC_DBGFORCE field values */
+	HDMI_FC_DBGFORCE_FORCEAUDIO = 0x10,
+	HDMI_FC_DBGFORCE_FORCEVIDEO = 0x1,
+
+/* PHY_CONF0 field values */
+	HDMI_PHY_CONF0_PDZ_MASK = 0x80,
+	HDMI_PHY_CONF0_PDZ_OFFSET = 7,
+	HDMI_PHY_CONF0_ENTMDS_MASK = 0x40,
+	HDMI_PHY_CONF0_ENTMDS_OFFSET = 6,
+	HDMI_PHY_CONF0_SPARECTRL = 0x20,
+	HDMI_PHY_CONF0_GEN2_PDDQ_MASK = 0x10,
+	HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET = 4,
+	HDMI_PHY_CONF0_GEN2_TXPWRON_MASK = 0x8,
+	HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET = 3,
+	HDMI_PHY_CONF0_GEN2_ENHPDRXSENSE_MASK = 0x4,
+	HDMI_PHY_CONF0_GEN2_ENHPDRXSENSE_OFFSET = 2,
+	HDMI_PHY_CONF0_SELDATAENPOL_MASK = 0x2,
+	HDMI_PHY_CONF0_SELDATAENPOL_OFFSET = 1,
+	HDMI_PHY_CONF0_SELDIPIF_MASK = 0x1,
+	HDMI_PHY_CONF0_SELDIPIF_OFFSET = 0,
+
+/* PHY_TST0 field values */
+	HDMI_PHY_TST0_TSTCLR_MASK = 0x20,
+	HDMI_PHY_TST0_TSTCLR_OFFSET = 5,
+	HDMI_PHY_TST0_TSTEN_MASK = 0x10,
+	HDMI_PHY_TST0_TSTEN_OFFSET = 4,
+	HDMI_PHY_TST0_TSTCLK_MASK = 0x1,
+	HDMI_PHY_TST0_TSTCLK_OFFSET = 0,
+
+/* PHY_STAT0 field values */
+	HDMI_PHY_RX_SENSE3 = 0x80,
+	HDMI_PHY_RX_SENSE2 = 0x40,
+	HDMI_PHY_RX_SENSE1 = 0x20,
+	HDMI_PHY_RX_SENSE0 = 0x10,
+	HDMI_PHY_HPD = 0x02,
+	HDMI_PHY_TX_PHY_LOCK = 0x01,
+
+/* PHY_I2CM_SLAVE_ADDR field values */
+	HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2 = 0x69,
+	HDMI_PHY_I2CM_SLAVE_ADDR_HEAC_PHY = 0x49,
+
+/* PHY_I2CM_OPERATION_ADDR field values */
+	HDMI_PHY_I2CM_OPERATION_ADDR_WRITE = 0x10,
+	HDMI_PHY_I2CM_OPERATION_ADDR_READ = 0x1,
+
+/* HDMI_PHY_I2CM_INT_ADDR */
+	HDMI_PHY_I2CM_INT_ADDR_DONE_POL = 0x08,
+	HDMI_PHY_I2CM_INT_ADDR_DONE_MASK = 0x04,
+
+/* HDMI_PHY_I2CM_CTLINT_ADDR */
+	HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL = 0x80,
+	HDMI_PHY_I2CM_CTLINT_ADDR_NAC_MASK = 0x40,
+	HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL = 0x08,
+	HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_MASK = 0x04,
+
+/* AUD_CTS3 field values */
+	HDMI_AUD_CTS3_N_SHIFT_OFFSET = 5,
+	HDMI_AUD_CTS3_N_SHIFT_MASK = 0xe0,
+	HDMI_AUD_CTS3_N_SHIFT_1 = 0,
+	HDMI_AUD_CTS3_N_SHIFT_16 = 0x20,
+	HDMI_AUD_CTS3_N_SHIFT_32 = 0x40,
+	HDMI_AUD_CTS3_N_SHIFT_64 = 0x60,
+	HDMI_AUD_CTS3_N_SHIFT_128 = 0x80,
+	HDMI_AUD_CTS3_N_SHIFT_256 = 0xa0,
+	/* note that the CTS3 MANUAL bit has been removed
+	   from our part. Can't set it, will read as 0. */
+	HDMI_AUD_CTS3_CTS_MANUAL = 0x10,
+	HDMI_AUD_CTS3_AUDCTS19_16_MASK = 0x0f,
+
+/* AHB_DMA_CONF0 field values */
+	HDMI_AHB_DMA_CONF0_SW_FIFO_RST_OFFSET = 7,
+	HDMI_AHB_DMA_CONF0_SW_FIFO_RST_MASK = 0x80,
+	HDMI_AHB_DMA_CONF0_HBR = 0x10,
+	HDMI_AHB_DMA_CONF0_EN_HLOCK_OFFSET = 3,
+	HDMI_AHB_DMA_CONF0_EN_HLOCK_MASK = 0x08,
+	HDMI_AHB_DMA_CONF0_INCR_TYPE_OFFSET = 1,
+	HDMI_AHB_DMA_CONF0_INCR_TYPE_MASK = 0x06,
+	HDMI_AHB_DMA_CONF0_INCR4 = 0x0,
+	HDMI_AHB_DMA_CONF0_INCR8 = 0x2,
+	HDMI_AHB_DMA_CONF0_INCR16 = 0x4,
+	HDMI_AHB_DMA_CONF0_BURST_MODE = 0x1,
+
+/* HDMI_AHB_DMA_START field values */
+	HDMI_AHB_DMA_START_START_OFFSET = 0,
+	HDMI_AHB_DMA_START_START_MASK = 0x01,
+
+/* HDMI_AHB_DMA_STOP field values */
+	HDMI_AHB_DMA_STOP_STOP_OFFSET = 0,
+	HDMI_AHB_DMA_STOP_STOP_MASK = 0x01,
+
+/* AHB_DMA_STAT, AHB_DMA_INT, AHB_DMA_MASK, AHB_DMA_POL field values */
+	HDMI_AHB_DMA_DONE = 0x80,
+	HDMI_AHB_DMA_RETRY_SPLIT = 0x40,
+	HDMI_AHB_DMA_LOSTOWNERSHIP = 0x20,
+	HDMI_AHB_DMA_ERROR = 0x10,
+	HDMI_AHB_DMA_FIFO_THREMPTY = 0x04,
+	HDMI_AHB_DMA_FIFO_FULL = 0x02,
+	HDMI_AHB_DMA_FIFO_EMPTY = 0x01,
+
+/* AHB_DMA_BUFFSTAT, AHB_DMA_BUFFINT,AHB_DMA_BUFFMASK,AHB_DMA_BUFFPOL values */
+	HDMI_AHB_DMA_BUFFSTAT_FULL = 0x02,
+	HDMI_AHB_DMA_BUFFSTAT_EMPTY = 0x01,
+
+/* MC_CLKDIS field values */
+	HDMI_MC_CLKDIS_HDCPCLK_DISABLE = 0x40,
+	HDMI_MC_CLKDIS_CECCLK_DISABLE = 0x20,
+	HDMI_MC_CLKDIS_CSCCLK_DISABLE = 0x10,
+	HDMI_MC_CLKDIS_AUDCLK_DISABLE = 0x8,
+	HDMI_MC_CLKDIS_PREPCLK_DISABLE = 0x4,
+	HDMI_MC_CLKDIS_TMDSCLK_DISABLE = 0x2,
+	HDMI_MC_CLKDIS_PIXELCLK_DISABLE = 0x1,
+
+/* MC_SWRSTZ field values */
+	HDMI_MC_SWRSTZ_TMDSSWRST_REQ = 0x02,
+
+/* MC_FLOWCTRL field values */
+	HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_MASK = 0x1,
+	HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH = 0x1,
+	HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS = 0x0,
+
+/* MC_PHYRSTZ field values */
+	HDMI_MC_PHYRSTZ_ASSERT = 0x0,
+	HDMI_MC_PHYRSTZ_DEASSERT = 0x1,
+
+/* MC_HEACPHY_RST field values */
+	HDMI_MC_HEACPHY_RST_ASSERT = 0x1,
+	HDMI_MC_HEACPHY_RST_DEASSERT = 0x0,
+
+/* CSC_CFG field values */
+	HDMI_CSC_CFG_INTMODE_MASK = 0x30,
+	HDMI_CSC_CFG_INTMODE_OFFSET = 4,
+	HDMI_CSC_CFG_INTMODE_DISABLE = 0x00,
+	HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1 = 0x10,
+	HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA2 = 0x20,
+	HDMI_CSC_CFG_DECMODE_MASK = 0x3,
+	HDMI_CSC_CFG_DECMODE_OFFSET = 0,
+	HDMI_CSC_CFG_DECMODE_DISABLE = 0x0,
+	HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA1 = 0x1,
+	HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA2 = 0x2,
+	HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3 = 0x3,
+
+/* CSC_SCALE field values */
+	HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK = 0xF0,
+	HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP = 0x00,
+	HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP = 0x50,
+	HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP = 0x60,
+	HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP = 0x70,
+	HDMI_CSC_SCALE_CSCSCALE_MASK = 0x03,
+
+/* A_HDCPCFG0 field values */
+	HDMI_A_HDCPCFG0_ELVENA_MASK = 0x80,
+	HDMI_A_HDCPCFG0_ELVENA_ENABLE = 0x80,
+	HDMI_A_HDCPCFG0_ELVENA_DISABLE = 0x00,
+	HDMI_A_HDCPCFG0_I2CFASTMODE_MASK = 0x40,
+	HDMI_A_HDCPCFG0_I2CFASTMODE_ENABLE = 0x40,
+	HDMI_A_HDCPCFG0_I2CFASTMODE_DISABLE = 0x00,
+	HDMI_A_HDCPCFG0_BYPENCRYPTION_MASK = 0x20,
+	HDMI_A_HDCPCFG0_BYPENCRYPTION_ENABLE = 0x20,
+	HDMI_A_HDCPCFG0_BYPENCRYPTION_DISABLE = 0x00,
+	HDMI_A_HDCPCFG0_SYNCRICHECK_MASK = 0x10,
+	HDMI_A_HDCPCFG0_SYNCRICHECK_ENABLE = 0x10,
+	HDMI_A_HDCPCFG0_SYNCRICHECK_DISABLE = 0x00,
+	HDMI_A_HDCPCFG0_AVMUTE_MASK = 0x8,
+	HDMI_A_HDCPCFG0_AVMUTE_ENABLE = 0x8,
+	HDMI_A_HDCPCFG0_AVMUTE_DISABLE = 0x0,
+	HDMI_A_HDCPCFG0_RXDETECT_MASK = 0x4,
+	HDMI_A_HDCPCFG0_RXDETECT_ENABLE = 0x4,
+	HDMI_A_HDCPCFG0_RXDETECT_DISABLE = 0x0,
+	HDMI_A_HDCPCFG0_EN11FEATURE_MASK = 0x2,
+	HDMI_A_HDCPCFG0_EN11FEATURE_ENABLE = 0x2,
+	HDMI_A_HDCPCFG0_EN11FEATURE_DISABLE = 0x0,
+	HDMI_A_HDCPCFG0_HDMIDVI_MASK = 0x1,
+	HDMI_A_HDCPCFG0_HDMIDVI_HDMI = 0x1,
+	HDMI_A_HDCPCFG0_HDMIDVI_DVI = 0x0,
+
+/* A_HDCPCFG1 field values */
+	HDMI_A_HDCPCFG1_DISSHA1CHECK_MASK = 0x8,
+	HDMI_A_HDCPCFG1_DISSHA1CHECK_DISABLE = 0x8,
+	HDMI_A_HDCPCFG1_DISSHA1CHECK_ENABLE = 0x0,
+	HDMI_A_HDCPCFG1_PH2UPSHFTENC_MASK = 0x4,
+	HDMI_A_HDCPCFG1_PH2UPSHFTENC_ENABLE = 0x4,
+	HDMI_A_HDCPCFG1_PH2UPSHFTENC_DISABLE = 0x0,
+	HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK = 0x2,
+	HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE = 0x2,
+	HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_ENABLE = 0x0,
+	HDMI_A_HDCPCFG1_SWRESET_MASK = 0x1,
+	HDMI_A_HDCPCFG1_SWRESET_ASSERT = 0x0,
+
+/* A_VIDPOLCFG field values */
+	HDMI_A_VIDPOLCFG_UNENCRYPTCONF_MASK = 0x60,
+	HDMI_A_VIDPOLCFG_UNENCRYPTCONF_OFFSET = 5,
+	HDMI_A_VIDPOLCFG_DATAENPOL_MASK = 0x10,
+	HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH = 0x10,
+	HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_LOW = 0x0,
+	HDMI_A_VIDPOLCFG_VSYNCPOL_MASK = 0x8,
+	HDMI_A_VIDPOLCFG_VSYNCPOL_ACTIVE_HIGH = 0x8,
+	HDMI_A_VIDPOLCFG_VSYNCPOL_ACTIVE_LOW = 0x0,
+	HDMI_A_VIDPOLCFG_HSYNCPOL_MASK = 0x2,
+	HDMI_A_VIDPOLCFG_HSYNCPOL_ACTIVE_HIGH = 0x2,
+	HDMI_A_VIDPOLCFG_HSYNCPOL_ACTIVE_LOW = 0x0,
+};
+#endif /* __IMX_HDMI_H__ */
-- 
1.9.0



From s.hauer at pengutronix.de  Fri Mar 14 10:32:35 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 14 Mar 2014 15:32:35 +0100
Subject: [PATCH 15/29] clk: let clk-divider handle the table based divider
 aswell
In-Reply-To: <1394807569-23620-1-git-send-email-s.hauer@pengutronix.de>
References: <1394807569-23620-1-git-send-email-s.hauer@pengutronix.de>
Message-ID: <1394807569-23620-16-git-send-email-s.hauer@pengutronix.de>

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 drivers/clk/Makefile            |   2 +-
 drivers/clk/clk-divider-table.c | 120 ----------------------------------------
 drivers/clk/clk-divider.c       |  36 ++++++++++++
 3 files changed, 37 insertions(+), 121 deletions(-)
 delete mode 100644 drivers/clk/clk-divider-table.c

diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index f5c0592..7506f87 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -1,5 +1,5 @@
 obj-$(CONFIG_COMMON_CLK)	+= clk.o clk-fixed.o clk-divider.o clk-fixed-factor.o \
-				clk-mux.o clk-gate.o clk-divider-table.o
+				clk-mux.o clk-gate.o
 obj-$(CONFIG_CLKDEV_LOOKUP)	+= clkdev.o
 
 obj-$(CONFIG_ARCH_MVEBU)	+= mvebu/
diff --git a/drivers/clk/clk-divider-table.c b/drivers/clk/clk-divider-table.c
deleted file mode 100644
index 0caf85d..0000000
--- a/drivers/clk/clk-divider-table.c
+++ /dev/null
@@ -1,120 +0,0 @@
-/*
- * clk-divider-table.c - generic barebox clock support. Based on Linux clk support
- *
- * Copyright (c) 2012 Sascha Hauer <s.hauer at pengutronix.de>, Pengutronix
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-#include <common.h>
-#include <io.h>
-#include <malloc.h>
-#include <linux/clk.h>
-#include <linux/err.h>
-
-struct clk_divider_table {
-	struct clk clk;
-	u8 shift;
-	u8 width;
-	void __iomem *reg;
-	const char *parent;
-	const struct clk_div_table *table;
-	int table_size;
-	int max_div_index;
-};
-
-static int clk_divider_set_rate(struct clk *clk, unsigned long rate,
-		unsigned long parent_rate)
-{
-	struct clk_divider_table *div =
-		container_of(clk, struct clk_divider_table, clk);
-	unsigned int val;
-	int i, div_index = -1;
-	unsigned long best = 0;
-
-	if (rate > parent_rate)
-		rate = parent_rate;
-	if (rate < parent_rate / div->table[div->max_div_index].div)
-		rate = parent_rate / div->table[div->max_div_index].div;
-
-	for (i = 0; i < div->table_size; i++) {
-		unsigned long now = parent_rate / div->table[i].div;
-
-		if (now <= rate && now >= best) {
-			best = now;
-			div_index = i;
-		}
-	}
-
-	val = readl(div->reg);
-	val &= ~(((1 << div->width) - 1) << div->shift);
-	val |= div_index << div->shift;
-	writel(val, div->reg);
-
-	return 0;
-}
-
-static unsigned long clk_divider_recalc_rate(struct clk *clk,
-		unsigned long parent_rate)
-{
-	struct clk_divider_table *div =
-		container_of(clk, struct clk_divider_table, clk);
-	unsigned int val;
-
-	val = readl(div->reg) >> div->shift;
-	val &= (1 << div->width) - 1;
-
-	if (val >= div->table_size)
-		return 0;
-
-	return parent_rate / div->table[val].div;
-}
-
-static struct clk_ops clk_divider_table_ops = {
-	.set_rate = clk_divider_set_rate,
-	.recalc_rate = clk_divider_recalc_rate,
-};
-
-struct clk *clk_divider_table(const char *name,
-		const char *parent, void __iomem *reg, u8 shift, u8 width,
-		const struct clk_div_table *table, unsigned flags)
-{
-	struct clk_divider_table *div = xzalloc(sizeof(*div));
-	const struct clk_div_table *clkt;
-	int ret, max_div = 0;
-
-	div->shift = shift;
-	div->reg = reg;
-	div->width = width;
-	div->parent = parent;
-	div->clk.ops = &clk_divider_table_ops;
-	div->clk.name = name;
-	div->clk.parent_names = &div->parent;
-	div->clk.flags = flags;
-	div->clk.num_parents = 1;
-	div->table = table;
-
-	for (clkt = div->table; clkt->div; clkt++) {
-		if (clkt->div > max_div) {
-			max_div = clkt->div;
-			div->max_div_index = div->table_size;
-		}
-		div->table_size++;
-	}
-
-	ret = clk_register(&div->clk);
-	if (ret) {
-		free(div);
-		return ERR_PTR(ret);
-	}
-
-	return &div->clk;
-}
diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index 9634bd3..67783da 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -248,3 +248,39 @@ struct clk *clk_divider_one_based(const char *name, const char *parent,
 
 	return clk;
 }
+
+struct clk *clk_divider_table(const char *name,
+		const char *parent, void __iomem *reg, u8 shift, u8 width,
+		const struct clk_div_table *table, unsigned flags)
+{
+	struct clk_divider *div = xzalloc(sizeof(*div));
+	const struct clk_div_table *clkt;
+	int ret, max_div = 0;
+
+	div->shift = shift;
+	div->reg = reg;
+	div->width = width;
+	div->parent = parent;
+	div->clk.ops = &clk_divider_ops;
+	div->clk.name = name;
+	div->clk.flags = flags;
+	div->clk.parent_names = &div->parent;
+	div->clk.num_parents = 1;
+	div->table = table;
+
+	for (clkt = div->table; clkt->div; clkt++) {
+		if (clkt->div > max_div) {
+			max_div = clkt->div;
+			div->max_div_index = div->table_size;
+		}
+		div->table_size++;
+	}
+
+	ret = clk_register(&div->clk);
+	if (ret) {
+		free(div);
+		return ERR_PTR(ret);
+	}
+
+	return &div->clk;
+}
-- 
1.9.0



From s.hauer at pengutronix.de  Fri Mar 14 10:32:34 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 14 Mar 2014 15:32:34 +0100
Subject: [PATCH 14/29] clk: clk-divider: sync with kernel code
In-Reply-To: <1394807569-23620-1-git-send-email-s.hauer@pengutronix.de>
References: <1394807569-23620-1-git-send-email-s.hauer@pengutronix.de>
Message-ID: <1394807569-23620-15-git-send-email-s.hauer@pengutronix.de>

This updates the clk-divider to Kernel code, but without power-of-two
divider support which we do not need yet. This also adds table based
divider support to the divider.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 drivers/clk/clk-divider.c | 191 ++++++++++++++++++++++++++++++++++++++--------
 include/linux/clk.h       |   3 +
 2 files changed, 164 insertions(+), 30 deletions(-)

diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index bb8bcc1..9634bd3 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -20,61 +20,192 @@
 #include <linux/clk.h>
 #include <linux/err.h>
 
-static unsigned int clk_divider_maxdiv(struct clk_divider *div)
+#define div_mask(d)	((1 << ((d)->width)) - 1)
+
+static unsigned int _get_maxdiv(struct clk_divider *divider)
 {
-	if (div->flags & CLK_DIVIDER_ONE_BASED)
-                return (1 << div->width) - 1;
-	return 1 << div->width;
+	if (divider->flags & CLK_DIVIDER_ONE_BASED)
+		return div_mask(divider);
+	return div_mask(divider) + 1;
 }
 
-static int clk_divider_set_rate(struct clk *clk, unsigned long rate,
+static unsigned int _get_table_div(const struct clk_div_table *table,
+							unsigned int val)
+{
+	const struct clk_div_table *clkt;
+
+	for (clkt = table; clkt->div; clkt++)
+		if (clkt->val == val)
+			return clkt->div;
+	return 0;
+}
+
+static unsigned int _get_div(struct clk_divider *divider, unsigned int val)
+{
+	if (divider->flags & CLK_DIVIDER_ONE_BASED)
+		return val;
+	if (divider->table)
+		return _get_table_div(divider->table, val);
+	return val + 1;
+}
+
+static unsigned int _get_table_val(const struct clk_div_table *table,
+							unsigned int div)
+{
+	const struct clk_div_table *clkt;
+
+	for (clkt = table; clkt->div; clkt++)
+		if (clkt->div == div)
+			return clkt->val;
+	return 0;
+}
+
+static unsigned int _get_val(struct clk_divider *divider, unsigned int div)
+{
+	if (divider->flags & CLK_DIVIDER_ONE_BASED)
+		return div;
+	if (divider->table)
+		return  _get_table_val(divider->table, div);
+	return div - 1;
+}
+
+static unsigned long clk_divider_recalc_rate(struct clk *clk,
 		unsigned long parent_rate)
 {
-	struct clk_divider *div = container_of(clk, struct clk_divider, clk);
-	unsigned int val, divval;
+	struct clk_divider *divider = container_of(clk, struct clk_divider, clk);
+	unsigned int div, val;
+
+	val = readl(divider->reg) >> divider->shift;
+	val &= div_mask(divider);
+
+	div = _get_div(divider, val);
+
+	return parent_rate / div;
+}
+
+/*
+ * The reverse of DIV_ROUND_UP: The maximum number which
+ * divided by m is r
+ */
+#define MULT_ROUND_UP(r, m) ((r) * (m) + (m) - 1)
+
+static bool _is_valid_table_div(const struct clk_div_table *table,
+							 unsigned int div)
+{
+	const struct clk_div_table *clkt;
+
+	for (clkt = table; clkt->div; clkt++)
+		if (clkt->div == div)
+			return true;
+	return false;
+}
+
+static bool _is_valid_div(struct clk_divider *divider, unsigned int div)
+{
+	if (divider->table)
+		return _is_valid_table_div(divider->table, div);
+	return true;
+}
+
+static int clk_divider_bestdiv(struct clk *clk, unsigned long rate,
+		unsigned long *best_parent_rate)
+{
+	struct clk_divider *divider = container_of(clk, struct clk_divider, clk);
+	int i, bestdiv = 0;
+	unsigned long parent_rate, best = 0, now, maxdiv;
+	unsigned long parent_rate_saved = *best_parent_rate;
 
-	if (rate > parent_rate)
-		rate = parent_rate;
 	if (!rate)
 		rate = 1;
 
-	divval = DIV_ROUND_UP(parent_rate, rate);
-	if (divval > clk_divider_maxdiv(div))
-		divval = clk_divider_maxdiv(div);
+	maxdiv = _get_maxdiv(divider);
 
-	if (!(div->flags & CLK_DIVIDER_ONE_BASED))
-		divval--;
+	if (!(clk->flags & CLK_SET_RATE_PARENT)) {
+		parent_rate = *best_parent_rate;
+		bestdiv = DIV_ROUND_UP(parent_rate, rate);
+		bestdiv = bestdiv == 0 ? 1 : bestdiv;
+		bestdiv = bestdiv > maxdiv ? maxdiv : bestdiv;
+		return bestdiv;
+	}
 
-	val = readl(div->reg);
-	val &= ~(((1 << div->width) - 1) << div->shift);
-	val |= divval << div->shift;
-	writel(val, div->reg);
+	/*
+	 * The maximum divider we can use without overflowing
+	 * unsigned long in rate * i below
+	 */
+	maxdiv = min(ULONG_MAX / rate, maxdiv);
+
+	for (i = 1; i <= maxdiv; i++) {
+		if (!_is_valid_div(divider, i))
+			continue;
+		if (rate * i == parent_rate_saved) {
+			/*
+			 * It's the most ideal case if the requested rate can be
+			 * divided from parent clock without needing to change
+			 * parent rate, so return the divider immediately.
+			 */
+			*best_parent_rate = parent_rate_saved;
+			return i;
+		}
+		parent_rate = clk_round_rate(clk_get_parent(clk),
+				MULT_ROUND_UP(rate, i));
+		now = parent_rate / i;
+		if (now <= rate && now > best) {
+			bestdiv = i;
+			best = now;
+			*best_parent_rate = parent_rate;
+		}
+	}
 
-	return 0;
+	if (!bestdiv) {
+		bestdiv = _get_maxdiv(divider);
+		*best_parent_rate = clk_round_rate(clk_get_parent(clk), 1);
+	}
+
+	return bestdiv;
 }
 
-static unsigned long clk_divider_recalc_rate(struct clk *clk,
-		unsigned long parent_rate)
+static long clk_divider_round_rate(struct clk *clk, unsigned long rate,
+		unsigned long *parent_rate)
 {
-	struct clk_divider *div = container_of(clk, struct clk_divider, clk);
-	unsigned int val;
+	int div;
 
-	val = readl(div->reg) >> div->shift;
-	val &= (1 << div->width) - 1;
+	div = clk_divider_bestdiv(clk, rate, parent_rate);
 
-	if (div->flags & CLK_DIVIDER_ONE_BASED) {
-		if (!val)
-			val++;
+	return *parent_rate / div;
+}
+
+static int clk_divider_set_rate(struct clk *clk, unsigned long rate,
+		unsigned long parent_rate)
+{
+	struct clk_divider *divider = container_of(clk, struct clk_divider, clk);
+	unsigned int div, value;
+	u32 val;
+
+	if (clk->flags & CLK_SET_RATE_PARENT) {
+		unsigned long best_parent_rate = parent_rate;
+		div = clk_divider_bestdiv(clk, rate, &best_parent_rate);
+		clk_set_rate(clk_get_parent(clk), best_parent_rate);
 	} else {
-		val++;
+		div = parent_rate / rate;
 	}
 
-	return parent_rate / val;
+	value = _get_val(divider, div);
+
+	if (value > div_mask(divider))
+		value = div_mask(divider);
+
+	val = readl(divider->reg);
+	val &= ~(div_mask(divider) << divider->shift);
+	val |= value << divider->shift;
+	writel(val, divider->reg);
+
+	return 0;
 }
 
 struct clk_ops clk_divider_ops = {
 	.set_rate = clk_divider_set_rate,
 	.recalc_rate = clk_divider_recalc_rate,
+	.round_rate = clk_divider_round_rate,
 };
 
 struct clk *clk_divider(const char *name, const char *parent,
diff --git a/include/linux/clk.h b/include/linux/clk.h
index 2704b0f..71b0466 100644
--- a/include/linux/clk.h
+++ b/include/linux/clk.h
@@ -240,6 +240,9 @@ struct clk_divider {
 	const char *parent;
 #define CLK_DIVIDER_ONE_BASED	(1 << 0)
 	unsigned flags;
+	const struct clk_div_table *table;
+	int max_div_index;
+	int table_size;
 };
 
 extern struct clk_ops clk_divider_ops;
-- 
1.9.0



From s.hauer at pengutronix.de  Fri Mar 14 10:32:32 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 14 Mar 2014 15:32:32 +0100
Subject: [PATCH 12/29] clk: clk-divider: pass flags to initializers
In-Reply-To: <1394807569-23620-1-git-send-email-s.hauer@pengutronix.de>
References: <1394807569-23620-1-git-send-email-s.hauer@pengutronix.de>
Message-ID: <1394807569-23620-13-git-send-email-s.hauer@pengutronix.de>

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/mach-imx/clk-imx6.c    | 2 +-
 arch/arm/mach-imx/clk.h         | 2 +-
 drivers/clk/clk-divider-table.c | 3 ++-
 drivers/clk/clk-divider.c       | 7 ++++---
 include/linux/clk.h             | 6 +++---
 5 files changed, 11 insertions(+), 9 deletions(-)

diff --git a/arch/arm/mach-imx/clk-imx6.c b/arch/arm/mach-imx/clk-imx6.c
index 5560fff..8d78a18 100644
--- a/arch/arm/mach-imx/clk-imx6.c
+++ b/arch/arm/mach-imx/clk-imx6.c
@@ -214,7 +214,7 @@ static int imx6_ccm_probe(struct device_d *dev)
 	clks[sata_ref_100m] = imx_clk_gate("sata_ref_100m", "sata_ref", base + 0xe0, 20);
 	clks[pcie_ref_125m] = imx_clk_gate("pcie_ref_125m", "pcie_ref", base + 0xe0, 19);
 
-	clks[enet_ref] = clk_divider_table("enet_ref", "pll6_enet", base + 0xe0, 0, 2, clk_enet_ref_table);
+	clks[enet_ref] = clk_divider_table("enet_ref", "pll6_enet", base + 0xe0, 0, 2, clk_enet_ref_table, 0);
 
 	/*                                name               parent_name         reg          idx */
 	clks[pll2_pfd0_352m] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus",     base + 0x100, 0);
diff --git a/arch/arm/mach-imx/clk.h b/arch/arm/mach-imx/clk.h
index 54f04ed..cdafad1 100644
--- a/arch/arm/mach-imx/clk.h
+++ b/arch/arm/mach-imx/clk.h
@@ -4,7 +4,7 @@
 static inline struct clk *imx_clk_divider(const char *name, const char *parent,
 		void __iomem *reg, u8 shift, u8 width)
 {
-	return clk_divider(name, parent, reg, shift, width);
+	return clk_divider(name, parent, reg, shift, width, 0);
 }
 
 static inline struct clk *imx_clk_fixed_factor(const char *name,
diff --git a/drivers/clk/clk-divider-table.c b/drivers/clk/clk-divider-table.c
index fd2d3fc..0caf85d 100644
--- a/drivers/clk/clk-divider-table.c
+++ b/drivers/clk/clk-divider-table.c
@@ -85,7 +85,7 @@ static struct clk_ops clk_divider_table_ops = {
 
 struct clk *clk_divider_table(const char *name,
 		const char *parent, void __iomem *reg, u8 shift, u8 width,
-		const struct clk_div_table *table)
+		const struct clk_div_table *table, unsigned flags)
 {
 	struct clk_divider_table *div = xzalloc(sizeof(*div));
 	const struct clk_div_table *clkt;
@@ -98,6 +98,7 @@ struct clk *clk_divider_table(const char *name,
 	div->clk.ops = &clk_divider_table_ops;
 	div->clk.name = name;
 	div->clk.parent_names = &div->parent;
+	div->clk.flags = flags;
 	div->clk.num_parents = 1;
 	div->table = table;
 
diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index 3bf8105..bb8bcc1 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -78,7 +78,7 @@ struct clk_ops clk_divider_ops = {
 };
 
 struct clk *clk_divider(const char *name, const char *parent,
-		void __iomem *reg, u8 shift, u8 width)
+		void __iomem *reg, u8 shift, u8 width, unsigned flags)
 {
 	struct clk_divider *div = xzalloc(sizeof(*div));
 	int ret;
@@ -89,6 +89,7 @@ struct clk *clk_divider(const char *name, const char *parent,
 	div->parent = parent;
 	div->clk.ops = &clk_divider_ops;
 	div->clk.name = name;
+	div->clk.flags = flags;
 	div->clk.parent_names = &div->parent;
 	div->clk.num_parents = 1;
 
@@ -102,12 +103,12 @@ struct clk *clk_divider(const char *name, const char *parent,
 }
 
 struct clk *clk_divider_one_based(const char *name, const char *parent,
-		void __iomem *reg, u8 shift, u8 width)
+		void __iomem *reg, u8 shift, u8 width, unsigned flags)
 {
 	struct clk_divider *div;
 	struct clk *clk;
 
-	clk = clk_divider(name, parent, reg, shift, width);
+	clk = clk_divider(name, parent, reg, shift, width, flags);
 	if (IS_ERR(clk))
 		return clk;
 
diff --git a/include/linux/clk.h b/include/linux/clk.h
index e65a62a..7e5010a 100644
--- a/include/linux/clk.h
+++ b/include/linux/clk.h
@@ -242,12 +242,12 @@ struct clk_divider {
 extern struct clk_ops clk_divider_ops;
 
 struct clk *clk_divider(const char *name, const char *parent,
-		void __iomem *reg, u8 shift, u8 width);
+		void __iomem *reg, u8 shift, u8 width, unsigned flags);
 struct clk *clk_divider_one_based(const char *name, const char *parent,
-		void __iomem *reg, u8 shift, u8 width);
+		void __iomem *reg, u8 shift, u8 width, unsigned flags);
 struct clk *clk_divider_table(const char *name,
 		const char *parent, void __iomem *reg, u8 shift, u8 width,
-		const struct clk_div_table *table);
+		const struct clk_div_table *table, unsigned flags);
 struct clk *clk_fixed_factor(const char *name,
 		const char *parent, unsigned int mult, unsigned int div,
 		unsigned flags);
-- 
1.9.0



From s.hauer at pengutronix.de  Fri Mar 14 10:32:42 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 14 Mar 2014 15:32:42 +0100
Subject: [PATCH 22/29] video: Add display timing from devicetree helper
In-Reply-To: <1394807569-23620-1-git-send-email-s.hauer@pengutronix.de>
References: <1394807569-23620-1-git-send-email-s.hauer@pengutronix.de>
Message-ID: <1394807569-23620-23-git-send-email-s.hauer@pengutronix.de>

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 drivers/video/Makefile            |   1 +
 drivers/video/of_display_timing.c | 238 ++++++++++++++++++++++++++++++++++++++
 include/fb.h                      |  14 ++-
 3 files changed, 252 insertions(+), 1 deletion(-)
 create mode 100644 drivers/video/of_display_timing.c

diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 31edfca..d36d83d 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -1,4 +1,5 @@
 obj-$(CONFIG_VIDEO) += fb.o
+obj-$(CONFIG_OFDEVICE) += of_display_timing.o
 
 obj-$(CONFIG_DRIVER_VIDEO_ATMEL) += atmel_lcdfb.o atmel_lcdfb_core.o
 obj-$(CONFIG_DRIVER_VIDEO_ATMEL_HLCD) += atmel_hlcdfb.o atmel_lcdfb_core.o
diff --git a/drivers/video/of_display_timing.c b/drivers/video/of_display_timing.c
new file mode 100644
index 0000000..5dfd5b3
--- /dev/null
+++ b/drivers/video/of_display_timing.c
@@ -0,0 +1,238 @@
+/*
+ * OF helpers for parsing display timings
+ *
+ * Copyright (c) 2012 Steffen Trumtrar <s.trumtrar at pengutronix.de>, Pengutronix
+ *
+ * based on of_videomode.c by Sascha Hauer <s.hauer at pengutronix.de>
+ *
+ * This file is released under the GPLv2
+ */
+#include <common.h>
+#include <of.h>
+#include <fb.h>
+#include <malloc.h>
+
+void display_timings_release(struct display_timings *disp)
+{
+	free(disp->modes);
+	free(disp);
+}
+EXPORT_SYMBOL_GPL(display_timings_release);
+
+/**
+ * parse_timing_property - parse timing_entry from device_node
+ * @np: device_node with the property
+ * @name: name of the property
+ * @result: will be set to the return value
+ *
+ * DESCRIPTION:
+ * Every display_timing can be specified with either just the typical value or
+ * a range consisting of min/typ/max. This function helps handling this
+ **/
+static int parse_timing_property(const struct device_node *np, const char *name,
+			  u32 *res)
+{
+	struct property *prop;
+	int length, cells, ret;
+
+	prop = of_find_property(np, name, &length);
+	if (!prop) {
+		pr_err("%s: could not find property %s\n",
+			np->full_name, name);
+		return -EINVAL;
+	}
+
+	cells = length / sizeof(u32);
+	if (cells == 1) {
+		ret = of_property_read_u32(np, name, res);
+	} else {
+		pr_err("%s: illegal timing specification in %s\n",
+			np->full_name, name);
+		return -EINVAL;
+	}
+
+	return ret;
+}
+
+/**
+ * of_parse_display_timing - parse display_timing entry from device_node
+ * @np: device_node with the properties
+ **/
+static int of_parse_display_timing(const struct device_node *np,
+		struct fb_videomode *mode)
+{
+	u32 val = 0, pixelclock = 0;
+	int ret = 0;
+
+	memset(mode, 0, sizeof(*mode));
+
+	ret |= parse_timing_property(np, "hback-porch", &mode->left_margin);
+	ret |= parse_timing_property(np, "hfront-porch", &mode->right_margin);
+	ret |= parse_timing_property(np, "hactive", &mode->xres);
+	ret |= parse_timing_property(np, "hsync-len", &mode->hsync_len);
+	ret |= parse_timing_property(np, "vback-porch", &mode->upper_margin);
+	ret |= parse_timing_property(np, "vfront-porch", &mode->lower_margin);
+	ret |= parse_timing_property(np, "vactive", &mode->yres);
+	ret |= parse_timing_property(np, "vsync-len", &mode->vsync_len);
+	ret |= parse_timing_property(np, "clock-frequency", &pixelclock);
+
+	mode->pixclock = pixelclock ? KHZ2PICOS(pixelclock / 1000) : 0;
+
+	if (!of_property_read_u32(np, "vsync-active", &val))
+		mode->sync |= val ? FB_SYNC_VERT_HIGH_ACT : 0;
+	if (!of_property_read_u32(np, "hsync-active", &val))
+		mode->sync |= val ? FB_SYNC_HOR_HIGH_ACT : 0;
+	if (!of_property_read_u32(np, "de-active", &val))
+		mode->display_flags |= val ? DISPLAY_FLAGS_DE_HIGH :
+				DISPLAY_FLAGS_DE_LOW;
+	if (!of_property_read_u32(np, "pixelclk-active", &val))
+		mode->display_flags |= val ? DISPLAY_FLAGS_PIXDATA_POSEDGE :
+				DISPLAY_FLAGS_PIXDATA_NEGEDGE;
+
+	if (ret) {
+		pr_err("%s: error reading timing properties\n",
+			np->full_name);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+/**
+ * of_get_display_timing - parse a display_timing entry
+ * @np: device_node with the timing subnode
+ * @name: name of the timing node
+ * @dt: display_timing struct to fill
+ **/
+int of_get_display_timing(struct device_node *np, const char *name,
+		struct fb_videomode *mode)
+{
+	struct device_node *timing_np;
+
+	if (!np) {
+		pr_err("%s: no devicenode given\n", np->full_name);
+		return -EINVAL;
+	}
+
+	timing_np = of_get_child_by_name(np, name);
+	if (!timing_np) {
+		pr_err("%s: could not find node '%s'\n",
+			np->full_name, name);
+		return -ENOENT;
+	}
+
+	return of_parse_display_timing(timing_np, mode);
+}
+EXPORT_SYMBOL_GPL(of_get_display_timing);
+
+/**
+ * of_get_display_timings - parse all display_timing entries from a device_node
+ * @np: device_node with the subnodes
+ **/
+struct display_timings *of_get_display_timings(struct device_node *np)
+{
+	struct device_node *timings_np;
+	struct device_node *entry;
+	struct device_node *native_mode;
+	struct display_timings *disp;
+
+	if (!np) {
+		pr_err("%s: no device node given\n", np->full_name);
+		return NULL;
+	}
+
+	timings_np = of_get_child_by_name(np, "display-timings");
+	if (!timings_np) {
+		pr_debug("%s: could not find display-timings node\n",
+			np->full_name);
+		return NULL;
+	}
+
+	disp = xzalloc(sizeof(*disp));
+
+	entry = of_parse_phandle(timings_np, "native-mode", 0);
+	/* assume first child as native mode if none provided */
+	if (!entry)
+		entry = of_get_next_available_child(np, NULL);
+	/* if there is no child, it is useless to go on */
+	if (!entry) {
+		pr_err("%s: no timing specifications given\n",
+			np->full_name);
+		goto entryfail;
+	}
+
+	pr_debug("%s: using %s as default timing\n",
+		np->full_name, entry->name);
+
+	native_mode = entry;
+
+	disp->num_modes = of_get_child_count(timings_np);
+	if (disp->num_modes == 0) {
+		/* should never happen, as entry was already found above */
+		pr_err("%s: no timings specified\n", np->full_name);
+		goto entryfail;
+	}
+
+	disp->modes = xzalloc(sizeof(struct fb_videomode) * disp->num_modes);
+
+	disp->num_modes = 0;
+	disp->native_mode = 0;
+
+	for_each_child_of_node(timings_np, entry) {
+		struct fb_videomode *mode;
+		int r;
+
+		mode = &disp->modes[disp->num_modes];
+
+		r = of_parse_display_timing(entry, mode);
+		if (r) {
+			/*
+			 * to not encourage wrong devicetrees, fail in case of
+			 * an error
+			 */
+			pr_err("%s: error in timing %d\n",
+				np->full_name, disp->num_modes + 1);
+			goto timingfail;
+		}
+
+		mode->name = xstrdup(entry->name);
+
+		if (native_mode == entry)
+			disp->native_mode = disp->num_modes;
+
+		disp->num_modes++;
+	}
+
+	pr_debug("%s: got %d timings. Using timing #%d as default\n",
+		np->full_name, disp->num_modes,
+		disp->native_mode + 1);
+
+	return disp;
+
+timingfail:
+	display_timings_release(disp);
+entryfail:
+	free(disp);
+
+	return NULL;
+}
+EXPORT_SYMBOL_GPL(of_get_display_timings);
+
+/**
+ * of_display_timings_exist - check if a display-timings node is provided
+ * @np: device_node with the timing
+ **/
+int of_display_timings_exist(struct device_node *np)
+{
+	struct device_node *timings_np;
+
+	if (!np)
+		return -EINVAL;
+
+	timings_np = of_parse_phandle(np, "display-timings", 0);
+	if (!timings_np)
+		return -EINVAL;
+
+	return 1;
+}
+EXPORT_SYMBOL_GPL(of_display_timings_exist);
diff --git a/include/fb.h b/include/fb.h
index 91d3fe4..8d255c0 100644
--- a/include/fb.h
+++ b/include/fb.h
@@ -32,6 +32,16 @@
 #define PICOS2KHZ(a) (1000000000UL/(a))
 #define KHZ2PICOS(a) (1000000000UL/(a))
 
+enum display_flags {
+	/* data enable flag */
+	DISPLAY_FLAGS_DE_LOW		= BIT(4),
+	DISPLAY_FLAGS_DE_HIGH		= BIT(5),
+	/* drive data on pos. edge */
+	DISPLAY_FLAGS_PIXDATA_POSEDGE	= BIT(6),
+	/* drive data on neg. edge */
+	DISPLAY_FLAGS_PIXDATA_NEGEDGE	= BIT(7),
+};
+
 struct fb_videomode {
 	const char *name;	/* optional */
 	u32 refresh;		/* optional */
@@ -46,7 +56,7 @@ struct fb_videomode {
 	u32 vsync_len;
 	u32 sync;
 	u32 vmode;
-	u32 flag;
+	u32 display_flags;
 };
 
 /* Interpretation of offset for color fields: All offsets are from the right,
@@ -125,6 +135,8 @@ struct fb_info {
 					 */
 };
 
+struct display_timings *of_get_display_timings(struct device_node *np);
+
 int register_framebuffer(struct fb_info *info);
 
 #define FBIOGET_SCREENINFO	_IOR('F', 1, loff_t)
-- 
1.9.0



From s.hauer at pengutronix.de  Fri Mar 14 10:32:22 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 14 Mar 2014 15:32:22 +0100
Subject: [PATCH 02/29] ARM: i.MX6: Add initial variscite VAR-SOM-MX6 CPU
 support
In-Reply-To: <1394807569-23620-1-git-send-email-s.hauer@pengutronix.de>
References: <1394807569-23620-1-git-send-email-s.hauer@pengutronix.de>
Message-ID: <1394807569-23620-3-git-send-email-s.hauer@pengutronix.de>

The VAR-SOM-MX6 is a System on module from Variscite, see:

http://www.variscite.com/products/system-on-module-som/cortex-a9/var-som-mx6-cpu-freescale-imx6

This adds support for this module on the VAR-MX6CustomBoard baseboard.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/boards/Makefile                           |   1 +
 arch/arm/boards/variscite-mx6/Makefile             |   3 +
 arch/arm/boards/variscite-mx6/board.c              | 135 +++++++++++++++++++
 .../variscite-mx6/flash-header-variscite.imxcfg    |  86 ++++++++++++
 arch/arm/boards/variscite-mx6/lowlevel.c           |  74 ++++++++++
 arch/arm/dts/Makefile                              |   4 +-
 arch/arm/dts/imx6q-var-custom.dts                  | 149 +++++++++++++++++++++
 arch/arm/dts/imx6q-var-som.dtsi                    |  99 ++++++++++++++
 arch/arm/mach-imx/Kconfig                          |   6 +
 images/Makefile.imx                                |   5 +
 10 files changed, 561 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/boards/variscite-mx6/Makefile
 create mode 100644 arch/arm/boards/variscite-mx6/board.c
 create mode 100644 arch/arm/boards/variscite-mx6/flash-header-variscite.imxcfg
 create mode 100644 arch/arm/boards/variscite-mx6/lowlevel.c
 create mode 100644 arch/arm/dts/imx6q-var-custom.dts
 create mode 100644 arch/arm/dts/imx6q-var-som.dtsi

diff --git a/arch/arm/boards/Makefile b/arch/arm/boards/Makefile
index 0d8c9cf..ac85093 100644
--- a/arch/arm/boards/Makefile
+++ b/arch/arm/boards/Makefile
@@ -100,3 +100,4 @@ obj-$(CONFIG_MACH_USB_A9G20)			+= usb-a926x/
 obj-$(CONFIG_MACH_VERSATILEPB)			+= versatile/
 obj-$(CONFIG_MACH_VEXPRESS)			+= vexpress/
 obj-$(CONFIG_MACH_ZEDBOARD)			+= avnet-zedboard/
+obj-$(CONFIG_MACH_VARISCITE_MX6)		+= variscite-mx6/
diff --git a/arch/arm/boards/variscite-mx6/Makefile b/arch/arm/boards/variscite-mx6/Makefile
new file mode 100644
index 0000000..35b114b
--- /dev/null
+++ b/arch/arm/boards/variscite-mx6/Makefile
@@ -0,0 +1,3 @@
+obj-y += board.o flash-header-variscite.dcd.o
+extra-y += flash-header-variscite.dcd.S flash-header-variscite.dcd
+lwl-y += lowlevel.o
diff --git a/arch/arm/boards/variscite-mx6/board.c b/arch/arm/boards/variscite-mx6/board.c
new file mode 100644
index 0000000..592b111
--- /dev/null
+++ b/arch/arm/boards/variscite-mx6/board.c
@@ -0,0 +1,135 @@
+/*
+ * Copyright (C) 2013 Michael Burkey
+ * Based on code (C) Sascha Hauer, Pengutronix
+ * Based on code (C) Variscite, Ltd.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation.
+ *
+ */
+
+#define pr_fmt(fmt) "var-som-mx6: " fmt
+
+#include <common.h>
+#include <gpio.h>
+#include <init.h>
+#include <of.h>
+#include <debug_ll.h>
+
+#include <environment.h>
+#include <asm/armlinux.h>
+#include <generated/mach-types.h>
+#include <partition.h>
+#include <asm/io.h>
+#include <asm/mmu.h>
+#include <mach/generic.h>
+#include <sizes.h>
+#include <mach/imx6.h>
+#include <mach/devices-imx6.h>
+#include <mach/iomux-mx6.h>
+#include <spi/spi.h>
+#include <mach/spi.h>
+#include <i2c/i2c.h>
+
+#define ETH_PHY_RST	IMX_GPIO_NR(1, 25)
+
+static int setup_pmic_voltages(void)
+{
+	unsigned char value, rev_id = 0 ;
+	struct i2c_adapter *adapter = NULL;
+	struct i2c_client client;
+	int addr = -1, ret, bus = 0;
+
+	/* I2C2 bus (2-1 = 1 in barebox numbering) */
+	bus = 1;
+
+	/* PFUZE100 device address is 0x08 */
+	addr = 0x08;
+
+	adapter = i2c_get_adapter(bus);
+	if (!adapter) {
+		pr_err("i2c bus %d not found\n", bus);
+		return -ENODEV;
+	}
+
+	client.adapter = adapter;
+	client.addr = addr;
+
+	/* Attempt to locate the PFUZE100 chip. */
+	if (i2c_read_reg(&client, 0x00, &value, 1) != 1) {
+		pr_err("Read device ID error!\n");
+		return -1;
+	}
+	if (i2c_read_reg(&client, 0x03, &rev_id, 1) != 1) {
+		pr_err("Read Rev ID error!\n");
+		return -1;
+	}
+
+	pr_info("Found PFUZE100! deviceid=%x,revid=%x\n", value, rev_id);
+
+	/* Set Gigabit Ethernet voltage (SOM v1.1/1.0)*/
+        value = 0x60;
+	ret = i2c_write_reg(&client, 0x4a, &value, 1);
+
+	/* set VGEN3 to 2.5V */
+	value = 0x77;
+	if (i2c_write_reg(&client, 0x6e, &value, 1) != 1) {
+		pr_err("Set VGEN3 error!\n");
+		return -EIO;
+	}
+
+	return 0;
+}
+
+static int eth_phy_reset(void)
+{
+	gpio_request(ETH_PHY_RST, "phy reset");
+	gpio_direction_output(ETH_PHY_RST, 0);
+	mdelay(1);
+	gpio_set_value(ETH_PHY_RST, 1);
+
+	return 0;
+}
+
+static int variscite_custom_init(void)
+{
+	if (!of_machine_is_compatible("variscite,imx6q-custom"))
+		return 0;
+
+	barebox_set_hostname("var-som-mx6");
+
+	setup_pmic_voltages();
+
+	eth_phy_reset();
+
+	armlinux_set_architecture(MACH_TYPE_VAR_SOM_MX6);
+
+	pr_debug("Completing custom_init()\n");
+
+	return 0;
+}
+device_initcall(variscite_custom_init);
+
+static int variscite_custom_core_init(void)
+{
+	if (!of_machine_is_compatible("variscite,imx6q-custom"))
+		return 0;
+
+	imx6_init_lowlevel();
+
+	pr_debug("Completing custom_core_init()\n");
+
+	return 0;
+}
+postcore_initcall(variscite_custom_core_init);
diff --git a/arch/arm/boards/variscite-mx6/flash-header-variscite.imxcfg b/arch/arm/boards/variscite-mx6/flash-header-variscite.imxcfg
new file mode 100644
index 0000000..ed21057
--- /dev/null
+++ b/arch/arm/boards/variscite-mx6/flash-header-variscite.imxcfg
@@ -0,0 +1,86 @@
+loadaddr 0x10000000
+soc imx6
+dcdofs 0x400
+wm 32 0x020e0798 0x000C0000
+wm 32 0x020e0758 0x00000000
+wm 32 0x020e0588 0x00000030
+wm 32 0x020e0594 0x00000030
+wm 32 0x020e056c 0x00000030
+wm 32 0x020e0578 0x00000030
+wm 32 0x020e074c 0x00000030
+wm 32 0x020e057c 0x00000030
+wm 32 0x020e058c 0x00000000
+wm 32 0x020e059c 0x00000030
+wm 32 0x020e05a0 0x00000030
+wm 32 0x020e078c 0x00000030
+wm 32 0x020e0750 0x00020000
+wm 32 0x020e05a8 0x00000030
+wm 32 0x020e05b0 0x00000030
+wm 32 0x020e0524 0x00000030
+wm 32 0x020e051c 0x00000030
+wm 32 0x020e0518 0x00000030
+wm 32 0x020e050c 0x00000030
+wm 32 0x020e05b8 0x00000030
+wm 32 0x020e05c0 0x00000030
+wm 32 0x020e0774 0x00020000
+wm 32 0x020e0784 0x00000030
+wm 32 0x020e0788 0x00000030
+wm 32 0x020e0794 0x00000030
+wm 32 0x020e079c 0x00000030
+wm 32 0x020e07a0 0x00000030
+wm 32 0x020e07a4 0x00000030
+wm 32 0x020e07a8 0x00000030
+wm 32 0x020e0748 0x00000030
+wm 32 0x020e05ac 0x00000030
+wm 32 0x020e05b4 0x00000030
+wm 32 0x020e0528 0x00000030
+wm 32 0x020e0520 0x00000030
+wm 32 0x020e0514 0x00000030
+wm 32 0x020e0510 0x00000030
+wm 32 0x020e05bc 0x00000030
+wm 32 0x020e05c4 0x00000030
+wm 32 0x021b0800 0xA1390003
+wm 32 0x021b080c 0x001F001F
+wm 32 0x021b0810 0x001F001F
+wm 32 0x021b480c 0x001F001F
+wm 32 0x021b4810 0x001F001F
+wm 32 0x021b083c 0x4333033F
+wm 32 0x021b0840 0x032C031D
+wm 32 0x021b483c 0x43200332
+wm 32 0x021b4840 0x031A026A
+wm 32 0x021b0848 0x4D464746
+wm 32 0x021b4848 0x47453F4D
+wm 32 0x021b0850 0x3E434440
+wm 32 0x021b4850 0x47384839
+wm 32 0x021b081c 0x33333333
+wm 32 0x021b0820 0x33333333
+wm 32 0x021b0824 0x33333333
+wm 32 0x021b0828 0x33333333
+wm 32 0x021b481c 0x33333333
+wm 32 0x021b4820 0x33333333
+wm 32 0x021b4824 0x33333333
+wm 32 0x021b4828 0x33333333
+wm 32 0x021b08b8 0x00000800
+wm 32 0x021b48b8 0x00000800
+wm 32 0x021b0004 0x00020036
+wm 32 0x021b0008 0x09444040
+wm 32 0x021b000c 0x555A7975
+wm 32 0x021b0010 0xFF538F64
+wm 32 0x021b0014 0x01FF00DB
+wm 32 0x021b0018 0x00001740
+wm 32 0x021b001c 0x00008000
+wm 32 0x021b002c 0x000026D2
+wm 32 0x021b0030 0x005A1023
+wm 32 0x021b0040 0x00000027
+wm 32 0x021b0000 0x831A0000
+wm 32 0x021b001c 0x04088032
+wm 32 0x021b001c 0x00008033
+wm 32 0x021b001c 0x00048031
+wm 32 0x021b001c 0x09408030
+wm 32 0x021b001c 0x04008040
+wm 32 0x021b0020 0x00005800
+wm 32 0x021b0818 0x00011117
+wm 32 0x021b4818 0x00011117
+wm 32 0x021b0004 0x00025576
+wm 32 0x021b0404 0x00011006
+wm 32 0x021b001c 0x00000000
diff --git a/arch/arm/boards/variscite-mx6/lowlevel.c b/arch/arm/boards/variscite-mx6/lowlevel.c
new file mode 100644
index 0000000..e93e874
--- /dev/null
+++ b/arch/arm/boards/variscite-mx6/lowlevel.c
@@ -0,0 +1,74 @@
+/*
+ *
+ * Copyright (C) 2013 Michael Burkey
+ * Based on code by Sascha Hauer <s.hauer at pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+#include <debug_ll.h>
+#include <common.h>
+#include <sizes.h>
+#include <io.h>
+#include <asm/barebox-arm-head.h>
+#include <asm/barebox-arm.h>
+#include <asm/sections.h>
+#include <asm/cache.h>
+#include <asm/mmu.h>
+#include <mach/imx6-mmdc.h>
+#include <mach/imx6.h>
+
+static inline void setup_uart(void)
+{
+	void __iomem *ccmbase = (void *)MX6_CCM_BASE_ADDR;
+	void __iomem *uartbase = (void *)MX6_UART1_BASE_ADDR;
+	void __iomem *iomuxbase = (void *)MX6_IOMUXC_BASE_ADDR;
+
+	writel(0x03, iomuxbase + 0x0280);
+	writel(0x03, iomuxbase + 0x0284);
+
+	writel(0xffffffff, ccmbase + 0x68);
+	writel(0xffffffff, ccmbase + 0x6c);
+	writel(0xffffffff, ccmbase + 0x70);
+	writel(0xffffffff, ccmbase + 0x74);
+	writel(0xffffffff, ccmbase + 0x78);
+	writel(0xffffffff, ccmbase + 0x7c);
+	writel(0xffffffff, ccmbase + 0x80);
+
+	writel(0x00000000, uartbase + 0x80);
+	writel(0x00004027, uartbase + 0x84);
+	writel(0x00000704, uartbase + 0x88);
+	writel(0x00000a81, uartbase + 0x90);
+	writel(0x0000002b, uartbase + 0x9c);
+	writel(0x00013880, uartbase + 0xb0);
+	writel(0x0000047f, uartbase + 0xa4);
+	writel(0x0000c34f, uartbase + 0xa8);
+	writel(0x00000001, uartbase + 0x80);
+
+	putc_ll('>');
+}
+extern char __dtb_imx6q_var_custom_start[];
+
+ENTRY_FUNCTION(start_variscite_custom, r0, r1, r2)
+{
+	uint32_t fdt;
+
+	arm_cpu_lowlevel_init();
+
+	arm_setup_stack(0x00920000 - 8);
+
+	if (IS_ENABLED(CONFIG_DEBUG_LL))
+	    setup_uart();
+
+	fdt = (uint32_t)__dtb_imx6q_var_custom_start - get_runtime_offset();
+
+	barebox_arm_entry(0x10000000, SZ_1G, fdt);
+}
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 6bac3b9..d42fde9 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -25,7 +25,8 @@ dtb-$(CONFIG_ARCH_IMX6) += imx6q-gk802.dtb \
 	imx6q-guf-santaro.dtb \
 	imx6q-nitrogen6x.dtb \
 	imx6dl-nitrogen6x.dtb \
-	imx6q-udoo.dtb
+	imx6q-udoo.dtb \
+	imx6q-var-custom.dtb
 dtb-$(CONFIG_ARCH_MVEBU) += dove-cubox-bb.dtb
 dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_cyclone5_sockit.dtb \
 	socfpga_cyclone5_socrates.dtb
@@ -60,6 +61,7 @@ pbl-$(CONFIG_MACH_SABRESD) += imx6q-sabresd.dtb.o
 pbl-$(CONFIG_MACH_GUF_SANTARO) += imx6q-guf-santaro.dtb.o
 pbl-$(CONFIG_MACH_NITROGEN6X) += imx6q-nitrogen6x.dtb.o imx6dl-nitrogen6x.dtb.o
 pbl-$(CONFIG_MACH_UDOO) += imx6q-udoo.dtb.o
+pbl-$(CONFIG_MACH_VARISCITE_MX6) += imx6q-var-custom.dtb.o
 
 .SECONDARY: $(obj)/$(BUILTIN_DTB).dtb.S
 .SECONDARY: $(patsubst %,$(obj)/%.S,$(dtb-y))
diff --git a/arch/arm/dts/imx6q-var-custom.dts b/arch/arm/dts/imx6q-var-custom.dts
new file mode 100644
index 0000000..bb1193f
--- /dev/null
+++ b/arch/arm/dts/imx6q-var-custom.dts
@@ -0,0 +1,149 @@
+/*
+ * Copyright 2013 Michael Burkey
+ * Based on code written by Christian Hemp, Phytec Messtechnik GmbH
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ *
+ *
+ * 		environment at 0 {
+			compatible = "barebox,environment";
+			device-path = &usdhc2, "partname:barebox-environment";
+		};
+
+ *
+ */
+
+/dts-v1/;
+#include "imx6q-var-som.dtsi"
+
+/ {
+	model = "Variscite i.MX6 Quad Custom Carrier-Board";
+	compatible = "variscite,imx6q-custom", "variscite,imx6q-som", "fsl,imx6q";
+
+	chosen {
+		linux,stdout-path = &uart1;
+
+		environment at 0 {
+			compatible = "barebox,environment";
+			device-path = &gpmi, "partname:barebox-environment";
+		};
+
+	};
+};
+
+&iomuxc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_hog>;
+
+	imx6q-variscite-custom {
+		pinctrl_i2c1: i2c1grp {
+			fsl,pins = <MX6QDL_I2C1_PINGRP1>;
+		};
+
+		pinctrl_i2c3: i2c3grp {
+			fsl,pins = <MX6QDL_I2C3_PINGRP3>;
+		};
+
+		pinctrl_usdhc2: usdhc2grp {
+			fsl,pins = <MX6QDL_USDHC2_PINGRP_D4>;
+		};
+
+		pinctrl_usdhc2_cd: usdhc2cd {
+			fsl,pins = <
+				MX6QDL_PAD_KEY_COL4__GPIO4_IO14	 0x80000000
+				MX6QDL_PAD_KEY_ROW4__GPIO4_IO15	 0x80000000
+			>;
+		};
+
+		pinctrl_uart1: uart1grp {
+			fsl,pins = <MX6QDL_UART1_PINGRP1>;
+		};
+	};
+};
+
+&ldb {
+	status = "okay";
+
+	lvds-channel at 0 {
+		fsl,data-mapping = "spwg";
+		fsl,data-width = <24>;
+		status = "okay";
+		display-timings {
+			native-mode = &claawvga;
+			claawvga: claawvga {
+				native-mode;
+				clock-frequency = <35714000>;
+				hactive = <800>;
+				vactive = <480>;
+				hback-porch = <28>;
+				hfront-porch = <17>;
+				vback-porch = <13>;
+				vfront-porch = <20>;
+				hsync-len = <20>;
+				vsync-len = <13>;
+			};
+		};
+	};
+};
+
+&uart1 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart1>;
+};
+
+&usdhc2 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc2>;
+	cd-gpios = <&gpio4 14 0>;
+	wp-gpios = <&gpio4 15 0>;
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	partition at 0 {
+		label = "barebox";
+		reg = <0x0 0x200000>;
+	};
+
+	partition at 1 {
+		label = "barebox-environment";
+		reg = <0x200000 0x20000>;
+	};
+
+	partition at 2 {
+		label = "kernel";
+		reg = <0x220000 0x600000>;
+	};
+
+	partition at 3 {
+		label = "rootfs";
+		reg = <0x820000 0x18000000>;
+	};
+};
+
+&usbh1 {
+	status = "okay";
+	disable-over-current;
+	dr_mode = "host";
+	phy_type = "utmi";
+};
+
+&i2c1 {
+	status = "okay";
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c1>;
+};
+
+&i2c3 {
+	status = "okay";
+	clock-frequency = <1000000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c3>;
+};
diff --git a/arch/arm/dts/imx6q-var-som.dtsi b/arch/arm/dts/imx6q-var-som.dtsi
new file mode 100644
index 0000000..f423f27
--- /dev/null
+++ b/arch/arm/dts/imx6q-var-som.dtsi
@@ -0,0 +1,99 @@
+/*
+ * Copyright 2013 Michael Burkey
+ * Based on code written by Christian Hemp, Phytec Messtechnik GmbH
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include "imx6q.dtsi"
+
+/ {
+	model = "Variscite i.MX6 Quad SOM";
+	compatible = "variscite,imx6q-som", "fsl,imx6q";
+
+	memory {
+		reg = <0x10000000 0x40000000>;
+	};
+};
+
+&fec {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_enet>;
+	phy-mode = "rgmii";
+	status = "okay";
+};
+
+&gpmi {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_gpmi_nand>;
+	nand-on-flash-bbt;
+	status = "okay";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	partition at 0 {
+		label = "barebox";
+		reg = <0x0 0x200000>;
+	};
+
+	partition at 1 {
+		label = "barebox-environment";
+		reg = <0x200000 0x20000>;
+	};
+
+	partition at 2 {
+		label = "kernel";
+		reg = <0x220000 0x600000>;
+	};
+
+	partition at 3 {
+		label = "rootfs";
+		reg = <0x820000 0x1F7E0000>;
+	};
+};
+
+&hdmi {
+	status = "okay";
+	ddc-i2c-bus = <&i2c2>;
+};
+
+&i2c2 {
+	status = "okay";
+	clock-frequency = <1000000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c2>;
+};
+
+&iomuxc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_hog>;
+
+	imx6q-variscite-som {
+		pinctrl_hog: hoggrp {
+			fsl,pins = <
+				MX6QDL_PAD_GPIO_0__CCM_CLKO1	0x80000000
+				MX6QDL_PAD_GPIO_3__CCM_CLKO2	0x80000000
+			>;
+		};
+
+		pinctrl_enet: enetgrp {
+			fsl,pins = <
+				MX6QDL_ENET_PINGRP_RGMII_MD(0x1b0b0, 0x1b0b0)
+				MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x80000000		/* KSZ9031 PHY Reset */
+			  >;
+		};
+
+		pinctrl_gpmi_nand: gpmigrp {
+			fsl,pins = <MX6QDL_GPMI_NAND_PINGRP1>;
+		};
+
+		pinctrl_i2c2: i2c2grp {
+			fsl,pins = <MX6QDL_I2C2_PINGRP2>;
+		};
+	};
+};
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index b7e7533..b242716 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -39,6 +39,7 @@ config ARCH_TEXT_BASE
 	default 0x4fc00000 if MACH_PHYTEC_PFLA02
 	default 0x4fc00000 if MACH_DFI_FS700_M60
 	default 0x4fc00000 if MACH_UDOO
+	default 0x4fc00000 if MACH_VARISCITE_MX6
 
 config ARCH_IMX_INTERNAL_BOOT
 	bool "support internal boot mode"
@@ -247,6 +248,11 @@ config MACH_UDOO
 	bool "Freescale i.MX6 UDOO Board"
 	select ARCH_IMX6
 
+config MACH_VARISCITE_MX6
+	bool "Variscite i.MX6 Quad SOM"
+	select ARCH_IMX6
+
+
 endif
 
 # ----------------------------------------------------------
diff --git a/images/Makefile.imx b/images/Makefile.imx
index 5b650de..6754a3f 100644
--- a/images/Makefile.imx
+++ b/images/Makefile.imx
@@ -143,3 +143,8 @@ pblx-$(CONFIG_MACH_UDOO) += start_imx6_udoo
 CFG_start_imx6_udoo.pblx.imximg = $(board)/udoo/flash-header-mx6-udoo.imxcfg
 FILE_barebox-udoo-imx6q.img = start_imx6_udoo.pblx.imximg
 image-$(CONFIG_MACH_UDOO) += barebox-udoo-imx6q.img
+
+pblx-$(CONFIG_MACH_VARISCITE_MX6) += start_variscite_custom
+CFG_start_variscite_custom.pblx.imximg = $(board)/variscite-mx6/flash-header-variscite.imxcfg
+FILE_barebox-variscite-custom.img = start_variscite_custom.pblx.imximg
+image-$(CONFIG_MACH_VARISCITE_MX6) += barebox-variscite-custom.img
-- 
1.9.0



From alex.aring at gmail.com  Fri Mar 14 12:01:33 2014
From: alex.aring at gmail.com (Alexander Aring)
Date: Fri, 14 Mar 2014 17:01:33 +0100
Subject: [PATCH 6/6] ARM: pfla02: Set new ethernet phy tx timings
In-Reply-To: <1394803820-29277-7-git-send-email-s.hauer@pengutronix.de>
References: <1394803820-29277-1-git-send-email-s.hauer@pengutronix.de>
 <1394803820-29277-7-git-send-email-s.hauer@pengutronix.de>
Message-ID: <20140314160132.GA7755@omega>

On Fri, Mar 14, 2014 at 02:30:20PM +0100, Sascha Hauer wrote:
> From: Christian Hemp <c.hemp at phytec.de>
> 
> TX_CLK line is approx. 54mm longer than other TX lines which adds
> a delay of 0.36ns. RGMII need a delay of min. 1.0ns. This mean we have to add
> a delay of 0.64ns. We choose 0.78 to have a little gap. This can be done by
> setting GTX pad skew value to 11100
>  => Set register 2.8 (RGMII Clock Pad Skew) to 0x038F.
> 
> Signed-off-by: Christian Hemp <c.hemp at phytec.de>
> ---
>  arch/arm/boards/phytec-phyflex-imx6/board.c | 20 ++++++++++++++++++++
>  1 file changed, 20 insertions(+)
> 
> diff --git a/arch/arm/boards/phytec-phyflex-imx6/board.c b/arch/arm/boards/phytec-phyflex-imx6/board.c
> index f510407..3db88da 100644
> --- a/arch/arm/boards/phytec-phyflex-imx6/board.c
> +++ b/arch/arm/boards/phytec-phyflex-imx6/board.c
> @@ -21,6 +21,9 @@
>  #include <gpio.h>
>  #include <init.h>
>  #include <of.h>
> +#include <fec.h>
> +
> +#include <linux/micrel_phy.h>
>  
>  #include <mach/imx6.h>
>  
> @@ -36,6 +39,21 @@ static int eth_phy_reset(void)
>  	return 0;
>  }
>  
> +static void mmd_write_reg(struct phy_device *dev, int device, int reg, int val)
> +{
> +	phy_write(dev, 0x0d, device);
> +	phy_write(dev, 0x0e, reg);
> +	phy_write(dev, 0x0d, (1 << 14) | device);
> +	phy_write(dev, 0x0e, val);
> +}
> +
> +static int ksz9031rn_phy_fixup(struct phy_device *dev)
> +{
> +	mmd_write_reg(dev, 2, 8, 0x039F);
> +
commit msg says 0x038F and here is 0x039F. Which one is correct now?

- Alex


From shc_work at mail.ru  Fri Mar 14 12:06:41 2014
From: shc_work at mail.ru (=?UTF-8?B?QWxleGFuZGVyIFNoaXlhbg==?=)
Date: Fri, 14 Mar 2014 20:06:41 +0400
Subject: =?UTF-8?B?UmU6IFtQQVRDSCAxMy8yOV0gY2xrOiBpbnRyb2R1Y2UgQ0xLX1NFVF9SQVRF?=
 =?UTF-8?B?X1BBUkVOVCBmbGFn?=
In-Reply-To: <1394807569-23620-14-git-send-email-s.hauer@pengutronix.de>
References: <1394807569-23620-1-git-send-email-s.hauer@pengutronix.de>
 <1394807569-23620-14-git-send-email-s.hauer@pengutronix.de>
Message-ID: <1394813201.850386421@f81.i.mail.ru>

???????, 14 ????? 2014, 15:32 +01:00 ?? Sascha Hauer <s.hauer at pengutronix.de>:
> Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
> ---
>  include/linux/clk.h | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/include/linux/clk.h b/include/linux/clk.h
> index 7e5010a..2704b0f 100644
> --- a/include/linux/clk.h
> +++ b/include/linux/clk.h
> @@ -196,6 +196,9 @@ static inline int clk_set_rate(struct clk *clk, unsigned long rate)
>  #endif
>  
>  #ifdef CONFIG_COMMON_CLK
> +
> +#define CLK_SET_RATE_PARENT     (1 << 0) /* propagate rate change up one level */

Lets do it same value as in the kernel, ie  CLK_SET_RATE_PARENT BIT(2)

---

From M.Stam at fugro.nl  Fri Mar 14 13:01:08 2014
From: M.Stam at fugro.nl (Stam, Michel [FINT])
Date: Fri, 14 Mar 2014 18:01:08 +0100
Subject: Barebox x86 IDE support
Message-ID: <C89EFD3CD56F64468D3D206D683A8D22030ADB06@ldam-msx2.fugro-nl.local>

Dear list,

While working on barebox recently, I decided to port a couple of patches ?I made to an old barebox tree a few years ago, to fix the IDE ports on the x86 platform.

I had to work on the resource allocation a bit, as the current GIT repository does not allow IORESOURCE_IO type to be passed to dev_request_region( ) and friends. I tried to keep the interface the same as much as possible by using macros etc.
Please find that attached in 0001-common-driver-Allow-for-I-O-mapped-I-O-in-resource-r.patch. 

Next, I added support to the platform IDE interface to use I/O-mapped I/O, and added the necessary allocation to the generic_pc board.

I did have to add a call to ata_port_detect( ) to ide_port_register to actually get the drives to be probed. Without it the interface seems to be stuck in some sort of limbo. This patch is in 0002-x86-Add-support-for-IDE-on-the-legacy-I-O-ports.patch.

Lastly, I added an extra serial port to the generic_pc board. Most (legacy) PCs have support for 2 serial ports, it seemed useful to me.

What does puzzle me is that the arch/x86/boot/Kconfig mentions X86_VESA and X86_VGA support, but the files (console_vga.c and console_vesa.c) do not nor have ever existed. Is this a remnant from U-boot v1?

Best regards,

Michel Stam
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From plagnioj at jcrosoft.com  Fri Mar 14 13:11:16 2014
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Fri, 14 Mar 2014 18:11:16 +0100
Subject: [SPAM] [PATCH] splash: Print error message when no renderer is
 found
In-Reply-To: <1394791908-22061-1-git-send-email-s.hauer@pengutronix.de>
References: <1394791908-22061-1-git-send-email-s.hauer@pengutronix.de>
Message-ID: <20140314171116.GE6478@ns203013.ovh.net>

On 11:11 Fri 14 Mar     , Sascha Hauer wrote:
> the splash command silently fails when no renderer is found for
> an image type. Print an error message in this case.
> 
> Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
> ---
>  lib/gui/image_renderer.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/lib/gui/image_renderer.c b/lib/gui/image_renderer.c
> index 78e5777..9c92983 100644
> --- a/lib/gui/image_renderer.c
> +++ b/lib/gui/image_renderer.c
> @@ -23,6 +23,8 @@ static struct image_renderer *get_renderer(void* buf, size_t bufsize)
>  			return ir;
>  	}
>  
> +	printf("No renderer found for filetype %s\n", file_type_to_string(type));

	eprintf?
> +
>  	return NULL;
>  }
>  
> -- 
> 1.9.0
> 
> 
> _______________________________________________
> barebox mailing list
> barebox at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/barebox


From raespi at icid.cu  Fri Mar 14 14:45:05 2014
From: raespi at icid.cu (raespi)
Date: Fri, 14 Mar 2014 14:45:05 -0400
Subject: problem booting with Micron MT29F8G08ABABAWP ...
In-Reply-To: <20140313212810.4179d0c2@e6520eb>
References: <532207C7.9020206@icid.cu> <20140313212810.4179d0c2@e6520eb>
Message-ID: <53234E31.2070300@icid.cu>

Hello again ... diving through the drivers/mtd/nand/nand_base.c code I 
managed to boot with this little modification in the 
nand_flash_detect_onfi() function just before exiting from it:

     if ( mtd->oobsize > 128 )
       mtd->oobsize = 128;

Apparently the only allowed oobsizes are 8, 16, 64 and 128 according to 
the nand_scan_ident() function.  I followed Eric's advice in seeing how 
the i.Mx manages it and it's something like this:

NFC_V3_CONFIG2_SPAS(((mtd->oobsize > 218) ?
             218 : mtd->oobsize) >> 1)

Basically setting it to a value of 218.  I first tried a value of 218 
and it didn't work, with a value of 128 I arrive at the prompt but not 
very cleanly I presume:

nand: ONFI param page 0 valid
OOBSIZE4: 128
nand: ONFI flash detected
nand: NAND device: Manufacturer ID: 0x2c, Chip ID: 0x38 (Micron 
MT29F8G08ABABAWP), 1028
Bad block table found at page 262016, version 0x01
Bad block table found at page 261888, version 0x01

I'm currently having trouble booting the kernel from the 
/dev/nand0.kernel partition, it boots fine from an SD partition meaning 
the boot mechanism in barebox is fine.  Still moving forward ...

On 03/13/2014 04:28 PM, Eric B?nard wrote:
> Hi,
>
> Le Thu, 13 Mar 2014 15:32:23 -0400,
> raespi <raespi at icid.cu> a ?crit :
>> Hi ... I'm using barebox 2014.02.0 to boot with a clone of the mini2440
>> board using the MT29F8G08ABABAWP NAND.
>>
>> I'm getting the following error:
>>
>> barebox 2014.02.0 #1 Thu Mar 13 15:28:57 CDT 2014
>>
>> Board: <NULL>
>> nand: ONFI param page 0 valid
>> nand: ONFI flash detected
>> nand: NAND device: Manufacturer ID: 0x2c, Chip ID: 0x38 (Micron
>> MT29F8G08ABABAWP), 1024
>> nand: No oob scheme defined for oobsize 224
>> BUG: failure at drivers/mtd/nand/nand_base.c:3357/nand_scan_tail()!
>> BUG!
>> no stack data available
>> DIVN_UPLL0
>> MPLLVal [M:61h,P:1h,S:2h]
>> CLKDIVN:7h
>>
>> After this poing the board gets resetted back to the original point.  I
>> can never get to the barebox prompt.
>>
>> Any ideas on how to fix this ??
>>
> you may need to add support for 4k+224 page size to your nand
> controller.
> For example this was done for i.MX in comit
> 632c45795065e6a7471ab82be38e808eb6204341
>
> Eric
>
>




From eric at eukrea.com  Fri Mar 14 16:18:58 2014
From: eric at eukrea.com (Eric =?ISO-8859-1?B?QuluYXJk?=)
Date: Fri, 14 Mar 2014 21:18:58 +0100
Subject: problem booting with Micron MT29F8G08ABABAWP ...
In-Reply-To: <53234E31.2070300@icid.cu>
References: <532207C7.9020206@icid.cu> <20140313212810.4179d0c2@e6520eb>
 <53234E31.2070300@icid.cu>
Message-ID: <20140314211858.05897c4e@e6520eb>

Hello,

Le Fri, 14 Mar 2014 14:45:05 -0400,
raespi <raespi at icid.cu> a ?crit :

> Hello again ... diving through the drivers/mtd/nand/nand_base.c code I 
> managed to boot with this little modification in the 
> nand_flash_detect_onfi() function just before exiting from it:
> 
>      if ( mtd->oobsize > 128 )
>        mtd->oobsize = 128;
> 
then you tell your flash has an OOB of 128 when it has more ...

> Apparently the only allowed oobsizes are 8, 16, 64 and 128 according to 
> the nand_scan_ident() function.  I followed Eric's advice in seeing how 
> the i.Mx manages it and it's something like this:
> 
> NFC_V3_CONFIG2_SPAS(((mtd->oobsize > 218) ?
>              218 : mtd->oobsize) >> 1)
> 
that's specific to the i.MX NAND controller : you need to adapt the
code of _your_ CPU's NAND controller to get it to properly support 4k
page flashes.

Eric


From raespi at icid.cu  Fri Mar 14 16:30:53 2014
From: raespi at icid.cu (raespi)
Date: Fri, 14 Mar 2014 16:30:53 -0400
Subject: problem booting with Micron MT29F8G08ABABAWP ...
In-Reply-To: <20140314211858.05897c4e@e6520eb>
References: <532207C7.9020206@icid.cu>	<20140313212810.4179d0c2@e6520eb>	<53234E31.2070300@icid.cu>
 <20140314211858.05897c4e@e6520eb>
Message-ID: <532366FD.509@icid.cu>

So what I'm understanding here is that it isn't enough to fix an oobsize 
also the 4k support is needed. I'm guessing it's not something so 
trivial then, I'll have to delve in deeper.  Any tips on how to code it 
as simple as possible?? I'm a programmer but I'm not familiarized with 
the inner workings of a NAND flash or how to initialize it from the 
bootloader.

On 03/14/2014 04:18 PM, Eric B?nard wrote:
> Hello,
>
> Le Fri, 14 Mar 2014 14:45:05 -0400,
> raespi <raespi at icid.cu> a ?crit :
>
>> Hello again ... diving through the drivers/mtd/nand/nand_base.c code I
>> managed to boot with this little modification in the
>> nand_flash_detect_onfi() function just before exiting from it:
>>
>>       if ( mtd->oobsize > 128 )
>>         mtd->oobsize = 128;
>>
> then you tell your flash has an OOB of 128 when it has more ...
>
>> Apparently the only allowed oobsizes are 8, 16, 64 and 128 according to
>> the nand_scan_ident() function.  I followed Eric's advice in seeing how
>> the i.Mx manages it and it's something like this:
>>
>> NFC_V3_CONFIG2_SPAS(((mtd->oobsize > 218) ?
>>               218 : mtd->oobsize) >> 1)
>>
> that's specific to the i.MX NAND controller : you need to adapt the
> code of _your_ CPU's NAND controller to get it to properly support 4k
> page flashes.
>
> Eric
>
>




From shc_work at mail.ru  Sun Mar 16 01:23:44 2014
From: shc_work at mail.ru (Alexander Shiyan)
Date: Sun, 16 Mar 2014 09:23:44 +0400
Subject: [PATCH] mci: core: Typo fix in printk specifier
Message-ID: <1394947424-25936-1-git-send-email-shc_work@mail.ru>

Signed-off-by: Alexander Shiyan <shc_work at mail.ru>
---
 drivers/mci/mci-core.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/mci/mci-core.c b/drivers/mci/mci-core.c
index a18b555..1dca0c0 100644
--- a/drivers/mci/mci-core.c
+++ b/drivers/mci/mci-core.c
@@ -1813,7 +1813,7 @@ void mci_of_parse(struct mci_host *host)
 		break;
 	default:
 		dev_err(host->hw_dev,
-			"Invalid \"bus-width\" value %ud!\n", bus_width);
+			"Invalid \"bus-width\" value %u!\n", bus_width);
 	}
 
 	/* f_max is obtained from the optional "max-frequency" property */
-- 
1.8.3.2



From shc_work at mail.ru  Sun Mar 16 04:27:24 2014
From: shc_work at mail.ru (Alexander Shiyan)
Date: Sun, 16 Mar 2014 12:27:24 +0400
Subject: [PATCH] ARM: i.MX27: dts: Separate barebox-specific DT changes
Message-ID: <1394958444-32489-1-git-send-email-shc_work@mail.ru>

To ease DT import from Linux, which is still maintained in-tree, we
separate barebox-specific changes by including the original dts in
a separate DT file. This allows to overlay modifications and keep
clean DT history. Additionally, this patch updates i.MX27 DTS tree.

Signed-off-by: Alexander Shiyan <shc_work at mail.ru>
---
 arch/arm/dts/Makefile                          |   3 +-
 arch/arm/dts/imx27-phytec-phycard-s-rdk-bb.dts |  38 +++++++
 arch/arm/dts/imx27-phytec-phycard-s-rdk.dts    |  39 +++++--
 arch/arm/dts/imx27-phytec-phycard-s-som.dts    | 102 -----------------
 arch/arm/dts/imx27-phytec-phycard-s-som.dtsi   | 103 +++++++++++++++++
 arch/arm/dts/imx27-pingrp.h                    | 151 -------------------------
 arch/arm/dts/imx27.dtsi                        |  59 +++++++++-
 7 files changed, 229 insertions(+), 266 deletions(-)
 create mode 100644 arch/arm/dts/imx27-phytec-phycard-s-rdk-bb.dts
 delete mode 100644 arch/arm/dts/imx27-phytec-phycard-s-som.dts
 create mode 100644 arch/arm/dts/imx27-phytec-phycard-s-som.dtsi
 delete mode 100644 arch/arm/dts/imx27-pingrp.h

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 6bac3b9..8ba31b1 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -3,8 +3,7 @@ dtb-$(CONFIG_ARCH_AM33XX) += \
 	am335x-boneblack.dtb \
 	am335x-phytec-phycore.dtb
 dtb-$(CONFIG_ARCH_IMX25) += imx25-karo-tx25.dtb
-dtb-$(CONFIG_ARCH_IMX27) += imx27-phytec-phycard-s-rdk.dtb \
-	imx27-phytec-phycard-s-som.dtb
+dtb-$(CONFIG_ARCH_IMX27) += imx27-phytec-phycard-s-rdk-bb.dtb
 dtb-$(CONFIG_ARCH_IMX51) += imx51-babbage.dtb \
 	imx51-genesi-efika-sb.dtb
 dtb-$(CONFIG_ARCH_IMX53) += imx53-mba53.dtb \
diff --git a/arch/arm/dts/imx27-phytec-phycard-s-rdk-bb.dts b/arch/arm/dts/imx27-phytec-phycard-s-rdk-bb.dts
new file mode 100644
index 0000000..cecfc5a
--- /dev/null
+++ b/arch/arm/dts/imx27-phytec-phycard-s-rdk-bb.dts
@@ -0,0 +1,38 @@
+/*
+ * Barebox specific DT overlay for Phytec PCA100 RDK
+ */
+
+#include "imx27-phytec-phycard-s-rdk.dts"
+
+/ {
+	chosen {
+		linux,stdout-path = &uart1;
+
+		environment at 0 {
+			compatible = "barebox,environment";
+			device-path = &nfc, "partname:environment";
+		};
+	};
+};
+
+&nfc {
+	partition at 0 {
+		label = "boot";
+		reg = <0x0 0x80000>;
+	};
+
+	partition at 1 {
+		label = "environment";
+		reg = <0x80000 0x80000>;
+	};
+
+	partition at 2 {
+		label = "kernel";
+		reg = <0x100000 0x400000>;
+	};
+
+	partition at 3 {
+		label = "root";
+		reg = <0x500000 0x7b00000>;
+	};
+};
diff --git a/arch/arm/dts/imx27-phytec-phycard-s-rdk.dts b/arch/arm/dts/imx27-phytec-phycard-s-rdk.dts
index fb2b874..3c3964a 100644
--- a/arch/arm/dts/imx27-phytec-phycard-s-rdk.dts
+++ b/arch/arm/dts/imx27-phytec-phycard-s-rdk.dts
@@ -9,7 +9,7 @@
  * http://www.gnu.org/copyleft/gpl.html
  */
 
-#include "imx27-phytec-phycard-s-som.dts"
+#include "imx27-phytec-phycard-s-som.dtsi"
 
 / {
 	model = "Phytec pca100 rapid development kit";
@@ -76,35 +76,54 @@
 &iomuxc {
 	imx27-phycard-s-rdk {
 		pinctrl_i2c1: i2c1grp {
-			fsl,pins = <MX27_I2C2_PINGRP1>;
+			fsl,pins = <
+				MX27_PAD_I2C2_SDA__I2C2_SDA 0x0
+				MX27_PAD_I2C2_SCL__I2C2_SCL 0x0
+			>;
 		};
 
 		pinctrl_owire1: owire1grp {
-			fsl,pins = <MX27_OWIRE1_PINGRP1>;
+			fsl,pins = <
+				MX27_PAD_RTCK__OWIRE 0x0
+			>;
 		};
 
 		pinctrl_sdhc2: sdhc2grp {
-			fsl,pins = <MX27_SDHC2_PINGRP1>;
+			fsl,pins = <
+				MX27_PAD_SD2_CLK__SD2_CLK 0x0
+				MX27_PAD_SD2_CMD__SD2_CMD 0x0
+				MX27_PAD_SD2_D0__SD2_D0 0x0
+				MX27_PAD_SD2_D1__SD2_D1 0x0
+				MX27_PAD_SD2_D2__SD2_D2 0x0
+				MX27_PAD_SD2_D3__SD2_D3 0x0
+				MX27_PAD_SSI3_RXDAT__GPIO3_29 0x0 /* CD */
+			>;
 		};
 
 		pinctrl_uart1: uart1grp {
 			fsl,pins = <
-				MX27_UART1_PINGRP1
-				MX27_UART1_RTSCTS_PINGRP1
+				MX27_PAD_UART1_TXD__UART1_TXD 0x0
+				MX27_PAD_UART1_RXD__UART1_RXD 0x0
+				MX27_PAD_UART1_CTS__UART1_CTS 0x0
+				MX27_PAD_UART1_RTS__UART1_RTS 0x0
 			>;
 		};
 
 		pinctrl_uart2: uart2grp {
 			fsl,pins = <
-				MX27_UART2_PINGRP1
-				MX27_UART2_RTSCTS_PINGRP1
+				MX27_PAD_UART2_TXD__UART2_TXD 0x0
+				MX27_PAD_UART2_RXD__UART2_RXD 0x0
+				MX27_PAD_UART2_CTS__UART2_CTS 0x0
+				MX27_PAD_UART2_RTS__UART2_RTS 0x0
 			>;
 		};
 
 		pinctrl_uart3: uart3grp {
 			fsl,pins = <
-				MX27_UART3_PINGRP1
-				MX27_UART3_RTSCTS_PINGRP1
+				MX27_PAD_UART3_TXD__UART3_TXD 0x0
+				MX27_PAD_UART3_RXD__UART3_RXD 0x0
+				MX27_PAD_UART3_CTS__UART3_CTS 0x0
+				MX27_PAD_UART3_RTS__UART3_RTS 0x0
 			>;
 		};
 	};
diff --git a/arch/arm/dts/imx27-phytec-phycard-s-som.dts b/arch/arm/dts/imx27-phytec-phycard-s-som.dts
deleted file mode 100644
index a48d4e1..0000000
--- a/arch/arm/dts/imx27-phytec-phycard-s-som.dts
+++ /dev/null
@@ -1,102 +0,0 @@
-/*
- * Copyright 2012 Sascha Hauer, Uwe Kleine-K?nig, Steffen Trumtrar
- * and Markus Pargmann, Pengutronix
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-/dts-v1/;
-#include "imx27.dtsi"
-
-/ {
-	model = "Phytec pca100";
-	compatible = "phytec,imx27-pca100", "fsl,imx27";
-
-	chosen {
-		linux,stdout-path = &uart1;
-
-		environment at 0 {
-			compatible = "barebox,environment";
-			device-path = &nfc, "partname:environment";
-		};
-	};
-
-	memory {
-		reg = <0xa0000000 0x08000000>; /* 128MB */
-	};
-};
-
-&cspi1 {
-	fsl,spi-num-chipselects = <2>;
-	cs-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>,
-		   <&gpio4 27 GPIO_ACTIVE_HIGH>;
-	status = "okay";
-};
-
-&iomuxc {
-	imx27-phycard-s-som {
-		pinctrl_fec1: fec1grp {
-			fsl,pins = <MX27_FEC1_PINGRP1>;
-		};
-
-		pinctrl_i2c2: i2c2grp {
-			fsl,pins = <MX27_I2C2_PINGRP1>;
-		};
-
-		pinctrl_nfc: nfcgrp {
-			fsl,pins = <MX27_NFC_PINGRP1>;
-		};
-	};
-};
-
-&fec {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_fec1>;
-	status = "okay";
-};
-
-&i2c2 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_i2c2>;
-	status = "okay";
-
-	at24 at 52 {
-		compatible = "at,24c32";
-		pagesize = <32>;
-		reg = <0x52>;
-	};
-};
-
-&nfc {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_nfc>;
-	nand-bus-width = <8>;
-	nand-ecc-mode = "hw";
-	nand-on-flash-bbt;
-	status = "okay";
-
-	partition at 0 {
-		label = "boot";
-		reg = <0x0 0x80000>;
-	};
-
-	partition at 1 {
-		label = "environment";
-		reg = <0x80000 0x80000>;
-	};
-
-	partition at 2 {
-		label = "kernel";
-		reg = <0x100000 0x400000>;
-	};
-
-	partition at 3 {
-		label = "root";
-		reg = <0x500000 0x7b00000>;
-	};
-};
diff --git a/arch/arm/dts/imx27-phytec-phycard-s-som.dtsi b/arch/arm/dts/imx27-phytec-phycard-s-som.dtsi
new file mode 100644
index 0000000..1b62480
--- /dev/null
+++ b/arch/arm/dts/imx27-phytec-phycard-s-som.dtsi
@@ -0,0 +1,103 @@
+/*
+ * Copyright 2012 Sascha Hauer, Uwe Kleine-K?nig, Steffen Trumtrar
+ * and Markus Pargmann, Pengutronix
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+#include "imx27.dtsi"
+
+/ {
+	model = "Phytec pca100";
+	compatible = "phytec,imx27-pca100", "fsl,imx27";
+
+	memory {
+		reg = <0xa0000000 0x08000000>; /* 128MB */
+	};
+};
+
+&cspi1 {
+	fsl,spi-num-chipselects = <2>;
+	cs-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>,
+		   <&gpio4 27 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+};
+
+&fec {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_fec1>;
+	status = "okay";
+};
+
+&i2c2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c2>;
+	status = "okay";
+
+	at24 at 52 {
+		compatible = "at,24c32";
+		pagesize = <32>;
+		reg = <0x52>;
+	};
+};
+
+&iomuxc {
+	imx27-phycard-s-som {
+		pinctrl_fec1: fec1grp {
+			fsl,pins = <
+				MX27_PAD_SD3_CMD__FEC_TXD0 0x0
+				MX27_PAD_SD3_CLK__FEC_TXD1 0x0
+				MX27_PAD_ATA_DATA0__FEC_TXD2 0x0
+				MX27_PAD_ATA_DATA1__FEC_TXD3 0x0
+				MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0
+				MX27_PAD_ATA_DATA3__FEC_RXD1 0x0
+				MX27_PAD_ATA_DATA4__FEC_RXD2 0x0
+				MX27_PAD_ATA_DATA5__FEC_RXD3 0x0
+				MX27_PAD_ATA_DATA6__FEC_MDIO 0x0
+				MX27_PAD_ATA_DATA7__FEC_MDC 0x0
+				MX27_PAD_ATA_DATA8__FEC_CRS 0x0
+				MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0
+				MX27_PAD_ATA_DATA10__FEC_RXD0 0x0
+				MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0
+				MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0
+				MX27_PAD_ATA_DATA13__FEC_COL 0x0
+				MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0
+				MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0
+			>;
+		};
+
+		pinctrl_i2c2: i2c2grp {
+			fsl,pins = <
+				MX27_PAD_I2C2_SDA__I2C2_SDA 0x0
+				MX27_PAD_I2C2_SCL__I2C2_SCL 0x0
+			>;
+		};
+
+		pinctrl_nfc: nfcgrp {
+			fsl,pins = <
+				MX27_PAD_NFRB__NFRB 0x0
+				MX27_PAD_NFCLE__NFCLE 0x0
+				MX27_PAD_NFWP_B__NFWP_B 0x0
+				MX27_PAD_NFCE_B__NFCE_B 0x0
+				MX27_PAD_NFALE__NFALE 0x0
+				MX27_PAD_NFRE_B__NFRE_B 0x0
+				MX27_PAD_NFWE_B__NFWE_B 0x0
+			>;
+		};
+	};
+};
+
+&nfc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_nfc>;
+	nand-bus-width = <8>;
+	nand-ecc-mode = "hw";
+	nand-on-flash-bbt;
+	status = "okay";
+};
diff --git a/arch/arm/dts/imx27-pingrp.h b/arch/arm/dts/imx27-pingrp.h
deleted file mode 100644
index 57ca02f..0000000
--- a/arch/arm/dts/imx27-pingrp.h
+++ /dev/null
@@ -1,151 +0,0 @@
-/*
- * Copyright 2013 Markus Pargmann <mpa at pengutronix.de>, Pengutronix
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-#ifndef __DTS_IMX27_PINGRP_H
-#define __DTS_IMX27_PINGRP_H
-
-#include "imx27-pinfunc.h"
-
-#define MX27_CSPI1_PINGRP1 \
-	MX27_PAD_CSPI1_MISO__CSPI1_MISO 0x0 \
-	MX27_PAD_CSPI1_MOSI__CSPI1_MOSI 0x0 \
-	MX27_PAD_CSPI1_SCLK__CSPI1_SCLK 0x0
-
-#define MX27_CSPI2_PINGRP1 \
-	MX27_PAD_CSPI2_MISO__CSPI2_MISO 0x0 \
-	MX27_PAD_CSPI2_MOSI__CSPI2_MOSI 0x0 \
-	MX27_PAD_CSPI2_SCLK__CSPI2_SCLK 0x0
-
-#define MX27_CSPI3_PINGRP1 \
-	MX27_PAD_SD1_CLK__CSPI3_SCLK 0x0 \
-	MX27_PAD_SD1_D0__CSPI3_MISO 0x0 \
-	MX27_PAD_SD1_CMD__CSPI3_MOSI 0x0
-
-#define MX27_FB_PINGRP1 \
-	MX27_PAD_CLS__CLS 0x0 \
-	MX27_PAD_CONTRAST__CONTRAST 0x0 \
-	MX27_PAD_LD0__LD0 0x0 \
-	MX27_PAD_LD1__LD1 0x0 \
-	MX27_PAD_LD2__LD2 0x0 \
-	MX27_PAD_LD3__LD3 0x0 \
-	MX27_PAD_LD4__LD4 0x0 \
-	MX27_PAD_LD5__LD5 0x0 \
-	MX27_PAD_LD6__LD6 0x0 \
-	MX27_PAD_LD7__LD7 0x0 \
-	MX27_PAD_LD8__LD8 0x0 \
-	MX27_PAD_LD9__LD9 0x0 \
-	MX27_PAD_LD10__LD10 0x0 \
-	MX27_PAD_LD11__LD11 0x0 \
-	MX27_PAD_LD12__LD12 0x0 \
-	MX27_PAD_LD13__LD13 0x0 \
-	MX27_PAD_LD14__LD14 0x0 \
-	MX27_PAD_LD15__LD15 0x0 \
-	MX27_PAD_LD16__LD16 0x0 \
-	MX27_PAD_LD17__LD17 0x0 \
-	MX27_PAD_LSCLK__LSCLK 0x0 \
-	MX27_PAD_OE_ACD__OE_ACD 0x0 \
-	MX27_PAD_PS__PS 0x0 \
-	MX27_PAD_REV__REV 0x0 \
-	MX27_PAD_SPL_SPR__SPL_SPR 0x0 \
-	MX27_PAD_HSYNC__HSYNC 0x0 \
-	MX27_PAD_VSYNC__VSYNC 0x0
-
-#define MX27_FEC1_PINGRP1 \
-	MX27_PAD_SD3_CMD__FEC_TXD0 0x0 \
-	MX27_PAD_SD3_CLK__FEC_TXD1 0x0 \
-	MX27_PAD_ATA_DATA0__FEC_TXD2 0x0 \
-	MX27_PAD_ATA_DATA1__FEC_TXD3 0x0 \
-	MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0 \
-	MX27_PAD_ATA_DATA3__FEC_RXD1 0x0 \
-	MX27_PAD_ATA_DATA4__FEC_RXD2 0x0 \
-	MX27_PAD_ATA_DATA5__FEC_RXD3 0x0 \
-	MX27_PAD_ATA_DATA6__FEC_MDIO 0x0 \
-	MX27_PAD_ATA_DATA7__FEC_MDC 0x0 \
-	MX27_PAD_ATA_DATA8__FEC_CRS 0x0 \
-	MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0 \
-	MX27_PAD_ATA_DATA10__FEC_RXD0 0x0 \
-	MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0 \
-	MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0 \
-	MX27_PAD_ATA_DATA13__FEC_COL 0x0 \
-	MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0 \
-	MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0
-
-#define MX27_I2C1_PINGRP1 \
-	MX27_PAD_I2C_DATA__I2C_DATA 0x0 \
-	MX27_PAD_I2C_CLK__I2C_CLK 0x0
-
-#define MX27_I2C2_PINGRP1 \
-	MX27_PAD_I2C2_SDA__I2C2_SDA 0x0 \
-	MX27_PAD_I2C2_SCL__I2C2_SCL 0x0
-
-#define MX27_NFC_PINGRP1 \
-	MX27_PAD_NFRB__NFRB 0x0 \
-	MX27_PAD_NFCLE__NFCLE 0x0 \
-	MX27_PAD_NFWP_B__NFWP_B 0x0 \
-	MX27_PAD_NFCE_B__NFCE_B 0x0 \
-	MX27_PAD_NFALE__NFALE 0x0 \
-	MX27_PAD_NFRE_B__NFRE_B 0x0 \
-	MX27_PAD_NFWE_B__NFWE_B 0x0
-
-#define MX27_OWIRE1_PINGRP1 \
-	MX27_PAD_RTCK__OWIRE 0x0
-
-#define MX27_PWM_PINGRP1 \
-	MX27_PAD_PWMO__PWMO 0x0
-
-#define MX27_SDHC1_PINGRP1 \
-	MX27_PAD_SD1_CLK__SD1_CLK 0x0 \
-	MX27_PAD_SD1_CMD__SD1_CMD 0x0 \
-	MX27_PAD_SD1_D0__SD1_D0 0x0 \
-	MX27_PAD_SD1_D1__SD1_D1 0x0 \
-	MX27_PAD_SD1_D2__SD1_D2 0x0 \
-	MX27_PAD_SD1_D3__SD1_D3 0x0
-
-#define MX27_SDHC2_PINGRP1 \
-	MX27_PAD_SD2_CLK__SD2_CLK 0x0 \
-	MX27_PAD_SD2_CMD__SD2_CMD 0x0 \
-	MX27_PAD_SD2_D0__SD2_D0 0x0 \
-	MX27_PAD_SD2_D1__SD2_D1 0x0 \
-	MX27_PAD_SD2_D2__SD2_D2 0x0 \
-	MX27_PAD_SD2_D3__SD2_D3 0x0
-
-#define MX27_SDHC3_PINGRP1 \
-	MX27_PAD_SD3_CLK__SD3_CLK 0x0 \
-	MX27_PAD_SD3_CMD__SD3_CMD 0x0 \
-	MX27_PAD_SD3_D0__SD3_D0 0x0 \
-	MX27_PAD_SD3_D1__SD3_D1 0x0 \
-	MX27_PAD_SD3_D2__SD3_D2 0x0 \
-	MX27_PAD_SD3_D3__SD3_D3 0x0
-
-#define MX27_UART1_PINGRP1 \
-	MX27_PAD_UART1_TXD__UART1_TXD 0x0 \
-	MX27_PAD_UART1_RXD__UART1_RXD 0x0
-
-#define MX27_UART1_RTSCTS_PINGRP1 \
-	MX27_PAD_UART1_CTS__UART1_CTS 0x0 \
-	MX27_PAD_UART1_RTS__UART1_RTS 0x0
-
-#define MX27_UART2_PINGRP1 \
-	MX27_PAD_UART2_TXD__UART2_TXD 0x0 \
-	MX27_PAD_UART2_RXD__UART2_RXD 0x0
-
-#define MX27_UART2_RTSCTS_PINGRP1 \
-	MX27_PAD_UART2_CTS__UART2_CTS 0x0 \
-	MX27_PAD_UART2_RTS__UART2_RTS 0x0
-
-#define MX27_UART3_PINGRP1 \
-	MX27_PAD_UART3_TXD__UART3_TXD 0x0 \
-	MX27_PAD_UART3_RXD__UART3_RXD 0x0
-
-#define MX27_UART3_RTSCTS_PINGRP1 \
-	MX27_PAD_UART3_CTS__UART3_CTS 0x0 \
-	MX27_PAD_UART3_RTS__UART3_RTS 0x0
-
-#endif /* __DTS_IMX27_PINGRP_H */
diff --git a/arch/arm/dts/imx27.dtsi b/arch/arm/dts/imx27.dtsi
index 7e98966..83a8247 100644
--- a/arch/arm/dts/imx27.dtsi
+++ b/arch/arm/dts/imx27.dtsi
@@ -10,12 +10,13 @@
  */
 
 #include "skeleton.dtsi"
-#include "imx27-pingrp.h"
+#include "imx27-pinfunc.h"
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/gpio/gpio.h>
 
 / {
 	aliases {
+		ethernet0 = &fec;
 		gpio0 = &gpio1;
 		gpio1 = &gpio2;
 		gpio2 = &gpio3;
@@ -70,6 +71,26 @@
 		};
 	};
 
+	usbphy {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		usbphy0: usbphy at 0 {
+			compatible = "usb-nop-xceiv";
+			reg = <0>;
+			clocks = <&clks 75>;
+			clock-names = "main_clk";
+		};
+
+		usbphy2: usbphy at 2 {
+			compatible = "usb-nop-xceiv";
+			reg = <2>;
+			clocks = <&clks 75>;
+			clock-names = "main_clk";
+		};
+	};
+
 	soc {
 		#address-cells = <1>;
 		#size-cells = <1>;
@@ -439,6 +460,42 @@
 				iram = <&iram>;
 			};
 
+			usbotg: usb at 10024000 {
+				compatible = "fsl,imx27-usb";
+				reg = <0x10024000 0x200>;
+				interrupts = <56>;
+				clocks = <&clks 15>;
+				fsl,usbmisc = <&usbmisc 0>;
+				fsl,usbphy = <&usbphy0>;
+				status = "disabled";
+			};
+
+			usbh1: usb at 10024200 {
+				compatible = "fsl,imx27-usb";
+				reg = <0x10024200 0x200>;
+				interrupts = <54>;
+				clocks = <&clks 15>;
+				fsl,usbmisc = <&usbmisc 1>;
+				status = "disabled";
+			};
+
+			usbh2: usb at 10024400 {
+				compatible = "fsl,imx27-usb";
+				reg = <0x10024400 0x200>;
+				interrupts = <55>;
+				clocks = <&clks 15>;
+				fsl,usbmisc = <&usbmisc 2>;
+				fsl,usbphy = <&usbphy2>;
+				status = "disabled";
+			};
+
+			usbmisc: usbmisc at 10024600 {
+				#index-cells = <1>;
+				compatible = "fsl,imx27-usbmisc";
+				reg = <0x10024600 0x200>;
+				clocks = <&clks 62>;
+			};
+
 			sahara2: sahara at 10025000 {
 				compatible = "fsl,imx27-sahara";
 				reg = <0x10025000 0x1000>;
-- 
1.8.3.2



From antonynpavlov at gmail.com  Sun Mar 16 09:48:12 2014
From: antonynpavlov at gmail.com (Antony Pavlov)
Date: Sun, 16 Mar 2014 17:48:12 +0400
Subject: [PATCH v2 01/10] import _AC and UL macros from linux kernel
In-Reply-To: <1394977701-5889-1-git-send-email-antonynpavlov@gmail.com>
References: <1394977701-5889-1-git-send-email-antonynpavlov@gmail.com>
Message-ID: <1394977701-5889-2-git-send-email-antonynpavlov@gmail.com>

This macros are used in exported from linux TI DaVinci code.
Also this macros are used in MIPS cache support code.

Signed-off-by: Antony Pavlov <antonynpavlov at gmail.com>
---
 arch/arm/include/asm/memory.h |  7 +++++++
 include/linux/const.h         | 27 +++++++++++++++++++++++++++
 2 files changed, 34 insertions(+)

diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h
index 28afaa3..52114d0 100644
--- a/arch/arm/include/asm/memory.h
+++ b/arch/arm/include/asm/memory.h
@@ -3,6 +3,13 @@
 
 #include <memory.h>
 
+#include <linux/const.h>
+/*
+ * Allow for constants defined here to be used from assembly code
+ * by prepending the UL suffix only with actual C code compilation.
+ */
+#define UL(x) _AC(x, UL)
+
 static inline void arm_add_mem_device(const char* name, resource_size_t start,
 				    resource_size_t size)
 {
diff --git a/include/linux/const.h b/include/linux/const.h
new file mode 100644
index 0000000..c872bfd
--- /dev/null
+++ b/include/linux/const.h
@@ -0,0 +1,27 @@
+/* const.h: Macros for dealing with constants.  */
+
+#ifndef _LINUX_CONST_H
+#define _LINUX_CONST_H
+
+/* Some constant macros are used in both assembler and
+ * C code.  Therefore we cannot annotate them always with
+ * 'UL' and other type specifiers unilaterally.  We
+ * use the following macros to deal with this.
+ *
+ * Similarly, _AT() will cast an expression with a type in C, but
+ * leave it unchanged in asm.
+ */
+
+#ifdef __ASSEMBLY__
+#define _AC(X,Y)	X
+#define _AT(T,X)	X
+#else
+#define __AC(X,Y)	(X##Y)
+#define _AC(X,Y)	__AC(X,Y)
+#define _AT(T,X)	((T)(X))
+#endif
+
+#define _BITUL(x)	(_AC(1,UL) << (x))
+#define _BITULL(x)	(_AC(1,ULL) << (x))
+
+#endif /* !(_LINUX_CONST_H) */
-- 
1.9.0



From antonynpavlov at gmail.com  Sun Mar 16 09:48:11 2014
From: antonynpavlov at gmail.com (Antony Pavlov)
Date: Sun, 16 Mar 2014 17:48:11 +0400
Subject: [PATCH v2 00/10] ARM: initial support for TI DaVinci SoCs and
 virt2real board
Message-ID: <1394977701-5889-1-git-send-email-antonynpavlov@gmail.com>

Change since v1:

- add hardware-base clocksource and move dummy software-only
  clocksource to separate patchseries;
- add gpio driver;
- use devicetree for probing devices.

Antony Pavlov (10):
  import _AC and UL macros from linux kernel
  ARM: initial support for TI DaVinci SoCs
  ARM: davinci: add DEBUG_LL support
  ARM: davinci: add clocksource
  gpio: add driver for TI DaVinci SoCs
  ARM: dts: Add TI TMS320DM365 devicetree file
  ARM: davinci: add documentation
  ARM: davinci: add virt2real board support
  ARM: virt2real: add documentation
  ARM: davinci: add virt2real_defconfig

 Documentation/boards.dox                      |   1 +
 arch/arm/Kconfig                              |   7 +
 arch/arm/Makefile                             |   1 +
 arch/arm/boards/Makefile                      |   1 +
 arch/arm/boards/virt2real/Makefile            |   1 +
 arch/arm/boards/virt2real/board.c             |  27 ++++
 arch/arm/boards/virt2real/lowlevel.c          |  34 +++++
 arch/arm/boards/virt2real/virt2real.dox       |  41 +++++
 arch/arm/configs/virt2real_defconfig          |  49 ++++++
 arch/arm/dts/dm365.dtsi                       |  28 ++++
 arch/arm/dts/virt2real.dts                    |  35 +++++
 arch/arm/include/asm/memory.h                 |   7 +
 arch/arm/mach-arm.dox                         |   2 +
 arch/arm/mach-davinci/Kconfig                 |  16 ++
 arch/arm/mach-davinci/Makefile                |   1 +
 arch/arm/mach-davinci/include/mach/debug_ll.h |  42 +++++
 arch/arm/mach-davinci/include/mach/hardware.h |  29 ++++
 arch/arm/mach-davinci/include/mach/serial.h   |  20 +++
 arch/arm/mach-davinci/include/mach/time.h     |  20 +++
 arch/arm/mach-davinci/mach-davinci.dox        |   7 +
 arch/arm/mach-davinci/time.c                  | 209 +++++++++++++++++++++++++
 drivers/gpio/Kconfig                          |   7 +
 drivers/gpio/Makefile                         |   1 +
 drivers/gpio/gpio-davinci.c                   | 211 ++++++++++++++++++++++++++
 include/linux/const.h                         |  27 ++++
 25 files changed, 824 insertions(+)
 create mode 100644 arch/arm/boards/virt2real/Makefile
 create mode 100644 arch/arm/boards/virt2real/board.c
 create mode 100644 arch/arm/boards/virt2real/lowlevel.c
 create mode 100644 arch/arm/boards/virt2real/virt2real.dox
 create mode 100644 arch/arm/configs/virt2real_defconfig
 create mode 100644 arch/arm/dts/dm365.dtsi
 create mode 100644 arch/arm/dts/virt2real.dts
 create mode 100644 arch/arm/mach-davinci/Kconfig
 create mode 100644 arch/arm/mach-davinci/Makefile
 create mode 100644 arch/arm/mach-davinci/include/mach/debug_ll.h
 create mode 100644 arch/arm/mach-davinci/include/mach/hardware.h
 create mode 100644 arch/arm/mach-davinci/include/mach/serial.h
 create mode 100644 arch/arm/mach-davinci/include/mach/time.h
 create mode 100644 arch/arm/mach-davinci/mach-davinci.dox
 create mode 100644 arch/arm/mach-davinci/time.c
 create mode 100644 drivers/gpio/gpio-davinci.c
 create mode 100644 include/linux/const.h

-- 
1.9.0



From antonynpavlov at gmail.com  Sun Mar 16 09:48:13 2014
From: antonynpavlov at gmail.com (Antony Pavlov)
Date: Sun, 16 Mar 2014 17:48:13 +0400
Subject: [PATCH v2 02/10] ARM: initial support for TI DaVinci SoCs
In-Reply-To: <1394977701-5889-1-git-send-email-antonynpavlov@gmail.com>
References: <1394977701-5889-1-git-send-email-antonynpavlov@gmail.com>
Message-ID: <1394977701-5889-3-git-send-email-antonynpavlov@gmail.com>

This commit adds minimal support for the DaVinci DM365 SoCs
from Texas Instruments.

Signed-off-by: Antony Pavlov <antonynpavlov at gmail.com>
---
 arch/arm/Kconfig                              |  5 ++
 arch/arm/Makefile                             |  1 +
 arch/arm/mach-davinci/Kconfig                 |  7 ++
 arch/arm/mach-davinci/Makefile                |  1 +
 arch/arm/mach-davinci/include/mach/hardware.h | 29 ++++++++
 arch/arm/mach-davinci/include/mach/serial.h   | 20 ++++++
 arch/arm/mach-davinci/include/mach/time.h     | 18 +++++
 arch/arm/mach-davinci/time.c                  | 95 +++++++++++++++++++++++++++
 8 files changed, 176 insertions(+)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 21f9012..42ff01b 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -54,6 +54,10 @@ config ARCH_CLPS711X
 	select GPIOLIB
 	select MFD_SYSCON
 
+config ARCH_DAVINCI
+	bool "TI Davinci"
+	select CPU_ARM926T
+
 config ARCH_EP93XX
 	bool "Cirrus Logic EP93xx"
 	select CPU_ARM920T
@@ -188,6 +192,7 @@ source arch/arm/cpu/Kconfig
 source arch/arm/mach-at91/Kconfig
 source arch/arm/mach-bcm2835/Kconfig
 source arch/arm/mach-clps711x/Kconfig
+source arch/arm/mach-davinci/Kconfig
 source arch/arm/mach-ep93xx/Kconfig
 source arch/arm/mach-highbank/Kconfig
 source arch/arm/mach-imx/Kconfig
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 2bbba35..c1bd836 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -54,6 +54,7 @@ AFLAGS   += -include asm/unified.h -msoft-float $(AFLAGS_THUMB2)
 machine-$(CONFIG_ARCH_AT91)		:= at91
 machine-$(CONFIG_ARCH_BCM2835)		:= bcm2835
 machine-$(CONFIG_ARCH_CLPS711X)		:= clps711x
+machine-$(CONFIG_ARCH_DAVINCI)		:= davinci
 machine-$(CONFIG_ARCH_EP93XX)		:= ep93xx
 machine-$(CONFIG_ARCH_HIGHBANK)		:= highbank
 machine-$(CONFIG_ARCH_IMX)		:= imx
diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig
new file mode 100644
index 0000000..5677f8d
--- /dev/null
+++ b/arch/arm/mach-davinci/Kconfig
@@ -0,0 +1,7 @@
+if ARCH_DAVINCI
+
+config ARCH_TEXT_BASE
+	hex
+	default 0x82000000
+
+endif
diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile
new file mode 100644
index 0000000..b96d414
--- /dev/null
+++ b/arch/arm/mach-davinci/Makefile
@@ -0,0 +1 @@
+obj-y += time.o
diff --git a/arch/arm/mach-davinci/include/mach/hardware.h b/arch/arm/mach-davinci/include/mach/hardware.h
new file mode 100644
index 0000000..ea9f481
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/hardware.h
@@ -0,0 +1,29 @@
+/*
+ * Hardware definitions common to all DaVinci family processors
+ *
+ * Author: Kevin Hilman, Deep Root Systems, LLC
+ *
+ * 2007 (c) Deep Root Systems, LLC. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#include <asm/memory.h>
+
+/*
+ * Before you add anything to this file:
+ *
+ * This header is for defines common to ALL DaVinci family chips.
+ * Anything that is chip specific should go in <chipname>.h,
+ * and the chip/board init code should then explicitly include
+ * <chipname>.h
+ */
+/*
+ * I/O mapping
+ */
+#define IO_PHYS				UL(0x01c00000)
+
+#endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/mach-davinci/include/mach/serial.h b/arch/arm/mach-davinci/include/mach/serial.h
new file mode 100644
index 0000000..bc7449f
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/serial.h
@@ -0,0 +1,20 @@
+/*
+ * DaVinci serial device definitions
+ *
+ * Author: Kevin Hilman, MontaVista Software, Inc. <source at mvista.com>
+ *
+ * 2007 (c) MontaVista Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+#ifndef __ASM_ARCH_SERIAL_H
+#define __ASM_ARCH_SERIAL_H
+
+#include <mach/hardware.h>
+
+#define DAVINCI_UART0_BASE	(IO_PHYS + 0x20000)
+#define DAVINCI_UART1_BASE	(IO_PHYS + 0x20400)
+#define DAVINCI_UART2_BASE	(IO_PHYS + 0x20800)
+
+#endif /* __ASM_ARCH_SERIAL_H */
diff --git a/arch/arm/mach-davinci/include/mach/time.h b/arch/arm/mach-davinci/include/mach/time.h
new file mode 100644
index 0000000..741e90c
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/time.h
@@ -0,0 +1,18 @@
+/*
+ * Local header file for DaVinci time code.
+ *
+ * Author: Kevin Hilman, MontaVista Software, Inc. <source at mvista.com>
+ *
+ * 2007 (c) MontaVista Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+#ifndef __ARCH_ARM_MACH_DAVINCI_TIME_H
+#define __ARCH_ARM_MACH_DAVINCI_TIME_H
+
+#include <mach/hardware.h>
+
+#define DAVINCI_WDOG_BASE		(IO_PHYS + 0x21C00)
+
+#endif /* __ARCH_ARM_MACH_DAVINCI_TIME_H */
diff --git a/arch/arm/mach-davinci/time.c b/arch/arm/mach-davinci/time.c
new file mode 100644
index 0000000..1e00719
--- /dev/null
+++ b/arch/arm/mach-davinci/time.c
@@ -0,0 +1,95 @@
+/*
+ * DaVinci timer subsystem
+ *
+ * Author: Kevin Hilman, MontaVista Software, Inc. <source at mvista.com>
+ *
+ * 2007 (c) MontaVista Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+
+#include <common.h>
+#include <io.h>
+
+#include <mach/time.h>
+
+/* Timer register offsets */
+#define PID12			0x0
+#define TIM12			0x10
+#define TIM34			0x14
+#define PRD12			0x18
+#define PRD34			0x1c
+#define TCR			0x20
+#define TGCR			0x24
+#define WDTCR			0x28
+
+/* Timer register bitfields */
+#define TCR_ENAMODE_DISABLE          0x0
+#define TCR_ENAMODE_ONESHOT          0x1
+#define TCR_ENAMODE_PERIODIC         0x2
+#define TCR_ENAMODE_MASK             0x3
+
+#define TGCR_TIMMODE_SHIFT           2
+#define TGCR_TIMMODE_64BIT_GP        0x0
+#define TGCR_TIMMODE_32BIT_UNCHAINED 0x1
+#define TGCR_TIMMODE_64BIT_WDOG      0x2
+#define TGCR_TIMMODE_32BIT_CHAINED   0x3
+
+#define TGCR_TIM12RS_SHIFT           0
+#define TGCR_TIM34RS_SHIFT           1
+#define TGCR_RESET                   0x0
+#define TGCR_UNRESET                 0x1
+#define TGCR_RESET_MASK              0x3
+
+#define WDTCR_WDEN_SHIFT             14
+#define WDTCR_WDEN_DISABLE           0x0
+#define WDTCR_WDEN_ENABLE            0x1
+#define WDTCR_WDKEY_SHIFT            16
+#define WDTCR_WDKEY_SEQ0             0xa5c6
+#define WDTCR_WDKEY_SEQ1             0xda7e
+
+/* reset board using watchdog timer */
+void __noreturn reset_cpu(ulong addr)
+{
+	u32 tgcr, wdtcr;
+	void __iomem *base;
+
+	base = IOMEM(DAVINCI_WDOG_BASE);
+
+	/* disable, internal clock source */
+	__raw_writel(0, base + TCR);
+
+	/* reset timer, set mode to 64-bit watchdog, and unreset */
+	tgcr = 0;
+	__raw_writel(tgcr, base + TGCR);
+	tgcr = TGCR_TIMMODE_64BIT_WDOG << TGCR_TIMMODE_SHIFT;
+	tgcr |= (TGCR_UNRESET << TGCR_TIM12RS_SHIFT) |
+		(TGCR_UNRESET << TGCR_TIM34RS_SHIFT);
+	__raw_writel(tgcr, base + TGCR);
+
+	/* clear counter and period regs */
+	__raw_writel(0, base + TIM12);
+	__raw_writel(0, base + TIM34);
+	__raw_writel(0, base + PRD12);
+	__raw_writel(0, base + PRD34);
+
+	/* put watchdog in pre-active state */
+	wdtcr = __raw_readl(base + WDTCR);
+	wdtcr = (WDTCR_WDKEY_SEQ0 << WDTCR_WDKEY_SHIFT) |
+		(WDTCR_WDEN_ENABLE << WDTCR_WDEN_SHIFT);
+	__raw_writel(wdtcr, base + WDTCR);
+
+	/* put watchdog in active state */
+	wdtcr = (WDTCR_WDKEY_SEQ1 << WDTCR_WDKEY_SHIFT) |
+		(WDTCR_WDEN_ENABLE << WDTCR_WDEN_SHIFT);
+	__raw_writel(wdtcr, base + WDTCR);
+
+	/* write an invalid value to the WDKEY field to trigger
+	 * a watchdog reset */
+	wdtcr = 0x00004000;
+	__raw_writel(wdtcr, base + WDTCR);
+
+	unreachable();
+}
+EXPORT_SYMBOL(reset_cpu);
-- 
1.9.0



From antonynpavlov at gmail.com  Sun Mar 16 09:48:14 2014
From: antonynpavlov at gmail.com (Antony Pavlov)
Date: Sun, 16 Mar 2014 17:48:14 +0400
Subject: [PATCH v2 03/10] ARM: davinci: add DEBUG_LL support
In-Reply-To: <1394977701-5889-1-git-send-email-antonynpavlov@gmail.com>
References: <1394977701-5889-1-git-send-email-antonynpavlov@gmail.com>
Message-ID: <1394977701-5889-4-git-send-email-antonynpavlov@gmail.com>

Signed-off-by: Antony Pavlov <antonynpavlov at gmail.com>
---
 arch/arm/Kconfig                              |  1 +
 arch/arm/mach-davinci/include/mach/debug_ll.h | 42 +++++++++++++++++++++++++++
 2 files changed, 43 insertions(+)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 42ff01b..407f27d 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -57,6 +57,7 @@ config ARCH_CLPS711X
 config ARCH_DAVINCI
 	bool "TI Davinci"
 	select CPU_ARM926T
+	select HAS_DEBUG_LL
 
 config ARCH_EP93XX
 	bool "Cirrus Logic EP93xx"
diff --git a/arch/arm/mach-davinci/include/mach/debug_ll.h b/arch/arm/mach-davinci/include/mach/debug_ll.h
new file mode 100644
index 0000000..587f408
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/debug_ll.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright (C) 2014 Antony Pavlov <antonynpavlov at gmail.com>
+ *
+ * This file is part of barebox.
+ * See file CREDITS for list of people who contributed to this project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+/** @file
+ *  This File contains declaration for early output support
+ */
+#ifndef __INCLUDE_ARCH_DEBUG_LL_H__
+#define __INCLUDE_ARCH_DEBUG_LL_H__
+
+#include <asm/io.h>
+#include <mach/serial.h>
+
+#define DEBUG_LL_UART_ADDR	DAVINCI_UART0_BASE
+#define DEBUG_LL_UART_RSHFT	2
+
+#define rbr		(0 << DEBUG_LL_UART_RSHFT)
+#define lsr		(5 << DEBUG_LL_UART_RSHFT)
+#define LSR_THRE	0x20	/* Xmit holding register empty */
+
+static inline void PUTC_LL(char ch)
+{
+	while (!(__raw_readb(DEBUG_LL_UART_ADDR + lsr) & LSR_THRE))
+		;
+
+	__raw_writeb(ch, DEBUG_LL_UART_ADDR + rbr);
+}
+
+#endif /* __INCLUDE_ARCH_DEBUG_LL_H__ */
-- 
1.9.0



From antonynpavlov at gmail.com  Sun Mar 16 09:48:15 2014
From: antonynpavlov at gmail.com (Antony Pavlov)
Date: Sun, 16 Mar 2014 17:48:15 +0400
Subject: [PATCH v2 04/10] ARM: davinci: add clocksource
In-Reply-To: <1394977701-5889-1-git-send-email-antonynpavlov@gmail.com>
References: <1394977701-5889-1-git-send-email-antonynpavlov@gmail.com>
Message-ID: <1394977701-5889-5-git-send-email-antonynpavlov@gmail.com>

Signed-off-by: Antony Pavlov <antonynpavlov at gmail.com>
---
 arch/arm/mach-davinci/include/mach/time.h |   2 +
 arch/arm/mach-davinci/time.c              | 114 ++++++++++++++++++++++++++++++
 2 files changed, 116 insertions(+)

diff --git a/arch/arm/mach-davinci/include/mach/time.h b/arch/arm/mach-davinci/include/mach/time.h
index 741e90c..34781b6 100644
--- a/arch/arm/mach-davinci/include/mach/time.h
+++ b/arch/arm/mach-davinci/include/mach/time.h
@@ -13,6 +13,8 @@
 
 #include <mach/hardware.h>
 
+#define DAVINCI_TIMER0_BASE		(IO_PHYS + 0x21400)
+#define DAVINCI_TIMER1_BASE		(IO_PHYS + 0x21800)
 #define DAVINCI_WDOG_BASE		(IO_PHYS + 0x21C00)
 
 #endif /* __ARCH_ARM_MACH_DAVINCI_TIME_H */
diff --git a/arch/arm/mach-davinci/time.c b/arch/arm/mach-davinci/time.c
index 1e00719..60f0d19 100644
--- a/arch/arm/mach-davinci/time.c
+++ b/arch/arm/mach-davinci/time.c
@@ -11,6 +11,8 @@
 
 #include <common.h>
 #include <io.h>
+#include <init.h>
+#include <clock.h>
 
 #include <mach/time.h>
 
@@ -49,6 +51,118 @@
 #define WDTCR_WDKEY_SEQ0             0xa5c6
 #define WDTCR_WDKEY_SEQ1             0xda7e
 
+#define DAVINCI_TIMER_CLOCK 24000000
+
+struct timer_s {
+	void __iomem *base;
+	unsigned long tim_off;
+	unsigned long prd_off;
+	unsigned long enamode_shift;
+};
+
+static struct timer_s timers[] = {
+	{
+		.base = IOMEM(DAVINCI_TIMER0_BASE),
+		.enamode_shift = 6,
+		.tim_off = TIM12,
+		.prd_off = PRD12,
+	},
+	{
+		.base = IOMEM(DAVINCI_TIMER0_BASE),
+		.enamode_shift = 22,
+		.tim_off = TIM34,
+		.prd_off = PRD34,
+	},
+	{
+		.base = IOMEM(DAVINCI_TIMER1_BASE),
+		.enamode_shift = 6,
+		.tim_off = TIM12,
+		.prd_off = PRD12,
+	},
+	{
+		.base = IOMEM(DAVINCI_TIMER1_BASE),
+		.enamode_shift = 22,
+		.tim_off = TIM34,
+		.prd_off = PRD34,
+	},
+};
+
+static struct timer_s *t = &timers[0];
+
+static uint64_t davinci_cs_read(void)
+{
+	return (uint64_t)__raw_readl(t->base + t->tim_off);
+}
+
+static struct clocksource davinci_cs = {
+	.read	= davinci_cs_read,
+	.mask	= CLOCKSOURCE_MASK(32),
+};
+
+static int timer32_config(struct timer_s *t)
+{
+	u32 tcr;
+
+	tcr = __raw_readl(t->base + TCR);
+
+	/* disable timer */
+	tcr &= ~(TCR_ENAMODE_MASK << t->enamode_shift);
+	__raw_writel(tcr, t->base + TCR);
+
+	/* reset counter to zero, set new period */
+	__raw_writel(0, t->base + t->tim_off);
+	__raw_writel(0xffffffff, t->base + t->prd_off);
+
+	/* Set enable mode for periodic timer */
+	tcr |= TCR_ENAMODE_PERIODIC << t->enamode_shift;
+
+	__raw_writel(tcr, t->base + TCR);
+
+	return 0;
+}
+
+/* Global init of 64-bit timer as a whole */
+static void __init timer_init(void __iomem *base)
+{
+	u32 tgcr;
+
+	/* Disabled, Internal clock source */
+	__raw_writel(0, base + TCR);
+
+	/* reset both timers, no pre-scaler for timer34 */
+	tgcr = 0;
+	__raw_writel(tgcr, base + TGCR);
+
+	/* Set both timers to unchained 32-bit */
+	tgcr = TGCR_TIMMODE_32BIT_UNCHAINED << TGCR_TIMMODE_SHIFT;
+	__raw_writel(tgcr, base + TGCR);
+
+	/* Unreset timers */
+	tgcr |= (TGCR_UNRESET << TGCR_TIM12RS_SHIFT) |
+		(TGCR_UNRESET << TGCR_TIM34RS_SHIFT);
+	__raw_writel(tgcr, base + TGCR);
+
+	/* Init both counters to zero */
+	__raw_writel(0, base + TIM12);
+	__raw_writel(0, base + TIM34);
+}
+
+static int clocksource_init(void)
+{
+	clocks_calc_mult_shift(&davinci_cs.mult, &davinci_cs.shift,
+		DAVINCI_TIMER_CLOCK, NSEC_PER_SEC, 10);
+
+	init_clock(&davinci_cs);
+
+	timer_init(IOMEM(DAVINCI_TIMER0_BASE));
+	timer_init(IOMEM(DAVINCI_TIMER1_BASE));
+
+	timer32_config(t);
+
+	return 0;
+}
+core_initcall(clocksource_init);
+
 /* reset board using watchdog timer */
 void __noreturn reset_cpu(ulong addr)
 {
-- 
1.9.0



From antonynpavlov at gmail.com  Sun Mar 16 09:48:17 2014
From: antonynpavlov at gmail.com (Antony Pavlov)
Date: Sun, 16 Mar 2014 17:48:17 +0400
Subject: [PATCH v2 06/10] ARM: dts: Add TI TMS320DM365 devicetree file
In-Reply-To: <1394977701-5889-1-git-send-email-antonynpavlov@gmail.com>
References: <1394977701-5889-1-git-send-email-antonynpavlov@gmail.com>
Message-ID: <1394977701-5889-7-git-send-email-antonynpavlov@gmail.com>

Signed-off-by: Antony Pavlov <antonynpavlov at gmail.com>
---
 arch/arm/dts/dm365.dtsi | 28 ++++++++++++++++++++++++++++
 1 file changed, 28 insertions(+)

diff --git a/arch/arm/dts/dm365.dtsi b/arch/arm/dts/dm365.dtsi
new file mode 100644
index 0000000..ea69007
--- /dev/null
+++ b/arch/arm/dts/dm365.dtsi
@@ -0,0 +1,28 @@
+#include "skeleton.dtsi"
+
+/ {
+	soc {
+		compatible = "simple-bus";
+		model = "TI TMS320DM365";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0x0 0x01c00000 0x400000>;
+
+		serial0: serial at 1c20000 {
+			compatible = "ns16550a";
+			reg = <0x20000 0x400>;
+			reg-shift = <2>;
+			clock-frequency = <24000000>;
+			status = "disabled";
+		};
+
+		gpio: gpio at 1c67000 {
+			compatible = "ti,dm6441-gpio";
+			gpio-controller;
+			reg = <0x67000 0x800>;
+			#gpio-cells = <2>;
+			ti,ngpio = <107>;
+			status = "disabled";
+		};
+	};
+};
-- 
1.9.0



From antonynpavlov at gmail.com  Sun Mar 16 09:48:16 2014
From: antonynpavlov at gmail.com (Antony Pavlov)
Date: Sun, 16 Mar 2014 17:48:16 +0400
Subject: [PATCH v2 05/10] gpio: add driver for TI DaVinci SoCs
In-Reply-To: <1394977701-5889-1-git-send-email-antonynpavlov@gmail.com>
References: <1394977701-5889-1-git-send-email-antonynpavlov@gmail.com>
Message-ID: <1394977701-5889-6-git-send-email-antonynpavlov@gmail.com>

This driver is dts-only version of driver from Linux v3.14-rc5.

Signed-off-by: Antony Pavlov <antonynpavlov at gmail.com>
---
 arch/arm/Kconfig            |   1 +
 drivers/gpio/Kconfig        |   7 ++
 drivers/gpio/Makefile       |   1 +
 drivers/gpio/gpio-davinci.c | 211 ++++++++++++++++++++++++++++++++++++++++++++
 4 files changed, 220 insertions(+)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 407f27d..3754646 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -58,6 +58,7 @@ config ARCH_DAVINCI
 	bool "TI Davinci"
 	select CPU_ARM926T
 	select HAS_DEBUG_LL
+	select GPIOLIB
 
 config ARCH_EP93XX
 	bool "Cirrus Logic EP93xx"
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 7c42656..7302955 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -20,6 +20,13 @@ config GPIO_CLPS711X
 	help
 	  Say yes here to enable the GPIO driver for the CLPS711X CPUs
 
+config GPIO_DAVINCI
+	bool "TI Davinci/Keystone GPIO support"
+	default y if ARCH_DAVINCI
+	depends on ARM && ARCH_DAVINCI
+	help
+	  Say yes here to enable GPIO support for TI Davinci/Keystone SoCs.
+
 config GPIO_GENERIC_PLATFORM
 	bool "Generic memory-mapped GPIO controller support"
 	select GPIO_GENERIC
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index b7c536d..68a76a3 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -1,6 +1,7 @@
 obj-$(CONFIG_GPIOLIB)		+= gpiolib.o
 
 obj-$(CONFIG_GPIO_BCM2835)	+= gpio-bcm2835.o
+obj-$(CONFIG_GPIO_DAVINCI)	+= gpio-davinci.o
 obj-$(CONFIG_GPIO_CLPS711X)	+= gpio-clps711x.o
 obj-$(CONFIG_GPIO_GENERIC)	+= gpio-generic.o
 obj-$(CONFIG_GPIO_IMX)		+= gpio-imx.o
diff --git a/drivers/gpio/gpio-davinci.c b/drivers/gpio/gpio-davinci.c
new file mode 100644
index 0000000..7d15b85
--- /dev/null
+++ b/drivers/gpio/gpio-davinci.c
@@ -0,0 +1,211 @@
+/*
+ * TI DaVinci GPIO Support
+ *
+ * Copyright (c) 2006-2007 David Brownell
+ * Copyright (c) 2007, MontaVista Software, Inc. <source at mvista.com>
+ * Copyright (c) 2014 Antony Pavlov <antonynpavlov at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <common.h>
+#include <gpio.h>
+#include <init.h>
+#include <io.h>
+#include <linux/err.h>
+
+#define readl_relaxed	readl
+#define writel_relaxed	writel
+
+struct davinci_gpio_regs {
+	u32	dir;
+	u32	out_data;
+	u32	set_data;
+	u32	clr_data;
+	u32	in_data;
+	u32	set_rising;
+	u32	clr_rising;
+	u32	set_falling;
+	u32	clr_falling;
+	u32	intstat;
+};
+
+struct davinci_gpio_controller {
+	struct gpio_chip	chip;
+	/* Serialize access to GPIO registers */
+	void __iomem		*regs;
+	void __iomem		*set_data;
+	void __iomem		*clr_data;
+	void __iomem		*in_data;
+};
+
+#define chip2controller(chip)	\
+	container_of(chip, struct davinci_gpio_controller, chip)
+
+static struct davinci_gpio_regs __iomem *gpio2regs(void __iomem *gpio_base,
+							unsigned gpio)
+{
+	void __iomem *ptr;
+
+	if (gpio < 32 * 1)
+		ptr = gpio_base + 0x10;
+	else if (gpio < 32 * 2)
+		ptr = gpio_base + 0x38;
+	else if (gpio < 32 * 3)
+		ptr = gpio_base + 0x60;
+	else if (gpio < 32 * 4)
+		ptr = gpio_base + 0x88;
+	else if (gpio < 32 * 5)
+		ptr = gpio_base + 0xb0;
+	else
+		ptr = NULL;
+	return ptr;
+}
+
+static int davinci_get_direction(struct gpio_chip *chip, unsigned offset)
+{
+	struct davinci_gpio_controller *d = chip2controller(chip);
+	struct davinci_gpio_regs __iomem *g = d->regs;
+
+	return ((readl_relaxed(&g->dir)) & (1 << offset)) ?
+		GPIOF_DIR_IN : GPIOF_DIR_OUT;
+}
+
+static inline int __davinci_direction(struct gpio_chip *chip,
+			unsigned offset, bool out, int value)
+{
+	struct davinci_gpio_controller *d = chip2controller(chip);
+	struct davinci_gpio_regs __iomem *g = d->regs;
+	u32 temp;
+	u32 mask = 1 << offset;
+
+	temp = readl_relaxed(&g->dir);
+	if (out) {
+		temp &= ~mask;
+		writel_relaxed(mask, value ? &g->set_data : &g->clr_data);
+	} else {
+		temp |= mask;
+	}
+	writel_relaxed(temp, &g->dir);
+
+	return 0;
+}
+
+static int davinci_direction_in(struct gpio_chip *chip, unsigned offset)
+{
+	return __davinci_direction(chip, offset, false, 0);
+}
+
+static int
+davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value)
+{
+	return __davinci_direction(chip, offset, true, value);
+}
+
+/*
+ * Read the pin's value (works even if it's set up as output);
+ * returns zero/nonzero.
+ *
+ * Note that changes are synched to the GPIO clock, so reading values back
+ * right after you've set them may give old values.
+ */
+static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset)
+{
+	struct davinci_gpio_controller *d = chip2controller(chip);
+	struct davinci_gpio_regs __iomem *g = d->regs;
+
+	return (1 << offset) & readl_relaxed(&g->in_data);
+}
+
+/*
+ * Assuming the pin is muxed as a gpio output, set its output value.
+ */
+static void
+davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
+{
+	struct davinci_gpio_controller *d = chip2controller(chip);
+	struct davinci_gpio_regs __iomem *g = d->regs;
+
+	writel_relaxed((1 << offset), value ? &g->set_data : &g->clr_data);
+}
+
+static struct gpio_ops davinci_gpio_ops = {
+	.direction_input = davinci_direction_in,
+	.direction_output = davinci_direction_out,
+	.get_direction = davinci_get_direction,
+	.get = davinci_gpio_get,
+	.set = davinci_gpio_set,
+};
+
+static int davinci_gpio_probe(struct device_d *dev)
+{
+	void __iomem *gpio_base;
+	int ret;
+	u32 val;
+	int i, base;
+	unsigned ngpio;
+	struct davinci_gpio_controller *chips;
+
+	ret = of_property_read_u32(dev->device_node, "ti,ngpio", &val);
+	if (ret) {
+		dev_err(dev, "could not read 'ti,ngpio' property\n");
+		return -EINVAL;
+	}
+
+	ngpio = val;
+
+	if (WARN_ON(ARCH_NR_GPIOS < ngpio))
+		ngpio = ARCH_NR_GPIOS;
+
+	chips = xzalloc((ngpio / 32 + 1) * sizeof(*chips));
+
+	gpio_base = dev_request_mem_region(dev, 0);
+	if (!gpio_base) {
+		dev_err(dev, "could not get memory region\n");
+		return -ENODEV;
+	}
+
+	for (i = 0, base = 0; base < ngpio; i++, base += 32) {
+		struct davinci_gpio_regs __iomem *regs;
+		struct gpio_chip *gc;
+
+		gc = &chips[i].chip;
+		gc->ops = &davinci_gpio_ops;
+
+		gc->dev = dev;
+		gc->base = base;
+		gc->ngpio = ngpio - base;
+		if (gc->ngpio > 32)
+			gc->ngpio = 32;
+
+		regs = gpio2regs(gpio_base, base);
+		chips[i].regs = regs;
+		chips[i].set_data = &regs->set_data;
+		chips[i].clr_data = &regs->clr_data;
+		chips[i].in_data = &regs->in_data;
+
+		gpiochip_add(gc);
+	}
+
+	return 0;
+}
+
+static struct of_device_id davinci_gpio_ids[] = {
+	{ .compatible = "ti,dm6441-gpio", },
+	{ /* sentinel */ },
+};
+
+static struct driver_d davinci_gpio_driver = {
+	.name		= "davinci_gpio",
+	.probe		= davinci_gpio_probe,
+	.of_compatible	= DRV_OF_COMPAT(davinci_gpio_ids),
+};
+
+static int davinci_gpio_drv_reg(void)
+{
+	return platform_driver_register(&davinci_gpio_driver);
+}
+coredevice_initcall(davinci_gpio_drv_reg);
-- 
1.9.0



From antonynpavlov at gmail.com  Sun Mar 16 09:48:18 2014
From: antonynpavlov at gmail.com (Antony Pavlov)
Date: Sun, 16 Mar 2014 17:48:18 +0400
Subject: [PATCH v2 07/10] ARM: davinci: add documentation
In-Reply-To: <1394977701-5889-1-git-send-email-antonynpavlov@gmail.com>
References: <1394977701-5889-1-git-send-email-antonynpavlov@gmail.com>
Message-ID: <1394977701-5889-8-git-send-email-antonynpavlov@gmail.com>

Signed-off-by: Antony Pavlov <antonynpavlov at gmail.com>
---
 arch/arm/mach-arm.dox                  | 2 ++
 arch/arm/mach-davinci/mach-davinci.dox | 5 +++++
 2 files changed, 7 insertions(+)

diff --git a/arch/arm/mach-arm.dox b/arch/arm/mach-arm.dox
index 758df3f..1d2de48 100644
--- a/arch/arm/mach-arm.dox
+++ b/arch/arm/mach-arm.dox
@@ -54,6 +54,8 @@ For details on specific architectures:
 
 @subsection mach_arm_omap_info OMAP CPUs
 
+ at li @subpage dev_davinci_arch
+
 @li @subpage dev_omap_arch
 
 @subsection mach_arm_s3c24xx_info S3C24XX CPUs
diff --git a/arch/arm/mach-davinci/mach-davinci.dox b/arch/arm/mach-davinci/mach-davinci.dox
new file mode 100644
index 0000000..f0f3a92
--- /dev/null
+++ b/arch/arm/mach-davinci/mach-davinci.dox
@@ -0,0 +1,5 @@
+/** @page dev_davinci_arch TI DaVinci in barebox
+
+ at section davinci_boards DaVinci-based boards
+
+*/
-- 
1.9.0



From antonynpavlov at gmail.com  Sun Mar 16 09:48:19 2014
From: antonynpavlov at gmail.com (Antony Pavlov)
Date: Sun, 16 Mar 2014 17:48:19 +0400
Subject: [PATCH v2 08/10] ARM: davinci: add virt2real board support
In-Reply-To: <1394977701-5889-1-git-send-email-antonynpavlov@gmail.com>
References: <1394977701-5889-1-git-send-email-antonynpavlov@gmail.com>
Message-ID: <1394977701-5889-9-git-send-email-antonynpavlov@gmail.com>

The virt2real microcontroller, or virturilka,
is a miniature board for creation of WiFi
or internet controllable smart devices.

See http://virt2real.com for details.

Signed-off-by: Antony Pavlov <antonynpavlov at gmail.com>
---
 arch/arm/boards/Makefile             |  1 +
 arch/arm/boards/virt2real/Makefile   |  1 +
 arch/arm/boards/virt2real/board.c    | 27 +++++++++++++++++++++++++++
 arch/arm/boards/virt2real/lowlevel.c | 34 ++++++++++++++++++++++++++++++++++
 arch/arm/dts/virt2real.dts           | 35 +++++++++++++++++++++++++++++++++++
 arch/arm/mach-davinci/Kconfig        |  9 +++++++++
 6 files changed, 107 insertions(+)

diff --git a/arch/arm/boards/Makefile b/arch/arm/boards/Makefile
index 0d8c9cf..e7af889 100644
--- a/arch/arm/boards/Makefile
+++ b/arch/arm/boards/Makefile
@@ -99,4 +99,5 @@ obj-$(CONFIG_MACH_USB_A9263)			+= usb-a926x/
 obj-$(CONFIG_MACH_USB_A9G20)			+= usb-a926x/
 obj-$(CONFIG_MACH_VERSATILEPB)			+= versatile/
 obj-$(CONFIG_MACH_VEXPRESS)			+= vexpress/
+obj-$(CONFIG_MACH_VIRT2REAL)			+= virt2real/
 obj-$(CONFIG_MACH_ZEDBOARD)			+= avnet-zedboard/
diff --git a/arch/arm/boards/virt2real/Makefile b/arch/arm/boards/virt2real/Makefile
new file mode 100644
index 0000000..b2f44bb
--- /dev/null
+++ b/arch/arm/boards/virt2real/Makefile
@@ -0,0 +1 @@
+obj-y += lowlevel.o board.o
diff --git a/arch/arm/boards/virt2real/board.c b/arch/arm/boards/virt2real/board.c
new file mode 100644
index 0000000..b7f7217
--- /dev/null
+++ b/arch/arm/boards/virt2real/board.c
@@ -0,0 +1,27 @@
+/*
+ * Copyright (C) 2014 Antony Pavlov <antonynpavlov at gmail.com>
+ *
+ * This file is part of barebox.
+ * See file CREDITS for list of people who contributed to this project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <common.h>
+#include <init.h>
+
+static int hostname_init(void)
+{
+	barebox_set_hostname("virt2real");
+
+	return 0;
+}
+core_initcall(hostname_init);
diff --git a/arch/arm/boards/virt2real/lowlevel.c b/arch/arm/boards/virt2real/lowlevel.c
new file mode 100644
index 0000000..3c90d78
--- /dev/null
+++ b/arch/arm/boards/virt2real/lowlevel.c
@@ -0,0 +1,34 @@
+/*
+ * Copyright (C) 2014 Antony Pavlov <antonynpavlov at gmail.com>
+ *
+ * This file is part of barebox.
+ * See file CREDITS for list of people who contributed to this project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#define __LOWLEVEL_INIT__
+
+#include <common.h>
+#include <asm/barebox-arm.h>
+#include <asm/barebox-arm-head.h>
+#include <init.h>
+#include <sizes.h>
+
+#define VIRT2REAL_SRAM_BASE 0x82000000
+#define VIRT2REAL_SRAM_SIZE SZ_16M
+
+void __naked __bare_init barebox_arm_reset_vector(void)
+{
+	arm_cpu_lowlevel_init();
+
+	barebox_arm_entry(VIRT2REAL_SRAM_BASE, VIRT2REAL_SRAM_SIZE, 0);
+}
diff --git a/arch/arm/dts/virt2real.dts b/arch/arm/dts/virt2real.dts
new file mode 100644
index 0000000..0e2210a
--- /dev/null
+++ b/arch/arm/dts/virt2real.dts
@@ -0,0 +1,35 @@
+/dts-v1/;
+
+#include "dm365.dtsi"
+
+/ {
+	model = "virt2real";
+
+	memory {
+		reg = <0x82000000 0x01000000>;
+	};
+
+	soc {
+		serial0: serial at 1c20000 {
+			status = "okay";
+		};
+
+		gpio: gpio at 1c67000 {
+			status = "okay";
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		green_led {
+			label = "green led";
+			gpios = <&gpio 73 0>;
+		};
+
+		red_led {
+			label = "red led";
+			gpios = <&gpio 74 0>;
+		};
+	};
+};
diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig
index 5677f8d..3165d50 100644
--- a/arch/arm/mach-davinci/Kconfig
+++ b/arch/arm/mach-davinci/Kconfig
@@ -4,4 +4,13 @@ config ARCH_TEXT_BASE
 	hex
 	default 0x82000000
 
+choice
+	prompt "Davinci Board type"
+
+config MACH_VIRT2REAL
+	bool "Virt2Real"
+	select HAVE_DEFAULT_ENVIRONMENT_NEW
+
+endchoice
+
 endif
-- 
1.9.0



From antonynpavlov at gmail.com  Sun Mar 16 09:48:20 2014
From: antonynpavlov at gmail.com (Antony Pavlov)
Date: Sun, 16 Mar 2014 17:48:20 +0400
Subject: [PATCH v2 09/10] ARM: virt2real: add documentation
In-Reply-To: <1394977701-5889-1-git-send-email-antonynpavlov@gmail.com>
References: <1394977701-5889-1-git-send-email-antonynpavlov@gmail.com>
Message-ID: <1394977701-5889-10-git-send-email-antonynpavlov@gmail.com>

Signed-off-by: Antony Pavlov <antonynpavlov at gmail.com>
---
 Documentation/boards.dox                |  1 +
 arch/arm/boards/virt2real/virt2real.dox | 41 +++++++++++++++++++++++++++++++++
 arch/arm/mach-davinci/mach-davinci.dox  |  2 ++
 3 files changed, 44 insertions(+)

diff --git a/Documentation/boards.dox b/Documentation/boards.dox
index 6bcc14f..9a14aee 100644
--- a/Documentation/boards.dox
+++ b/Documentation/boards.dox
@@ -43,6 +43,7 @@ ARM type:
 @li @subpage tny-a9263
 @li @subpage usb-a9g20-lpw
 @li @subpage usb-a9263
+ at li @subpage virt2real
 
 Blackfin type:
 
diff --git a/arch/arm/boards/virt2real/virt2real.dox b/arch/arm/boards/virt2real/virt2real.dox
new file mode 100644
index 0000000..fc38321
--- /dev/null
+++ b/arch/arm/boards/virt2real/virt2real.dox
@@ -0,0 +1,41 @@
+/** @page virt2real virt2real board
+
+virt2real is a is a miniature board for creation of WiFi
+or internet controllable smart devices.
+
+The board has
+ at li TI DaVinchi DM365 running at 300 MHz
+ at li 128 MiB DDR2 SDRAM;
+ at li 256 MiB NAND Flash Memory;
+ at li 2 x UART serial interfaces;
+ at li 2 x Ethernet interfaces;
+ at li 1 x USB interface;
+ at li microSD card slot.
+
+The board uses U-Boot as bootloader.
+
+Barebox mini-howto:
+
+1. Connect to the boards's UART0 (115200 8N1);
+Use J2.2 (GND), J2.4 (UART0_TXD), J2.6(UART0_RXD) pins.
+
+2. Turn board's power on;
+
+3. Wait 'Hit any key to stop autoboot' prompt and press the space key.
+
+4. Upload barebox.bin via Ymodem
+ at verbatim
+    virt2real ># loady
+ at endverbatim
+
+5. Run barebox
+ at verbatim
+    virt2real ># go 0x82000000
+ at endverbatim
+
+virt2real links:
+ at li http://virt2real.com/
+ at li http://wiki.virt2real.ru/
+ at li https://github.com/virt2real
+
+*/
diff --git a/arch/arm/mach-davinci/mach-davinci.dox b/arch/arm/mach-davinci/mach-davinci.dox
index f0f3a92..789eacc 100644
--- a/arch/arm/mach-davinci/mach-davinci.dox
+++ b/arch/arm/mach-davinci/mach-davinci.dox
@@ -2,4 +2,6 @@
 
 @section davinci_boards DaVinci-based boards
 
+ at li @subpage virt2real
+
 */
-- 
1.9.0



From antonynpavlov at gmail.com  Sun Mar 16 09:48:21 2014
From: antonynpavlov at gmail.com (Antony Pavlov)
Date: Sun, 16 Mar 2014 17:48:21 +0400
Subject: [PATCH v2 10/10] ARM: davinci: add virt2real_defconfig
In-Reply-To: <1394977701-5889-1-git-send-email-antonynpavlov@gmail.com>
References: <1394977701-5889-1-git-send-email-antonynpavlov@gmail.com>
Message-ID: <1394977701-5889-11-git-send-email-antonynpavlov@gmail.com>

Signed-off-by: Antony Pavlov <antonynpavlov at gmail.com>
---
 arch/arm/configs/virt2real_defconfig | 49 ++++++++++++++++++++++++++++++++++++
 1 file changed, 49 insertions(+)

diff --git a/arch/arm/configs/virt2real_defconfig b/arch/arm/configs/virt2real_defconfig
new file mode 100644
index 0000000..a81d18b
--- /dev/null
+++ b/arch/arm/configs/virt2real_defconfig
@@ -0,0 +1,49 @@
+CONFIG_BUILTIN_DTB=y
+CONFIG_BUILTIN_DTB_NAME="virt2real"
+CONFIG_ARCH_DAVINCI=y
+CONFIG_AEABI=y
+CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
+CONFIG_TEXT_BASE=0x82300000
+CONFIG_MALLOC_SIZE=0x200000
+CONFIG_MALLOC_TLSF=y
+CONFIG_PROMPT="virt2real: "
+CONFIG_LONGHELP=y
+CONFIG_GLOB=y
+CONFIG_HUSH_FANCY_PROMPT=y
+CONFIG_CMDLINE_EDITING=y
+CONFIG_AUTO_COMPLETE=y
+CONFIG_MENU=y
+CONFIG_PASSWORD=y
+CONFIG_PARTITION=y
+CONFIG_CMD_EDIT=y
+CONFIG_CMD_SLEEP=y
+CONFIG_CMD_EXPORT=y
+CONFIG_CMD_PRINTENV=y
+CONFIG_CMD_READLINE=y
+CONFIG_CMD_ECHO_E=y
+CONFIG_CMD_LOADB=y
+CONFIG_CMD_LOADY=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_IOMEM=y
+CONFIG_CMD_MM=y
+# CONFIG_CMD_BOOTM is not set
+# CONFIG_CMD_BOOTU is not set
+CONFIG_CMD_RESET=y
+CONFIG_CMD_GO=y
+CONFIG_CMD_OFTREE=y
+CONFIG_CMD_OF_PROPERTY=y
+CONFIG_CMD_OF_NODE=y
+CONFIG_CMD_TIMEOUT=y
+CONFIG_CMD_PARTITION=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_UNCOMPRESS=y
+CONFIG_CMD_LED=y
+CONFIG_OFDEVICE=y
+CONFIG_OF_BAREBOX_DRIVERS=y
+CONFIG_DRIVER_SERIAL_NS16550=y
+# CONFIG_SPI is not set
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_LED_GPIO_OF=y
+CONFIG_SHA1=y
+CONFIG_SHA256=y
-- 
1.9.0



From xobs at kosagi.com  Mon Mar 17 00:28:28 2014
From: xobs at kosagi.com (Sean Cross)
Date: Mon, 17 Mar 2014 12:28:28 +0800
Subject: Porting barebox to Novena: misc questions
In-Reply-To: <20140314082252.GW17250@pengutronix.de>
References: <53211233.5070806@kosagi.com>
 <20140313073817.GR17250@pengutronix.de> <53218604.6080702@kosagi.com>
 <20140313202719.GS17250@pengutronix.de> <532278F0.1040409@kosagi.com>
 <20140314082252.GW17250@pengutronix.de>
Message-ID: <532679EC.4020806@kosagi.com>

On 14/3/14 4:22 PM, Sascha Hauer wrote:
> On Fri, Mar 14, 2014 at 11:35:12AM +0800, Sean Cross wrote:
>> On 14/3/14 4:27 AM, Sascha Hauer wrote:
>>> On Thu, Mar 13, 2014 at 06:18:44PM +0800, Sean Cross wrote:
>>>> On 13/3/14 3:38 PM, Sascha Hauer wrote:
>>>>> Hi Sean,
>>>>>
>>>>> On Thu, Mar 13, 2014 at 10:04:35AM +0800, Sean Cross wrote:
>>>>>> The "usb" command just hangs the system.  It should at least detect the
>>>>>> other ASIX Ethernet port.  I have &usbh1 configured identically to
>>>>>> sabrelite.  Is there something else I need to configure?
>>>>>
>>>>> This usually means the phys are not configured correctly. Are you
>>>>> probing from devicetree?
>>>>
>>>> I am probing from devicetree.  I don't see phys mentioned anywhere
>>>> except in the imx6qdl.dtsi file, which means that in theory there
>>>> shouldn't be anything for me to modify.
>>>
>>> I can try to reproduce this tomorrow on a sabrelite board.
>>>
>>>> Board: Kosagi i.MX6DL Novena Board
>>>> detected i.MX6 DualLite revision 1.1
>>>> ERROR: out of memory
>>>>
>>>> [<5062e9ed>] (unwind_backtrace+0x1/0x74) from [<5061c525>] (panic+0x1d/0x34)
>>>> [<5061c525>] (panic+0x1d/0x34) from [<5061cc27>] (xmemalign+0xf/0x14)
>>>> [<5061cc27>] (xmemalign+0xf/0x14) from [<5062f687>] (mmu_init+0x16b/0x1f8)
>>>> [<5062f687>] (mmu_init+0x16b/0x1f8) from [<50600797>]
>>>> (start_barebox+0x1b/0xd0)
>>>> [<50600797>] (start_barebox+0x1b/0xd0) from [<5062efcd>] (__start+0x91/0xa4)
>>>> [<5062efcd>] (__start+0x91/0xa4) from [<50600005>]
>>>> (__bare_init_start+0x1/0xc)
>>>> ### ERROR ### Please RESET the board ###
>>>>
>>>> If I also enable early MMU, it hangs much much earlier.  When I dug into
>>>> it, it looked like it was trying to place a TTB just outside of the
>>>> allocated memory region, for some reason.
>>>>
>>>> This is with me passing SZ_1G to barebox_arm_entry().  If I pass
>>>> something small like SZ_64M, it hangs completely.  If I instead pass it
>>>> SZ_128M, it works just fine, but of course the MMU still doesn't work.
>>>
>>> I suspect you have some memory setting that doesn't work in your
>>> .config. Could you post it? Particularly the addresses in your backtrace
>>> are outside the reachable memory (0x10000000 + 1GiB = 0x50000000). This
>>> should not happen. Do you have CONFIG_RELOCATABLE enabled? If not, make
>>> sure CONFIG_ARCH_TEXT_BASE is inside the memory you pass to
>>> barebox_arm_entry(). Otherwise the autodetection for usable malloc area
>>> space might produce wrong results.
>>
>> You're on the right track.  Earlier on I started calling
>> barebox_arm_entry(0x10000000 + 0x800000, SZ_1G, fdt), because otherwise
>> it would fail in mysterious ways.  Now that I've got ram passing working
>> correctly, I've set it back to 0x10000000, and I'm able to get further.
>>  I've also increased the MALLOC_SIZE from 8MB to 64MB, which has made
>> some out-of-memory errors go away.
>>
>> Now, it gets much further, even with CONFIG_MMU_EARLY enabled.  Now it
>> crashes with an error that I see SabreSD was getting at one point, but
>> I'm not sure how they resolved it:
>>
>> Board: Kosagi i.MX6DL Novena Board
>> detected i.MX6 DualLite revision 1.1
>> BUG: failure at arch/arm/cpu/mmu.c:122/find_pte()!
>> BUG!
> 
> This can mean that dma_alloc_coherent() is called too early, before
> mmu_init(). That's quite unlikely since the chipidea probe is in
> device_initcall, way after mmu_initcall. Other possibility is that
> mmu_init failed due to missing memory banks.
> 
> Please apply "ARM: MMU: Add some debugging aids and hints" I just sent
> to the list. It adds more sanity checks and hopefully gives more clue
> what is wrong.
> 
>> CONFIG_PBL_IMAGE=y
>> CONFIG_PBL_MULTI_IMAGES=y
>> CONFIG_PBL_RELOCATABLE=y
>> CONFIG_IMAGE_COMPRESSION=y
>> # CONFIG_IMAGE_COMPRESSION_LZ4 is not set
>> CONFIG_IMAGE_COMPRESSION_LZO=y
>> # CONFIG_IMAGE_COMPRESSION_GZIP is not set
>> # CONFIG_IMAGE_COMPRESSION_NONE is not set
>> CONFIG_MMU=y
>> CONFIG_MMU_EARLY=y
>> CONFIG_HAVE_CONFIGURABLE_TEXT_BASE=y
>> CONFIG_TEXT_BASE=0x17800000
>> CONFIG_BAREBOX_MAX_PBL_SIZE=0xffffffff
>> CONFIG_BAREBOX_MAX_BARE_INIT_SIZE=0xffffffff
>> CONFIG_STACK_SIZE=0x400000
> 
> This is too much 0x8000 should be enough.
> 
>> CONFIG_MALLOC_SIZE=0x4000000
> 
> You can also set this to 0x0 in which case barebox will pick a memory
> region inside available SDRAM.
> 
> Your stack size / malloc size settings shouldn't make problems though.

Hi Sascha,

I've applied the patch you sent, along with a separate modification that
prints out the progress of request_sdram_region:

diff --git a/common/memory.c b/common/memory.c
index c82bbaa..d509af7 100644
--- a/common/memory.c
+++ b/common/memory.c
@@ -145,14 +145,20 @@ struct resource *request_sdram_region(const char
*name, re
 {
        struct memory_bank *bank;

+       printf("Trying to request region %s (from 0x%08lx:0x%08lx):",
+               name, start, start + size - 1);
        for_each_memory_bank(bank) {
                struct resource *res;

                res = request_region(bank->res, name, start, start +
size - 1);
-               if (res)
+               if (res) {
+                       printf(" ok\n");
                        return res;
+               }
+               printf(" no");
        }

+       printf(" fail\n");
        return NULL;
 }

Here is the resulting output and BUG from this run:

barebox 2014.03.0-00628-g7fed07d-dirty #158 Mon Mar 17 12:25:45 SGT 2014


Board: Kosagi i.MX6DL Novena Board
detected i.MX6 DualLite revision 1.1
Trying to request region ttb (from 0x4fff4000:0x4fff7fff): ok
Trying to request region malloc space (from 0x4be00000:0x4fdfffff): ok
Trying to request region barebox (from 0x4fe00000:0x4fe4b4a7): ok
Trying to request region barebox data (from 0x4fe4b4a8:0x4fe5c8f7): ok
Trying to request region bss (from 0x4fe5c8f8:0x4fe6214f): ok
Trying to request region stack (from 0x4fff8000:0x4fffffff): ok
mmu: find_pte: TTB for address 0x4cd1e000 is not of type table
mmu: Memory banks:
mmu: #0 0x10000000 - 0xffffffff
BUG: failure at arch/arm/cpu/mmu.c:153/find_pte()!
BUG!
[<4fe2e9cd>] (unwind_backtrace+0x1/0x74) from [<4fe1c525>] (panic+0x1d/0x34)
[<4fe1c525>] (panic+0x1d/0x34) from [<4fe2f4d5>] (remap_range+0x65/0xdc)
[<4fe2f4d5>] (remap_range+0x65/0xdc) from [<4fe2f7d1>]
(dma_alloc_coherent+0x2d/0x34)
[<4fe2f7d1>] (dma_alloc_coherent+0x2d/0x34) from [<4fe0d689>]
(ehci_register+0x41/0xa8)
[<4fe0d689>] (ehci_register+0x41/0xa8) from [<4fe0936f>]
(imx_chipidea_probe+0x123/0x168)
[<4fe0936f>] (imx_chipidea_probe+0x123/0x168) from [<4fe07de7>]
(platform_probe+0x9/0xa)
[<4fe07de7>] (platform_probe+0x9/0xa) from [<4fe07bf9>]
(device_probe+0x11/0x44)
[<4fe07bf9>] (device_probe+0x11/0x44) from [<4fe07c53>]
(match.part.3+0x27/0x30)
[<4fe07c53>] (match.part.3+0x27/0x30) from [<4fe07cb5>]
(register_driver+0x59/0x74)
[<4fe07cb5>] (register_driver+0x59/0x74) from [<4fe00797>]
(start_barebox+0x1b/0xd0)
[<4fe00797>] (start_barebox+0x1b/0xd0) from [<4fe2efc5>] (__start+0xa9/0xbc)
[<4fe2efc5>] (__start+0xa9/0xbc) from [<4fe00005>]
(__bare_init_start+0x1/0xc)
### ERROR ### Please RESET the board ###




From s.hauer at pengutronix.de  Mon Mar 17 02:24:35 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Mon, 17 Mar 2014 07:24:35 +0100
Subject: [PATCH 6/6] ARM: pfla02: Set new ethernet phy tx timings
In-Reply-To: <20140314160132.GA7755@omega>
References: <1394803820-29277-1-git-send-email-s.hauer@pengutronix.de>
 <1394803820-29277-7-git-send-email-s.hauer@pengutronix.de>
 <20140314160132.GA7755@omega>
Message-ID: <20140317062434.GA17250@pengutronix.de>

On Fri, Mar 14, 2014 at 05:01:33PM +0100, Alexander Aring wrote:
> On Fri, Mar 14, 2014 at 02:30:20PM +0100, Sascha Hauer wrote:
> > From: Christian Hemp <c.hemp at phytec.de>
> > 
> > TX_CLK line is approx. 54mm longer than other TX lines which adds
> > a delay of 0.36ns. RGMII need a delay of min. 1.0ns. This mean we have to add
> > a delay of 0.64ns. We choose 0.78 to have a little gap. This can be done by
> > setting GTX pad skew value to 11100
> >  => Set register 2.8 (RGMII Clock Pad Skew) to 0x038F.
> > 
> > Signed-off-by: Christian Hemp <c.hemp at phytec.de>
> > ---
> >  arch/arm/boards/phytec-phyflex-imx6/board.c | 20 ++++++++++++++++++++
> >  1 file changed, 20 insertions(+)
> > 
> > diff --git a/arch/arm/boards/phytec-phyflex-imx6/board.c b/arch/arm/boards/phytec-phyflex-imx6/board.c
> > index f510407..3db88da 100644
> > --- a/arch/arm/boards/phytec-phyflex-imx6/board.c
> > +++ b/arch/arm/boards/phytec-phyflex-imx6/board.c
> > @@ -21,6 +21,9 @@
> >  #include <gpio.h>
> >  #include <init.h>
> >  #include <of.h>
> > +#include <fec.h>
> > +
> > +#include <linux/micrel_phy.h>
> >  
> >  #include <mach/imx6.h>
> >  
> > @@ -36,6 +39,21 @@ static int eth_phy_reset(void)
> >  	return 0;
> >  }
> >  
> > +static void mmd_write_reg(struct phy_device *dev, int device, int reg, int val)
> > +{
> > +	phy_write(dev, 0x0d, device);
> > +	phy_write(dev, 0x0e, reg);
> > +	phy_write(dev, 0x0d, (1 << 14) | device);
> > +	phy_write(dev, 0x0e, val);
> > +}
> > +
> > +static int ksz9031rn_phy_fixup(struct phy_device *dev)
> > +{
> > +	mmd_write_reg(dev, 2, 8, 0x039F);
> > +
> commit msg says 0x038F and here is 0x039F. Which one is correct now?

0x39f is correct, I squashed a followup commit into this one without
fixing the commit message. I changed the commit message accordingly.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From s.hauer at pengutronix.de  Mon Mar 17 02:31:07 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Mon, 17 Mar 2014 07:31:07 +0100
Subject: i.MX21 ADS NAND flash bad blocks scan. Barebox vs Linux
In-Reply-To: <loom.20140313T212720-896@post.gmane.org>
References: <loom.20140313T212720-896@post.gmane.org>
Message-ID: <20140317063107.GB17250@pengutronix.de>

On Thu, Mar 13, 2014 at 08:44:08PM +0000, Cristiano De Alti wrote:
> Hi,
>   I'm probably posting to the wrong list since this is Linux issue.
> I'm still trying to revive this old board.
> 
> This board has a 64MBi Samsung NAND flash that is detected both by Barebox
> (recent snapshot) and Linux 3.4.77.
> 
> The issue is that, while the bad blocks scan takes a negligible time on
> Barebox, it takes 10 minutes to complete on Linux.
> They both detect block 0 as a bad block. This is strange since it is
> guaranteed to be good by the manufacturer but I've read the OOB data with
> barebox and it's marked ad bad. I found this board in the lab and don't know
> how it was used before.
> 
> Barebox code, nand_imx.c, and Linux code, mxc_nand.c, are similar but not
> identical of course. I also think that Linux code was contributed by
> Pengutronix so this is the reason I'm asking here.
> 
> I've enabled debug statements in Linux code and added my own statements.
> As said, scan completes, everything looks OK but it is very slow.

I assume this is a 512 byte page Nand, right? In this case you shouldn't
have any issues with bad block marker swapping.
An issue could be that one party uses a bad block table wereas the other
scans each time. I recommend using a bad block table for barebox and the
kernel.
Maybe somebody has marked block 0 as bad to see whether the ROM Code
handles this properly.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From s.hauer at pengutronix.de  Mon Mar 17 02:39:04 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Mon, 17 Mar 2014 07:39:04 +0100
Subject: problem booting with Micron MT29F8G08ABABAWP ...
In-Reply-To: <53234E31.2070300@icid.cu>
References: <532207C7.9020206@icid.cu> <20140313212810.4179d0c2@e6520eb>
 <53234E31.2070300@icid.cu>
Message-ID: <20140317063904.GC17250@pengutronix.de>

On Fri, Mar 14, 2014 at 02:45:05PM -0400, raespi wrote:
> Hello again ... diving through the drivers/mtd/nand/nand_base.c code
> I managed to boot with this little modification in the
> nand_flash_detect_onfi() function just before exiting from it:
> 
>     if ( mtd->oobsize > 128 )
>       mtd->oobsize = 128;
> 
> Apparently the only allowed oobsizes are 8, 16, 64 and 128 according
> to the nand_scan_ident() function.

You're probably referring to this code:

	/*
	 * If no default placement scheme is given, select an
	 * appropriate one.
	 */
	if (!chip->ecc.layout && (chip->ecc.mode != NAND_ECC_SOFT_BCH)) {
		switch (mtd->oobsize) {
		case 8:
			chip->ecc.layout = &nand_oob_8;
			break;
		case 16:
			chip->ecc.layout = &nand_oob_16;
			break;
		case 64:
			chip->ecc.layout = &nand_oob_64;
			break;
		case 128:
			chip->ecc.layout = &nand_oob_128;
			break;
		default:
			pr_warn("No oob scheme defined for oobsize %d\n",
				   mtd->oobsize);
			BUG();
		}
	}

This check is only executed when you haven't specified an ecc layout in
your chip driver. You probably have to set chip->ecc.layout in your
driver.

For problems like this it often helps to compare it to the kernel code
(provided it works there). The code is quite similar.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From alex.aring at gmail.com  Mon Mar 17 02:40:51 2014
From: alex.aring at gmail.com (Alexander Aring)
Date: Mon, 17 Mar 2014 07:40:51 +0100
Subject: [PATCH 6/6] ARM: pfla02: Set new ethernet phy tx timings
In-Reply-To: <20140317062434.GA17250@pengutronix.de>
References: <1394803820-29277-1-git-send-email-s.hauer@pengutronix.de>
 <1394803820-29277-7-git-send-email-s.hauer@pengutronix.de>
 <20140314160132.GA7755@omega>
 <20140317062434.GA17250@pengutronix.de>
Message-ID: <20140317064048.GA18901@omega>

On Mon, Mar 17, 2014 at 07:24:35AM +0100, Sascha Hauer wrote:
> On Fri, Mar 14, 2014 at 05:01:33PM +0100, Alexander Aring wrote:
> > On Fri, Mar 14, 2014 at 02:30:20PM +0100, Sascha Hauer wrote:
> > > From: Christian Hemp <c.hemp at phytec.de>
> > > 
> > > TX_CLK line is approx. 54mm longer than other TX lines which adds
> > > a delay of 0.36ns. RGMII need a delay of min. 1.0ns. This mean we have to add
> > > a delay of 0.64ns. We choose 0.78 to have a little gap. This can be done by
> > > setting GTX pad skew value to 11100
> > >  => Set register 2.8 (RGMII Clock Pad Skew) to 0x038F.
> > > 
> > > Signed-off-by: Christian Hemp <c.hemp at phytec.de>
> > > ---
> > >  arch/arm/boards/phytec-phyflex-imx6/board.c | 20 ++++++++++++++++++++
> > >  1 file changed, 20 insertions(+)
> > > 
> > > diff --git a/arch/arm/boards/phytec-phyflex-imx6/board.c b/arch/arm/boards/phytec-phyflex-imx6/board.c
> > > index f510407..3db88da 100644
> > > --- a/arch/arm/boards/phytec-phyflex-imx6/board.c
> > > +++ b/arch/arm/boards/phytec-phyflex-imx6/board.c
> > > @@ -21,6 +21,9 @@
> > >  #include <gpio.h>
> > >  #include <init.h>
> > >  #include <of.h>
> > > +#include <fec.h>
> > > +
> > > +#include <linux/micrel_phy.h>
> > >  
> > >  #include <mach/imx6.h>
> > >  
> > > @@ -36,6 +39,21 @@ static int eth_phy_reset(void)
> > >  	return 0;
> > >  }
> > >  
> > > +static void mmd_write_reg(struct phy_device *dev, int device, int reg, int val)
> > > +{
> > > +	phy_write(dev, 0x0d, device);
> > > +	phy_write(dev, 0x0e, reg);
> > > +	phy_write(dev, 0x0d, (1 << 14) | device);
> > > +	phy_write(dev, 0x0e, val);
> > > +}
> > > +
> > > +static int ksz9031rn_phy_fixup(struct phy_device *dev)
> > > +{
> > > +	mmd_write_reg(dev, 2, 8, 0x039F);
> > > +
> > commit msg says 0x038F and here is 0x039F. Which one is correct now?
> 
> 0x39f is correct, I squashed a followup commit into this one without
> fixing the commit message. I changed the commit message accordingly.
> 

ok, thanks Sascha. I just saw this and want to be sure that this is the
right value.

- Alex


From s.hauer at pengutronix.de  Mon Mar 17 02:43:08 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Mon, 17 Mar 2014 07:43:08 +0100
Subject: [PATCH 13/29] clk: introduce CLK_SET_RATE_PARENT flag
In-Reply-To: <1394813201.850386421@f81.i.mail.ru>
References: <1394807569-23620-1-git-send-email-s.hauer@pengutronix.de>
 <1394807569-23620-14-git-send-email-s.hauer@pengutronix.de>
 <1394813201.850386421@f81.i.mail.ru>
Message-ID: <20140317064308.GD17250@pengutronix.de>

On Fri, Mar 14, 2014 at 08:06:41PM +0400, Alexander Shiyan wrote:
> ???????, 14 ????? 2014, 15:32 +01:00 ?? Sascha Hauer <s.hauer at pengutronix.de>:
> > Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
> > ---
> >  include/linux/clk.h | 3 +++
> >  1 file changed, 3 insertions(+)
> > 
> > diff --git a/include/linux/clk.h b/include/linux/clk.h
> > index 7e5010a..2704b0f 100644
> > --- a/include/linux/clk.h
> > +++ b/include/linux/clk.h
> > @@ -196,6 +196,9 @@ static inline int clk_set_rate(struct clk *clk, unsigned long rate)
> >  #endif
> >  
> >  #ifdef CONFIG_COMMON_CLK
> > +
> > +#define CLK_SET_RATE_PARENT     (1 << 0) /* propagate rate change up one level */
> 
> Lets do it same value as in the kernel, ie  CLK_SET_RATE_PARENT BIT(2)

Ok, can do. Maybe it's better when we add more flags from the kernel.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From alex.aring at gmail.com  Mon Mar 17 02:43:30 2014
From: alex.aring at gmail.com (Alexander Aring)
Date: Mon, 17 Mar 2014 07:43:30 +0100
Subject: i.MX21 ADS NAND flash bad blocks scan. Barebox vs Linux
In-Reply-To: <loom.20140313T212720-896@post.gmane.org>
References: <loom.20140313T212720-896@post.gmane.org>
Message-ID: <20140317064328.GB18901@omega>

Hi,

just an idea... don't asking about why. But can you please disable

ARM_OPTIMZED_STRING_FUNCTIONS

and test it again? I will check something there...

- Alex


From s.hauer at pengutronix.de  Mon Mar 17 02:44:01 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Mon, 17 Mar 2014 07:44:01 +0100
Subject: [PATCH] mci: core: Typo fix in printk specifier
In-Reply-To: <1394947424-25936-1-git-send-email-shc_work@mail.ru>
References: <1394947424-25936-1-git-send-email-shc_work@mail.ru>
Message-ID: <20140317064401.GE17250@pengutronix.de>

On Sun, Mar 16, 2014 at 09:23:44AM +0400, Alexander Shiyan wrote:
> Signed-off-by: Alexander Shiyan <shc_work at mail.ru>

Applied, thanks

Sascha

> ---
>  drivers/mci/mci-core.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/mci/mci-core.c b/drivers/mci/mci-core.c
> index a18b555..1dca0c0 100644
> --- a/drivers/mci/mci-core.c
> +++ b/drivers/mci/mci-core.c
> @@ -1813,7 +1813,7 @@ void mci_of_parse(struct mci_host *host)
>  		break;
>  	default:
>  		dev_err(host->hw_dev,
> -			"Invalid \"bus-width\" value %ud!\n", bus_width);
> +			"Invalid \"bus-width\" value %u!\n", bus_width);
>  	}
>  
>  	/* f_max is obtained from the optional "max-frequency" property */
> -- 
> 1.8.3.2
> 
> 
> _______________________________________________
> barebox mailing list
> barebox at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/barebox
> 

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From s.hauer at pengutronix.de  Mon Mar 17 02:47:17 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Mon, 17 Mar 2014 07:47:17 +0100
Subject: [PATCH 0/6] ppc: add Freescale P1022DS board support
In-Reply-To: <1394734204-8181-1-git-send-email-renaud.barbier@ge.com>
References: <1394734204-8181-1-git-send-email-renaud.barbier@ge.com>
Message-ID: <20140317064717.GF17250@pengutronix.de>

On Thu, Mar 13, 2014 at 06:09:57PM +0000, Renaud Barbier wrote:
> Addition of Freescale P1022DS platform and DDR3 support.
> 
> Patches based on import of existing U-Boot code with modifications
> limited to code cleanup, and making DDR2 and DDR3 support co-existent.
> 
> Renaud Barbier (6):
>   ppc: add SoC support for Freescale P1022
>   common: DDR3 SPD verification support
>   ppc: mpc8xxx: add DDR3 support
>   ppc: add Freescale P1022DS board support
>   ppc: mpc85xx:gianfar: add stashing support
>   ppc: P1022DS: update Kconfig and Makefile

Applied all, thanks

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From s.hauer at pengutronix.de  Mon Mar 17 03:05:53 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Mon, 17 Mar 2014 08:05:53 +0100
Subject: [PATCH] ARM: i.MX27: dts: Separate barebox-specific DT changes
In-Reply-To: <1394958444-32489-1-git-send-email-shc_work@mail.ru>
References: <1394958444-32489-1-git-send-email-shc_work@mail.ru>
Message-ID: <20140317070553.GG17250@pengutronix.de>

On Sun, Mar 16, 2014 at 12:27:24PM +0400, Alexander Shiyan wrote:
> To ease DT import from Linux, which is still maintained in-tree, we
> separate barebox-specific changes by including the original dts in
> a separate DT file. This allows to overlay modifications and keep
> clean DT history. Additionally, this patch updates i.MX27 DTS tree.
> 
> Signed-off-by: Alexander Shiyan <shc_work at mail.ru>

Applied, thanks

Sascha

> ---
>  arch/arm/dts/Makefile                          |   3 +-
>  arch/arm/dts/imx27-phytec-phycard-s-rdk-bb.dts |  38 +++++++
>  arch/arm/dts/imx27-phytec-phycard-s-rdk.dts    |  39 +++++--
>  arch/arm/dts/imx27-phytec-phycard-s-som.dts    | 102 -----------------
>  arch/arm/dts/imx27-phytec-phycard-s-som.dtsi   | 103 +++++++++++++++++
>  arch/arm/dts/imx27-pingrp.h                    | 151 -------------------------
>  arch/arm/dts/imx27.dtsi                        |  59 +++++++++-
>  7 files changed, 229 insertions(+), 266 deletions(-)
>  create mode 100644 arch/arm/dts/imx27-phytec-phycard-s-rdk-bb.dts
>  delete mode 100644 arch/arm/dts/imx27-phytec-phycard-s-som.dts
>  create mode 100644 arch/arm/dts/imx27-phytec-phycard-s-som.dtsi
>  delete mode 100644 arch/arm/dts/imx27-pingrp.h
> 
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index 6bac3b9..8ba31b1 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -3,8 +3,7 @@ dtb-$(CONFIG_ARCH_AM33XX) += \
>  	am335x-boneblack.dtb \
>  	am335x-phytec-phycore.dtb
>  dtb-$(CONFIG_ARCH_IMX25) += imx25-karo-tx25.dtb
> -dtb-$(CONFIG_ARCH_IMX27) += imx27-phytec-phycard-s-rdk.dtb \
> -	imx27-phytec-phycard-s-som.dtb
> +dtb-$(CONFIG_ARCH_IMX27) += imx27-phytec-phycard-s-rdk-bb.dtb
>  dtb-$(CONFIG_ARCH_IMX51) += imx51-babbage.dtb \
>  	imx51-genesi-efika-sb.dtb
>  dtb-$(CONFIG_ARCH_IMX53) += imx53-mba53.dtb \
> diff --git a/arch/arm/dts/imx27-phytec-phycard-s-rdk-bb.dts b/arch/arm/dts/imx27-phytec-phycard-s-rdk-bb.dts
> new file mode 100644
> index 0000000..cecfc5a
> --- /dev/null
> +++ b/arch/arm/dts/imx27-phytec-phycard-s-rdk-bb.dts
> @@ -0,0 +1,38 @@
> +/*
> + * Barebox specific DT overlay for Phytec PCA100 RDK
> + */
> +
> +#include "imx27-phytec-phycard-s-rdk.dts"
> +
> +/ {
> +	chosen {
> +		linux,stdout-path = &uart1;
> +
> +		environment at 0 {
> +			compatible = "barebox,environment";
> +			device-path = &nfc, "partname:environment";
> +		};
> +	};
> +};
> +
> +&nfc {
> +	partition at 0 {
> +		label = "boot";
> +		reg = <0x0 0x80000>;
> +	};
> +
> +	partition at 1 {
> +		label = "environment";
> +		reg = <0x80000 0x80000>;
> +	};
> +
> +	partition at 2 {
> +		label = "kernel";
> +		reg = <0x100000 0x400000>;
> +	};
> +
> +	partition at 3 {
> +		label = "root";
> +		reg = <0x500000 0x7b00000>;
> +	};
> +};
> diff --git a/arch/arm/dts/imx27-phytec-phycard-s-rdk.dts b/arch/arm/dts/imx27-phytec-phycard-s-rdk.dts
> index fb2b874..3c3964a 100644
> --- a/arch/arm/dts/imx27-phytec-phycard-s-rdk.dts
> +++ b/arch/arm/dts/imx27-phytec-phycard-s-rdk.dts
> @@ -9,7 +9,7 @@
>   * http://www.gnu.org/copyleft/gpl.html
>   */
>  
> -#include "imx27-phytec-phycard-s-som.dts"
> +#include "imx27-phytec-phycard-s-som.dtsi"
>  
>  / {
>  	model = "Phytec pca100 rapid development kit";
> @@ -76,35 +76,54 @@
>  &iomuxc {
>  	imx27-phycard-s-rdk {
>  		pinctrl_i2c1: i2c1grp {
> -			fsl,pins = <MX27_I2C2_PINGRP1>;
> +			fsl,pins = <
> +				MX27_PAD_I2C2_SDA__I2C2_SDA 0x0
> +				MX27_PAD_I2C2_SCL__I2C2_SCL 0x0
> +			>;
>  		};
>  
>  		pinctrl_owire1: owire1grp {
> -			fsl,pins = <MX27_OWIRE1_PINGRP1>;
> +			fsl,pins = <
> +				MX27_PAD_RTCK__OWIRE 0x0
> +			>;
>  		};
>  
>  		pinctrl_sdhc2: sdhc2grp {
> -			fsl,pins = <MX27_SDHC2_PINGRP1>;
> +			fsl,pins = <
> +				MX27_PAD_SD2_CLK__SD2_CLK 0x0
> +				MX27_PAD_SD2_CMD__SD2_CMD 0x0
> +				MX27_PAD_SD2_D0__SD2_D0 0x0
> +				MX27_PAD_SD2_D1__SD2_D1 0x0
> +				MX27_PAD_SD2_D2__SD2_D2 0x0
> +				MX27_PAD_SD2_D3__SD2_D3 0x0
> +				MX27_PAD_SSI3_RXDAT__GPIO3_29 0x0 /* CD */
> +			>;
>  		};
>  
>  		pinctrl_uart1: uart1grp {
>  			fsl,pins = <
> -				MX27_UART1_PINGRP1
> -				MX27_UART1_RTSCTS_PINGRP1
> +				MX27_PAD_UART1_TXD__UART1_TXD 0x0
> +				MX27_PAD_UART1_RXD__UART1_RXD 0x0
> +				MX27_PAD_UART1_CTS__UART1_CTS 0x0
> +				MX27_PAD_UART1_RTS__UART1_RTS 0x0
>  			>;
>  		};
>  
>  		pinctrl_uart2: uart2grp {
>  			fsl,pins = <
> -				MX27_UART2_PINGRP1
> -				MX27_UART2_RTSCTS_PINGRP1
> +				MX27_PAD_UART2_TXD__UART2_TXD 0x0
> +				MX27_PAD_UART2_RXD__UART2_RXD 0x0
> +				MX27_PAD_UART2_CTS__UART2_CTS 0x0
> +				MX27_PAD_UART2_RTS__UART2_RTS 0x0
>  			>;
>  		};
>  
>  		pinctrl_uart3: uart3grp {
>  			fsl,pins = <
> -				MX27_UART3_PINGRP1
> -				MX27_UART3_RTSCTS_PINGRP1
> +				MX27_PAD_UART3_TXD__UART3_TXD 0x0
> +				MX27_PAD_UART3_RXD__UART3_RXD 0x0
> +				MX27_PAD_UART3_CTS__UART3_CTS 0x0
> +				MX27_PAD_UART3_RTS__UART3_RTS 0x0
>  			>;
>  		};
>  	};
> diff --git a/arch/arm/dts/imx27-phytec-phycard-s-som.dts b/arch/arm/dts/imx27-phytec-phycard-s-som.dts
> deleted file mode 100644
> index a48d4e1..0000000
> --- a/arch/arm/dts/imx27-phytec-phycard-s-som.dts
> +++ /dev/null
> @@ -1,102 +0,0 @@
> -/*
> - * Copyright 2012 Sascha Hauer, Uwe Kleine-K?nig, Steffen Trumtrar
> - * and Markus Pargmann, Pengutronix
> - *
> - * The code contained herein is licensed under the GNU General Public
> - * License. You may obtain a copy of the GNU General Public License
> - * Version 2 or later at the following locations:
> - *
> - * http://www.opensource.org/licenses/gpl-license.html
> - * http://www.gnu.org/copyleft/gpl.html
> - */
> -
> -/dts-v1/;
> -#include "imx27.dtsi"
> -
> -/ {
> -	model = "Phytec pca100";
> -	compatible = "phytec,imx27-pca100", "fsl,imx27";
> -
> -	chosen {
> -		linux,stdout-path = &uart1;
> -
> -		environment at 0 {
> -			compatible = "barebox,environment";
> -			device-path = &nfc, "partname:environment";
> -		};
> -	};
> -
> -	memory {
> -		reg = <0xa0000000 0x08000000>; /* 128MB */
> -	};
> -};
> -
> -&cspi1 {
> -	fsl,spi-num-chipselects = <2>;
> -	cs-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>,
> -		   <&gpio4 27 GPIO_ACTIVE_HIGH>;
> -	status = "okay";
> -};
> -
> -&iomuxc {
> -	imx27-phycard-s-som {
> -		pinctrl_fec1: fec1grp {
> -			fsl,pins = <MX27_FEC1_PINGRP1>;
> -		};
> -
> -		pinctrl_i2c2: i2c2grp {
> -			fsl,pins = <MX27_I2C2_PINGRP1>;
> -		};
> -
> -		pinctrl_nfc: nfcgrp {
> -			fsl,pins = <MX27_NFC_PINGRP1>;
> -		};
> -	};
> -};
> -
> -&fec {
> -	pinctrl-names = "default";
> -	pinctrl-0 = <&pinctrl_fec1>;
> -	status = "okay";
> -};
> -
> -&i2c2 {
> -	pinctrl-names = "default";
> -	pinctrl-0 = <&pinctrl_i2c2>;
> -	status = "okay";
> -
> -	at24 at 52 {
> -		compatible = "at,24c32";
> -		pagesize = <32>;
> -		reg = <0x52>;
> -	};
> -};
> -
> -&nfc {
> -	pinctrl-names = "default";
> -	pinctrl-0 = <&pinctrl_nfc>;
> -	nand-bus-width = <8>;
> -	nand-ecc-mode = "hw";
> -	nand-on-flash-bbt;
> -	status = "okay";
> -
> -	partition at 0 {
> -		label = "boot";
> -		reg = <0x0 0x80000>;
> -	};
> -
> -	partition at 1 {
> -		label = "environment";
> -		reg = <0x80000 0x80000>;
> -	};
> -
> -	partition at 2 {
> -		label = "kernel";
> -		reg = <0x100000 0x400000>;
> -	};
> -
> -	partition at 3 {
> -		label = "root";
> -		reg = <0x500000 0x7b00000>;
> -	};
> -};
> diff --git a/arch/arm/dts/imx27-phytec-phycard-s-som.dtsi b/arch/arm/dts/imx27-phytec-phycard-s-som.dtsi
> new file mode 100644
> index 0000000..1b62480
> --- /dev/null
> +++ b/arch/arm/dts/imx27-phytec-phycard-s-som.dtsi
> @@ -0,0 +1,103 @@
> +/*
> + * Copyright 2012 Sascha Hauer, Uwe Kleine-K?nig, Steffen Trumtrar
> + * and Markus Pargmann, Pengutronix
> + *
> + * The code contained herein is licensed under the GNU General Public
> + * License. You may obtain a copy of the GNU General Public License
> + * Version 2 or later at the following locations:
> + *
> + * http://www.opensource.org/licenses/gpl-license.html
> + * http://www.gnu.org/copyleft/gpl.html
> + */
> +
> +/dts-v1/;
> +#include "imx27.dtsi"
> +
> +/ {
> +	model = "Phytec pca100";
> +	compatible = "phytec,imx27-pca100", "fsl,imx27";
> +
> +	memory {
> +		reg = <0xa0000000 0x08000000>; /* 128MB */
> +	};
> +};
> +
> +&cspi1 {
> +	fsl,spi-num-chipselects = <2>;
> +	cs-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>,
> +		   <&gpio4 27 GPIO_ACTIVE_HIGH>;
> +	status = "okay";
> +};
> +
> +&fec {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_fec1>;
> +	status = "okay";
> +};
> +
> +&i2c2 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_i2c2>;
> +	status = "okay";
> +
> +	at24 at 52 {
> +		compatible = "at,24c32";
> +		pagesize = <32>;
> +		reg = <0x52>;
> +	};
> +};
> +
> +&iomuxc {
> +	imx27-phycard-s-som {
> +		pinctrl_fec1: fec1grp {
> +			fsl,pins = <
> +				MX27_PAD_SD3_CMD__FEC_TXD0 0x0
> +				MX27_PAD_SD3_CLK__FEC_TXD1 0x0
> +				MX27_PAD_ATA_DATA0__FEC_TXD2 0x0
> +				MX27_PAD_ATA_DATA1__FEC_TXD3 0x0
> +				MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0
> +				MX27_PAD_ATA_DATA3__FEC_RXD1 0x0
> +				MX27_PAD_ATA_DATA4__FEC_RXD2 0x0
> +				MX27_PAD_ATA_DATA5__FEC_RXD3 0x0
> +				MX27_PAD_ATA_DATA6__FEC_MDIO 0x0
> +				MX27_PAD_ATA_DATA7__FEC_MDC 0x0
> +				MX27_PAD_ATA_DATA8__FEC_CRS 0x0
> +				MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0
> +				MX27_PAD_ATA_DATA10__FEC_RXD0 0x0
> +				MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0
> +				MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0
> +				MX27_PAD_ATA_DATA13__FEC_COL 0x0
> +				MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0
> +				MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0
> +			>;
> +		};
> +
> +		pinctrl_i2c2: i2c2grp {
> +			fsl,pins = <
> +				MX27_PAD_I2C2_SDA__I2C2_SDA 0x0
> +				MX27_PAD_I2C2_SCL__I2C2_SCL 0x0
> +			>;
> +		};
> +
> +		pinctrl_nfc: nfcgrp {
> +			fsl,pins = <
> +				MX27_PAD_NFRB__NFRB 0x0
> +				MX27_PAD_NFCLE__NFCLE 0x0
> +				MX27_PAD_NFWP_B__NFWP_B 0x0
> +				MX27_PAD_NFCE_B__NFCE_B 0x0
> +				MX27_PAD_NFALE__NFALE 0x0
> +				MX27_PAD_NFRE_B__NFRE_B 0x0
> +				MX27_PAD_NFWE_B__NFWE_B 0x0
> +			>;
> +		};
> +	};
> +};
> +
> +&nfc {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_nfc>;
> +	nand-bus-width = <8>;
> +	nand-ecc-mode = "hw";
> +	nand-on-flash-bbt;
> +	status = "okay";
> +};
> diff --git a/arch/arm/dts/imx27-pingrp.h b/arch/arm/dts/imx27-pingrp.h
> deleted file mode 100644
> index 57ca02f..0000000
> --- a/arch/arm/dts/imx27-pingrp.h
> +++ /dev/null
> @@ -1,151 +0,0 @@
> -/*
> - * Copyright 2013 Markus Pargmann <mpa at pengutronix.de>, Pengutronix
> - *
> - * The code contained herein is licensed under the GNU General Public
> - * License. You may obtain a copy of the GNU General Public License
> - * Version 2 or later at the following locations:
> - *
> - * http://www.opensource.org/licenses/gpl-license.html
> - * http://www.gnu.org/copyleft/gpl.html
> - */
> -#ifndef __DTS_IMX27_PINGRP_H
> -#define __DTS_IMX27_PINGRP_H
> -
> -#include "imx27-pinfunc.h"
> -
> -#define MX27_CSPI1_PINGRP1 \
> -	MX27_PAD_CSPI1_MISO__CSPI1_MISO 0x0 \
> -	MX27_PAD_CSPI1_MOSI__CSPI1_MOSI 0x0 \
> -	MX27_PAD_CSPI1_SCLK__CSPI1_SCLK 0x0
> -
> -#define MX27_CSPI2_PINGRP1 \
> -	MX27_PAD_CSPI2_MISO__CSPI2_MISO 0x0 \
> -	MX27_PAD_CSPI2_MOSI__CSPI2_MOSI 0x0 \
> -	MX27_PAD_CSPI2_SCLK__CSPI2_SCLK 0x0
> -
> -#define MX27_CSPI3_PINGRP1 \
> -	MX27_PAD_SD1_CLK__CSPI3_SCLK 0x0 \
> -	MX27_PAD_SD1_D0__CSPI3_MISO 0x0 \
> -	MX27_PAD_SD1_CMD__CSPI3_MOSI 0x0
> -
> -#define MX27_FB_PINGRP1 \
> -	MX27_PAD_CLS__CLS 0x0 \
> -	MX27_PAD_CONTRAST__CONTRAST 0x0 \
> -	MX27_PAD_LD0__LD0 0x0 \
> -	MX27_PAD_LD1__LD1 0x0 \
> -	MX27_PAD_LD2__LD2 0x0 \
> -	MX27_PAD_LD3__LD3 0x0 \
> -	MX27_PAD_LD4__LD4 0x0 \
> -	MX27_PAD_LD5__LD5 0x0 \
> -	MX27_PAD_LD6__LD6 0x0 \
> -	MX27_PAD_LD7__LD7 0x0 \
> -	MX27_PAD_LD8__LD8 0x0 \
> -	MX27_PAD_LD9__LD9 0x0 \
> -	MX27_PAD_LD10__LD10 0x0 \
> -	MX27_PAD_LD11__LD11 0x0 \
> -	MX27_PAD_LD12__LD12 0x0 \
> -	MX27_PAD_LD13__LD13 0x0 \
> -	MX27_PAD_LD14__LD14 0x0 \
> -	MX27_PAD_LD15__LD15 0x0 \
> -	MX27_PAD_LD16__LD16 0x0 \
> -	MX27_PAD_LD17__LD17 0x0 \
> -	MX27_PAD_LSCLK__LSCLK 0x0 \
> -	MX27_PAD_OE_ACD__OE_ACD 0x0 \
> -	MX27_PAD_PS__PS 0x0 \
> -	MX27_PAD_REV__REV 0x0 \
> -	MX27_PAD_SPL_SPR__SPL_SPR 0x0 \
> -	MX27_PAD_HSYNC__HSYNC 0x0 \
> -	MX27_PAD_VSYNC__VSYNC 0x0
> -
> -#define MX27_FEC1_PINGRP1 \
> -	MX27_PAD_SD3_CMD__FEC_TXD0 0x0 \
> -	MX27_PAD_SD3_CLK__FEC_TXD1 0x0 \
> -	MX27_PAD_ATA_DATA0__FEC_TXD2 0x0 \
> -	MX27_PAD_ATA_DATA1__FEC_TXD3 0x0 \
> -	MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0 \
> -	MX27_PAD_ATA_DATA3__FEC_RXD1 0x0 \
> -	MX27_PAD_ATA_DATA4__FEC_RXD2 0x0 \
> -	MX27_PAD_ATA_DATA5__FEC_RXD3 0x0 \
> -	MX27_PAD_ATA_DATA6__FEC_MDIO 0x0 \
> -	MX27_PAD_ATA_DATA7__FEC_MDC 0x0 \
> -	MX27_PAD_ATA_DATA8__FEC_CRS 0x0 \
> -	MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0 \
> -	MX27_PAD_ATA_DATA10__FEC_RXD0 0x0 \
> -	MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0 \
> -	MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0 \
> -	MX27_PAD_ATA_DATA13__FEC_COL 0x0 \
> -	MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0 \
> -	MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0
> -
> -#define MX27_I2C1_PINGRP1 \
> -	MX27_PAD_I2C_DATA__I2C_DATA 0x0 \
> -	MX27_PAD_I2C_CLK__I2C_CLK 0x0
> -
> -#define MX27_I2C2_PINGRP1 \
> -	MX27_PAD_I2C2_SDA__I2C2_SDA 0x0 \
> -	MX27_PAD_I2C2_SCL__I2C2_SCL 0x0
> -
> -#define MX27_NFC_PINGRP1 \
> -	MX27_PAD_NFRB__NFRB 0x0 \
> -	MX27_PAD_NFCLE__NFCLE 0x0 \
> -	MX27_PAD_NFWP_B__NFWP_B 0x0 \
> -	MX27_PAD_NFCE_B__NFCE_B 0x0 \
> -	MX27_PAD_NFALE__NFALE 0x0 \
> -	MX27_PAD_NFRE_B__NFRE_B 0x0 \
> -	MX27_PAD_NFWE_B__NFWE_B 0x0
> -
> -#define MX27_OWIRE1_PINGRP1 \
> -	MX27_PAD_RTCK__OWIRE 0x0
> -
> -#define MX27_PWM_PINGRP1 \
> -	MX27_PAD_PWMO__PWMO 0x0
> -
> -#define MX27_SDHC1_PINGRP1 \
> -	MX27_PAD_SD1_CLK__SD1_CLK 0x0 \
> -	MX27_PAD_SD1_CMD__SD1_CMD 0x0 \
> -	MX27_PAD_SD1_D0__SD1_D0 0x0 \
> -	MX27_PAD_SD1_D1__SD1_D1 0x0 \
> -	MX27_PAD_SD1_D2__SD1_D2 0x0 \
> -	MX27_PAD_SD1_D3__SD1_D3 0x0
> -
> -#define MX27_SDHC2_PINGRP1 \
> -	MX27_PAD_SD2_CLK__SD2_CLK 0x0 \
> -	MX27_PAD_SD2_CMD__SD2_CMD 0x0 \
> -	MX27_PAD_SD2_D0__SD2_D0 0x0 \
> -	MX27_PAD_SD2_D1__SD2_D1 0x0 \
> -	MX27_PAD_SD2_D2__SD2_D2 0x0 \
> -	MX27_PAD_SD2_D3__SD2_D3 0x0
> -
> -#define MX27_SDHC3_PINGRP1 \
> -	MX27_PAD_SD3_CLK__SD3_CLK 0x0 \
> -	MX27_PAD_SD3_CMD__SD3_CMD 0x0 \
> -	MX27_PAD_SD3_D0__SD3_D0 0x0 \
> -	MX27_PAD_SD3_D1__SD3_D1 0x0 \
> -	MX27_PAD_SD3_D2__SD3_D2 0x0 \
> -	MX27_PAD_SD3_D3__SD3_D3 0x0
> -
> -#define MX27_UART1_PINGRP1 \
> -	MX27_PAD_UART1_TXD__UART1_TXD 0x0 \
> -	MX27_PAD_UART1_RXD__UART1_RXD 0x0
> -
> -#define MX27_UART1_RTSCTS_PINGRP1 \
> -	MX27_PAD_UART1_CTS__UART1_CTS 0x0 \
> -	MX27_PAD_UART1_RTS__UART1_RTS 0x0
> -
> -#define MX27_UART2_PINGRP1 \
> -	MX27_PAD_UART2_TXD__UART2_TXD 0x0 \
> -	MX27_PAD_UART2_RXD__UART2_RXD 0x0
> -
> -#define MX27_UART2_RTSCTS_PINGRP1 \
> -	MX27_PAD_UART2_CTS__UART2_CTS 0x0 \
> -	MX27_PAD_UART2_RTS__UART2_RTS 0x0
> -
> -#define MX27_UART3_PINGRP1 \
> -	MX27_PAD_UART3_TXD__UART3_TXD 0x0 \
> -	MX27_PAD_UART3_RXD__UART3_RXD 0x0
> -
> -#define MX27_UART3_RTSCTS_PINGRP1 \
> -	MX27_PAD_UART3_CTS__UART3_CTS 0x0 \
> -	MX27_PAD_UART3_RTS__UART3_RTS 0x0
> -
> -#endif /* __DTS_IMX27_PINGRP_H */
> diff --git a/arch/arm/dts/imx27.dtsi b/arch/arm/dts/imx27.dtsi
> index 7e98966..83a8247 100644
> --- a/arch/arm/dts/imx27.dtsi
> +++ b/arch/arm/dts/imx27.dtsi
> @@ -10,12 +10,13 @@
>   */
>  
>  #include "skeleton.dtsi"
> -#include "imx27-pingrp.h"
> +#include "imx27-pinfunc.h"
>  #include <dt-bindings/interrupt-controller/irq.h>
>  #include <dt-bindings/gpio/gpio.h>
>  
>  / {
>  	aliases {
> +		ethernet0 = &fec;
>  		gpio0 = &gpio1;
>  		gpio1 = &gpio2;
>  		gpio2 = &gpio3;
> @@ -70,6 +71,26 @@
>  		};
>  	};
>  
> +	usbphy {
> +		compatible = "simple-bus";
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		usbphy0: usbphy at 0 {
> +			compatible = "usb-nop-xceiv";
> +			reg = <0>;
> +			clocks = <&clks 75>;
> +			clock-names = "main_clk";
> +		};
> +
> +		usbphy2: usbphy at 2 {
> +			compatible = "usb-nop-xceiv";
> +			reg = <2>;
> +			clocks = <&clks 75>;
> +			clock-names = "main_clk";
> +		};
> +	};
> +
>  	soc {
>  		#address-cells = <1>;
>  		#size-cells = <1>;
> @@ -439,6 +460,42 @@
>  				iram = <&iram>;
>  			};
>  
> +			usbotg: usb at 10024000 {
> +				compatible = "fsl,imx27-usb";
> +				reg = <0x10024000 0x200>;
> +				interrupts = <56>;
> +				clocks = <&clks 15>;
> +				fsl,usbmisc = <&usbmisc 0>;
> +				fsl,usbphy = <&usbphy0>;
> +				status = "disabled";
> +			};
> +
> +			usbh1: usb at 10024200 {
> +				compatible = "fsl,imx27-usb";
> +				reg = <0x10024200 0x200>;
> +				interrupts = <54>;
> +				clocks = <&clks 15>;
> +				fsl,usbmisc = <&usbmisc 1>;
> +				status = "disabled";
> +			};
> +
> +			usbh2: usb at 10024400 {
> +				compatible = "fsl,imx27-usb";
> +				reg = <0x10024400 0x200>;
> +				interrupts = <55>;
> +				clocks = <&clks 15>;
> +				fsl,usbmisc = <&usbmisc 2>;
> +				fsl,usbphy = <&usbphy2>;
> +				status = "disabled";
> +			};
> +
> +			usbmisc: usbmisc at 10024600 {
> +				#index-cells = <1>;
> +				compatible = "fsl,imx27-usbmisc";
> +				reg = <0x10024600 0x200>;
> +				clocks = <&clks 62>;
> +			};
> +
>  			sahara2: sahara at 10025000 {
>  				compatible = "fsl,imx27-sahara";
>  				reg = <0x10025000 0x1000>;
> -- 
> 1.8.3.2
> 
> 
> _______________________________________________
> barebox mailing list
> barebox at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/barebox

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From s.hauer at pengutronix.de  Mon Mar 17 03:18:58 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Mon, 17 Mar 2014 08:18:58 +0100
Subject: Porting barebox to Novena: misc questions
In-Reply-To: <532679EC.4020806@kosagi.com>
References: <53211233.5070806@kosagi.com>
 <20140313073817.GR17250@pengutronix.de>
 <53218604.6080702@kosagi.com>
 <20140313202719.GS17250@pengutronix.de>
 <532278F0.1040409@kosagi.com>
 <20140314082252.GW17250@pengutronix.de>
 <532679EC.4020806@kosagi.com>
Message-ID: <20140317071857.GH17250@pengutronix.de>

On Mon, Mar 17, 2014 at 12:28:28PM +0800, Sean Cross wrote:
> Here is the resulting output and BUG from this run:
> 
> barebox 2014.03.0-00628-g7fed07d-dirty #158 Mon Mar 17 12:25:45 SGT 2014
> 
> 
> Board: Kosagi i.MX6DL Novena Board
> detected i.MX6 DualLite revision 1.1
> Trying to request region ttb (from 0x4fff4000:0x4fff7fff): ok
> Trying to request region malloc space (from 0x4be00000:0x4fdfffff): ok
> Trying to request region barebox (from 0x4fe00000:0x4fe4b4a7): ok
> Trying to request region barebox data (from 0x4fe4b4a8:0x4fe5c8f7): ok
> Trying to request region bss (from 0x4fe5c8f8:0x4fe6214f): ok
> Trying to request region stack (from 0x4fff8000:0x4fffffff): ok
> mmu: find_pte: TTB for address 0x4cd1e000 is not of type table
> mmu: Memory banks:
> mmu: #0 0x10000000 - 0xffffffff

So you have one memory bank that starts at 0x10000000 which is the
standard SDRAM base for i.MX6. Good. But why is the size 0? Have you
specified this in your devicetree? It should contain the correct size.
It could also be that we do not parse #ddress-cells / #size-cells
correctly (in case one of these is not 1 in your devicetree).

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From s.hauer at pengutronix.de  Mon Mar 17 03:21:32 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Mon, 17 Mar 2014 08:21:32 +0100
Subject: [SPAM] [PATCH] splash: Print error message when no renderer is
 found
In-Reply-To: <20140314171116.GE6478@ns203013.ovh.net>
References: <1394791908-22061-1-git-send-email-s.hauer@pengutronix.de>
 <20140314171116.GE6478@ns203013.ovh.net>
Message-ID: <20140317072132.GI17250@pengutronix.de>

On Fri, Mar 14, 2014 at 06:11:16PM +0100, Jean-Christophe PLAGNIOL-VILLARD wrote:
> On 11:11 Fri 14 Mar     , Sascha Hauer wrote:
> > the splash command silently fails when no renderer is found for
> > an image type. Print an error message in this case.
> > 
> > Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
> > ---
> >  lib/gui/image_renderer.c | 2 ++
> >  1 file changed, 2 insertions(+)
> > 
> > diff --git a/lib/gui/image_renderer.c b/lib/gui/image_renderer.c
> > index 78e5777..9c92983 100644
> > --- a/lib/gui/image_renderer.c
> > +++ b/lib/gui/image_renderer.c
> > @@ -23,6 +23,8 @@ static struct image_renderer *get_renderer(void* buf, size_t bufsize)
> >  			return ir;
> >  	}
> >  
> > +	printf("No renderer found for filetype %s\n", file_type_to_string(type));
> 
> 	eprintf?

ok

Sascha


-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From alex.aring at gmail.com  Mon Mar 17 03:31:53 2014
From: alex.aring at gmail.com (Alexander Aring)
Date: Mon, 17 Mar 2014 08:31:53 +0100
Subject: Porting barebox to Novena: misc questions
In-Reply-To: <20140317071857.GH17250@pengutronix.de>
References: <53211233.5070806@kosagi.com>
 <20140313073817.GR17250@pengutronix.de>
 <53218604.6080702@kosagi.com>
 <20140313202719.GS17250@pengutronix.de>
 <532278F0.1040409@kosagi.com>
 <20140314082252.GW17250@pengutronix.de>
 <532679EC.4020806@kosagi.com>
 <20140317071857.GH17250@pengutronix.de>
Message-ID: <20140317073150.GA21767@omega>

On Mon, Mar 17, 2014 at 08:18:58AM +0100, Sascha Hauer wrote:
> On Mon, Mar 17, 2014 at 12:28:28PM +0800, Sean Cross wrote:
> > Here is the resulting output and BUG from this run:
> > 
> > barebox 2014.03.0-00628-g7fed07d-dirty #158 Mon Mar 17 12:25:45 SGT 2014
> > 
> > 
> > Board: Kosagi i.MX6DL Novena Board
> > detected i.MX6 DualLite revision 1.1
> > Trying to request region ttb (from 0x4fff4000:0x4fff7fff): ok
> > Trying to request region malloc space (from 0x4be00000:0x4fdfffff): ok
> > Trying to request region barebox (from 0x4fe00000:0x4fe4b4a7): ok
> > Trying to request region barebox data (from 0x4fe4b4a8:0x4fe5c8f7): ok
> > Trying to request region bss (from 0x4fe5c8f8:0x4fe6214f): ok
> > Trying to request region stack (from 0x4fff8000:0x4fffffff): ok
> > mmu: find_pte: TTB for address 0x4cd1e000 is not of type table
> > mmu: Memory banks:
> > mmu: #0 0x10000000 - 0xffffffff
> 
> So you have one memory bank that starts at 0x10000000 which is the
> standard SDRAM base for i.MX6. Good. But why is the size 0? Have you
> specified this in your devicetree? It should contain the correct size.
> It could also be that we do not parse #ddress-cells / #size-cells
> correctly (in case one of these is not 1 in your devicetree).
> 

does this smells like an error case which we should handle with a slightly
eprintf? :-)

- Alex


From xobs at kosagi.com  Mon Mar 17 03:44:15 2014
From: xobs at kosagi.com (Sean Cross)
Date: Mon, 17 Mar 2014 15:44:15 +0800
Subject: Porting barebox to Novena: misc questions
In-Reply-To: <20140317071857.GH17250@pengutronix.de>
References: <53211233.5070806@kosagi.com>
 <20140313073817.GR17250@pengutronix.de> <53218604.6080702@kosagi.com>
 <20140313202719.GS17250@pengutronix.de> <532278F0.1040409@kosagi.com>
 <20140314082252.GW17250@pengutronix.de> <532679EC.4020806@kosagi.com>
 <20140317071857.GH17250@pengutronix.de>
Message-ID: <5326A7CF.7020005@kosagi.com>

On 17/3/14 3:18 PM, Sascha Hauer wrote:
> On Mon, Mar 17, 2014 at 12:28:28PM +0800, Sean Cross wrote:
>> Here is the resulting output and BUG from this run:
>>
>> barebox 2014.03.0-00628-g7fed07d-dirty #158 Mon Mar 17 12:25:45 SGT 2014
>>
>>
>> Board: Kosagi i.MX6DL Novena Board
>> detected i.MX6 DualLite revision 1.1
>> Trying to request region ttb (from 0x4fff4000:0x4fff7fff): ok
>> Trying to request region malloc space (from 0x4be00000:0x4fdfffff): ok
>> Trying to request region barebox (from 0x4fe00000:0x4fe4b4a7): ok
>> Trying to request region barebox data (from 0x4fe4b4a8:0x4fe5c8f7): ok
>> Trying to request region bss (from 0x4fe5c8f8:0x4fe6214f): ok
>> Trying to request region stack (from 0x4fff8000:0x4fffffff): ok
>> mmu: find_pte: TTB for address 0x4cd1e000 is not of type table
>> mmu: Memory banks:
>> mmu: #0 0x10000000 - 0xffffffff
> 
> So you have one memory bank that starts at 0x10000000 which is the
> standard SDRAM base for i.MX6. Good. But why is the size 0? Have you
> specified this in your devicetree? It should contain the correct size.
> It could also be that we do not parse #ddress-cells / #size-cells
> correctly (in case one of these is not 1 in your devicetree).

There is no "memory" node in my .dts file, so it's inheriting the
default "memory { device_type = "memory"; reg = <0 0>; };" from
skeleton.dtsi.  I add memory in my board.c file:

static int kosagi_novena_mem_init(void)
{
        /* Pull out RAM capacity, which was stored here in lowlevel.c */
        arm_add_mem_device("ram0", 0x10000000, readl(MX6_SRC_BASE_ADDR +
0x20));
        return 0;
}
mem_initcall(kosagi_novena_mem_init);



From ivor at veriline.co.za  Mon Mar 17 04:47:06 2014
From: ivor at veriline.co.za (Ivor Kruger)
Date: Mon, 17 Mar 2014 10:47:06 +0200
Subject: GPIO setting
In-Reply-To: <CF4C8000.DD58%ivor@veriline.co.za>
References: <CF4C8000.DD58%ivor@veriline.co.za>
Message-ID: <CF4C8306.DD5F%ivor@veriline.co.za>

Hi, sure this is a quick and easy question for the group?

On the OMAP4430, using the command from within barebox prompt to configure
a GPIO for testing hardware:

gpio_direction_output 140 0

Should this be sufficient to set the gpio pin low, or is it required to
still do some pin muxing as well?

Thanks
Ivor




From antonynpavlov at gmail.com  Mon Mar 17 05:37:02 2014
From: antonynpavlov at gmail.com (Antony Pavlov)
Date: Mon, 17 Mar 2014 13:37:02 +0400
Subject: [PATCH v2] clocksource: add dummy software-only clocksource
Message-ID: <1395049022-13693-1-git-send-email-antonynpavlov@gmail.com>

This driver is very handy for initial barebox porting.
It was used for running barebox on DiGiC2-based camera
and initial porting barebox to Loongson-1 and ar9331.

Signed-off-by: Antony Pavlov <antonynpavlov at gmail.com>
Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
Reported-by: Alexander Aring <alex.aring at gmail.com>
Reported-by: Alexander Shiyan <shc_work at mail.ru>
---
 drivers/clocksource/Kconfig  | 22 +++++++++++++++++
 drivers/clocksource/Makefile |  1 +
 drivers/clocksource/dummy.c  | 56 ++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 79 insertions(+)
 create mode 100644 drivers/clocksource/dummy.c

diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index 4ef25ec..f53c933 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -14,6 +14,28 @@ config CLOCKSOURCE_CLPS711X
 	bool
 	depends on ARCH_CLPS711X
 
+config CLOCKSOURCE_DUMMY
+	bool "Enable dummy software-only clocksource"
+	help
+	  When porting barebox to a new SoC there might be a case
+	  of broken or absent clocksource. This causes barebox serial
+	  console to be non functional.
+	  To solve the problem this software-only clocksource driver is used.
+	      WARNING!!! This clocksource doesn't provide correct timing.
+	  To adjust this clocksource please use CONFIG_CLOCKSOURCE_DUMMY_RATE.
+	  The bigger rate valuest makes clocksource "faster".
+	  It's possible to add this clocksource unconditionally.
+	  This clocksource starts very early (pure_initcall) so
+	  real clocksource will take over.
+	  This can help if initialization order is wrong so that
+	  the time functions are used before the real clocksource
+	  was initialized.
+
+config CLOCKSOURCE_DUMMY_RATE
+	int "  dummy clocksource rate"
+	depends on CLOCKSOURCE_DUMMY
+	default 1000
+
 config CLOCKSOURCE_MVEBU
 	bool
 	depends on ARCH_MVEBU
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index 25b7f46..834a15d 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -2,6 +2,7 @@ obj-$(CONFIG_AMBA_SP804) += amba-sp804.o
 obj-$(CONFIG_ARM_SMP_TWD) += arm_smp_twd.o
 obj-$(CONFIG_CLOCKSOURCE_BCM2835) += bcm2835.o
 obj-$(CONFIG_CLOCKSOURCE_CLPS711X) += clps711x.o
+obj-$(CONFIG_CLOCKSOURCE_DUMMY)   += dummy.o
 obj-$(CONFIG_CLOCKSOURCE_MVEBU)   += mvebu.o
 obj-$(CONFIG_CLOCKSOURCE_NOMADIK) += nomadik.o
 obj-$(CONFIG_CLOCKSOURCE_ORION)   += orion.o
diff --git a/drivers/clocksource/dummy.c b/drivers/clocksource/dummy.c
new file mode 100644
index 0000000..154a8cd
--- /dev/null
+++ b/drivers/clocksource/dummy.c
@@ -0,0 +1,56 @@
+/*
+ * Copyright (C) 2013 Antony Pavlov <antonynpavlov at gmail.com>
+ *
+ * This file is part of barebox.
+ * See file CREDITS for list of people who contributed to this project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <common.h>
+#include <init.h>
+#include <clock.h>
+
+static uint64_t dummy_counter;
+
+static uint64_t dummy_cs_read(void)
+{
+	static int first;
+
+	if (!first) {
+		pr_warn("Warning: Using dummy clocksource\n");
+		first = 1;
+	}
+
+	dummy_counter += CONFIG_CLOCKSOURCE_DUMMY_RATE;
+
+	return dummy_counter;
+}
+
+static struct clocksource dummy_cs = {
+	.read	= dummy_cs_read,
+	.mask   = CLOCKSOURCE_MASK(32),
+};
+
+static int clocksource_init(void)
+{
+	dummy_counter = 0;
+
+	clocks_calc_mult_shift(&dummy_cs.mult, &dummy_cs.shift,
+		100000000, NSEC_PER_SEC, 10);
+
+	pr_debug("clocksource_init: mult=%08x, shift=%08x\n",
+			dummy_cs.mult, dummy_cs.shift);
+	init_clock(&dummy_cs);
+
+	return 0;
+}
+pure_initcall(clocksource_init);
-- 
1.9.0



From s.hauer at pengutronix.de  Mon Mar 17 06:53:18 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Mon, 17 Mar 2014 11:53:18 +0100
Subject: Porting barebox to Novena: misc questions
In-Reply-To: <5326A7CF.7020005@kosagi.com>
References: <53211233.5070806@kosagi.com>
 <20140313073817.GR17250@pengutronix.de>
 <53218604.6080702@kosagi.com>
 <20140313202719.GS17250@pengutronix.de>
 <532278F0.1040409@kosagi.com>
 <20140314082252.GW17250@pengutronix.de>
 <532679EC.4020806@kosagi.com>
 <20140317071857.GH17250@pengutronix.de>
 <5326A7CF.7020005@kosagi.com>
Message-ID: <20140317105318.GJ17250@pengutronix.de>

On Mon, Mar 17, 2014 at 03:44:15PM +0800, Sean Cross wrote:
> On 17/3/14 3:18 PM, Sascha Hauer wrote:
> > On Mon, Mar 17, 2014 at 12:28:28PM +0800, Sean Cross wrote:
> >> Here is the resulting output and BUG from this run:
> >>
> >> barebox 2014.03.0-00628-g7fed07d-dirty #158 Mon Mar 17 12:25:45 SGT 2014
> >>
> >>
> >> Board: Kosagi i.MX6DL Novena Board
> >> detected i.MX6 DualLite revision 1.1
> >> Trying to request region ttb (from 0x4fff4000:0x4fff7fff): ok
> >> Trying to request region malloc space (from 0x4be00000:0x4fdfffff): ok
> >> Trying to request region barebox (from 0x4fe00000:0x4fe4b4a7): ok
> >> Trying to request region barebox data (from 0x4fe4b4a8:0x4fe5c8f7): ok
> >> Trying to request region bss (from 0x4fe5c8f8:0x4fe6214f): ok
> >> Trying to request region stack (from 0x4fff8000:0x4fffffff): ok
> >> mmu: find_pte: TTB for address 0x4cd1e000 is not of type table
> >> mmu: Memory banks:
> >> mmu: #0 0x10000000 - 0xffffffff
> > 
> > So you have one memory bank that starts at 0x10000000 which is the
> > standard SDRAM base for i.MX6. Good. But why is the size 0? Have you
> > specified this in your devicetree? It should contain the correct size.
> > It could also be that we do not parse #ddress-cells / #size-cells
> > correctly (in case one of these is not 1 in your devicetree).
> 
> There is no "memory" node in my .dts file, so it's inheriting the
> default "memory { device_type = "memory"; reg = <0 0>; };" from
> skeleton.dtsi.

Ok, that's fine.

> I add memory in my board.c file:
> 
> static int kosagi_novena_mem_init(void)
> {
>         /* Pull out RAM capacity, which was stored here in lowlevel.c */
>         arm_add_mem_device("ram0", 0x10000000, readl(MX6_SRC_BASE_ADDR +
> 0x20));

Are you sure the readl returns the proper memory size? How about
replacing this with a hardcoded value for testing?

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From c.hemp at phytec.de  Mon Mar 17 07:00:52 2014
From: c.hemp at phytec.de (Christian Hemp)
Date: Mon, 17 Mar 2014 12:00:52 +0100
Subject: [PATCH 4/6] ARM: pfla02: Set ODT to recommended setting
In-Reply-To: <1394803820-29277-5-git-send-email-s.hauer@pengutronix.de>
References: <1394803820-29277-1-git-send-email-s.hauer@pengutronix.de>
 <1394803820-29277-5-git-send-email-s.hauer@pengutronix.de>
Message-ID: <1395054052.2700.179.camel@lws-hemp>

Hello Sascha,

We removed this ODT values, because we had problems. I think before we
use this settings we have to do some tests (climate cabinet...) with
different modules.


Christian

Am Freitag, den 14.03.2014, 14:30 +0100 schrieb Sascha Hauer:
> From: Christian Hemp <c.hemp at phytec.de>
> 
> Change the ODT values to  0x11117 (Recommended from Freescale)
> see App note AN4579 "i.MX 6 Series Thermal Management Guidelines"
> 
> Signed-off-by: Christian Hemp <c.hemp at phytec.de>
> Signed-off-by: Philipp Zabel <p.zabel at pengutronix.de>
> ---
>  arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02.h | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02.h b/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02.h
> index 138ae36..fd09054 100644
> --- a/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02.h
> +++ b/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02.h
> @@ -75,8 +75,8 @@ wm 32 0x021b001c 0x04008048
>  wm 32 0x021b0800 0xa1380003
>  wm 32 0x021b4800 0xa1380003
>  wm 32 0x021b0020 0x00005800
> -wm 32 0x021b0818 0x00022227
> -wm 32 0x021b4818 0x00022227
> +wm 32 0x021b0818 0x00011117
> +wm 32 0x021b4818 0x00011117
>  wm 32 0x021b083c 0x433c033f
>  wm 32 0x021b0840 0x033e033d
>  wm 32 0x021b483c 0x43490351




From s.hauer at pengutronix.de  Mon Mar 17 08:09:56 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Mon, 17 Mar 2014 13:09:56 +0100
Subject: GPIO setting
In-Reply-To: <CF4C8306.DD5F%ivor@veriline.co.za>
References: <CF4C8000.DD58%ivor@veriline.co.za>
 <CF4C8306.DD5F%ivor@veriline.co.za>
Message-ID: <20140317120956.GV24917@pengutronix.de>

On Mon, Mar 17, 2014 at 10:47:06AM +0200, Ivor Kruger wrote:
> Hi, sure this is a quick and easy question for the group?
> 
> On the OMAP4430, using the command from within barebox prompt to configure
> a GPIO for testing hardware:
> 
> gpio_direction_output 140 0
> 
> Should this be sufficient to set the gpio pin low, or is it required to
> still do some pin muxing as well?

The gpio functions only configure the gpio controller. If this pin is
not gpio by default, you have to configure the pinmux controller aswell.
There is no way to do that on the barebox commandline other than direct register
writes to the pinmux controller.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From s.hauer at pengutronix.de  Mon Mar 17 08:12:09 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Mon, 17 Mar 2014 13:12:09 +0100
Subject: [PATCH 4/6] ARM: pfla02: Set ODT to recommended setting
In-Reply-To: <1395054052.2700.179.camel@lws-hemp>
References: <1394803820-29277-1-git-send-email-s.hauer@pengutronix.de>
 <1394803820-29277-5-git-send-email-s.hauer@pengutronix.de>
 <1395054052.2700.179.camel@lws-hemp>
Message-ID: <20140317121209.GM17250@pengutronix.de>

Hi Christian,

On Mon, Mar 17, 2014 at 12:00:52PM +0100, Christian Hemp wrote:
> Hello Sascha,
> 
> We removed this ODT values, because we had problems. I think before we
> use this settings we have to do some tests (climate cabinet...) with
> different modules.

Ok, I'll drop the patch then.

Sascha

> 
> 
> Christian
> 
> Am Freitag, den 14.03.2014, 14:30 +0100 schrieb Sascha Hauer:
> > From: Christian Hemp <c.hemp at phytec.de>
> > 
> > Change the ODT values to  0x11117 (Recommended from Freescale)
> > see App note AN4579 "i.MX 6 Series Thermal Management Guidelines"
> > 
> > Signed-off-by: Christian Hemp <c.hemp at phytec.de>
> > Signed-off-by: Philipp Zabel <p.zabel at pengutronix.de>
> > ---
> >  arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02.h | 4 ++--
> >  1 file changed, 2 insertions(+), 2 deletions(-)
> > 
> > diff --git a/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02.h b/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02.h
> > index 138ae36..fd09054 100644
> > --- a/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02.h
> > +++ b/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02.h
> > @@ -75,8 +75,8 @@ wm 32 0x021b001c 0x04008048
> >  wm 32 0x021b0800 0xa1380003
> >  wm 32 0x021b4800 0xa1380003
> >  wm 32 0x021b0020 0x00005800
> > -wm 32 0x021b0818 0x00022227
> > -wm 32 0x021b4818 0x00022227
> > +wm 32 0x021b0818 0x00011117
> > +wm 32 0x021b4818 0x00011117
> >  wm 32 0x021b083c 0x433c033f
> >  wm 32 0x021b0840 0x033e033d
> >  wm 32 0x021b483c 0x43490351
> 
> 
> 

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From ivor at veriline.co.za  Mon Mar 17 09:43:36 2014
From: ivor at veriline.co.za (Ivor Kruger)
Date: Mon, 17 Mar 2014 15:43:36 +0200
Subject: GPIO setting
In-Reply-To: <20140317120956.GV24917@pengutronix.de>
References: <CF4C8000.DD58%ivor@veriline.co.za>
 <CF4C8306.DD5F%ivor@veriline.co.za>
 <20140317120956.GV24917@pengutronix.de>
Message-ID: <CF4CC78F.DDE2%ivor@veriline.co.za>

Thanks for the reply. So I take it I need to edit the mux.c file in the
PCM049(which is the one I use) board directory. I changed the lines as
below:

{I2C4_SDA, (PTU | IEN | M0)},					/* i2c4_sda */
	{MCSPI1_CLK, (M3)},					/* gpio134 */
	{MCSPI1_SOMI, (M3)},					/* gpio135 */
	{MCSPI1_SIMO, (M3)},					/* gpio136 */
	{MCSPI1_CS0, (M3)},					/* gpio137 */
	{MCSPI1_CS1, (M3)},					/* gpio138 */
	{MCSPI1_CS2, (M3)},				/* gpio139 */
	{MCSPI1_CS3, (M3)},					/* gpio140 */
	{UART3_CTS_RCTX, (PTU | IEN | M0)},				/* uart3_tx */

This still did not allow me to change pin conditions. So in the board.c
file for the PCM049, I also added these lines to force the config of the
pins:

 omap_add_display(&pcm049_fb_data);
	gpio_direction_output(135, 1);
	gpio_direction_output(136, 1);
	gpio_direction_output(137, 1);
	gpio_direction_output(138, 1);
	gpio_direction_output(139, 1);
	gpio_direction_output(140, 1);


If I then do the gpiolib command inbarebox, the pins are indicated as gpio
as below:

gpio  133:     false
gpio  134:     false
gpio  135:      true  gpio
gpio  136:      true  gpio
gpio  137:      true  gpio
gpio  138:      true  gpio
gpio  139:      true  gpio
gpio  140:      true  gpio
gpio  141:     false
gpio  142:     false
gpio  143:     false

BUT using the commands:

gpio_direction_output 135 0

And 

gpio_direction_output 135 1

Still does not change the pin condition.

Is there something else I still need to do?

Thanks
Ivor







On 2014/03/17, 2:09 PM, "Sascha Hauer" <s.hauer at pengutronix.de> wrote:

>On Mon, Mar 17, 2014 at 10:47:06AM +0200, Ivor Kruger wrote:
>> Hi, sure this is a quick and easy question for the group?
>> 
>> On the OMAP4430, using the command from within barebox prompt to
>>configure
>> a GPIO for testing hardware:
>> 
>> gpio_direction_output 140 0
>> 
>> Should this be sufficient to set the gpio pin low, or is it required to
>> still do some pin muxing as well?
>
>The gpio functions only configure the gpio controller. If this pin is
>not gpio by default, you have to configure the pinmux controller aswell.
>There is no way to do that on the barebox commandline other than direct
>register
>writes to the pinmux controller.
>
>Sascha
>
>-- 
>Pengutronix e.K.                           |                             |
>Industrial Linux Solutions                 | http://www.pengutronix.de/  |
>Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
>Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |




From cristiano_dealti at hotmail.com  Mon Mar 17 18:09:18 2014
From: cristiano_dealti at hotmail.com (Cristiano De Alti)
Date: Mon, 17 Mar 2014 22:09:18 +0000 (UTC)
Subject: i.MX21 ADS NAND flash bad blocks scan. Barebox vs Linux
References: <loom.20140313T212720-896@post.gmane.org>
 <20140317063107.GB17250@pengutronix.de>
Message-ID: <loom.20140317T223214-735@post.gmane.org>

Sascha Hauer <s.hauer at ...> writes:

> 
> On Thu, Mar 13, 2014 at 08:44:08PM +0000, Cristiano De Alti wrote:
> > Hi,
> >   I'm probably posting to the wrong list since this is Linux issue.
> > I'm still trying to revive this old board.
> > 
> > This board has a 64MBi Samsung NAND flash that is detected both by Barebox
> > (recent snapshot) and Linux 3.4.77.
> > 
> > The issue is that, while the bad blocks scan takes a negligible time on
> > Barebox, it takes 10 minutes to complete on Linux.
> > They both detect block 0 as a bad block. This is strange since it is
> > guaranteed to be good by the manufacturer but I've read the OOB data with
> > barebox and it's marked ad bad. I found this board in the lab and don't know
> > how it was used before.
> > 
> > Barebox code, nand_imx.c, and Linux code, mxc_nand.c, are similar but not
> > identical of course. I also think that Linux code was contributed by
> > Pengutronix so this is the reason I'm asking here.
> > 
> > I've enabled debug statements in Linux code and added my own statements.
> > As said, scan completes, everything looks OK but it is very slow.
> 
> I assume this is a 512 byte page Nand, right? In this case you shouldn't
> have any issues with bad block marker swapping.
> An issue could be that one party uses a bad block table wereas the other
> scans each time. I recommend using a bad block table for barebox and the
> kernel.
> Maybe somebody has marked block 0 as bad to see whether the ROM Code
> handles this properly.
> 
> Sascha
> I

For sure Linux scans and I was under the impression that Barebox did it too.
Is there any CONFIG in Barebox I can check to determine if it uses a bad
block table (I'm pretty sure it does not use it since I've deleted the NAND
device from Barebox and the scan always takes a short time to complete).

The NAND flash is a Samsung K9K1208Q0C with 512 bytes per page and 16 bytes
of OOB data.

The Linux code uses this function to check for operation complete:

/* This function polls the NANDFC to wait for the basic operation to
 * complete by checking the INT bit of config2 register.
 */
static void wait_op_done(struct mxc_nand_host *host, int useirq)
{
        int max_retries = 8000;

        if (useirq) {
                if (!host->check_int(host)) {
                        INIT_COMPLETION(host->op_completion);
                        host->irq_control(host, 1);
                        wait_for_completion(&host->op_completion);
                        pr_debug("@@@CDA: wait_op_done() completed");
                }
        } else {
                while (max_retries-- > 0) {
                        if (host->check_int(host))
                                break;

                        /* CDA */
                        pr_debug(".");

                        udelay(1);
                }
                if (max_retries < 0)
                        pr_debug("%s: INT not set\n", __func__);
        }
}  

Completion of short running operations is done by polling the NFC.
A "." is always printed for these operations while they should actually take
ns to complete on the NAND.

Completion of long running operations are done using the NFC interrupt.
The longest running operation (Data Transfer from Cell to Register) for a
READ command should be 10us.
If I try to use polling for this operation too, by modifying the above code,
I see about 50 '.' printed but the impression is that it takes much more
time given that the scan rate seems in the order of 5-10 pages per second.

Maybe I should try to understand how long it really takes by toggling a
GPIO. I'm not sure if the udelay function is accurate. If it is then the
bottleneck is somewhere else, maybe in the error correction or bad block
scan code.



From cristiano_dealti at hotmail.com  Mon Mar 17 18:25:59 2014
From: cristiano_dealti at hotmail.com (Cristiano De Alti)
Date: Mon, 17 Mar 2014 22:25:59 +0000 (UTC)
Subject: i.MX21 ADS NAND flash bad blocks scan. Barebox vs Linux
References: <loom.20140313T212720-896@post.gmane.org>
 <20140317064328.GB18901@omega>
Message-ID: <loom.20140317T232302-965@post.gmane.org>

Alexander Aring <alex.aring at ...> writes:

> 
> Hi,
> 
> just an idea... don't asking about why. But can you please disable
> 
> ARM_OPTIMZED_STRING_FUNCTIONS
> 
> and test it again? I will check something there...
> 
> - Alex
> 

I've disabled the above CONFIG in Barebox and I don't see any difference in
the duration of the bad blocks scan. Should it take longer?
What was the idea here?
Thanks for your help. I didn't imagine supporting this board was still of
some interest for someone ;)



From xobs at kosagi.com  Mon Mar 17 23:35:26 2014
From: xobs at kosagi.com (Sean Cross)
Date: Tue, 18 Mar 2014 11:35:26 +0800
Subject: Porting barebox to Novena: misc questions
In-Reply-To: <20140317105318.GJ17250@pengutronix.de>
References: <53211233.5070806@kosagi.com>
 <20140313073817.GR17250@pengutronix.de> <53218604.6080702@kosagi.com>
 <20140313202719.GS17250@pengutronix.de> <532278F0.1040409@kosagi.com>
 <20140314082252.GW17250@pengutronix.de> <532679EC.4020806@kosagi.com>
 <20140317071857.GH17250@pengutronix.de> <5326A7CF.7020005@kosagi.com>
 <20140317105318.GJ17250@pengutronix.de>
Message-ID: <5327BEFE.9020003@kosagi.com>

On 17/3/14 6:53 PM, Sascha Hauer wrote:
> On Mon, Mar 17, 2014 at 03:44:15PM +0800, Sean Cross wrote:
>> On 17/3/14 3:18 PM, Sascha Hauer wrote:
>>> On Mon, Mar 17, 2014 at 12:28:28PM +0800, Sean Cross wrote:
>>>> Here is the resulting output and BUG from this run:
>>>>
>>>> barebox 2014.03.0-00628-g7fed07d-dirty #158 Mon Mar 17 12:25:45 SGT 2014
>>>>
>>>>
>>>> Board: Kosagi i.MX6DL Novena Board
>>>> detected i.MX6 DualLite revision 1.1
>>>> Trying to request region ttb (from 0x4fff4000:0x4fff7fff): ok
>>>> Trying to request region malloc space (from 0x4be00000:0x4fdfffff): ok
>>>> Trying to request region barebox (from 0x4fe00000:0x4fe4b4a7): ok
>>>> Trying to request region barebox data (from 0x4fe4b4a8:0x4fe5c8f7): ok
>>>> Trying to request region bss (from 0x4fe5c8f8:0x4fe6214f): ok
>>>> Trying to request region stack (from 0x4fff8000:0x4fffffff): ok
>>>> mmu: find_pte: TTB for address 0x4cd1e000 is not of type table
>>>> mmu: Memory banks:
>>>> mmu: #0 0x10000000 - 0xffffffff
>>>
>>> So you have one memory bank that starts at 0x10000000 which is the
>>> standard SDRAM base for i.MX6. Good. But why is the size 0? Have you
>>> specified this in your devicetree? It should contain the correct size.
>>> It could also be that we do not parse #ddress-cells / #size-cells
>>> correctly (in case one of these is not 1 in your devicetree).
>>
>> There is no "memory" node in my .dts file, so it's inheriting the
>> default "memory { device_type = "memory"; reg = <0 0>; };" from
>> skeleton.dtsi.
> 
> Ok, that's fine.
> 
>> I add memory in my board.c file:
>>
>> static int kosagi_novena_mem_init(void)
>> {
>>         /* Pull out RAM capacity, which was stored here in lowlevel.c */
>>         arm_add_mem_device("ram0", 0x10000000, readl(MX6_SRC_BASE_ADDR +
>> 0x20));
> 
> Are you sure the readl returns the proper memory size? How about
> replacing this with a hardcoded value for testing?

That's very good thinking.  I'm guessing there's a fencepost error
somewhere.  It works if I set it to SZ_1GB, but not when I include the
full amount.  I've tried printing the value stored in that register, and
it is correct.

This works:

        arm_add_mem_device("ram0", 0x10000000, SZ_2G + SZ_1G + SZ_512M +
SZ_128M);

This does not:

        arm_add_mem_device("ram0", 0x10000000, SZ_2G + SZ_1G + SZ_512M +
SZ_128M + 1);

Is there something special about the address 0xf8000000?


Sean


From alex.aring at gmail.com  Tue Mar 18 02:22:22 2014
From: alex.aring at gmail.com (Alexander Aring)
Date: Tue, 18 Mar 2014 07:22:22 +0100
Subject: i.MX21 ADS NAND flash bad blocks scan. Barebox vs Linux
In-Reply-To: <loom.20140317T232302-965@post.gmane.org>
References: <loom.20140313T212720-896@post.gmane.org>
 <20140317064328.GB18901@omega>
 <loom.20140317T232302-965@post.gmane.org>
Message-ID: <20140318062220.GA17105@omega>

On Mon, Mar 17, 2014 at 10:25:59PM +0000, Cristiano De Alti wrote:
> Alexander Aring <alex.aring at ...> writes:
> 
> > 
> > Hi,
> > 
> > just an idea... don't asking about why. But can you please disable
> > 
> > ARM_OPTIMZED_STRING_FUNCTIONS
> > 
> > and test it again? I will check something there...
> > 
> > - Alex
> > 
> 
> I've disabled the above CONFIG in Barebox and I don't see any difference in
> the duration of the bad blocks scan. Should it take longer?
> What was the idea here?
> Thanks for your help. I didn't imagine supporting this board was still of
> some interest for someone ;)
> 

mhh then sorry, I experienced a slow imx nand some time ago, too. The
config ARM_OPTIMZED_STRING_FUNCTIONS helped to improve the speedup. Was
just a try, I never looked deeper into the issue...

The issue was a slow tftp with a 'special' host ethernet card. I never
realize what the real problem was and I don't have this hardware anymore.

- Alex


From s.hauer at pengutronix.de  Tue Mar 18 04:36:19 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Tue, 18 Mar 2014 09:36:19 +0100
Subject: Porting barebox to Novena: misc questions
In-Reply-To: <5327BEFE.9020003@kosagi.com>
References: <20140313073817.GR17250@pengutronix.de>
 <53218604.6080702@kosagi.com>
 <20140313202719.GS17250@pengutronix.de>
 <532278F0.1040409@kosagi.com>
 <20140314082252.GW17250@pengutronix.de>
 <532679EC.4020806@kosagi.com>
 <20140317071857.GH17250@pengutronix.de>
 <5326A7CF.7020005@kosagi.com>
 <20140317105318.GJ17250@pengutronix.de>
 <5327BEFE.9020003@kosagi.com>
Message-ID: <20140318083619.GS17250@pengutronix.de>

On Tue, Mar 18, 2014 at 11:35:26AM +0800, Sean Cross wrote:
> On 17/3/14 6:53 PM, Sascha Hauer wrote:
> > On Mon, Mar 17, 2014 at 03:44:15PM +0800, Sean Cross wrote:
> >> On 17/3/14 3:18 PM, Sascha Hauer wrote:
> >>> On Mon, Mar 17, 2014 at 12:28:28PM +0800, Sean Cross wrote:
> >>>> Here is the resulting output and BUG from this run:
> >>>>
> >>>> barebox 2014.03.0-00628-g7fed07d-dirty #158 Mon Mar 17 12:25:45 SGT 2014
> >>>>
> >>>>
> >>>> Board: Kosagi i.MX6DL Novena Board
> >>>> detected i.MX6 DualLite revision 1.1
> >>>> Trying to request region ttb (from 0x4fff4000:0x4fff7fff): ok
> >>>> Trying to request region malloc space (from 0x4be00000:0x4fdfffff): ok
> >>>> Trying to request region barebox (from 0x4fe00000:0x4fe4b4a7): ok
> >>>> Trying to request region barebox data (from 0x4fe4b4a8:0x4fe5c8f7): ok
> >>>> Trying to request region bss (from 0x4fe5c8f8:0x4fe6214f): ok
> >>>> Trying to request region stack (from 0x4fff8000:0x4fffffff): ok
> >>>> mmu: find_pte: TTB for address 0x4cd1e000 is not of type table
> >>>> mmu: Memory banks:
> >>>> mmu: #0 0x10000000 - 0xffffffff
> >>>
> >>> So you have one memory bank that starts at 0x10000000 which is the
> >>> standard SDRAM base for i.MX6. Good. But why is the size 0? Have you
> >>> specified this in your devicetree? It should contain the correct size.
> >>> It could also be that we do not parse #ddress-cells / #size-cells
> >>> correctly (in case one of these is not 1 in your devicetree).
> >>
> >> There is no "memory" node in my .dts file, so it's inheriting the
> >> default "memory { device_type = "memory"; reg = <0 0>; };" from
> >> skeleton.dtsi.
> > 
> > Ok, that's fine.
> > 
> >> I add memory in my board.c file:
> >>
> >> static int kosagi_novena_mem_init(void)
> >> {
> >>         /* Pull out RAM capacity, which was stored here in lowlevel.c */
> >>         arm_add_mem_device("ram0", 0x10000000, readl(MX6_SRC_BASE_ADDR +
> >> 0x20));
> > 
> > Are you sure the readl returns the proper memory size? How about
> > replacing this with a hardcoded value for testing?
> 
> That's very good thinking.  I'm guessing there's a fencepost error
> somewhere.  It works if I set it to SZ_1GB, but not when I include the
> full amount.  I've tried printing the value stored in that register, and
> it is correct.
> 
> This works:
> 
>         arm_add_mem_device("ram0", 0x10000000, SZ_2G + SZ_1G + SZ_512M +
> SZ_128M);
> 
> This does not:
> 
>         arm_add_mem_device("ram0", 0x10000000, SZ_2G + SZ_1G + SZ_512M +
> SZ_128M + 1);
> 
> Is there something special about the address 0xf8000000?

The memory start and size should be aligned to 1MiB. Otherwise the MMU
code doesn't work. I didn't bother to catch this because all real memory
fulfills this requirement. There's nothing special with 0xf8000000, I
just tried:

arm_add_mem_device("ram0", 0x10000000, SZ_2G + SZ_1G + SZ_512M + SZ_128M + SZ_1M);

and this works on a board I have here (although that board doesn't even
have that amount of memory)

Sascha


-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From xobs at kosagi.com  Tue Mar 18 04:43:32 2014
From: xobs at kosagi.com (Sean Cross)
Date: Tue, 18 Mar 2014 16:43:32 +0800
Subject: Porting barebox to Novena: misc questions
In-Reply-To: <20140318083619.GS17250@pengutronix.de>
References: <20140313073817.GR17250@pengutronix.de>
 <53218604.6080702@kosagi.com> <20140313202719.GS17250@pengutronix.de>
 <532278F0.1040409@kosagi.com> <20140314082252.GW17250@pengutronix.de>
 <532679EC.4020806@kosagi.com> <20140317071857.GH17250@pengutronix.de>
 <5326A7CF.7020005@kosagi.com> <20140317105318.GJ17250@pengutronix.de>
 <5327BEFE.9020003@kosagi.com> <20140318083619.GS17250@pengutronix.de>
Message-ID: <53280734.6000802@kosagi.com>

On 18/3/14 4:36 PM, Sascha Hauer wrote:
> On Tue, Mar 18, 2014 at 11:35:26AM +0800, Sean Cross wrote:
>> On 17/3/14 6:53 PM, Sascha Hauer wrote:
>>> On Mon, Mar 17, 2014 at 03:44:15PM +0800, Sean Cross wrote:
>>>> On 17/3/14 3:18 PM, Sascha Hauer wrote:
>>>>> On Mon, Mar 17, 2014 at 12:28:28PM +0800, Sean Cross wrote:
>>>>>> Here is the resulting output and BUG from this run:
>>>>>>
>>>>>> barebox 2014.03.0-00628-g7fed07d-dirty #158 Mon Mar 17 12:25:45 SGT 2014
>>>>>>
>>>>>>
>>>>>> Board: Kosagi i.MX6DL Novena Board
>>>>>> detected i.MX6 DualLite revision 1.1
>>>>>> Trying to request region ttb (from 0x4fff4000:0x4fff7fff): ok
>>>>>> Trying to request region malloc space (from 0x4be00000:0x4fdfffff): ok
>>>>>> Trying to request region barebox (from 0x4fe00000:0x4fe4b4a7): ok
>>>>>> Trying to request region barebox data (from 0x4fe4b4a8:0x4fe5c8f7): ok
>>>>>> Trying to request region bss (from 0x4fe5c8f8:0x4fe6214f): ok
>>>>>> Trying to request region stack (from 0x4fff8000:0x4fffffff): ok
>>>>>> mmu: find_pte: TTB for address 0x4cd1e000 is not of type table
>>>>>> mmu: Memory banks:
>>>>>> mmu: #0 0x10000000 - 0xffffffff
>>>>>
>>>>> So you have one memory bank that starts at 0x10000000 which is the
>>>>> standard SDRAM base for i.MX6. Good. But why is the size 0? Have you
>>>>> specified this in your devicetree? It should contain the correct size.
>>>>> It could also be that we do not parse #ddress-cells / #size-cells
>>>>> correctly (in case one of these is not 1 in your devicetree).
>>>>
>>>> There is no "memory" node in my .dts file, so it's inheriting the
>>>> default "memory { device_type = "memory"; reg = <0 0>; };" from
>>>> skeleton.dtsi.
>>>
>>> Ok, that's fine.
>>>
>>>> I add memory in my board.c file:
>>>>
>>>> static int kosagi_novena_mem_init(void)
>>>> {
>>>>         /* Pull out RAM capacity, which was stored here in lowlevel.c */
>>>>         arm_add_mem_device("ram0", 0x10000000, readl(MX6_SRC_BASE_ADDR +
>>>> 0x20));
>>>
>>> Are you sure the readl returns the proper memory size? How about
>>> replacing this with a hardcoded value for testing?
>>
>> That's very good thinking.  I'm guessing there's a fencepost error
>> somewhere.  It works if I set it to SZ_1GB, but not when I include the
>> full amount.  I've tried printing the value stored in that register, and
>> it is correct.
>>
>> This works:
>>
>>         arm_add_mem_device("ram0", 0x10000000, SZ_2G + SZ_1G + SZ_512M +
>> SZ_128M);
>>
>> This does not:
>>
>>         arm_add_mem_device("ram0", 0x10000000, SZ_2G + SZ_1G + SZ_512M +
>> SZ_128M + 1);
>>
>> Is there something special about the address 0xf8000000?
> 
> The memory start and size should be aligned to 1MiB. Otherwise the MMU
> code doesn't work. I didn't bother to catch this because all real memory
> fulfills this requirement. There's nothing special with 0xf8000000, I
> just tried:
> 
> arm_add_mem_device("ram0", 0x10000000, SZ_2G + SZ_1G + SZ_512M + SZ_128M + SZ_1M);
> 
> and this works on a board I have here (although that board doesn't even
> have that amount of memory)

Oh, I didn't realize there was a requirement to align to the nearest
megabyte.

In that case, you're right.  I tried this, and it works:

arm_add_mem_device("ram0", 0x10000000, SZ_2G + SZ_1G + SZ_512M + SZ_256M
- SZ_1M);

However, this fails:

arm_add_mem_device("ram0", 0x10000000, SZ_2G + SZ_1G + SZ_512M + SZ_256M);


Sean


From s.hauer at pengutronix.de  Tue Mar 18 04:56:26 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Tue, 18 Mar 2014 09:56:26 +0100
Subject: [PATCH] ARM: MMU: Fix memory reaching to the end of address space
Message-ID: <1395132986-25217-1-git-send-email-s.hauer@pengutronix.de>

For memory reaching the end of the address space
phys + bank->size overflows to 0. Fix this by right shifting
phys and bank->size before adding them.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/cpu/mmu.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/cpu/mmu.c b/arch/arm/cpu/mmu.c
index 84daa3d..bf0141b 100644
--- a/arch/arm/cpu/mmu.c
+++ b/arch/arm/cpu/mmu.c
@@ -200,7 +200,7 @@ static int arm_mmu_remap_sdram(struct memory_bank *bank)
 {
 	unsigned long phys = (unsigned long)bank->start;
 	unsigned long ttb_start = phys >> 20;
-	unsigned long ttb_end = (phys + bank->size) >> 20;
+	unsigned long ttb_end = (phys >> 20) + (bank->size >> 20);
 	unsigned long num_ptes = bank->size >> 10;
 	int i, pte;
 	u32 *ptes;
-- 
1.9.0



From s.hauer at pengutronix.de  Tue Mar 18 04:58:12 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Tue, 18 Mar 2014 09:58:12 +0100
Subject: Porting barebox to Novena: misc questions
In-Reply-To: <53280734.6000802@kosagi.com>
References: <20140313202719.GS17250@pengutronix.de>
 <532278F0.1040409@kosagi.com>
 <20140314082252.GW17250@pengutronix.de>
 <532679EC.4020806@kosagi.com>
 <20140317071857.GH17250@pengutronix.de>
 <5326A7CF.7020005@kosagi.com>
 <20140317105318.GJ17250@pengutronix.de>
 <5327BEFE.9020003@kosagi.com>
 <20140318083619.GS17250@pengutronix.de>
 <53280734.6000802@kosagi.com>
Message-ID: <20140318085811.GU17250@pengutronix.de>

On Tue, Mar 18, 2014 at 04:43:32PM +0800, Sean Cross wrote:
> > arm_add_mem_device("ram0", 0x10000000, SZ_2G + SZ_1G + SZ_512M + SZ_128M + SZ_1M);
> > 
> > and this works on a board I have here (although that board doesn't even
> > have that amount of memory)
> 
> Oh, I didn't realize there was a requirement to align to the nearest
> megabyte.
> 
> In that case, you're right.  I tried this, and it works:
> 
> arm_add_mem_device("ram0", 0x10000000, SZ_2G + SZ_1G + SZ_512M + SZ_256M
> - SZ_1M);
> 
> However, this fails:
> 
> arm_add_mem_device("ram0", 0x10000000, SZ_2G + SZ_1G + SZ_512M + SZ_256M);

You are really exploring corner cases here ;)

Try this:

--------------------------8<--------------------

>From 4a84905c61d4a4a895c83f4f156f60a7258e6413 Mon Sep 17 00:00:00 2001
From: Sascha Hauer <s.hauer at pengutronix.de>
Date: Tue, 18 Mar 2014 09:53:18 +0100
Subject: [PATCH] ARM: MMU: Fix memory reaching to the end of address space

For memory reaching the end of the address space
phys + bank->size overflows to 0. Fix this by right shifting
phys and bank->size before adding them.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/cpu/mmu.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/cpu/mmu.c b/arch/arm/cpu/mmu.c
index 84daa3d..bf0141b 100644
--- a/arch/arm/cpu/mmu.c
+++ b/arch/arm/cpu/mmu.c
@@ -200,7 +200,7 @@ static int arm_mmu_remap_sdram(struct memory_bank *bank)
 {
 	unsigned long phys = (unsigned long)bank->start;
 	unsigned long ttb_start = phys >> 20;
-	unsigned long ttb_end = (phys + bank->size) >> 20;
+	unsigned long ttb_end = (phys >> 20) + (bank->size >> 20);
 	unsigned long num_ptes = bank->size >> 10;
 	int i, pte;
 	u32 *ptes;
-- 
1.9.0

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From xobs at kosagi.com  Tue Mar 18 05:04:28 2014
From: xobs at kosagi.com (Sean Cross)
Date: Tue, 18 Mar 2014 17:04:28 +0800
Subject: Porting barebox to Novena: misc questions
In-Reply-To: <20140318085811.GU17250@pengutronix.de>
References: <20140313202719.GS17250@pengutronix.de>
 <532278F0.1040409@kosagi.com> <20140314082252.GW17250@pengutronix.de>
 <532679EC.4020806@kosagi.com> <20140317071857.GH17250@pengutronix.de>
 <5326A7CF.7020005@kosagi.com> <20140317105318.GJ17250@pengutronix.de>
 <5327BEFE.9020003@kosagi.com> <20140318083619.GS17250@pengutronix.de>
 <53280734.6000802@kosagi.com> <20140318085811.GU17250@pengutronix.de>
Message-ID: <53280C1C.1040802@kosagi.com>

On 18/3/14 4:58 PM, Sascha Hauer wrote:
> On Tue, Mar 18, 2014 at 04:43:32PM +0800, Sean Cross wrote:
>>> arm_add_mem_device("ram0", 0x10000000, SZ_2G + SZ_1G + SZ_512M + SZ_128M + SZ_1M);
>>>
>>> and this works on a board I have here (although that board doesn't even
>>> have that amount of memory)
>>
>> Oh, I didn't realize there was a requirement to align to the nearest
>> megabyte.
>>
>> In that case, you're right.  I tried this, and it works:
>>
>> arm_add_mem_device("ram0", 0x10000000, SZ_2G + SZ_1G + SZ_512M + SZ_256M
>> - SZ_1M);
>>
>> However, this fails:
>>
>> arm_add_mem_device("ram0", 0x10000000, SZ_2G + SZ_1G + SZ_512M + SZ_256M);
> 
> You are really exploring corner cases here ;)
> 
> Try this:
> 
> --------------------------8<--------------------
> 
> From 4a84905c61d4a4a895c83f4f156f60a7258e6413 Mon Sep 17 00:00:00 2001
> From: Sascha Hauer <s.hauer at pengutronix.de>
> Date: Tue, 18 Mar 2014 09:53:18 +0100
> Subject: [PATCH] ARM: MMU: Fix memory reaching to the end of address space
> 
> For memory reaching the end of the address space
> phys + bank->size overflows to 0. Fix this by right shifting
> phys and bank->size before adding them.
> 
> Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
> ---
>  arch/arm/cpu/mmu.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm/cpu/mmu.c b/arch/arm/cpu/mmu.c
> index 84daa3d..bf0141b 100644
> --- a/arch/arm/cpu/mmu.c
> +++ b/arch/arm/cpu/mmu.c
> @@ -200,7 +200,7 @@ static int arm_mmu_remap_sdram(struct memory_bank *bank)
>  {
>  	unsigned long phys = (unsigned long)bank->start;
>  	unsigned long ttb_start = phys >> 20;
> -	unsigned long ttb_end = (phys + bank->size) >> 20;
> +	unsigned long ttb_end = (phys >> 20) + (bank->size >> 20);
>  	unsigned long num_ptes = bank->size >> 10;
>  	int i, pte;
>  	u32 *ptes;
> 


That fixes the problem for booting with the MMU enabled.  Now I can use
the entire memory range.  Go ahead and add my tested-by:

Tested-by: Sean Cross <xobs at kosagi.com>

It's certainly looking a whole lot better now.  The board still suffers
from quirks, such as the 10-second delay during boot when the network
driver is enabled and the cable is unplugged (even if I have 'ip=none'
in my env/config file), and the following crash when I try to start up
USB now:

barebox at Kosagi i.MX6DL Novena Board:/ usb
USB: scanning bus for devices...
unable to handle paging request at address 0x4fe4bc03
pc : [<4fe0ce76>]    lr : [<4fe09171>]
sp : 4ffffd88  ip : 00000016  fp : 4fffff10
r10: 4cca08f4  r9 : 4fe4b6b8  r8 : 00200200
r7 : 00100100  r6 : 4fe4aa14  r5 : 00000000  r4 : 4be19f6c
r3 : 4fe4bc00  r2 : 00010011  r1 : 80088000  r0 : 00000000
Flags: Nzcv  IRQs off  FIQs off  Mode SVC_32
[<4fe0ce76>] (ehci_init+0x62/0xcc) from [<4fe08d5f>]
(usb_host_detect+0x83/0xb4)
[<4fe08d5f>] (usb_host_detect+0x83/0xb4) from [<4fe08dbd>]
(usb_rescan+0x2d/0x50)
[<4fe08dbd>] (usb_rescan+0x2d/0x50) from [<4fe1a5cd>] (do_usb+0x25/0x2c)
[<4fe1a5cd>] (do_usb+0x25/0x2c) from [<4fe029bd>]
(execute_command+0x21/0x48)
[<4fe029bd>] (execute_command+0x21/0x48) from [<4fe06efb>]
(run_list_real+0x54b/0x618)
[<4fe06efb>] (run_list_real+0x54b/0x618) from [<4fe06877>]
(parse_stream_outer+0x107/0x19c)
[<4fe06877>] (parse_stream_outer+0x107/0x19c) from [<4fe070cd>]
(run_shell+0x29/0x54)
[<4fe070cd>] (run_shell+0x29/0x54) from [<4fe00815>]
(start_barebox+0x99/0xd0)
[<4fe00815>] (start_barebox+0x99/0xd0) from [<4fe2eb05>] (__start+0xa9/0xbc)
[<4fe2eb05>] (__start+0xa9/0xbc) from [<4fe00005>]
(__bare_init_start+0x1/0xc)

[<4fe2e50d>] (unwind_backtrace+0x1/0x74) from [<4fe1c68d>] (panic+0x1d/0x34)
[<4fe1c68d>] (panic+0x1d/0x34) from [<4fe2e9c1>] (do_exception+0xd/0x10)
[<4fe2e9c1>] (do_exception+0xd/0x10) from [<4fe2ea29>]
(do_data_abort+0x21/0x2c)
[<4fe2ea29>] (do_data_abort+0x21/0x2c) from [<4fe2e6e8>]
(data_abort+0x48/0x60)

But the mystery of the MMU has been solved.


Sean


From ivor at veriline.co.za  Tue Mar 18 05:21:47 2014
From: ivor at veriline.co.za (Ivor Kruger)
Date: Tue, 18 Mar 2014 11:21:47 +0200
Subject: GPIO setting
In-Reply-To: <20140317120956.GV24917@pengutronix.de>
References: <CF4C8000.DD58%ivor@veriline.co.za>
 <CF4C8306.DD5F%ivor@veriline.co.za>
 <20140317120956.GV24917@pengutronix.de>
Message-ID: <CF4DDB75.DE67%ivor@veriline.co.za>

Hi, I am still having a problem with the GPIO.

When I check the mux registers for the GPIO pins I want to use, i get:

barebox at Phytec phyCORE pcm049:/ md 0x4a100130
4a100130: 00070118 00070007 00070007 00070007
................
4a100140: 00000118 00000100 01180118 01180118
................

This indicates that the pins are still in safe mode despite the settings
of below in the mux.c file.

{MCSPI1_CLK, (M3)},					/* gpio134 */
	{MCSPI1_SOMI, (M3)},					/* gpio135 */
	{MCSPI1_SIMO, (M3)},					/* gpio136 */
	{MCSPI1_CS0, (M3)},					/* gpio137 */
	{MCSPI1_CS1, (M3)},					/* gpio138 */
	{MCSPI1_CS2, (M3)},					/* gpio139 */
	{MCSPI1_CS3, (M3)},					/* gpio140 */

In the board file I have the following code:

static int pcm049_devices_init(void)
{
	i2c_register_board_info(0, i2c_devices, ARRAY_SIZE(i2c_devices));
	omap44xx_add_i2c1(NULL);
	omap44xx_add_mmc1(NULL);

	gpmc_generic_init(0x10);

	pcm049_network_init();

	omap_add_gpmc_nand_device(&nand_plat);

#ifdef CONFIG_PARTITION
	devfs_add_partition("nand0", 0x00000, SZ_128K, DEVFS_PARTITION_FIXED,
"xload_raw");
	dev_add_bb_dev("xload_raw", "xload");
	devfs_add_partition("nand0", SZ_128K, SZ_512K, DEVFS_PARTITION_FIXED,
"self_raw");
	dev_add_bb_dev("self_raw", "self0");
	devfs_add_partition("nand0", SZ_128K + SZ_512K, SZ_128K,
DEVFS_PARTITION_FIXED, "env_raw");
	dev_add_bb_dev("env_raw", "env0");
#endif

	armlinux_set_bootparams((void *)0x80000100);
	armlinux_set_architecture(MACH_TYPE_PCM049);

	omap_add_display(&pcm049_fb_data);

	gpio_direction_output(134, 1);
	gpio_direction_output(135, 1);
	gpio_direction_output(136, 1);
	gpio_direction_output(137, 1);
	gpio_direction_output(138, 0);
	gpio_direction_output(139, 0);
	gpio_direction_output(140, 0);

	return 0;
}

If I do a mw 0x4a10013c 0x00030003 the register is changed as expected. I
can then use the gpio_direction_output command to toggle the pin.


So the problem clearly lies within the way the mux registers are
configured.

Any ideas on what I am doing wrong

Vielen dank
Ivor





On 2014/03/17, 2:09 PM, "Sascha Hauer" <s.hauer at pengutronix.de> wrote:

>On Mon, Mar 17, 2014 at 10:47:06AM +0200, Ivor Kruger wrote:
>> Hi, sure this is a quick and easy question for the group?
>> 
>> On the OMAP4430, using the command from within barebox prompt to
>>configure
>> a GPIO for testing hardware:
>> 
>> gpio_direction_output 140 0
>> 
>> Should this be sufficient to set the gpio pin low, or is it required to
>> still do some pin muxing as well?
>
>The gpio functions only configure the gpio controller. If this pin is
>not gpio by default, you have to configure the pinmux controller aswell.
>There is no way to do that on the barebox commandline other than direct
>register
>writes to the pinmux controller.
>
>Sascha
>
>-- 
>Pengutronix e.K.                           |                             |
>Industrial Linux Solutions                 | http://www.pengutronix.de/  |
>Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
>Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |




From ivor at veriline.co.za  Tue Mar 18 05:40:52 2014
From: ivor at veriline.co.za (Ivor Kruger)
Date: Tue, 18 Mar 2014 11:40:52 +0200
Subject: GPIO setting
In-Reply-To: <CF4DDB75.DE67%ivor@veriline.co.za>
References: <CF4C8000.DD58%ivor@veriline.co.za>
 <CF4C8306.DD5F%ivor@veriline.co.za>
 <20140317120956.GV24917@pengutronix.de>
 <CF4DDB75.DE67%ivor@veriline.co.za>
Message-ID: <CF4DE0B6.DE83%ivor@veriline.co.za>

Hi, actually, I found my problem.

You know how they say that assumptions are the mother of all screw ups?

Well I assumed that the function set_muxconf_regs() was called in the init
function?upon checking I found that it was not, thus the mux was just set
to the default values and no amount of editing in the settings made a
difference.

So I added it to  be the first line in the "static int
pcm049_devices_init(void)? function.

Now the mux gets configured correctly.

Regards
Ivor


On 2014/03/18, 11:21 AM, "Ivor Kruger" <ivor at veriline.co.za> wrote:

>Hi, I am still having a problem with the GPIO.
>
>When I check the mux registers for the GPIO pins I want to use, i get:
>
>barebox at Phytec phyCORE pcm049:/ md 0x4a100130
>4a100130: 00070118 00070007 00070007 00070007
>................
>4a100140: 00000118 00000100 01180118 01180118
>................
>
>This indicates that the pins are still in safe mode despite the settings
>of below in the mux.c file.
>
>{MCSPI1_CLK, (M3)},					/* gpio134 */
>	{MCSPI1_SOMI, (M3)},					/* gpio135 */
>	{MCSPI1_SIMO, (M3)},					/* gpio136 */
>	{MCSPI1_CS0, (M3)},					/* gpio137 */
>	{MCSPI1_CS1, (M3)},					/* gpio138 */
>	{MCSPI1_CS2, (M3)},					/* gpio139 */
>	{MCSPI1_CS3, (M3)},					/* gpio140 */
>
>In the board file I have the following code:
>
>static int pcm049_devices_init(void)
>{
>	i2c_register_board_info(0, i2c_devices, ARRAY_SIZE(i2c_devices));
>	omap44xx_add_i2c1(NULL);
>	omap44xx_add_mmc1(NULL);
>
>	gpmc_generic_init(0x10);
>
>	pcm049_network_init();
>
>	omap_add_gpmc_nand_device(&nand_plat);
>
>#ifdef CONFIG_PARTITION
>	devfs_add_partition("nand0", 0x00000, SZ_128K, DEVFS_PARTITION_FIXED,
>"xload_raw");
>	dev_add_bb_dev("xload_raw", "xload");
>	devfs_add_partition("nand0", SZ_128K, SZ_512K, DEVFS_PARTITION_FIXED,
>"self_raw");
>	dev_add_bb_dev("self_raw", "self0");
>	devfs_add_partition("nand0", SZ_128K + SZ_512K, SZ_128K,
>DEVFS_PARTITION_FIXED, "env_raw");
>	dev_add_bb_dev("env_raw", "env0");
>#endif
>
>	armlinux_set_bootparams((void *)0x80000100);
>	armlinux_set_architecture(MACH_TYPE_PCM049);
>
>	omap_add_display(&pcm049_fb_data);
>
>	gpio_direction_output(134, 1);
>	gpio_direction_output(135, 1);
>	gpio_direction_output(136, 1);
>	gpio_direction_output(137, 1);
>	gpio_direction_output(138, 0);
>	gpio_direction_output(139, 0);
>	gpio_direction_output(140, 0);
>
>	return 0;
>}
>
>If I do a mw 0x4a10013c 0x00030003 the register is changed as expected. I
>can then use the gpio_direction_output command to toggle the pin.
>
>
>So the problem clearly lies within the way the mux registers are
>configured.
>
>Any ideas on what I am doing wrong
>
>Vielen dank
>Ivor
>
>
>
>
>
>On 2014/03/17, 2:09 PM, "Sascha Hauer" <s.hauer at pengutronix.de> wrote:
>
>>On Mon, Mar 17, 2014 at 10:47:06AM +0200, Ivor Kruger wrote:
>>> Hi, sure this is a quick and easy question for the group?
>>> 
>>> On the OMAP4430, using the command from within barebox prompt to
>>>configure
>>> a GPIO for testing hardware:
>>> 
>>> gpio_direction_output 140 0
>>> 
>>> Should this be sufficient to set the gpio pin low, or is it required to
>>> still do some pin muxing as well?
>>
>>The gpio functions only configure the gpio controller. If this pin is
>>not gpio by default, you have to configure the pinmux controller aswell.
>>There is no way to do that on the barebox commandline other than direct
>>register
>>writes to the pinmux controller.
>>
>>Sascha
>>
>>-- 
>>Pengutronix e.K.                           |
>>|
>>Industrial Linux Solutions                 | http://www.pengutronix.de/
>>|
>>Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0
>>|
>>Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555
>>|




From s.hauer at pengutronix.de  Tue Mar 18 12:18:47 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Tue, 18 Mar 2014 17:18:47 +0100
Subject: GPIO setting
In-Reply-To: <CF4CC78F.DDE2%ivor@veriline.co.za>
References: <CF4C8000.DD58%ivor@veriline.co.za>
 <CF4C8306.DD5F%ivor@veriline.co.za>
 <20140317120956.GV24917@pengutronix.de>
 <CF4CC78F.DDE2%ivor@veriline.co.za>
Message-ID: <20140318161847.GW17250@pengutronix.de>

On Mon, Mar 17, 2014 at 03:43:36PM +0200, Ivor Kruger wrote:
> Thanks for the reply. So I take it I need to edit the mux.c file in the
> PCM049(which is the one I use) board directory. I changed the lines as
> below:
> 
> {I2C4_SDA, (PTU | IEN | M0)},					/* i2c4_sda */
> 	{MCSPI1_CLK, (M3)},					/* gpio134 */
> 	{MCSPI1_SOMI, (M3)},					/* gpio135 */
> 	{MCSPI1_SIMO, (M3)},					/* gpio136 */
> 	{MCSPI1_CS0, (M3)},					/* gpio137 */
> 	{MCSPI1_CS1, (M3)},					/* gpio138 */
> 	{MCSPI1_CS2, (M3)},				/* gpio139 */
> 	{MCSPI1_CS3, (M3)},					/* gpio140 */
> 	{UART3_CTS_RCTX, (PTU | IEN | M0)},				/* uart3_tx */
> 
> This still did not allow me to change pin conditions. So in the board.c
> file for the PCM049, I also added these lines to force the config of the
> pins:
> 
>  omap_add_display(&pcm049_fb_data);
> 	gpio_direction_output(135, 1);
> 	gpio_direction_output(136, 1);
> 	gpio_direction_output(137, 1);
> 	gpio_direction_output(138, 1);
> 	gpio_direction_output(139, 1);
> 	gpio_direction_output(140, 1);
> 
> 
> If I then do the gpiolib command inbarebox, the pins are indicated as gpio
> as below:
> 
> gpio  133:     false
> gpio  134:     false
> gpio  135:      true  gpio
> gpio  136:      true  gpio
> gpio  137:      true  gpio
> gpio  138:      true  gpio
> gpio  139:      true  gpio
> gpio  140:      true  gpio
> gpio  141:     false
> gpio  142:     false
> gpio  143:     false
> 
> BUT using the commands:
> 
> gpio_direction_output 135 0
> 
> And 
> 
> gpio_direction_output 135 1
> 
> Still does not change the pin condition.
> 
> Is there something else I still need to do?

Generally that's all you have to do: Configure pinmux and use gpio
functions. I'm not very familiar with OMAPs. How does the translation
from MCSPI1_SOMI to gpio135 work? Are you sure the gpio number is
correct? Is gpio generally M3 and what do the other flags lie IEN and
PTU do? I have no idea what goes wrong here, but that would be the next
places I would look at.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From s.hauer at pengutronix.de  Tue Mar 18 12:27:19 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Tue, 18 Mar 2014 17:27:19 +0100
Subject: [PATCH v2] clocksource: add dummy software-only clocksource
In-Reply-To: <1395049022-13693-1-git-send-email-antonynpavlov@gmail.com>
References: <1395049022-13693-1-git-send-email-antonynpavlov@gmail.com>
Message-ID: <20140318162719.GY17250@pengutronix.de>

On Mon, Mar 17, 2014 at 01:37:02PM +0400, Antony Pavlov wrote:
> This driver is very handy for initial barebox porting.
> It was used for running barebox on DiGiC2-based camera
> and initial porting barebox to Loongson-1 and ar9331.
> 
> Signed-off-by: Antony Pavlov <antonynpavlov at gmail.com>
> Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
> Reported-by: Alexander Aring <alex.aring at gmail.com>
> Reported-by: Alexander Shiyan <shc_work at mail.ru>

Applied, thanks

Sascha

> ---
>  drivers/clocksource/Kconfig  | 22 +++++++++++++++++
>  drivers/clocksource/Makefile |  1 +
>  drivers/clocksource/dummy.c  | 56 ++++++++++++++++++++++++++++++++++++++++++++
>  3 files changed, 79 insertions(+)
>  create mode 100644 drivers/clocksource/dummy.c
> 
> diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
> index 4ef25ec..f53c933 100644
> --- a/drivers/clocksource/Kconfig
> +++ b/drivers/clocksource/Kconfig
> @@ -14,6 +14,28 @@ config CLOCKSOURCE_CLPS711X
>  	bool
>  	depends on ARCH_CLPS711X
>  
> +config CLOCKSOURCE_DUMMY
> +	bool "Enable dummy software-only clocksource"
> +	help
> +	  When porting barebox to a new SoC there might be a case
> +	  of broken or absent clocksource. This causes barebox serial
> +	  console to be non functional.
> +	  To solve the problem this software-only clocksource driver is used.
> +	      WARNING!!! This clocksource doesn't provide correct timing.
> +	  To adjust this clocksource please use CONFIG_CLOCKSOURCE_DUMMY_RATE.
> +	  The bigger rate valuest makes clocksource "faster".
> +	  It's possible to add this clocksource unconditionally.
> +	  This clocksource starts very early (pure_initcall) so
> +	  real clocksource will take over.
> +	  This can help if initialization order is wrong so that
> +	  the time functions are used before the real clocksource
> +	  was initialized.
> +
> +config CLOCKSOURCE_DUMMY_RATE
> +	int "  dummy clocksource rate"
> +	depends on CLOCKSOURCE_DUMMY
> +	default 1000
> +
>  config CLOCKSOURCE_MVEBU
>  	bool
>  	depends on ARCH_MVEBU
> diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
> index 25b7f46..834a15d 100644
> --- a/drivers/clocksource/Makefile
> +++ b/drivers/clocksource/Makefile
> @@ -2,6 +2,7 @@ obj-$(CONFIG_AMBA_SP804) += amba-sp804.o
>  obj-$(CONFIG_ARM_SMP_TWD) += arm_smp_twd.o
>  obj-$(CONFIG_CLOCKSOURCE_BCM2835) += bcm2835.o
>  obj-$(CONFIG_CLOCKSOURCE_CLPS711X) += clps711x.o
> +obj-$(CONFIG_CLOCKSOURCE_DUMMY)   += dummy.o
>  obj-$(CONFIG_CLOCKSOURCE_MVEBU)   += mvebu.o
>  obj-$(CONFIG_CLOCKSOURCE_NOMADIK) += nomadik.o
>  obj-$(CONFIG_CLOCKSOURCE_ORION)   += orion.o
> diff --git a/drivers/clocksource/dummy.c b/drivers/clocksource/dummy.c
> new file mode 100644
> index 0000000..154a8cd
> --- /dev/null
> +++ b/drivers/clocksource/dummy.c
> @@ -0,0 +1,56 @@
> +/*
> + * Copyright (C) 2013 Antony Pavlov <antonynpavlov at gmail.com>
> + *
> + * This file is part of barebox.
> + * See file CREDITS for list of people who contributed to this project.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2
> + * as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + */
> +
> +#include <common.h>
> +#include <init.h>
> +#include <clock.h>
> +
> +static uint64_t dummy_counter;
> +
> +static uint64_t dummy_cs_read(void)
> +{
> +	static int first;
> +
> +	if (!first) {
> +		pr_warn("Warning: Using dummy clocksource\n");
> +		first = 1;
> +	}
> +
> +	dummy_counter += CONFIG_CLOCKSOURCE_DUMMY_RATE;
> +
> +	return dummy_counter;
> +}
> +
> +static struct clocksource dummy_cs = {
> +	.read	= dummy_cs_read,
> +	.mask   = CLOCKSOURCE_MASK(32),
> +};
> +
> +static int clocksource_init(void)
> +{
> +	dummy_counter = 0;
> +
> +	clocks_calc_mult_shift(&dummy_cs.mult, &dummy_cs.shift,
> +		100000000, NSEC_PER_SEC, 10);
> +
> +	pr_debug("clocksource_init: mult=%08x, shift=%08x\n",
> +			dummy_cs.mult, dummy_cs.shift);
> +	init_clock(&dummy_cs);
> +
> +	return 0;
> +}
> +pure_initcall(clocksource_init);
> -- 
> 1.9.0
> 
> 

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From l.stach at pengutronix.de  Tue Mar 18 12:29:45 2014
From: l.stach at pengutronix.de (Lucas Stach)
Date: Tue, 18 Mar 2014 17:29:45 +0100
Subject: [PATCH] arm: imx53: qsb: set hostname from board file
Message-ID: <1395160185-32125-1-git-send-email-l.stach@pengutronix.de>

Otherwise it won't get set in a multiimage build.

Signed-off-by: Lucas Stach <l.stach at pengutronix.de>
---
 arch/arm/boards/freescale-mx53-qsb/board.c          | 2 ++
 arch/arm/boards/freescale-mx53-qsb/env/config-board | 1 -
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boards/freescale-mx53-qsb/board.c b/arch/arm/boards/freescale-mx53-qsb/board.c
index 74826e4a5e43..0553f1c82895 100644
--- a/arch/arm/boards/freescale-mx53-qsb/board.c
+++ b/arch/arm/boards/freescale-mx53-qsb/board.c
@@ -99,6 +99,7 @@ static int loco_late_init(void)
 		rev = readl(MX53_IIM_BASE_ADDR + 0x878);
 		set_board_rev(rev);
 		printf("MCIMX53-START-R board 1.0 rev %c\n", (rev == 1) ? 'A' : 'B' );
+		barebox_set_hostname("loco-r");
 		armlinux_set_revision(loco_system_rev);
 		/* Set VDDGP to 1.25V for 1GHz on SW1 */
 		mc13xxx_reg_read(mc34708, MC13892_REG_SW_0, &val);
@@ -146,6 +147,7 @@ static int loco_late_init(void)
 	} else {
 		/* so we have a DA9053 based board */
 		printf("MCIMX53-START board 1.0\n");
+		barebox_set_hostname("loco");
 		armlinux_set_revision(loco_system_rev);
 		return 0;
 	}
diff --git a/arch/arm/boards/freescale-mx53-qsb/env/config-board b/arch/arm/boards/freescale-mx53-qsb/env/config-board
index a6cf69ddbc7f..e8e8378f53f5 100644
--- a/arch/arm/boards/freescale-mx53-qsb/env/config-board
+++ b/arch/arm/boards/freescale-mx53-qsb/env/config-board
@@ -3,5 +3,4 @@
 # board defaults, do not change in running system. Change /env/config
 # instead
 
-global.hostname=loco
 global.linux.bootargs.base="console=ttymxc0,115200"
-- 
1.9.0



From s.hauer at pengutronix.de  Tue Mar 18 12:54:20 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Tue, 18 Mar 2014 17:54:20 +0100
Subject: [PATCH v2 06/10] ARM: dts: Add TI TMS320DM365 devicetree file
In-Reply-To: <1394977701-5889-7-git-send-email-antonynpavlov@gmail.com>
References: <1394977701-5889-1-git-send-email-antonynpavlov@gmail.com>
 <1394977701-5889-7-git-send-email-antonynpavlov@gmail.com>
Message-ID: <20140318165420.GZ17250@pengutronix.de>

On Sun, Mar 16, 2014 at 05:48:17PM +0400, Antony Pavlov wrote:
> Signed-off-by: Antony Pavlov <antonynpavlov at gmail.com>
> ---
>  arch/arm/dts/dm365.dtsi | 28 ++++++++++++++++++++++++++++
>  1 file changed, 28 insertions(+)
> 
> diff --git a/arch/arm/dts/dm365.dtsi b/arch/arm/dts/dm365.dtsi
> new file mode 100644
> index 0000000..ea69007
> --- /dev/null
> +++ b/arch/arm/dts/dm365.dtsi
> @@ -0,0 +1,28 @@
> +#include "skeleton.dtsi"
> +
> +/ {
> +	soc {
> +		compatible = "simple-bus";
> +		model = "TI TMS320DM365";
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		ranges = <0x0 0x01c00000 0x400000>;
> +
> +		serial0: serial at 1c20000 {
> +			compatible = "ns16550a";
> +			reg = <0x20000 0x400>;
> +			reg-shift = <2>;
> +			clock-frequency = <24000000>;
> +			status = "disabled";
> +		};
> +
> +		gpio: gpio at 1c67000 {
> +			compatible = "ti,dm6441-gpio";
> +			gpio-controller;
> +			reg = <0x67000 0x800>;
> +			#gpio-cells = <2>;
> +			ti,ngpio = <107>;
> +			status = "disabled";

The device should be enabled in the dtsi. Virtually every board wants to
use it.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From s.hauer at pengutronix.de  Tue Mar 18 12:56:11 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Tue, 18 Mar 2014 17:56:11 +0100
Subject: [PATCH v2 08/10] ARM: davinci: add virt2real board support
In-Reply-To: <1394977701-5889-9-git-send-email-antonynpavlov@gmail.com>
References: <1394977701-5889-1-git-send-email-antonynpavlov@gmail.com>
 <1394977701-5889-9-git-send-email-antonynpavlov@gmail.com>
Message-ID: <20140318165611.GA17250@pengutronix.de>

On Sun, Mar 16, 2014 at 05:48:19PM +0400, Antony Pavlov wrote:
> The virt2real microcontroller, or virturilka,
> is a miniature board for creation of WiFi
> or internet controllable smart devices.
> 
> See http://virt2real.com for details.
> +/ {
> +	model = "virt2real";
> +
> +	memory {
> +		reg = <0x82000000 0x01000000>;
> +	};
> +
> +	soc {
> +		serial0: serial at 1c20000 {
> +			status = "okay";
> +		};
> +
> +		gpio: gpio at 1c67000 {
> +			status = "okay";
> +		};
> +	};
> +
> +	leds {
> +		compatible = "gpio-leds";
> +
> +		green_led {
> +			label = "green led";
> +			gpios = <&gpio 73 0>;
> +		};

You should use labels without whitespaces. I'm not sure if all layers in
barebox and the kernel handle whitespaces correctly.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From renaud.barbier at ge.com  Wed Mar 19 07:25:27 2014
From: renaud.barbier at ge.com (Renaud Barbier)
Date: Wed, 19 Mar 2014 11:25:27 +0000
Subject: [PATCH] ppc: P2020RDB: add persistent configuration support
In-Reply-To: <1394556858-27282-1-git-send-email-renaud.barbier@ge.com>
References: <1394556858-27282-1-git-send-email-renaud.barbier@ge.com>
Message-ID: <53297EA7.7010605@ge.com>

Hello,
I noticed this single patch has not been applied yet while the large
P1022DS patch-set sent later has been.

Let me know whether there is any issue and I will fix it immediately?

Cheers,
Renaud

On 11/03/2014 16:54, Renaud Barbier wrote:
> Add an environment partition and support commands to have persistent
> boot configuration for Linux.
> 
> Signed-off-by: Renaud Barbier <renaud.barbier at ge.com>
> ---
>  arch/ppc/boards/freescale-p2020rdb/env/bin/init |  2 ++
>  arch/ppc/boards/freescale-p2020rdb/env/config   |  2 ++
>  arch/ppc/boards/freescale-p2020rdb/p2020rdb.c   |  9 +++++----
>  arch/ppc/configs/p2020rdb_defconfig             | 21 ++++++++++++++++++++-
>  4 files changed, 29 insertions(+), 5 deletions(-)
>  create mode 100644 arch/ppc/boards/freescale-p2020rdb/env/bin/init
>  create mode 100644 arch/ppc/boards/freescale-p2020rdb/env/config
> 



From antonynpavlov at gmail.com  Wed Mar 19 07:28:57 2014
From: antonynpavlov at gmail.com (Antony Pavlov)
Date: Wed, 19 Mar 2014 15:28:57 +0400
Subject: [PATCH] [FOR SQUASH] ARM: virt2real.dts: use labels without
 whitespaces
Message-ID: <1395228537-28677-1-git-send-email-antonynpavlov@gmail.com>

see comment in the maillist
  http://lists.infradead.org/pipermail/barebox/2014-March/018333.html

Signed-off-by: Antony Pavlov <antonynpavlov at gmail.com>
---
 arch/arm/dts/virt2real.dts | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/dts/virt2real.dts b/arch/arm/dts/virt2real.dts
index 0e2210a..09aec1f 100644
--- a/arch/arm/dts/virt2real.dts
+++ b/arch/arm/dts/virt2real.dts
@@ -23,12 +23,12 @@
 		compatible = "gpio-leds";
 
 		green_led {
-			label = "green led";
+			label = "green-led";
 			gpios = <&gpio 73 0>;
 		};
 
 		red_led {
-			label = "red led";
+			label = "red-led";
 			gpios = <&gpio 74 0>;
 		};
 	};
-- 
1.9.0



From antonynpavlov at gmail.com  Wed Mar 19 07:29:12 2014
From: antonynpavlov at gmail.com (Antony Pavlov)
Date: Wed, 19 Mar 2014 15:29:12 +0400
Subject: [PATCH] [FOR SQUASH] clocksource: dummy.c: remove Kconfig warning
Message-ID: <1395228552-28724-1-git-send-email-antonynpavlov@gmail.com>

This patch removes this warning during 'make *config':

  drivers/clocksource/Kconfig:36:warning: leading whitespace ignored

Signed-off-by: Antony Pavlov <antonynpavlov at gmail.com>
---
 drivers/clocksource/Kconfig | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index f53c933..43974f0 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -32,7 +32,8 @@ config CLOCKSOURCE_DUMMY
 	  was initialized.
 
 config CLOCKSOURCE_DUMMY_RATE
-	int "  dummy clocksource rate"
+	int
+	prompt "dummy clocksource rate"
 	depends on CLOCKSOURCE_DUMMY
 	default 1000
 
-- 
1.9.0



From p.zabel at pengutronix.de  Wed Mar 19 09:25:02 2014
From: p.zabel at pengutronix.de (Philipp Zabel)
Date: Wed, 19 Mar 2014 14:25:02 +0100
Subject: [PATCH] mtd: ubi: avoid NULL pointer dereference in ubi_get_device
Message-ID: <1395235502-27629-1-git-send-email-p.zabel@pengutronix.de>

If the ubidetach command is given a number that passes the range check
in ubi_detach_mtd_dev, but at which index the ubi_devices array contains
a NULL pointer, ubi_get_device tries to dereference this NULL pointer
to increment the ubi device reference count.

Signed-off-by: Philipp Zabel <p.zabel at pengutronix.de>
---
 drivers/mtd/ubi/build.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/mtd/ubi/build.c b/drivers/mtd/ubi/build.c
index da21f69..b908fcd 100644
--- a/drivers/mtd/ubi/build.c
+++ b/drivers/mtd/ubi/build.c
@@ -104,6 +104,8 @@ struct ubi_device *ubi_get_device(int ubi_num)
 	struct ubi_device *ubi;
 
 	ubi = ubi_devices[ubi_num];
+	if (!ubi)
+		return NULL;
 
 	ubi->ref_count++;
 
-- 
1.9.0



From s.hauer at pengutronix.de  Wed Mar 19 11:17:09 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Wed, 19 Mar 2014 16:17:09 +0100
Subject: [PATCH 1/2] usb: gadget: set composite to NULL when
 usb_gadget_register_driver fails
Message-ID: <1395242230-6947-1-git-send-email-s.hauer@pengutronix.de>

From: Lucas Stach <dev at lynxeye.de>

So that it can be tried later again.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 drivers/usb/gadget/composite.c | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/usb/gadget/composite.c b/drivers/usb/gadget/composite.c
index 11b6c18..71d0ecf 100644
--- a/drivers/usb/gadget/composite.c
+++ b/drivers/usb/gadget/composite.c
@@ -994,6 +994,8 @@ static struct usb_gadget_driver composite_driver = {
  */
 int usb_composite_register(struct usb_composite_driver *driver)
 {
+	int ret;
+
 	if (!driver || !driver->dev || !driver->bind || composite)
 		return -EINVAL;
 
@@ -1002,7 +1004,12 @@ int usb_composite_register(struct usb_composite_driver *driver)
 	composite_driver.function =  (char *) driver->name;
 	composite = driver;
 
-	return usb_gadget_register_driver(&composite_driver);
+	ret = usb_gadget_register_driver(&composite_driver);
+
+	if (ret)
+		composite = NULL;
+
+	return ret;
 }
 
 /**
-- 
1.9.0



From s.hauer at pengutronix.de  Wed Mar 19 11:17:10 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Wed, 19 Mar 2014 16:17:10 +0100
Subject: [PATCH 2/2] usb: gadget: propagate error code from
 usb_composite_register
In-Reply-To: <1395242230-6947-1-git-send-email-s.hauer@pengutronix.de>
References: <1395242230-6947-1-git-send-email-s.hauer@pengutronix.de>
Message-ID: <1395242230-6947-2-git-send-email-s.hauer@pengutronix.de>

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 drivers/usb/gadget/dfu.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/usb/gadget/dfu.c b/drivers/usb/gadget/dfu.c
index 76b5def..d0f2155 100644
--- a/drivers/usb/gadget/dfu.c
+++ b/drivers/usb/gadget/dfu.c
@@ -703,7 +703,9 @@ int usb_dfu_register(struct usb_dfu_pdata *pdata)
 	strings_dev[STRING_MANUFACTURER_IDX].s = pdata->manufacturer;
 	strings_dev[STRING_PRODUCT_IDX].s = pdata->productname;
 
-	usb_composite_register(&dfu_driver);
+	ret = usb_composite_register(&dfu_driver);
+	if (ret)
+		return ret;
 
 	while (1) {
 		ret = usb_gadget_poll();
-- 
1.9.0



From s.hauer at pengutronix.de  Wed Mar 19 11:20:11 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Wed, 19 Mar 2014 16:20:11 +0100
Subject: [PATCH 2/2] boot command: only create boot entries from scripts
In-Reply-To: <1395242411-10247-1-git-send-email-s.hauer@pengutronix.de>
References: <1395242411-10247-1-git-send-email-s.hauer@pengutronix.de>
Message-ID: <1395242411-10247-2-git-send-email-s.hauer@pengutronix.de>

When given a directory ignore all files that are not shell scripts.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 commands/boot.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/commands/boot.c b/commands/boot.c
index 9c7aa21..a54d0d5 100644
--- a/commands/boot.c
+++ b/commands/boot.c
@@ -106,6 +106,11 @@ static void bootsource_action(struct menu *m, struct menu_entry *me)
 static int bootscript_create_entry(struct blspec *blspec, const char *name)
 {
 	struct blspec_entry *be;
+	enum filetype type;
+
+	type = file_name_detect_type(name);
+	if (type != filetype_sh)
+		return -EINVAL;
 
 	be = blspec_entry_alloc(blspec);
 	be->me.type = MENU_ENTRY_NORMAL;
-- 
1.9.0



From s.hauer at pengutronix.de  Wed Mar 19 11:20:10 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Wed, 19 Mar 2014 16:20:10 +0100
Subject: [PATCH 1/2] boot command: honour global.boot.default also for -l and
 -m
Message-ID: <1395242411-10247-1-git-send-email-s.hauer@pengutronix.de>

The boot command is expected to work on bootsources from the commandline
if given, on global.boot.default otherwise. Fix this behaviour for the
-m and -l options also.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 commands/boot.c | 79 +++++++++++++++++++++++++++++++++++----------------------
 1 file changed, 48 insertions(+), 31 deletions(-)

diff --git a/commands/boot.c b/commands/boot.c
index bb8d07f..9c7aa21 100644
--- a/commands/boot.c
+++ b/commands/boot.c
@@ -333,9 +333,11 @@ static int boot(const char *name)
 
 static int do_boot(int argc, char *argv[])
 {
-	const char *sources = NULL;
-	char *source, *freep;
+	char *freep = NULL;
 	int opt, ret = 0, do_list = 0, do_menu = 0;
+	char **sources;
+	int num_sources;
+	int i;
 
 	verbose = 0;
 	dryrun = 0;
@@ -361,47 +363,62 @@ static int do_boot(int argc, char *argv[])
 		}
 	}
 
-	if (do_list) {
-		bootsources_list(&argv[optind], argc - optind);
-		return 0;
-	}
+	if (optind < argc) {
+		num_sources = argc - optind;
+		sources = xmemdup(&argv[optind], sizeof(char *) * num_sources);
+	} else {
+		const char *def;
+		char *sep;
 
-	if (do_menu) {
-		bootsources_menu(&argv[optind], argc - optind);
-		return 0;
-	}
+		def = getenv("global.boot.default");
+		if (!def)
+			return 0;
 
-	if (optind < argc) {
-		while (optind < argc) {
-			source = argv[optind];
-			optind++;
-			ret = boot(source);
-			if (!ret)
+		sep = freep = xstrdup(def);
+
+		num_sources = 0;
+
+		while (1) {
+			num_sources++;
+
+			sep = strchr(sep, ' ');
+			if (!sep)
 				break;
+			sep++;
+		}
+
+		sources = xmalloc(sizeof(char *) * num_sources);
+
+		sep = freep;
+
+		for (i = 0; i < num_sources; i++) {
+			sources[i] = sep;
+			sep = strchr(sep, ' ');
+			if (sep)
+				*sep = 0;
+			sep++;
 		}
-		return ret;
 	}
 
-	sources = getenv("global.boot.default");
-	if (!sources)
-		return 0;
+	if (do_list) {
+		bootsources_list(sources, num_sources);
+		goto out;
+	}
 
-	freep = source = xstrdup(sources);
+	if (do_menu) {
+		bootsources_menu(sources, num_sources);
+		goto out;
+	}
 
-	while (1) {
-		char *sep = strchr(source, ' ');
-		if (sep)
-			*sep = 0;
-		ret = boot(source);
+	for (i = 0; i < num_sources; i++) {
+		ret = boot(sources[i]);
 		if (!ret)
 			break;
-
-		if (sep)
-			source = sep + 1;
-		else
-			break;
+		goto out;
 	}
 
+out:
+	free(sources);
 	free(freep);
 
 	return ret;
-- 
1.9.0



From s.hauer at pengutronix.de  Wed Mar 19 11:20:45 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Wed, 19 Mar 2014 16:20:45 +0100
Subject: [PATCH] ARM i.MX6Q: Fix IOMUXC GPR1 defines for ENET_CLK_SEL and
 IPU1/2_MUX
Message-ID: <1395242445-15939-1-git-send-email-s.hauer@pengutronix.de>

From: Philipp Zabel <p.zabel at pengutronix.de>

Signed-off-by: Philipp Zabel <p.zabel at pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 include/mfd/imx6q-iomuxc-gpr.h | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/include/mfd/imx6q-iomuxc-gpr.h b/include/mfd/imx6q-iomuxc-gpr.h
index db43d59..3ccc254 100644
--- a/include/mfd/imx6q-iomuxc-gpr.h
+++ b/include/mfd/imx6q-iomuxc-gpr.h
@@ -103,15 +103,15 @@
 #define IMX6Q_GPR1_EXC_MON_MASK			BIT(22)
 #define IMX6Q_GPR1_EXC_MON_OKAY			0x0
 #define IMX6Q_GPR1_EXC_MON_SLVE			BIT(22)
-#define IMX6Q_GPR1_MIPI_IPU2_SEL_MASK		BIT(21)
-#define IMX6Q_GPR1_MIPI_IPU2_SEL_GASKET		0x0
-#define IMX6Q_GPR1_MIPI_IPU2_SEL_IOMUX		BIT(21)
-#define IMX6Q_GPR1_MIPI_IPU1_MUX_MASK		BIT(20)
-#define IMX6Q_GPR1_MIPI_IPU1_MUX_GASKET		0x0
-#define IMX6Q_GPR1_MIPI_IPU1_MUX_IOMUX		BIT(20)
-#define IMX6Q_GPR1_MIPI_IPU2_MUX_MASK		BIT(19)
+#define IMX6Q_GPR1_ENET_CLK_SEL_MASK		BIT(21)
+#define IMX6Q_GPR1_ENET_CLK_SEL_PAD		0
+#define IMX6Q_GPR1_ENET_CLK_SEL_ANATOP		BIT(21)
+#define IMX6Q_GPR1_MIPI_IPU2_MUX_MASK		BIT(20)
 #define IMX6Q_GPR1_MIPI_IPU2_MUX_GASKET		0x0
-#define IMX6Q_GPR1_MIPI_IPU2_MUX_IOMUX		BIT(19)
+#define IMX6Q_GPR1_MIPI_IPU2_MUX_IOMUX		BIT(20)
+#define IMX6Q_GPR1_MIPI_IPU1_MUX_MASK		BIT(19)
+#define IMX6Q_GPR1_MIPI_IPU1_MUX_GASKET		0x0
+#define IMX6Q_GPR1_MIPI_IPU1_MUX_IOMUX		BIT(19)
 #define IMX6Q_GPR1_PCIE_TEST_PD			BIT(18)
 #define IMX6Q_GPR1_IPU_VPU_MUX_MASK		BIT(17)
 #define IMX6Q_GPR1_IPU_VPU_MUX_IPU1		0x0
-- 
1.9.0



From s.hauer at pengutronix.de  Wed Mar 19 16:45:09 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Wed, 19 Mar 2014 21:45:09 +0100
Subject: [PATCH] [FOR SQUASH] ARM: virt2real.dts: use labels without
 whitespaces
In-Reply-To: <1395228537-28677-1-git-send-email-antonynpavlov@gmail.com>
References: <1395228537-28677-1-git-send-email-antonynpavlov@gmail.com>
Message-ID: <20140319204509.GC17250@pengutronix.de>

On Wed, Mar 19, 2014 at 03:28:57PM +0400, Antony Pavlov wrote:
> see comment in the maillist
>   http://lists.infradead.org/pipermail/barebox/2014-March/018333.html
> 
> Signed-off-by: Antony Pavlov <antonynpavlov at gmail.com>

Squashed into the commit, thanks

Sascha

> ---
>  arch/arm/dts/virt2real.dts | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/dts/virt2real.dts b/arch/arm/dts/virt2real.dts
> index 0e2210a..09aec1f 100644
> --- a/arch/arm/dts/virt2real.dts
> +++ b/arch/arm/dts/virt2real.dts
> @@ -23,12 +23,12 @@
>  		compatible = "gpio-leds";
>  
>  		green_led {
> -			label = "green led";
> +			label = "green-led";
>  			gpios = <&gpio 73 0>;
>  		};
>  
>  		red_led {
> -			label = "red led";
> +			label = "red-led";
>  			gpios = <&gpio 74 0>;
>  		};
>  	};
> -- 
> 1.9.0
> 
> 

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From s.hauer at pengutronix.de  Wed Mar 19 16:45:29 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Wed, 19 Mar 2014 21:45:29 +0100
Subject: [PATCH] [FOR SQUASH] clocksource: dummy.c: remove Kconfig warning
In-Reply-To: <1395228552-28724-1-git-send-email-antonynpavlov@gmail.com>
References: <1395228552-28724-1-git-send-email-antonynpavlov@gmail.com>
Message-ID: <20140319204529.GD17250@pengutronix.de>

On Wed, Mar 19, 2014 at 03:29:12PM +0400, Antony Pavlov wrote:
> This patch removes this warning during 'make *config':
> 
>   drivers/clocksource/Kconfig:36:warning: leading whitespace ignored
> 
> Signed-off-by: Antony Pavlov <antonynpavlov at gmail.com>

Also squashed into the original commit.

Sascha

> ---
>  drivers/clocksource/Kconfig | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
> index f53c933..43974f0 100644
> --- a/drivers/clocksource/Kconfig
> +++ b/drivers/clocksource/Kconfig
> @@ -32,7 +32,8 @@ config CLOCKSOURCE_DUMMY
>  	  was initialized.
>  
>  config CLOCKSOURCE_DUMMY_RATE
> -	int "  dummy clocksource rate"
> +	int
> +	prompt "dummy clocksource rate"
>  	depends on CLOCKSOURCE_DUMMY
>  	default 1000
>  
> -- 
> 1.9.0
> 
> 

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From antonynpavlov at gmail.com  Thu Mar 20 03:39:45 2014
From: antonynpavlov at gmail.com (Antony Pavlov)
Date: Thu, 20 Mar 2014 11:39:45 +0400
Subject: [PATCH] [FOR SQUASH] clocksource: dummy.c: remove Kconfig warning
In-Reply-To: <20140319204529.GD17250@pengutronix.de>
References: <1395228552-28724-1-git-send-email-antonynpavlov@gmail.com>
 <20140319204529.GD17250@pengutronix.de>
Message-ID: <20140320113945.b5d5addb8bed349118566364@gmail.com>

On Wed, 19 Mar 2014 21:45:29 +0100
Sascha Hauer <s.hauer at pengutronix.de> wrote:

> On Wed, Mar 19, 2014 at 03:29:12PM +0400, Antony Pavlov wrote:
> > This patch removes this warning during 'make *config':
> > 
> >   drivers/clocksource/Kconfig:36:warning: leading whitespace ignored
> > 
> > Signed-off-by: Antony Pavlov <antonynpavlov at gmail.com>
> 
> Also squashed into the original commit.

Excuse me for my Treppenwitz!

Could you please change

+	int
+	prompt "dummy clocksource rate"

to more usual

+	int "dummy clocksource rate"
?

I'm so sorry!

]> 
> > ---
> >  drivers/clocksource/Kconfig | 3 ++-
> >  1 file changed, 2 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
> > index f53c933..43974f0 100644
> > --- a/drivers/clocksource/Kconfig
> > +++ b/drivers/clocksource/Kconfig
> > @@ -32,7 +32,8 @@ config CLOCKSOURCE_DUMMY
> >  	  was initialized.
> >  
> >  config CLOCKSOURCE_DUMMY_RATE
> > -	int "  dummy clocksource rate"
> > +	int
> > +	prompt "dummy clocksource rate"
> >  	depends on CLOCKSOURCE_DUMMY
> >  	default 1000
> >  
> > -- 
> > 1.9.0
> > 
> > 
> 
> -- 
> Pengutronix e.K.                           |                             |
> Industrial Linux Solutions                 | http://www.pengutronix.de/  |
> Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
> Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

--?
Best regards,
? Antony Pavlov


From d.lavnikevich at sam-solutions.net  Thu Mar 20 06:28:59 2014
From: d.lavnikevich at sam-solutions.net (Dmitry Lavnikevich)
Date: Thu, 20 Mar 2014 13:28:59 +0300
Subject: [PATCH] i.MX6: bbu: Barebox update support for NAND.
In-Reply-To: <20140313065458.GQ17250@pengutronix.de>
References: <1394610851-721-1-git-send-email-d.lavnikevich@sam-solutions.com>
 <20140313065458.GQ17250@pengutronix.de>
Message-ID: <532AC2EB.2040302@sam-solutions.net>

Hello Sascha,

have you tried my patch on your board yet?
I will correct mentioned points and resent it to mail list later.
I'm also interested to see your implementation of this functionality.
Particulary regarding the

> This doesn't seem to take bad blocks into account. What happens when the
> first firmware image gets bigger due to bad blocks? It will be
> overwritten by the 2nd image.

part.

Best regards,
Lavnikevich Dmitry

On 03/13/14 09:54, Sascha Hauer wrote:
> Hi Dmitry,
>
> On Wed, Mar 12, 2014 at 10:54:11AM +0300, Dmitry Lavnikevich wrote:
>> This patch implements updating barebox on i.MX6 NAND. In userspace
>> similar task is performed by freescale kobs-ng utility.
>> To use this bbu profile nand handler should be registered in board
>> code with 'imx6_bbu_internal_nand_register_handler' function.
> I have the very same patch in the queue, it seems we have duplicated
> some work. As this version has some shortcomings I'll post my version as
> an alternative implementation. Also I'll try your version on a board I
> have here on which my version doesn't work (which is the reason I
> haven't posted my patch yet)
>
>> +static int erase_part(struct mtd_info *mtd)
>> +{
>> +	loff_t ofs;
>> +	int ret = 0;
>> +	struct erase_info erase_opts = {
>> +		.mtd = mtd,
>> +		.addr = 0,
>> +		.len = mtd->erasesize,
>> +		.callback = NULL,
>> +	};
>> +
>> +	for (ofs = 0; ofs < mtd->size; ofs += mtd->erasesize) {
>> +		ret = mtd_block_isbad(mtd, ofs);
>> +		if (ret > 0) {
>> +			printf("Warning: bad block at 0x%08llx. Skipping\n",
>> +				   ofs);
>> +			continue;
> This is not worth issueing a warning. Bad blocks just happen.
>
>> +		} else if (ret < 0) {
>> +			printf("Error: checking bad block at 0x%llx failed\n",
>> +				   ofs);
>> +			ret = 1;
>> +			goto err;
>> +		}
>> +
>> +		erase_opts.addr = ofs;
>> +		ret = mtd->erase(mtd, &erase_opts);
> You should use mtd_erase and friends rather than dereferencing struct
> mtd_info.
>
>> +	buf = malloc(mtd->erasesize);
>> +	if (!buf) {
>> +		ret = -ENOMEM;
>> +		goto err_out;
>> +	}
>> +
>> +	image = read_imagefile(mtd, data->imagefile, &fw_size);
>> +	if (!image) {
>> +		ret = -errno;
>> +		goto err_out1;
>> +	}
> No Need to read the image, data->image contains a pointer to it.
>
>> +
>> +	search_area_size_in_bytes =
>> +		(1 << SEARCH_EXPONENT) * PAGES_PER_STRIDE * mtd->writesize;
>> +	max_boot_stream_in_bytes =
>> +		(mtd->size - search_area_size_in_bytes * 2) / 2;
>> +
>> +	fw1_offset = 2 * search_area_size_in_bytes;
>> +	fw2_offset = fw1_offset + max_boot_stream_in_bytes;
>> +
>> +	fcb = create_fcb(mtd, buf, fw1_offset, fw_size, fw2_offset);
>> +	if (IS_ERR(fcb)) {
>> +		printf("Failed to initialize FCB: %ld\n", PTR_ERR(fcb));
>> +		ret = PTR_ERR(fcb);
>> +		goto err_out2;
>> +	}
>> +	encode_hamming_13_8(fcb, (void *)fcb + 512, 512);
>> +
>> +	dbbt = create_dbbt(mtd, &bbtn);
>> +	if (!dbbt)
>> +		goto err_out2;
>> +
>> +	erase_part(mtd);
> Error checking?
>
>> +
>> +	block = bcb_cdev->offset;
>> +	for (fcb_written = 0; fcb_written < 4; fcb_written++) {
>> +
>> +		if (nand_isbad_bbt(mtd, block, false))
>> +			continue;
>> +
>> +		ret = write_fcb(mtd, buf, block);
>> +		if (ret) {
>> +			printf("Failed to write FCB to block %u\n", block);
>> +			goto err_out2;
>> +		}
>> +		block += mtd->erasesize;
>> +	}
>> +	ret = fcb_written ? 0 : -ENOSPC;
>> +	if (ret)
>> +		goto err_out2;
>> +
>> +	stride_size_in_bytes = PAGES_PER_STRIDE * mtd->writesize;
>> +	block = SEARCH_AREA_SIZE_IN_PAGES * mtd->writesize;
>> +	i = 0;
>> +	while (i < SEARCH_AREA_SIZE_IN_STRIDES) {
>> +		ret = write_dbbt(mtd, dbbt, buf, block, sizeof(*dbbt));
>> +		if (ret)
>> +			goto err_out2;
>> +
>> +		block += stride_size_in_bytes;
>> +		i++;
>> +	}
>> +
>> +	block = SEARCH_AREA_SIZE_IN_PAGES * mtd->writesize + 4 * mtd->writesize;
>> +	i = 0;
>> +	while (i < SEARCH_AREA_SIZE_IN_STRIDES) {
>> +		ret = write_bbtn(mtd, bbtn, buf, block, sizeof(*bbtn));
>> +		if (ret)
>> +			goto err_out2;
>> +
>> +		block += stride_size_in_bytes;
>> +		i++;
>> +	}
>> +
>> +	ret = write_image(mtd, image, fw1_offset, fw_size);
>> +	if (ret)
>> +		goto err_out2;
>> +	ret = write_image(mtd, image, fw2_offset, fw_size);
>> +	if (ret)
>> +		goto err_out2;
> This doesn't seem to take bad blocks into account. What happens when the
> first firmware image gets bigger due to bad blocks? It will be
> overwritten by the 2nd image.
>
> Sascha
>



From s.hauer at pengutronix.de  Fri Mar 21 04:23:35 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 21 Mar 2014 09:23:35 +0100
Subject: [PATCH] blspec: Check if an entry is compatible with the current
 machine
Message-ID: <1395390215-4219-1-git-send-email-s.hauer@pengutronix.de>

When a bootspec entry has the 'devicetree' property specified, check
if the tree is compatible with the currently running machine, otherwise
ignore the entry. This makes it possible to have entries for multiple
machines on an SD card and pick a suitable one.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 common/blspec.c | 81 +++++++++++++++++++++++++++++++++++++++++++++++++++++++--
 1 file changed, 79 insertions(+), 2 deletions(-)

diff --git a/common/blspec.c b/common/blspec.c
index 9b4b096..f165b77 100644
--- a/common/blspec.c
+++ b/common/blspec.c
@@ -235,6 +235,78 @@ out:
 }
 
 /*
+ * entry_is_of_compatible - check if a bootspec entry is compatible with
+ *                          the current machine.
+ *
+ * returns true is the entry is compatible, false otherwise
+ */
+static bool entry_is_of_compatible(struct blspec_entry *entry)
+{
+	const char *devicetree;
+	const char *abspath;
+	size_t size;
+	void *fdt = NULL;
+	int ret;
+	struct device_node *root = NULL, *barebox_root;
+	const char *compat;
+	char *filename;
+
+	/* If we don't have a root node every entry is compatible */
+	barebox_root = of_get_root_node();
+	if (!barebox_root)
+		return true;
+
+	ret = of_property_read_string(barebox_root, "compatible", &compat);
+	if (ret)
+		return false;
+
+	if (entry->rootpath)
+		abspath = entry->rootpath;
+	else
+		abspath = "";
+
+	/* If the entry doesn't specifiy a devicetree we are compatible */
+	devicetree = blspec_entry_var_get(entry, "devicetree");
+	if (!devicetree)
+		return true;
+
+	if (!strcmp(devicetree, "none"))
+		return true;
+
+	filename = asprintf("%s/%s", abspath, devicetree);
+
+	fdt = read_file(filename, &size);
+	if (!fdt) {
+		ret = false;
+		goto out;
+	}
+
+	root = of_unflatten_dtb(NULL, fdt);
+	if (IS_ERR(root)) {
+		ret = PTR_ERR(root);
+		goto out;
+	}
+
+	if (of_device_is_compatible(root, compat)) {
+		ret = true;
+		goto out;
+	}
+
+	pr_info("ignoring entry with incompatible devicetree \"%s\"\n",
+			(char *)of_get_property(root, "compatible", &size));
+
+	ret = false;
+
+out:
+	if (root)
+		of_delete_node(root);
+	free(filename);
+	free(fdt);
+
+	return ret;
+}
+
+/*
  * blspec_scan_directory - scan over a directory
  *
  * Given a root path collects all blspec entries found under /blspec/entries/.
@@ -313,12 +385,17 @@ int blspec_scan_directory(struct blspec *blspec, const char *root)
 			continue;
 		}
 
-		found++;
-
 		entry->rootpath = xstrdup(root);
 		entry->configpath = configname;
 		entry->cdev = get_cdev_by_mountpath(root);
 
+		if (!entry_is_of_compatible(entry)) {
+			blspec_entry_free(entry);
+			continue;
+		}
+
+		found++;
+
 		name = asprintf("%s/%s", dirname, d->d_name);
 		if (entry_default && !strcmp(name, entry_default))
 			entry->boot_default = true;
-- 
1.9.0



From s.hauer at pengutronix.de  Sat Mar 22 03:06:30 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Sat, 22 Mar 2014 08:06:30 +0100
Subject: [PATCH] i.MX6: bbu: Barebox update support for NAND.
In-Reply-To: <532AC2EB.2040302@sam-solutions.net>
References: <1394610851-721-1-git-send-email-d.lavnikevich@sam-solutions.com>
 <20140313065458.GQ17250@pengutronix.de>
 <532AC2EB.2040302@sam-solutions.net>
Message-ID: <20140322070630.GG17250@pengutronix.de>

Hi Dmitry,

On Thu, Mar 20, 2014 at 01:28:59PM +0300, Dmitry Lavnikevich wrote:
> Hello Sascha,
> 
> have you tried my patch on your board yet?
> I will correct mentioned points and resent it to mail list later.
> I'm also interested to see your implementation of this functionality.
> Particulary regarding the
> 
> >This doesn't seem to take bad blocks into account. What happens when the
> >first firmware image gets bigger due to bad blocks? It will be
> >overwritten by the 2nd image.
> 
> part.

We still didn't manage to make that board boot. Here's my version of the
patch in the meantime.

Sascha

--------------------------------8<-----------------------------
>From 86d47e0f5664f4d5115dcfe74fb1e124decf01cd Mon Sep 17 00:00:00 2001
From: Sascha Hauer <s.hauer at pengutronix.de>
Date: Thu, 6 Mar 2014 10:03:33 +0100
Subject: [PATCH] ARM: i.MX6: Add Nand boot bbu handler

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/mach-imx/Makefile           |   2 +-
 arch/arm/mach-imx/imx6-bbu-nand.c    | 489 +++++++++++++++++++++++++++++++++++
 arch/arm/mach-imx/include/mach/bbu.h |   6 +
 3 files changed, 496 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/mach-imx/imx6-bbu-nand.c

diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index b3f00f9..e7997fb 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -18,6 +18,6 @@ lwl-$(CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND) += external-nand-boot.o
 obj-$(CONFIG_COMMON_CLK) += clk-pllv1.o clk-pllv2.o clk-pllv3.o clk-pfd.o
 obj-y += devices.o imx.o esdctl.o
 obj-y += boot.o
-obj-$(CONFIG_BAREBOX_UPDATE) += imx-bbu-internal.o
+obj-$(CONFIG_BAREBOX_UPDATE) += imx-bbu-internal.o imx6-bbu-nand.o
 obj-$(CONFIG_BAREBOX_UPDATE_IMX_EXTERNAL_NAND) += imx-bbu-external-nand.o
 pbl-y += esdctl.o
diff --git a/arch/arm/mach-imx/imx6-bbu-nand.c b/arch/arm/mach-imx/imx6-bbu-nand.c
new file mode 100644
index 0000000..f6d16e7
--- /dev/null
+++ b/arch/arm/mach-imx/imx6-bbu-nand.c
@@ -0,0 +1,489 @@
+/*
+ * Copyright (C) 2014 Sascha Hauer, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation.
+ *
+ */
+
+#define pr_fmt(fmt) "imx6-bbu-nand: " fmt
+
+#include <filetype.h>
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <fcntl.h>
+#include <ioctl.h>
+#include <sizes.h>
+#include <bbu.h>
+#include <fs.h>
+#include <mach/bbu.h>
+#include <linux/mtd/mtd-abi.h>
+#include <linux/mtd/mtd.h>
+#include <linux/stat.h>
+
+struct dbbt_block {
+	uint32_t Checksum;
+	uint32_t FingerPrint;
+	uint32_t Version;
+	uint32_t reserved;
+	uint32_t DBBTNumOfPages;
+};
+
+struct fcb_block {
+	uint32_t Checksum;		/* First fingerprint in first byte */
+	uint32_t FingerPrint;		/* 2nd fingerprint at byte 4 */
+	uint32_t Version;		/* 3rd fingerprint at byte 8 */
+	uint8_t DataSetup;
+	uint8_t DataHold;
+	uint8_t AddressSetup;
+	uint8_t DSAMPLE_TIME;
+	/* These are for application use only and not for ROM. */
+	uint8_t NandTimingState;
+	uint8_t REA;
+	uint8_t RLOH;
+	uint8_t RHOH;
+	uint32_t PageDataSize;		/* 2048 for 2K pages, 4096 for 4K pages */
+	uint32_t TotalPageSize;		/* 2112 for 2K pages, 4314 for 4K pages */
+	uint32_t SectorsPerBlock;	/* Number of 2K sections per block */
+	uint32_t NumberOfNANDs;		/* Total Number of NANDs - not used by ROM */
+	uint32_t TotalInternalDie;	/* Number of separate chips in this NAND */
+	uint32_t CellType;		/* MLC or SLC */
+	uint32_t EccBlockNEccType;	/* Type of ECC, can be one of BCH-0-20 */
+	uint32_t EccBlock0Size;		/* Number of bytes for Block0 - BCH */
+	uint32_t EccBlockNSize;		/* Block size in bytes for all blocks other than Block0 - BCH */
+	uint32_t EccBlock0EccType;	/* Ecc level for Block 0 - BCH */
+	uint32_t MetadataBytes;		/* Metadata size - BCH */
+	uint32_t NumEccBlocksPerPage;	/* Number of blocks per page for ROM use - BCH */
+	uint32_t EccBlockNEccLevelSDK;	/* Type of ECC, can be one of BCH-0-20 */
+	uint32_t EccBlock0SizeSDK;	/* Number of bytes for Block0 - BCH */
+	uint32_t EccBlockNSizeSDK;	/* Block size in bytes for all blocks other than Block0 - BCH */
+	uint32_t EccBlock0EccLevelSDK;	/* Ecc level for Block 0 - BCH */
+	uint32_t NumEccBlocksPerPageSDK;/* Number of blocks per page for SDK use - BCH */
+	uint32_t MetadataBytesSDK;	/* Metadata size - BCH */
+	uint32_t EraseThreshold;	/* To set into BCH_MODE register */
+	uint32_t BootPatch;		/* 0 for normal boot and 1 to load patch starting next to FCB */
+	uint32_t PatchSectors;		/* Size of patch in sectors */
+	uint32_t Firmware1_startingPage;/* Firmware image starts on this sector */
+	uint32_t Firmware2_startingPage;/* Secondary FW Image starting Sector */
+	uint32_t PagesInFirmware1;	/* Number of sectors in firmware image */
+	uint32_t PagesInFirmware2;	/* Number of sector in secondary FW image */
+	uint32_t DBBTSearchAreaStartAddress; /* Page address where dbbt search area begins */
+	uint32_t BadBlockMarkerByte;	/* Byte in page data that have manufacturer marked bad block marker, */
+					/* this will be swapped with metadata[0] to complete page data. */
+	uint32_t BadBlockMarkerStartBit;/* For BCH ECC sizes other than 8 and 16 the bad block marker does not */
+					/* start at 0th bit of BadBlockMarkerByte. This field is used to get to */
+					/* the start bit of bad block marker byte with in BadBlockMarkerByte */
+	uint32_t BBMarkerPhysicalOffset;/* FCB value that gives byte offset for bad block marker on physical NAND page */
+	uint32_t BCHType;
+
+	uint32_t TMTiming2_ReadLatency;
+	uint32_t TMTiming2_PreambleDelay;
+	uint32_t TMTiming2_CEDelay;
+	uint32_t TMTiming2_PostambleDelay;
+	uint32_t TMTiming2_CmdAddPause;
+	uint32_t TMTiming2_DataPause;
+	uint32_t TMSpeed;
+	uint32_t TMTiming1_BusyTimeout;
+
+	uint32_t DISBBM;	/* the flag to enable (1)/disable(0) bi swap */
+	uint32_t BBMarkerPhysicalOffsetInSpareData; /* The swap position of main area in spare area */
+};
+
+#define BF_VAL(v, bf)		(((v) & bf##_MASK) >> bf##_OFFSET)
+#define GETBIT(v,n)	(((v) >> (n)) & 0x1)
+
+static uint8_t calculate_parity_13_8(uint8_t d)
+{
+	uint8_t p = 0;
+
+	p |= (GETBIT(d, 6) ^ GETBIT(d, 5) ^ GETBIT(d, 3) ^ GETBIT(d, 2))		 << 0;
+	p |= (GETBIT(d, 7) ^ GETBIT(d, 5) ^ GETBIT(d, 4) ^ GETBIT(d, 2) ^ GETBIT(d, 1)) << 1;
+	p |= (GETBIT(d, 7) ^ GETBIT(d, 6) ^ GETBIT(d, 5) ^ GETBIT(d, 1) ^ GETBIT(d, 0)) << 2;
+	p |= (GETBIT(d, 7) ^ GETBIT(d, 4) ^ GETBIT(d, 3) ^ GETBIT(d, 0))		 << 3;
+	p |= (GETBIT(d, 6) ^ GETBIT(d, 4) ^ GETBIT(d, 3) ^ GETBIT(d, 2) ^ GETBIT(d, 1) ^ GETBIT(d, 0)) << 4;
+	return p;
+}
+
+static void encode_hamming_13_8(void *_src, void *_ecc, size_t size)
+{
+	int i;
+	uint8_t *src = _src;
+	uint8_t *ecc = _ecc;
+
+	for (i = 0; i < size; i++)
+		ecc[i] = calculate_parity_13_8(src[i]);
+}
+
+static uint32_t calc_chksum(void *buf, size_t size)
+{
+	u32 chksum = 0;
+	u8 *bp = buf;
+	size_t i;
+
+	for (i = 0; i < size; i++)
+		chksum += bp[i];
+
+	return ~chksum;
+}
+
+static __maybe_unused void dump_fcb(void *buf)
+{
+	struct fcb_block *fcb = buf;
+
+	pr_debug("Checksum:                   0x%08x\n", fcb->Checksum);
+	pr_debug("FingerPrint:                0x%08x\n", fcb->FingerPrint);
+	pr_debug("Version:                    0x%08x\n", fcb->Version);
+	pr_debug("DataSetup:                  0x%02x\n", fcb->DataSetup);
+	pr_debug("DataHold:                   0x%02x\n", fcb->DataHold);
+	pr_debug("AddressSetup:               0x%02x\n", fcb->AddressSetup);
+	pr_debug("DSAMPLE_TIME:               0x%02x\n", fcb->DSAMPLE_TIME);
+	pr_debug("NandTimingState:            0x%02x\n", fcb->NandTimingState);
+	pr_debug("REA:                        0x%02x\n", fcb->REA);
+	pr_debug("RLOH:                       0x%02x\n", fcb->RLOH);
+	pr_debug("RHOH:                       0x%02x\n", fcb->RHOH);
+	pr_debug("PageDataSize:               0x%08x\n", fcb->PageDataSize);
+	pr_debug("TotalPageSize:              0x%08x\n", fcb->TotalPageSize);
+	pr_debug("SectorsPerBlock:            0x%08x\n", fcb->SectorsPerBlock);
+	pr_debug("NumberOfNANDs:              0x%08x\n", fcb->NumberOfNANDs);
+	pr_debug("TotalInternalDie:           0x%08x\n", fcb->TotalInternalDie);
+	pr_debug("CellType:                   0x%08x\n", fcb->CellType);
+	pr_debug("EccBlockNEccType:           0x%08x\n", fcb->EccBlockNEccType);
+	pr_debug("EccBlock0Size:              0x%08x\n", fcb->EccBlock0Size);
+	pr_debug("EccBlockNSize:              0x%08x\n", fcb->EccBlockNSize);
+	pr_debug("EccBlock0EccType:           0x%08x\n", fcb->EccBlock0EccType);
+	pr_debug("MetadataBytes:              0x%08x\n", fcb->MetadataBytes);
+	pr_debug("NumEccBlocksPerPage:        0x%08x\n", fcb->NumEccBlocksPerPage);
+	pr_debug("EccBlockNEccLevelSDK:       0x%08x\n", fcb->EccBlockNEccLevelSDK);
+	pr_debug("EccBlock0SizeSDK:           0x%08x\n", fcb->EccBlock0SizeSDK);
+	pr_debug("EccBlockNSizeSDK:           0x%08x\n", fcb->EccBlockNSizeSDK);
+	pr_debug("EccBlock0EccLevelSDK:       0x%08x\n", fcb->EccBlock0EccLevelSDK);
+	pr_debug("NumEccBlocksPerPageSDK:     0x%08x\n", fcb->NumEccBlocksPerPageSDK);
+	pr_debug("MetadataBytesSDK:           0x%08x\n", fcb->MetadataBytesSDK);
+	pr_debug("EraseThreshold:             0x%08x\n", fcb->EraseThreshold);
+	pr_debug("BootPatch:                  0x%08x\n", fcb->BootPatch);
+	pr_debug("PatchSectors:               0x%08x\n", fcb->PatchSectors);
+	pr_debug("Firmware1_startingPage:     0x%08x\n", fcb->Firmware1_startingPage);
+	pr_debug("Firmware2_startingPage:     0x%08x\n", fcb->Firmware2_startingPage);
+	pr_debug("PagesInFirmware1:           0x%08x\n", fcb->PagesInFirmware1);
+	pr_debug("PagesInFirmware2:           0x%08x\n", fcb->PagesInFirmware2);
+	pr_debug("DBBTSearchAreaStartAddress: 0x%08x\n", fcb->DBBTSearchAreaStartAddress);
+	pr_debug("BadBlockMarkerByte:         0x%08x\n", fcb->BadBlockMarkerByte);
+	pr_debug("BadBlockMarkerStartBit:     0x%08x\n", fcb->BadBlockMarkerStartBit);
+	pr_debug("BBMarkerPhysicalOffset:     0x%08x\n", fcb->BBMarkerPhysicalOffset);
+	pr_debug("BCHType:                    0x%08x\n", fcb->BCHType);
+	pr_debug("TMTiming2_ReadLatency:      0x%08x\n", fcb->TMTiming2_ReadLatency);
+	pr_debug("TMTiming2_PreambleDelay:    0x%08x\n", fcb->TMTiming2_PreambleDelay);
+	pr_debug("TMTiming2_CEDelay:          0x%08x\n", fcb->TMTiming2_CEDelay);
+	pr_debug("TMTiming2_PostambleDelay:   0x%08x\n", fcb->TMTiming2_PostambleDelay);
+	pr_debug("TMTiming2_CmdAddPause:      0x%08x\n", fcb->TMTiming2_CmdAddPause);
+	pr_debug("TMTiming2_DataPause:        0x%08x\n", fcb->TMTiming2_DataPause);
+	pr_debug("TMSpeed:                    0x%08x\n", fcb->TMSpeed);
+	pr_debug("TMTiming1_BusyTimeout:      0x%08x\n", fcb->TMTiming1_BusyTimeout);
+	pr_debug("DISBBM:                     0x%08x\n", fcb->DISBBM);
+	pr_debug("BBMarkerPhysOfsInSpareData: 0x%08x\n", fcb->BBMarkerPhysicalOffsetInSpareData);
+}
+
+static __maybe_unused ssize_t raw_read_page(struct mtd_info *mtd, void *dst, loff_t offset)
+{
+	struct mtd_oob_ops ops;
+	ssize_t ret;
+
+	ops.mode = MTD_OPS_RAW;
+	ops.ooboffs = 0;
+	ops.datbuf = dst;
+	ops.len = mtd->writesize;
+	ops.oobbuf = dst + mtd->writesize;
+	ops.ooblen = mtd->oobsize;
+	ret = mtd_read_oob(mtd, offset, &ops);
+
+        return ret;
+}
+
+static ssize_t raw_write_page(struct mtd_info *mtd, void *buf, loff_t offset)
+{
+	struct mtd_oob_ops ops;
+	ssize_t ret;
+
+	ops.mode = MTD_OPS_RAW;
+	ops.ooboffs = 0;
+	ops.datbuf = buf;
+	ops.len = mtd->writesize;
+	ops.oobbuf = buf + mtd->writesize;
+	ops.ooblen = mtd->oobsize;
+	ret = mtd_write_oob(mtd, offset, &ops);
+
+        return ret;
+}
+
+static int fcb_create(struct fcb_block *fcb, struct mtd_info *mtd)
+{
+	fcb->FingerPrint = 0x20424346;
+	fcb->Version = 0x01000000;
+	fcb->PageDataSize = mtd->writesize;
+	fcb->TotalPageSize = mtd->writesize + mtd->oobsize;
+	fcb->SectorsPerBlock = mtd->erasesize / mtd->writesize;
+
+	if (mtd->writesize == 2048) {
+		fcb->EccBlock0EccType = 4;
+	} else if (mtd->writesize == 4096) {
+		if (mtd->oobsize == 218) {
+			fcb->EccBlock0EccType = 8;
+		} else if (mtd->oobsize == 128) {
+			fcb->EccBlock0EccType = 4;
+		} else {
+			pr_err("Illegal oobsize %d\n", mtd->oobsize);
+			return -EINVAL;
+		}
+	} else {
+		pr_err("Illegal writesize %d\n", mtd->writesize);
+		return -EINVAL;
+	}
+
+	fcb->EccBlockNEccType = fcb->EccBlock0EccType;
+
+	/* Also hardcoded in kobs-ng */
+	fcb->DataSetup = 80;
+	fcb->DataHold = 60;
+	fcb->AddressSetup = 25;
+	fcb->DSAMPLE_TIME = 6;
+	fcb->MetadataBytes = 0x0000000a;
+	fcb->EccBlock0Size = 0x00000200;
+	fcb->EccBlockNSize = 0x00000200;
+
+	fcb->NumEccBlocksPerPage = mtd->writesize / fcb->EccBlock0Size - 1;
+
+	/* DBBT search area starts at third block */
+	fcb->DBBTSearchAreaStartAddress = mtd->erasesize / mtd->writesize * 2;
+
+	if (mtd->writesize == 2048) {
+		fcb->BadBlockMarkerByte = 0x000007cf;
+	} else {
+		pr_err("BadBlockMarkerByte unknown for writesize %d\n", mtd->writesize);
+		return -EINVAL;
+	}
+
+	fcb->BBMarkerPhysicalOffset = mtd->writesize;
+
+	fcb->Checksum = calc_chksum((void *)fcb + 4, sizeof(*fcb) - 4);
+
+	return 0;
+}
+
+static int imx6_bbu_erase(struct mtd_info *mtd)
+{
+	uint64_t offset = 0;
+	int len = SZ_2M;
+	struct erase_info erase;
+	int ret;
+
+	while (len > 0) {
+		pr_debug("erasing at 0x%08llx\n", offset);
+		if (mtd_block_isbad(mtd, offset)) {
+			offset += mtd->erasesize;
+			pr_debug("erase skip block @ 0x%08llx\n", offset);
+			continue;
+		}
+
+		memset(&erase, 0, sizeof(erase));
+		erase.addr = offset;
+		erase.len = mtd->erasesize;
+		
+		ret = mtd_erase(mtd, &erase);
+		if (ret)
+			return ret;
+
+		offset += mtd->erasesize;
+		len -= mtd->erasesize;
+	}
+
+	return 0;
+}
+
+static int imx6_bbu_write_firmware(struct mtd_info *mtd, int block, void *buf, size_t len)
+{
+	uint64_t offset = block * mtd->erasesize;
+	int ret;
+	size_t written;
+
+	while (len > 0) {
+		int now = min(len, mtd->erasesize);
+
+		pr_debug("writing %p at 0x%08llx, left 0x%08x\n",
+				buf, offset, len);
+
+		if (mtd_block_isbad(mtd, offset)) {
+			offset += mtd->erasesize;
+			block++;
+			pr_debug("write skip block @ 0x%08llx\n", offset);
+			continue;
+		}
+
+		ret = mtd_write(mtd, offset, now, &written, buf);
+		if (ret)
+			return ret;
+
+		offset += now;
+		len -= now;
+		buf += now;
+		block++;
+	}
+
+	return block;
+}
+
+static int dbbt_data_create(struct mtd_info *mtd, void *buf, int block_last)
+{
+	int n;
+	int n_bad_blocks = 0;
+	uint32_t *bb = buf + 0x8;
+	uint32_t *n_bad_blocksp = buf + 0x4;
+
+	for (n = 0; n <= block_last; n++) {
+		loff_t offset = n * mtd->erasesize;
+		if (mtd_block_isbad(mtd, offset)) {
+			n_bad_blocks++;
+			*bb = n;
+			bb++;
+		}
+	}
+
+	*n_bad_blocksp = n_bad_blocks;
+
+	return n_bad_blocks;
+}
+
+static int imx6_bbu_nand_update(struct bbu_handler *handler, struct bbu_data *data)
+{
+	struct cdev *bcb_cdev;
+	struct mtd_info *mtd;
+	int ret, block_fw1, block_fw2, block_last;
+	struct fcb_block *fcb;
+	struct dbbt_block *dbbt;
+	void *fcb_raw_page, *dbbt_page, *dbbt_data_page;
+	void *ecc;
+	int written;
+	void *fw;
+	unsigned fw_size;
+	int i;
+
+	bcb_cdev = cdev_by_name("nand0");
+	if (!bcb_cdev) {
+		pr_err("%s: No FCB device!\n", __func__);
+		return -ENODEV;
+	}
+
+	mtd = bcb_cdev->mtd;
+
+	fcb_raw_page = xzalloc(mtd->writesize + mtd->oobsize);
+
+	fcb = fcb_raw_page + 12;
+	ecc = fcb_raw_page + 512 + 12;
+
+	dbbt_page = xzalloc(mtd->writesize);
+	dbbt_data_page = xzalloc(mtd->writesize);
+	dbbt = dbbt_page;
+
+	/*
+	 * We have to write one additional page to make the ROM happy.
+	 * Maybe the PagesInFirmwarex fields are really the number of pages - 1.
+	 * kobs-ng has the same.
+	 */
+	fw_size = ALIGN(data->len + mtd->writesize, mtd->writesize);
+	fw = xzalloc(fw_size);
+	memcpy(fw, data->image, data->len);
+
+	block_fw1 = 4;
+
+	ret = imx6_bbu_erase(mtd);
+	if (ret)
+		goto out;
+
+	ret = imx6_bbu_write_firmware(mtd, block_fw1, fw, fw_size);
+	if (ret < 0)
+		goto out;
+
+	block_fw2 = ret;
+
+	ret = imx6_bbu_write_firmware(mtd, block_fw2, fw, fw_size);
+	if (ret < 0)
+		goto out;
+
+	block_last = ret;
+
+	fcb->Firmware1_startingPage = block_fw1 * mtd->erasesize / mtd->writesize;
+	fcb->Firmware2_startingPage = block_fw2 * mtd->erasesize / mtd->writesize;
+	fcb->PagesInFirmware1 = ALIGN(data->len, mtd->writesize) / mtd->writesize;
+	fcb->PagesInFirmware2 = fcb->PagesInFirmware1;
+
+	fcb_create(fcb, mtd);
+	encode_hamming_13_8(fcb, ecc, 512);
+	ret = raw_write_page(mtd, fcb_raw_page, 0);
+	if (ret)
+		goto out;
+
+	ret = raw_write_page(mtd, fcb_raw_page, mtd->erasesize);
+	if (ret)
+		goto out;
+
+	dbbt->Checksum = 0;
+	dbbt->FingerPrint = 0x54424244;
+	dbbt->Version = 0x01000000;
+
+	ret = dbbt_data_create(mtd, dbbt_data_page, block_last);
+	if (ret < 0)
+		goto out;
+
+	if (ret > 0)
+		dbbt->DBBTNumOfPages = 1;
+
+	for (i = 2; i < 4; i++) {
+		ret = mtd_write(mtd, mtd->erasesize * i, 2048, &written, dbbt_page);
+		if (ret)
+			goto out;
+
+		if (dbbt->DBBTNumOfPages > 0) {
+			ret = mtd_write(mtd, mtd->erasesize * i + mtd->writesize * 4,
+					2048, &written, dbbt_data_page);
+			if (ret)
+				goto out;
+		}
+	}
+
+out:
+	free(dbbt_page);
+	free(dbbt_data_page);
+	free(fcb_raw_page);
+	free(fw);
+
+	return ret;
+}
+
+int imx6_bbu_nand_register_handler(const char *name, unsigned long flags)
+{
+	struct bbu_handler *handler;
+	int ret;
+
+	handler = xzalloc(sizeof(*handler));
+	handler->devicefile = "/dev/nand0";
+	handler->name = name;
+	handler->flags = flags;
+	handler->handler = imx6_bbu_nand_update;
+
+	ret = bbu_register_handler(handler);
+	if (ret)
+		free(handler);
+
+	return ret;
+}
diff --git a/arch/arm/mach-imx/include/mach/bbu.h b/arch/arm/mach-imx/include/mach/bbu.h
index 3cd3b1e..1644d85 100644
--- a/arch/arm/mach-imx/include/mach/bbu.h
+++ b/arch/arm/mach-imx/include/mach/bbu.h
@@ -33,6 +33,8 @@ int imx6_bbu_internal_spi_i2c_register_handler(const char *name, char *devicefil
 		unsigned long flags, struct imx_dcd_v2_entry *dcd, int dcdsize,
 		unsigned long app_dest);
 
+int imx6_bbu_nand_register_handler(const char *name, unsigned long flags);
+
 #else
 
 static inline int imx51_bbu_internal_mmc_register_handler(const char *name, char *devicefile,
@@ -77,6 +79,10 @@ static inline int imx6_bbu_internal_spi_i2c_register_handler(const char *name, c
 	return -ENOSYS;
 }
 
+static inline int imx6_bbu_nand_register_handler(const char *name, unsigned long flags)
+{
+	return -ENOSYS;
+}
 #endif
 
 #if defined(CONFIG_BAREBOX_UPDATE_IMX_EXTERNAL_NAND)
-- 
1.9.0


-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From shc_work at mail.ru  Sat Mar 22 04:03:38 2014
From: shc_work at mail.ru (Alexander Shiyan)
Date: Sat, 22 Mar 2014 12:03:38 +0400
Subject: [PATCH RESEND] drivers: treewide: Kill empty remove() implementations
Message-ID: <1395475418-15885-1-git-send-email-shc_work@mail.ru>

Signed-off-by: Alexander Shiyan <shc_work at mail.ru>
---
 drivers/net/ar231x.c       | 6 ------
 drivers/net/at91_ether.c   | 5 -----
 drivers/net/designware.c   | 5 -----
 drivers/video/imx-ipu-fb.c | 5 -----
 drivers/video/imx.c        | 5 -----
 drivers/video/pxa.c        | 5 -----
 6 files changed, 31 deletions(-)

diff --git a/drivers/net/ar231x.c b/drivers/net/ar231x.c
index 5c09114..515de17 100644
--- a/drivers/net/ar231x.c
+++ b/drivers/net/ar231x.c
@@ -419,15 +419,9 @@ static int ar231x_eth_probe(struct device_d *dev)
 	return 0;
 }
 
-static void ar231x_eth_remove(struct device_d *dev)
-{
-
-}
-
 static struct driver_d ar231x_eth_driver = {
 	.name = "ar231x_eth",
 	.probe = ar231x_eth_probe,
-	.remove = ar231x_eth_remove,
 };
 
 static int ar231x_eth_driver_init(void)
diff --git a/drivers/net/at91_ether.c b/drivers/net/at91_ether.c
index 25924cf..bf2f957 100644
--- a/drivers/net/at91_ether.c
+++ b/drivers/net/at91_ether.c
@@ -357,13 +357,8 @@ static int at91_ether_probe(struct device_d *dev)
 	return 0;
 }
 
-static void at91_ether_remove(struct device_d *dev)
-{
-}
-
 static struct driver_d at91_ether_driver = {
 	.name = "at91_ether",
 	.probe = at91_ether_probe,
-	.remove = at91_ether_remove,
 };
 device_platform_driver(at91_ether_driver);
diff --git a/drivers/net/designware.c b/drivers/net/designware.c
index ecb4656..e706f54 100644
--- a/drivers/net/designware.c
+++ b/drivers/net/designware.c
@@ -477,10 +477,6 @@ static int dwc_ether_probe(struct device_d *dev)
 	return 0;
 }
 
-static void dwc_ether_remove(struct device_d *dev)
-{
-}
-
 static __maybe_unused struct of_device_id dwc_ether_compatible[] = {
 	{
 		.compatible = "snps,dwmac-3.70a",
@@ -493,7 +489,6 @@ static __maybe_unused struct of_device_id dwc_ether_compatible[] = {
 static struct driver_d dwc_ether_driver = {
 	.name = "designware_eth",
 	.probe = dwc_ether_probe,
-	.remove = dwc_ether_remove,
 	.of_compatible = DRV_OF_COMPAT(dwc_ether_compatible),
 };
 device_platform_driver(dwc_ether_driver);
diff --git a/drivers/video/imx-ipu-fb.c b/drivers/video/imx-ipu-fb.c
index 7276647..cd74b03 100644
--- a/drivers/video/imx-ipu-fb.c
+++ b/drivers/video/imx-ipu-fb.c
@@ -1047,14 +1047,9 @@ static int imxfb_probe(struct device_d *dev)
 	return ret;
 }
 
-static void imxfb_remove(struct device_d *dev)
-{
-}
-
 static struct driver_d imx3fb_driver = {
 	.name = "imx-ipu-fb",
 	.probe = imxfb_probe,
-	.remove = imxfb_remove,
 };
 device_platform_driver(imx3fb_driver);
 
diff --git a/drivers/video/imx.c b/drivers/video/imx.c
index 05c6105..e4dcc35 100644
--- a/drivers/video/imx.c
+++ b/drivers/video/imx.c
@@ -580,13 +580,8 @@ static int imxfb_probe(struct device_d *dev)
 	return 0;
 }
 
-static void imxfb_remove(struct device_d *dev)
-{
-}
-
 static struct driver_d imxfb_driver = {
 	.name		= "imxfb",
 	.probe		= imxfb_probe,
-	.remove		= imxfb_remove,
 };
 device_platform_driver(imxfb_driver);
diff --git a/drivers/video/pxa.c b/drivers/video/pxa.c
index 529190b..b4ce3a1 100644
--- a/drivers/video/pxa.c
+++ b/drivers/video/pxa.c
@@ -536,13 +536,8 @@ static int pxafb_probe(struct device_d *dev)
 	return 0;
 }
 
-static void pxafb_remove(struct device_d *dev)
-{
-}
-
 static struct driver_d pxafb_driver = {
 	.name	= "pxafb",
 	.probe	= pxafb_probe,
-	.remove	= pxafb_remove,
 };
 device_platform_driver(pxafb_driver);
-- 
1.8.3.2



From antonynpavlov at gmail.com  Sat Mar 22 07:29:50 2014
From: antonynpavlov at gmail.com (Antony Pavlov)
Date: Sat, 22 Mar 2014 15:29:50 +0400
Subject: [PATCH 0/7] MIPS: improve Ingenic JZ4755 device tree support
Message-ID: <1395487797-16599-1-git-send-email-antonynpavlov@gmail.com>

This patcheseries moves Ingenic JZ4755 UART initialization
into device tree and makes JZ4755 device tree organization
more clear.

This patchseries is a part of work on Ingenic chips support
and prepares MIPS board support switch to device tree.
Next patchseries will add device tree Ingenic gpio, clk
and pinctls support.

Antony Pavlov (7):
  MIPS: mach-xburst: fix DEBUG_LL=n build error
  MIPS: dts: rzx50: move jz4755 description to the separate file
  serial: ns16550: make it possible to get reg_write() from devtype
  serial: ns16550: add compatible entry for "ingenic,jz4740-uart"
  MIPS: rzx50: drop console initialization in board code
  MIPS: mach-xburst: drop serial.c
  MIPS: boards: rename rzx50 -> ritmix-rzx50

 Documentation/boards.dox                           |  2 +-
 arch/mips/Makefile                                 |  2 +-
 arch/mips/boards/ritmix-rzx50/Makefile             |  1 +
 .../ritmix-rzx50/include/board/board_pbl_start.h   | 43 ++++++++++++++++
 .../boards/ritmix-rzx50/include/board/debug_ll.h   | 23 +++++++++
 arch/mips/boards/ritmix-rzx50/ritmix-rzx50.dox     | 46 +++++++++++++++++
 arch/mips/boards/ritmix-rzx50/serial.c             | 27 ++++++++++
 arch/mips/boards/rzx50/Makefile                    |  1 -
 .../boards/rzx50/include/board/board_pbl_start.h   | 43 ----------------
 arch/mips/boards/rzx50/include/board/debug_ll.h    | 23 ---------
 arch/mips/boards/rzx50/rzx50.dox                   | 46 -----------------
 arch/mips/boards/rzx50/serial.c                    | 32 ------------
 arch/mips/configs/ritmix-rzx50_defconfig           | 39 ++++++++++++++
 arch/mips/configs/rzx50_defconfig                  | 39 --------------
 arch/mips/dts/jz4755.dtsi                          | 35 +++++++++++++
 arch/mips/dts/rzx50.dts                            |  8 ++-
 arch/mips/include/asm/debug_ll_ns16550.h           |  2 +
 arch/mips/mach-xburst/Makefile                     |  1 -
 arch/mips/mach-xburst/mach-xburst.dox              |  2 +-
 arch/mips/mach-xburst/serial.c                     | 60 ----------------------
 drivers/serial/serial_ns16550.c                    | 35 +++++++++++++
 21 files changed, 261 insertions(+), 249 deletions(-)
 create mode 100644 arch/mips/boards/ritmix-rzx50/Makefile
 create mode 100644 arch/mips/boards/ritmix-rzx50/include/board/board_pbl_start.h
 create mode 100644 arch/mips/boards/ritmix-rzx50/include/board/debug_ll.h
 create mode 100644 arch/mips/boards/ritmix-rzx50/ritmix-rzx50.dox
 create mode 100644 arch/mips/boards/ritmix-rzx50/serial.c
 delete mode 100644 arch/mips/boards/rzx50/Makefile
 delete mode 100644 arch/mips/boards/rzx50/include/board/board_pbl_start.h
 delete mode 100644 arch/mips/boards/rzx50/include/board/debug_ll.h
 delete mode 100644 arch/mips/boards/rzx50/rzx50.dox
 delete mode 100644 arch/mips/boards/rzx50/serial.c
 create mode 100644 arch/mips/configs/ritmix-rzx50_defconfig
 delete mode 100644 arch/mips/configs/rzx50_defconfig
 create mode 100644 arch/mips/dts/jz4755.dtsi
 delete mode 100644 arch/mips/mach-xburst/serial.c

-- 
1.9.0



From antonynpavlov at gmail.com  Sat Mar 22 07:29:53 2014
From: antonynpavlov at gmail.com (Antony Pavlov)
Date: Sat, 22 Mar 2014 15:29:53 +0400
Subject: [PATCH 3/7] serial: ns16550: make it possible to get reg_write() from
 devtype
In-Reply-To: <1395487797-16599-1-git-send-email-antonynpavlov@gmail.com>
References: <1395487797-16599-1-git-send-email-antonynpavlov@gmail.com>
Message-ID: <1395487797-16599-4-git-send-email-antonynpavlov@gmail.com>

Signed-off-by: Antony Pavlov <antonynpavlov at gmail.com>
---
 drivers/serial/serial_ns16550.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/serial/serial_ns16550.c b/drivers/serial/serial_ns16550.c
index f1da44b..aa0992f 100644
--- a/drivers/serial/serial_ns16550.c
+++ b/drivers/serial/serial_ns16550.c
@@ -57,6 +57,8 @@ static inline struct ns16550_priv *to_ns16550_priv(struct console_device *cdev)
 
 struct ns16550_drvdata {
 	void (*init_port)(struct console_device *cdev);
+	void (*reg_write)(unsigned int val, unsigned long base,
+				    unsigned char reg_offset);
 	const char *linux_console_name;
 };
 
@@ -316,6 +318,9 @@ static int ns16550_probe(struct device_d *dev)
 	cdev->setbrg = ns16550_setbaudrate;
 	cdev->linux_console_name = devtype->linux_console_name;
 
+	if (devtype->reg_write)
+		priv->plat.reg_write = devtype->reg_write;
+
 	devtype->init_port(cdev);
 
 	return console_register(cdev);
-- 
1.9.0



From antonynpavlov at gmail.com  Sat Mar 22 07:29:54 2014
From: antonynpavlov at gmail.com (Antony Pavlov)
Date: Sat, 22 Mar 2014 15:29:54 +0400
Subject: [PATCH 4/7] serial: ns16550: add compatible entry for "ingenic,
 jz4740-uart"
In-Reply-To: <1395487797-16599-1-git-send-email-antonynpavlov@gmail.com>
References: <1395487797-16599-1-git-send-email-antonynpavlov@gmail.com>
Message-ID: <1395487797-16599-5-git-send-email-antonynpavlov@gmail.com>

Signed-off-by: Antony Pavlov <antonynpavlov at gmail.com>
---
 drivers/serial/serial_ns16550.c | 30 ++++++++++++++++++++++++++++++
 1 file changed, 30 insertions(+)

diff --git a/drivers/serial/serial_ns16550.c b/drivers/serial/serial_ns16550.c
index aa0992f..7130871 100644
--- a/drivers/serial/serial_ns16550.c
+++ b/drivers/serial/serial_ns16550.c
@@ -257,6 +257,30 @@ static __maybe_unused struct ns16550_drvdata omap_drvdata = {
 	.linux_console_name = "ttyO",
 };
 
+#define JZ_UART_SHIFT	2
+
+static void jz_serial_reg_write(unsigned int val, unsigned long base,
+	unsigned char reg_offset)
+{
+	switch (reg_offset) {
+	case (fcr << JZ_UART_SHIFT):
+		val |= 0x10; /* Enable uart module */
+		break;
+	case (ier << JZ_UART_SHIFT):
+		val |= (val & 0x4) << 2;
+		break;
+	default:
+		break;
+	}
+
+	writeb(val & 0xff, (void *)(base + reg_offset));
+}
+
+static __maybe_unused struct ns16550_drvdata jz_drvdata = {
+	.init_port = ns16550_serial_init_port,
+	.reg_write = jz_serial_reg_write,
+};
+
 /**
  * @brief Probe entry point -called on the first match for device
  *
@@ -351,6 +375,12 @@ static struct of_device_id ns16550_serial_dt_ids[] = {
 		.data = (unsigned long)&omap_drvdata,
 	},
 #endif
+#if IS_ENABLED(CONFIG_MACH_MIPS_XBURST)
+	{
+		.compatible = "ingenic,jz4740-uart",
+		.data = (unsigned long)&jz_drvdata,
+	},
+#endif
 	{
 		/* sentinel */
 	},
-- 
1.9.0



From antonynpavlov at gmail.com  Sat Mar 22 07:29:55 2014
From: antonynpavlov at gmail.com (Antony Pavlov)
Date: Sat, 22 Mar 2014 15:29:55 +0400
Subject: [PATCH 5/7] MIPS: rzx50: drop console initialization in board code
In-Reply-To: <1395487797-16599-1-git-send-email-antonynpavlov@gmail.com>
References: <1395487797-16599-1-git-send-email-antonynpavlov@gmail.com>
Message-ID: <1395487797-16599-6-git-send-email-antonynpavlov@gmail.com>

Signed-off-by: Antony Pavlov <antonynpavlov at gmail.com>
---
 arch/mips/boards/rzx50/Makefile | 2 +-
 arch/mips/boards/rzx50/serial.c | 9 ++-------
 2 files changed, 3 insertions(+), 8 deletions(-)

diff --git a/arch/mips/boards/rzx50/Makefile b/arch/mips/boards/rzx50/Makefile
index ff1a655..31c0629 100644
--- a/arch/mips/boards/rzx50/Makefile
+++ b/arch/mips/boards/rzx50/Makefile
@@ -1 +1 @@
-obj-$(CONFIG_DRIVER_SERIAL_NS16550) += serial.o
+obj-y += serial.o
diff --git a/arch/mips/boards/rzx50/serial.c b/arch/mips/boards/rzx50/serial.c
index 566356a..f1e8da0 100644
--- a/arch/mips/boards/rzx50/serial.c
+++ b/arch/mips/boards/rzx50/serial.c
@@ -17,16 +17,11 @@
 
 #include <common.h>
 #include <init.h>
-#include <mach/devices.h>
-#include <mach/jz4750d_regs.h>
 
-static int rzx50_console_init(void)
+static int rzx50_hostname_init(void)
 {
 	barebox_set_hostname("rzx50");
 
-	/* Register the serial port */
-	jz_add_uart(DEVICE_ID_DYNAMIC, UART1_BASE, 12000000);
-
 	return 0;
 }
-console_initcall(rzx50_console_init);
+console_initcall(rzx50_hostname_init);
-- 
1.9.0



From antonynpavlov at gmail.com  Sat Mar 22 07:29:56 2014
From: antonynpavlov at gmail.com (Antony Pavlov)
Date: Sat, 22 Mar 2014 15:29:56 +0400
Subject: [PATCH 6/7] MIPS: mach-xburst: drop serial.c
In-Reply-To: <1395487797-16599-1-git-send-email-antonynpavlov@gmail.com>
References: <1395487797-16599-1-git-send-email-antonynpavlov@gmail.com>
Message-ID: <1395487797-16599-7-git-send-email-antonynpavlov@gmail.com>

We use dts for serial port initialization,
so we have no need in mach-xburst/serial.c anymore.

Signed-off-by: Antony Pavlov <antonynpavlov at gmail.com>
---
 arch/mips/mach-xburst/Makefile |  1 -
 arch/mips/mach-xburst/serial.c | 60 ------------------------------------------
 2 files changed, 61 deletions(-)

diff --git a/arch/mips/mach-xburst/Makefile b/arch/mips/mach-xburst/Makefile
index 3e0cd73..e5634ba 100644
--- a/arch/mips/mach-xburst/Makefile
+++ b/arch/mips/mach-xburst/Makefile
@@ -1,2 +1 @@
-obj-y += serial.o
 obj-$(CONFIG_CPU_JZ4755) += csrc-jz4750.o reset-jz4750.o
diff --git a/arch/mips/mach-xburst/serial.c b/arch/mips/mach-xburst/serial.c
deleted file mode 100644
index acf5648..0000000
--- a/arch/mips/mach-xburst/serial.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- * Copyright (C) 2013 Antony Pavlov <antonynpavlov at gmail.com>
- *
- * Based on the linux kernel JZ4740 serial support:
- * Copyright (C) 2010, Lars-Peter Clausen <lars at metafoo.de>
- *
- * This file is part of barebox.
- * See file CREDITS for list of people who contributed to this project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2
- * as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <common.h>
-#include <ns16550.h>
-#include <io.h>
-#include <mach/devices.h>
-
-#define JZ_UART_SHIFT	2
-
-#define ier		(1 << JZ_UART_SHIFT)
-#define fcr		(2 << JZ_UART_SHIFT)
-
-static void jz_serial_reg_write(unsigned int val, unsigned long base,
-	unsigned char reg_offset)
-{
-	switch (reg_offset) {
-	case fcr:
-		val |= 0x10; /* Enable uart module */
-		break;
-	case ier:
-		val |= (val & 0x4) << 2;
-		break;
-	default:
-		break;
-	}
-
-	writeb(val & 0xff, (void *)(base + reg_offset));
-}
-
-struct device_d *jz_add_uart(int id, unsigned long base, unsigned int clock)
-{
-	struct NS16550_plat *serial_plat;
-
-	serial_plat = xzalloc(sizeof(*serial_plat));
-
-	serial_plat->shift = JZ_UART_SHIFT;
-	serial_plat->reg_write = &jz_serial_reg_write;
-	serial_plat->clock = clock;
-
-	return add_ns16550_device(id, base, 8 << JZ_UART_SHIFT,
-			IORESOURCE_MEM_8BIT, serial_plat);
-}
-- 
1.9.0



From antonynpavlov at gmail.com  Sat Mar 22 07:29:57 2014
From: antonynpavlov at gmail.com (Antony Pavlov)
Date: Sat, 22 Mar 2014 15:29:57 +0400
Subject: [PATCH 7/7] MIPS: boards: rename rzx50 -> ritmix-rzx50
In-Reply-To: <1395487797-16599-1-git-send-email-antonynpavlov@gmail.com>
References: <1395487797-16599-1-git-send-email-antonynpavlov@gmail.com>
Message-ID: <1395487797-16599-8-git-send-email-antonynpavlov@gmail.com>

All MIPS board use <vendor>-<model> name template save Ritmix RZX-50.
This commit fixes this inconsistency.

Signed-off-by: Antony Pavlov <antonynpavlov at gmail.com>
---
 Documentation/boards.dox                           |  2 +-
 arch/mips/Makefile                                 |  2 +-
 arch/mips/boards/ritmix-rzx50/Makefile             |  1 +
 .../ritmix-rzx50/include/board/board_pbl_start.h   | 43 ++++++++++++++++++++
 .../boards/ritmix-rzx50/include/board/debug_ll.h   | 23 +++++++++++
 arch/mips/boards/ritmix-rzx50/ritmix-rzx50.dox     | 46 ++++++++++++++++++++++
 arch/mips/boards/ritmix-rzx50/serial.c             | 27 +++++++++++++
 arch/mips/boards/rzx50/Makefile                    |  1 -
 .../boards/rzx50/include/board/board_pbl_start.h   | 43 --------------------
 arch/mips/boards/rzx50/include/board/debug_ll.h    | 23 -----------
 arch/mips/boards/rzx50/rzx50.dox                   | 46 ----------------------
 arch/mips/boards/rzx50/serial.c                    | 27 -------------
 arch/mips/configs/ritmix-rzx50_defconfig           | 39 ++++++++++++++++++
 arch/mips/configs/rzx50_defconfig                  | 39 ------------------
 arch/mips/mach-xburst/mach-xburst.dox              |  2 +-
 15 files changed, 182 insertions(+), 182 deletions(-)

diff --git a/Documentation/boards.dox b/Documentation/boards.dox
index 9a14aee..42bc5e6 100644
--- a/Documentation/boards.dox
+++ b/Documentation/boards.dox
@@ -59,7 +59,7 @@ MIPS type:
 @li @subpage dlink_dir_320
 @li @subpage loongson_ls1b
 @li @subpage qemu_malta
- at li @subpage rzx50
+ at li @subpage ritmix-rzx50
 
 */
 
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 8986fcf..e3d65c8 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -85,7 +85,7 @@ machine-$(CONFIG_MACH_MIPS_LOONGSON)	:= loongson
 board-$(CONFIG_BOARD_LOONGSON_TECH_LS1B)	:= loongson-ls1b
 
 machine-$(CONFIG_MACH_MIPS_XBURST)	:= xburst
-board-$(CONFIG_BOARD_RZX50)	:= rzx50
+board-$(CONFIG_BOARD_RZX50)	:= ritmix-rzx50
 
 machdirs := $(patsubst %,arch/mips/mach-%/,$(machine-y))
 
diff --git a/arch/mips/boards/ritmix-rzx50/Makefile b/arch/mips/boards/ritmix-rzx50/Makefile
new file mode 100644
index 0000000..31c0629
--- /dev/null
+++ b/arch/mips/boards/ritmix-rzx50/Makefile
@@ -0,0 +1 @@
+obj-y += serial.o
diff --git a/arch/mips/boards/ritmix-rzx50/include/board/board_pbl_start.h b/arch/mips/boards/ritmix-rzx50/include/board/board_pbl_start.h
new file mode 100644
index 0000000..fb914d9
--- /dev/null
+++ b/arch/mips/boards/ritmix-rzx50/include/board/board_pbl_start.h
@@ -0,0 +1,43 @@
+/*
+ * Startup Code for Ritmix RZX-50 board
+ *
+ * Copyright (C) 2013 Antony Pavlov <antonynpavlov at gmail.com>
+ *
+ * This file is part of barebox.
+ * See file CREDITS for list of people who contributed to this project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <asm/pbl_macros.h>
+#include <mach/debug_ll.h>
+#include <asm/pbl_nmon.h>
+
+	.macro	board_pbl_start
+	.set	push
+	.set	noreorder
+
+	mips_disable_interrupts
+
+	/* CPU/SoC specific setup ... */
+	/* ... absent */
+
+	debug_ll_ns16550_init
+
+	debug_ll_ns16550_outc '.'
+	debug_ll_ns16550_outnl
+
+	mips_nmon
+
+	copy_to_link_location	pbl_start
+
+	.set	pop
+	.endm
diff --git a/arch/mips/boards/ritmix-rzx50/include/board/debug_ll.h b/arch/mips/boards/ritmix-rzx50/include/board/debug_ll.h
new file mode 100644
index 0000000..7ae0e2a
--- /dev/null
+++ b/arch/mips/boards/ritmix-rzx50/include/board/debug_ll.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (C) 2012 Antony Pavlov <antonynpavlov at gmail.com>
+ *
+ * This file is part of barebox.
+ * See file CREDITS for list of people who contributed to this project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __INCLUDE_RZX50_BOARD_DEBUG_LL_H__
+#define __INCLUDE_RZX50_BOARD_DEBUG_LL_H__
+
+#include <mach/debug_ll_jz4750d.h>
+
+#endif  /* __INCLUDE_RZX50_BOARD_DEBUG_LL_H__ */
diff --git a/arch/mips/boards/ritmix-rzx50/ritmix-rzx50.dox b/arch/mips/boards/ritmix-rzx50/ritmix-rzx50.dox
new file mode 100644
index 0000000..5ec8194
--- /dev/null
+++ b/arch/mips/boards/ritmix-rzx50/ritmix-rzx50.dox
@@ -0,0 +1,46 @@
+/** @page ritmix-rzx50 Ritmix RZX-50 game console
+
+Ritmix RZX-50 is a portable game console for the Russian market.
+
+The portable game console has
+ at li Ingenic JZ4755 SoC;
+ at li 64 MiB SDRAM;
+ at li 4 GiB microSDHC card / 4 GiB NAND type Flash Memory;
+ at li RS232 serial interface (LV-TTL levels on the board!);
+ at li LCD display (480x272);
+ at li Video out interface;
+ at li 1xUSB interface;
+ at li buttons.
+
+The game console uses U-Boot 1.1.6 as bootloader.
+
+barebox-rzx50 mini-howto:
+
+1. Connect to the game console's UART (see. http://a320.emulate.su/2012/01/19/uart-na-ritmix-rzx-50/);
+
+2. Unblock U-Boot console (see. http://a320.emulate.su/2012/01/25/rzx-50-dostup-k-konsoli-u-boot/); Please note that U-Boot's Zmodem support does not work;
+
+3. Boot Ritmix linux and login;
+
+4. Upload barebox.bin via Zmodem
+ at verbatim
+  # cd /tmp
+  # rz
+ at endverbatim
+
+5. Write barebox to onboard flash
+ at verbatim
+  # dd if=barebox.bin of=/dev/mmcblk0 seek=1048576 bs=1 count=262144
+ at endverbatim
+
+6. Reboot RZX-50, next in U-Boot console start barebox:
+ at verbatim
+  CETUS # msc read 0xa0800000 0x100000 0x40000; g a0800000
+ at endverbatim
+
+Ritmix RZX-50 links:
+ at li http://www.ritmixrussia.ru/products/252/entertainment/game/rzx-50
+ at li ftp://ftp.ingenic.cn/2soc/4755/JZ4755_ds.pdf
+ at li ftp://ftp.ingenic.cn/3sw/01linux/01loader/u-boot/u-boot-1.1.6-jz-20110719-r1728-add-jz4770.patch.bz2
+
+*/
diff --git a/arch/mips/boards/ritmix-rzx50/serial.c b/arch/mips/boards/ritmix-rzx50/serial.c
new file mode 100644
index 0000000..f1e8da0
--- /dev/null
+++ b/arch/mips/boards/ritmix-rzx50/serial.c
@@ -0,0 +1,27 @@
+/*
+ * Copyright (C) 2012 Antony Pavlov <antonynpavlov at gmail.com>
+ *
+ * This file is part of barebox.
+ * See file CREDITS for list of people who contributed to this project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <common.h>
+#include <init.h>
+
+static int rzx50_hostname_init(void)
+{
+	barebox_set_hostname("rzx50");
+
+	return 0;
+}
+console_initcall(rzx50_hostname_init);
diff --git a/arch/mips/boards/rzx50/Makefile b/arch/mips/boards/rzx50/Makefile
deleted file mode 100644
index 31c0629..0000000
--- a/arch/mips/boards/rzx50/Makefile
+++ /dev/null
@@ -1 +0,0 @@
-obj-y += serial.o
diff --git a/arch/mips/boards/rzx50/include/board/board_pbl_start.h b/arch/mips/boards/rzx50/include/board/board_pbl_start.h
deleted file mode 100644
index fb914d9..0000000
--- a/arch/mips/boards/rzx50/include/board/board_pbl_start.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * Startup Code for Ritmix RZX-50 board
- *
- * Copyright (C) 2013 Antony Pavlov <antonynpavlov at gmail.com>
- *
- * This file is part of barebox.
- * See file CREDITS for list of people who contributed to this project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2
- * as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <asm/pbl_macros.h>
-#include <mach/debug_ll.h>
-#include <asm/pbl_nmon.h>
-
-	.macro	board_pbl_start
-	.set	push
-	.set	noreorder
-
-	mips_disable_interrupts
-
-	/* CPU/SoC specific setup ... */
-	/* ... absent */
-
-	debug_ll_ns16550_init
-
-	debug_ll_ns16550_outc '.'
-	debug_ll_ns16550_outnl
-
-	mips_nmon
-
-	copy_to_link_location	pbl_start
-
-	.set	pop
-	.endm
diff --git a/arch/mips/boards/rzx50/include/board/debug_ll.h b/arch/mips/boards/rzx50/include/board/debug_ll.h
deleted file mode 100644
index 7ae0e2a..0000000
--- a/arch/mips/boards/rzx50/include/board/debug_ll.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * Copyright (C) 2012 Antony Pavlov <antonynpavlov at gmail.com>
- *
- * This file is part of barebox.
- * See file CREDITS for list of people who contributed to this project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2
- * as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef __INCLUDE_RZX50_BOARD_DEBUG_LL_H__
-#define __INCLUDE_RZX50_BOARD_DEBUG_LL_H__
-
-#include <mach/debug_ll_jz4750d.h>
-
-#endif  /* __INCLUDE_RZX50_BOARD_DEBUG_LL_H__ */
diff --git a/arch/mips/boards/rzx50/rzx50.dox b/arch/mips/boards/rzx50/rzx50.dox
deleted file mode 100644
index 963473c..0000000
--- a/arch/mips/boards/rzx50/rzx50.dox
+++ /dev/null
@@ -1,46 +0,0 @@
-/** @page rzx50 Ritmix RZX-50 game console
-
-Ritmix RZX-50 is a portable game console for the Russian market.
-
-The portable game console has
- at li Ingenic JZ4755 SoC;
- at li 64 MiB SDRAM;
- at li 4 GiB microSDHC card / 4 GiB NAND type Flash Memory;
- at li RS232 serial interface (LV-TTL levels on the board!);
- at li LCD display (480x272);
- at li Video out interface;
- at li 1xUSB interface;
- at li buttons.
-
-The game console uses U-Boot 1.1.6 as bootloader.
-
-barebox-rzx50 mini-howto:
-
-1. Connect to the game console's UART (see. http://a320.emulate.su/2012/01/19/uart-na-ritmix-rzx-50/);
-
-2. Unblock U-Boot console (see. http://a320.emulate.su/2012/01/25/rzx-50-dostup-k-konsoli-u-boot/); Please note that U-Boot's Zmodem support does not work;
-
-3. Boot Ritmix linux and login;
-
-4. Upload barebox.bin via Zmodem
- at verbatim
-  # cd /tmp
-  # rz
- at endverbatim
-
-5. Write barebox to onboard flash
- at verbatim
-  # dd if=barebox.bin of=/dev/mmcblk0 seek=1048576 bs=1 count=262144
- at endverbatim
-
-6. Reboot RZX-50, next in U-Boot console start barebox:
- at verbatim
-  CETUS # msc read 0xa0800000 0x100000 0x40000; g a0800000
- at endverbatim
-
-Ritmix RZX-50 links:
- at li http://www.ritmixrussia.ru/products/252/entertainment/game/rzx-50
- at li ftp://ftp.ingenic.cn/2soc/4755/JZ4755_ds.pdf
- at li ftp://ftp.ingenic.cn/3sw/01linux/01loader/u-boot/u-boot-1.1.6-jz-20110719-r1728-add-jz4770.patch.bz2
-
-*/
diff --git a/arch/mips/boards/rzx50/serial.c b/arch/mips/boards/rzx50/serial.c
deleted file mode 100644
index f1e8da0..0000000
--- a/arch/mips/boards/rzx50/serial.c
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * Copyright (C) 2012 Antony Pavlov <antonynpavlov at gmail.com>
- *
- * This file is part of barebox.
- * See file CREDITS for list of people who contributed to this project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2
- * as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <common.h>
-#include <init.h>
-
-static int rzx50_hostname_init(void)
-{
-	barebox_set_hostname("rzx50");
-
-	return 0;
-}
-console_initcall(rzx50_hostname_init);
diff --git a/arch/mips/configs/ritmix-rzx50_defconfig b/arch/mips/configs/ritmix-rzx50_defconfig
new file mode 100644
index 0000000..7691bae
--- /dev/null
+++ b/arch/mips/configs/ritmix-rzx50_defconfig
@@ -0,0 +1,39 @@
+CONFIG_BUILTIN_DTB=y
+CONFIG_BUILTIN_DTB_NAME="rzx50"
+CONFIG_MACH_MIPS_XBURST=y
+CONFIG_JZ4750D_DEBUG_LL_UART1=y
+CONFIG_PBL_IMAGE=y
+CONFIG_BAUDRATE=57600
+CONFIG_GLOB=y
+CONFIG_HUSH_FANCY_PROMPT=y
+CONFIG_HUSH_GETOPT=y
+CONFIG_CMDLINE_EDITING=y
+CONFIG_AUTO_COMPLETE=y
+# CONFIG_DEFAULT_ENVIRONMENT is not set
+CONFIG_DEBUG_LL=y
+CONFIG_CMD_EDIT=y
+CONFIG_CMD_SLEEP=y
+CONFIG_CMD_LOADB=y
+CONFIG_CMD_LOADY=y
+CONFIG_CMD_LOADS=y
+CONFIG_CMD_SAVES=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_IOMEM=y
+CONFIG_CMD_MD5SUM=y
+CONFIG_CMD_BOOTM_SHOW_TYPE=y
+CONFIG_CMD_BOOTM_VERBOSE=y
+CONFIG_CMD_BOOTM_INITRD=y
+CONFIG_CMD_BOOTM_OFTREE=y
+CONFIG_CMD_BOOTM_OFTREE_UIMAGE=y
+CONFIG_CMD_UIMAGE=y
+CONFIG_CMD_RESET=y
+CONFIG_CMD_POWEROFF=y
+CONFIG_CMD_GO=y
+CONFIG_CMD_OFTREE=y
+CONFIG_CMD_OF_PROPERTY=y
+CONFIG_CMD_OF_NODE=y
+CONFIG_OFDEVICE=y
+# CONFIG_SPI is not set
+CONFIG_SHA1=y
+CONFIG_SHA224=y
+CONFIG_SHA256=y
diff --git a/arch/mips/configs/rzx50_defconfig b/arch/mips/configs/rzx50_defconfig
deleted file mode 100644
index 7691bae..0000000
--- a/arch/mips/configs/rzx50_defconfig
+++ /dev/null
@@ -1,39 +0,0 @@
-CONFIG_BUILTIN_DTB=y
-CONFIG_BUILTIN_DTB_NAME="rzx50"
-CONFIG_MACH_MIPS_XBURST=y
-CONFIG_JZ4750D_DEBUG_LL_UART1=y
-CONFIG_PBL_IMAGE=y
-CONFIG_BAUDRATE=57600
-CONFIG_GLOB=y
-CONFIG_HUSH_FANCY_PROMPT=y
-CONFIG_HUSH_GETOPT=y
-CONFIG_CMDLINE_EDITING=y
-CONFIG_AUTO_COMPLETE=y
-# CONFIG_DEFAULT_ENVIRONMENT is not set
-CONFIG_DEBUG_LL=y
-CONFIG_CMD_EDIT=y
-CONFIG_CMD_SLEEP=y
-CONFIG_CMD_LOADB=y
-CONFIG_CMD_LOADY=y
-CONFIG_CMD_LOADS=y
-CONFIG_CMD_SAVES=y
-CONFIG_CMD_MEMINFO=y
-CONFIG_CMD_IOMEM=y
-CONFIG_CMD_MD5SUM=y
-CONFIG_CMD_BOOTM_SHOW_TYPE=y
-CONFIG_CMD_BOOTM_VERBOSE=y
-CONFIG_CMD_BOOTM_INITRD=y
-CONFIG_CMD_BOOTM_OFTREE=y
-CONFIG_CMD_BOOTM_OFTREE_UIMAGE=y
-CONFIG_CMD_UIMAGE=y
-CONFIG_CMD_RESET=y
-CONFIG_CMD_POWEROFF=y
-CONFIG_CMD_GO=y
-CONFIG_CMD_OFTREE=y
-CONFIG_CMD_OF_PROPERTY=y
-CONFIG_CMD_OF_NODE=y
-CONFIG_OFDEVICE=y
-# CONFIG_SPI is not set
-CONFIG_SHA1=y
-CONFIG_SHA224=y
-CONFIG_SHA256=y
diff --git a/arch/mips/mach-xburst/mach-xburst.dox b/arch/mips/mach-xburst/mach-xburst.dox
index a5e524d..052c05e 100644
--- a/arch/mips/mach-xburst/mach-xburst.dox
+++ b/arch/mips/mach-xburst/mach-xburst.dox
@@ -2,6 +2,6 @@
 
 @section xburst_boards XBurst-based boards
 
- at li @subpage rzx50
+ at li @subpage ritmix-rzx50
 
 */
-- 
1.9.0



From antonynpavlov at gmail.com  Sat Mar 22 07:29:52 2014
From: antonynpavlov at gmail.com (Antony Pavlov)
Date: Sat, 22 Mar 2014 15:29:52 +0400
Subject: [PATCH 2/7] MIPS: dts: rzx50: move jz4755 description to the separate
 file
In-Reply-To: <1395487797-16599-1-git-send-email-antonynpavlov@gmail.com>
References: <1395487797-16599-1-git-send-email-antonynpavlov@gmail.com>
Message-ID: <1395487797-16599-3-git-send-email-antonynpavlov@gmail.com>

Signed-off-by: Antony Pavlov <antonynpavlov at gmail.com>
---
 arch/mips/dts/jz4755.dtsi | 35 +++++++++++++++++++++++++++++++++++
 arch/mips/dts/rzx50.dts   |  8 +++++++-
 2 files changed, 42 insertions(+), 1 deletion(-)

diff --git a/arch/mips/dts/jz4755.dtsi b/arch/mips/dts/jz4755.dtsi
new file mode 100644
index 0000000..44ff912
--- /dev/null
+++ b/arch/mips/dts/jz4755.dtsi
@@ -0,0 +1,35 @@
+#include "skeleton.dtsi"
+
+/ {
+	soc {
+		compatible = "simple-bus";
+		model = "Ingenic JZ4755";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		serial0: serial at b0030000 {
+			compatible = "ingenic,jz4740-uart";
+			reg = <0xb0030000 0x20>;
+			reg-shift = <2>;
+			clock-frequency = <12000000>;
+			status = "disabled";
+		};
+
+		serial1: serial at b0031000 {
+			compatible = "ingenic,jz4740-uart";
+			reg = <0xb0031000 0x20>;
+			reg-shift = <2>;
+			clock-frequency = <12000000>;
+			status = "disabled";
+		};
+
+		serial2: serial at b0032000 {
+			compatible = "ingenic,jz4740-uart";
+			reg = <0xb0032000 0x20>;
+			reg-shift = <2>;
+			clock-frequency = <12000000>;
+			status = "disabled";
+		};
+	};
+};
diff --git a/arch/mips/dts/rzx50.dts b/arch/mips/dts/rzx50.dts
index 69320dd..78103e3 100644
--- a/arch/mips/dts/rzx50.dts
+++ b/arch/mips/dts/rzx50.dts
@@ -1,6 +1,6 @@
 /dts-v1/;
 
-/include/ "skeleton.dtsi"
+#include "jz4755.dtsi"
 
 / {
 	model = "Ritmix RZX-50";
@@ -9,4 +9,10 @@
 	memory {
 		reg = <0x00000000 0x4000000>;
 	};
+
+	soc {
+		serial1: serial at b0031000 {
+			status = "okay";
+		};
+	};
 };
-- 
1.9.0



From antonynpavlov at gmail.com  Sat Mar 22 07:29:51 2014
From: antonynpavlov at gmail.com (Antony Pavlov)
Date: Sat, 22 Mar 2014 15:29:51 +0400
Subject: [PATCH 1/7] MIPS: mach-xburst: fix DEBUG_LL=n build error
In-Reply-To: <1395487797-16599-1-git-send-email-antonynpavlov@gmail.com>
References: <1395487797-16599-1-git-send-email-antonynpavlov@gmail.com>
Message-ID: <1395487797-16599-2-git-send-email-antonynpavlov@gmail.com>

Here is my error log:

  CC      common/startup.o
In file included from arch/mips/mach-xburst/include/mach/debug_ll.h:25,
                 from include/debug_ll.h:31,
                 from common/startup.c:36:
arch/mips/include/asm/debug_ll_ns16550.h: In function 'PUTC_LL':
arch/mips/include/asm/debug_ll_ns16550.h:62: error: 'DEBUG_LL_UART_ADDR' undeclared (first use in this function)
arch/mips/include/asm/debug_ll_ns16550.h:62: error: (Each undeclared identifier is reported only once
arch/mips/include/asm/debug_ll_ns16550.h:62: error: for each function it appears in.)
make[1]: *** [common/startup.o] Error 1

Signed-off-by: Antony Pavlov <antonynpavlov at gmail.com>
---
 arch/mips/include/asm/debug_ll_ns16550.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/mips/include/asm/debug_ll_ns16550.h b/arch/mips/include/asm/debug_ll_ns16550.h
index f36010c..032f0a2 100644
--- a/arch/mips/include/asm/debug_ll_ns16550.h
+++ b/arch/mips/include/asm/debug_ll_ns16550.h
@@ -59,9 +59,11 @@
 
 static __inline__ void PUTC_LL(char ch)
 {
+#ifdef CONFIG_DEBUG_LL
 	while (!(__raw_readb((u8 *)DEBUG_LL_UART_ADDR + UART_LSR) & UART_LSR_THRE))
 		;
 	__raw_writeb(ch, (u8 *)DEBUG_LL_UART_ADDR + UART_THR);
+#endif /* CONFIG_DEBUG_LL */
 }
 #else /* __ASSEMBLY__ */
 /*
-- 
1.9.0



From cristiano_dealti at hotmail.com  Sat Mar 22 12:08:02 2014
From: cristiano_dealti at hotmail.com (Cristiano De Alti)
Date: Sat, 22 Mar 2014 16:08:02 +0000 (UTC)
Subject: i.MX21 ADS NAND flash bad blocks scan. Barebox vs Linux
References: <loom.20140313T212720-896@post.gmane.org>
Message-ID: <loom.20140322T170353-879@post.gmane.org>

Cristiano De Alti <cristiano_dealti at ...> writes:

> This board has a 64MBi Samsung NAND flash that is detected both by Barebox
> (recent snapshot) and Linux 3.4.77.
> 
> The issue is that, while the bad blocks scan takes a negligible time on
> Barebox, it takes 10 minutes to complete on Linux.

I believe the NAND flash is faulty. Mechanically stressing the NAND flash
card seems to speed up BB scan on Linux or detect more bad blocks. I wont's
spend more time on this issue




From vicencb at gmail.com  Sat Mar 22 13:39:04 2014
From: vicencb at gmail.com (Vicente Bergas)
Date: Sat, 22 Mar 2014 17:39:04 +0000
Subject: [PATCH] OMAP4_USBboot: Change output text formatting
Message-ID: <1395509944-1512-1-git-send-email-vicencb@gmail.com>

The basic console used for USBboot has two different formattings,
one for text coming from the host and another for text coming from
the target.
This change makes both formattings readable regardless of the
console background color.

Signed-off-by: Vicente Bergas <vicencb at gmail.com>
---
 scripts/omap4_usbboot/omap4_usbboot.c | 17 +++++++++--------
 1 file changed, 9 insertions(+), 8 deletions(-)

diff --git a/scripts/omap4_usbboot/omap4_usbboot.c b/scripts/omap4_usbboot/omap4_usbboot.c
index e521086..0e5abcb 100644
--- a/scripts/omap4_usbboot/omap4_usbboot.c
+++ b/scripts/omap4_usbboot/omap4_usbboot.c
@@ -35,16 +35,17 @@
 #define WHITE   8
 #define RED     1
 #define BLACK   0
-#define FORMAT        "%c[%d;%d;%dm"
-#define TARGET_FORMAT 0x1B, BRIGHT, RED+30, BLACK+40
-#define HOST_FORMAT   0x1B, RESET, WHITE+30, BLACK+40
-#define host_print(fmt, arg...)	printf(FORMAT fmt FORMAT, \
+#define TFORMAT       "%c[%d;%dm"
+#define HFORMAT       "%c[%dm"
+#define TARGET_FORMAT 0x1B, BRIGHT, RED+30
+#define HOST_FORMAT   0x1B, RESET
+#define host_print(fmt, arg...)	printf(HFORMAT fmt TFORMAT, \
 					HOST_FORMAT, ##arg, TARGET_FORMAT)
 
 void panic(struct termios *t_restore)
 {
 	tcsetattr(STDIN_FILENO, TCSANOW, t_restore);
-	printf(FORMAT, HOST_FORMAT);
+	printf(HFORMAT, HOST_FORMAT);
 	exit(1);
 }
 
@@ -354,7 +355,7 @@ int usb_boot(
 	tcgetattr(STDIN_FILENO, &vars.t_restore);
 	tn = vars.t_restore;
 	tn.c_lflag &= ~(ICANON | ECHO);
-	printf(FORMAT, TARGET_FORMAT);
+	printf(TFORMAT, TARGET_FORMAT);
 	tcsetattr(STDIN_FILENO, TCSANOW, &tn);
 	if (pthread_create(&thread, NULL, listenerTask, &vars))
 		host_print("listenerTask failed\n");
@@ -375,7 +376,7 @@ int usb_boot(
 	usb_close(usb);
 	pthread_mutex_destroy(&vars.usb_mutex);
 	tcsetattr(STDIN_FILENO, TCSANOW, &vars.t_restore);
-	printf(FORMAT, HOST_FORMAT);
+	printf(HFORMAT, HOST_FORMAT);
 	return 0;
 }
 
@@ -415,7 +416,7 @@ int main(int argc, char **argv)
 	sz = s.st_size;
 	close(fd);
 	argv++;
-	printf(FORMAT, HOST_FORMAT);
+	printf(HFORMAT, HOST_FORMAT);
 	for (once = 1;;) {
 		usb = usb_open(match_omap4_bootloader);
 		if (usb)
-- 
1.9.1



From s.hauer at pengutronix.de  Sun Mar 23 04:47:15 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Sun, 23 Mar 2014 09:47:15 +0100
Subject: [PATCH] mtd: ubi: avoid NULL pointer dereference in ubi_get_device
In-Reply-To: <1395235502-27629-1-git-send-email-p.zabel@pengutronix.de>
References: <1395235502-27629-1-git-send-email-p.zabel@pengutronix.de>
Message-ID: <20140323084715.GH17250@pengutronix.de>

On Wed, Mar 19, 2014 at 02:25:02PM +0100, Philipp Zabel wrote:
> If the ubidetach command is given a number that passes the range check
> in ubi_detach_mtd_dev, but at which index the ubi_devices array contains
> a NULL pointer, ubi_get_device tries to dereference this NULL pointer
> to increment the ubi device reference count.
> 
> Signed-off-by: Philipp Zabel <p.zabel at pengutronix.de>

Applied, thanks

Sascha

> ---
>  drivers/mtd/ubi/build.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/mtd/ubi/build.c b/drivers/mtd/ubi/build.c
> index da21f69..b908fcd 100644
> --- a/drivers/mtd/ubi/build.c
> +++ b/drivers/mtd/ubi/build.c
> @@ -104,6 +104,8 @@ struct ubi_device *ubi_get_device(int ubi_num)
>  	struct ubi_device *ubi;
>  
>  	ubi = ubi_devices[ubi_num];
> +	if (!ubi)
> +		return NULL;
>  
>  	ubi->ref_count++;
>  
> -- 
> 1.9.0
> 
> 
> _______________________________________________
> barebox mailing list
> barebox at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/barebox
> 

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From s.hauer at pengutronix.de  Sun Mar 23 04:48:13 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Sun, 23 Mar 2014 09:48:13 +0100
Subject: [PATCH] arm: imx53: qsb: set hostname from board file
In-Reply-To: <1395160185-32125-1-git-send-email-l.stach@pengutronix.de>
References: <1395160185-32125-1-git-send-email-l.stach@pengutronix.de>
Message-ID: <20140323084813.GI17250@pengutronix.de>

On Tue, Mar 18, 2014 at 05:29:45PM +0100, Lucas Stach wrote:
> Otherwise it won't get set in a multiimage build.
> 
> Signed-off-by: Lucas Stach <l.stach at pengutronix.de>

Applied, thanks

Sascha

> ---
>  arch/arm/boards/freescale-mx53-qsb/board.c          | 2 ++
>  arch/arm/boards/freescale-mx53-qsb/env/config-board | 1 -
>  2 files changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm/boards/freescale-mx53-qsb/board.c b/arch/arm/boards/freescale-mx53-qsb/board.c
> index 74826e4a5e43..0553f1c82895 100644
> --- a/arch/arm/boards/freescale-mx53-qsb/board.c
> +++ b/arch/arm/boards/freescale-mx53-qsb/board.c
> @@ -99,6 +99,7 @@ static int loco_late_init(void)
>  		rev = readl(MX53_IIM_BASE_ADDR + 0x878);
>  		set_board_rev(rev);
>  		printf("MCIMX53-START-R board 1.0 rev %c\n", (rev == 1) ? 'A' : 'B' );
> +		barebox_set_hostname("loco-r");
>  		armlinux_set_revision(loco_system_rev);
>  		/* Set VDDGP to 1.25V for 1GHz on SW1 */
>  		mc13xxx_reg_read(mc34708, MC13892_REG_SW_0, &val);
> @@ -146,6 +147,7 @@ static int loco_late_init(void)
>  	} else {
>  		/* so we have a DA9053 based board */
>  		printf("MCIMX53-START board 1.0\n");
> +		barebox_set_hostname("loco");
>  		armlinux_set_revision(loco_system_rev);
>  		return 0;
>  	}
> diff --git a/arch/arm/boards/freescale-mx53-qsb/env/config-board b/arch/arm/boards/freescale-mx53-qsb/env/config-board
> index a6cf69ddbc7f..e8e8378f53f5 100644
> --- a/arch/arm/boards/freescale-mx53-qsb/env/config-board
> +++ b/arch/arm/boards/freescale-mx53-qsb/env/config-board
> @@ -3,5 +3,4 @@
>  # board defaults, do not change in running system. Change /env/config
>  # instead
>  
> -global.hostname=loco
>  global.linux.bootargs.base="console=ttymxc0,115200"
> -- 
> 1.9.0
> 
> 
> _______________________________________________
> barebox mailing list
> barebox at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/barebox
> 

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From s.hauer at pengutronix.de  Mon Mar 24 02:45:31 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Mon, 24 Mar 2014 07:45:31 +0100
Subject: [PATCH 4/7] serial: ns16550: add compatible entry for "ingenic,
 jz4740-uart"
In-Reply-To: <1395487797-16599-5-git-send-email-antonynpavlov@gmail.com>
References: <1395487797-16599-1-git-send-email-antonynpavlov@gmail.com>
 <1395487797-16599-5-git-send-email-antonynpavlov@gmail.com>
Message-ID: <20140324064531.GJ17250@pengutronix.de>

On Sat, Mar 22, 2014 at 03:29:54PM +0400, Antony Pavlov wrote:
> Signed-off-by: Antony Pavlov <antonynpavlov at gmail.com>
> ---
>  drivers/serial/serial_ns16550.c | 30 ++++++++++++++++++++++++++++++
>  1 file changed, 30 insertions(+)
> 
> diff --git a/drivers/serial/serial_ns16550.c b/drivers/serial/serial_ns16550.c
> index aa0992f..7130871 100644
> --- a/drivers/serial/serial_ns16550.c
> +++ b/drivers/serial/serial_ns16550.c
> @@ -257,6 +257,30 @@ static __maybe_unused struct ns16550_drvdata omap_drvdata = {
>  	.linux_console_name = "ttyO",
>  };
>  
> +#define JZ_UART_SHIFT	2
> +
> +static void jz_serial_reg_write(unsigned int val, unsigned long base,
> +	unsigned char reg_offset)
> +{
> +	switch (reg_offset) {
> +	case (fcr << JZ_UART_SHIFT):
> +		val |= 0x10; /* Enable uart module */
> +		break;

You could also do this by overwriting .init_port.

> +	case (ier << JZ_UART_SHIFT):
> +		val |= (val & 0x4) << 2;

What does this bit do?

Putting driver logic into the register writes is not good. Where this
leads to can be seen in drivers/mmc/host/sdhci-esdhc-imx.c in the
kernel. Could we make fcrval overwritable in drvdata? Or just special
case the fcr register access in ns16550_setbaudrate?

Sascha


-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From s.hauer at pengutronix.de  Mon Mar 24 02:59:14 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Mon, 24 Mar 2014 07:59:14 +0100
Subject: [PATCH] OMAP4_USBboot: Change output text formatting
In-Reply-To: <1395509944-1512-1-git-send-email-vicencb@gmail.com>
References: <1395509944-1512-1-git-send-email-vicencb@gmail.com>
Message-ID: <20140324065914.GK17250@pengutronix.de>

On Sat, Mar 22, 2014 at 05:39:04PM +0000, Vicente Bergas wrote:
> The basic console used for USBboot has two different formattings,
> one for text coming from the host and another for text coming from
> the target.
> This change makes both formattings readable regardless of the
> console background color.
> 
> Signed-off-by: Vicente Bergas <vicencb at gmail.com>

Applied, thanks

Sascha

> ---
>  scripts/omap4_usbboot/omap4_usbboot.c | 17 +++++++++--------
>  1 file changed, 9 insertions(+), 8 deletions(-)
> 
> diff --git a/scripts/omap4_usbboot/omap4_usbboot.c b/scripts/omap4_usbboot/omap4_usbboot.c
> index e521086..0e5abcb 100644
> --- a/scripts/omap4_usbboot/omap4_usbboot.c
> +++ b/scripts/omap4_usbboot/omap4_usbboot.c
> @@ -35,16 +35,17 @@
>  #define WHITE   8
>  #define RED     1
>  #define BLACK   0
> -#define FORMAT        "%c[%d;%d;%dm"
> -#define TARGET_FORMAT 0x1B, BRIGHT, RED+30, BLACK+40
> -#define HOST_FORMAT   0x1B, RESET, WHITE+30, BLACK+40
> -#define host_print(fmt, arg...)	printf(FORMAT fmt FORMAT, \
> +#define TFORMAT       "%c[%d;%dm"
> +#define HFORMAT       "%c[%dm"
> +#define TARGET_FORMAT 0x1B, BRIGHT, RED+30
> +#define HOST_FORMAT   0x1B, RESET
> +#define host_print(fmt, arg...)	printf(HFORMAT fmt TFORMAT, \
>  					HOST_FORMAT, ##arg, TARGET_FORMAT)
>  
>  void panic(struct termios *t_restore)
>  {
>  	tcsetattr(STDIN_FILENO, TCSANOW, t_restore);
> -	printf(FORMAT, HOST_FORMAT);
> +	printf(HFORMAT, HOST_FORMAT);
>  	exit(1);
>  }
>  
> @@ -354,7 +355,7 @@ int usb_boot(
>  	tcgetattr(STDIN_FILENO, &vars.t_restore);
>  	tn = vars.t_restore;
>  	tn.c_lflag &= ~(ICANON | ECHO);
> -	printf(FORMAT, TARGET_FORMAT);
> +	printf(TFORMAT, TARGET_FORMAT);
>  	tcsetattr(STDIN_FILENO, TCSANOW, &tn);
>  	if (pthread_create(&thread, NULL, listenerTask, &vars))
>  		host_print("listenerTask failed\n");
> @@ -375,7 +376,7 @@ int usb_boot(
>  	usb_close(usb);
>  	pthread_mutex_destroy(&vars.usb_mutex);
>  	tcsetattr(STDIN_FILENO, TCSANOW, &vars.t_restore);
> -	printf(FORMAT, HOST_FORMAT);
> +	printf(HFORMAT, HOST_FORMAT);
>  	return 0;
>  }
>  
> @@ -415,7 +416,7 @@ int main(int argc, char **argv)
>  	sz = s.st_size;
>  	close(fd);
>  	argv++;
> -	printf(FORMAT, HOST_FORMAT);
> +	printf(HFORMAT, HOST_FORMAT);
>  	for (once = 1;;) {
>  		usb = usb_open(match_omap4_bootloader);
>  		if (usb)
> -- 
> 1.9.1
> 
> 
> _______________________________________________
> barebox mailing list
> barebox at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/barebox
> 

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From M.Stam at fugro.nl  Mon Mar 24 05:37:48 2014
From: M.Stam at fugro.nl (Stam, Michel [FINT])
Date: Mon, 24 Mar 2014 10:37:48 +0100
Subject: Barebox x86 IDE support
Message-ID: <C89EFD3CD56F64468D3D206D683A8D2203154121@ldam-msx2.fugro-nl.local>

Hello maintainers,

I was wondering if one of you has had time to verify these patches and apply them to trunk?

Kind regards,

Michel Stam

--

From: Stam, Michel [FINT] 
Sent: Friday, March 14, 2014 17:31 PM
To: 'barebox at lists.infradead.org'
Subject: Barebox x86 IDE support

Dear list,

While working on barebox recently, I decided to port a couple of patches ?I made to an old barebox tree a few years ago, to fix the IDE ports on the x86 platform.

I had to work on the resource allocation a bit, as the current GIT repository does not allow IORESOURCE_IO type to be passed to dev_request_region( ) and friends. I tried to keep the interface the same as much as possible by using macros etc.
Please find that attached in 0001-common-driver-Allow-for-I-O-mapped-I-O-in-resource-r.patch. 

Next, I added support to the platform IDE interface to use I/O-mapped I/O, and added the necessary allocation to the generic_pc board.

I did have to add a call to ata_port_detect( ) to ide_port_register to actually get the drives to be probed. Without it the interface seems to be stuck in some sort of limbo. This patch is in 0002-x86-Add-support-for-IDE-on-the-legacy-I-O-ports.patch.

Lastly, I added an extra serial port to the generic_pc board. Most (legacy) PCs have support for 2 serial ports, it seemed useful to me.

What does puzzle me is that the arch/x86/boot/Kconfig mentions X86_VESA and X86_VGA support, but the files (console_vga.c and console_vesa.c) do not nor have ever existed. Is this a remnant from U-boot v1?

Best regards,

Michel Stam


From antonynpavlov at gmail.com  Mon Mar 24 16:23:30 2014
From: antonynpavlov at gmail.com (Antony Pavlov)
Date: Tue, 25 Mar 2014 00:23:30 +0400
Subject: [PATCH 4/7] serial: ns16550: add compatible entry for
 "ingenic, jz4740-uart"
In-Reply-To: <20140324064531.GJ17250@pengutronix.de>
References: <1395487797-16599-1-git-send-email-antonynpavlov@gmail.com>
 <1395487797-16599-5-git-send-email-antonynpavlov@gmail.com>
 <20140324064531.GJ17250@pengutronix.de>
Message-ID: <20140325002330.48d4fac7fcb327f0c0a418cb@gmail.com>

On Mon, 24 Mar 2014 07:45:31 +0100
Sascha Hauer <s.hauer at pengutronix.de> wrote:

> On Sat, Mar 22, 2014 at 03:29:54PM +0400, Antony Pavlov wrote:
> > Signed-off-by: Antony Pavlov <antonynpavlov at gmail.com>
> > ---
> >  drivers/serial/serial_ns16550.c | 30 ++++++++++++++++++++++++++++++
> >  1 file changed, 30 insertions(+)
> > 
> > diff --git a/drivers/serial/serial_ns16550.c b/drivers/serial/serial_ns16550.c
> > index aa0992f..7130871 100644
> > --- a/drivers/serial/serial_ns16550.c
> > +++ b/drivers/serial/serial_ns16550.c
> > @@ -257,6 +257,30 @@ static __maybe_unused struct ns16550_drvdata omap_drvdata = {
> >  	.linux_console_name = "ttyO",
> >  };
> >  
> > +#define JZ_UART_SHIFT	2
> > +
> > +static void jz_serial_reg_write(unsigned int val, unsigned long base,
> > +	unsigned char reg_offset)
> > +{
> > +	switch (reg_offset) {
> > +	case (fcr << JZ_UART_SHIFT):
> > +		val |= 0x10; /* Enable uart module */
> > +		break;
> 
> You could also do this by overwriting .init_port.

I'll do so.
 
> > +	case (ier << JZ_UART_SHIFT):
> > +		val |= (val & 0x4) << 2;
> 
> What does this bit do?

It's non-standard Ingenic-specific 'Receive Timeout Interrupt Enable' bit.
We can simply drop it as we use 'ns16550_write(cdev, 0x00, ier);' for ier initialization.

> 
> Putting driver logic into the register writes is not good. Where this
> leads to can be seen in drivers/mmc/host/sdhci-esdhc-imx.c in the
> kernel. Could we make fcrval overwritable in drvdata? Or just special
> case the fcr register access in ns16550_setbaudrate?

Please see v2 patchseries.

--?
Best regards,
? Antony Pavlov


From antonynpavlov at gmail.com  Mon Mar 24 16:13:46 2014
From: antonynpavlov at gmail.com (Antony Pavlov)
Date: Tue, 25 Mar 2014 00:13:46 +0400
Subject: [PATCH v2 0/8] MIPS: improve Ingenic JZ4755 device tree support
Message-ID: <1395692034-5821-1-git-send-email-antonynpavlov@gmail.com>

This patcheseries moves Ingenic JZ4755 UART initialization
into device tree and makes JZ4755 device tree organization
more clear.

This patchseries is a part of work on Ingenic chips support
and prepares MIPS board support switch to device tree.
Next patchseries will add device tree Ingenic gpio, clk
and pinctls support.

Changes since v1:
  * use "make FCR setup value part of struct ns16550_priv"
    instead of "make it possible to get reg_write() from devtype";
  * add a trivial "fix whitespaces" patch.


Antony Pavlov (8):
  MIPS: mach-xburst: fix DEBUG_LL=n build error
  MIPS: dts: rzx50: move jz4755 description to the separate file
  serial: ns16550: fix whitespaces
  serial: ns16550: make FCR setup value part of struct ns16550_priv
  serial: ns16550: add compatible entry for "ingenic,jz4740-uart"
  MIPS: rzx50: drop console initialization in board code
  MIPS: mach-xburst: drop serial.c
  MIPS: boards: rename rzx50 -> ritmix-rzx50

 Documentation/boards.dox                           |  2 +-
 arch/mips/Makefile                                 |  2 +-
 arch/mips/boards/ritmix-rzx50/Makefile             |  1 +
 .../ritmix-rzx50/include/board/board_pbl_start.h   | 43 ++++++++++++++++
 .../boards/ritmix-rzx50/include/board/debug_ll.h   | 23 +++++++++
 arch/mips/boards/ritmix-rzx50/ritmix-rzx50.dox     | 46 +++++++++++++++++
 arch/mips/boards/ritmix-rzx50/serial.c             | 27 ++++++++++
 arch/mips/boards/rzx50/Makefile                    |  1 -
 .../boards/rzx50/include/board/board_pbl_start.h   | 43 ----------------
 arch/mips/boards/rzx50/include/board/debug_ll.h    | 23 ---------
 arch/mips/boards/rzx50/rzx50.dox                   | 46 -----------------
 arch/mips/boards/rzx50/serial.c                    | 32 ------------
 arch/mips/configs/ritmix-rzx50_defconfig           | 39 ++++++++++++++
 arch/mips/configs/rzx50_defconfig                  | 39 --------------
 arch/mips/dts/jz4755.dtsi                          | 35 +++++++++++++
 arch/mips/dts/rzx50.dts                            |  8 ++-
 arch/mips/include/asm/debug_ll_ns16550.h           |  2 +
 arch/mips/mach-xburst/Makefile                     |  1 -
 arch/mips/mach-xburst/mach-xburst.dox              |  2 +-
 arch/mips/mach-xburst/serial.c                     | 60 ----------------------
 drivers/serial/serial_ns16550.c                    | 35 ++++++++++---
 21 files changed, 254 insertions(+), 256 deletions(-)
 create mode 100644 arch/mips/boards/ritmix-rzx50/Makefile
 create mode 100644 arch/mips/boards/ritmix-rzx50/include/board/board_pbl_start.h
 create mode 100644 arch/mips/boards/ritmix-rzx50/include/board/debug_ll.h
 create mode 100644 arch/mips/boards/ritmix-rzx50/ritmix-rzx50.dox
 create mode 100644 arch/mips/boards/ritmix-rzx50/serial.c
 delete mode 100644 arch/mips/boards/rzx50/Makefile
 delete mode 100644 arch/mips/boards/rzx50/include/board/board_pbl_start.h
 delete mode 100644 arch/mips/boards/rzx50/include/board/debug_ll.h
 delete mode 100644 arch/mips/boards/rzx50/rzx50.dox
 delete mode 100644 arch/mips/boards/rzx50/serial.c
 create mode 100644 arch/mips/configs/ritmix-rzx50_defconfig
 delete mode 100644 arch/mips/configs/rzx50_defconfig
 create mode 100644 arch/mips/dts/jz4755.dtsi
 delete mode 100644 arch/mips/mach-xburst/serial.c

-- 
1.9.0



From antonynpavlov at gmail.com  Mon Mar 24 16:13:47 2014
From: antonynpavlov at gmail.com (Antony Pavlov)
Date: Tue, 25 Mar 2014 00:13:47 +0400
Subject: [PATCH v2 1/8] MIPS: mach-xburst: fix DEBUG_LL=n build error
In-Reply-To: <1395692034-5821-1-git-send-email-antonynpavlov@gmail.com>
References: <1395692034-5821-1-git-send-email-antonynpavlov@gmail.com>
Message-ID: <1395692034-5821-2-git-send-email-antonynpavlov@gmail.com>

Here is my error log:

  CC      common/startup.o
In file included from arch/mips/mach-xburst/include/mach/debug_ll.h:25,
                 from include/debug_ll.h:31,
                 from common/startup.c:36:
arch/mips/include/asm/debug_ll_ns16550.h: In function 'PUTC_LL':
arch/mips/include/asm/debug_ll_ns16550.h:62: error: 'DEBUG_LL_UART_ADDR' undeclared (first use in this function)
arch/mips/include/asm/debug_ll_ns16550.h:62: error: (Each undeclared identifier is reported only once
arch/mips/include/asm/debug_ll_ns16550.h:62: error: for each function it appears in.)
make[1]: *** [common/startup.o] Error 1

Signed-off-by: Antony Pavlov <antonynpavlov at gmail.com>
---
 arch/mips/include/asm/debug_ll_ns16550.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/mips/include/asm/debug_ll_ns16550.h b/arch/mips/include/asm/debug_ll_ns16550.h
index f36010c..032f0a2 100644
--- a/arch/mips/include/asm/debug_ll_ns16550.h
+++ b/arch/mips/include/asm/debug_ll_ns16550.h
@@ -59,9 +59,11 @@
 
 static __inline__ void PUTC_LL(char ch)
 {
+#ifdef CONFIG_DEBUG_LL
 	while (!(__raw_readb((u8 *)DEBUG_LL_UART_ADDR + UART_LSR) & UART_LSR_THRE))
 		;
 	__raw_writeb(ch, (u8 *)DEBUG_LL_UART_ADDR + UART_THR);
+#endif /* CONFIG_DEBUG_LL */
 }
 #else /* __ASSEMBLY__ */
 /*
-- 
1.9.0



From antonynpavlov at gmail.com  Mon Mar 24 16:13:48 2014
From: antonynpavlov at gmail.com (Antony Pavlov)
Date: Tue, 25 Mar 2014 00:13:48 +0400
Subject: [PATCH v2 2/8] MIPS: dts: rzx50: move jz4755 description to the
 separate file
In-Reply-To: <1395692034-5821-1-git-send-email-antonynpavlov@gmail.com>
References: <1395692034-5821-1-git-send-email-antonynpavlov@gmail.com>
Message-ID: <1395692034-5821-3-git-send-email-antonynpavlov@gmail.com>

Signed-off-by: Antony Pavlov <antonynpavlov at gmail.com>
---
 arch/mips/dts/jz4755.dtsi | 35 +++++++++++++++++++++++++++++++++++
 arch/mips/dts/rzx50.dts   |  8 +++++++-
 2 files changed, 42 insertions(+), 1 deletion(-)

diff --git a/arch/mips/dts/jz4755.dtsi b/arch/mips/dts/jz4755.dtsi
new file mode 100644
index 0000000..44ff912
--- /dev/null
+++ b/arch/mips/dts/jz4755.dtsi
@@ -0,0 +1,35 @@
+#include "skeleton.dtsi"
+
+/ {
+	soc {
+		compatible = "simple-bus";
+		model = "Ingenic JZ4755";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		serial0: serial at b0030000 {
+			compatible = "ingenic,jz4740-uart";
+			reg = <0xb0030000 0x20>;
+			reg-shift = <2>;
+			clock-frequency = <12000000>;
+			status = "disabled";
+		};
+
+		serial1: serial at b0031000 {
+			compatible = "ingenic,jz4740-uart";
+			reg = <0xb0031000 0x20>;
+			reg-shift = <2>;
+			clock-frequency = <12000000>;
+			status = "disabled";
+		};
+
+		serial2: serial at b0032000 {
+			compatible = "ingenic,jz4740-uart";
+			reg = <0xb0032000 0x20>;
+			reg-shift = <2>;
+			clock-frequency = <12000000>;
+			status = "disabled";
+		};
+	};
+};
diff --git a/arch/mips/dts/rzx50.dts b/arch/mips/dts/rzx50.dts
index 69320dd..78103e3 100644
--- a/arch/mips/dts/rzx50.dts
+++ b/arch/mips/dts/rzx50.dts
@@ -1,6 +1,6 @@
 /dts-v1/;
 
-/include/ "skeleton.dtsi"
+#include "jz4755.dtsi"
 
 / {
 	model = "Ritmix RZX-50";
@@ -9,4 +9,10 @@
 	memory {
 		reg = <0x00000000 0x4000000>;
 	};
+
+	soc {
+		serial1: serial at b0031000 {
+			status = "okay";
+		};
+	};
 };
-- 
1.9.0



From antonynpavlov at gmail.com  Mon Mar 24 16:13:49 2014
From: antonynpavlov at gmail.com (Antony Pavlov)
Date: Tue, 25 Mar 2014 00:13:49 +0400
Subject: [PATCH v2 3/8] serial: ns16550: fix whitespaces
In-Reply-To: <1395692034-5821-1-git-send-email-antonynpavlov@gmail.com>
References: <1395692034-5821-1-git-send-email-antonynpavlov@gmail.com>
Message-ID: <1395692034-5821-4-git-send-email-antonynpavlov@gmail.com>

Signed-off-by: Antony Pavlov <antonynpavlov at gmail.com>
---
 drivers/serial/serial_ns16550.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/serial/serial_ns16550.c b/drivers/serial/serial_ns16550.c
index f1da44b..d217014 100644
--- a/drivers/serial/serial_ns16550.c
+++ b/drivers/serial/serial_ns16550.c
@@ -192,7 +192,7 @@ static void ns16550_omap_init_port(struct console_device *cdev)
 	ns16550_serial_init_port(cdev);
 
 	ns16550_write(cdev, 0x07, omap_mdr1);	/* Disable */
-	ns16550_write(cdev, 0x00,  omap_mdr1);
+	ns16550_write(cdev, 0x00, omap_mdr1);
 }
 
 /*********** Exposed Functions **********************************/
-- 
1.9.0



From antonynpavlov at gmail.com  Mon Mar 24 16:13:50 2014
From: antonynpavlov at gmail.com (Antony Pavlov)
Date: Tue, 25 Mar 2014 00:13:50 +0400
Subject: [PATCH v2 4/8] serial: ns16550: make FCR setup value part of struct
 ns16550_priv
In-Reply-To: <1395692034-5821-1-git-send-email-antonynpavlov@gmail.com>
References: <1395692034-5821-1-git-send-email-antonynpavlov@gmail.com>
Message-ID: <1395692034-5821-5-git-send-email-antonynpavlov@gmail.com>

Signed-off-by: Antony Pavlov <antonynpavlov at gmail.com>
---
 drivers/serial/serial_ns16550.c | 13 +++++++------
 1 file changed, 7 insertions(+), 6 deletions(-)

diff --git a/drivers/serial/serial_ns16550.c b/drivers/serial/serial_ns16550.c
index d217014..0089a04 100644
--- a/drivers/serial/serial_ns16550.c
+++ b/drivers/serial/serial_ns16550.c
@@ -48,6 +48,7 @@ struct ns16550_priv {
 	struct NS16550_plat plat;
 	int access_width;
 	struct clk *clk;
+	uint32_t fcrval;
 };
 
 static inline struct ns16550_priv *to_ns16550_priv(struct console_device *cdev)
@@ -157,18 +158,13 @@ static int ns16550_setbaudrate(struct console_device *cdev, int baud_rate)
 {
 	unsigned int baud_divisor = ns16550_calc_divisor(cdev, baud_rate);
 	struct ns16550_priv *priv = to_ns16550_priv(cdev);
-	struct NS16550_plat *plat = &priv->plat;
 
 	ns16550_write(cdev, LCR_BKSE, lcr);
 	ns16550_write(cdev, baud_divisor & 0xff, dll);
 	ns16550_write(cdev, (baud_divisor >> 8) & 0xff, dlm);
 	ns16550_write(cdev, LCRVAL, lcr);
 	ns16550_write(cdev, MCRVAL, mcr);
-
-	if (plat->flags & NS16650_FLAG_DISABLE_FIFO)
-		ns16550_write(cdev, FCRVAL & ~FCR_FIFO_EN, fcr);
-	else
-		ns16550_write(cdev, FCRVAL, fcr);
+	ns16550_write(cdev, priv->fcrval, fcr);
 
 	return 0;
 }
@@ -316,6 +312,11 @@ static int ns16550_probe(struct device_d *dev)
 	cdev->setbrg = ns16550_setbaudrate;
 	cdev->linux_console_name = devtype->linux_console_name;
 
+	if (plat->flags & NS16650_FLAG_DISABLE_FIFO)
+		priv->fcrval = FCRVAL & ~FCR_FIFO_EN;
+	else
+		priv->fcrval = FCRVAL;
+
 	devtype->init_port(cdev);
 
 	return console_register(cdev);
-- 
1.9.0



From antonynpavlov at gmail.com  Mon Mar 24 16:13:51 2014
From: antonynpavlov at gmail.com (Antony Pavlov)
Date: Tue, 25 Mar 2014 00:13:51 +0400
Subject: [PATCH v2 5/8] serial: ns16550: add compatible entry for "ingenic,
 jz4740-uart"
In-Reply-To: <1395692034-5821-1-git-send-email-antonynpavlov@gmail.com>
References: <1395692034-5821-1-git-send-email-antonynpavlov@gmail.com>
Message-ID: <1395692034-5821-6-git-send-email-antonynpavlov@gmail.com>

Signed-off-by: Antony Pavlov <antonynpavlov at gmail.com>
---
 drivers/serial/serial_ns16550.c | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/drivers/serial/serial_ns16550.c b/drivers/serial/serial_ns16550.c
index 0089a04..a37ac69 100644
--- a/drivers/serial/serial_ns16550.c
+++ b/drivers/serial/serial_ns16550.c
@@ -191,6 +191,16 @@ static void ns16550_omap_init_port(struct console_device *cdev)
 	ns16550_write(cdev, 0x00, omap_mdr1);
 }
 
+#define JZ_FCR_UME 0x10 /* Uart Module Enable */
+
+static void ns16550_jz_init_port(struct console_device *cdev)
+{
+	struct ns16550_priv *priv = to_ns16550_priv(cdev);
+
+	priv->fcrval |= JZ_FCR_UME;
+	ns16550_serial_init_port(cdev);
+}
+
 /*********** Exposed Functions **********************************/
 
 /**
@@ -251,6 +261,10 @@ static __maybe_unused struct ns16550_drvdata omap_drvdata = {
 	.linux_console_name = "ttyO",
 };
 
+static __maybe_unused struct ns16550_drvdata jz_drvdata = {
+	.init_port = ns16550_jz_init_port,
+};
+
 /**
  * @brief Probe entry point -called on the first match for device
  *
@@ -347,6 +361,12 @@ static struct of_device_id ns16550_serial_dt_ids[] = {
 		.data = (unsigned long)&omap_drvdata,
 	},
 #endif
+#if IS_ENABLED(CONFIG_MACH_MIPS_XBURST)
+	{
+		.compatible = "ingenic,jz4740-uart",
+		.data = (unsigned long)&jz_drvdata,
+	},
+#endif
 	{
 		/* sentinel */
 	},
-- 
1.9.0



From antonynpavlov at gmail.com  Mon Mar 24 16:13:52 2014
From: antonynpavlov at gmail.com (Antony Pavlov)
Date: Tue, 25 Mar 2014 00:13:52 +0400
Subject: [PATCH v2 6/8] MIPS: rzx50: drop console initialization in board code
In-Reply-To: <1395692034-5821-1-git-send-email-antonynpavlov@gmail.com>
References: <1395692034-5821-1-git-send-email-antonynpavlov@gmail.com>
Message-ID: <1395692034-5821-7-git-send-email-antonynpavlov@gmail.com>

Signed-off-by: Antony Pavlov <antonynpavlov at gmail.com>
---
 arch/mips/boards/rzx50/Makefile | 2 +-
 arch/mips/boards/rzx50/serial.c | 9 ++-------
 2 files changed, 3 insertions(+), 8 deletions(-)

diff --git a/arch/mips/boards/rzx50/Makefile b/arch/mips/boards/rzx50/Makefile
index ff1a655..31c0629 100644
--- a/arch/mips/boards/rzx50/Makefile
+++ b/arch/mips/boards/rzx50/Makefile
@@ -1 +1 @@
-obj-$(CONFIG_DRIVER_SERIAL_NS16550) += serial.o
+obj-y += serial.o
diff --git a/arch/mips/boards/rzx50/serial.c b/arch/mips/boards/rzx50/serial.c
index 566356a..f1e8da0 100644
--- a/arch/mips/boards/rzx50/serial.c
+++ b/arch/mips/boards/rzx50/serial.c
@@ -17,16 +17,11 @@
 
 #include <common.h>
 #include <init.h>
-#include <mach/devices.h>
-#include <mach/jz4750d_regs.h>
 
-static int rzx50_console_init(void)
+static int rzx50_hostname_init(void)
 {
 	barebox_set_hostname("rzx50");
 
-	/* Register the serial port */
-	jz_add_uart(DEVICE_ID_DYNAMIC, UART1_BASE, 12000000);
-
 	return 0;
 }
-console_initcall(rzx50_console_init);
+console_initcall(rzx50_hostname_init);
-- 
1.9.0



From antonynpavlov at gmail.com  Mon Mar 24 16:13:53 2014
From: antonynpavlov at gmail.com (Antony Pavlov)
Date: Tue, 25 Mar 2014 00:13:53 +0400
Subject: [PATCH v2 7/8] MIPS: mach-xburst: drop serial.c
In-Reply-To: <1395692034-5821-1-git-send-email-antonynpavlov@gmail.com>
References: <1395692034-5821-1-git-send-email-antonynpavlov@gmail.com>
Message-ID: <1395692034-5821-8-git-send-email-antonynpavlov@gmail.com>

We use dts for serial port initialization,
so we have no need in mach-xburst/serial.c anymore.

Signed-off-by: Antony Pavlov <antonynpavlov at gmail.com>
---
 arch/mips/mach-xburst/Makefile |  1 -
 arch/mips/mach-xburst/serial.c | 60 ------------------------------------------
 2 files changed, 61 deletions(-)

diff --git a/arch/mips/mach-xburst/Makefile b/arch/mips/mach-xburst/Makefile
index 3e0cd73..e5634ba 100644
--- a/arch/mips/mach-xburst/Makefile
+++ b/arch/mips/mach-xburst/Makefile
@@ -1,2 +1 @@
-obj-y += serial.o
 obj-$(CONFIG_CPU_JZ4755) += csrc-jz4750.o reset-jz4750.o
diff --git a/arch/mips/mach-xburst/serial.c b/arch/mips/mach-xburst/serial.c
deleted file mode 100644
index acf5648..0000000
--- a/arch/mips/mach-xburst/serial.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- * Copyright (C) 2013 Antony Pavlov <antonynpavlov at gmail.com>
- *
- * Based on the linux kernel JZ4740 serial support:
- * Copyright (C) 2010, Lars-Peter Clausen <lars at metafoo.de>
- *
- * This file is part of barebox.
- * See file CREDITS for list of people who contributed to this project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2
- * as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <common.h>
-#include <ns16550.h>
-#include <io.h>
-#include <mach/devices.h>
-
-#define JZ_UART_SHIFT	2
-
-#define ier		(1 << JZ_UART_SHIFT)
-#define fcr		(2 << JZ_UART_SHIFT)
-
-static void jz_serial_reg_write(unsigned int val, unsigned long base,
-	unsigned char reg_offset)
-{
-	switch (reg_offset) {
-	case fcr:
-		val |= 0x10; /* Enable uart module */
-		break;
-	case ier:
-		val |= (val & 0x4) << 2;
-		break;
-	default:
-		break;
-	}
-
-	writeb(val & 0xff, (void *)(base + reg_offset));
-}
-
-struct device_d *jz_add_uart(int id, unsigned long base, unsigned int clock)
-{
-	struct NS16550_plat *serial_plat;
-
-	serial_plat = xzalloc(sizeof(*serial_plat));
-
-	serial_plat->shift = JZ_UART_SHIFT;
-	serial_plat->reg_write = &jz_serial_reg_write;
-	serial_plat->clock = clock;
-
-	return add_ns16550_device(id, base, 8 << JZ_UART_SHIFT,
-			IORESOURCE_MEM_8BIT, serial_plat);
-}
-- 
1.9.0



From antonynpavlov at gmail.com  Mon Mar 24 16:13:54 2014
From: antonynpavlov at gmail.com (Antony Pavlov)
Date: Tue, 25 Mar 2014 00:13:54 +0400
Subject: [PATCH v2 8/8] MIPS: boards: rename rzx50 -> ritmix-rzx50
In-Reply-To: <1395692034-5821-1-git-send-email-antonynpavlov@gmail.com>
References: <1395692034-5821-1-git-send-email-antonynpavlov@gmail.com>
Message-ID: <1395692034-5821-9-git-send-email-antonynpavlov@gmail.com>

All MIPS board use <vendor>-<model> name template save Ritmix RZX-50.
This commit fixes this inconsistency.

Signed-off-by: Antony Pavlov <antonynpavlov at gmail.com>
---
 Documentation/boards.dox                           |  2 +-
 arch/mips/Makefile                                 |  2 +-
 arch/mips/boards/ritmix-rzx50/Makefile             |  1 +
 .../ritmix-rzx50/include/board/board_pbl_start.h   | 43 ++++++++++++++++++++
 .../boards/ritmix-rzx50/include/board/debug_ll.h   | 23 +++++++++++
 arch/mips/boards/ritmix-rzx50/ritmix-rzx50.dox     | 46 ++++++++++++++++++++++
 arch/mips/boards/ritmix-rzx50/serial.c             | 27 +++++++++++++
 arch/mips/boards/rzx50/Makefile                    |  1 -
 .../boards/rzx50/include/board/board_pbl_start.h   | 43 --------------------
 arch/mips/boards/rzx50/include/board/debug_ll.h    | 23 -----------
 arch/mips/boards/rzx50/rzx50.dox                   | 46 ----------------------
 arch/mips/boards/rzx50/serial.c                    | 27 -------------
 arch/mips/configs/ritmix-rzx50_defconfig           | 39 ++++++++++++++++++
 arch/mips/configs/rzx50_defconfig                  | 39 ------------------
 arch/mips/mach-xburst/mach-xburst.dox              |  2 +-
 15 files changed, 182 insertions(+), 182 deletions(-)

diff --git a/Documentation/boards.dox b/Documentation/boards.dox
index 9a14aee..42bc5e6 100644
--- a/Documentation/boards.dox
+++ b/Documentation/boards.dox
@@ -59,7 +59,7 @@ MIPS type:
 @li @subpage dlink_dir_320
 @li @subpage loongson_ls1b
 @li @subpage qemu_malta
- at li @subpage rzx50
+ at li @subpage ritmix-rzx50
 
 */
 
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 8986fcf..e3d65c8 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -85,7 +85,7 @@ machine-$(CONFIG_MACH_MIPS_LOONGSON)	:= loongson
 board-$(CONFIG_BOARD_LOONGSON_TECH_LS1B)	:= loongson-ls1b
 
 machine-$(CONFIG_MACH_MIPS_XBURST)	:= xburst
-board-$(CONFIG_BOARD_RZX50)	:= rzx50
+board-$(CONFIG_BOARD_RZX50)	:= ritmix-rzx50
 
 machdirs := $(patsubst %,arch/mips/mach-%/,$(machine-y))
 
diff --git a/arch/mips/boards/ritmix-rzx50/Makefile b/arch/mips/boards/ritmix-rzx50/Makefile
new file mode 100644
index 0000000..31c0629
--- /dev/null
+++ b/arch/mips/boards/ritmix-rzx50/Makefile
@@ -0,0 +1 @@
+obj-y += serial.o
diff --git a/arch/mips/boards/ritmix-rzx50/include/board/board_pbl_start.h b/arch/mips/boards/ritmix-rzx50/include/board/board_pbl_start.h
new file mode 100644
index 0000000..fb914d9
--- /dev/null
+++ b/arch/mips/boards/ritmix-rzx50/include/board/board_pbl_start.h
@@ -0,0 +1,43 @@
+/*
+ * Startup Code for Ritmix RZX-50 board
+ *
+ * Copyright (C) 2013 Antony Pavlov <antonynpavlov at gmail.com>
+ *
+ * This file is part of barebox.
+ * See file CREDITS for list of people who contributed to this project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <asm/pbl_macros.h>
+#include <mach/debug_ll.h>
+#include <asm/pbl_nmon.h>
+
+	.macro	board_pbl_start
+	.set	push
+	.set	noreorder
+
+	mips_disable_interrupts
+
+	/* CPU/SoC specific setup ... */
+	/* ... absent */
+
+	debug_ll_ns16550_init
+
+	debug_ll_ns16550_outc '.'
+	debug_ll_ns16550_outnl
+
+	mips_nmon
+
+	copy_to_link_location	pbl_start
+
+	.set	pop
+	.endm
diff --git a/arch/mips/boards/ritmix-rzx50/include/board/debug_ll.h b/arch/mips/boards/ritmix-rzx50/include/board/debug_ll.h
new file mode 100644
index 0000000..7ae0e2a
--- /dev/null
+++ b/arch/mips/boards/ritmix-rzx50/include/board/debug_ll.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (C) 2012 Antony Pavlov <antonynpavlov at gmail.com>
+ *
+ * This file is part of barebox.
+ * See file CREDITS for list of people who contributed to this project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __INCLUDE_RZX50_BOARD_DEBUG_LL_H__
+#define __INCLUDE_RZX50_BOARD_DEBUG_LL_H__
+
+#include <mach/debug_ll_jz4750d.h>
+
+#endif  /* __INCLUDE_RZX50_BOARD_DEBUG_LL_H__ */
diff --git a/arch/mips/boards/ritmix-rzx50/ritmix-rzx50.dox b/arch/mips/boards/ritmix-rzx50/ritmix-rzx50.dox
new file mode 100644
index 0000000..5ec8194
--- /dev/null
+++ b/arch/mips/boards/ritmix-rzx50/ritmix-rzx50.dox
@@ -0,0 +1,46 @@
+/** @page ritmix-rzx50 Ritmix RZX-50 game console
+
+Ritmix RZX-50 is a portable game console for the Russian market.
+
+The portable game console has
+ at li Ingenic JZ4755 SoC;
+ at li 64 MiB SDRAM;
+ at li 4 GiB microSDHC card / 4 GiB NAND type Flash Memory;
+ at li RS232 serial interface (LV-TTL levels on the board!);
+ at li LCD display (480x272);
+ at li Video out interface;
+ at li 1xUSB interface;
+ at li buttons.
+
+The game console uses U-Boot 1.1.6 as bootloader.
+
+barebox-rzx50 mini-howto:
+
+1. Connect to the game console's UART (see. http://a320.emulate.su/2012/01/19/uart-na-ritmix-rzx-50/);
+
+2. Unblock U-Boot console (see. http://a320.emulate.su/2012/01/25/rzx-50-dostup-k-konsoli-u-boot/); Please note that U-Boot's Zmodem support does not work;
+
+3. Boot Ritmix linux and login;
+
+4. Upload barebox.bin via Zmodem
+ at verbatim
+  # cd /tmp
+  # rz
+ at endverbatim
+
+5. Write barebox to onboard flash
+ at verbatim
+  # dd if=barebox.bin of=/dev/mmcblk0 seek=1048576 bs=1 count=262144
+ at endverbatim
+
+6. Reboot RZX-50, next in U-Boot console start barebox:
+ at verbatim
+  CETUS # msc read 0xa0800000 0x100000 0x40000; g a0800000
+ at endverbatim
+
+Ritmix RZX-50 links:
+ at li http://www.ritmixrussia.ru/products/252/entertainment/game/rzx-50
+ at li ftp://ftp.ingenic.cn/2soc/4755/JZ4755_ds.pdf
+ at li ftp://ftp.ingenic.cn/3sw/01linux/01loader/u-boot/u-boot-1.1.6-jz-20110719-r1728-add-jz4770.patch.bz2
+
+*/
diff --git a/arch/mips/boards/ritmix-rzx50/serial.c b/arch/mips/boards/ritmix-rzx50/serial.c
new file mode 100644
index 0000000..f1e8da0
--- /dev/null
+++ b/arch/mips/boards/ritmix-rzx50/serial.c
@@ -0,0 +1,27 @@
+/*
+ * Copyright (C) 2012 Antony Pavlov <antonynpavlov at gmail.com>
+ *
+ * This file is part of barebox.
+ * See file CREDITS for list of people who contributed to this project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <common.h>
+#include <init.h>
+
+static int rzx50_hostname_init(void)
+{
+	barebox_set_hostname("rzx50");
+
+	return 0;
+}
+console_initcall(rzx50_hostname_init);
diff --git a/arch/mips/boards/rzx50/Makefile b/arch/mips/boards/rzx50/Makefile
deleted file mode 100644
index 31c0629..0000000
--- a/arch/mips/boards/rzx50/Makefile
+++ /dev/null
@@ -1 +0,0 @@
-obj-y += serial.o
diff --git a/arch/mips/boards/rzx50/include/board/board_pbl_start.h b/arch/mips/boards/rzx50/include/board/board_pbl_start.h
deleted file mode 100644
index fb914d9..0000000
--- a/arch/mips/boards/rzx50/include/board/board_pbl_start.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * Startup Code for Ritmix RZX-50 board
- *
- * Copyright (C) 2013 Antony Pavlov <antonynpavlov at gmail.com>
- *
- * This file is part of barebox.
- * See file CREDITS for list of people who contributed to this project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2
- * as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <asm/pbl_macros.h>
-#include <mach/debug_ll.h>
-#include <asm/pbl_nmon.h>
-
-	.macro	board_pbl_start
-	.set	push
-	.set	noreorder
-
-	mips_disable_interrupts
-
-	/* CPU/SoC specific setup ... */
-	/* ... absent */
-
-	debug_ll_ns16550_init
-
-	debug_ll_ns16550_outc '.'
-	debug_ll_ns16550_outnl
-
-	mips_nmon
-
-	copy_to_link_location	pbl_start
-
-	.set	pop
-	.endm
diff --git a/arch/mips/boards/rzx50/include/board/debug_ll.h b/arch/mips/boards/rzx50/include/board/debug_ll.h
deleted file mode 100644
index 7ae0e2a..0000000
--- a/arch/mips/boards/rzx50/include/board/debug_ll.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * Copyright (C) 2012 Antony Pavlov <antonynpavlov at gmail.com>
- *
- * This file is part of barebox.
- * See file CREDITS for list of people who contributed to this project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2
- * as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef __INCLUDE_RZX50_BOARD_DEBUG_LL_H__
-#define __INCLUDE_RZX50_BOARD_DEBUG_LL_H__
-
-#include <mach/debug_ll_jz4750d.h>
-
-#endif  /* __INCLUDE_RZX50_BOARD_DEBUG_LL_H__ */
diff --git a/arch/mips/boards/rzx50/rzx50.dox b/arch/mips/boards/rzx50/rzx50.dox
deleted file mode 100644
index 963473c..0000000
--- a/arch/mips/boards/rzx50/rzx50.dox
+++ /dev/null
@@ -1,46 +0,0 @@
-/** @page rzx50 Ritmix RZX-50 game console
-
-Ritmix RZX-50 is a portable game console for the Russian market.
-
-The portable game console has
- at li Ingenic JZ4755 SoC;
- at li 64 MiB SDRAM;
- at li 4 GiB microSDHC card / 4 GiB NAND type Flash Memory;
- at li RS232 serial interface (LV-TTL levels on the board!);
- at li LCD display (480x272);
- at li Video out interface;
- at li 1xUSB interface;
- at li buttons.
-
-The game console uses U-Boot 1.1.6 as bootloader.
-
-barebox-rzx50 mini-howto:
-
-1. Connect to the game console's UART (see. http://a320.emulate.su/2012/01/19/uart-na-ritmix-rzx-50/);
-
-2. Unblock U-Boot console (see. http://a320.emulate.su/2012/01/25/rzx-50-dostup-k-konsoli-u-boot/); Please note that U-Boot's Zmodem support does not work;
-
-3. Boot Ritmix linux and login;
-
-4. Upload barebox.bin via Zmodem
- at verbatim
-  # cd /tmp
-  # rz
- at endverbatim
-
-5. Write barebox to onboard flash
- at verbatim
-  # dd if=barebox.bin of=/dev/mmcblk0 seek=1048576 bs=1 count=262144
- at endverbatim
-
-6. Reboot RZX-50, next in U-Boot console start barebox:
- at verbatim
-  CETUS # msc read 0xa0800000 0x100000 0x40000; g a0800000
- at endverbatim
-
-Ritmix RZX-50 links:
- at li http://www.ritmixrussia.ru/products/252/entertainment/game/rzx-50
- at li ftp://ftp.ingenic.cn/2soc/4755/JZ4755_ds.pdf
- at li ftp://ftp.ingenic.cn/3sw/01linux/01loader/u-boot/u-boot-1.1.6-jz-20110719-r1728-add-jz4770.patch.bz2
-
-*/
diff --git a/arch/mips/boards/rzx50/serial.c b/arch/mips/boards/rzx50/serial.c
deleted file mode 100644
index f1e8da0..0000000
--- a/arch/mips/boards/rzx50/serial.c
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * Copyright (C) 2012 Antony Pavlov <antonynpavlov at gmail.com>
- *
- * This file is part of barebox.
- * See file CREDITS for list of people who contributed to this project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2
- * as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <common.h>
-#include <init.h>
-
-static int rzx50_hostname_init(void)
-{
-	barebox_set_hostname("rzx50");
-
-	return 0;
-}
-console_initcall(rzx50_hostname_init);
diff --git a/arch/mips/configs/ritmix-rzx50_defconfig b/arch/mips/configs/ritmix-rzx50_defconfig
new file mode 100644
index 0000000..7691bae
--- /dev/null
+++ b/arch/mips/configs/ritmix-rzx50_defconfig
@@ -0,0 +1,39 @@
+CONFIG_BUILTIN_DTB=y
+CONFIG_BUILTIN_DTB_NAME="rzx50"
+CONFIG_MACH_MIPS_XBURST=y
+CONFIG_JZ4750D_DEBUG_LL_UART1=y
+CONFIG_PBL_IMAGE=y
+CONFIG_BAUDRATE=57600
+CONFIG_GLOB=y
+CONFIG_HUSH_FANCY_PROMPT=y
+CONFIG_HUSH_GETOPT=y
+CONFIG_CMDLINE_EDITING=y
+CONFIG_AUTO_COMPLETE=y
+# CONFIG_DEFAULT_ENVIRONMENT is not set
+CONFIG_DEBUG_LL=y
+CONFIG_CMD_EDIT=y
+CONFIG_CMD_SLEEP=y
+CONFIG_CMD_LOADB=y
+CONFIG_CMD_LOADY=y
+CONFIG_CMD_LOADS=y
+CONFIG_CMD_SAVES=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_IOMEM=y
+CONFIG_CMD_MD5SUM=y
+CONFIG_CMD_BOOTM_SHOW_TYPE=y
+CONFIG_CMD_BOOTM_VERBOSE=y
+CONFIG_CMD_BOOTM_INITRD=y
+CONFIG_CMD_BOOTM_OFTREE=y
+CONFIG_CMD_BOOTM_OFTREE_UIMAGE=y
+CONFIG_CMD_UIMAGE=y
+CONFIG_CMD_RESET=y
+CONFIG_CMD_POWEROFF=y
+CONFIG_CMD_GO=y
+CONFIG_CMD_OFTREE=y
+CONFIG_CMD_OF_PROPERTY=y
+CONFIG_CMD_OF_NODE=y
+CONFIG_OFDEVICE=y
+# CONFIG_SPI is not set
+CONFIG_SHA1=y
+CONFIG_SHA224=y
+CONFIG_SHA256=y
diff --git a/arch/mips/configs/rzx50_defconfig b/arch/mips/configs/rzx50_defconfig
deleted file mode 100644
index 7691bae..0000000
--- a/arch/mips/configs/rzx50_defconfig
+++ /dev/null
@@ -1,39 +0,0 @@
-CONFIG_BUILTIN_DTB=y
-CONFIG_BUILTIN_DTB_NAME="rzx50"
-CONFIG_MACH_MIPS_XBURST=y
-CONFIG_JZ4750D_DEBUG_LL_UART1=y
-CONFIG_PBL_IMAGE=y
-CONFIG_BAUDRATE=57600
-CONFIG_GLOB=y
-CONFIG_HUSH_FANCY_PROMPT=y
-CONFIG_HUSH_GETOPT=y
-CONFIG_CMDLINE_EDITING=y
-CONFIG_AUTO_COMPLETE=y
-# CONFIG_DEFAULT_ENVIRONMENT is not set
-CONFIG_DEBUG_LL=y
-CONFIG_CMD_EDIT=y
-CONFIG_CMD_SLEEP=y
-CONFIG_CMD_LOADB=y
-CONFIG_CMD_LOADY=y
-CONFIG_CMD_LOADS=y
-CONFIG_CMD_SAVES=y
-CONFIG_CMD_MEMINFO=y
-CONFIG_CMD_IOMEM=y
-CONFIG_CMD_MD5SUM=y
-CONFIG_CMD_BOOTM_SHOW_TYPE=y
-CONFIG_CMD_BOOTM_VERBOSE=y
-CONFIG_CMD_BOOTM_INITRD=y
-CONFIG_CMD_BOOTM_OFTREE=y
-CONFIG_CMD_BOOTM_OFTREE_UIMAGE=y
-CONFIG_CMD_UIMAGE=y
-CONFIG_CMD_RESET=y
-CONFIG_CMD_POWEROFF=y
-CONFIG_CMD_GO=y
-CONFIG_CMD_OFTREE=y
-CONFIG_CMD_OF_PROPERTY=y
-CONFIG_CMD_OF_NODE=y
-CONFIG_OFDEVICE=y
-# CONFIG_SPI is not set
-CONFIG_SHA1=y
-CONFIG_SHA224=y
-CONFIG_SHA256=y
diff --git a/arch/mips/mach-xburst/mach-xburst.dox b/arch/mips/mach-xburst/mach-xburst.dox
index a5e524d..052c05e 100644
--- a/arch/mips/mach-xburst/mach-xburst.dox
+++ b/arch/mips/mach-xburst/mach-xburst.dox
@@ -2,6 +2,6 @@
 
 @section xburst_boards XBurst-based boards
 
- at li @subpage rzx50
+ at li @subpage ritmix-rzx50
 
 */
-- 
1.9.0



From antonynpavlov at gmail.com  Mon Mar 24 16:28:25 2014
From: antonynpavlov at gmail.com (Antony Pavlov)
Date: Tue, 25 Mar 2014 00:28:25 +0400
Subject: [PATCH v2 4/8] serial: ns16550: make FCR setup value part of
 struct ns16550_priv
In-Reply-To: <1395692034-5821-5-git-send-email-antonynpavlov@gmail.com>
References: <1395692034-5821-1-git-send-email-antonynpavlov@gmail.com>
 <1395692034-5821-5-git-send-email-antonynpavlov@gmail.com>
Message-ID: <20140325002825.5a467114657bd471de6c15ad@gmail.com>

On Tue, 25 Mar 2014 00:13:50 +0400
Antony Pavlov <antonynpavlov at gmail.com> wrote:

This patch can be very handy for adding device tree FIFO-less controllers support in the future.

E.g.:  .compatible = "ns8250" or .compatible = "ns16450"

> Signed-off-by: Antony Pavlov <antonynpavlov at gmail.com>
> ---
>  drivers/serial/serial_ns16550.c | 13 +++++++------
>  1 file changed, 7 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/serial/serial_ns16550.c b/drivers/serial/serial_ns16550.c
> index d217014..0089a04 100644
> --- a/drivers/serial/serial_ns16550.c
> +++ b/drivers/serial/serial_ns16550.c
> @@ -48,6 +48,7 @@ struct ns16550_priv {
>  	struct NS16550_plat plat;
>  	int access_width;
>  	struct clk *clk;
> +	uint32_t fcrval;
>  };
>  
>  static inline struct ns16550_priv *to_ns16550_priv(struct console_device *cdev)
> @@ -157,18 +158,13 @@ static int ns16550_setbaudrate(struct console_device *cdev, int baud_rate)
>  {
>  	unsigned int baud_divisor = ns16550_calc_divisor(cdev, baud_rate);
>  	struct ns16550_priv *priv = to_ns16550_priv(cdev);
> -	struct NS16550_plat *plat = &priv->plat;
>  
>  	ns16550_write(cdev, LCR_BKSE, lcr);
>  	ns16550_write(cdev, baud_divisor & 0xff, dll);
>  	ns16550_write(cdev, (baud_divisor >> 8) & 0xff, dlm);
>  	ns16550_write(cdev, LCRVAL, lcr);
>  	ns16550_write(cdev, MCRVAL, mcr);
> -
> -	if (plat->flags & NS16650_FLAG_DISABLE_FIFO)
> -		ns16550_write(cdev, FCRVAL & ~FCR_FIFO_EN, fcr);
> -	else
> -		ns16550_write(cdev, FCRVAL, fcr);
> +	ns16550_write(cdev, priv->fcrval, fcr);
>  
>  	return 0;
>  }
> @@ -316,6 +312,11 @@ static int ns16550_probe(struct device_d *dev)
>  	cdev->setbrg = ns16550_setbaudrate;
>  	cdev->linux_console_name = devtype->linux_console_name;
>  
> +	if (plat->flags & NS16650_FLAG_DISABLE_FIFO)
> +		priv->fcrval = FCRVAL & ~FCR_FIFO_EN;
> +	else
> +		priv->fcrval = FCRVAL;
> +
>  	devtype->init_port(cdev);
>  
>  	return console_register(cdev);
> -- 
> 1.9.0
> 


-- 
--?
Best regards,
? Antony Pavlov


From s.hauer at pengutronix.de  Tue Mar 25 04:18:15 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Tue, 25 Mar 2014 09:18:15 +0100
Subject: Barebox x86 IDE support
In-Reply-To: <C89EFD3CD56F64468D3D206D683A8D2203154121@ldam-msx2.fugro-nl.local>
References: <C89EFD3CD56F64468D3D206D683A8D2203154121@ldam-msx2.fugro-nl.local>
Message-ID: <20140325081815.GM17250@pengutronix.de>

Hi Michel,

On Mon, Mar 24, 2014 at 10:37:48AM +0100, Stam, Michel [FINT] wrote:
> Hello maintainers,
> 
> I was wondering if one of you has had time to verify these patches and apply them to trunk?

Could you send the patches as a series so that it's easier to comment on
the patches on the list?

There are some things to comment on, I think the most important one is
this:

> +/*
> + * request an io region inside the io space
> + */
> +struct resource *request_io_region(const char *name,
> +		resource_size_t start, resource_size_t end,int type)
> +{
> +	return request_region(&iomem_resource, name, start, end, type);
> +}
> 

You request here from the iomem resource, but ioports are a completely
separate resource, so you have to use a new toplevel resource like
this:

/* The root resource for the whole io space */
struct resource io_resource = {
	.start = 0,
	.end = 0xffffffff,
	.name = "ioport",
	.children = LIST_HEAD_INIT(io_resource.children),
};

/*
 * request an io region inside the io space
 */
struct resource *request_io_region(const char *name,
		resource_size_t start, resource_size_t end)
{
	return request_region(&io_resource, name, start, end, IORESOURCE_IO);
}

The 'type' argument to request_io_region is unnecessary since the
function name already implies it, right?

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From antonynpavlov at gmail.com  Tue Mar 25 05:40:40 2014
From: antonynpavlov at gmail.com (Antony Pavlov)
Date: Tue, 25 Mar 2014 13:40:40 +0400
Subject: [PATCH v2 0/8] MIPS: improve Ingenic JZ4755 device tree support
In-Reply-To: <1395692034-5821-1-git-send-email-antonynpavlov@gmail.com>
References: <1395692034-5821-1-git-send-email-antonynpavlov@gmail.com>
Message-ID: <20140325134040.c957f0ef648db46f734bfaf4@gmail.com>

On Tue, 25 Mar 2014 00:13:46 +0400
Antony Pavlov <antonynpavlov at gmail.com> wrote:

Sascha!

Please ignore this series!

There is a error in 
  [PATCH v2 4/8] serial: ns16550: make FCR setup value part of struct ns16550_priv

This code does not check 'plat' value before checking plat->flags!

+	if (plat->flags & NS16650_FLAG_DISABLE_FIFO)
+		priv->fcrval = FCRVAL & ~FCR_FIFO_EN;
+	else
+		priv->fcrval = FCRVAL;
+

> This patcheseries moves Ingenic JZ4755 UART initialization
> into device tree and makes JZ4755 device tree organization
> more clear.
> 
> This patchseries is a part of work on Ingenic chips support
> and prepares MIPS board support switch to device tree.
> Next patchseries will add device tree Ingenic gpio, clk
> and pinctls support.
> 
> Changes since v1:
>   * use "make FCR setup value part of struct ns16550_priv"
>     instead of "make it possible to get reg_write() from devtype";
>   * add a trivial "fix whitespaces" patch.
> 
> 
> Antony Pavlov (8):
>   MIPS: mach-xburst: fix DEBUG_LL=n build error
>   MIPS: dts: rzx50: move jz4755 description to the separate file
>   serial: ns16550: fix whitespaces
>   serial: ns16550: make FCR setup value part of struct ns16550_priv
>   serial: ns16550: add compatible entry for "ingenic,jz4740-uart"
>   MIPS: rzx50: drop console initialization in board code
>   MIPS: mach-xburst: drop serial.c
>   MIPS: boards: rename rzx50 -> ritmix-rzx50
> 
>  Documentation/boards.dox                           |  2 +-
>  arch/mips/Makefile                                 |  2 +-
>  arch/mips/boards/ritmix-rzx50/Makefile             |  1 +
>  .../ritmix-rzx50/include/board/board_pbl_start.h   | 43 ++++++++++++++++
>  .../boards/ritmix-rzx50/include/board/debug_ll.h   | 23 +++++++++
>  arch/mips/boards/ritmix-rzx50/ritmix-rzx50.dox     | 46 +++++++++++++++++
>  arch/mips/boards/ritmix-rzx50/serial.c             | 27 ++++++++++
>  arch/mips/boards/rzx50/Makefile                    |  1 -
>  .../boards/rzx50/include/board/board_pbl_start.h   | 43 ----------------
>  arch/mips/boards/rzx50/include/board/debug_ll.h    | 23 ---------
>  arch/mips/boards/rzx50/rzx50.dox                   | 46 -----------------
>  arch/mips/boards/rzx50/serial.c                    | 32 ------------
>  arch/mips/configs/ritmix-rzx50_defconfig           | 39 ++++++++++++++
>  arch/mips/configs/rzx50_defconfig                  | 39 --------------
>  arch/mips/dts/jz4755.dtsi                          | 35 +++++++++++++
>  arch/mips/dts/rzx50.dts                            |  8 ++-
>  arch/mips/include/asm/debug_ll_ns16550.h           |  2 +
>  arch/mips/mach-xburst/Makefile                     |  1 -
>  arch/mips/mach-xburst/mach-xburst.dox              |  2 +-
>  arch/mips/mach-xburst/serial.c                     | 60 ----------------------
>  drivers/serial/serial_ns16550.c                    | 35 ++++++++++---
>  21 files changed, 254 insertions(+), 256 deletions(-)
>  create mode 100644 arch/mips/boards/ritmix-rzx50/Makefile
>  create mode 100644 arch/mips/boards/ritmix-rzx50/include/board/board_pbl_start.h
>  create mode 100644 arch/mips/boards/ritmix-rzx50/include/board/debug_ll.h
>  create mode 100644 arch/mips/boards/ritmix-rzx50/ritmix-rzx50.dox
>  create mode 100644 arch/mips/boards/ritmix-rzx50/serial.c
>  delete mode 100644 arch/mips/boards/rzx50/Makefile
>  delete mode 100644 arch/mips/boards/rzx50/include/board/board_pbl_start.h
>  delete mode 100644 arch/mips/boards/rzx50/include/board/debug_ll.h
>  delete mode 100644 arch/mips/boards/rzx50/rzx50.dox
>  delete mode 100644 arch/mips/boards/rzx50/serial.c
>  create mode 100644 arch/mips/configs/ritmix-rzx50_defconfig
>  delete mode 100644 arch/mips/configs/rzx50_defconfig
>  create mode 100644 arch/mips/dts/jz4755.dtsi
>  delete mode 100644 arch/mips/mach-xburst/serial.c
> 
> -- 
> 1.9.0
> 


-- 
--?
Best regards,
? Antony Pavlov


From michel at reverze.net  Tue Mar 25 07:04:24 2014
From: michel at reverze.net (Michel Stam)
Date: Tue, 25 Mar 2014 12:04:24 +0100
Subject: Barebox x86 IDE support
In-Reply-To: <20140325081815.GM17250@pengutronix.de>
References: <C89EFD3CD56F64468D3D206D683A8D2203154121@ldam-msx2.fugro-nl.local>
 <20140325081815.GM17250@pengutronix.de>
Message-ID: <533162B8.8050300@reverze.net>

Hello Sascha,

I will repost the patches separately as you requested.

With regard to your comment below, this was somewhat intentional, as I 
understood:
> struct resource iomem_resource = {
>         .start = 0,
>         .end = 0xffffffff,
>         .name = "iomem",
>         .children = LIST_HEAD_INIT(iomem_resource.children),
> };
as "I/O and memory resource". This is also why I check on the resource 
type in request_region( ):
>         /*
>          * We keep the list of child resources ordered which helps
>          * us searching for conflicts here.
>          */
>         list_for_each_entry(r, &parent->children, sibling) {
>                 if (end < r->start)
>                         goto ok;
>                 if (start > r->end)
>                         continue;
>
>                 if (type != resource_type(r->parent))
>                         continue;
I retain one resource tree that way, also for if people decide to add 
DMA or IRQ's in the future. The iteration function skips the resource if 
the types do not match. To me the discussion seems the difference 
between one linked list for every resource type (== more work if a new 
type is added), or a single linked list with a type field (new resource 
type == new integer constant, no more).

I would like to hear your thoughts on that.

to be continued after the posting.

Cheers,

Michel
On 03/25/2014 09:18 AM, Sascha Hauer wrote:
> Hi Michel,
>
> On Mon, Mar 24, 2014 at 10:37:48AM +0100, Stam, Michel [FINT] wrote:
>> Hello maintainers,
>>
>> I was wondering if one of you has had time to verify these patches and apply them to trunk?
> Could you send the patches as a series so that it's easier to comment on
> the patches on the list?
>
> There are some things to comment on, I think the most important one is
> this:
>
>> +/*
>> + * request an io region inside the io space
>> + */
>> +struct resource *request_io_region(const char *name,
>> +		resource_size_t start, resource_size_t end,int type)
>> +{
>> +	return request_region(&iomem_resource, name, start, end, type);
>> +}
>>
> You request here from the iomem resource, but ioports are a completely
> separate resource, so you have to use a new toplevel resource like
> this:
>
> /* The root resource for the whole io space */
> struct resource io_resource = {
> 	.start = 0,
> 	.end = 0xffffffff,
> 	.name = "ioport",
> 	.children = LIST_HEAD_INIT(io_resource.children),
> };
>
> /*
>   * request an io region inside the io space
>   */
> struct resource *request_io_region(const char *name,
> 		resource_size_t start, resource_size_t end)
> {
> 	return request_region(&io_resource, name, start, end, IORESOURCE_IO);
> }
>
> The 'type' argument to request_io_region is unnecessary since the
> function name already implies it, right?
>
> Sascha
>


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From michel at reverze.net  Tue Mar 25 07:11:44 2014
From: michel at reverze.net (Michel Stam)
Date: Tue, 25 Mar 2014 12:11:44 +0100
Subject: [PATCH 1/3] common: driver: Allow for I/O mapped I/O in resource
 requests
Message-ID: <53316470.4040004@reverze.net>

The current resource framework is fully geared towards memory
mapped I/O.
This patch adds support for other types of I/O in the resource
structures / function calls.
---
  common/memory.c        |  2 +-
  common/resource.c      | 18 ++++++++++++++++--
  drivers/base/driver.c  | 36 ++++++++++++++++++------------------
  include/driver.h       | 24 +++++++++++++++++-------
  include/linux/ioport.h |  5 ++++-
  5 files changed, 56 insertions(+), 29 deletions(-)

diff --git a/common/memory.c b/common/memory.c
index c82bbaa..d36c8df 100644
--- a/common/memory.c
+++ b/common/memory.c
@@ -148,7 +148,7 @@ struct resource *request_sdram_region(const char 
*name, resource_size_t start,
  	for_each_memory_bank(bank) {
  		struct resource *res;
  -		res = request_region(bank->res, name, start, start + size - 1);
+		res = request_region(bank->res, name, start, start + size - 1, 
IORESOURCE_MEM);
  		if (res)
  			return res;
  	}
diff --git a/common/resource.c b/common/resource.c
index 5795e79..6600444 100644
--- a/common/resource.c
+++ b/common/resource.c
@@ -38,7 +38,7 @@ static int init_resource(struct resource *res, const 
char *name)
   */
  struct resource *request_region(struct resource *parent,
  		const char *name, resource_size_t start,
-		resource_size_t end)
+		resource_size_t end, int type)
  {
  	struct resource *r, *new;
  @@ -70,6 +70,10 @@ struct resource *request_region(struct resource 
*parent,
  			goto ok;
  		if (start > r->end)
  			continue;
+
+		if (type != resource_type(r->parent))
+			continue;
+
  		debug("%s: 0x%08llx:0x%08llx conflicts with 0x%08llx:0x%08llx\n",
  				__func__,
  				(unsigned long long)start,
@@ -89,6 +93,7 @@ ok:
  	new->start = start;
  	new->end = end;
  	new->parent = parent;
+	new->flags = type;
  	list_add_tail(&new->sibling, &r->sibling);
   	return new;
@@ -123,5 +128,14 @@ struct resource iomem_resource = {
  struct resource *request_iomem_region(const char *name,
  		resource_size_t start, resource_size_t end)
  {
-	return request_region(&iomem_resource, name, start, end);
+	return request_region(&iomem_resource, name, start, end, IORESOURCE_MEM);
+}
+
+/*
+ * request an io region inside the io space
+ */
+struct resource *request_io_region(const char *name,
+		resource_size_t start, resource_size_t end,int type)
+{
+	return request_region(&iomem_resource, name, start, end, type);
  }
diff --git a/drivers/base/driver.c b/drivers/base/driver.c
index 37560fd..560579a 100644
--- a/drivers/base/driver.c
+++ b/drivers/base/driver.c
@@ -241,13 +241,13 @@ int register_driver(struct driver_d *drv)
  }
  EXPORT_SYMBOL(register_driver);
  -struct resource *dev_get_resource(struct device_d *dev, int num)
+struct resource *dev_get_resource(struct device_d *dev, int num, int type)
  {
  	int i, n = 0;
   	for (i = 0; i < dev->num_resources; i++) {
  		struct resource *res = &dev->resource[i];
-		if (resource_type(res) == IORESOURCE_MEM) {
+		if (!type || (resource_type(res) == type)) {
  			if (n == num)
  				return res;
  			n++;
@@ -257,26 +257,26 @@ struct resource *dev_get_resource(struct device_d 
*dev, int num)
  	return NULL;
  }
  -void *dev_get_mem_region(struct device_d *dev, int num)
+void *dev_get_region(struct device_d *dev, int num, int type)
  {
  	struct resource *res;
  -	res = dev_get_resource(dev, num);
+	res = dev_get_resource(dev, num, type);
  	if (!res)
  		return NULL;
   	return (void __force *)res->start;
  }
-EXPORT_SYMBOL(dev_get_mem_region);
+EXPORT_SYMBOL(dev_get_region);
   struct resource *dev_get_resource_by_name(struct device_d *dev,
-					  const char *name)
+					  const char *name, int type)
  {
  	int i;
   	for (i = 0; i < dev->num_resources; i++) {
  		struct resource *res = &dev->resource[i];
-		if (resource_type(res) != IORESOURCE_MEM)
+		if (!type && (resource_type(res) != type))
  			continue;
  		if (!res->name)
  			continue;
@@ -287,49 +287,49 @@ struct resource *dev_get_resource_by_name(struct 
device_d *dev,
  	return NULL;
  }
  -void *dev_get_mem_region_by_name(struct device_d *dev, const char *name)
+void *dev_get_region_by_name(struct device_d *dev, const char *name, 
int type)
  {
  	struct resource *res;
  -	res = dev_get_resource_by_name(dev, name);
+	res = dev_get_resource_by_name(dev, name, type);
  	if (!res)
  		return NULL;
   	return (void __force *)res->start;
  }
-EXPORT_SYMBOL(dev_get_mem_region_by_name);
+EXPORT_SYMBOL(dev_get_region_by_name);
  -void __iomem *dev_request_mem_region_by_name(struct device_d *dev, 
const char *name)
+void __iomem *dev_request_region_by_name(struct device_d *dev, const 
char *name, int type)
  {
  	struct resource *res;
  -	res = dev_get_resource_by_name(dev, name);
+	res = dev_get_resource_by_name(dev, name, type);
  	if (!res)
  		return NULL;
  -	res = request_iomem_region(dev_name(dev), res->start, res->end);
+	res = request_io_region(dev_name(dev), res->start, res->end, type);
  	if (!res)
  		return NULL;
   	return (void __force __iomem *)res->start;
  }
-EXPORT_SYMBOL(dev_request_mem_region_by_name);
+EXPORT_SYMBOL(dev_request_region_by_name);
  -void __iomem *dev_request_mem_region(struct device_d *dev, int num)
+void __iomem *dev_request_region(struct device_d *dev, int num,int type)
  {
  	struct resource *res;
  -	res = dev_get_resource(dev, num);
+	res = dev_get_resource(dev, num, type);
  	if (!res)
  		return NULL;
  -	res = request_iomem_region(dev_name(dev), res->start, res->end);
+	res = request_io_region(dev_name(dev), res->start, res->end, type);
  	if (!res)
  		return NULL;
   	return (void __force __iomem *)res->start;
  }
-EXPORT_SYMBOL(dev_request_mem_region);
+EXPORT_SYMBOL(dev_request_region);
   int dev_protect(struct device_d *dev, size_t count, unsigned long 
offset, int prot)
  {
diff --git a/include/driver.h b/include/driver.h
index 01b181d..2eb4cf8 100644
--- a/include/driver.h
+++ b/include/driver.h
@@ -203,31 +203,41 @@ static inline const char *dev_name(const struct 
device_d *dev)
  /*
   * get resource 'num' for a device
   */
-struct resource *dev_get_resource(struct device_d *dev, int num);
+struct resource *dev_get_resource(struct device_d *dev, int num, int type);
  /*
   * get resource base 'name' for a device
   */
  struct resource *dev_get_resource_by_name(struct device_d *dev,
-					  const char *name);
+					  const char *name, int type);
+
  /*
+ *
   * get register base 'name' for a device
   */
-void *dev_get_mem_region_by_name(struct device_d *dev, const char *name);
+void *dev_get_region_by_name(struct device_d *dev, const char *name, 
int type);
   /*
   * exlusively request register base 'name' for a device
   */
-void __iomem *dev_request_mem_region_by_name(struct device_d *dev,
-					     const char *name);
+void __iomem *dev_request_region_by_name(struct device_d *dev,
+					 const char *name, int type);
  /*
   * get register base 'num' for a device
   */
-void *dev_get_mem_region(struct device_d *dev, int num);
+void *dev_get_region(struct device_d *dev, int num, int type);
   /*
   * exlusively request register base 'num' for a device
   */
-void __iomem *dev_request_mem_region(struct device_d *dev, int num);
+void __iomem *dev_request_region(struct device_d *dev, int num, int type);
+
+/*
+ * Macros for requesting memory resources
+ */
+#define dev_get_mem_region(dev, num)			dev_get_region(dev, num, 
IORESOURCE_MEM)
+#define dev_get_mem_region_by_name(dev, name)	 
dev_get_region_by_name(dev, name, IORESOURCE_MEM)
+#define dev_request_mem_region_by_name(dev, name) 
dev_request_region_by_name(dev, name, IORESOURCE_MEM)
+#define dev_request_mem_region(dev, num)		dev_request_region(dev, num, 
IORESOURCE_MEM)
   struct device_d *device_alloc(const char *devname, int id);
  diff --git a/include/linux/ioport.h b/include/linux/ioport.h
index ff0cba0..3fc2665 100644
--- a/include/linux/ioport.h
+++ b/include/linux/ioport.h
@@ -138,9 +138,12 @@ static inline unsigned long resource_type(const 
struct resource *res)
  struct resource *request_iomem_region(const char *name,
  		resource_size_t start, resource_size_t end);
  +struct resource *request_io_region(const char *name,
+		resource_size_t start, resource_size_t end, int type);
+
  struct resource *request_region(struct resource *parent,
  		const char *name, resource_size_t end,
-		resource_size_t size);
+		resource_size_t size,int type);
   int release_region(struct resource *res);
  -- 1.8.4



From michel at reverze.net  Tue Mar 25 07:12:00 2014
From: michel at reverze.net (Michel Stam)
Date: Tue, 25 Mar 2014 12:12:00 +0100
Subject: [PATCH 2/3] x86: Add support for IDE on the legacy I/O ports
Message-ID: <53316480.2030103@reverze.net>

---
  arch/x86/boards/x86_generic/generic_pc.c | 71 ++++++++++++++++++++++++
  drivers/ata/ide-sff.c                    | 94 
++++++++++++++++++++++++++------
  drivers/ata/intf_platform_ide.c          | 14 ++++-
  include/ata_drive.h                      |  1 +
  4 files changed, 161 insertions(+), 19 deletions(-)

diff --git a/arch/x86/boards/x86_generic/generic_pc.c 
b/arch/x86/boards/x86_generic/generic_pc.c
index 74a7224..6152afc 100644
--- a/arch/x86/boards/x86_generic/generic_pc.c
+++ b/arch/x86/boards/x86_generic/generic_pc.c
@@ -27,6 +27,10 @@
  #include <ns16550.h>
  #include <linux/err.h>
  +#ifdef CONFIG_DISK_INTF_PLATFORM_IDE
+#include <platform_ide.h>
+#endif
+
  /*
   * These datas are from the MBR, created by the linker and filled by the
   * setup tool while installing barebox on the disk drive
@@ -41,6 +45,55 @@ extern uint8_t pers_env_drive;
   */
  #define PATCH_AREA_PERS_SIZE_UNUSED 0x000
  +#ifdef CONFIG_DISK_INTF_PLATFORM_IDE
+
+static struct ide_port_info ide_plat = {
+	.ioport_shift = 0,
+	.dataif_be = 0,
+};
+
+static struct resource primary_ide_resources[] = {
+	{
+		.name = "base",
+		.start = 0x1f0,
+		.end =  0x1f8,
+		.flags = IORESOURCE_IO
+	},
+	{
+		.name = "alt",
+		.start = 0x3f6,
+		.end =  0x3f8,
+		.flags = IORESOURCE_IO
+	}
+};
+
+static struct resource secondary_ide_resources[] = {
+	{
+		.name = "base",
+		.start = 0x170,
+		.end =  0x177,
+		.flags = IORESOURCE_IO
+	},
+};
+
+static struct device_d primary_ide_device = {
+	.name = "ide_intf",
+	.id = 0,
+	.platform_data = &ide_plat,
+	.resource = primary_ide_resources,
+	.num_resources = ARRAY_SIZE( primary_ide_resources ),
+};
+
+static struct device_d secondary_ide_device = {
+	.name = "ide_intf",
+	.id = 1,
+	.platform_data = &ide_plat,
+	.resource = secondary_ide_resources,
+	.num_resources = ARRAY_SIZE( secondary_ide_resources ),
+};
+
+#endif /* CONFIG_DISK_INTF_PLATFORM_IDE */
+
  static int devices_init(void)
  {
  	struct cdev *cdev;
@@ -48,9 +101,26 @@ static int devices_init(void)
  	/* extended memory only */
  	add_mem_device("ram0", 0x0, bios_get_memsize() << 10,
  		       IORESOURCE_MEM_WRITEABLE);
+#ifdef CONFIG_DISK_BIOS
  	add_generic_device("biosdrive", DEVICE_ID_DYNAMIC, NULL, 0, 0, 
IORESOURCE_MEM,
  			NULL);
+#endif
+
+#ifdef CONFIG_DISK_INTF_PLATFORM_IDE
+	platform_device_register( &primary_ide_device );
+	platform_device_register( &secondary_ide_device );
+
+	if (pers_env_size != PATCH_AREA_PERS_SIZE_UNUSED) {
+		cdev = devfs_add_partition("ata0",
+				pers_env_storage * 512,
+				(unsigned)pers_env_size * 512,
+				DEVFS_PARTITION_FIXED, "env0");
+		printf("Partition: %ld\n", IS_ERR(cdev) ? PTR_ERR(cdev) : 0);
+	} else
+		printf("No persistent storage defined\n");
+#endif /* CONFIG_DISK_INTF_PLATFORM_IDE */
  +#ifdef CONFIG_DISK_BIOS
  	if (pers_env_size != PATCH_AREA_PERS_SIZE_UNUSED) {
  		cdev = devfs_add_partition("biosdisk0",
  				pers_env_storage * 512,
@@ -59,6 +129,7 @@ static int devices_init(void)
  		printf("Partition: %ld\n", IS_ERR(cdev) ? PTR_ERR(cdev) : 0);
  	} else
  		printf("No persistent storage defined\n");
+#endif
           return 0;
  }
diff --git a/drivers/ata/ide-sff.c b/drivers/ata/ide-sff.c
index 3d5932e..809a129 100644
--- a/drivers/ata/ide-sff.c
+++ b/drivers/ata/ide-sff.c
@@ -15,13 +15,71 @@
  #define DISK_SLAVE 1
   /**
+ * Read a byte from the ATA controller
+ * @param ide IDE port structure
+ * @param addr Register adress
+ * @return Register's content
+ */
+static inline uint8_t ata_rd_byte(struct ide_port *ide, void __iomem 
*addr )
+{
+	if (!ide->io.mmio)
+		return (uint8_t) inb((int) addr);
+	else
+		return readb(addr);
+}
+
+/**
+ * Write a byte to the ATA controller
+ * @param ide IDE port structure
+ * @param value Value to write
+ * @param addr Register adress
+ * @return Register's content
+ */
+static inline void ata_wr_byte(struct ide_port *ide, uint8_t value, 
void __iomem *addr )
+{
+	if (!ide->io.mmio)
+		outb(value, (int) addr);
+	else
+		writeb(value,addr);
+}
+
+/**
+ * Read a word from the ATA controller
+ * @param ide IDE port structure
+ * @param addr Register adress
+ * @return Register's content
+ */
+static inline uint16_t ata_rd_word(struct ide_port *ide, void __iomem 
*addr )
+{
+	if (!ide->io.mmio)
+		return (uint16_t) inw((int) addr);
+	else
+		return readw(addr);
+}
+
+/**
+ * Write a word to the ATA controller
+ * @param ide IDE port structure
+ * @param value Value to write
+ * @param addr Register adress
+ * @return Register's content
+ */
+static inline void ata_wr_word(struct ide_port *ide, uint16_t value, 
void __iomem *addr )
+{
+	if (!ide->io.mmio)
+		outw(value, (int) addr);
+	else
+		writew(value,addr);
+}
+
+/**
   * Read the status register of the ATA drive
   * @param io Register file
   * @return Register's content
   */
  static uint8_t ata_rd_status(struct ide_port *ide)
  {
-	return readb(ide->io.status_addr);
+	return ata_rd_byte(ide,ide->io.status_addr);
  }
   /**
@@ -83,12 +141,12 @@ static int ata_set_lba_sector(struct ide_port *ide, 
unsigned drive, uint64_t num
  	if (num > 0x0FFFFFFF || drive > 1)
  		return -EINVAL;
  -	writeb(0xA0 | LBA_FLAG | drive << 4 | num >> 24, ide->io.device_addr);
-	writeb(0x00, ide->io.error_addr);
-	writeb(0x01, ide->io.nsect_addr);
-	writeb(num, ide->io.lbal_addr);	/* 0 ... 7 */
-	writeb(num >> 8, ide->io.lbam_addr); /* 8 ... 15 */
-	writeb(num >> 16, ide->io.lbah_addr); /* 16 ... 23 */
+	ata_wr_byte(ide, 0xA0 | LBA_FLAG | drive << 4 | num >> 24, 
ide->io.device_addr);
+	ata_wr_byte(ide, 0x00, ide->io.error_addr);
+	ata_wr_byte(ide, 0x01, ide->io.nsect_addr);
+	ata_wr_byte(ide, num, ide->io.lbal_addr);	/* 0 ... 7 */
+	ata_wr_byte(ide, num >> 8, ide->io.lbam_addr); /* 8 ... 15 */
+	ata_wr_byte(ide, num >> 16, ide->io.lbah_addr); /* 16 ... 23 */
   	return 0;
  }
@@ -107,7 +165,7 @@ static int ata_wr_cmd(struct ide_port *ide, uint8_t cmd)
  	if (rc != 0)
  		return rc;
  -	writeb(cmd, ide->io.command_addr);
+	ata_wr_byte(ide, cmd, ide->io.command_addr);
  	return 0;
  }
  @@ -118,7 +176,7 @@ static int ata_wr_cmd(struct ide_port *ide, 
uint8_t cmd)
   */
  static void ata_wr_dev_ctrl(struct ide_port *ide, uint8_t val)
  {
-	writeb(val, ide->io.ctl_addr);
+	ata_wr_byte(ide, val, ide->io.ctl_addr);
  }
   /**
@@ -133,10 +191,10 @@ static void ata_rd_sector(struct ide_port *ide, 
void *buf)
   	if (ide->io.dataif_be) {
  		for (; u > 0; u--)
-			*b++ = be16_to_cpu(readw(ide->io.data_addr));
+			*b++ = be16_to_cpu(ata_rd_word(ide, ide->io.data_addr));
  	} else {
  		for (; u > 0; u--)
-			*b++ = le16_to_cpu(readw(ide->io.data_addr));
+			*b++ = le16_to_cpu(ata_rd_word(ide, ide->io.data_addr));
  	}
  }
  @@ -152,10 +210,10 @@ static void ata_wr_sector(struct ide_port *ide, 
const void *buf)
   	if (ide->io.dataif_be) {
  		for (; u > 0; u--)
-			writew(cpu_to_be16(*b++), ide->io.data_addr);
+			ata_wr_word(ide, cpu_to_be16(*b++), ide->io.data_addr);
  	} else {
  		for (; u > 0; u--)
-			writew(cpu_to_le16(*b++), ide->io.data_addr);
+			ata_wr_word(ide, cpu_to_le16(*b++), ide->io.data_addr);
  	}
  }
  @@ -169,10 +227,10 @@ static int ide_read_id(struct ata_port *port, 
void *buf)
  	struct ide_port *ide = to_ata_drive_access(port);
  	int rc;
  -	writeb(0xA0, ide->io.device_addr);	/* FIXME drive */
-	writeb(0x00, ide->io.lbal_addr);
-	writeb(0x00, ide->io.lbam_addr);
-	writeb(0x00, ide->io.lbah_addr);
+	ata_wr_byte(ide, 0xA0, ide->io.device_addr);	/* FIXME drive */
+	ata_wr_byte(ide, 0x00, ide->io.lbal_addr);
+	ata_wr_byte(ide, 0x00, ide->io.lbam_addr);
+	ata_wr_byte(ide, 0x00, ide->io.lbah_addr);
   	rc = ata_wr_cmd(ide, ATA_CMD_ID_ATA);
  	if (rc != 0)
@@ -327,6 +385,8 @@ int ide_port_register(struct ide_port *ide)
  	ide->port.ops = &ide_ops;
   	ret = ata_port_register(&ide->port);
+	if ( !ret )
+		ata_port_detect(&ide->port);
   	if (ret)
  		free(ide);
diff --git a/drivers/ata/intf_platform_ide.c 
b/drivers/ata/intf_platform_ide.c
index 8ae0f05..24f78f4 100644
--- a/drivers/ata/intf_platform_ide.c
+++ b/drivers/ata/intf_platform_ide.c
@@ -89,8 +89,18 @@ static int platform_ide_probe(struct device_d *dev)
  	}
   	ide = xzalloc(sizeof(*ide));
-	reg_base = dev_request_mem_region(dev, 0);
-	alt_base = dev_request_mem_region(dev, 1);
+	reg_base = dev_request_region(dev, 0, IORESOURCE_MEM);
+	if (reg_base != NULL)
+	{
+		alt_base = dev_request_region(dev, 1, IORESOURCE_MEM);
+		ide->io.mmio = 1;
+	}
+	else
+	{
+		reg_base = dev_request_region(dev, 0, IORESOURCE_IO);
+		alt_base = dev_request_region(dev, 1, IORESOURCE_IO);
+	}
+
  	platform_ide_setup_port(reg_base, alt_base, &ide->io, 
pdata->ioport_shift);
  	ide->io.reset = pdata->reset;
  	ide->io.dataif_be = pdata->dataif_be;
diff --git a/include/ata_drive.h b/include/ata_drive.h
index 6d6cca4..44073cb 100644
--- a/include/ata_drive.h
+++ b/include/ata_drive.h
@@ -119,6 +119,7 @@ struct ata_ioports {
  	/* hard reset line handling */
  	void (*reset)(int);	/* true: assert reset, false: de-assert reset */
  	int dataif_be;	/* true if 16 bit data register is big endian */
+	int mmio; /* true if memory-mapped io */
  };
   struct ata_port;
-- 
1.8.4



From michel at reverze.net  Tue Mar 25 07:12:12 2014
From: michel at reverze.net (Michel Stam)
Date: Tue, 25 Mar 2014 12:12:12 +0100
Subject: [PATCH 3/3] x86: Most systems support a second serial port. Add it.
Message-ID: <5331648C.9030506@reverze.net>

---
  arch/x86/boards/x86_generic/generic_pc.c | 1 +
  1 file changed, 1 insertion(+)

diff --git a/arch/x86/boards/x86_generic/generic_pc.c 
b/arch/x86/boards/x86_generic/generic_pc.c
index 6152afc..4031a7e 100644
--- a/arch/x86/boards/x86_generic/generic_pc.c
+++ b/arch/x86/boards/x86_generic/generic_pc.c
@@ -150,6 +150,7 @@ static int pc_console_init(void)
   	/* Register the serial port */
  	add_ns16550_device(DEVICE_ID_DYNAMIC, 0x3f8, 8, 0, &serial_plat);
+	add_ns16550_device(DEVICE_ID_DYNAMIC, 0x2f8, 8, 0, &serial_plat);
   	return 0;
  }
-- 
1.8.4



From antonynpavlov at gmail.com  Tue Mar 25 12:50:51 2014
From: antonynpavlov at gmail.com (Antony Pavlov)
Date: Tue, 25 Mar 2014 20:50:51 +0400
Subject: [PATCH v3 0/8] MIPS: improve Ingenic JZ4755 device tree support
Message-ID: <1395766259-31866-1-git-send-email-antonynpavlov@gmail.com>

This patcheseries moves Ingenic JZ4755 UART initialization
into device tree and makes JZ4755 device tree organization
more clear.

This patchseries is a part of work on Ingenic chips support
and prepares MIPS board support switch to device tree.
Next patchseries will add device tree Ingenic gpio, clk
and pinctls support.

Changes since v2:
  * add the plat pointer check into "make FCR setup value part of struct ns16550_priv"
  * add the "serial: ns16550: add compatible entry for "ns16450"" commit
  * rebase over updated next branch

Changes since v1:
  * use "make FCR setup value part of struct ns16550_priv"
    instead of "make it possible to get reg_write() from devtype";
  * add a trivial "fix whitespaces" patch.

Antony Pavlov (8):
  MIPS: dts: rzx50: move jz4755 description to the separate file
  serial: ns16550: fix whitespaces
  serial: ns16550: make FCR setup value part of struct ns16550_priv
  serial: ns16550: add compatible entry for "ns16450"
  serial: ns16550: add compatible entry for "ingenic,jz4740-uart"
  MIPS: rzx50: drop console initialization in board code
  MIPS: mach-xburst: drop serial.c
  MIPS: boards: rename rzx50 -> ritmix-rzx50

 Documentation/boards.dox                           |  2 +-
 arch/mips/Makefile                                 |  2 +-
 arch/mips/boards/ritmix-rzx50/Makefile             |  1 +
 .../ritmix-rzx50/include/board/board_pbl_start.h   | 43 ++++++++++++++++
 .../boards/ritmix-rzx50/include/board/debug_ll.h   | 23 +++++++++
 arch/mips/boards/ritmix-rzx50/ritmix-rzx50.dox     | 46 +++++++++++++++++
 arch/mips/boards/ritmix-rzx50/serial.c             | 27 ++++++++++
 arch/mips/boards/rzx50/Makefile                    |  1 -
 .../boards/rzx50/include/board/board_pbl_start.h   | 43 ----------------
 arch/mips/boards/rzx50/include/board/debug_ll.h    | 23 ---------
 arch/mips/boards/rzx50/rzx50.dox                   | 46 -----------------
 arch/mips/boards/rzx50/serial.c                    | 32 ------------
 arch/mips/configs/ritmix-rzx50_defconfig           | 39 ++++++++++++++
 arch/mips/configs/rzx50_defconfig                  | 39 --------------
 arch/mips/dts/jz4755.dtsi                          | 35 +++++++++++++
 arch/mips/dts/rzx50.dts                            |  8 ++-
 arch/mips/mach-xburst/Makefile                     |  1 -
 arch/mips/mach-xburst/mach-xburst.dox              |  2 +-
 arch/mips/mach-xburst/serial.c                     | 60 ----------------------
 drivers/serial/serial_ns16550.c                    | 51 +++++++++++++++---
 20 files changed, 268 insertions(+), 256 deletions(-)
 create mode 100644 arch/mips/boards/ritmix-rzx50/Makefile
 create mode 100644 arch/mips/boards/ritmix-rzx50/include/board/board_pbl_start.h
 create mode 100644 arch/mips/boards/ritmix-rzx50/include/board/debug_ll.h
 create mode 100644 arch/mips/boards/ritmix-rzx50/ritmix-rzx50.dox
 create mode 100644 arch/mips/boards/ritmix-rzx50/serial.c
 delete mode 100644 arch/mips/boards/rzx50/Makefile
 delete mode 100644 arch/mips/boards/rzx50/include/board/board_pbl_start.h
 delete mode 100644 arch/mips/boards/rzx50/include/board/debug_ll.h
 delete mode 100644 arch/mips/boards/rzx50/rzx50.dox
 delete mode 100644 arch/mips/boards/rzx50/serial.c
 create mode 100644 arch/mips/configs/ritmix-rzx50_defconfig
 delete mode 100644 arch/mips/configs/rzx50_defconfig
 create mode 100644 arch/mips/dts/jz4755.dtsi
 delete mode 100644 arch/mips/mach-xburst/serial.c

-- 
1.9.0



From antonynpavlov at gmail.com  Tue Mar 25 12:50:52 2014
From: antonynpavlov at gmail.com (Antony Pavlov)
Date: Tue, 25 Mar 2014 20:50:52 +0400
Subject: [PATCH v3 1/8] MIPS: dts: rzx50: move jz4755 description to the
 separate file
In-Reply-To: <1395766259-31866-1-git-send-email-antonynpavlov@gmail.com>
References: <1395766259-31866-1-git-send-email-antonynpavlov@gmail.com>
Message-ID: <1395766259-31866-2-git-send-email-antonynpavlov@gmail.com>

Signed-off-by: Antony Pavlov <antonynpavlov at gmail.com>
---
 arch/mips/dts/jz4755.dtsi | 35 +++++++++++++++++++++++++++++++++++
 arch/mips/dts/rzx50.dts   |  8 +++++++-
 2 files changed, 42 insertions(+), 1 deletion(-)

diff --git a/arch/mips/dts/jz4755.dtsi b/arch/mips/dts/jz4755.dtsi
new file mode 100644
index 0000000..44ff912
--- /dev/null
+++ b/arch/mips/dts/jz4755.dtsi
@@ -0,0 +1,35 @@
+#include "skeleton.dtsi"
+
+/ {
+	soc {
+		compatible = "simple-bus";
+		model = "Ingenic JZ4755";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		serial0: serial at b0030000 {
+			compatible = "ingenic,jz4740-uart";
+			reg = <0xb0030000 0x20>;
+			reg-shift = <2>;
+			clock-frequency = <12000000>;
+			status = "disabled";
+		};
+
+		serial1: serial at b0031000 {
+			compatible = "ingenic,jz4740-uart";
+			reg = <0xb0031000 0x20>;
+			reg-shift = <2>;
+			clock-frequency = <12000000>;
+			status = "disabled";
+		};
+
+		serial2: serial at b0032000 {
+			compatible = "ingenic,jz4740-uart";
+			reg = <0xb0032000 0x20>;
+			reg-shift = <2>;
+			clock-frequency = <12000000>;
+			status = "disabled";
+		};
+	};
+};
diff --git a/arch/mips/dts/rzx50.dts b/arch/mips/dts/rzx50.dts
index 69320dd..78103e3 100644
--- a/arch/mips/dts/rzx50.dts
+++ b/arch/mips/dts/rzx50.dts
@@ -1,6 +1,6 @@
 /dts-v1/;
 
-/include/ "skeleton.dtsi"
+#include "jz4755.dtsi"
 
 / {
 	model = "Ritmix RZX-50";
@@ -9,4 +9,10 @@
 	memory {
 		reg = <0x00000000 0x4000000>;
 	};
+
+	soc {
+		serial1: serial at b0031000 {
+			status = "okay";
+		};
+	};
 };
-- 
1.9.0



From antonynpavlov at gmail.com  Tue Mar 25 12:50:53 2014
From: antonynpavlov at gmail.com (Antony Pavlov)
Date: Tue, 25 Mar 2014 20:50:53 +0400
Subject: [PATCH v3 2/8] serial: ns16550: fix whitespaces
In-Reply-To: <1395766259-31866-1-git-send-email-antonynpavlov@gmail.com>
References: <1395766259-31866-1-git-send-email-antonynpavlov@gmail.com>
Message-ID: <1395766259-31866-3-git-send-email-antonynpavlov@gmail.com>

Signed-off-by: Antony Pavlov <antonynpavlov at gmail.com>
---
 drivers/serial/serial_ns16550.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/serial/serial_ns16550.c b/drivers/serial/serial_ns16550.c
index f1da44b..d217014 100644
--- a/drivers/serial/serial_ns16550.c
+++ b/drivers/serial/serial_ns16550.c
@@ -192,7 +192,7 @@ static void ns16550_omap_init_port(struct console_device *cdev)
 	ns16550_serial_init_port(cdev);
 
 	ns16550_write(cdev, 0x07, omap_mdr1);	/* Disable */
-	ns16550_write(cdev, 0x00,  omap_mdr1);
+	ns16550_write(cdev, 0x00, omap_mdr1);
 }
 
 /*********** Exposed Functions **********************************/
-- 
1.9.0



From antonynpavlov at gmail.com  Tue Mar 25 12:50:54 2014
From: antonynpavlov at gmail.com (Antony Pavlov)
Date: Tue, 25 Mar 2014 20:50:54 +0400
Subject: [PATCH v3 3/8] serial: ns16550: make FCR setup value part of struct
 ns16550_priv
In-Reply-To: <1395766259-31866-1-git-send-email-antonynpavlov@gmail.com>
References: <1395766259-31866-1-git-send-email-antonynpavlov@gmail.com>
Message-ID: <1395766259-31866-4-git-send-email-antonynpavlov@gmail.com>

Signed-off-by: Antony Pavlov <antonynpavlov at gmail.com>
---
 drivers/serial/serial_ns16550.c | 13 +++++++------
 1 file changed, 7 insertions(+), 6 deletions(-)

diff --git a/drivers/serial/serial_ns16550.c b/drivers/serial/serial_ns16550.c
index d217014..7bd426d 100644
--- a/drivers/serial/serial_ns16550.c
+++ b/drivers/serial/serial_ns16550.c
@@ -48,6 +48,7 @@ struct ns16550_priv {
 	struct NS16550_plat plat;
 	int access_width;
 	struct clk *clk;
+	uint32_t fcrval;
 };
 
 static inline struct ns16550_priv *to_ns16550_priv(struct console_device *cdev)
@@ -157,18 +158,13 @@ static int ns16550_setbaudrate(struct console_device *cdev, int baud_rate)
 {
 	unsigned int baud_divisor = ns16550_calc_divisor(cdev, baud_rate);
 	struct ns16550_priv *priv = to_ns16550_priv(cdev);
-	struct NS16550_plat *plat = &priv->plat;
 
 	ns16550_write(cdev, LCR_BKSE, lcr);
 	ns16550_write(cdev, baud_divisor & 0xff, dll);
 	ns16550_write(cdev, (baud_divisor >> 8) & 0xff, dlm);
 	ns16550_write(cdev, LCRVAL, lcr);
 	ns16550_write(cdev, MCRVAL, mcr);
-
-	if (plat->flags & NS16650_FLAG_DISABLE_FIFO)
-		ns16550_write(cdev, FCRVAL & ~FCR_FIFO_EN, fcr);
-	else
-		ns16550_write(cdev, FCRVAL, fcr);
+	ns16550_write(cdev, priv->fcrval, fcr);
 
 	return 0;
 }
@@ -316,6 +312,11 @@ static int ns16550_probe(struct device_d *dev)
 	cdev->setbrg = ns16550_setbaudrate;
 	cdev->linux_console_name = devtype->linux_console_name;
 
+	if (plat && (plat->flags & NS16650_FLAG_DISABLE_FIFO))
+		priv->fcrval = FCRVAL & ~FCR_FIFO_EN;
+	else
+		priv->fcrval = FCRVAL;
+
 	devtype->init_port(cdev);
 
 	return console_register(cdev);
-- 
1.9.0



From antonynpavlov at gmail.com  Tue Mar 25 12:50:55 2014
From: antonynpavlov at gmail.com (Antony Pavlov)
Date: Tue, 25 Mar 2014 20:50:55 +0400
Subject: [PATCH v3 4/8] serial: ns16550: add compatible entry for "ns16450"
In-Reply-To: <1395766259-31866-1-git-send-email-antonynpavlov@gmail.com>
References: <1395766259-31866-1-git-send-email-antonynpavlov@gmail.com>
Message-ID: <1395766259-31866-5-git-send-email-antonynpavlov@gmail.com>

"ns16450" uses the same code as "ns16550a" but with FIFO disabled.

Signed-off-by: Antony Pavlov <antonynpavlov at gmail.com>
---
 drivers/serial/serial_ns16550.c | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/drivers/serial/serial_ns16550.c b/drivers/serial/serial_ns16550.c
index 7bd426d..635c2b7 100644
--- a/drivers/serial/serial_ns16550.c
+++ b/drivers/serial/serial_ns16550.c
@@ -181,6 +181,15 @@ static void ns16550_serial_init_port(struct console_device *cdev)
 	ns16550_write(cdev, 0x00, ier);
 }
 
+static void ns16450_serial_init_port(struct console_device *cdev)
+{
+	struct ns16550_priv *priv = to_ns16550_priv(cdev);
+
+	priv->fcrval &= ~FCR_FIFO_EN;
+
+	ns16550_serial_init_port(cdev);
+}
+
 #define omap_mdr1		8
 
 static void ns16550_omap_init_port(struct console_device *cdev)
@@ -242,6 +251,10 @@ static void ns16550_probe_dt(struct device_d *dev, struct ns16550_priv *priv)
 	of_property_read_u32(np, "reg-shift", &priv->plat.shift);
 }
 
+static struct ns16550_drvdata ns16450_drvdata = {
+	.init_port = ns16450_serial_init_port,
+};
+
 static struct ns16550_drvdata ns16550_drvdata = {
 	.init_port = ns16550_serial_init_port,
 };
@@ -329,6 +342,9 @@ err:
 
 static struct of_device_id ns16550_serial_dt_ids[] = {
 	{
+		.compatible = "ns16450",
+		.data = (unsigned long)&ns16450_drvdata,
+	}, {
 		.compatible = "ns16550a",
 		.data = (unsigned long)&ns16550_drvdata,
 	}, {
-- 
1.9.0



From antonynpavlov at gmail.com  Tue Mar 25 12:50:56 2014
From: antonynpavlov at gmail.com (Antony Pavlov)
Date: Tue, 25 Mar 2014 20:50:56 +0400
Subject: [PATCH v3 5/8] serial: ns16550: add compatible entry for "ingenic,
 jz4740-uart"
In-Reply-To: <1395766259-31866-1-git-send-email-antonynpavlov@gmail.com>
References: <1395766259-31866-1-git-send-email-antonynpavlov@gmail.com>
Message-ID: <1395766259-31866-6-git-send-email-antonynpavlov@gmail.com>

Signed-off-by: Antony Pavlov <antonynpavlov at gmail.com>
---
 drivers/serial/serial_ns16550.c | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/drivers/serial/serial_ns16550.c b/drivers/serial/serial_ns16550.c
index 635c2b7..0c00eb1 100644
--- a/drivers/serial/serial_ns16550.c
+++ b/drivers/serial/serial_ns16550.c
@@ -200,6 +200,16 @@ static void ns16550_omap_init_port(struct console_device *cdev)
 	ns16550_write(cdev, 0x00, omap_mdr1);
 }
 
+#define JZ_FCR_UME 0x10 /* Uart Module Enable */
+
+static void ns16550_jz_init_port(struct console_device *cdev)
+{
+	struct ns16550_priv *priv = to_ns16550_priv(cdev);
+
+	priv->fcrval |= JZ_FCR_UME;
+	ns16550_serial_init_port(cdev);
+}
+
 /*********** Exposed Functions **********************************/
 
 /**
@@ -264,6 +274,10 @@ static __maybe_unused struct ns16550_drvdata omap_drvdata = {
 	.linux_console_name = "ttyO",
 };
 
+static __maybe_unused struct ns16550_drvdata jz_drvdata = {
+	.init_port = ns16550_jz_init_port,
+};
+
 /**
  * @brief Probe entry point -called on the first match for device
  *
@@ -363,6 +377,12 @@ static struct of_device_id ns16550_serial_dt_ids[] = {
 		.data = (unsigned long)&omap_drvdata,
 	},
 #endif
+#if IS_ENABLED(CONFIG_MACH_MIPS_XBURST)
+	{
+		.compatible = "ingenic,jz4740-uart",
+		.data = (unsigned long)&jz_drvdata,
+	},
+#endif
 	{
 		/* sentinel */
 	},
-- 
1.9.0



From antonynpavlov at gmail.com  Tue Mar 25 12:50:57 2014
From: antonynpavlov at gmail.com (Antony Pavlov)
Date: Tue, 25 Mar 2014 20:50:57 +0400
Subject: [PATCH v3 6/8] MIPS: rzx50: drop console initialization in board code
In-Reply-To: <1395766259-31866-1-git-send-email-antonynpavlov@gmail.com>
References: <1395766259-31866-1-git-send-email-antonynpavlov@gmail.com>
Message-ID: <1395766259-31866-7-git-send-email-antonynpavlov@gmail.com>

Signed-off-by: Antony Pavlov <antonynpavlov at gmail.com>
---
 arch/mips/boards/rzx50/Makefile | 2 +-
 arch/mips/boards/rzx50/serial.c | 9 ++-------
 2 files changed, 3 insertions(+), 8 deletions(-)

diff --git a/arch/mips/boards/rzx50/Makefile b/arch/mips/boards/rzx50/Makefile
index ff1a655..31c0629 100644
--- a/arch/mips/boards/rzx50/Makefile
+++ b/arch/mips/boards/rzx50/Makefile
@@ -1 +1 @@
-obj-$(CONFIG_DRIVER_SERIAL_NS16550) += serial.o
+obj-y += serial.o
diff --git a/arch/mips/boards/rzx50/serial.c b/arch/mips/boards/rzx50/serial.c
index 566356a..f1e8da0 100644
--- a/arch/mips/boards/rzx50/serial.c
+++ b/arch/mips/boards/rzx50/serial.c
@@ -17,16 +17,11 @@
 
 #include <common.h>
 #include <init.h>
-#include <mach/devices.h>
-#include <mach/jz4750d_regs.h>
 
-static int rzx50_console_init(void)
+static int rzx50_hostname_init(void)
 {
 	barebox_set_hostname("rzx50");
 
-	/* Register the serial port */
-	jz_add_uart(DEVICE_ID_DYNAMIC, UART1_BASE, 12000000);
-
 	return 0;
 }
-console_initcall(rzx50_console_init);
+console_initcall(rzx50_hostname_init);
-- 
1.9.0



From antonynpavlov at gmail.com  Tue Mar 25 12:50:58 2014
From: antonynpavlov at gmail.com (Antony Pavlov)
Date: Tue, 25 Mar 2014 20:50:58 +0400
Subject: [PATCH v3 7/8] MIPS: mach-xburst: drop serial.c
In-Reply-To: <1395766259-31866-1-git-send-email-antonynpavlov@gmail.com>
References: <1395766259-31866-1-git-send-email-antonynpavlov@gmail.com>
Message-ID: <1395766259-31866-8-git-send-email-antonynpavlov@gmail.com>

We use dts for serial port initialization,
so we have no need in mach-xburst/serial.c anymore.

Signed-off-by: Antony Pavlov <antonynpavlov at gmail.com>
---
 arch/mips/mach-xburst/Makefile |  1 -
 arch/mips/mach-xburst/serial.c | 60 ------------------------------------------
 2 files changed, 61 deletions(-)

diff --git a/arch/mips/mach-xburst/Makefile b/arch/mips/mach-xburst/Makefile
index 3e0cd73..e5634ba 100644
--- a/arch/mips/mach-xburst/Makefile
+++ b/arch/mips/mach-xburst/Makefile
@@ -1,2 +1 @@
-obj-y += serial.o
 obj-$(CONFIG_CPU_JZ4755) += csrc-jz4750.o reset-jz4750.o
diff --git a/arch/mips/mach-xburst/serial.c b/arch/mips/mach-xburst/serial.c
deleted file mode 100644
index acf5648..0000000
--- a/arch/mips/mach-xburst/serial.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- * Copyright (C) 2013 Antony Pavlov <antonynpavlov at gmail.com>
- *
- * Based on the linux kernel JZ4740 serial support:
- * Copyright (C) 2010, Lars-Peter Clausen <lars at metafoo.de>
- *
- * This file is part of barebox.
- * See file CREDITS for list of people who contributed to this project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2
- * as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <common.h>
-#include <ns16550.h>
-#include <io.h>
-#include <mach/devices.h>
-
-#define JZ_UART_SHIFT	2
-
-#define ier		(1 << JZ_UART_SHIFT)
-#define fcr		(2 << JZ_UART_SHIFT)
-
-static void jz_serial_reg_write(unsigned int val, unsigned long base,
-	unsigned char reg_offset)
-{
-	switch (reg_offset) {
-	case fcr:
-		val |= 0x10; /* Enable uart module */
-		break;
-	case ier:
-		val |= (val & 0x4) << 2;
-		break;
-	default:
-		break;
-	}
-
-	writeb(val & 0xff, (void *)(base + reg_offset));
-}
-
-struct device_d *jz_add_uart(int id, unsigned long base, unsigned int clock)
-{
-	struct NS16550_plat *serial_plat;
-
-	serial_plat = xzalloc(sizeof(*serial_plat));
-
-	serial_plat->shift = JZ_UART_SHIFT;
-	serial_plat->reg_write = &jz_serial_reg_write;
-	serial_plat->clock = clock;
-
-	return add_ns16550_device(id, base, 8 << JZ_UART_SHIFT,
-			IORESOURCE_MEM_8BIT, serial_plat);
-}
-- 
1.9.0



From antonynpavlov at gmail.com  Tue Mar 25 12:50:59 2014
From: antonynpavlov at gmail.com (Antony Pavlov)
Date: Tue, 25 Mar 2014 20:50:59 +0400
Subject: [PATCH v3 8/8] MIPS: boards: rename rzx50 -> ritmix-rzx50
In-Reply-To: <1395766259-31866-1-git-send-email-antonynpavlov@gmail.com>
References: <1395766259-31866-1-git-send-email-antonynpavlov@gmail.com>
Message-ID: <1395766259-31866-9-git-send-email-antonynpavlov@gmail.com>

All MIPS board use <vendor>-<model> name template save Ritmix RZX-50.
This commit fixes this inconsistency.

Signed-off-by: Antony Pavlov <antonynpavlov at gmail.com>
---
 Documentation/boards.dox                           |  2 +-
 arch/mips/Makefile                                 |  2 +-
 arch/mips/boards/ritmix-rzx50/Makefile             |  1 +
 .../ritmix-rzx50/include/board/board_pbl_start.h   | 43 ++++++++++++++++++++
 .../boards/ritmix-rzx50/include/board/debug_ll.h   | 23 +++++++++++
 arch/mips/boards/ritmix-rzx50/ritmix-rzx50.dox     | 46 ++++++++++++++++++++++
 arch/mips/boards/ritmix-rzx50/serial.c             | 27 +++++++++++++
 arch/mips/boards/rzx50/Makefile                    |  1 -
 .../boards/rzx50/include/board/board_pbl_start.h   | 43 --------------------
 arch/mips/boards/rzx50/include/board/debug_ll.h    | 23 -----------
 arch/mips/boards/rzx50/rzx50.dox                   | 46 ----------------------
 arch/mips/boards/rzx50/serial.c                    | 27 -------------
 arch/mips/configs/ritmix-rzx50_defconfig           | 39 ++++++++++++++++++
 arch/mips/configs/rzx50_defconfig                  | 39 ------------------
 arch/mips/mach-xburst/mach-xburst.dox              |  2 +-
 15 files changed, 182 insertions(+), 182 deletions(-)

diff --git a/Documentation/boards.dox b/Documentation/boards.dox
index 9a14aee..42bc5e6 100644
--- a/Documentation/boards.dox
+++ b/Documentation/boards.dox
@@ -59,7 +59,7 @@ MIPS type:
 @li @subpage dlink_dir_320
 @li @subpage loongson_ls1b
 @li @subpage qemu_malta
- at li @subpage rzx50
+ at li @subpage ritmix-rzx50
 
 */
 
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 8986fcf..e3d65c8 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -85,7 +85,7 @@ machine-$(CONFIG_MACH_MIPS_LOONGSON)	:= loongson
 board-$(CONFIG_BOARD_LOONGSON_TECH_LS1B)	:= loongson-ls1b
 
 machine-$(CONFIG_MACH_MIPS_XBURST)	:= xburst
-board-$(CONFIG_BOARD_RZX50)	:= rzx50
+board-$(CONFIG_BOARD_RZX50)	:= ritmix-rzx50
 
 machdirs := $(patsubst %,arch/mips/mach-%/,$(machine-y))
 
diff --git a/arch/mips/boards/ritmix-rzx50/Makefile b/arch/mips/boards/ritmix-rzx50/Makefile
new file mode 100644
index 0000000..31c0629
--- /dev/null
+++ b/arch/mips/boards/ritmix-rzx50/Makefile
@@ -0,0 +1 @@
+obj-y += serial.o
diff --git a/arch/mips/boards/ritmix-rzx50/include/board/board_pbl_start.h b/arch/mips/boards/ritmix-rzx50/include/board/board_pbl_start.h
new file mode 100644
index 0000000..fb914d9
--- /dev/null
+++ b/arch/mips/boards/ritmix-rzx50/include/board/board_pbl_start.h
@@ -0,0 +1,43 @@
+/*
+ * Startup Code for Ritmix RZX-50 board
+ *
+ * Copyright (C) 2013 Antony Pavlov <antonynpavlov at gmail.com>
+ *
+ * This file is part of barebox.
+ * See file CREDITS for list of people who contributed to this project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <asm/pbl_macros.h>
+#include <mach/debug_ll.h>
+#include <asm/pbl_nmon.h>
+
+	.macro	board_pbl_start
+	.set	push
+	.set	noreorder
+
+	mips_disable_interrupts
+
+	/* CPU/SoC specific setup ... */
+	/* ... absent */
+
+	debug_ll_ns16550_init
+
+	debug_ll_ns16550_outc '.'
+	debug_ll_ns16550_outnl
+
+	mips_nmon
+
+	copy_to_link_location	pbl_start
+
+	.set	pop
+	.endm
diff --git a/arch/mips/boards/ritmix-rzx50/include/board/debug_ll.h b/arch/mips/boards/ritmix-rzx50/include/board/debug_ll.h
new file mode 100644
index 0000000..7ae0e2a
--- /dev/null
+++ b/arch/mips/boards/ritmix-rzx50/include/board/debug_ll.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (C) 2012 Antony Pavlov <antonynpavlov at gmail.com>
+ *
+ * This file is part of barebox.
+ * See file CREDITS for list of people who contributed to this project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __INCLUDE_RZX50_BOARD_DEBUG_LL_H__
+#define __INCLUDE_RZX50_BOARD_DEBUG_LL_H__
+
+#include <mach/debug_ll_jz4750d.h>
+
+#endif  /* __INCLUDE_RZX50_BOARD_DEBUG_LL_H__ */
diff --git a/arch/mips/boards/ritmix-rzx50/ritmix-rzx50.dox b/arch/mips/boards/ritmix-rzx50/ritmix-rzx50.dox
new file mode 100644
index 0000000..5ec8194
--- /dev/null
+++ b/arch/mips/boards/ritmix-rzx50/ritmix-rzx50.dox
@@ -0,0 +1,46 @@
+/** @page ritmix-rzx50 Ritmix RZX-50 game console
+
+Ritmix RZX-50 is a portable game console for the Russian market.
+
+The portable game console has
+ at li Ingenic JZ4755 SoC;
+ at li 64 MiB SDRAM;
+ at li 4 GiB microSDHC card / 4 GiB NAND type Flash Memory;
+ at li RS232 serial interface (LV-TTL levels on the board!);
+ at li LCD display (480x272);
+ at li Video out interface;
+ at li 1xUSB interface;
+ at li buttons.
+
+The game console uses U-Boot 1.1.6 as bootloader.
+
+barebox-rzx50 mini-howto:
+
+1. Connect to the game console's UART (see. http://a320.emulate.su/2012/01/19/uart-na-ritmix-rzx-50/);
+
+2. Unblock U-Boot console (see. http://a320.emulate.su/2012/01/25/rzx-50-dostup-k-konsoli-u-boot/); Please note that U-Boot's Zmodem support does not work;
+
+3. Boot Ritmix linux and login;
+
+4. Upload barebox.bin via Zmodem
+ at verbatim
+  # cd /tmp
+  # rz
+ at endverbatim
+
+5. Write barebox to onboard flash
+ at verbatim
+  # dd if=barebox.bin of=/dev/mmcblk0 seek=1048576 bs=1 count=262144
+ at endverbatim
+
+6. Reboot RZX-50, next in U-Boot console start barebox:
+ at verbatim
+  CETUS # msc read 0xa0800000 0x100000 0x40000; g a0800000
+ at endverbatim
+
+Ritmix RZX-50 links:
+ at li http://www.ritmixrussia.ru/products/252/entertainment/game/rzx-50
+ at li ftp://ftp.ingenic.cn/2soc/4755/JZ4755_ds.pdf
+ at li ftp://ftp.ingenic.cn/3sw/01linux/01loader/u-boot/u-boot-1.1.6-jz-20110719-r1728-add-jz4770.patch.bz2
+
+*/
diff --git a/arch/mips/boards/ritmix-rzx50/serial.c b/arch/mips/boards/ritmix-rzx50/serial.c
new file mode 100644
index 0000000..f1e8da0
--- /dev/null
+++ b/arch/mips/boards/ritmix-rzx50/serial.c
@@ -0,0 +1,27 @@
+/*
+ * Copyright (C) 2012 Antony Pavlov <antonynpavlov at gmail.com>
+ *
+ * This file is part of barebox.
+ * See file CREDITS for list of people who contributed to this project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <common.h>
+#include <init.h>
+
+static int rzx50_hostname_init(void)
+{
+	barebox_set_hostname("rzx50");
+
+	return 0;
+}
+console_initcall(rzx50_hostname_init);
diff --git a/arch/mips/boards/rzx50/Makefile b/arch/mips/boards/rzx50/Makefile
deleted file mode 100644
index 31c0629..0000000
--- a/arch/mips/boards/rzx50/Makefile
+++ /dev/null
@@ -1 +0,0 @@
-obj-y += serial.o
diff --git a/arch/mips/boards/rzx50/include/board/board_pbl_start.h b/arch/mips/boards/rzx50/include/board/board_pbl_start.h
deleted file mode 100644
index fb914d9..0000000
--- a/arch/mips/boards/rzx50/include/board/board_pbl_start.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * Startup Code for Ritmix RZX-50 board
- *
- * Copyright (C) 2013 Antony Pavlov <antonynpavlov at gmail.com>
- *
- * This file is part of barebox.
- * See file CREDITS for list of people who contributed to this project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2
- * as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <asm/pbl_macros.h>
-#include <mach/debug_ll.h>
-#include <asm/pbl_nmon.h>
-
-	.macro	board_pbl_start
-	.set	push
-	.set	noreorder
-
-	mips_disable_interrupts
-
-	/* CPU/SoC specific setup ... */
-	/* ... absent */
-
-	debug_ll_ns16550_init
-
-	debug_ll_ns16550_outc '.'
-	debug_ll_ns16550_outnl
-
-	mips_nmon
-
-	copy_to_link_location	pbl_start
-
-	.set	pop
-	.endm
diff --git a/arch/mips/boards/rzx50/include/board/debug_ll.h b/arch/mips/boards/rzx50/include/board/debug_ll.h
deleted file mode 100644
index 7ae0e2a..0000000
--- a/arch/mips/boards/rzx50/include/board/debug_ll.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * Copyright (C) 2012 Antony Pavlov <antonynpavlov at gmail.com>
- *
- * This file is part of barebox.
- * See file CREDITS for list of people who contributed to this project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2
- * as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef __INCLUDE_RZX50_BOARD_DEBUG_LL_H__
-#define __INCLUDE_RZX50_BOARD_DEBUG_LL_H__
-
-#include <mach/debug_ll_jz4750d.h>
-
-#endif  /* __INCLUDE_RZX50_BOARD_DEBUG_LL_H__ */
diff --git a/arch/mips/boards/rzx50/rzx50.dox b/arch/mips/boards/rzx50/rzx50.dox
deleted file mode 100644
index 963473c..0000000
--- a/arch/mips/boards/rzx50/rzx50.dox
+++ /dev/null
@@ -1,46 +0,0 @@
-/** @page rzx50 Ritmix RZX-50 game console
-
-Ritmix RZX-50 is a portable game console for the Russian market.
-
-The portable game console has
- at li Ingenic JZ4755 SoC;
- at li 64 MiB SDRAM;
- at li 4 GiB microSDHC card / 4 GiB NAND type Flash Memory;
- at li RS232 serial interface (LV-TTL levels on the board!);
- at li LCD display (480x272);
- at li Video out interface;
- at li 1xUSB interface;
- at li buttons.
-
-The game console uses U-Boot 1.1.6 as bootloader.
-
-barebox-rzx50 mini-howto:
-
-1. Connect to the game console's UART (see. http://a320.emulate.su/2012/01/19/uart-na-ritmix-rzx-50/);
-
-2. Unblock U-Boot console (see. http://a320.emulate.su/2012/01/25/rzx-50-dostup-k-konsoli-u-boot/); Please note that U-Boot's Zmodem support does not work;
-
-3. Boot Ritmix linux and login;
-
-4. Upload barebox.bin via Zmodem
- at verbatim
-  # cd /tmp
-  # rz
- at endverbatim
-
-5. Write barebox to onboard flash
- at verbatim
-  # dd if=barebox.bin of=/dev/mmcblk0 seek=1048576 bs=1 count=262144
- at endverbatim
-
-6. Reboot RZX-50, next in U-Boot console start barebox:
- at verbatim
-  CETUS # msc read 0xa0800000 0x100000 0x40000; g a0800000
- at endverbatim
-
-Ritmix RZX-50 links:
- at li http://www.ritmixrussia.ru/products/252/entertainment/game/rzx-50
- at li ftp://ftp.ingenic.cn/2soc/4755/JZ4755_ds.pdf
- at li ftp://ftp.ingenic.cn/3sw/01linux/01loader/u-boot/u-boot-1.1.6-jz-20110719-r1728-add-jz4770.patch.bz2
-
-*/
diff --git a/arch/mips/boards/rzx50/serial.c b/arch/mips/boards/rzx50/serial.c
deleted file mode 100644
index f1e8da0..0000000
--- a/arch/mips/boards/rzx50/serial.c
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * Copyright (C) 2012 Antony Pavlov <antonynpavlov at gmail.com>
- *
- * This file is part of barebox.
- * See file CREDITS for list of people who contributed to this project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2
- * as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <common.h>
-#include <init.h>
-
-static int rzx50_hostname_init(void)
-{
-	barebox_set_hostname("rzx50");
-
-	return 0;
-}
-console_initcall(rzx50_hostname_init);
diff --git a/arch/mips/configs/ritmix-rzx50_defconfig b/arch/mips/configs/ritmix-rzx50_defconfig
new file mode 100644
index 0000000..7691bae
--- /dev/null
+++ b/arch/mips/configs/ritmix-rzx50_defconfig
@@ -0,0 +1,39 @@
+CONFIG_BUILTIN_DTB=y
+CONFIG_BUILTIN_DTB_NAME="rzx50"
+CONFIG_MACH_MIPS_XBURST=y
+CONFIG_JZ4750D_DEBUG_LL_UART1=y
+CONFIG_PBL_IMAGE=y
+CONFIG_BAUDRATE=57600
+CONFIG_GLOB=y
+CONFIG_HUSH_FANCY_PROMPT=y
+CONFIG_HUSH_GETOPT=y
+CONFIG_CMDLINE_EDITING=y
+CONFIG_AUTO_COMPLETE=y
+# CONFIG_DEFAULT_ENVIRONMENT is not set
+CONFIG_DEBUG_LL=y
+CONFIG_CMD_EDIT=y
+CONFIG_CMD_SLEEP=y
+CONFIG_CMD_LOADB=y
+CONFIG_CMD_LOADY=y
+CONFIG_CMD_LOADS=y
+CONFIG_CMD_SAVES=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_IOMEM=y
+CONFIG_CMD_MD5SUM=y
+CONFIG_CMD_BOOTM_SHOW_TYPE=y
+CONFIG_CMD_BOOTM_VERBOSE=y
+CONFIG_CMD_BOOTM_INITRD=y
+CONFIG_CMD_BOOTM_OFTREE=y
+CONFIG_CMD_BOOTM_OFTREE_UIMAGE=y
+CONFIG_CMD_UIMAGE=y
+CONFIG_CMD_RESET=y
+CONFIG_CMD_POWEROFF=y
+CONFIG_CMD_GO=y
+CONFIG_CMD_OFTREE=y
+CONFIG_CMD_OF_PROPERTY=y
+CONFIG_CMD_OF_NODE=y
+CONFIG_OFDEVICE=y
+# CONFIG_SPI is not set
+CONFIG_SHA1=y
+CONFIG_SHA224=y
+CONFIG_SHA256=y
diff --git a/arch/mips/configs/rzx50_defconfig b/arch/mips/configs/rzx50_defconfig
deleted file mode 100644
index 7691bae..0000000
--- a/arch/mips/configs/rzx50_defconfig
+++ /dev/null
@@ -1,39 +0,0 @@
-CONFIG_BUILTIN_DTB=y
-CONFIG_BUILTIN_DTB_NAME="rzx50"
-CONFIG_MACH_MIPS_XBURST=y
-CONFIG_JZ4750D_DEBUG_LL_UART1=y
-CONFIG_PBL_IMAGE=y
-CONFIG_BAUDRATE=57600
-CONFIG_GLOB=y
-CONFIG_HUSH_FANCY_PROMPT=y
-CONFIG_HUSH_GETOPT=y
-CONFIG_CMDLINE_EDITING=y
-CONFIG_AUTO_COMPLETE=y
-# CONFIG_DEFAULT_ENVIRONMENT is not set
-CONFIG_DEBUG_LL=y
-CONFIG_CMD_EDIT=y
-CONFIG_CMD_SLEEP=y
-CONFIG_CMD_LOADB=y
-CONFIG_CMD_LOADY=y
-CONFIG_CMD_LOADS=y
-CONFIG_CMD_SAVES=y
-CONFIG_CMD_MEMINFO=y
-CONFIG_CMD_IOMEM=y
-CONFIG_CMD_MD5SUM=y
-CONFIG_CMD_BOOTM_SHOW_TYPE=y
-CONFIG_CMD_BOOTM_VERBOSE=y
-CONFIG_CMD_BOOTM_INITRD=y
-CONFIG_CMD_BOOTM_OFTREE=y
-CONFIG_CMD_BOOTM_OFTREE_UIMAGE=y
-CONFIG_CMD_UIMAGE=y
-CONFIG_CMD_RESET=y
-CONFIG_CMD_POWEROFF=y
-CONFIG_CMD_GO=y
-CONFIG_CMD_OFTREE=y
-CONFIG_CMD_OF_PROPERTY=y
-CONFIG_CMD_OF_NODE=y
-CONFIG_OFDEVICE=y
-# CONFIG_SPI is not set
-CONFIG_SHA1=y
-CONFIG_SHA224=y
-CONFIG_SHA256=y
diff --git a/arch/mips/mach-xburst/mach-xburst.dox b/arch/mips/mach-xburst/mach-xburst.dox
index a5e524d..052c05e 100644
--- a/arch/mips/mach-xburst/mach-xburst.dox
+++ b/arch/mips/mach-xburst/mach-xburst.dox
@@ -2,6 +2,6 @@
 
 @section xburst_boards XBurst-based boards
 
- at li @subpage rzx50
+ at li @subpage ritmix-rzx50
 
 */
-- 
1.9.0



From embedded.ashu at gmail.com  Wed Mar 26 01:55:07 2014
From: embedded.ashu at gmail.com (Ashutosh Singh)
Date: Wed, 26 Mar 2014 11:25:07 +0530
Subject: Can i access the barebox env from linux
Message-ID: <CA+dawz0DeA4+LWqamXp-tPDyWXW1JXfov-u2xdPBrSEsdFuZ3Q@mail.gmail.com>

Dear All,

Can i access the barebox env from linux.
Once the kernel boot if i want to create a directory and store some parameter
in default barebox /env folder without going to barebox from kernel.
For Eg.
I booted the board i get the linux promt and depending on some condition
i want to update the barebox env and create a directory in /env so the
next time
when barebox is loading the kernel image it can check that directory
and according
to that it can select the kernel from any source such as mmc, nand, nor, tftp.

What i observe that after the kernel boot i can see the barebox.env is
mounted as mtdblock5 (case of Nand)
now according to my understanding can i mount this partition modify
with my custom directory
and again boot so that this directory is available in barebox /env .

Thanks
Ashu


From s.hauer at pengutronix.de  Wed Mar 26 02:26:19 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Wed, 26 Mar 2014 07:26:19 +0100
Subject: Can i access the barebox env from linux
In-Reply-To: <CA+dawz0DeA4+LWqamXp-tPDyWXW1JXfov-u2xdPBrSEsdFuZ3Q@mail.gmail.com>
References: <CA+dawz0DeA4+LWqamXp-tPDyWXW1JXfov-u2xdPBrSEsdFuZ3Q@mail.gmail.com>
Message-ID: <20140326062619.GP17250@pengutronix.de>

On Wed, Mar 26, 2014 at 11:25:07AM +0530, Ashutosh Singh wrote:
> Dear All,
> 
> Can i access the barebox env from linux.
> Once the kernel boot if i want to create a directory and store some parameter
> in default barebox /env folder without going to barebox from kernel.
> For Eg.
> I booted the board i get the linux promt and depending on some condition
> i want to update the barebox env and create a directory in /env so the
> next time
> when barebox is loading the kernel image it can check that directory
> and according
> to that it can select the kernel from any source such as mmc, nand, nor, tftp.
> 
> What i observe that after the kernel boot i can see the barebox.env is
> mounted as mtdblock5 (case of Nand)
> now according to my understanding can i mount this partition modify
> with my custom directory
> and again boot so that this directory is available in barebox /env .

There is no filesystem support for the barebox environment, but you can
access the barebox env under Linux using the bareboxenv tool. Enable
 [x] build bareboxenv tool for target
and you'll find the tool under scripts/

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From s.hauer at pengutronix.de  Wed Mar 26 02:46:54 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Wed, 26 Mar 2014 07:46:54 +0100
Subject: [PATCH 1/3] common: driver: Allow for I/O mapped I/O in resource
 requests
In-Reply-To: <53316470.4040004@reverze.net>
References: <53316470.4040004@reverze.net>
Message-ID: <20140326064654.GQ17250@pengutronix.de>

On Tue, Mar 25, 2014 at 12:11:44PM +0100, Michel Stam wrote:
> The current resource framework is fully geared towards memory
> mapped I/O.
> This patch adds support for other types of I/O in the resource
> structures / function calls.
> ---
>  common/memory.c        |  2 +-
>  common/resource.c      | 18 ++++++++++++++++--
>  drivers/base/driver.c  | 36 ++++++++++++++++++------------------
>  include/driver.h       | 24 +++++++++++++++++-------
>  include/linux/ioport.h |  5 ++++-
>  5 files changed, 56 insertions(+), 29 deletions(-)
> 
> diff --git a/common/memory.c b/common/memory.c
> index c82bbaa..d36c8df 100644
> --- a/common/memory.c
> +++ b/common/memory.c
> @@ -148,7 +148,7 @@ struct resource *request_sdram_region(const char
> *name, resource_size_t start,
>  	for_each_memory_bank(bank) {
>  		struct resource *res;
>  -		res = request_region(bank->res, name, start, start + size - 1);
> +		res = request_region(bank->res, name, start, start + size - 1,
> IORESOURCE_MEM);
>  		if (res)
>  			return res;
>  	}
> diff --git a/common/resource.c b/common/resource.c
> index 5795e79..6600444 100644
> --- a/common/resource.c
> +++ b/common/resource.c
> @@ -38,7 +38,7 @@ static int init_resource(struct resource *res,
> const char *name)
>   */
>  struct resource *request_region(struct resource *parent,
>  		const char *name, resource_size_t start,
> -		resource_size_t end)
> +		resource_size_t end, int type)
>  {
>  	struct resource *r, *new;
>  @@ -70,6 +70,10 @@ struct resource *request_region(struct resource
> *parent,
>  			goto ok;
>  		if (start > r->end)
>  			continue;
> +
> +		if (type != resource_type(r->parent))
> +			continue;
> +
>  		debug("%s: 0x%08llx:0x%08llx conflicts with 0x%08llx:0x%08llx\n",
>  				__func__,
>  				(unsigned long long)start,
> @@ -89,6 +93,7 @@ ok:
>  	new->start = start;
>  	new->end = end;
>  	new->parent = parent;
> +	new->flags = type;
>  	list_add_tail(&new->sibling, &r->sibling);
>   	return new;
> @@ -123,5 +128,14 @@ struct resource iomem_resource = {
>  struct resource *request_iomem_region(const char *name,
>  		resource_size_t start, resource_size_t end)
>  {
> -	return request_region(&iomem_resource, name, start, end);
> +	return request_region(&iomem_resource, name, start, end, IORESOURCE_MEM);
> +}
> +
> +/*
> + * request an io region inside the io space
> + */
> +struct resource *request_io_region(const char *name,
> +		resource_size_t start, resource_size_t end,int type)
> +{
> +	return request_region(&iomem_resource, name, start, end, type);
>  }

iomem and memory really are two different resource trees. There is
memory from 0x0 to 0xffff and there are also ioports in this region. We
really have two toplevel resources. Also the iports do not span the
whole 32bit area, on x86 they are only up to 0xffff.
You would have to create a ioport command equivalent to the iomem
command we have now.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From alex.aring at gmail.com  Wed Mar 26 02:57:36 2014
From: alex.aring at gmail.com (Alexander Aring)
Date: Wed, 26 Mar 2014 07:57:36 +0100
Subject: Can i access the barebox env from linux
In-Reply-To: <20140326062619.GP17250@pengutronix.de>
References: <CA+dawz0DeA4+LWqamXp-tPDyWXW1JXfov-u2xdPBrSEsdFuZ3Q@mail.gmail.com>
 <20140326062619.GP17250@pengutronix.de>
Message-ID: <20140326065734.GA18805@omega.Speedport_W_921V_1_24_000>

Hi Sascha and Ashutosh,

On Wed, Mar 26, 2014 at 07:26:19AM +0100, Sascha Hauer wrote:
> On Wed, Mar 26, 2014 at 11:25:07AM +0530, Ashutosh Singh wrote:
> > Dear All,
> > 
> > Can i access the barebox env from linux.
> > Once the kernel boot if i want to create a directory and store some parameter
> > in default barebox /env folder without going to barebox from kernel.
> > For Eg.
> > I booted the board i get the linux promt and depending on some condition
> > i want to update the barebox env and create a directory in /env so the
> > next time
> > when barebox is loading the kernel image it can check that directory
> > and according
> > to that it can select the kernel from any source such as mmc, nand, nor, tftp.
> > 
> > What i observe that after the kernel boot i can see the barebox.env is
> > mounted as mtdblock5 (case of Nand)
> > now according to my understanding can i mount this partition modify
> > with my custom directory
> > and again boot so that this directory is available in barebox /env .
> 
> There is no filesystem support for the barebox environment, but you can
> access the barebox env under Linux using the bareboxenv tool. Enable
>  [x] build bareboxenv tool for target
> and you'll find the tool under scripts/
> 

I wrote fast some skript to handle a automatic write of the bareboxenv On
env changes. It use inotify to detect changes at the environment.

--- snip

#!/bin/sh 

MNT=$1
ENV=$2

bareboxenv -l $MNT $ENV

while true
do
inotifywait -e modify $MNT --excludei ".*.swp"
bareboxenv -s $MNT $ENV
done

--- snap

NOTE: Don't use this on nand partitions!

This script can be run as daemon on the target and will automatic write
the environment back. Usage: "./script $MNTPOINT $BBENV".


I hacked this in 10 seconds but it depends if it a mtd device then we
should use nandwrite etc... but maybe we can write a proper C
implementation, with inotify, mtd ioctl calls (if mtd), etc...

I mean this would be very easy to implemented. :-)

- Alex


From antonynpavlov at gmail.com  Wed Mar 26 03:43:16 2014
From: antonynpavlov at gmail.com (Antony Pavlov)
Date: Wed, 26 Mar 2014 11:43:16 +0400
Subject: on duplicating device tree clk constants
Message-ID: <20140326114316.26869b3b6dd537859df09a20@gmail.com>

Hi!

Just now I'm working on improvement of device tree support in barebox-mips.

I have examined some existing ARM device trees. I have a clock-related question.
I'll use tegra20 device tree as an example.

We have the include/dt-bindings/clock/tegra20-car.h file with clock numbers defines:

Here is a small part of the file:

  #define TEGRA20_CLK_CPU 0
  /* 1 */
  /* 2 */
  #define TEGRA20_CLK_AC97 3
  #define TEGRA20_CLK_RTC 4
  #define TEGRA20_CLK_TIMER 5
  #define TEGRA20_CLK_UARTA 6

At the other hand we have enum tegra20_clks definition in the drivers/clk/tegra/clk-tegra20.c file:

  enum tegra20_clks {
        cpu, ac97 = 3, rtc, timer, uarta, uartb, gpio, sdmmc2, i2s1 = 11, i2c1,
        ndflash, sdmmc1, sdmmc4, twc, pwm, i2s2, epp, gr2d = 21, usbd, isp,

I see that the constants are the same, but they have differrent names.

Can we drop duplicated definitions?

What device tree clock design pattern I have to use for new code?

--?
Best regards,
? Antony Pavlov


From s.hauer at pengutronix.de  Wed Mar 26 04:03:41 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Wed, 26 Mar 2014 09:03:41 +0100
Subject: [PATCH v3 0/8] MIPS: improve Ingenic JZ4755 device tree support
In-Reply-To: <1395766259-31866-1-git-send-email-antonynpavlov@gmail.com>
References: <1395766259-31866-1-git-send-email-antonynpavlov@gmail.com>
Message-ID: <20140326080341.GS17250@pengutronix.de>

On Tue, Mar 25, 2014 at 08:50:51PM +0400, Antony Pavlov wrote:
> This patcheseries moves Ingenic JZ4755 UART initialization
> into device tree and makes JZ4755 device tree organization
> more clear.
> 
> This patchseries is a part of work on Ingenic chips support
> and prepares MIPS board support switch to device tree.
> Next patchseries will add device tree Ingenic gpio, clk
> and pinctls support.

Applied, thanks

Sascha


-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From antonynpavlov at gmail.com  Wed Mar 26 04:29:25 2014
From: antonynpavlov at gmail.com (Antony Pavlov)
Date: Wed, 26 Mar 2014 12:29:25 +0400
Subject: [PATCH] MIPS: mach-xburst: fix DEBUG_LL=n build error
Message-ID: <1395822565-14283-1-git-send-email-antonynpavlov@gmail.com>

Here is my error log:

  CC      common/startup.o
In file included from arch/mips/mach-xburst/include/mach/debug_ll.h:25,
                 from include/debug_ll.h:31,
                 from common/startup.c:36:
arch/mips/include/asm/debug_ll_ns16550.h: In function 'PUTC_LL':
arch/mips/include/asm/debug_ll_ns16550.h:62: error: 'DEBUG_LL_UART_ADDR' undeclared (first use in this function)
arch/mips/include/asm/debug_ll_ns16550.h:62: error: (Each undeclared identifier is reported only once
arch/mips/include/asm/debug_ll_ns16550.h:62: error: for each function it appears in.)
make[1]: *** [common/startup.o] Error 1

Signed-off-by: Antony Pavlov <antonynpavlov at gmail.com>
---
 arch/mips/include/asm/debug_ll_ns16550.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/mips/include/asm/debug_ll_ns16550.h b/arch/mips/include/asm/debug_ll_ns16550.h
index f36010c..032f0a2 100644
--- a/arch/mips/include/asm/debug_ll_ns16550.h
+++ b/arch/mips/include/asm/debug_ll_ns16550.h
@@ -59,9 +59,11 @@
 
 static __inline__ void PUTC_LL(char ch)
 {
+#ifdef CONFIG_DEBUG_LL
 	while (!(__raw_readb((u8 *)DEBUG_LL_UART_ADDR + UART_LSR) & UART_LSR_THRE))
 		;
 	__raw_writeb(ch, (u8 *)DEBUG_LL_UART_ADDR + UART_THR);
+#endif /* CONFIG_DEBUG_LL */
 }
 #else /* __ASSEMBLY__ */
 /*
-- 
1.9.0



From antonynpavlov at gmail.com  Wed Mar 26 04:30:42 2014
From: antonynpavlov at gmail.com (Antony Pavlov)
Date: Wed, 26 Mar 2014 12:30:42 +0400
Subject: [PATCH] MIPS: lib: add BAREBOX_CLK_TABLE to linker script
Message-ID: <1395822642-14342-1-git-send-email-antonynpavlov@gmail.com>

This commit is based on
    commit fa1a406f7245c5482a17014d5b97e8948352e5a5
    Author: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
    Date:   Sat Nov 9 14:24:18 2013 +0100

        ARM: lib: add BAREBOX_CLK_TABLE to linker script

        This adds an .oftables section right before .dtb section with
        BAREBOX_CLK_TABLE to ARM linker script.

Signed-off-by: Antony Pavlov <antonynpavlov at gmail.com>
---
 arch/mips/lib/barebox.lds.S | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/mips/lib/barebox.lds.S b/arch/mips/lib/barebox.lds.S
index bc78d2b..4ee4252 100644
--- a/arch/mips/lib/barebox.lds.S
+++ b/arch/mips/lib/barebox.lds.S
@@ -69,6 +69,8 @@ SECTIONS
 	__usymtab : { BAREBOX_SYMS }
 	__usymtab_end = .;
 
+	.oftables : { BAREBOX_CLK_TABLE() }
+
 	.dtb : { BAREBOX_DTB() }
 
 	_edata = .;
-- 
1.9.0



From dev at lynxeye.de  Wed Mar 26 05:03:00 2014
From: dev at lynxeye.de (Lucas Stach)
Date: Wed, 26 Mar 2014 10:03:00 +0100
Subject: on duplicating device tree clk constants
In-Reply-To: <20140326114316.26869b3b6dd537859df09a20@gmail.com>
References: <20140326114316.26869b3b6dd537859df09a20@gmail.com>
Message-ID: <1395824580.2079.3.camel@tellur>

Am Mittwoch, den 26.03.2014, 11:43 +0400 schrieb Antony Pavlov:
> Hi!
> 
> Just now I'm working on improvement of device tree support in barebox-mips.
> 
> I have examined some existing ARM device trees. I have a clock-related question.
> I'll use tegra20 device tree as an example.
> 
> We have the include/dt-bindings/clock/tegra20-car.h file with clock numbers defines:
> 
> Here is a small part of the file:
> 
>   #define TEGRA20_CLK_CPU 0
>   /* 1 */
>   /* 2 */
>   #define TEGRA20_CLK_AC97 3
>   #define TEGRA20_CLK_RTC 4
>   #define TEGRA20_CLK_TIMER 5
>   #define TEGRA20_CLK_UARTA 6
> 
> At the other hand we have enum tegra20_clks definition in the drivers/clk/tegra/clk-tegra20.c file:
> 
>   enum tegra20_clks {
>         cpu, ac97 = 3, rtc, timer, uarta, uartb, gpio, sdmmc2, i2s1 = 11, i2c1,
>         ndflash, sdmmc1, sdmmc4, twc, pwm, i2s2, epp, gr2d = 21, usbd, isp,
> 
> I see that the constants are the same, but they have differrent names.
> 
> Can we drop duplicated definitions?
> 
> What device tree clock design pattern I have to use for new code?
> 
Right, the enum is still in the clock driver, as this was written before
the DT binding includes were there. I have some some additions to the
clock driver in the pipeline and will remove the enum in the course of
this.

So please if you write a new clock driver just use the DT includes. It
makes maintenance a lot easier.

Regards,
Lucas




From embedded.ashu at gmail.com  Wed Mar 26 07:14:30 2014
From: embedded.ashu at gmail.com (Ashutosh Singh)
Date: Wed, 26 Mar 2014 16:44:30 +0530
Subject: Can i access the barebox env from linux
In-Reply-To: <20140326065734.GA18805@omega.Speedport_W_921V_1_24_000>
References: <CA+dawz0DeA4+LWqamXp-tPDyWXW1JXfov-u2xdPBrSEsdFuZ3Q@mail.gmail.com>
 <20140326062619.GP17250@pengutronix.de>
 <20140326065734.GA18805@omega.Speedport_W_921V_1_24_000>
Message-ID: <CA+dawz1a0EVA5OvDGZjpchV13R8J5+hKS8hVOtmmi2HFef5spQ@mail.gmail.com>

Thanks Alex,

The script is quite helpful.
But since i am saving my barebox.env in nand and want to mount, modify
and write it back to nand.
Do you have a safer solution so that complete env data won't corrupted.

Here is my nand partition list created while booting :

Creating 8 MTD partitions on "omap2-nand.0":
[    1.127990] 0x000000000000-0x000000020000 : "nand0.xload"
[    1.135498] 0x000000020000-0x000000040000 : "nand0.xload_backup1"
[    1.143615] 0x000000040000-0x000000060000 : "nand0.xload_backup2"
[    1.151733] 0x000000060000-0x000000080000 : "nand0.xload_backup3"
[    1.159942] 0x000000080000-0x000000100000 : "nand0.barebox"
[    1.167755] 0x000000100000-0x000000120000 : "nand0.bareboxenv"
[    1.175506] 0x000000120000-0x000000920000 : "nand0.kernel"
[    1.189666] 0x000000920000-0x000020000000 : "nand0.root"

And the list in my rfs :

ls -l /dev/mtd
mtd0       mtd2       mtd4       mtd6       mtd8       mtdblock2  mtdblock6
mtd0ro     mtd2ro     mtd4ro     mtd6ro     mtd8ro     mtdblock3  mtdblock7
mtd1       mtd3       mtd5       mtd7       mtdblock0  mtdblock4  mtdblock8
mtd1ro     mtd3ro     mtd5ro     mtd7ro     mtdblock1  mtdblock5

~ Ashu

On Wed, Mar 26, 2014 at 12:27 PM, Alexander Aring <alex.aring at gmail.com> wrote:
> Hi Sascha and Ashutosh,
>
> On Wed, Mar 26, 2014 at 07:26:19AM +0100, Sascha Hauer wrote:
>> On Wed, Mar 26, 2014 at 11:25:07AM +0530, Ashutosh Singh wrote:
>> > Dear All,
>> >
>> > Can i access the barebox env from linux.
>> > Once the kernel boot if i want to create a directory and store some parameter
>> > in default barebox /env folder without going to barebox from kernel.
>> > For Eg.
>> > I booted the board i get the linux promt and depending on some condition
>> > i want to update the barebox env and create a directory in /env so the
>> > next time
>> > when barebox is loading the kernel image it can check that directory
>> > and according
>> > to that it can select the kernel from any source such as mmc, nand, nor, tftp.
>> >
>> > What i observe that after the kernel boot i can see the barebox.env is
>> > mounted as mtdblock5 (case of Nand)
>> > now according to my understanding can i mount this partition modify
>> > with my custom directory
>> > and again boot so that this directory is available in barebox /env .
>>
>> There is no filesystem support for the barebox environment, but you can
>> access the barebox env under Linux using the bareboxenv tool. Enable
>>  [x] build bareboxenv tool for target
>> and you'll find the tool under scripts/
>>
>
> I wrote fast some skript to handle a automatic write of the bareboxenv On
> env changes. It use inotify to detect changes at the environment.
>
> --- snip
>
> #!/bin/sh
>
> MNT=$1
> ENV=$2
>
> bareboxenv -l $MNT $ENV
>
> while true
> do
> inotifywait -e modify $MNT --excludei ".*.swp"
> bareboxenv -s $MNT $ENV
> done
>
> --- snap
>
> NOTE: Don't use this on nand partitions!
>
> This script can be run as daemon on the target and will automatic write
> the environment back. Usage: "./script $MNTPOINT $BBENV".
>
>
> I hacked this in 10 seconds but it depends if it a mtd device then we
> should use nandwrite etc... but maybe we can write a proper C
> implementation, with inotify, mtd ioctl calls (if mtd), etc...
>
> I mean this would be very easy to implemented. :-)
>
> - Alex


From alex.aring at gmail.com  Wed Mar 26 07:31:05 2014
From: alex.aring at gmail.com (Alexander Aring)
Date: Wed, 26 Mar 2014 12:31:05 +0100
Subject: Can i access the barebox env from linux
In-Reply-To: <CA+dawz1a0EVA5OvDGZjpchV13R8J5+hKS8hVOtmmi2HFef5spQ@mail.gmail.com>
References: <CA+dawz0DeA4+LWqamXp-tPDyWXW1JXfov-u2xdPBrSEsdFuZ3Q@mail.gmail.com>
 <20140326062619.GP17250@pengutronix.de>
 <20140326065734.GA18805@omega.Speedport_W_921V_1_24_000>
 <CA+dawz1a0EVA5OvDGZjpchV13R8J5+hKS8hVOtmmi2HFef5spQ@mail.gmail.com>
Message-ID: <20140326113103.GA9427@omega.Speedport_W_921V_1_24_000>

On Wed, Mar 26, 2014 at 04:44:30PM +0530, Ashutosh Singh wrote:
> Thanks Alex,
> 
> The script is quite helpful.
> But since i am saving my barebox.env in nand and want to mount, modify
> and write it back to nand.
> Do you have a safer solution so that complete env data won't corrupted.

1. You need to save the bareboxenv as image, the right place would be
   /tmp which is tmpfs and this uses ram for storing data. You need inotify
   support in kernel and I am sure tmpfs also supports inotify. You also need
   the inotify userspace utilities.

2. The image should write via nandwrite from mtd-utils [1]. Look for
   the nandwrite manpage. nandwrite should write the tmp-image from bbenv
   to your nand mtd device.



I know the nandwrite will make a better badblock handling... but if you
set your bbenv size exactly the eraseblock size so it doesn't matter...
because after badblock marking that eraseblock you don't have any bbenv
partition anymore :/

nandwrite uses the mtd api to write and I suppose they do something more
than only badblock handling, ECC calculation.... Nevertheless you should
ever use nandwrite to write images to your nand /dev/*.nand partition.

I don't have any time now to change the script for nandwrite and extract
to /tmp/bbenv/, etc..., sorry. We should do it right and implement a C
solution for that. :-) I don't have time to do that also, maybe at weekend.

I don't have also no nand device here, I need to use the nandsim module.
This will take some time to setup.


Sorry, but try to change the script yourself and then share it with us. I
will take a look and review it.

- Alex

[1] http://git.infradead.org/mtd-utils.git


From alex.aring at gmail.com  Wed Mar 26 07:33:01 2014
From: alex.aring at gmail.com (Alexander Aring)
Date: Wed, 26 Mar 2014 12:33:01 +0100
Subject: Can i access the barebox env from linux
In-Reply-To: <20140326113103.GA9427@omega.Speedport_W_921V_1_24_000>
References: <CA+dawz0DeA4+LWqamXp-tPDyWXW1JXfov-u2xdPBrSEsdFuZ3Q@mail.gmail.com>
 <20140326062619.GP17250@pengutronix.de>
 <20140326065734.GA18805@omega.Speedport_W_921V_1_24_000>
 <CA+dawz1a0EVA5OvDGZjpchV13R8J5+hKS8hVOtmmi2HFef5spQ@mail.gmail.com>
 <20140326113103.GA9427@omega.Speedport_W_921V_1_24_000>
Message-ID: <20140326113300.GB9427@omega.Speedport_W_921V_1_24_000>

On Wed, Mar 26, 2014 at 12:31:03PM +0100, Alexander Aring wrote:
> On Wed, Mar 26, 2014 at 04:44:30PM +0530, Ashutosh Singh wrote:
> > Thanks Alex,
> > 
> > The script is quite helpful.
> > But since i am saving my barebox.env in nand and want to mount, modify
> > and write it back to nand.
> > Do you have a safer solution so that complete env data won't corrupted.
> 
> 1. You need to save the bareboxenv as image, the right place would be
>    /tmp which is tmpfs and this uses ram for storing data. You need inotify
>    support in kernel and I am sure tmpfs also supports inotify. You also need
>    the inotify userspace utilities.
> 
> 2. The image should write via nandwrite from mtd-utils [1]. Look for
>    the nandwrite manpage. nandwrite should write the tmp-image from bbenv
>    to your nand mtd device.
> 

3. To read the image from bbenv partition you should also not use
   bareboxenv tool directly. Use nanddump for that and then use
   bareboxenv to extract these files to /tmp/bbenv or whatever.


From michel at reverze.net  Wed Mar 26 07:53:03 2014
From: michel at reverze.net (Michel Stam)
Date: Wed, 26 Mar 2014 12:53:03 +0100
Subject: Can i access the barebox env from linux
In-Reply-To: <20140326113300.GB9427@omega.Speedport_W_921V_1_24_000>
References: <CA+dawz0DeA4+LWqamXp-tPDyWXW1JXfov-u2xdPBrSEsdFuZ3Q@mail.gmail.com>
 <20140326062619.GP17250@pengutronix.de>
 <20140326065734.GA18805@omega.Speedport_W_921V_1_24_000>
 <CA+dawz1a0EVA5OvDGZjpchV13R8J5+hKS8hVOtmmi2HFef5spQ@mail.gmail.com>
 <20140326113103.GA9427@omega.Speedport_W_921V_1_24_000>
 <20140326113300.GB9427@omega.Speedport_W_921V_1_24_000>
Message-ID: <5332BF9F.8060308@reverze.net>

In case anyone is interested; for a barebox x86 project I wrote a 
library that overrides fopen/fclose/open/close/etc a while back, which 
allows read access to the environment sector if properly configured. I 
managed to get it working on arm/mips with mtdblock as well.

In the near future I'd like to write a kernel driver to read the 
filesystem properly, this was more of an experiment.

Cheers,

Michel
On 03/26/2014 12:33 PM, Alexander Aring wrote:
> On Wed, Mar 26, 2014 at 12:31:03PM +0100, Alexander Aring wrote:
>> On Wed, Mar 26, 2014 at 04:44:30PM +0530, Ashutosh Singh wrote:
>>> Thanks Alex,
>>>
>>> The script is quite helpful.
>>> But since i am saving my barebox.env in nand and want to mount, modify
>>> and write it back to nand.
>>> Do you have a safer solution so that complete env data won't corrupted.
>> 1. You need to save the bareboxenv as image, the right place would be
>>     /tmp which is tmpfs and this uses ram for storing data. You need inotify
>>     support in kernel and I am sure tmpfs also supports inotify. You also need
>>     the inotify userspace utilities.
>>
>> 2. The image should write via nandwrite from mtd-utils [1]. Look for
>>     the nandwrite manpage. nandwrite should write the tmp-image from bbenv
>>     to your nand mtd device.
>>
> 3. To read the image from bbenv partition you should also not use
>     bareboxenv tool directly. Use nanddump for that and then use
>     bareboxenv to extract these files to /tmp/bbenv or whatever.
>
> _______________________________________________
> barebox mailing list
> barebox at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/barebox


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From alex.aring at gmail.com  Wed Mar 26 07:58:57 2014
From: alex.aring at gmail.com (Alexander Aring)
Date: Wed, 26 Mar 2014 12:58:57 +0100
Subject: Can i access the barebox env from linux
In-Reply-To: <5332BF9F.8060308@reverze.net>
References: <CA+dawz0DeA4+LWqamXp-tPDyWXW1JXfov-u2xdPBrSEsdFuZ3Q@mail.gmail.com>
 <20140326062619.GP17250@pengutronix.de>
 <20140326065734.GA18805@omega.Speedport_W_921V_1_24_000>
 <CA+dawz1a0EVA5OvDGZjpchV13R8J5+hKS8hVOtmmi2HFef5spQ@mail.gmail.com>
 <20140326113103.GA9427@omega.Speedport_W_921V_1_24_000>
 <20140326113300.GB9427@omega.Speedport_W_921V_1_24_000>
 <5332BF9F.8060308@reverze.net>
Message-ID: <20140326115854.GA12190@omega.Speedport_W_921V_1_24_000>

On Wed, Mar 26, 2014 at 12:53:03PM +0100, Michel Stam wrote:
> In case anyone is interested; for a barebox x86 project I wrote a library
> that overrides fopen/fclose/open/close/etc a while back, which allows read
> access to the environment sector if properly configured. I managed to get it
> working on arm/mips with mtdblock as well.
> 
> In the near future I'd like to write a kernel driver to read the filesystem
> properly, this was more of an experiment.
> 
How does it work? As a kernel module, as registered filesystem under
/proc/filesystems ?

With fuse as userspace filesystem?

Or like the inotify solution?

- Alex


From michel at reverze.net  Wed Mar 26 08:14:39 2014
From: michel at reverze.net (Michel Stam)
Date: Wed, 26 Mar 2014 13:14:39 +0100
Subject: Can i access the barebox env from linux
In-Reply-To: <20140326115854.GA12190@omega.Speedport_W_921V_1_24_000>
References: <CA+dawz0DeA4+LWqamXp-tPDyWXW1JXfov-u2xdPBrSEsdFuZ3Q@mail.gmail.com>
 <20140326062619.GP17250@pengutronix.de>
 <20140326065734.GA18805@omega.Speedport_W_921V_1_24_000>
 <CA+dawz1a0EVA5OvDGZjpchV13R8J5+hKS8hVOtmmi2HFef5spQ@mail.gmail.com>
 <20140326113103.GA9427@omega.Speedport_W_921V_1_24_000>
 <20140326113300.GB9427@omega.Speedport_W_921V_1_24_000>
 <5332BF9F.8060308@reverze.net>
 <20140326115854.GA12190@omega.Speedport_W_921V_1_24_000>
Message-ID: <5332C4AF.4060009@reverze.net>

Hey Alex,

The current version? That is a library, quite ugly actually.
LD_PRELOAD=/lib/LIBRARY /command/to/execute

The preload overrides the libc calls to open/read/write files.
The command can then access the environment sector, read only. If the 
environment contains a /bin/init, then the file will be available from 
/bin/init if the library is preloaded. Memory footprint is around 
10kbyte RAM, or something like that. Its probably only usable for root, 
as it requires read access to the block device, something you wouldn't 
want to give all users.

As a kernel module I would make it a proper filesystem so you can do 
something like mount /dev/blockdev /path -t bbfs.
That kernel driver will probably be a long-term project, though.

Cheers,

Michel
On 03/26/2014 12:58 PM, Alexander Aring wrote:
> On Wed, Mar 26, 2014 at 12:53:03PM +0100, Michel Stam wrote:
>> In case anyone is interested; for a barebox x86 project I wrote a library
>> that overrides fopen/fclose/open/close/etc a while back, which allows read
>> access to the environment sector if properly configured. I managed to get it
>> working on arm/mips with mtdblock as well.
>>
>> In the near future I'd like to write a kernel driver to read the filesystem
>> properly, this was more of an experiment.
>>
> How does it work? As a kernel module, as registered filesystem under
> /proc/filesystems ?
>
> With fuse as userspace filesystem?
>
> Or like the inotify solution?
>
> - Alex


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From eric at eukrea.com  Wed Mar 26 16:22:42 2014
From: eric at eukrea.com (=?UTF-8?q?Eric=20B=C3=A9nard?=)
Date: Wed, 26 Mar 2014 21:22:42 +0100
Subject: [PATCH 2/3] MarSBoard: add new board
In-Reply-To: <1395865363-29307-1-git-send-email-eric@eukrea.com>
References: <1395865363-29307-1-git-send-email-eric@eukrea.com>
Message-ID: <1395865363-29307-2-git-send-email-eric@eukrea.com>

this board is produced by Embest/Element 14 and is based on i.MX6 Dual
The following features are tested :
    - UART2 (console)
    - eMMC
    - uSDCard
    - Ethernet
    - USB Host (through 2 ports hub)
    - I2C 1/2
    - SPI NOR Flash

Boot on SPI NOR and through USB loader are tested.

For more informations on this board :
http://www.embest-tech.com/shop/star/marsboard.html

Signed-off-by: Eric B?nard <eric at eukrea.com>
---
 arch/arm/boards/Makefile                           |   1 +
 arch/arm/boards/embest-marsboard/Makefile          |   3 +
 arch/arm/boards/embest-marsboard/board.c           |  90 +++++++++++++++++
 arch/arm/boards/embest-marsboard/env/config-board  |   6 ++
 .../flash-header-embest-marsboard.imxcfg           | 106 +++++++++++++++++++++
 arch/arm/boards/embest-marsboard/lowlevel.c        |  44 +++++++++
 arch/arm/dts/Makefile                              |   2 +
 arch/arm/mach-imx/Kconfig                          |   4 +
 images/Makefile.imx                                |   5 +
 9 files changed, 261 insertions(+)
 create mode 100644 arch/arm/boards/embest-marsboard/Makefile
 create mode 100644 arch/arm/boards/embest-marsboard/board.c
 create mode 100644 arch/arm/boards/embest-marsboard/env/config-board
 create mode 100644 arch/arm/boards/embest-marsboard/flash-header-embest-marsboard.imxcfg
 create mode 100644 arch/arm/boards/embest-marsboard/lowlevel.c

diff --git a/arch/arm/boards/Makefile b/arch/arm/boards/Makefile
index 4934a42..df2519e 100644
--- a/arch/arm/boards/Makefile
+++ b/arch/arm/boards/Makefile
@@ -29,6 +29,7 @@ obj-$(CONFIG_MACH_EDB9315A)			+= edb93xx/
 obj-$(CONFIG_MACH_EDB9315)			+= edb93xx/
 obj-$(CONFIG_MACH_EFIKA_MX_SMARTBOOK)		+= efika-mx-smartbook/
 obj-$(CONFIG_MACH_EMBEST_RIOTBOARD)		+= embest-riotboard/
+obj-$(CONFIG_MACH_EMBEST_MARSBOARD)		+= embest-marsboard/
 obj-$(CONFIG_MACH_EUKREA_CPUIMX25)		+= eukrea_cpuimx25/
 obj-$(CONFIG_MACH_EUKREA_CPUIMX27)		+= eukrea_cpuimx27/
 obj-$(CONFIG_MACH_EUKREA_CPUIMX35)		+= eukrea_cpuimx35/
diff --git a/arch/arm/boards/embest-marsboard/Makefile b/arch/arm/boards/embest-marsboard/Makefile
new file mode 100644
index 0000000..e77796c
--- /dev/null
+++ b/arch/arm/boards/embest-marsboard/Makefile
@@ -0,0 +1,3 @@
+obj-y += board.o flash-header-embest-marsboard.dcd.o
+extra-y += flash-header-embest-marsboard.dcd.S flash-header-embest-marsboard.dcd
+lwl-y += lowlevel.o
diff --git a/arch/arm/boards/embest-marsboard/board.c b/arch/arm/boards/embest-marsboard/board.c
new file mode 100644
index 0000000..9ee80ff
--- /dev/null
+++ b/arch/arm/boards/embest-marsboard/board.c
@@ -0,0 +1,90 @@
+/*
+ * Copyright (C) 2014 Eric B?nard <eric at eukrea.com>
+ * Copyright (C) 2013 Lucas Stach <l.stach at pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <asm/armlinux.h>
+#include <asm/io.h>
+#include <bootsource.h>
+#include <common.h>
+#include <environment.h>
+#include <envfs.h>
+#include <gpio.h>
+#include <init.h>
+#include <mach/bbu.h>
+#include <mach/generic.h>
+#include <mach/imx6-regs.h>
+#include <mach/imx6.h>
+#include <mfd/imx6q-iomuxc-gpr.h>
+#include <sizes.h>
+#include <linux/phy.h>
+
+static int ar8035_phy_fixup(struct phy_device *dev)
+{
+	u16 val;
+
+	/* Ar803x phy SmartEEE feature cause link status generates glitch,
+	 * which cause ethernet link down/up issue, so disable SmartEEE
+	 */
+	phy_write(dev, 0xd, 0x3);
+	phy_write(dev, 0xe, 0x805d);
+	phy_write(dev, 0xd, 0x4003);
+
+	val = phy_read(dev, 0xe);
+	phy_write(dev, 0xe, val & ~(1 << 8));
+
+	/* To enable AR8031 ouput a 125MHz clk from CLK_25M */
+	phy_write(dev, 0xd, 0x7);
+	phy_write(dev, 0xe, 0x8016);
+	phy_write(dev, 0xd, 0x4007);
+
+	val = phy_read(dev, 0xe);
+	val &= 0xffe3;
+	val |= 0x18;
+	phy_write(dev, 0xe, val);
+
+	/* introduce tx clock delay */
+	phy_write(dev, 0x1d, 0x5);
+	val = phy_read(dev, 0x1e);
+	val |= 0x0100;
+	phy_write(dev, 0x1e, val);
+
+	return 0;
+}
+
+static int marsboard_device_init(void)
+{
+	if (!of_machine_is_compatible("embest,marsboard"))
+		return 0;
+
+	phy_register_fixup_for_uid(0x004dd072, 0xffffffef, ar8035_phy_fixup);
+
+	imx6_bbu_internal_spi_i2c_register_handler("spiflash", "/dev/m25p0.barebox",
+			BBU_HANDLER_FLAG_DEFAULT, NULL, 0, 0);
+
+	return 0;
+}
+device_initcall(marsboard_device_init);
+
+static int marsboard_lwl_init(void)
+{
+	if (!of_machine_is_compatible("embest,marsboard"))
+		return 0;
+
+	barebox_set_hostname("marsboard");
+
+	imx6_init_lowlevel();
+
+	return 0;
+}
+postcore_initcall(marsboard_lwl_init);
diff --git a/arch/arm/boards/embest-marsboard/env/config-board b/arch/arm/boards/embest-marsboard/env/config-board
new file mode 100644
index 0000000..e8e8378
--- /dev/null
+++ b/arch/arm/boards/embest-marsboard/env/config-board
@@ -0,0 +1,6 @@
+#!/bin/sh
+
+# board defaults, do not change in running system. Change /env/config
+# instead
+
+global.linux.bootargs.base="console=ttymxc0,115200"
diff --git a/arch/arm/boards/embest-marsboard/flash-header-embest-marsboard.imxcfg b/arch/arm/boards/embest-marsboard/flash-header-embest-marsboard.imxcfg
new file mode 100644
index 0000000..60a39fe
--- /dev/null
+++ b/arch/arm/boards/embest-marsboard/flash-header-embest-marsboard.imxcfg
@@ -0,0 +1,106 @@
+soc imx6
+loadaddr 0x20000000
+dcdofs 0x400
+
+wm 32 0x020e05a8 0x00000030
+wm 32 0x020e05b0 0x00000030
+wm 32 0x020e0524 0x00000030
+wm 32 0x020e051c 0x00000030
+wm 32 0x020e0518 0x00000030
+wm 32 0x020e050c 0x00000030
+wm 32 0x020e05b8 0x00000030
+wm 32 0x020e05c0 0x00000030
+wm 32 0x020e05ac 0x00020030
+wm 32 0x020e05b4 0x00020030
+wm 32 0x020e0528 0x00020030
+wm 32 0x020e0520 0x00020030
+wm 32 0x020e0514 0x00020030
+wm 32 0x020e0510 0x00020030
+wm 32 0x020e05bc 0x00020030
+wm 32 0x020e05c4 0x00020030
+wm 32 0x020e056c 0x00020030
+wm 32 0x020e0578 0x00020030
+wm 32 0x020e0588 0x00020030
+wm 32 0x020e0594 0x00020030
+wm 32 0x020e057c 0x00020030
+wm 32 0x020e0590 0x00003000
+wm 32 0x020e0598 0x00003000
+wm 32 0x020e058c 0x00000000
+wm 32 0x020e059c 0x00003030
+wm 32 0x020e05a0 0x00003030
+wm 32 0x020e0784 0x00000030
+wm 32 0x020e0788 0x00000030
+wm 32 0x020e0794 0x00000030
+wm 32 0x020e079c 0x00000030
+wm 32 0x020e07a0 0x00000030
+wm 32 0x020e07a4 0x00000030
+wm 32 0x020e07a8 0x00000030
+wm 32 0x020e0748 0x00000030
+wm 32 0x020e074c 0x00000030
+wm 32 0x020e0750 0x00020000
+wm 32 0x020e0758 0x00000000
+wm 32 0x020e0774 0x00020000
+wm 32 0x020e078c 0x00000030
+wm 32 0x020e0798 0x000c0000
+wm 32 0x021b081c 0x33333333
+wm 32 0x021b0820 0x33333333
+wm 32 0x021b0824 0x33333333
+wm 32 0x021b0828 0x33333333
+wm 32 0x021b481c 0x33333333
+wm 32 0x021b4820 0x33333333
+wm 32 0x021b4824 0x33333333
+wm 32 0x021b4828 0x33333333
+wm 32 0x021b0018 0x00081740
+wm 32 0x021b001c 0x00008000
+wm 32 0x021b000c 0x555a7975
+wm 32 0x021b0010 0xff538e64
+wm 32 0x021b0014 0x01ff00db
+wm 32 0x021b002c 0x000026d2
+wm 32 0x021b0030 0x005b0e21
+wm 32 0x021b0008 0x09444040
+wm 32 0x021b0004 0x00025576
+wm 32 0x021b0040 0x00000027
+wm 32 0x021b0000 0x831a0000
+wm 32 0x021b001c 0x04088032
+wm 32 0x021b001c 0x0408803a
+wm 32 0x021b001c 0x00008033
+wm 32 0x021b001c 0x0000803b
+wm 32 0x021b001c 0x00428031
+wm 32 0x021b001c 0x00428039
+wm 32 0x021b001c 0x09408030
+wm 32 0x021b001c 0x09408038
+wm 32 0x021b001c 0x04008040
+wm 32 0x021b001c 0x04008048
+wm 32 0x021b0800 0xa1380003
+wm 32 0x021b4800 0xa1380003
+wm 32 0x021b0020 0x00005800
+wm 32 0x021b0818 0x00022227
+wm 32 0x021b4818 0x00022227
+wm 32 0x021b083c 0x434b0350
+wm 32 0x021b0840 0x034c0359
+wm 32 0x021b483c 0x434b0350
+wm 32 0x021b4840 0x03650348
+wm 32 0x021b0848 0x4436383b
+wm 32 0x021b4848 0x39393341
+wm 32 0x021b0850 0x35373933
+wm 32 0x021b4850 0x48254A36
+wm 32 0x021b080c 0x001f001f
+wm 32 0x021b0810 0x001f001f
+wm 32 0x021b480c 0x00440044
+wm 32 0x021b4810 0x00440044
+wm 32 0x021b08b8 0x00000800
+wm 32 0x021b48b8 0x00000800
+wm 32 0x021b001c 0x00000000
+wm 32 0x021b0404 0x00011006
+wm 32 0x020c4068 0x00c03f3f
+wm 32 0x020c406c 0x0030fc03
+wm 32 0x020c4070 0x0fffc000
+wm 32 0x020c4074 0x3ff00000
+wm 32 0x020c4078 0x00fff300
+wm 32 0x020c407c 0x0f0000c3
+wm 32 0x020c4080 0x000003ff
+/* enable AXI cache for VDOA/VPU/IPU */
+wm 32 0x020e0010 0xf00000cf
+/* set IPU AXI-id0 Qos=0xf(bypass AXI-id1 Qos=0x7 */
+wm 32 0x020e0018 0x007f007f
+wm 32 0x020e001c 0x007f007f
diff --git a/arch/arm/boards/embest-marsboard/lowlevel.c b/arch/arm/boards/embest-marsboard/lowlevel.c
new file mode 100644
index 0000000..47f0769
--- /dev/null
+++ b/arch/arm/boards/embest-marsboard/lowlevel.c
@@ -0,0 +1,44 @@
+#include <debug_ll.h>
+#include <common.h>
+#include <sizes.h>
+#include <io.h>
+#include <asm/barebox-arm-head.h>
+#include <asm/barebox-arm.h>
+#include <asm/sections.h>
+#include <asm/cache.h>
+#include <asm/mmu.h>
+#include <mach/imx6-mmdc.h>
+#include <mach/imx6.h>
+
+static inline void setup_uart(void)
+{
+	/* Enable UART for lowlevel debugging purposes */
+	writel(0x00000000, 0x021e8080);
+	writel(0x00004027, 0x021e8084);
+	writel(0x00000704, 0x021e8088);
+	writel(0x00000a81, 0x021e8090);
+	writel(0x0000002b, 0x021e809c);
+	writel(0x00013880, 0x021e80b0);
+	writel(0x0000047f, 0x021e80a4);
+	writel(0x0000c34f, 0x021e80a8);
+	writel(0x00000001, 0x021e8080);
+}
+
+extern char __dtb_imx6q_marsboard_start[];
+
+ENTRY_FUNCTION(start_imx6q_marsboard, r0, r1, r2)
+{
+	uint32_t fdt;
+
+	arm_cpu_lowlevel_init();
+
+	if (IS_ENABLED(CONFIG_DEBUG_LL)) {
+		writel(0x4, 0x020e016c);
+		setup_uart();
+		putc_ll('a');
+	}
+
+	fdt = (uint32_t)__dtb_imx6q_marsboard_start - get_runtime_offset();
+
+	barebox_arm_entry(0x10000000, SZ_1G, fdt);
+}
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 32fa44b..f6d00c1 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -26,6 +26,7 @@ dtb-$(CONFIG_ARCH_IMX6) += imx6q-gk802.dtb \
 	imx6q-nitrogen6x.dtb \
 	imx6dl-nitrogen6x.dtb \
 	imx6s-riotboard.dtb \
+	imx6q-marsboard.dtb \
 	imx6q-udoo.dtb
 dtb-$(CONFIG_ARCH_MVEBU) += dove-cubox-bb.dtb
 dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_cyclone5_sockit.dtb \
@@ -40,6 +41,7 @@ obj-$(CONFIG_BUILTIN_DTB) += $(BUILTIN_DTB).dtb.o
 pbl-$(CONFIG_MACH_BEAGLEBONE) += am335x-bone.dtb.o am335x-boneblack.dtb.o
 pbl-$(CONFIG_MACH_EFIKA_MX_SMARTBOOK) += imx51-genesi-efika-sb.dtb.o
 pbl-$(CONFIG_MACH_EMBEST_RIOTBOARD) += imx6s-riotboard.dtb.o
+pbl-$(CONFIG_MACH_EMBEST_MARSBOARD) += imx6q-marsboard.dtb.o
 pbl-$(CONFIG_MACH_FREESCALE_MX51_PDK) += imx51-babbage.dtb.o
 pbl-$(CONFIG_MACH_FREESCALE_MX53_LOCO) += imx53-qsb.dtb.o imx53-qsrb.dtb.o
 pbl-$(CONFIG_MACH_FREESCALE_MX53_VMX53) += imx53-voipac-bsb.dtb.o
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 15b78e2..a5b87e8 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -243,6 +243,10 @@ config MACH_SOLIDRUN_HUMMINGBOARD
 	bool "SolidRun Hummingboard"
 	select ARCH_IMX6
 
+config MACH_EMBEST_MARSBOARD
+	bool "Embest MarSBoard"
+	select ARCH_IMX6
+
 config MACH_EMBEST_RIOTBOARD
 	bool "Embest RIoTboard"
 	select ARCH_IMX6
diff --git a/images/Makefile.imx b/images/Makefile.imx
index bd1b300..7d927ce 100644
--- a/images/Makefile.imx
+++ b/images/Makefile.imx
@@ -148,3 +148,8 @@ pblx-$(CONFIG_MACH_EMBEST_RIOTBOARD) += start_imx6s_riotboard
 CFG_start_imx6s_riotboard.pblx.imximg = $(board)/embest-riotboard/flash-header-embest-riotboard.imxcfg
 FILE_barebox-embest-imx6s-riotboard.img = start_imx6s_riotboard.pblx.imximg
 image-$(CONFIG_MACH_EMBEST_RIOTBOARD) += barebox-embest-imx6s-riotboard.img
+
+pblx-$(CONFIG_MACH_EMBEST_MARSBOARD) += start_imx6q_marsboard
+CFG_start_imx6q_marsboard.pblx.imximg = $(board)/embest-marsboard/flash-header-embest-marsboard.imxcfg
+FILE_barebox-embest-imx6q-marsboard.img = start_imx6q_marsboard.pblx.imximg
+image-$(CONFIG_MACH_EMBEST_MARSBOARD) += barebox-embest-imx6q-marsboard.img
-- 
1.8.5.3



From eric at eukrea.com  Wed Mar 26 16:22:43 2014
From: eric at eukrea.com (=?UTF-8?q?Eric=20B=C3=A9nard?=)
Date: Wed, 26 Mar 2014 21:22:43 +0100
Subject: [PATCH 3/3] arm: add defconfig for Embest boards
In-Reply-To: <1395865363-29307-1-git-send-email-eric@eukrea.com>
References: <1395865363-29307-1-git-send-email-eric@eukrea.com>
Message-ID: <1395865363-29307-3-git-send-email-eric@eukrea.com>

Signed-off-by: Eric B?nard <eric at eukrea.com>
---
 arch/arm/configs/embest_defconfig | 100 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 100 insertions(+)
 create mode 100644 arch/arm/configs/embest_defconfig

diff --git a/arch/arm/configs/embest_defconfig b/arch/arm/configs/embest_defconfig
new file mode 100644
index 0000000..09b4d35
--- /dev/null
+++ b/arch/arm/configs/embest_defconfig
@@ -0,0 +1,100 @@
+CONFIG_ARCH_IMX=y
+CONFIG_IMX_MULTI_BOARDS=y
+CONFIG_MACH_EMBEST_MARSBOARD=y
+CONFIG_MACH_EMBEST_RIOTBOARD=y
+CONFIG_ARCH_IMX_USBLOADER=y
+CONFIG_IMX_IIM=y
+CONFIG_IMX_IIM_FUSE_BLOW=y
+CONFIG_THUMB2_BAREBOX=y
+CONFIG_CMD_ARM_MMUINFO=y
+CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
+CONFIG_ARM_UNWIND=y
+CONFIG_MMU=y
+CONFIG_TEXT_BASE=0x08f80000
+CONFIG_MALLOC_SIZE=0x4000000
+CONFIG_MALLOC_TLSF=y
+CONFIG_KALLSYMS=y
+CONFIG_RELOCATABLE=y
+CONFIG_LONGHELP=y
+CONFIG_HUSH_FANCY_PROMPT=y
+CONFIG_CMDLINE_EDITING=y
+CONFIG_AUTO_COMPLETE=y
+CONFIG_MENU=y
+CONFIG_CONSOLE_ACTIVATE_ALL=y
+CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y
+CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/embest-marsboard/env"
+CONFIG_DEFAULT_LOGLEVEL=6
+CONFIG_DEBUG_INFO=y
+CONFIG_CMD_EDIT=y
+CONFIG_CMD_SLEEP=y
+CONFIG_CMD_MSLEEP=y
+CONFIG_CMD_SAVEENV=y
+CONFIG_CMD_EXPORT=y
+CONFIG_CMD_READLINE=y
+CONFIG_CMD_MENU=y
+CONFIG_CMD_MENU_MANAGEMENT=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_TFTP=y
+CONFIG_CMD_ECHO_E=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_IOMEM=y
+CONFIG_CMD_CRC=y
+CONFIG_CMD_CRC_CMP=y
+CONFIG_CMD_MD5SUM=y
+CONFIG_CMD_FLASH=y
+CONFIG_CMD_BOOTM_SHOW_TYPE=y
+CONFIG_CMD_BOOTM_VERBOSE=y
+CONFIG_CMD_BOOTM_INITRD=y
+CONFIG_CMD_BOOTM_OFTREE=y
+CONFIG_CMD_BOOTM_OFTREE_UIMAGE=y
+CONFIG_CMD_BOOTM_AIMAGE=y
+# CONFIG_CMD_BOOTU is not set
+CONFIG_CMD_RESET=y
+CONFIG_CMD_GO=y
+CONFIG_CMD_TIMEOUT=y
+CONFIG_CMD_PARTITION=y
+CONFIG_CMD_MAGICVAR=y
+CONFIG_CMD_MAGICVAR_HELP=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_UNCOMPRESS=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_LED=y
+CONFIG_CMD_LED_TRIGGER=y
+CONFIG_CMD_MIITOOL=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DETECT=y
+CONFIG_NET=y
+CONFIG_NET_DHCP=y
+CONFIG_NET_PING=y
+CONFIG_OFDEVICE=y
+CONFIG_OF_BAREBOX_DRIVERS=y
+CONFIG_DRIVER_NET_FEC_IMX=y
+CONFIG_AT803X_PHY=y
+CONFIG_DRIVER_SPI_IMX=y
+CONFIG_I2C=y
+CONFIG_I2C_IMX=y
+CONFIG_MTD=y
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_SST25L=y
+CONFIG_USB=y
+CONFIG_USB_IMX_CHIPIDEA=y
+CONFIG_USB_EHCI=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DFU=y
+CONFIG_MCI=y
+CONFIG_MCI_IMX_ESDHC=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_LED_GPIO_OF=y
+CONFIG_LED_GPIO_RGB=y
+CONFIG_LED_GPIO_BICOLOR=y
+CONFIG_LED_TRIGGERS=y
+CONFIG_FS_EXT4=y
+CONFIG_FS_TFTP=y
+CONFIG_FS_NFS=y
+CONFIG_FS_FAT=y
+CONFIG_FS_FAT_WRITE=y
+CONFIG_FS_FAT_LFN=y
+CONFIG_LZO_DECOMPRESS=y
-- 
1.8.5.3



From eric at eukrea.com  Wed Mar 26 16:22:41 2014
From: eric at eukrea.com (=?UTF-8?q?Eric=20B=C3=A9nard?=)
Date: Wed, 26 Mar 2014 21:22:41 +0100
Subject: [PATCH 1/3] RiOTboard: add new board
Message-ID: <1395865363-29307-1-git-send-email-eric@eukrea.com>

this board is produced by Embest/Element 14 and is based on i.MX6 Solo
The following features are tested :
- UART2 (console)
- eMMC
- SDCard
- uSDCard
- Ethernet
- USB Host (through 4 ports hub)
- I2C 1/2/3
- 2 LEDs

Boot on eMMC and through USB loader are tested.

For more informations on this board : http://www.riotboard.org/

Signed-off-by: Eric B?nard <eric at eukrea.com>
---
 arch/arm/boards/Makefile                           |   1 +
 arch/arm/boards/embest-riotboard/Makefile          |   3 +
 arch/arm/boards/embest-riotboard/board.c           |  86 +++++
 arch/arm/boards/embest-riotboard/env/config-board  |   6 +
 .../flash-header-embest-riotboard.imxcfg           |  62 ++++
 arch/arm/boards/embest-riotboard/lowlevel.c        |  43 +++
 arch/arm/dts/Makefile                              |   2 +
 arch/arm/dts/imx6s-riotboard.dts                   | 386 +++++++++++++++++++++
 arch/arm/mach-imx/Kconfig                          |   4 +
 images/Makefile.imx                                |   5 +
 10 files changed, 598 insertions(+)
 create mode 100644 arch/arm/boards/embest-riotboard/Makefile
 create mode 100644 arch/arm/boards/embest-riotboard/board.c
 create mode 100644 arch/arm/boards/embest-riotboard/env/config-board
 create mode 100644 arch/arm/boards/embest-riotboard/flash-header-embest-riotboard.imxcfg
 create mode 100644 arch/arm/boards/embest-riotboard/lowlevel.c
 create mode 100644 arch/arm/dts/imx6s-riotboard.dts

diff --git a/arch/arm/boards/Makefile b/arch/arm/boards/Makefile
index 0d8c9cf..4934a42 100644
--- a/arch/arm/boards/Makefile
+++ b/arch/arm/boards/Makefile
@@ -28,6 +28,7 @@ obj-$(CONFIG_MACH_EDB9307)			+= edb93xx/
 obj-$(CONFIG_MACH_EDB9315A)			+= edb93xx/
 obj-$(CONFIG_MACH_EDB9315)			+= edb93xx/
 obj-$(CONFIG_MACH_EFIKA_MX_SMARTBOOK)		+= efika-mx-smartbook/
+obj-$(CONFIG_MACH_EMBEST_RIOTBOARD)		+= embest-riotboard/
 obj-$(CONFIG_MACH_EUKREA_CPUIMX25)		+= eukrea_cpuimx25/
 obj-$(CONFIG_MACH_EUKREA_CPUIMX27)		+= eukrea_cpuimx27/
 obj-$(CONFIG_MACH_EUKREA_CPUIMX35)		+= eukrea_cpuimx35/
diff --git a/arch/arm/boards/embest-riotboard/Makefile b/arch/arm/boards/embest-riotboard/Makefile
new file mode 100644
index 0000000..9f8e1f2
--- /dev/null
+++ b/arch/arm/boards/embest-riotboard/Makefile
@@ -0,0 +1,3 @@
+obj-y += board.o flash-header-embest-riotboard.dcd.o
+extra-y += flash-header-embest-riotboard.dcd.S flash-header-embest-riotboard.dcd
+lwl-y += lowlevel.o
diff --git a/arch/arm/boards/embest-riotboard/board.c b/arch/arm/boards/embest-riotboard/board.c
new file mode 100644
index 0000000..a33112f
--- /dev/null
+++ b/arch/arm/boards/embest-riotboard/board.c
@@ -0,0 +1,86 @@
+/*
+ * Copyright (C) 2014 Eric B?nard <eric at eukrea.com>
+ * Copyright (C) 2013 Lucas Stach <l.stach at pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <asm/armlinux.h>
+#include <asm/io.h>
+#include <bootsource.h>
+#include <common.h>
+#include <environment.h>
+#include <envfs.h>
+#include <gpio.h>
+#include <init.h>
+#include <mach/generic.h>
+#include <mach/imx6-regs.h>
+#include <mach/imx6.h>
+#include <mfd/imx6q-iomuxc-gpr.h>
+#include <sizes.h>
+#include <linux/phy.h>
+
+static int ar8035_phy_fixup(struct phy_device *dev)
+{
+	u16 val;
+
+	/* Ar803x phy SmartEEE feature cause link status generates glitch,
+	 * which cause ethernet link down/up issue, so disable SmartEEE
+	 */
+	phy_write(dev, 0xd, 0x3);
+	phy_write(dev, 0xe, 0x805d);
+	phy_write(dev, 0xd, 0x4003);
+
+	val = phy_read(dev, 0xe);
+	phy_write(dev, 0xe, val & ~(1 << 8));
+
+	/* To enable AR8031 ouput a 125MHz clk from CLK_25M */
+	phy_write(dev, 0xd, 0x7);
+	phy_write(dev, 0xe, 0x8016);
+	phy_write(dev, 0xd, 0x4007);
+
+	val = phy_read(dev, 0xe);
+	val &= 0xffe3;
+	val |= 0x18;
+	phy_write(dev, 0xe, val);
+
+	/* introduce tx clock delay */
+	phy_write(dev, 0x1d, 0x5);
+	val = phy_read(dev, 0x1e);
+	val |= 0x0100;
+	phy_write(dev, 0x1e, val);
+
+	return 0;
+}
+
+static int riotboard_device_init(void)
+{
+	if (!of_machine_is_compatible("embest,riotboard"))
+		return 0;
+
+	phy_register_fixup_for_uid(0x004dd072, 0xffffffef, ar8035_phy_fixup);
+
+	return 0;
+}
+device_initcall(riotboard_device_init);
+
+static int riotboard_lwl_init(void)
+{
+	if (!of_machine_is_compatible("embest,riotboard"))
+		return 0;
+
+	barebox_set_hostname("riotboard");
+
+	imx6_init_lowlevel();
+
+	return 0;
+}
+postcore_initcall(riotboard_lwl_init);
diff --git a/arch/arm/boards/embest-riotboard/env/config-board b/arch/arm/boards/embest-riotboard/env/config-board
new file mode 100644
index 0000000..e8e8378
--- /dev/null
+++ b/arch/arm/boards/embest-riotboard/env/config-board
@@ -0,0 +1,6 @@
+#!/bin/sh
+
+# board defaults, do not change in running system. Change /env/config
+# instead
+
+global.linux.bootargs.base="console=ttymxc0,115200"
diff --git a/arch/arm/boards/embest-riotboard/flash-header-embest-riotboard.imxcfg b/arch/arm/boards/embest-riotboard/flash-header-embest-riotboard.imxcfg
new file mode 100644
index 0000000..04e162b
--- /dev/null
+++ b/arch/arm/boards/embest-riotboard/flash-header-embest-riotboard.imxcfg
@@ -0,0 +1,62 @@
+loadaddr 0x20000000
+soc imx6
+dcdofs 0x400
+wm 32 0x020e0774 0x000c0000
+wm 32 0x020e0754 0x00000000
+wm 32 0x020e04ac 0x00000030
+wm 32 0x020e04b0 0x00000030
+wm 32 0x020e0464 0x00000030
+wm 32 0x020e0490 0x00000030
+wm 32 0x020e074c 0x00000030
+wm 32 0x020e0494 0x00000030
+wm 32 0x020e04a0 0x00000000
+wm 32 0x020e04b4 0x00000030
+wm 32 0x020e04b8 0x00000030
+wm 32 0x020e076c 0x00000030
+wm 32 0x020e0750 0x00020000
+wm 32 0x020e04bc 0x00000028
+wm 32 0x020e04c0 0x00000028
+wm 32 0x020e04c4 0x00000028
+wm 32 0x020e04c8 0x00000028
+wm 32 0x020e0760 0x00020000
+wm 32 0x020e0764 0x00000028
+wm 32 0x020e0770 0x00000028
+wm 32 0x020e0778 0x00000028
+wm 32 0x020e077c 0x00000028
+wm 32 0x020e0470 0x00000028
+wm 32 0x020e0474 0x00000028
+wm 32 0x020e0478 0x00000028
+wm 32 0x020e047c 0x00000028
+wm 32 0x021b0800 0xa1390003
+wm 32 0x021b080c 0x001f001f
+wm 32 0x021b0810 0x001f001f
+wm 32 0x021b083c 0x421c0216
+wm 32 0x021b0840 0x017b017a
+wm 32 0x021b0848 0x4b4a4e4c
+wm 32 0x021b0850 0x3f3f3334
+wm 32 0x021b081c 0x33333333
+wm 32 0x021b0820 0x33333333
+wm 32 0x021b0824 0x33333333
+wm 32 0x021b0828 0x33333333
+wm 32 0x021b08b8 0x00000800
+wm 32 0x021b0004 0x00020025
+wm 32 0x021b0008 0x00333030
+wm 32 0x021b000c 0x676b5313
+wm 32 0x021b0010 0xb66e8b63
+wm 32 0x021b0014 0x01ff00db
+wm 32 0x021b0018 0x00001740
+wm 32 0x021b001c 0x00008000
+wm 32 0x021b002c 0x000026d2
+wm 32 0x021b0030 0x006b1023
+wm 32 0x021b0040 0x00000027
+wm 32 0x021b0000 0x84190000
+wm 32 0x021b001c 0x04008032
+wm 32 0x021b001c 0x00008033
+wm 32 0x021b001c 0x00048031
+wm 32 0x021b001c 0x05208030
+wm 32 0x021b001c 0x04008040
+wm 32 0x021b0020 0x00005800
+wm 32 0x021b0818 0x00011117
+wm 32 0x021b0004 0x00025565
+wm 32 0x021b0404 0x00011006
+wm 32 0x021b001c 0x00000000
diff --git a/arch/arm/boards/embest-riotboard/lowlevel.c b/arch/arm/boards/embest-riotboard/lowlevel.c
new file mode 100644
index 0000000..814658a
--- /dev/null
+++ b/arch/arm/boards/embest-riotboard/lowlevel.c
@@ -0,0 +1,43 @@
+#include <debug_ll.h>
+#include <common.h>
+#include <sizes.h>
+#include <io.h>
+#include <asm/barebox-arm-head.h>
+#include <asm/barebox-arm.h>
+#include <asm/sections.h>
+#include <asm/cache.h>
+#include <asm/mmu.h>
+#include <mach/imx6-mmdc.h>
+#include <mach/imx6.h>
+
+static inline void setup_uart(void)
+{
+	/* Enable UART for lowlevel debugging purposes */
+	writel(0x00000000, 0x021e8080);
+	writel(0x00004027, 0x021e8084);
+	writel(0x00000704, 0x021e8088);
+	writel(0x00000a81, 0x021e8090);
+	writel(0x0000002b, 0x021e809c);
+	writel(0x00013880, 0x021e80b0);
+	writel(0x0000047f, 0x021e80a4);
+	writel(0x0000c34f, 0x021e80a8);
+	writel(0x00000001, 0x021e8080);
+}
+
+extern char __dtb_imx6s_riotboard_start[];
+
+ENTRY_FUNCTION(start_imx6s_riotboard, r0, r1, r2)
+{
+	uint32_t fdt;
+
+	arm_cpu_lowlevel_init();
+
+	if (IS_ENABLED(CONFIG_DEBUG_LL)) {
+		writel(0x4, 0x020e016c);
+		setup_uart();
+		putc_ll('a');
+	}
+
+	fdt = (uint32_t)__dtb_imx6s_riotboard_start - get_runtime_offset();
+	barebox_arm_entry(0x10000000, SZ_1G, fdt);
+}
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 6bac3b9..32fa44b 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -25,6 +25,7 @@ dtb-$(CONFIG_ARCH_IMX6) += imx6q-gk802.dtb \
 	imx6q-guf-santaro.dtb \
 	imx6q-nitrogen6x.dtb \
 	imx6dl-nitrogen6x.dtb \
+	imx6s-riotboard.dtb \
 	imx6q-udoo.dtb
 dtb-$(CONFIG_ARCH_MVEBU) += dove-cubox-bb.dtb
 dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_cyclone5_sockit.dtb \
@@ -38,6 +39,7 @@ obj-$(CONFIG_BUILTIN_DTB) += $(BUILTIN_DTB).dtb.o
 
 pbl-$(CONFIG_MACH_BEAGLEBONE) += am335x-bone.dtb.o am335x-boneblack.dtb.o
 pbl-$(CONFIG_MACH_EFIKA_MX_SMARTBOOK) += imx51-genesi-efika-sb.dtb.o
+pbl-$(CONFIG_MACH_EMBEST_RIOTBOARD) += imx6s-riotboard.dtb.o
 pbl-$(CONFIG_MACH_FREESCALE_MX51_PDK) += imx51-babbage.dtb.o
 pbl-$(CONFIG_MACH_FREESCALE_MX53_LOCO) += imx53-qsb.dtb.o imx53-qsrb.dtb.o
 pbl-$(CONFIG_MACH_FREESCALE_MX53_VMX53) += imx53-voipac-bsb.dtb.o
diff --git a/arch/arm/dts/imx6s-riotboard.dts b/arch/arm/dts/imx6s-riotboard.dts
new file mode 100644
index 0000000..3e1c263
--- /dev/null
+++ b/arch/arm/dts/imx6s-riotboard.dts
@@ -0,0 +1,386 @@
+/*
+ * Copyright (C) 2014 Eric B?nard - Eukr?a Electromatique
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License version 2.
+ */
+/dts-v1/;
+
+#include "imx6dl.dtsi"
+
+/ {
+	model = "RIoTboard Solo";
+	compatible = "embest,riotboard", "fsl,imx6dl";
+
+	chosen {
+		linux,stdout-path = &uart2;
+
+		environment at 0 {
+			compatible = "barebox,environment";
+			device-path = &usdhc4, "partname:barebox-environment";
+		};
+	};
+
+	memory {
+		reg = <0x10000000 0x40000000>;
+	};
+
+	gpio-leds {
+		compatible = "gpio-leds";
+
+		d45 {
+			label = "d45";
+			gpios = <&gpio5 2 1>;
+			linux,default-trigger = "heartbeat";
+		};
+
+		d46 {
+			label = "d46";
+			gpios = <&gpio3 28 1>;
+			linux,default-trigger = "default-on";
+		};
+	};
+
+
+	regulators {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		reg_3p3v: regulator at 1 {
+			compatible = "regulator-fixed";
+			reg = <1>;
+			regulator-name = "3P3V";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			regulator-always-on;
+		};
+	};
+};
+
+&iomuxc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_hog>;
+
+	imx6s-riotboard {
+		pinctrl_hog: hoggrp {
+			fsl,pins = <
+				MX6QDL_PAD_EIM_A25__GPIO5_IO02		0x80000000 /* LED D45 */
+				MX6QDL_PAD_EIM_D28__GPIO3_IO28		0x80000000 /* LED D46 */
+				MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16	0x80000000 /* PMIC_INT_B */
+				MX6QDL_PAD_GPIO_0__CCM_CLKO1		0x030b0 /* CAM_MCLK + SGTL_MCLK */
+			>;
+		};
+		pinctrl_uart2: uart2grp {
+			fsl,pins = <MX6QDL_UART2_PINGRP1>;
+		};
+		pinctrl_rgmii_ar8035: rgmii_ar8035 {
+			fsl,pins = <
+				MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0
+				MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0
+				/* AR8035 reset */
+				MX6QDL_PAD_EIM_D31__GPIO3_IO31		0x130b0
+				/* AR8035 interrupt */
+				MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28	0x80000000
+				/* GPIO16 -> AR8035 25MHz */
+				MX6QDL_PAD_GPIO_16__ENET_REF_CLK	0xc0000000
+				MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x80000000
+				MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b0b0
+				MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b0b0
+				MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b0b0
+				MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b0b0
+				MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b0b0
+				/* AR8035 CLK_25M --> ENET_REF_CLK (V22) */
+				MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x0a0b1
+				/* AR8035 pin strapping: IO voltage: pull up */
+				MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b0b0
+				/* AR8035 pin strapping: PHYADDR#0: pull down */
+				MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x130b0
+				/* AR8035 pin strapping: PHYADDR#1: pull down */
+				MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x130b0
+				/* AR8035 pin strapping: MODE#1: pull up */
+				MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b0b0
+				/* AR8035 pin strapping: MODE#3: pull up */
+				MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b0b0
+				/* AR8035 pin strapping: MODE#0: pull down */
+				MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x130b0
+			>;
+		};
+		pinctrl_usdhc4: usdhc4grp {
+			fsl,pins = <
+				MX6QDL_PAD_SD4_CLK__SD4_CLK			0x80000000
+				MX6QDL_PAD_SD4_CMD__SD4_CMD			0x80000000
+				MX6QDL_PAD_SD4_DAT0__SD4_DATA0			0x80000000
+				MX6QDL_PAD_SD4_DAT1__SD4_DATA1			0x80000000
+				MX6QDL_PAD_SD4_DAT2__SD4_DATA2			0x80000000
+				MX6QDL_PAD_SD4_DAT3__SD4_DATA3			0x80000000
+			>;
+		};
+		pinctrl_usdhc2: usdhc2grp {
+			fsl,pins = <
+				MX6QDL_PAD_SD2_CLK__SD2_CLK			0x80000000
+				MX6QDL_PAD_SD2_CMD__SD2_CMD			0x80000000
+				MX6QDL_PAD_SD2_DAT0__SD2_DATA0			0x80000000
+				MX6QDL_PAD_SD2_DAT1__SD2_DATA1			0x80000000
+				MX6QDL_PAD_SD2_DAT2__SD2_DATA2			0x80000000
+				MX6QDL_PAD_SD2_DAT3__SD2_DATA3			0x80000000
+				MX6QDL_PAD_GPIO_2__GPIO1_IO02			0x80000000
+				MX6QDL_PAD_GPIO_4__GPIO1_IO04			0x80000000
+			>;
+		};
+		pinctrl_usdhc3: usdhc3grp {
+			fsl,pins = <
+				MX6QDL_PAD_SD3_CMD__SD3_CMD			0x80000000
+				MX6QDL_PAD_SD3_CLK__SD3_CLK			0x80000000
+				MX6QDL_PAD_SD3_DAT0__SD3_DATA0			0x80000000
+				MX6QDL_PAD_SD3_DAT1__SD3_DATA1			0x80000000
+				MX6QDL_PAD_SD3_DAT2__SD3_DATA2			0x80000000
+				MX6QDL_PAD_SD3_DAT3__SD3_DATA3			0x80000000
+				MX6QDL_PAD_SD3_DAT4__GPIO7_IO01			0x80000000
+				MX6QDL_PAD_SD3_DAT5__GPIO7_IO00			0x80000000
+			>;
+		};
+		pinctrl_usbotg: usbotggrp {
+			fsl,pins = <
+				MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID		0x80000000
+				MX6QDL_PAD_EIM_D22__USB_OTG_PWR			0x80000000
+				MX6QDL_PAD_EIM_D21__USB_OTG_OC			0x80000000
+			>;
+		};
+		pinctrl_i2c1_2: i2c1grp-2 {
+			fsl,pins = <
+				MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
+				MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
+			>;
+		};
+		pinctrl_i2c2_2: i2c2grp-2 {
+			fsl,pins = <
+				MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
+				MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
+			>;
+		};
+		pinctrl_i2c3_2: i2c3grp-2 {
+			fsl,pins = <
+				MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
+				MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
+			>;
+		};
+		pinctrl_i2c4_2: i2c4grp-2 {
+			fsl,pins = <
+				MX6QDL_PAD_GPIO_7__I2C4_SCL 0x4001b8b1
+				MX6QDL_PAD_GPIO_8__I2C4_SDA 0x4001b8b1
+			>;
+		};
+	};
+};
+
+&uart2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart2>;
+	status = "okay";
+};
+
+&fec {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_rgmii_ar8035>;
+	phy-mode = "rgmii";
+	phy-reset-duration = <2>;
+	phy-reset-gpios = <&gpio3 31 0>;
+	status = "okay";
+};
+
+&usdhc2 {
+	/* SD card socket - bottom */
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc2>;
+	bus-width = <4>;
+	cd-gpios = <&gpio1 4 0>;
+	wp-gpios = <&gpio1 2 0>;
+	status = "okay";
+	#address-cells = <1>;
+	#size-cells = <1>;
+};
+
+&usdhc3 {
+	/* uSD card socket - top */
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc3>;
+	bus-width = <4>;
+	cd-gpios = <&gpio7 0 0>;
+	wp-gpios = <&gpio7 1 0>;
+	status = "okay";
+	#address-cells = <1>;
+	#size-cells = <1>;
+};
+
+&usdhc4 {
+	/* eMMC */
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc4>;
+	bus-width = <4>;
+	non-removable;
+	status = "okay";
+
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	partition at 0 {
+		label = "barebox";
+		reg = <0x0 0x80000>;
+	};
+
+	partition at 1 {
+		label = "barebox-environment";
+		reg = <0x80000 0x80000>;
+	};
+};
+
+&usbh1 {
+	status = "okay";
+	phy_type = "utmi";
+	disable-over-current;
+};
+
+&usbotg {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usbotg>;
+	phy_type = "utmi";
+	dr_mode = "peripheral";
+	otg_id_pin_select_change;
+	status = "okay";
+};
+
+&i2c1 {
+	status = "okay";
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c1_2>;
+
+	pmic: pf0100 at 08 {
+		compatible = "pf0100-regulator";
+		reg = <0x08>;
+		interrupt-parent = <&gpio5>;
+		interrupts = <16 8>;
+
+		regulators {
+			reg_vddcore: sw1ab {
+				regulator-min-microvolt = <300000>;
+				regulator-max-microvolt = <1875000>;
+				regulator-always-on;
+			};
+
+			reg_vddsoc: sw1c {
+				regulator-min-microvolt = <300000>;
+				regulator-max-microvolt = <1875000>;
+				regulator-always-on;
+			};
+
+			reg_gen_3v3: sw2 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			reg_ddr_1v5a: sw3a {
+				regulator-min-microvolt = <400000>;
+				regulator-max-microvolt = <1975000>;
+				regulator-always-on;
+			};
+
+			reg_ddr_1v5b: sw3b {
+				regulator-min-microvolt = <400000>;
+				regulator-max-microvolt = <1975000>;
+				regulator-always-on;
+			};
+
+			reg_ddr_vtt: sw4 {
+				regulator-min-microvolt = <400000>;
+				regulator-max-microvolt = <1975000>;
+				regulator-always-on;
+			};
+
+			reg_5v_600mA: swbst {
+				regulator-min-microvolt = <5000000>;
+				regulator-max-microvolt = <5150000>;
+				regulator-always-on;
+			};
+
+			reg_snvs_3v: vsnvs {
+				regulator-min-microvolt = <1500000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-always-on;
+			};
+
+			reg_vrefddr: vrefddr {
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <750000>;
+				regulator-always-on;
+			};
+
+			reg_vgen1_1v5: vgen1 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1550000>;
+				/* not used */
+			};
+
+			reg_vgen2_1v2_eth: vgen2 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1550000>;
+				regulator-always-on;
+			};
+
+			reg_vgen3_2v8: vgen3 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			reg_vgen4_1v8: vgen4 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			reg_vgen5_2v5_sgtl: vgen5 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			reg_vgen6_3v3: vgen6 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+		};
+	};
+
+	codec: sgtl5000 at 0a {
+		compatible = "fsl,sgtl5000";
+		reg = <0x0a>;
+		clocks = <&clks 201>;
+		VDDA-supply = <&reg_vgen5_2v5_sgtl>;
+		VDDIO-supply = <&reg_3p3v>;
+	};
+};
+
+&i2c2 {
+	status = "okay";
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c2_2>;
+};
+
+&i2c3 {
+	status = "okay";
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c3_2>;
+};
+
+&i2c4 {
+	status = "okay";
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c4_2>;
+};
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index b7e7533..15b78e2 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -243,6 +243,10 @@ config MACH_SOLIDRUN_HUMMINGBOARD
 	bool "SolidRun Hummingboard"
 	select ARCH_IMX6
 
+config MACH_EMBEST_RIOTBOARD
+	bool "Embest RIoTboard"
+	select ARCH_IMX6
+
 config MACH_UDOO
 	bool "Freescale i.MX6 UDOO Board"
 	select ARCH_IMX6
diff --git a/images/Makefile.imx b/images/Makefile.imx
index 5b650de..bd1b300 100644
--- a/images/Makefile.imx
+++ b/images/Makefile.imx
@@ -143,3 +143,8 @@ pblx-$(CONFIG_MACH_UDOO) += start_imx6_udoo
 CFG_start_imx6_udoo.pblx.imximg = $(board)/udoo/flash-header-mx6-udoo.imxcfg
 FILE_barebox-udoo-imx6q.img = start_imx6_udoo.pblx.imximg
 image-$(CONFIG_MACH_UDOO) += barebox-udoo-imx6q.img
+
+pblx-$(CONFIG_MACH_EMBEST_RIOTBOARD) += start_imx6s_riotboard
+CFG_start_imx6s_riotboard.pblx.imximg = $(board)/embest-riotboard/flash-header-embest-riotboard.imxcfg
+FILE_barebox-embest-imx6s-riotboard.img = start_imx6s_riotboard.pblx.imximg
+image-$(CONFIG_MACH_EMBEST_RIOTBOARD) += barebox-embest-imx6s-riotboard.img
-- 
1.8.5.3



From l.stach at pengutronix.de  Thu Mar 27 06:07:56 2014
From: l.stach at pengutronix.de (Lucas Stach)
Date: Thu, 27 Mar 2014 11:07:56 +0100
Subject: [PATCH 3/3] arm: add defconfig for Embest boards
In-Reply-To: <1395865363-29307-3-git-send-email-eric@eukrea.com>
References: <1395865363-29307-1-git-send-email-eric@eukrea.com>
 <1395865363-29307-3-git-send-email-eric@eukrea.com>
Message-ID: <1395914876.5063.2.camel@weser.hi.pengutronix.de>

Hi Eric,

Am Mittwoch, den 26.03.2014, 21:22 +0100 schrieb Eric B?nard:
> Signed-off-by: Eric B?nard <eric at eukrea.com>
> ---
>  arch/arm/configs/embest_defconfig | 100 ++++++++++++++++++++++++++++++++++++++
>  1 file changed, 100 insertions(+)
>  create mode 100644 arch/arm/configs/embest_defconfig
> 
Please don't add new configs for multi-image capable boards. If anything
is missing from the imx_v7_defconfig just add it there. This means at
least both of your board additions should be reflected in the imx_v7
defconfig.

Regards,
Lucas

-- 
Pengutronix e.K.                           | Lucas Stach                 |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-5076 |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |



From antonynpavlov at gmail.com  Thu Mar 27 17:26:36 2014
From: antonynpavlov at gmail.com (Antony Pavlov)
Date: Fri, 28 Mar 2014 01:26:36 +0400
Subject: [PATCH 1/9] MIPS: lib: add BAREBOX_CLK_TABLE to linker script
In-Reply-To: <1395955604-12826-1-git-send-email-antonynpavlov@gmail.com>
References: <1395955604-12826-1-git-send-email-antonynpavlov@gmail.com>
Message-ID: <1395955604-12826-2-git-send-email-antonynpavlov@gmail.com>

This commit is based on
    commit fa1a406f7245c5482a17014d5b97e8948352e5a5
    Author: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
    Date:   Sat Nov 9 14:24:18 2013 +0100

        ARM: lib: add BAREBOX_CLK_TABLE to linker script

        This adds an .oftables section right before .dtb section with
        BAREBOX_CLK_TABLE to ARM linker script.

Signed-off-by: Antony Pavlov <antonynpavlov at gmail.com>
---
 arch/mips/lib/barebox.lds.S | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/mips/lib/barebox.lds.S b/arch/mips/lib/barebox.lds.S
index bc78d2b..4ee4252 100644
--- a/arch/mips/lib/barebox.lds.S
+++ b/arch/mips/lib/barebox.lds.S
@@ -69,6 +69,8 @@ SECTIONS
 	__usymtab : { BAREBOX_SYMS }
 	__usymtab_end = .;
 
+	.oftables : { BAREBOX_CLK_TABLE() }
+
 	.dtb : { BAREBOX_DTB() }
 
 	_edata = .;
-- 
1.9.0



From antonynpavlov at gmail.com  Thu Mar 27 17:26:35 2014
From: antonynpavlov at gmail.com (Antony Pavlov)
Date: Fri, 28 Mar 2014 01:26:35 +0400
Subject: [PATCH 0/9] MIPS: add Atheros AR933x SoC & TP-LINK MR3020 board
 support
Message-ID: <1395955604-12826-1-git-send-email-antonynpavlov@gmail.com>

Antony Pavlov (8):
  MIPS: lib: add BAREBOX_CLK_TABLE to linker script
  MIPS: ath79: add DEBUG_LL support for Atheros AR933x
  serial: add Atheros AR933x driver
  clk: add Atheros AR933x driver
  MIPS: ath79: ar9331: add devicetree files
  MIPS: ath79: add tplink-mr3020 board support
  MIPS: tplink-mr3020: add documentation
  MIPS: add tplink-mr3020_defconfig

Du Huanpeng (1):
  MIPS: add Atheros ar933x family support

 Documentation/boards.dox                         |   1 +
 arch/mips/Kconfig                                |  14 ++
 arch/mips/Makefile                               |   3 +
 arch/mips/boards/tplink-mr3020/Makefile          |   1 +
 arch/mips/boards/tplink-mr3020/board.c           |  27 +++
 arch/mips/boards/tplink-mr3020/tplink-mr3020.dox |  64 +++++++
 arch/mips/configs/tplink-mr3020_defconfig        |  29 ++++
 arch/mips/dts/ar9331.dtsi                        |  26 +++
 arch/mips/dts/include/dt-bindings                |   1 +
 arch/mips/dts/tplink-mr3020.dts                  |  18 ++
 arch/mips/lib/barebox.lds.S                      |   2 +
 arch/mips/mach-ath79/Kconfig                     |  15 ++
 arch/mips/mach-ath79/Makefile                    |   1 +
 arch/mips/mach-ath79/include/mach/ar71xx_regs.h  |  64 +++++++
 arch/mips/mach-ath79/include/mach/ath79.h        |  33 ++++
 arch/mips/mach-ath79/include/mach/debug_ll.h     |  56 +++++++
 arch/mips/mach-ath79/reset.c                     |  32 ++++
 drivers/clk/Makefile                             |   1 +
 drivers/clk/clk-ar933x.c                         | 175 +++++++++++++++++++
 drivers/serial/Kconfig                           |   7 +
 drivers/serial/Makefile                          |   1 +
 drivers/serial/serial_ar933x.c                   | 204 +++++++++++++++++++++++
 drivers/serial/serial_ar933x.h                   |  69 ++++++++
 include/dt-bindings/clock/ar933x-clk.h           |  22 +++
 24 files changed, 866 insertions(+)
 create mode 100644 arch/mips/boards/tplink-mr3020/Makefile
 create mode 100644 arch/mips/boards/tplink-mr3020/board.c
 create mode 100644 arch/mips/boards/tplink-mr3020/tplink-mr3020.dox
 create mode 100644 arch/mips/configs/tplink-mr3020_defconfig
 create mode 100644 arch/mips/dts/ar9331.dtsi
 create mode 120000 arch/mips/dts/include/dt-bindings
 create mode 100644 arch/mips/dts/tplink-mr3020.dts
 create mode 100644 arch/mips/mach-ath79/Kconfig
 create mode 100644 arch/mips/mach-ath79/Makefile
 create mode 100644 arch/mips/mach-ath79/include/mach/ar71xx_regs.h
 create mode 100644 arch/mips/mach-ath79/include/mach/ath79.h
 create mode 100644 arch/mips/mach-ath79/include/mach/debug_ll.h
 create mode 100644 arch/mips/mach-ath79/reset.c
 create mode 100644 drivers/clk/clk-ar933x.c
 create mode 100644 drivers/serial/serial_ar933x.c
 create mode 100644 drivers/serial/serial_ar933x.h
 create mode 100644 include/dt-bindings/clock/ar933x-clk.h

-- 
1.9.0



From antonynpavlov at gmail.com  Thu Mar 27 17:26:37 2014
From: antonynpavlov at gmail.com (Antony Pavlov)
Date: Fri, 28 Mar 2014 01:26:37 +0400
Subject: [PATCH 2/9] MIPS: add Atheros ar933x family support
In-Reply-To: <1395955604-12826-1-git-send-email-antonynpavlov@gmail.com>
References: <1395955604-12826-1-git-send-email-antonynpavlov@gmail.com>
Message-ID: <1395955604-12826-3-git-send-email-antonynpavlov@gmail.com>

From: Du Huanpeng <u74147 at gmail.com>

Use the mach-ath79 name for compatibility with linux kernel.

Signed-off-by: Du Huanpeng <u74147 at gmail.com>
Signed-off-by: Antony Pavlov <antonynpavlov at gmail.com>
Signed-off-by: Oleksij Rempel <linux at rempel-privat.de>
---
 arch/mips/Kconfig                               | 13 +++++
 arch/mips/Makefile                              |  2 +
 arch/mips/mach-ath79/Kconfig                    |  7 +++
 arch/mips/mach-ath79/Makefile                   |  1 +
 arch/mips/mach-ath79/include/mach/ar71xx_regs.h | 64 +++++++++++++++++++++++++
 arch/mips/mach-ath79/include/mach/ath79.h       | 33 +++++++++++++
 arch/mips/mach-ath79/reset.c                    | 32 +++++++++++++
 7 files changed, 152 insertions(+)

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index b819b49..521af7c 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -54,6 +54,18 @@ config MACH_MIPS_AR231X
 	select DRIVER_SERIAL_NS16550
 	select HAS_DEBUG_LL
 
+config MACH_MIPS_ATH79
+	bool "Atheros AR71XX/AR724X/AR913X/AR933X based boards"
+	select SYS_HAS_CPU_MIPS32_R2
+	select SYS_SUPPORTS_32BIT_KERNEL
+	select SYS_SUPPORTS_BIG_ENDIAN
+	select CSRC_R4K_LIB
+	select HAVE_CLK
+	select COMMON_CLK
+	select COMMON_CLK_OF_PROVIDER
+	select CLKDEV_LOOKUP
+	select OFTREE
+
 config MACH_MIPS_BCM47XX
 	bool "Broadcom BCM47xx-based boards"
 	select CSRC_R4K_LIB
@@ -80,6 +92,7 @@ endchoice
 
 source arch/mips/mach-malta/Kconfig
 source arch/mips/mach-ar231x/Kconfig
+source arch/mips/mach-ath79/Kconfig
 source arch/mips/mach-bcm47xx/Kconfig
 source arch/mips/mach-loongson/Kconfig
 source arch/mips/mach-xburst/Kconfig
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index e3d65c8..5ca5fc9 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -78,6 +78,8 @@ board-$(CONFIG_BOARD_QEMU_MALTA)	:= qemu-malta
 machine-$(CONFIG_MACH_MIPS_AR231X)	:= ar231x
 board-$(CONFIG_BOARD_NETGEAR_WG102)	:= netgear-wg102
 
+machine-$(CONFIG_MACH_MIPS_ATH79)	:= ath79
+
 machine-$(CONFIG_MACH_MIPS_BCM47XX)	:= bcm47xx
 board-$(CONFIG_BOARD_DLINK_DIR320)	:= dlink-dir-320
 
diff --git a/arch/mips/mach-ath79/Kconfig b/arch/mips/mach-ath79/Kconfig
new file mode 100644
index 0000000..5f73e0a
--- /dev/null
+++ b/arch/mips/mach-ath79/Kconfig
@@ -0,0 +1,7 @@
+if MACH_MIPS_ATH79
+
+config ARCH_TEXT_BASE
+	hex
+	default 0xa0800000
+
+endif
diff --git a/arch/mips/mach-ath79/Makefile b/arch/mips/mach-ath79/Makefile
new file mode 100644
index 0000000..f3cc668
--- /dev/null
+++ b/arch/mips/mach-ath79/Makefile
@@ -0,0 +1 @@
+obj-y += reset.o
diff --git a/arch/mips/mach-ath79/include/mach/ar71xx_regs.h b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h
new file mode 100644
index 0000000..0c6ddd6
--- /dev/null
+++ b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h
@@ -0,0 +1,64 @@
+/*
+ *  Atheros AR71XX/AR724X/AR913X SoC register definitions
+ *
+ *  Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan at atheros.com>
+ *  Copyright (C) 2008-2010 Gabor Juhos <juhosg at openwrt.org>
+ *  Copyright (C) 2008 Imre Kaloz <kaloz at openwrt.org>
+ *
+ *  Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ */
+
+#ifndef __ASM_MACH_AR71XX_REGS_H
+#define __ASM_MACH_AR71XX_REGS_H
+
+#include <linux/bitops.h>
+
+#define AR71XX_APB_BASE		0x18000000
+
+#define AR71XX_PLL_BASE		(AR71XX_APB_BASE + 0x00050000)
+#define AR71XX_PLL_SIZE		0x100
+#define AR71XX_RESET_BASE	(AR71XX_APB_BASE + 0x00060000)
+#define AR71XX_RESET_SIZE	0x100
+
+#define AR933X_UART_BASE	(AR71XX_APB_BASE + 0x00020000)
+#define AR933X_UART_SIZE	0x14
+
+/*
+ * PLL block
+ */
+#define AR933X_PLL_CPU_CONFIG_REG	0x00
+#define AR933X_PLL_CPU_CONFIG2_REG	0x04
+#define AR933X_PLL_CLOCK_CTRL_REG	0x08
+#define AR933X_PLL_DITHER_FRAC_REG	0x10
+#define AR933X_PLL_DITHER_REG		0x14
+
+#define AR933X_PLL_CPU_CONFIG_NINT_SHIFT	10
+#define AR933X_PLL_CPU_CONFIG_NINT_MASK		0x3f
+#define AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT	16
+#define AR933X_PLL_CPU_CONFIG_REFDIV_MASK	0x1f
+#define AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT	23
+#define AR933X_PLL_CPU_CONFIG_OUTDIV_MASK	0x7
+
+#define AR933X_PLL_CLOCK_CTRL_BYPASS		BIT(2)
+#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT	5
+#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK	0x3
+#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT	10
+#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK	0x3
+#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT	15
+#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK	0x7
+
+/*
+ * RESET block
+ */
+#define AR933X_RESET_REG_RESET_MODULE		0x1c
+#define AR933X_RESET_REG_BOOTSTRAP		0xac
+
+#define AR71XX_RESET_FULL_CHIP		BIT(24)
+
+#define AR933X_BOOTSTRAP_REF_CLK_40	BIT(0)
+
+#endif /* __ASM_MACH_AR71XX_REGS_H */
diff --git a/arch/mips/mach-ath79/include/mach/ath79.h b/arch/mips/mach-ath79/include/mach/ath79.h
new file mode 100644
index 0000000..ff53406
--- /dev/null
+++ b/arch/mips/mach-ath79/include/mach/ath79.h
@@ -0,0 +1,33 @@
+/*
+ *  Atheros AR71XX/AR724X/AR913X common definitions
+ *
+ *  Copyright (C) 2008-2011 Gabor Juhos <juhosg at openwrt.org>
+ *  Copyright (C) 2008 Imre Kaloz <kaloz at openwrt.org>
+ *
+ *  Parts of this file are based on Atheros' 2.6.15 BSP
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ */
+
+#ifndef __ASM_MACH_ATH79_H
+#define __ASM_MACH_ATH79_H
+
+#include <common.h>
+#include <io.h>
+#include <asm/memory.h>
+
+#include <mach/ar71xx_regs.h>
+
+static inline void ath79_reset_wr(unsigned reg, u32 val)
+{
+	__raw_writel(val, (char *)KSEG1ADDR(AR71XX_RESET_BASE + reg));
+}
+
+static inline u32 ath79_reset_rr(unsigned reg)
+{
+	return __raw_readl((char *)KSEG1ADDR(AR71XX_RESET_BASE + reg));
+}
+
+#endif /* __ASM_MACH_ATH79_H */
diff --git a/arch/mips/mach-ath79/reset.c b/arch/mips/mach-ath79/reset.c
new file mode 100644
index 0000000..a0e9b34
--- /dev/null
+++ b/arch/mips/mach-ath79/reset.c
@@ -0,0 +1,32 @@
+/*
+ * Copyright (C) 2013 Du Huanpeng <u74147 at gmail.com>
+ *
+ * This file is part of barebox.
+ * See file CREDITS for list of people who contributed to this project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <common.h>
+#include <mach/ath79.h>
+
+void __noreturn reset_cpu(ulong addr)
+{
+	ath79_reset_wr(AR933X_RESET_REG_RESET_MODULE, AR71XX_RESET_FULL_CHIP);
+	/*
+	 * Used to command a full chip reset. This is the software equivalent of
+	 * pulling the reset pin. The system will reboot with PLL disabled.
+	 * Always zero when read.
+	 */
+	unreachable();
+	/*NOTREACHED*/
+}
+EXPORT_SYMBOL(reset_cpu);
-- 
1.9.0



From antonynpavlov at gmail.com  Thu Mar 27 17:26:38 2014
From: antonynpavlov at gmail.com (Antony Pavlov)
Date: Fri, 28 Mar 2014 01:26:38 +0400
Subject: [PATCH 3/9] MIPS: ath79: add DEBUG_LL support for Atheros AR933x
In-Reply-To: <1395955604-12826-1-git-send-email-antonynpavlov@gmail.com>
References: <1395955604-12826-1-git-send-email-antonynpavlov@gmail.com>
Message-ID: <1395955604-12826-4-git-send-email-antonynpavlov@gmail.com>

Signed-off-by: Antony Pavlov <antonynpavlov at gmail.com>
---
 arch/mips/Kconfig                            |  1 +
 arch/mips/mach-ath79/include/mach/debug_ll.h | 56 ++++++++++++++++++++++++++++
 2 files changed, 57 insertions(+)

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 521af7c..9a240b7 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -60,6 +60,7 @@ config MACH_MIPS_ATH79
 	select SYS_SUPPORTS_32BIT_KERNEL
 	select SYS_SUPPORTS_BIG_ENDIAN
 	select CSRC_R4K_LIB
+	select HAS_DEBUG_LL
 	select HAVE_CLK
 	select COMMON_CLK
 	select COMMON_CLK_OF_PROVIDER
diff --git a/arch/mips/mach-ath79/include/mach/debug_ll.h b/arch/mips/mach-ath79/include/mach/debug_ll.h
new file mode 100644
index 0000000..de4c00d
--- /dev/null
+++ b/arch/mips/mach-ath79/include/mach/debug_ll.h
@@ -0,0 +1,56 @@
+/*
+ * based on linux.git/drivers/tty/serial/ar933x_uart.c
+ *
+ * This file is part of barebox.
+ * See file CREDITS for list of people who contributed to this project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __AR933X_DEBUG_LL__
+#define __AR933X_DEBUG_LL__
+
+#include <io.h>
+#include <linux/bitops.h>
+#include <asm/addrspace.h>
+
+#include <mach/ar71xx_regs.h>
+
+#define AR933X_UART_DATA_REG            0x00
+#define AR933X_UART_DATA_TX_RX_MASK     0xff
+#define AR933X_UART_DATA_TX_CSR         BIT(9)
+
+#define DEBUG_LL_UART_ADDR	KSEG1ADDR(AR933X_UART_BASE)
+
+static inline void ar933x_debug_ll_writel(u32 b, int offset)
+{
+	cpu_writel(b, (u8 *)DEBUG_LL_UART_ADDR + offset);
+}
+
+static inline u32 ar933x_debug_ll_readl(int offset)
+{
+	return cpu_readl((u8 *)DEBUG_LL_UART_ADDR + offset);
+}
+
+static inline void PUTC_LL(int ch)
+{
+	u32 data;
+
+	/* wait transmitter ready */
+	data = ar933x_debug_ll_readl(AR933X_UART_DATA_REG);
+	while (!(data & AR933X_UART_DATA_TX_CSR))
+		data = ar933x_debug_ll_readl(AR933X_UART_DATA_REG);
+
+	data = (ch & AR933X_UART_DATA_TX_RX_MASK) | AR933X_UART_DATA_TX_CSR;
+	ar933x_debug_ll_writel(data, AR933X_UART_DATA_REG);
+}
+
+#endif /* __AR933X_DEBUG_LL__ */
-- 
1.9.0



From antonynpavlov at gmail.com  Thu Mar 27 17:26:40 2014
From: antonynpavlov at gmail.com (Antony Pavlov)
Date: Fri, 28 Mar 2014 01:26:40 +0400
Subject: [PATCH 5/9] clk: add Atheros AR933x driver
In-Reply-To: <1395955604-12826-1-git-send-email-antonynpavlov@gmail.com>
References: <1395955604-12826-1-git-send-email-antonynpavlov@gmail.com>
Message-ID: <1395955604-12826-6-git-send-email-antonynpavlov@gmail.com>

Signed-off-by: Oleksij Rempel <linux at rempel-privat.de>
Signed-off-by: Antony Pavlov <antonynpavlov at gmail.com>
---
 drivers/clk/Makefile                   |   1 +
 drivers/clk/clk-ar933x.c               | 175 +++++++++++++++++++++++++++++++++
 include/dt-bindings/clock/ar933x-clk.h |  22 +++++
 3 files changed, 198 insertions(+)

diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index f5c0592..b4b5414 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -6,3 +6,4 @@ obj-$(CONFIG_ARCH_MVEBU)	+= mvebu/
 obj-$(CONFIG_ARCH_MXS)		+= mxs/
 obj-$(CONFIG_ARCH_TEGRA)	+= tegra/
 obj-$(CONFIG_CLK_SOCFPGA)	+= socfpga.o
+obj-$(CONFIG_MACH_MIPS_ATH79)	+= clk-ar933x.o
diff --git a/drivers/clk/clk-ar933x.c b/drivers/clk/clk-ar933x.c
new file mode 100644
index 0000000..f9701ae
--- /dev/null
+++ b/drivers/clk/clk-ar933x.c
@@ -0,0 +1,175 @@
+/*
+ * Copyright (C) 2013 Lucas Stach <l.stach at pengutronix.de>
+ *
+ * Based on the Linux Tegra clock code
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <common.h>
+#include <init.h>
+#include <io.h>
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/err.h>
+
+#include <mach/ath79.h>
+#include <dt-bindings/clock/ar933x-clk.h>
+
+static struct clk *clks[AR933X_CLK_END];
+static struct clk_onecell_data clk_data;
+
+struct clk_ar933x {
+	struct clk clk;
+	void __iomem *base;
+	u32 div_shift;
+	u32 div_mask;
+	const char *parent;
+};
+
+static unsigned long clk_ar933x_recalc_rate(struct clk *clk,
+	unsigned long parent_rate)
+{
+	struct clk_ar933x *f = container_of(clk, struct clk_ar933x, clk);
+	unsigned long rate;
+	unsigned long freq;
+	u32 clock_ctrl;
+	u32 cpu_config;
+	u32 t;
+
+	clock_ctrl = __raw_readl(f->base + AR933X_PLL_CLOCK_CTRL_REG);
+
+	if (clock_ctrl & AR933X_PLL_CLOCK_CTRL_BYPASS) {
+		rate = parent_rate;
+	} else {
+		cpu_config = __raw_readl(f->base + AR933X_PLL_CPU_CONFIG_REG);
+
+		t = (cpu_config >> AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
+		    AR933X_PLL_CPU_CONFIG_REFDIV_MASK;
+		freq = parent_rate / t;
+
+		t = (cpu_config >> AR933X_PLL_CPU_CONFIG_NINT_SHIFT) &
+		    AR933X_PLL_CPU_CONFIG_NINT_MASK;
+		freq *= t;
+
+		t = (cpu_config >> AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
+		    AR933X_PLL_CPU_CONFIG_OUTDIV_MASK;
+		if (t == 0)
+			t = 1;
+
+		freq >>= t;
+
+		t = ((clock_ctrl >> f->div_shift) & f->div_mask) + 1;
+		rate = freq / t;
+	}
+
+	return rate;
+}
+
+struct clk_ops clk_ar933x_ops = {
+	.recalc_rate = clk_ar933x_recalc_rate,
+};
+
+static struct clk *clk_ar933x(const char *name, const char *parent,
+	void __iomem *base, u32 div_shift, u32 div_mask)
+{
+	struct clk_ar933x *f = xzalloc(sizeof(*f));
+
+	f->parent = parent;
+	f->base = base;
+	f->div_shift = div_shift;
+	f->div_mask = div_mask;
+
+	f->clk.ops = &clk_ar933x_ops;
+	f->clk.name = name;
+	f->clk.parent_names = &f->parent;
+	f->clk.num_parents = 1;
+
+	clk_register(&f->clk);
+
+	return &f->clk;
+}
+
+static void ar933x_ref_clk_init(void __iomem *base)
+{
+	u32 t;
+	unsigned long ref_rate;
+	struct clk *clk;
+	int err;
+
+	t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
+	if (t & AR933X_BOOTSTRAP_REF_CLK_40)
+		ref_rate = (40 * 1000 * 1000);
+	else
+		ref_rate = (25 * 1000 * 1000);
+
+	clks[AR933X_CLK_REF] = clk_fixed("ref", ref_rate);
+}
+
+static void ar933x_pll_init(void __iomem *base)
+{
+	clks[AR933X_CLK_UART] = clk_fixed_factor("uart", "ref", 1, 1);
+
+	clks[AR933X_CLK_CPU] = clk_ar933x("cpu", "ref", base,
+		AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT,
+		AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK);
+
+	clks[AR933X_CLK_DDR] = clk_ar933x("ddr", "ref", base,
+		AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT,
+		AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK);
+
+	clks[AR933X_CLK_AHB] = clk_ar933x("ahb", "ref", base,
+		AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT,
+		AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK);
+
+	clks[AR933X_CLK_WDT] = clk_fixed_factor("wdt", "ahb", 1, 1);
+}
+
+static int ar933x_clk_probe(struct device_d *dev)
+{
+	void __iomem *base;
+
+	base = dev_request_mem_region(dev, 0);
+	if (!base)
+		return -EBUSY;
+
+	ar933x_ref_clk_init(base);
+	ar933x_pll_init(base);
+
+	clk_data.clks = clks;
+	clk_data.clk_num = ARRAY_SIZE(clks);
+	of_clk_add_provider(dev->device_node, of_clk_src_onecell_get,
+			    &clk_data);
+
+	return 0;
+}
+
+static __maybe_unused struct of_device_id ar933x_clk_dt_ids[] = {
+	{
+		.compatible = "qca,ar933x-clk",
+	}, {
+		/* sentinel */
+	}
+};
+
+static struct driver_d ar933x_clk_driver = {
+	.probe	= ar933x_clk_probe,
+	.name	= "ar933x_clk",
+	.of_compatible = DRV_OF_COMPAT(ar933x_clk_dt_ids),
+};
+
+static int ar933x_clk_init(void)
+{
+	return platform_driver_register(&ar933x_clk_driver);
+}
+postcore_initcall(ar933x_clk_init);
diff --git a/include/dt-bindings/clock/ar933x-clk.h b/include/dt-bindings/clock/ar933x-clk.h
new file mode 100644
index 0000000..f048930
--- /dev/null
+++ b/include/dt-bindings/clock/ar933x-clk.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright (C) 2014 Antony Pavlov <antonynpavlov at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DT_BINDINGS_AR933X_CLK_H
+#define __DT_BINDINGS_AR933X_CLK_H
+
+#define AR933X_CLK_REF		0
+#define AR933X_CLK_UART		1
+#define AR933X_CLK_CPU		2
+#define AR933X_CLK_DDR		3
+#define AR933X_CLK_AHB		4
+#define AR933X_CLK_WDT		5
+
+#define AR933X_CLK_END		6
+
+#endif /* __DT_BINDINGS_AR933X_CLK_H */
-- 
1.9.0



From antonynpavlov at gmail.com  Thu Mar 27 17:26:41 2014
From: antonynpavlov at gmail.com (Antony Pavlov)
Date: Fri, 28 Mar 2014 01:26:41 +0400
Subject: [PATCH 6/9] MIPS: ath79: ar9331: add devicetree files
In-Reply-To: <1395955604-12826-1-git-send-email-antonynpavlov@gmail.com>
References: <1395955604-12826-1-git-send-email-antonynpavlov@gmail.com>
Message-ID: <1395955604-12826-7-git-send-email-antonynpavlov@gmail.com>

Signed-off-by: Antony Pavlov <antonynpavlov at gmail.com>
---
 arch/mips/dts/ar9331.dtsi         | 26 ++++++++++++++++++++++++++
 arch/mips/dts/include/dt-bindings |  1 +
 2 files changed, 27 insertions(+)

diff --git a/arch/mips/dts/ar9331.dtsi b/arch/mips/dts/ar9331.dtsi
new file mode 100644
index 0000000..890fda8
--- /dev/null
+++ b/arch/mips/dts/ar9331.dtsi
@@ -0,0 +1,26 @@
+#include <dt-bindings/clock/ar933x-clk.h>
+
+#include "skeleton.dtsi"
+
+/ {
+	soc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		device_type = "soc";
+		ranges;
+
+		serial0: serial at b8020000 {
+			compatible = "qca,ar9330-uart";
+			reg = <0xb8020000 0x14>;
+			clocks = <&ar9331_clk AR933X_CLK_UART>;
+			status = "disabled";
+		};
+
+		ar9331_clk: clock {
+			compatible = "qca,ar933x-clk";
+			reg = <0xb8050000 0x48>;
+			#clock-cells = <1>;
+		};
+	};
+};
diff --git a/arch/mips/dts/include/dt-bindings b/arch/mips/dts/include/dt-bindings
new file mode 120000
index 0000000..0cecb3d
--- /dev/null
+++ b/arch/mips/dts/include/dt-bindings
@@ -0,0 +1 @@
+../../../../include/dt-bindings
\ No newline at end of file
-- 
1.9.0



From antonynpavlov at gmail.com  Thu Mar 27 17:26:42 2014
From: antonynpavlov at gmail.com (Antony Pavlov)
Date: Fri, 28 Mar 2014 01:26:42 +0400
Subject: [PATCH 7/9] MIPS: ath79: add tplink-mr3020 board support
In-Reply-To: <1395955604-12826-1-git-send-email-antonynpavlov@gmail.com>
References: <1395955604-12826-1-git-send-email-antonynpavlov@gmail.com>
Message-ID: <1395955604-12826-8-git-send-email-antonynpavlov@gmail.com>

This board support code can be used for TP-LINK WR703 too.

TP-LINK WR703 is very similar to TP-LINK MR3020, there are
some non-essential differences:

  * WR703 is smaller and cheaper;
  * WR703 has only one led, but MR3020 has five leds;
  * MR3020 uses mini-USB connector, WR703 uses micro-USB connector.

See https://forum.openwrt.org/viewtopic.php?id=45159 for details.

Signed-off-by: Antony Pavlov <antonynpavlov at gmail.com>
---
 arch/mips/Makefile                      |  1 +
 arch/mips/boards/tplink-mr3020/Makefile |  1 +
 arch/mips/boards/tplink-mr3020/board.c  | 27 +++++++++++++++++++++++++++
 arch/mips/dts/tplink-mr3020.dts         | 18 ++++++++++++++++++
 arch/mips/mach-ath79/Kconfig            |  8 ++++++++
 5 files changed, 55 insertions(+)

diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 5ca5fc9..b3bacf3 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -79,6 +79,7 @@ machine-$(CONFIG_MACH_MIPS_AR231X)	:= ar231x
 board-$(CONFIG_BOARD_NETGEAR_WG102)	:= netgear-wg102
 
 machine-$(CONFIG_MACH_MIPS_ATH79)	:= ath79
+board-$(CONFIG_BOARD_TPLINK_MR3020)	:= tplink-mr3020
 
 machine-$(CONFIG_MACH_MIPS_BCM47XX)	:= bcm47xx
 board-$(CONFIG_BOARD_DLINK_DIR320)	:= dlink-dir-320
diff --git a/arch/mips/boards/tplink-mr3020/Makefile b/arch/mips/boards/tplink-mr3020/Makefile
new file mode 100644
index 0000000..dcfc293
--- /dev/null
+++ b/arch/mips/boards/tplink-mr3020/Makefile
@@ -0,0 +1 @@
+obj-y += board.o
diff --git a/arch/mips/boards/tplink-mr3020/board.c b/arch/mips/boards/tplink-mr3020/board.c
new file mode 100644
index 0000000..318998c
--- /dev/null
+++ b/arch/mips/boards/tplink-mr3020/board.c
@@ -0,0 +1,27 @@
+/*
+ * Copyright (C) 2014 Antony Pavlov <antonynpavlov at gmail.com>
+ *
+ * This file is part of barebox.
+ * See file CREDITS for list of people who contributed to this project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <common.h>
+#include <init.h>
+
+static int model_hostname_init(void)
+{
+	barebox_set_hostname("mr3020");
+
+	return 0;
+}
+postcore_initcall(model_hostname_init);
diff --git a/arch/mips/dts/tplink-mr3020.dts b/arch/mips/dts/tplink-mr3020.dts
new file mode 100644
index 0000000..b9539c5
--- /dev/null
+++ b/arch/mips/dts/tplink-mr3020.dts
@@ -0,0 +1,18 @@
+/dts-v1/;
+
+#include <ar9331.dtsi>
+
+/ {
+	model = "TP-LINK MR3020";
+	compatible = "tplink,mr3020";
+
+	memory {
+		reg = <0x00000000 0x2000000>;
+	};
+
+	soc {
+		serial0: serial at b8020000 {
+			status = "okay";
+		};
+	};
+};
diff --git a/arch/mips/mach-ath79/Kconfig b/arch/mips/mach-ath79/Kconfig
index 5f73e0a..96fffd3 100644
--- a/arch/mips/mach-ath79/Kconfig
+++ b/arch/mips/mach-ath79/Kconfig
@@ -4,4 +4,12 @@ config ARCH_TEXT_BASE
 	hex
 	default 0xa0800000
 
+choice
+	prompt "Board type"
+
+config BOARD_TPLINK_MR3020
+	bool "TP-LINK MR3020"
+
+endchoice
+
 endif
-- 
1.9.0



From antonynpavlov at gmail.com  Thu Mar 27 17:26:39 2014
From: antonynpavlov at gmail.com (Antony Pavlov)
Date: Fri, 28 Mar 2014 01:26:39 +0400
Subject: [PATCH 4/9] serial: add Atheros AR933x driver
In-Reply-To: <1395955604-12826-1-git-send-email-antonynpavlov@gmail.com>
References: <1395955604-12826-1-git-send-email-antonynpavlov@gmail.com>
Message-ID: <1395955604-12826-5-git-send-email-antonynpavlov@gmail.com>

Signed-off-by: Antony Pavlov <antonynpavlov at gmail.com>
Signed-off-by: Oleksij Rempel <linux at rempel-privat.de>
---
 drivers/serial/Kconfig         |   7 ++
 drivers/serial/Makefile        |   1 +
 drivers/serial/serial_ar933x.c | 204 +++++++++++++++++++++++++++++++++++++++++
 drivers/serial/serial_ar933x.h |  69 ++++++++++++++
 4 files changed, 281 insertions(+)

diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 11fc155..f51c6e6 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -14,6 +14,13 @@ config SERIAL_AMBA_PL011
 
 	  If unsure, say N.
 
+config DRIVER_SERIAL_AR933X
+	bool "AR933X serial driver"
+	depends on MACH_MIPS_ATH79
+	help
+	  If you have an Atheros AR933X SOC based board and want to use the
+	  built-in UART of the SoC, say Y to this option.
+
 config DRIVER_SERIAL_IMX
 	depends on ARCH_IMX
 	default y
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index 93790b5..e1865f7 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -1,5 +1,6 @@
 obj-$(CONFIG_DRIVER_SERIAL_ARM_DCC)		+= arm_dcc.o
 obj-$(CONFIG_SERIAL_AMBA_PL011)			+= amba-pl011.o
+obj-$(CONFIG_DRIVER_SERIAL_AR933X)		+= serial_ar933x.o
 obj-$(CONFIG_DRIVER_SERIAL_IMX)			+= serial_imx.o
 obj-$(CONFIG_DRIVER_SERIAL_STM378X)		+= stm-serial.o
 obj-$(CONFIG_DRIVER_SERIAL_ATMEL)		+= atmel.o
diff --git a/drivers/serial/serial_ar933x.c b/drivers/serial/serial_ar933x.c
new file mode 100644
index 0000000..27cccba
--- /dev/null
+++ b/drivers/serial/serial_ar933x.c
@@ -0,0 +1,204 @@
+/*
+ * based on linux.git/drivers/tty/serial/serial_ar933x.c
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <common.h>
+#include <driver.h>
+#include <init.h>
+#include <malloc.h>
+#include <io.h>
+#include <asm-generic/div64.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+
+#include "serial_ar933x.h"
+
+#define AR933X_UART_MAX_SCALE	0xff
+#define AR933X_UART_MAX_STEP	0xffff
+
+struct ar933x_uart_priv {
+	void __iomem	*base;
+	struct clk	*clk;
+};
+
+static inline void ar933x_serial_writel(struct console_device *cdev,
+	u32 b, int offset)
+{
+	struct ar933x_uart_priv *priv = cdev->dev->priv;
+
+	cpu_writel(b, priv->base + offset);
+}
+
+static inline u32 ar933x_serial_readl(struct console_device *cdev,
+	int offset)
+{
+	struct ar933x_uart_priv *priv = cdev->dev->priv;
+
+	return cpu_readl(priv->base + offset);
+}
+
+/*
+ * baudrate = (clk / (scale + 1)) * (step * (1 / 2^17))
+ * take from linux.
+ */
+static unsigned long ar933x_uart_get_baud(unsigned int clk,
+					  unsigned int scale,
+					  unsigned int step)
+{
+	u64 t;
+	u32 div;
+
+	div = (2 << 16) * (scale + 1);
+	t = clk;
+	t *= step;
+	t += (div / 2);
+	do_div(t, div);
+
+	return t;
+}
+
+static void ar933x_uart_get_scale_step(unsigned int clk,
+				       unsigned int baud,
+				       unsigned int *scale,
+				       unsigned int *step)
+{
+	unsigned int tscale;
+	long min_diff;
+
+	*scale = 0;
+	*step = 0;
+
+	min_diff = baud;
+	for (tscale = 0; tscale < AR933X_UART_MAX_SCALE; tscale++) {
+		u64 tstep;
+		int diff;
+
+		tstep = baud * (tscale + 1);
+		tstep *= (2 << 16);
+		do_div(tstep, clk);
+
+		if (tstep > AR933X_UART_MAX_STEP)
+			break;
+
+		diff = abs(ar933x_uart_get_baud(clk, tscale, tstep) - baud);
+		if (diff < min_diff) {
+			min_diff = diff;
+			*scale = tscale;
+			*step = tstep;
+		}
+	}
+}
+
+static int ar933x_serial_setbaudrate(struct console_device *cdev, int baudrate)
+{
+	struct ar933x_uart_priv *priv = cdev->dev->priv;
+	unsigned int scale, step;
+
+	ar933x_uart_get_scale_step(clk_get_rate(priv->clk), baudrate, &scale,
+			&step);
+	ar933x_serial_writel(cdev, (scale << AR933X_UART_CLOCK_SCALE_S) | step,
+			AR933X_UART_CLOCK_REG);
+
+	return 0;
+}
+
+static void ar933x_serial_putc(struct console_device *cdev, char ch)
+{
+	u32 data;
+
+	/* wait transmitter ready */
+	data = ar933x_serial_readl(cdev, AR933X_UART_DATA_REG);
+	while (!(data & AR933X_UART_DATA_TX_CSR))
+		data = ar933x_serial_readl(cdev, AR933X_UART_DATA_REG);
+
+	data = (ch & AR933X_UART_DATA_TX_RX_MASK) | AR933X_UART_DATA_TX_CSR;
+	ar933x_serial_writel(cdev, data, AR933X_UART_DATA_REG);
+}
+
+static int ar933x_serial_tstc(struct console_device *cdev)
+{
+	u32 rdata;
+
+	rdata = ar933x_serial_readl(cdev, AR933X_UART_DATA_REG);
+
+	return rdata & AR933X_UART_DATA_RX_CSR;
+}
+
+static int ar933x_serial_getc(struct console_device *cdev)
+{
+	u32 rdata;
+
+	while (!ar933x_serial_tstc(cdev))
+		;
+
+	rdata = ar933x_serial_readl(cdev, AR933X_UART_DATA_REG);
+
+	/* remove the character from the FIFO */
+	ar933x_serial_writel(cdev, AR933X_UART_DATA_RX_CSR,
+		AR933X_UART_DATA_REG);
+
+	return rdata & AR933X_UART_DATA_TX_RX_MASK;
+}
+
+static int ar933x_serial_probe(struct device_d *dev)
+{
+	struct console_device *cdev;
+	struct ar933x_uart_priv	*priv;
+	u32 uart_cs;
+
+	cdev = xzalloc(sizeof(struct console_device));
+	priv = xzalloc(sizeof(struct ar933x_uart_priv));
+	priv->base = dev_request_mem_region(dev, 0);
+	dev->priv = priv;
+
+	cdev->dev = dev;
+	cdev->tstc = ar933x_serial_tstc;
+	cdev->putc = ar933x_serial_putc;
+	cdev->getc = ar933x_serial_getc;
+	cdev->setbrg = ar933x_serial_setbaudrate;
+
+	priv->clk = clk_get(dev, NULL);
+	if (IS_ERR(priv->clk)) {
+		dev_err(dev, "unable to get UART clock\n");
+		return PTR_ERR(priv->clk);
+	}
+
+	uart_cs = (AR933X_UART_CS_IF_MODE_DCE << AR933X_UART_CS_IF_MODE_S)
+		| AR933X_UART_CS_TX_READY_ORIDE
+		| AR933X_UART_CS_RX_READY_ORIDE;
+	ar933x_serial_writel(cdev, uart_cs, AR933X_UART_CS_REG);
+	/* FIXME: need ar933x_serial_init_port(cdev); */
+
+	console_register(cdev);
+
+	return 0;
+}
+
+static struct of_device_id ar933x_serial_dt_ids[] = {
+	{
+		.compatible = "qca,ar9330-uart",
+	}, {
+		/* sentinel */
+	},
+};
+
+static struct driver_d ar933x_serial_driver = {
+	.name  = "ar933x_serial",
+	.probe = ar933x_serial_probe,
+	.of_compatible = DRV_OF_COMPAT(ar933x_serial_dt_ids),
+};
+console_platform_driver(ar933x_serial_driver);
diff --git a/drivers/serial/serial_ar933x.h b/drivers/serial/serial_ar933x.h
new file mode 100644
index 0000000..f55f0fa
--- /dev/null
+++ b/drivers/serial/serial_ar933x.h
@@ -0,0 +1,69 @@
+/*
+ *  Atheros AR933X UART defines
+ *
+ *  Copyright (C) 2011 Gabor Juhos <juhosg at openwrt.org>
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ */
+
+#ifndef __AR933X_UART_H
+#define __AR933X_UART_H
+
+#include <linux/bitops.h>
+
+#define AR933X_UART_REGS_SIZE		20
+#define AR933X_UART_FIFO_SIZE		16
+
+#define AR933X_UART_DATA_REG		0x00
+#define AR933X_UART_CS_REG		0x04
+#define AR933X_UART_CLOCK_REG		0x08
+#define AR933X_UART_INT_REG		0x0c
+#define AR933X_UART_INT_EN_REG		0x10
+
+#define AR933X_UART_DATA_TX_RX_MASK	0xff
+#define AR933X_UART_DATA_RX_CSR		BIT(8)
+#define AR933X_UART_DATA_TX_CSR		BIT(9)
+
+#define AR933X_UART_CS_PARITY_S		0
+#define AR933X_UART_CS_PARITY_M		0x3
+#define	  AR933X_UART_CS_PARITY_NONE	0
+#define	  AR933X_UART_CS_PARITY_ODD	1
+#define	  AR933X_UART_CS_PARITY_EVEN	2
+#define AR933X_UART_CS_IF_MODE_S	2
+#define AR933X_UART_CS_IF_MODE_M	0x3
+#define	  AR933X_UART_CS_IF_MODE_NONE	0
+#define	  AR933X_UART_CS_IF_MODE_DTE	1
+#define	  AR933X_UART_CS_IF_MODE_DCE	2
+#define AR933X_UART_CS_FLOW_CTRL_S	4
+#define AR933X_UART_CS_FLOW_CTRL_M	0x3
+#define AR933X_UART_CS_DMA_EN		BIT(6)
+#define AR933X_UART_CS_TX_READY_ORIDE	BIT(7)
+#define AR933X_UART_CS_RX_READY_ORIDE	BIT(8)
+#define AR933X_UART_CS_TX_READY		BIT(9)
+#define AR933X_UART_CS_RX_BREAK		BIT(10)
+#define AR933X_UART_CS_TX_BREAK		BIT(11)
+#define AR933X_UART_CS_HOST_INT		BIT(12)
+#define AR933X_UART_CS_HOST_INT_EN	BIT(13)
+#define AR933X_UART_CS_TX_BUSY		BIT(14)
+#define AR933X_UART_CS_RX_BUSY		BIT(15)
+
+#define AR933X_UART_CLOCK_STEP_M	0xffff
+#define AR933X_UART_CLOCK_SCALE_M	0xfff
+#define AR933X_UART_CLOCK_SCALE_S	16
+#define AR933X_UART_CLOCK_STEP_M	0xffff
+
+#define AR933X_UART_INT_RX_VALID	BIT(0)
+#define AR933X_UART_INT_TX_READY	BIT(1)
+#define AR933X_UART_INT_RX_FRAMING_ERR	BIT(2)
+#define AR933X_UART_INT_RX_OFLOW_ERR	BIT(3)
+#define AR933X_UART_INT_TX_OFLOW_ERR	BIT(4)
+#define AR933X_UART_INT_RX_PARITY_ERR	BIT(5)
+#define AR933X_UART_INT_RX_BREAK_ON	BIT(6)
+#define AR933X_UART_INT_RX_BREAK_OFF	BIT(7)
+#define AR933X_UART_INT_RX_FULL		BIT(8)
+#define AR933X_UART_INT_TX_EMPTY	BIT(9)
+#define AR933X_UART_INT_ALLINTS		0x3ff
+
+#endif /* __AR933X_UART_H */
-- 
1.9.0



From antonynpavlov at gmail.com  Thu Mar 27 17:26:43 2014
From: antonynpavlov at gmail.com (Antony Pavlov)
Date: Fri, 28 Mar 2014 01:26:43 +0400
Subject: [PATCH 8/9] MIPS: tplink-mr3020: add documentation
In-Reply-To: <1395955604-12826-1-git-send-email-antonynpavlov@gmail.com>
References: <1395955604-12826-1-git-send-email-antonynpavlov@gmail.com>
Message-ID: <1395955604-12826-9-git-send-email-antonynpavlov@gmail.com>

Signed-off-by: Antony Pavlov <antonynpavlov at gmail.com>
---
 Documentation/boards.dox                         |  1 +
 arch/mips/boards/tplink-mr3020/tplink-mr3020.dox | 64 ++++++++++++++++++++++++
 2 files changed, 65 insertions(+)

diff --git a/Documentation/boards.dox b/Documentation/boards.dox
index 42bc5e6..8d4fabb 100644
--- a/Documentation/boards.dox
+++ b/Documentation/boards.dox
@@ -60,6 +60,7 @@ MIPS type:
 @li @subpage loongson_ls1b
 @li @subpage qemu_malta
 @li @subpage ritmix-rzx50
+ at li @subpage tplink-mr3020
 
 */
 
diff --git a/arch/mips/boards/tplink-mr3020/tplink-mr3020.dox b/arch/mips/boards/tplink-mr3020/tplink-mr3020.dox
new file mode 100644
index 0000000..16fe465
--- /dev/null
+++ b/arch/mips/boards/tplink-mr3020/tplink-mr3020.dox
@@ -0,0 +1,64 @@
+/** @page tplink-mr3020 TP-LINK MR3020 wireless router
+
+The router has
+ at li Atheros ar9331 SoC;
+ at li 32 MiB SDRAM;
+ at li 4 MiB NOR type SPI Flash Memory;
+ at li RS232 serial interface (LV-TTL levels on board!);
+ at li 1 USB interface;
+ at li 1 Ethernet interfaces;
+ at li 802.11b/g/n (WiFi) interface;
+ at li LEDs & buttons.
+
+The router uses U-Boot 1.1.4 as firmware.
+
+Barebox can be started from U-Boot using tftp.
+But you have to encode barebox image in a very special way.
+
+First obtain 'lzma' and 'mktplinkfw' utilities.
+
+The 'lzma' utility can be obtained in Debian/Ubuntu
+distro by installing lzma package.
+
+The 'mktplinkfw' utility can be obtained from openwrt, e.g.:
+
+ at verbatim
+$ OWRTPREF=https://raw.githubusercontent.com/mirrors/openwrt/master
+$ curl -OL $OWRTPREF/tools/firmware-utils/src/mktplinkfw.c \
+        -OL $OWRTPREF/tools/firmware-utils/src/md5.c \
+        -OL $OWRTPREF/tools/firmware-utils/src/md5.h
+$ cc -o mktplinkfw mktplinkfw.c md5.c
+ at endverbatim
+
+To convert your barebox.bin to U-Boot-loadable image (6F01A8C0.img)
+use this command sequence:
+
+ at verbatim
+$ lzma -c -k barebox.bin > barebox.lzma
+$ ./FW/mktplinkfw -c -H 0x07200103 -W 1 -N TL-WR720N-v3 \
+    -s -F 4Mlzma -k barebox.lzma -o 6F01A8C0.img
+ at endverbatim
+
+You must setup tftp-server on host 192.168.0.1.
+Put your 6F01A8C0.img to tftp-server directory
+(usual /tftpboot or /srv/tftp).
+Connect your board to your tftp-server network via Ethernet.
+
+Next, setup network on MR3020 and run 6F01A8C0.img, e.g.:
+ at verbatim
+hornet> set ipaddr 192.168.0.2
+hornet> set serverip 192.168.0.1
+hornet> tftpboot 0x81000000 6F01A8C0.img
+hornet> bootm 0x81000000
+ at endverbatim
+
+TP-LINK MR3020 links:
+ at li http://www.tp-link.com/en/products/details/?model=TL-MR3020
+ at li http://wiki.openwrt.org/toh/tp-link/tl-mr3020
+ at li https://wikidevi.com/wiki/TP-LINK_TL-MR3020
+
+See also:
+ at li http://www.eeboard.com/wp-content/uploads/downloads/2013/08/AR9331.pdf
+ at li http://squonk42.github.io/TL-WR703N/
+
+*/
-- 
1.9.0



From antonynpavlov at gmail.com  Thu Mar 27 17:26:44 2014
From: antonynpavlov at gmail.com (Antony Pavlov)
Date: Fri, 28 Mar 2014 01:26:44 +0400
Subject: [PATCH 9/9] MIPS: add tplink-mr3020_defconfig
In-Reply-To: <1395955604-12826-1-git-send-email-antonynpavlov@gmail.com>
References: <1395955604-12826-1-git-send-email-antonynpavlov@gmail.com>
Message-ID: <1395955604-12826-10-git-send-email-antonynpavlov@gmail.com>

Signed-off-by: Antony Pavlov <antonynpavlov at gmail.com>
---
 arch/mips/configs/tplink-mr3020_defconfig | 29 +++++++++++++++++++++++++++++
 1 file changed, 29 insertions(+)

diff --git a/arch/mips/configs/tplink-mr3020_defconfig b/arch/mips/configs/tplink-mr3020_defconfig
new file mode 100644
index 0000000..2e925d9
--- /dev/null
+++ b/arch/mips/configs/tplink-mr3020_defconfig
@@ -0,0 +1,29 @@
+CONFIG_BUILTIN_DTB=y
+CONFIG_BUILTIN_DTB_NAME="tplink-mr3020"
+CONFIG_MACH_MIPS_ATH79=y
+CONFIG_LONGHELP=y
+CONFIG_CMDLINE_EDITING=y
+CONFIG_AUTO_COMPLETE=y
+CONFIG_CMD_EDIT=y
+CONFIG_CMD_SLEEP=y
+CONFIG_CMD_LET=y
+CONFIG_CMD_GLOBAL=y
+CONFIG_CMD_LOADB=y
+CONFIG_CMD_LOADY=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_IOMEM=y
+CONFIG_CMD_MM=y
+CONFIG_CMD_SHA1SUM=y
+# CONFIG_CMD_BOOTM is not set
+CONFIG_CMD_RESET=y
+CONFIG_CMD_GO=y
+CONFIG_CMD_OFTREE=y
+CONFIG_CMD_OF_PROPERTY=y
+CONFIG_CMD_OF_NODE=y
+CONFIG_CMD_CLK=y
+CONFIG_OFDEVICE=y
+CONFIG_DRIVER_SERIAL_AR933X=y
+# CONFIG_SPI is not set
+CONFIG_MD5=y
+CONFIG_SHA224=y
+CONFIG_SHA256=y
-- 
1.9.0



From eric at eukrea.com  Thu Mar 27 18:45:56 2014
From: eric at eukrea.com (Eric =?UTF-8?B?QsOpbmFyZA==?=)
Date: Thu, 27 Mar 2014 23:45:56 +0100
Subject: [PATCH 3/3] arm: add defconfig for Embest boards
In-Reply-To: <1395914876.5063.2.camel@weser.hi.pengutronix.de>
References: <1395865363-29307-1-git-send-email-eric@eukrea.com>
 <1395865363-29307-3-git-send-email-eric@eukrea.com>
 <1395914876.5063.2.camel@weser.hi.pengutronix.de>
Message-ID: <20140327234556.6b638f46@e6520eb>

Hi Lucas,

Le Thu, 27 Mar 2014 11:07:56 +0100,
Lucas Stach <l.stach at pengutronix.de> a ?crit :
> Please don't add new configs for multi-image capable boards. If anything
> is missing from the imx_v7_defconfig just add it there. This means at
> least both of your board additions should be reflected in the imx_v7
> defconfig.
> 
OK, I'll include them to imx_v7_defconfig and also will factorize the
dts and board support as both boards are very similar.

Eric


From s.hauer at pengutronix.de  Fri Mar 28 03:46:47 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 28 Mar 2014 08:46:47 +0100
Subject: [PATCH 2/3] MarSBoard: add new board
In-Reply-To: <1395865363-29307-2-git-send-email-eric@eukrea.com>
References: <1395865363-29307-1-git-send-email-eric@eukrea.com>
 <1395865363-29307-2-git-send-email-eric@eukrea.com>
Message-ID: <20140328074647.GA17250@pengutronix.de>

Hi Eric,

On Wed, Mar 26, 2014 at 09:22:42PM +0100, Eric B?nard wrote:
> +}
> +postcore_initcall(marsboard_lwl_init);
> diff --git a/arch/arm/boards/embest-marsboard/env/config-board b/arch/arm/boards/embest-marsboard/env/config-board
> new file mode 100644
> index 0000000..e8e8378
> --- /dev/null
> +++ b/arch/arm/boards/embest-marsboard/env/config-board
> @@ -0,0 +1,6 @@
> +#!/bin/sh
> +
> +# board defaults, do not change in running system. Change /env/config
> +# instead
> +
> +global.linux.bootargs.base="console=ttymxc0,115200"

For the board specific environment I'd like to do the following:

move the $BOARD/env directory to a board specific name, like
$BOARD/marsboard-env. In your board code (when you know that you're
running on the marsboard), do: defaultenv_append_directory(marsboard_env);

For the environment snippet above: You can simply drop it. barebox will
append a correct 'console=' parameter automatically for you.

> +wm 32 0x020c407c 0x0f0000c3
> +wm 32 0x020c4080 0x000003ff
> +/* enable AXI cache for VDOA/VPU/IPU */
> +wm 32 0x020e0010 0xf00000cf
> +/* set IPU AXI-id0 Qos=0xf(bypass AXI-id1 Qos=0x7 */
> +wm 32 0x020e0018 0x007f007f
> +wm 32 0x020e001c 0x007f007f

You can probably drop these. The -next branch has a patch in it which
should do it:

3739b84 ARM i.MX6q: Mark VPU and IPU AXI transfers as cacheable, increase IPU priority

Sascha


-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From antonynpavlov at gmail.com  Fri Mar 28 04:00:00 2014
From: antonynpavlov at gmail.com (Antony Pavlov)
Date: Fri, 28 Mar 2014 12:00:00 +0400
Subject: [PATCH] MIPS: mach-xburst: fix DEBUG_LL=n build error
In-Reply-To: <1395822565-14283-1-git-send-email-antonynpavlov@gmail.com>
References: <1395822565-14283-1-git-send-email-antonynpavlov@gmail.com>
Message-ID: <20140328120000.7a6b0bbc99ec261bd6c88c67@gmail.com>

On Wed, 26 Mar 2014 12:29:25 +0400
Antony Pavlov <antonynpavlov at gmail.com> wrote:

ping

> Here is my error log:
> 
>   CC      common/startup.o
> In file included from arch/mips/mach-xburst/include/mach/debug_ll.h:25,
>                  from include/debug_ll.h:31,
>                  from common/startup.c:36:
> arch/mips/include/asm/debug_ll_ns16550.h: In function 'PUTC_LL':
> arch/mips/include/asm/debug_ll_ns16550.h:62: error: 'DEBUG_LL_UART_ADDR' undeclared (first use in this function)
> arch/mips/include/asm/debug_ll_ns16550.h:62: error: (Each undeclared identifier is reported only once
> arch/mips/include/asm/debug_ll_ns16550.h:62: error: for each function it appears in.)
> make[1]: *** [common/startup.o] Error 1
> 
> Signed-off-by: Antony Pavlov <antonynpavlov at gmail.com>
> ---
>  arch/mips/include/asm/debug_ll_ns16550.h | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/arch/mips/include/asm/debug_ll_ns16550.h b/arch/mips/include/asm/debug_ll_ns16550.h
> index f36010c..032f0a2 100644
> --- a/arch/mips/include/asm/debug_ll_ns16550.h
> +++ b/arch/mips/include/asm/debug_ll_ns16550.h
> @@ -59,9 +59,11 @@
>  
>  static __inline__ void PUTC_LL(char ch)
>  {
> +#ifdef CONFIG_DEBUG_LL
>  	while (!(__raw_readb((u8 *)DEBUG_LL_UART_ADDR + UART_LSR) & UART_LSR_THRE))
>  		;
>  	__raw_writeb(ch, (u8 *)DEBUG_LL_UART_ADDR + UART_THR);
> +#endif /* CONFIG_DEBUG_LL */
>  }
>  #else /* __ASSEMBLY__ */
>  /*
> -- 
> 1.9.0
> 


-- 
--?
Best regards,
? Antony Pavlov


From antonynpavlov at gmail.com  Fri Mar 28 04:01:32 2014
From: antonynpavlov at gmail.com (Antony Pavlov)
Date: Fri, 28 Mar 2014 12:01:32 +0400
Subject: [PATCH] MIPS: lib: add BAREBOX_CLK_TABLE to linker script
In-Reply-To: <1395822642-14342-1-git-send-email-antonynpavlov@gmail.com>
References: <1395822642-14342-1-git-send-email-antonynpavlov@gmail.com>
Message-ID: <20140328120132.60cb4a7d25fb42cda18bdadc@gmail.com>

On Wed, 26 Mar 2014 12:30:42 +0400
Antony Pavlov <antonynpavlov at gmail.com> wrote:

I have included just the same patch into Atheros AR933x series.

> This commit is based on
>     commit fa1a406f7245c5482a17014d5b97e8948352e5a5
>     Author: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
>     Date:   Sat Nov 9 14:24:18 2013 +0100
> 
>         ARM: lib: add BAREBOX_CLK_TABLE to linker script
> 
>         This adds an .oftables section right before .dtb section with
>         BAREBOX_CLK_TABLE to ARM linker script.
> 
> Signed-off-by: Antony Pavlov <antonynpavlov at gmail.com>
> ---
>  arch/mips/lib/barebox.lds.S | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/arch/mips/lib/barebox.lds.S b/arch/mips/lib/barebox.lds.S
> index bc78d2b..4ee4252 100644
> --- a/arch/mips/lib/barebox.lds.S
> +++ b/arch/mips/lib/barebox.lds.S
> @@ -69,6 +69,8 @@ SECTIONS
>  	__usymtab : { BAREBOX_SYMS }
>  	__usymtab_end = .;
>  
> +	.oftables : { BAREBOX_CLK_TABLE() }
> +
>  	.dtb : { BAREBOX_DTB() }
>  
>  	_edata = .;
> -- 
> 1.9.0
> 


-- 
--?
Best regards,
? Antony Pavlov


From s.hauer at pengutronix.de  Fri Mar 28 05:06:00 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 28 Mar 2014 10:06:00 +0100
Subject: [PATCH] MIPS: mach-xburst: fix DEBUG_LL=n build error
In-Reply-To: <1395822565-14283-1-git-send-email-antonynpavlov@gmail.com>
References: <1395822565-14283-1-git-send-email-antonynpavlov@gmail.com>
Message-ID: <20140328090600.GC17250@pengutronix.de>

On Wed, Mar 26, 2014 at 12:29:25PM +0400, Antony Pavlov wrote:
> Here is my error log:
> 
>   CC      common/startup.o
> In file included from arch/mips/mach-xburst/include/mach/debug_ll.h:25,
>                  from include/debug_ll.h:31,
>                  from common/startup.c:36:
> arch/mips/include/asm/debug_ll_ns16550.h: In function 'PUTC_LL':
> arch/mips/include/asm/debug_ll_ns16550.h:62: error: 'DEBUG_LL_UART_ADDR' undeclared (first use in this function)
> arch/mips/include/asm/debug_ll_ns16550.h:62: error: (Each undeclared identifier is reported only once
> arch/mips/include/asm/debug_ll_ns16550.h:62: error: for each function it appears in.)
> make[1]: *** [common/startup.o] Error 1
> 
> Signed-off-by: Antony Pavlov <antonynpavlov at gmail.com>

Applied, thanks

Sascha

> ---
>  arch/mips/include/asm/debug_ll_ns16550.h | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/arch/mips/include/asm/debug_ll_ns16550.h b/arch/mips/include/asm/debug_ll_ns16550.h
> index f36010c..032f0a2 100644
> --- a/arch/mips/include/asm/debug_ll_ns16550.h
> +++ b/arch/mips/include/asm/debug_ll_ns16550.h
> @@ -59,9 +59,11 @@
>  
>  static __inline__ void PUTC_LL(char ch)
>  {
> +#ifdef CONFIG_DEBUG_LL
>  	while (!(__raw_readb((u8 *)DEBUG_LL_UART_ADDR + UART_LSR) & UART_LSR_THRE))
>  		;
>  	__raw_writeb(ch, (u8 *)DEBUG_LL_UART_ADDR + UART_THR);
> +#endif /* CONFIG_DEBUG_LL */
>  }
>  #else /* __ASSEMBLY__ */
>  /*
> -- 
> 1.9.0
> 
> 
> _______________________________________________
> barebox mailing list
> barebox at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/barebox
> 

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From s.hauer at pengutronix.de  Fri Mar 28 05:06:47 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 28 Mar 2014 10:06:47 +0100
Subject: [PATCH] MIPS: lib: add BAREBOX_CLK_TABLE to linker script
In-Reply-To: <20140328120132.60cb4a7d25fb42cda18bdadc@gmail.com>
References: <1395822642-14342-1-git-send-email-antonynpavlov@gmail.com>
 <20140328120132.60cb4a7d25fb42cda18bdadc@gmail.com>
Message-ID: <20140328090647.GD17250@pengutronix.de>

On Fri, Mar 28, 2014 at 12:01:32PM +0400, Antony Pavlov wrote:
> On Wed, 26 Mar 2014 12:30:42 +0400
> Antony Pavlov <antonynpavlov at gmail.com> wrote:
> 
> I have included just the same patch into Atheros AR933x series.

Ok, I'll just ignore this one then.

Sascha

> 
> > This commit is based on
> >     commit fa1a406f7245c5482a17014d5b97e8948352e5a5
> >     Author: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
> >     Date:   Sat Nov 9 14:24:18 2013 +0100
> > 
> >         ARM: lib: add BAREBOX_CLK_TABLE to linker script
> > 
> >         This adds an .oftables section right before .dtb section with
> >         BAREBOX_CLK_TABLE to ARM linker script.
> > 
> > Signed-off-by: Antony Pavlov <antonynpavlov at gmail.com>
> > ---
> >  arch/mips/lib/barebox.lds.S | 2 ++
> >  1 file changed, 2 insertions(+)
> > 
> > diff --git a/arch/mips/lib/barebox.lds.S b/arch/mips/lib/barebox.lds.S
> > index bc78d2b..4ee4252 100644
> > --- a/arch/mips/lib/barebox.lds.S
> > +++ b/arch/mips/lib/barebox.lds.S
> > @@ -69,6 +69,8 @@ SECTIONS
> >  	__usymtab : { BAREBOX_SYMS }
> >  	__usymtab_end = .;
> >  
> > +	.oftables : { BAREBOX_CLK_TABLE() }
> > +
> >  	.dtb : { BAREBOX_DTB() }
> >  
> >  	_edata = .;
> > -- 
> > 1.9.0
> > 
> 
> 
> -- 
> --?
> Best regards,
> ? Antony Pavlov
> 

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From s.hauer at pengutronix.de  Fri Mar 28 05:14:40 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 28 Mar 2014 10:14:40 +0100
Subject: Add support for creating menus from a directory structure
Message-ID: <1395998083-18979-1-git-send-email-s.hauer@pengutronix.de>

The current menu command makes it quite difficult to create a menu
from the shell. This series adds a menutree command which allows it
to create a menu from a directory structure. Each directory in this
structure represents a menu entry. Subdirectories are submenus. The
defenv-2 menu is then converted to use the menutree command.

Sascha

----------------------------------------------------------------
Sascha Hauer (3):
      Add shell_expand function
      add menutree command
      defenv-2: replace menu with menutree

 commands/Kconfig                                   |   8 +
 commands/Makefile                                  |   1 +
 commands/menutree.c                                |  60 +++++++
 common/Kconfig                                     |   5 +-
 common/Makefile                                    |   1 +
 common/hush.c                                      |  33 ++++
 common/menutree.c                                  | 181 +++++++++++++++++++++
 .../defaultenv-2-menu/menu/00-boot-default/action  |   5 +
 .../defaultenv-2-menu/menu/00-boot-default/title   |   1 +
 .../defaultenv-2-menu/menu/10-boot-all/action      |   3 +
 .../defaultenv-2-menu/menu/10-boot-all/net/action  |   5 +
 .../defaultenv-2-menu/menu/10-boot-all/net/title   |   1 +
 .../defaultenv-2-menu/menu/10-boot-all/title       |   1 +
 .../menu/20-settings/config/action                 |   5 +
 .../menu/20-settings/config/title                  |   1 +
 .../menu/20-settings/network/action                |   3 +
 .../menu/20-settings/network/title                 |   1 +
 .../defaultenv-2-menu/menu/20-settings/title       |   1 +
 .../defaultenv-2-menu/menu/30-saveenv/action       |   8 +
 defaultenv/defaultenv-2-menu/menu/30-saveenv/title |   1 +
 defaultenv/defaultenv-2-menu/menu/40-shell/action  |   5 +
 defaultenv/defaultenv-2-menu/menu/40-shell/title   |   1 +
 defaultenv/defaultenv-2-menu/menu/50-reset/action  |   3 +
 defaultenv/defaultenv-2-menu/menu/50-reset/title   |   1 +
 .../defaultenv-2-menu/menu/boot-entries-collect    |  13 --
 .../defaultenv-2-menu/menu/boot-entries-edit       |  20 ---
 .../defaultenv-2-menu/menu/boot-entries-remove     |  18 --
 .../defaultenv-2-menu/menu/boot-menu-add-entry     |   5 -
 .../menu/boot-menu-new-boot-entry                  |  21 ---
 .../defaultenv-2-menu/menu/init-entries-collect    |   9 -
 .../defaultenv-2-menu/menu/init-entries-edit       |  20 ---
 .../defaultenv-2-menu/menu/init-menu-add-entry     |   3 -
 defaultenv/defaultenv-2-menu/menu/mainmenu         |  20 +--
 defaultenv/defaultenv-2-menu/menu/settings         |  21 ---
 defaultenv/defaultenv-2-menu/menu/title            |   1 +
 include/common.h                                   |   9 +
 include/menu.h                                     |   2 +
 37 files changed, 347 insertions(+), 150 deletions(-)
 create mode 100644 commands/menutree.c
 create mode 100644 common/menutree.c
 create mode 100644 defaultenv/defaultenv-2-menu/menu/00-boot-default/action
 create mode 100644 defaultenv/defaultenv-2-menu/menu/00-boot-default/title
 create mode 100644 defaultenv/defaultenv-2-menu/menu/10-boot-all/action
 create mode 100644 defaultenv/defaultenv-2-menu/menu/10-boot-all/net/action
 create mode 100644 defaultenv/defaultenv-2-menu/menu/10-boot-all/net/title
 create mode 100644 defaultenv/defaultenv-2-menu/menu/10-boot-all/title
 create mode 100644 defaultenv/defaultenv-2-menu/menu/20-settings/config/action
 create mode 100644 defaultenv/defaultenv-2-menu/menu/20-settings/config/title
 create mode 100644 defaultenv/defaultenv-2-menu/menu/20-settings/network/action
 create mode 100644 defaultenv/defaultenv-2-menu/menu/20-settings/network/title
 create mode 100644 defaultenv/defaultenv-2-menu/menu/20-settings/title
 create mode 100644 defaultenv/defaultenv-2-menu/menu/30-saveenv/action
 create mode 100644 defaultenv/defaultenv-2-menu/menu/30-saveenv/title
 create mode 100644 defaultenv/defaultenv-2-menu/menu/40-shell/action
 create mode 100644 defaultenv/defaultenv-2-menu/menu/40-shell/title
 create mode 100644 defaultenv/defaultenv-2-menu/menu/50-reset/action
 create mode 100644 defaultenv/defaultenv-2-menu/menu/50-reset/title
 delete mode 100644 defaultenv/defaultenv-2-menu/menu/boot-entries-collect
 delete mode 100644 defaultenv/defaultenv-2-menu/menu/boot-entries-edit
 delete mode 100644 defaultenv/defaultenv-2-menu/menu/boot-entries-remove
 delete mode 100644 defaultenv/defaultenv-2-menu/menu/boot-menu-add-entry
 delete mode 100644 defaultenv/defaultenv-2-menu/menu/boot-menu-new-boot-entry
 delete mode 100644 defaultenv/defaultenv-2-menu/menu/init-entries-collect
 delete mode 100644 defaultenv/defaultenv-2-menu/menu/init-entries-edit
 delete mode 100644 defaultenv/defaultenv-2-menu/menu/init-menu-add-entry
 delete mode 100644 defaultenv/defaultenv-2-menu/menu/settings
 create mode 100644 defaultenv/defaultenv-2-menu/menu/title


From s.hauer at pengutronix.de  Fri Mar 28 05:14:41 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 28 Mar 2014 10:14:41 +0100
Subject: [PATCH 1/3] Add shell_expand function
In-Reply-To: <1395998083-18979-1-git-send-email-s.hauer@pengutronix.de>
References: <1395998083-18979-1-git-send-email-s.hauer@pengutronix.de>
Message-ID: <1395998083-18979-2-git-send-email-s.hauer@pengutronix.de>

shell_expand expands shell variables in a string.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 common/hush.c    | 33 +++++++++++++++++++++++++++++++++
 include/common.h |  9 +++++++++
 2 files changed, 42 insertions(+)

diff --git a/common/hush.c b/common/hush.c
index bd534c1..1447fdb 100644
--- a/common/hush.c
+++ b/common/hush.c
@@ -1637,6 +1637,39 @@ static void update_ifs_map(void)
 	mapset(ifs, 2);			/* also flow through if quoted */
 }
 
+/*
+ * shell_expand - Expand shell variables in a string.
+ * @str:	The input string containing shell variables like
+ *		$var or ${var}
+ * Return:	The expanded string. Must be freed with free().
+ */
+char *shell_expand(char *str)
+{
+	struct p_context ctx = {};
+	o_string o = {};
+	char *res, *parsed;
+
+	remove_quotes_in_str(str);
+
+	o.quote = 1;
+
+	initialize_context(&ctx);
+
+	parse_string(&o, &ctx, str);
+
+	parsed = xmemdup(o.data, o.length + 1);
+	parsed[o.length] = 0;
+
+	res = insert_var_value(parsed);
+	if (res != parsed)
+		free(parsed);
+
+	free_pipe_list(ctx.list_head, 0);
+	b_free(&o);
+
+	return res;
+}
+
 /* most recursion does not come through here, the exeception is
  * from builtin_source() */
 static int parse_stream_outer(struct p_context *ctx, struct in_str *inp, int flag)
diff --git a/include/common.h b/include/common.h
index 6987b4f..bfd3ce8 100644
--- a/include/common.h
+++ b/include/common.h
@@ -165,6 +165,15 @@ void arch_shutdown(void);
 
 int run_shell(void);
 
+#ifdef CONFIG_SHELL_HUSH
+char *shell_expand(char *str);
+#else
+static inline char *shell_expand(char *str)
+{
+	return strdup(str);
+}
+#endif
+
 /* Force a compilation error if condition is true */
 #define BUILD_BUG_ON(condition) ((void)BUILD_BUG_ON_ZERO(condition))
 
-- 
1.9.0



From s.hauer at pengutronix.de  Fri Mar 28 05:14:42 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 28 Mar 2014 10:14:42 +0100
Subject: [PATCH 2/3] add menutree command
In-Reply-To: <1395998083-18979-1-git-send-email-s.hauer@pengutronix.de>
References: <1395998083-18979-1-git-send-email-s.hauer@pengutronix.de>
Message-ID: <1395998083-18979-3-git-send-email-s.hauer@pengutronix.de>

Creating menus from the shell using the regular 'menu' command is rather
complicated. This adds a 'menutree' command which creates a menu from
a directory structure. In the directory structure each directory corresponds
to a single menu entry. The directory contains the following files:

title -  A file containing the title of the entry as shown in the menu
box -    If present, the entry is a 'bool' entry. The file contains a variable
         name from which the current state of the bool is taken from and saved
         to.
action - if present this file contains a shell script which is executed when
         when the entry is selected.

If neither 'box' or 'action' are present this entry is considered a submenu
containing more entries.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 commands/Kconfig    |   8 +++
 commands/Makefile   |   1 +
 commands/menutree.c |  60 +++++++++++++++++
 common/Kconfig      |   3 +
 common/Makefile     |   1 +
 common/menutree.c   | 181 ++++++++++++++++++++++++++++++++++++++++++++++++++++
 include/menu.h      |   2 +
 7 files changed, 256 insertions(+)
 create mode 100644 commands/menutree.c
 create mode 100644 common/menutree.c

diff --git a/commands/Kconfig b/commands/Kconfig
index 352e8bf..cc014f3 100644
--- a/commands/Kconfig
+++ b/commands/Kconfig
@@ -90,6 +90,14 @@ config CMD_MENU_MANAGEMENT
 	depends on CMD_MENU
 	prompt "menu scripts management"
 
+config CMD_MENUTREE
+	bool
+	depends on MENU
+	select MENUTREE
+	prompt "menutree"
+	help
+	  The menutree command allows to create a menu from a directory structure
+
 config CMD_LOGIN
 	tristate
 	select PASSWORD
diff --git a/commands/Makefile b/commands/Makefile
index 91ec0e9..e463031 100644
--- a/commands/Makefile
+++ b/commands/Makefile
@@ -94,3 +94,4 @@ obj-$(CONFIG_CMD_DETECT)	+= detect.o
 obj-$(CONFIG_CMD_BOOT)		+= boot.o
 obj-$(CONFIG_CMD_DEVINFO)	+= devinfo.o
 obj-$(CONFIG_CMD_READF)		+= readf.o
+obj-$(CONFIG_CMD_MENUTREE)	+= menutree.o
diff --git a/commands/menutree.c b/commands/menutree.c
new file mode 100644
index 0000000..3b1a263
--- /dev/null
+++ b/commands/menutree.c
@@ -0,0 +1,60 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include <command.h>
+#include <common.h>
+#include <getopt.h>
+#include <menu.h>
+
+static int do_menutree(int argc, char *argv[])
+{
+	int opt, ret;
+	char *path = "/env/menu";
+
+	while ((opt = getopt(argc, argv, "m:")) > 0) {
+		switch (opt) {
+		case 'm':
+			path = optarg;
+			break;
+		}
+	}
+
+	ret = menutree(path, 1);
+
+	return ret;
+}
+
+BAREBOX_CMD_HELP_START(menutree)
+BAREBOX_CMD_HELP_USAGE("menutree [OPTIONS]\n")
+"\n"
+"Create a menu from a directory structure\n"
+"Each menu entry is described by a subdirectory. Each subdirectory\n"
+"can contain the following files which further describe the entry:\n"
+"\n"
+"title -  A file containing the title of the entry as shown in the menu\n"
+"box -    If present, the entry is a 'bool' entry. The file contains a variable\n"
+"         name from which the current state of the bool is taken from and saved\n"
+"         to.\n"
+"action - if present this file contains a shell script which is executed when\n"
+"         when the entry is selected.\n"
+"If neither 'box' or 'action' are present this entry is considered a submenu\n"
+"containing more entries.\n"
+"\n"
+"Options:\n"
+" -m <dir>     directory where the menu starts (/env/menu)\n"
+
+BAREBOX_CMD_HELP_END
+
+
+BAREBOX_CMD_START(menutree)
+	.cmd	= do_menutree,
+	.usage		= "create a menu from a directory structure",
+	BAREBOX_CMD_HELP(cmd_menutree_help)
+BAREBOX_CMD_END
diff --git a/common/Kconfig b/common/Kconfig
index 84c52fc..bc54e97 100644
--- a/common/Kconfig
+++ b/common/Kconfig
@@ -62,6 +62,9 @@ config STDDEV
 config BAREBOX_UPDATE
 	bool
 
+config MENUTREE
+	bool
+
 menu "General Settings"
 
 config LOCALVERSION
diff --git a/common/Makefile b/common/Makefile
index 667c7b3..204241c 100644
--- a/common/Makefile
+++ b/common/Makefile
@@ -43,6 +43,7 @@ obj-$(CONFIG_RESET_SOURCE)	+= reset_source.o
 obj-$(CONFIG_SHELL_HUSH)	+= hush.o
 obj-$(CONFIG_SHELL_SIMPLE)	+= parser.o
 obj-$(CONFIG_UIMAGE)		+= image.o uimage.o
+obj-$(CONFIG_MENUTREE) += menutree.o
 
 quiet_cmd_pwd_h = PWDH    $@
 ifdef CONFIG_PASSWORD
diff --git a/common/menutree.c b/common/menutree.c
new file mode 100644
index 0000000..814512d
--- /dev/null
+++ b/common/menutree.c
@@ -0,0 +1,181 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <environment.h>
+#include <libbb.h>
+#include <common.h>
+#include <glob.h>
+#include <menu.h>
+#include <fs.h>
+
+#include <linux/stat.h>
+
+struct menutree {
+	char *action;
+	struct menu_entry me;
+};
+
+static void menutree_action_subdir(struct menu *m, struct menu_entry *me)
+{
+	struct menutree *mt = container_of(me, struct menutree, me);
+
+	menutree(mt->action, 0);
+}
+
+static void menutree_action(struct menu *m, struct menu_entry *me)
+{
+	struct menutree *mt = container_of(me, struct menutree, me);
+
+	run_command(mt->action);
+}
+
+static void setenv_bool(const char *var, bool val)
+{
+	const char *str;
+
+	if (val)
+		str = "1";
+	else
+		str = "0";
+
+	setenv(var, str);
+}
+
+static void menutree_box(struct menu *m, struct menu_entry *me)
+{
+	struct menutree *mt = container_of(me, struct menutree, me);
+
+	setenv_bool(mt->action, me->box_state);
+}
+
+static void menutree_entry_free(struct menu_entry *me)
+{
+	struct menutree *mt = container_of(me, struct menutree, me);
+
+	free(mt->action);
+	free(mt->me.display);
+	free(mt);
+}
+
+/*
+ * menutree - show a menu constructed from a directory structure
+ * @path: the path to the directory structure
+ *
+ * Each menu entry is described by a subdirectory. Each subdirectory
+ * can contain the following files which further describe the entry:
+ *
+ * title - A file containing the title of the entry as shown in the menu
+ * box - If present, the entry is a 'bool' entry. The file contains a variable
+ *       name from which the current state of the bool is taken from and saved
+ *       to.
+ * action - if present this file contains a shell script which is executed when
+ *          when the entry is selected.
+ *
+ * If neither 'box' or 'action' are present this entry is considered a submenu
+ * containing more entries.
+ */
+int menutree(const char *path, int toplevel)
+{
+	int ret;
+	struct menu *menu;
+	struct stat s;
+	char *box;
+	struct menutree *mt;
+	glob_t g;
+	int i;
+	char *globpath, *display;
+
+	menu = menu_alloc();
+
+	globpath = asprintf("%s/*", path);
+	ret = glob(globpath, 0, NULL, &g);
+	free(globpath);
+	if (ret == GLOB_NOMATCH) {
+		ret = -EINVAL;
+		goto out;
+	}
+
+	display = read_file_line("%s/title", path);
+	if (!display) {
+		eprintf("no title found in %s/title\n", path);
+		ret = -EINVAL;
+		goto out;
+	}
+
+	menu->display = shell_expand(display);
+	free(display);
+
+	for (i = 0; i < g.gl_pathc; i++) {
+		ret = stat(g.gl_pathv[i], &s);
+		if (ret)
+			goto out;
+
+		if (!S_ISDIR(s.st_mode))
+			continue;
+
+		mt = xzalloc(sizeof(*mt));
+
+		display = read_file_line("%s/title", g.gl_pathv[i]);
+		if (!display) {
+			eprintf("no title found in %s/title\n", g.gl_pathv[i]);
+			ret = -EINVAL;
+			goto out;
+		}
+
+		mt->me.display = shell_expand(display);
+		free(display);
+		mt->me.free = menutree_entry_free;
+
+		box = read_file_line("%s/box", g.gl_pathv[i]);
+		if (box) {
+			mt->me.type = MENU_ENTRY_BOX;
+			mt->me.action = menutree_box;
+			mt->action = box;
+			getenv_bool(box, &mt->me.box_state);
+			menu_add_entry(menu, &mt->me);
+			continue;
+		}
+
+		mt->me.type = MENU_ENTRY_NORMAL;
+
+		mt->action = asprintf("%s/action", g.gl_pathv[i]);
+
+		ret = stat(mt->action, &s);
+		if (ret) {
+			mt->me.action = menutree_action_subdir;
+			free(mt->action);
+			mt->action = xstrdup(g.gl_pathv[i]);
+		} else {
+			mt->me.action = menutree_action;
+		}
+
+		menu_add_entry(menu, &mt->me);
+	}
+
+	if (!toplevel) {
+		mt = xzalloc(sizeof(*mt));
+		mt->me.display = xstrdup("back");
+		mt->me.type = MENU_ENTRY_NORMAL;
+		mt->me.non_re_ent = 1;
+		mt->me.free = menutree_entry_free;
+		menu_add_entry(menu, &mt->me);
+	}
+
+	menu_show(menu);
+
+	ret = 0;
+out:
+	menu_free(menu);
+
+	globfree(&g);
+
+	return ret;
+}
diff --git a/include/menu.h b/include/menu.h
index f63a405..8b0ffb1 100644
--- a/include/menu.h
+++ b/include/menu.h
@@ -106,4 +106,6 @@ struct menu_entry* menu_entry_get_by_num(struct menu* m, int num);
  */
 void menu_action_exit(struct menu *m, struct menu_entry *me);
 
+int menutree(const char *path, int toplevel);
+
 #endif /* __MENU_H__ */
-- 
1.9.0



From s.hauer at pengutronix.de  Fri Mar 28 05:14:43 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 28 Mar 2014 10:14:43 +0100
Subject: [PATCH 3/3] defenv-2: replace menu with menutree
In-Reply-To: <1395998083-18979-1-git-send-email-s.hauer@pengutronix.de>
References: <1395998083-18979-1-git-send-email-s.hauer@pengutronix.de>
Message-ID: <1395998083-18979-4-git-send-email-s.hauer@pengutronix.de>

This makes the menu easier to extend and to maintain.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 common/Kconfig                                      |  2 +-
 .../defaultenv-2-menu/menu/00-boot-default/action   |  5 +++++
 .../defaultenv-2-menu/menu/00-boot-default/title    |  1 +
 .../defaultenv-2-menu/menu/10-boot-all/action       |  3 +++
 .../defaultenv-2-menu/menu/10-boot-all/net/action   |  5 +++++
 .../defaultenv-2-menu/menu/10-boot-all/net/title    |  1 +
 defaultenv/defaultenv-2-menu/menu/10-boot-all/title |  1 +
 .../menu/20-settings/config/action                  |  5 +++++
 .../defaultenv-2-menu/menu/20-settings/config/title |  1 +
 .../menu/20-settings/network/action                 |  3 +++
 .../menu/20-settings/network/title                  |  1 +
 defaultenv/defaultenv-2-menu/menu/20-settings/title |  1 +
 defaultenv/defaultenv-2-menu/menu/30-saveenv/action |  8 ++++++++
 defaultenv/defaultenv-2-menu/menu/30-saveenv/title  |  1 +
 defaultenv/defaultenv-2-menu/menu/40-shell/action   |  5 +++++
 defaultenv/defaultenv-2-menu/menu/40-shell/title    |  1 +
 defaultenv/defaultenv-2-menu/menu/50-reset/action   |  3 +++
 defaultenv/defaultenv-2-menu/menu/50-reset/title    |  1 +
 .../defaultenv-2-menu/menu/boot-entries-collect     | 13 -------------
 defaultenv/defaultenv-2-menu/menu/boot-entries-edit | 20 --------------------
 .../defaultenv-2-menu/menu/boot-entries-remove      | 18 ------------------
 .../defaultenv-2-menu/menu/boot-menu-add-entry      |  5 -----
 .../defaultenv-2-menu/menu/boot-menu-new-boot-entry | 21 ---------------------
 .../defaultenv-2-menu/menu/init-entries-collect     |  9 ---------
 defaultenv/defaultenv-2-menu/menu/init-entries-edit | 20 --------------------
 .../defaultenv-2-menu/menu/init-menu-add-entry      |  3 ---
 defaultenv/defaultenv-2-menu/menu/mainmenu          | 20 +-------------------
 defaultenv/defaultenv-2-menu/menu/settings          | 21 ---------------------
 defaultenv/defaultenv-2-menu/menu/title             |  1 +
 29 files changed, 49 insertions(+), 150 deletions(-)
 create mode 100644 defaultenv/defaultenv-2-menu/menu/00-boot-default/action
 create mode 100644 defaultenv/defaultenv-2-menu/menu/00-boot-default/title
 create mode 100644 defaultenv/defaultenv-2-menu/menu/10-boot-all/action
 create mode 100644 defaultenv/defaultenv-2-menu/menu/10-boot-all/net/action
 create mode 100644 defaultenv/defaultenv-2-menu/menu/10-boot-all/net/title
 create mode 100644 defaultenv/defaultenv-2-menu/menu/10-boot-all/title
 create mode 100644 defaultenv/defaultenv-2-menu/menu/20-settings/config/action
 create mode 100644 defaultenv/defaultenv-2-menu/menu/20-settings/config/title
 create mode 100644 defaultenv/defaultenv-2-menu/menu/20-settings/network/action
 create mode 100644 defaultenv/defaultenv-2-menu/menu/20-settings/network/title
 create mode 100644 defaultenv/defaultenv-2-menu/menu/20-settings/title
 create mode 100644 defaultenv/defaultenv-2-menu/menu/30-saveenv/action
 create mode 100644 defaultenv/defaultenv-2-menu/menu/30-saveenv/title
 create mode 100644 defaultenv/defaultenv-2-menu/menu/40-shell/action
 create mode 100644 defaultenv/defaultenv-2-menu/menu/40-shell/title
 create mode 100644 defaultenv/defaultenv-2-menu/menu/50-reset/action
 create mode 100644 defaultenv/defaultenv-2-menu/menu/50-reset/title
 delete mode 100644 defaultenv/defaultenv-2-menu/menu/boot-entries-collect
 delete mode 100644 defaultenv/defaultenv-2-menu/menu/boot-entries-edit
 delete mode 100644 defaultenv/defaultenv-2-menu/menu/boot-entries-remove
 delete mode 100644 defaultenv/defaultenv-2-menu/menu/boot-menu-add-entry
 delete mode 100644 defaultenv/defaultenv-2-menu/menu/boot-menu-new-boot-entry
 delete mode 100644 defaultenv/defaultenv-2-menu/menu/init-entries-collect
 delete mode 100644 defaultenv/defaultenv-2-menu/menu/init-entries-edit
 delete mode 100644 defaultenv/defaultenv-2-menu/menu/init-menu-add-entry
 delete mode 100644 defaultenv/defaultenv-2-menu/menu/settings
 create mode 100644 defaultenv/defaultenv-2-menu/menu/title

diff --git a/common/Kconfig b/common/Kconfig
index bc54e97..0031cc8 100644
--- a/common/Kconfig
+++ b/common/Kconfig
@@ -605,7 +605,7 @@ config DEFAULT_ENVIRONMENT_GENERIC_NEW
 config DEFAULT_ENVIRONMENT_GENERIC_NEW_MENU
 	bool
 	depends on DEFAULT_ENVIRONMENT_GENERIC_NEW
-	depends on CMD_MENU_MANAGEMENT
+	depends on CMD_MENUTREE
 	default y
 
 config DEFAULT_ENVIRONMENT_GENERIC_NEW_DFU
diff --git a/defaultenv/defaultenv-2-menu/menu/00-boot-default/action b/defaultenv/defaultenv-2-menu/menu/00-boot-default/action
new file mode 100644
index 0000000..3d72ff6
--- /dev/null
+++ b/defaultenv/defaultenv-2-menu/menu/00-boot-default/action
@@ -0,0 +1,5 @@
+#!/bin/sh
+
+boot
+
+readline "Booting failed. Press any key to continue" ignore
diff --git a/defaultenv/defaultenv-2-menu/menu/00-boot-default/title b/defaultenv/defaultenv-2-menu/menu/00-boot-default/title
new file mode 100644
index 0000000..ef8c3dd
--- /dev/null
+++ b/defaultenv/defaultenv-2-menu/menu/00-boot-default/title
@@ -0,0 +1 @@
+Boot default
diff --git a/defaultenv/defaultenv-2-menu/menu/10-boot-all/action b/defaultenv/defaultenv-2-menu/menu/10-boot-all/action
new file mode 100644
index 0000000..a890ffe
--- /dev/null
+++ b/defaultenv/defaultenv-2-menu/menu/10-boot-all/action
@@ -0,0 +1,3 @@
+#!/bin/sh
+
+boot -m
diff --git a/defaultenv/defaultenv-2-menu/menu/10-boot-all/net/action b/defaultenv/defaultenv-2-menu/menu/10-boot-all/net/action
new file mode 100644
index 0000000..b31b0e4
--- /dev/null
+++ b/defaultenv/defaultenv-2-menu/menu/10-boot-all/net/action
@@ -0,0 +1,5 @@
+#!/bin/sh
+
+echo "Boot from Network...."
+
+sleep 3
diff --git a/defaultenv/defaultenv-2-menu/menu/10-boot-all/net/title b/defaultenv/defaultenv-2-menu/menu/10-boot-all/net/title
new file mode 100644
index 0000000..79a6d8f
--- /dev/null
+++ b/defaultenv/defaultenv-2-menu/menu/10-boot-all/net/title
@@ -0,0 +1 @@
+Boot from network
diff --git a/defaultenv/defaultenv-2-menu/menu/10-boot-all/title b/defaultenv/defaultenv-2-menu/menu/10-boot-all/title
new file mode 100644
index 0000000..0f05e98
--- /dev/null
+++ b/defaultenv/defaultenv-2-menu/menu/10-boot-all/title
@@ -0,0 +1 @@
+Detect bootsources
diff --git a/defaultenv/defaultenv-2-menu/menu/20-settings/config/action b/defaultenv/defaultenv-2-menu/menu/20-settings/config/action
new file mode 100644
index 0000000..9a993af
--- /dev/null
+++ b/defaultenv/defaultenv-2-menu/menu/20-settings/config/action
@@ -0,0 +1,5 @@
+#!/bin/sh
+
+edit /env/config
+
+/env/config
diff --git a/defaultenv/defaultenv-2-menu/menu/20-settings/config/title b/defaultenv/defaultenv-2-menu/menu/20-settings/config/title
new file mode 100644
index 0000000..a8955a9
--- /dev/null
+++ b/defaultenv/defaultenv-2-menu/menu/20-settings/config/title
@@ -0,0 +1 @@
+Config settings
diff --git a/defaultenv/defaultenv-2-menu/menu/20-settings/network/action b/defaultenv/defaultenv-2-menu/menu/20-settings/network/action
new file mode 100644
index 0000000..d27a77f
--- /dev/null
+++ b/defaultenv/defaultenv-2-menu/menu/20-settings/network/action
@@ -0,0 +1,3 @@
+#!/bin/sh
+
+edit /env/network/eth0
diff --git a/defaultenv/defaultenv-2-menu/menu/20-settings/network/title b/defaultenv/defaultenv-2-menu/menu/20-settings/network/title
new file mode 100644
index 0000000..4641d48
--- /dev/null
+++ b/defaultenv/defaultenv-2-menu/menu/20-settings/network/title
@@ -0,0 +1 @@
+Network settings
diff --git a/defaultenv/defaultenv-2-menu/menu/20-settings/title b/defaultenv/defaultenv-2-menu/menu/20-settings/title
new file mode 100644
index 0000000..163d304
--- /dev/null
+++ b/defaultenv/defaultenv-2-menu/menu/20-settings/title
@@ -0,0 +1 @@
+Settings
diff --git a/defaultenv/defaultenv-2-menu/menu/30-saveenv/action b/defaultenv/defaultenv-2-menu/menu/30-saveenv/action
new file mode 100644
index 0000000..c6aed70
--- /dev/null
+++ b/defaultenv/defaultenv-2-menu/menu/30-saveenv/action
@@ -0,0 +1,8 @@
+#!/bin/sh
+
+saveenv
+if [ $? != 0 ]; then
+	echo "saving environment failed"
+fi
+
+sleep 2
diff --git a/defaultenv/defaultenv-2-menu/menu/30-saveenv/title b/defaultenv/defaultenv-2-menu/menu/30-saveenv/title
new file mode 100644
index 0000000..8ae292d
--- /dev/null
+++ b/defaultenv/defaultenv-2-menu/menu/30-saveenv/title
@@ -0,0 +1 @@
+Save environment
diff --git a/defaultenv/defaultenv-2-menu/menu/40-shell/action b/defaultenv/defaultenv-2-menu/menu/40-shell/action
new file mode 100644
index 0000000..fd5bc2b
--- /dev/null
+++ b/defaultenv/defaultenv-2-menu/menu/40-shell/action
@@ -0,0 +1,5 @@
+#!/bin/sh
+
+echo "Enter 'exit' to get back to the menu"
+
+sh
diff --git a/defaultenv/defaultenv-2-menu/menu/40-shell/title b/defaultenv/defaultenv-2-menu/menu/40-shell/title
new file mode 100644
index 0000000..6567bb2
--- /dev/null
+++ b/defaultenv/defaultenv-2-menu/menu/40-shell/title
@@ -0,0 +1 @@
+Shell
diff --git a/defaultenv/defaultenv-2-menu/menu/50-reset/action b/defaultenv/defaultenv-2-menu/menu/50-reset/action
new file mode 100644
index 0000000..61d5c9a
--- /dev/null
+++ b/defaultenv/defaultenv-2-menu/menu/50-reset/action
@@ -0,0 +1,3 @@
+#!/bin/sh
+
+reset
diff --git a/defaultenv/defaultenv-2-menu/menu/50-reset/title b/defaultenv/defaultenv-2-menu/menu/50-reset/title
new file mode 100644
index 0000000..6d9fd4d
--- /dev/null
+++ b/defaultenv/defaultenv-2-menu/menu/50-reset/title
@@ -0,0 +1 @@
+Reset
diff --git a/defaultenv/defaultenv-2-menu/menu/boot-entries-collect b/defaultenv/defaultenv-2-menu/menu/boot-entries-collect
deleted file mode 100644
index c066c93..0000000
--- a/defaultenv/defaultenv-2-menu/menu/boot-entries-collect
+++ /dev/null
@@ -1,13 +0,0 @@
-#!/bin/sh
-
-cd /env/boot
-
-./$global.boot.default menu
-
-for i in *; do
-	if [ "$i" != "$global.boot.default" ]; then
-		./$i menu
-	fi
-done
-
-cd /
diff --git a/defaultenv/defaultenv-2-menu/menu/boot-entries-edit b/defaultenv/defaultenv-2-menu/menu/boot-entries-edit
deleted file mode 100644
index c4e1c3d..0000000
--- a/defaultenv/defaultenv-2-menu/menu/boot-entries-edit
+++ /dev/null
@@ -1,20 +0,0 @@
-#!/bin/sh
-
-export menu_exit=false
-
-while true; do
-	menu -a -m boot_entries_edit -d "\e[1;36mEdit boot entries\e[0m"
-
-	boot-entries-collect
-
-	menu -e -a -m boot_entries_edit -c "boot-menu-new-boot-entry" -d "Add a new entry"
-	menu -e -a -m boot_entries_edit -c "boot-entries-remove" -d "Remove an entry"
-	menu -e -a -m boot_entries_edit -c "menu_exit=true" -d "back"
-
-	menu -s -m boot_entries_edit
-	menu -r -m boot_entries_edit
-
-	if [ $menu_exit = true ]; then
-		exit
-	fi
-done
diff --git a/defaultenv/defaultenv-2-menu/menu/boot-entries-remove b/defaultenv/defaultenv-2-menu/menu/boot-entries-remove
deleted file mode 100644
index 566be9d..0000000
--- a/defaultenv/defaultenv-2-menu/menu/boot-entries-remove
+++ /dev/null
@@ -1,18 +0,0 @@
-#!/bin/sh
-
-export menu_exit=false
-
-while true; do
-	menu -a -m boot_entries_remove -d "\e[1;36mRemove Boot entry\e[0m"
-
-	boot-entries-collect
-
-	menu -e -a -m boot_entries_remove -c "menu_exit=true" -d "back"
-
-	menu -s -m boot_entries_remove
-	menu -r -m boot_entries_remove
-
-	if [ $menu_exit = true ]; then
-		exit
-	fi
-done
diff --git a/defaultenv/defaultenv-2-menu/menu/boot-menu-add-entry b/defaultenv/defaultenv-2-menu/menu/boot-menu-add-entry
deleted file mode 100644
index f06c524..0000000
--- a/defaultenv/defaultenv-2-menu/menu/boot-menu-add-entry
+++ /dev/null
@@ -1,5 +0,0 @@
-#!/bin/sh
-
-menu -e -a -m boot -c "boot -v $1; echo; readline \"press enter to continue\" a " -d "Boot: ${GREEN}$2${NC}"
-menu -e -a -m boot_entries_edit -c "$global.editcmd /env/boot/$1" -d "${GREEN}$2${NC}"
-menu -e -a -m boot_entries_remove -c "rm /env/boot/$1" -d "${GREEN}$2${NC}"
diff --git a/defaultenv/defaultenv-2-menu/menu/boot-menu-new-boot-entry b/defaultenv/defaultenv-2-menu/menu/boot-menu-new-boot-entry
deleted file mode 100644
index c5e982c..0000000
--- a/defaultenv/defaultenv-2-menu/menu/boot-menu-new-boot-entry
+++ /dev/null
@@ -1,21 +0,0 @@
-#!/bin/sh
-
-name=
-
-readline "Name of the new entry: " name
-
-if [ -z "$name" ]; then
-	exit 1
-fi
-
-if [ -e "/env/boot/$name" ]; then
-	echo "entry $name already exists"
-	readline "<enter>" unused
-	exit 1
-fi
-
-cp /env/data/boot-template /env/boot/$name
-
-edit /env/boot/$name
-
-boot-menu-show rebuild
diff --git a/defaultenv/defaultenv-2-menu/menu/init-entries-collect b/defaultenv/defaultenv-2-menu/menu/init-entries-collect
deleted file mode 100644
index dbb7757..0000000
--- a/defaultenv/defaultenv-2-menu/menu/init-entries-collect
+++ /dev/null
@@ -1,9 +0,0 @@
-#!/bin/sh
-
-cd /env/init
-
-for i in *; do
-	./$i menu
-done
-
-cd /
diff --git a/defaultenv/defaultenv-2-menu/menu/init-entries-edit b/defaultenv/defaultenv-2-menu/menu/init-entries-edit
deleted file mode 100644
index fc02b32..0000000
--- a/defaultenv/defaultenv-2-menu/menu/init-entries-edit
+++ /dev/null
@@ -1,20 +0,0 @@
-#!/bin/sh
-
-export menu_exit=false
-
-while true; do
-	menu -a -m init_entries_edit -d "\e[1;36mEdit init entries\e[0m"
-
-	menu -e -a -m init_entries_edit -R -c "true" -d ">> Reset board to let changes here take effect <<"
-
-	init-entries-collect
-
-	menu -e -a -m init_entries_edit -c "menu_exit=true" -d "back"
-
-	menu -s -m init_entries_edit
-	menu -r -m init_entries_edit
-
-	if [ $menu_exit = true ]; then
-		exit
-	fi
-done
diff --git a/defaultenv/defaultenv-2-menu/menu/init-menu-add-entry b/defaultenv/defaultenv-2-menu/menu/init-menu-add-entry
deleted file mode 100644
index 7cb5686..0000000
--- a/defaultenv/defaultenv-2-menu/menu/init-menu-add-entry
+++ /dev/null
@@ -1,3 +0,0 @@
-#!/bin/sh
-
-menu -e -a -m init_entries_edit -c "$global.editcmd /env/init/$1" -d "\e[1;32m$2\e[0m"
diff --git a/defaultenv/defaultenv-2-menu/menu/mainmenu b/defaultenv/defaultenv-2-menu/menu/mainmenu
index f10f67a..9803947 100644
--- a/defaultenv/defaultenv-2-menu/menu/mainmenu
+++ b/defaultenv/defaultenv-2-menu/menu/mainmenu
@@ -1,23 +1,5 @@
 #!/bin/sh
 
-savepath=$PATH
-export menupath=$PATH:/env/menu
-
 . /env/data/ansi-colors
 
-while true; do
-	export PATH=${menupath}
-
-	echo $PATH
-
-	menu -a -m boot -d "${CYAN}Welcome to Barebox${NC}"
-
-	boot-entries-collect
-
-	menu -e -a -m boot -c "settings" -d "Settings"
-	menu -e -a -m boot -c 'PATH=$savepath; echo "enter exit to return to menu"; sh' -d "${DARK_YELLOW}Shell${NC}"
-	menu -e -a -m boot -c reset -d "${RED}Reset${NC}"
-
-	menu -s -m boot
-	menu -r -m boot
-done
+menutree
diff --git a/defaultenv/defaultenv-2-menu/menu/settings b/defaultenv/defaultenv-2-menu/menu/settings
deleted file mode 100644
index db619af..0000000
--- a/defaultenv/defaultenv-2-menu/menu/settings
+++ /dev/null
@@ -1,21 +0,0 @@
-#!/bin/sh
-
-export menu_exit=false
-
-while true; do
-	menu -a -m settings -d "${CYAN}Settings${NC}"
-
-	menu -e -a -R -m settings -c "$global.editcmd /env/network/eth0" -d "Network settings"
-	menu -e -a -R -m settings -c "$global.editcmd /env/config" -d "Config settings"
-	menu -e -a -m settings -c "boot-entries-edit" -d "Edit boot entries"
-	menu -e -a -m settings -c "init-entries-edit" -d "Edit init entries"
-	menu -e -a -R -m settings -c "saveenv || echo \"failed to save environment\" && sleep 2" -d "Save settings"
-	menu -e -a -m settings -c "menu_exit=true" -d "back"
-
-	menu -s -m settings
-	menu -r -m settings
-
-	if [ $menu_exit = true ]; then
-		exit
-	fi
-done
diff --git a/defaultenv/defaultenv-2-menu/menu/title b/defaultenv/defaultenv-2-menu/menu/title
new file mode 100644
index 0000000..f3c47b5
--- /dev/null
+++ b/defaultenv/defaultenv-2-menu/menu/title
@@ -0,0 +1 @@
+${RED}Main menu${NC}
-- 
1.9.0



From antonynpavlov at gmail.com  Fri Mar 28 05:28:11 2014
From: antonynpavlov at gmail.com (Antony Pavlov)
Date: Fri, 28 Mar 2014 13:28:11 +0400
Subject: [PATCH 0/9] MIPS: add Atheros AR933x SoC & TP-LINK MR3020 board
 support
In-Reply-To: <1395955604-12826-1-git-send-email-antonynpavlov@gmail.com>
References: <1395955604-12826-1-git-send-email-antonynpavlov@gmail.com>
Message-ID: <20140328132811.ee85068f4bd2ee0f623c6be2@gmail.com>

On Fri, 28 Mar 2014 01:26:35 +0400
Antony Pavlov <antonynpavlov at gmail.com> wrote:

Your latest clk-related changes break build of this patchseries.

I'll resend this series soon.

> Antony Pavlov (8):
>   MIPS: lib: add BAREBOX_CLK_TABLE to linker script
>   MIPS: ath79: add DEBUG_LL support for Atheros AR933x
>   serial: add Atheros AR933x driver
>   clk: add Atheros AR933x driver
>   MIPS: ath79: ar9331: add devicetree files
>   MIPS: ath79: add tplink-mr3020 board support
>   MIPS: tplink-mr3020: add documentation
>   MIPS: add tplink-mr3020_defconfig
> 
> Du Huanpeng (1):
>   MIPS: add Atheros ar933x family support
> 
>  Documentation/boards.dox                         |   1 +
>  arch/mips/Kconfig                                |  14 ++
>  arch/mips/Makefile                               |   3 +
>  arch/mips/boards/tplink-mr3020/Makefile          |   1 +
>  arch/mips/boards/tplink-mr3020/board.c           |  27 +++
>  arch/mips/boards/tplink-mr3020/tplink-mr3020.dox |  64 +++++++
>  arch/mips/configs/tplink-mr3020_defconfig        |  29 ++++
>  arch/mips/dts/ar9331.dtsi                        |  26 +++
>  arch/mips/dts/include/dt-bindings                |   1 +
>  arch/mips/dts/tplink-mr3020.dts                  |  18 ++
>  arch/mips/lib/barebox.lds.S                      |   2 +
>  arch/mips/mach-ath79/Kconfig                     |  15 ++
>  arch/mips/mach-ath79/Makefile                    |   1 +
>  arch/mips/mach-ath79/include/mach/ar71xx_regs.h  |  64 +++++++
>  arch/mips/mach-ath79/include/mach/ath79.h        |  33 ++++
>  arch/mips/mach-ath79/include/mach/debug_ll.h     |  56 +++++++
>  arch/mips/mach-ath79/reset.c                     |  32 ++++
>  drivers/clk/Makefile                             |   1 +
>  drivers/clk/clk-ar933x.c                         | 175 +++++++++++++++++++
>  drivers/serial/Kconfig                           |   7 +
>  drivers/serial/Makefile                          |   1 +
>  drivers/serial/serial_ar933x.c                   | 204 +++++++++++++++++++++++
>  drivers/serial/serial_ar933x.h                   |  69 ++++++++
>  include/dt-bindings/clock/ar933x-clk.h           |  22 +++
>  24 files changed, 866 insertions(+)
>  create mode 100644 arch/mips/boards/tplink-mr3020/Makefile
>  create mode 100644 arch/mips/boards/tplink-mr3020/board.c
>  create mode 100644 arch/mips/boards/tplink-mr3020/tplink-mr3020.dox
>  create mode 100644 arch/mips/configs/tplink-mr3020_defconfig
>  create mode 100644 arch/mips/dts/ar9331.dtsi
>  create mode 120000 arch/mips/dts/include/dt-bindings
>  create mode 100644 arch/mips/dts/tplink-mr3020.dts
>  create mode 100644 arch/mips/mach-ath79/Kconfig
>  create mode 100644 arch/mips/mach-ath79/Makefile
>  create mode 100644 arch/mips/mach-ath79/include/mach/ar71xx_regs.h
>  create mode 100644 arch/mips/mach-ath79/include/mach/ath79.h
>  create mode 100644 arch/mips/mach-ath79/include/mach/debug_ll.h
>  create mode 100644 arch/mips/mach-ath79/reset.c
>  create mode 100644 drivers/clk/clk-ar933x.c
>  create mode 100644 drivers/serial/serial_ar933x.c
>  create mode 100644 drivers/serial/serial_ar933x.h
>  create mode 100644 include/dt-bindings/clock/ar933x-clk.h
> 
> -- 
> 1.9.0
> 


-- 
--?
Best regards,
? Antony Pavlov


From antonynpavlov at gmail.com  Fri Mar 28 05:31:44 2014
From: antonynpavlov at gmail.com (Antony Pavlov)
Date: Fri, 28 Mar 2014 13:31:44 +0400
Subject: tegra: clk_fixed_factor
Message-ID: <20140328133144.83922cc5506a8d980d2cbd14@gmail.com>

Hi!

This latest commit in next breaks tegra build

  Author: Sascha Hauer <s.hauer at pengutronix.de>
  Date:   Thu Mar 13 09:41:28 2014 +0100

      clk: clk-fixed-factor: pass flags to initializers
     
      Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>

I can't check this trivial fix properly by myself as my tegra board is conserved:

--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -62,7 +62,7 @@ static void tegra20_osc_clk_init(void)
        clks[clk_32k] = clk_fixed("clk_32k", 32768);
 
        clks[pll_ref] = clk_fixed_factor("pll_ref", "clk_m", 1,
-                                        get_pll_ref_div());
+                                        get_pll_ref_div(), 0);
 }

--?
Best regards,
? Antony Pavlov


From voice.shen at atmel.com  Fri Mar 28 05:22:55 2014
From: voice.shen at atmel.com (Bo Shen)
Date: Fri, 28 Mar 2014 17:22:55 +0800
Subject: [PATCH] ARM: at91: add sama5d36 SoC support
Message-ID: <1395998575-25170-1-git-send-email-voice.shen@atmel.com>

SAMA5D36 SoC is a sub type of SAMA5D3 which has two Ethernets

Signed-off-by: Bo Shen <voice.shen at atmel.com>
---
 arch/arm/mach-at91/include/mach/cpu.h | 5 ++++-
 arch/arm/mach-at91/sama5d3.c          | 6 ++++--
 arch/arm/mach-at91/setup.c            | 3 +++
 3 files changed, 11 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-at91/include/mach/cpu.h b/arch/arm/mach-at91/include/mach/cpu.h
index 7132489..0e213ce 100644
--- a/arch/arm/mach-at91/include/mach/cpu.h
+++ b/arch/arm/mach-at91/include/mach/cpu.h
@@ -52,6 +52,7 @@
 #define ARCH_EXID_SAMA5D33	0x00414300
 #define ARCH_EXID_SAMA5D34	0x00414301
 #define ARCH_EXID_SAMA5D35	0x00584300
+#define ARCH_EXID_SAMA5D36	0x00004301
 
 #define ARCH_FAMILY_AT91X92	0x09200000
 #define ARCH_FAMILY_AT91SAM9	0x01900000
@@ -104,7 +105,7 @@ enum at91_soc_subtype {
 
 	/* SAMA5D3 */
 	AT91_SOC_SAMA5D31, AT91_SOC_SAMA5D33, AT91_SOC_SAMA5D34,
-	AT91_SOC_SAMA5D35,
+	AT91_SOC_SAMA5D35, AT91_SOC_SAMA5D36,
 
 	/* Unknown subtype */
 	AT91_SOC_SUBTYPE_NONE
@@ -206,12 +207,14 @@ static inline int at91_soc_is_detected(void)
 #define cpu_is_sama5d33()	(at91_soc_initdata.subtype == AT91_SOC_SAMA5D33)
 #define cpu_is_sama5d34()	(at91_soc_initdata.subtype == AT91_SOC_SAMA5D34)
 #define cpu_is_sama5d35()	(at91_soc_initdata.subtype == AT91_SOC_SAMA5D35)
+#define cpu_is_sama5d36()	(at91_soc_initdata.subtype == AT91_SOC_SAMA5D36)
 #else
 #define cpu_is_sama5d3()	(0)
 #define cpu_is_sama5d31()	(0)
 #define cpu_is_sama5d33()	(0)
 #define cpu_is_sama5d34()	(0)
 #define cpu_is_sama5d35()	(0)
+#define cpu_is_sama5d36()	(0)
 #endif
 
 /*
diff --git a/arch/arm/mach-at91/sama5d3.c b/arch/arm/mach-at91/sama5d3.c
index 1bfae14..85efb2d 100644
--- a/arch/arm/mach-at91/sama5d3.c
+++ b/arch/arm/mach-at91/sama5d3.c
@@ -348,11 +348,13 @@ static void __init sama5d3_register_clocks(void)
 
 	if ( cpu_is_sama5d33()
 	|| cpu_is_sama5d34()
-	|| cpu_is_sama5d35() )
+	|| cpu_is_sama5d35()
+	|| cpu_is_sama5d36())
 		clk_register(&macb0_clk);
 
 	if ( cpu_is_sama5d31()
-	|| cpu_is_sama5d35() )
+	|| cpu_is_sama5d35()
+	|| cpu_is_sama5d36())
 		clk_register(&macb1_clk);
 
 	if (!cpu_is_sama5d35())
diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
index 65d0588..7a7de98 100644
--- a/arch/arm/mach-at91/setup.c
+++ b/arch/arm/mach-at91/setup.c
@@ -162,6 +162,8 @@ static void __init soc_detect(u32 dbgu_base)
 			break;
 		case ARCH_EXID_SAMA5D35:
 			at91_soc_initdata.subtype = AT91_SOC_SAMA5D35;
+		case ARCH_EXID_SAMA5D36:
+			at91_soc_initdata.subtype = AT91_SOC_SAMA5D36;
 			break;
 		}
 	}
@@ -205,6 +207,7 @@ static const char *soc_subtype_name[] = {
 	[AT91_SOC_SAMA5D33]	= "sama5d33",
 	[AT91_SOC_SAMA5D34]	= "sama5d34",
 	[AT91_SOC_SAMA5D35]	= "sama5d35",
+	[AT91_SOC_SAMA5D36]	= "sama5d36",
 	[AT91_SOC_SUBTYPE_NONE]	= "Unknown"
 };
 
-- 
1.8.5.2



From s.hauer at pengutronix.de  Fri Mar 28 05:38:44 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 28 Mar 2014 10:38:44 +0100
Subject: [PATCH 0/9] MIPS: add Atheros AR933x SoC & TP-LINK MR3020 board
 support
In-Reply-To: <20140328132811.ee85068f4bd2ee0f623c6be2@gmail.com>
References: <1395955604-12826-1-git-send-email-antonynpavlov@gmail.com>
 <20140328132811.ee85068f4bd2ee0f623c6be2@gmail.com>
Message-ID: <20140328093844.GF17250@pengutronix.de>

On Fri, Mar 28, 2014 at 01:28:11PM +0400, Antony Pavlov wrote:
> On Fri, 28 Mar 2014 01:26:35 +0400
> Antony Pavlov <antonynpavlov at gmail.com> wrote:
> 
> Your latest clk-related changes break build of this patchseries.
> 
> I'll resend this series soon.

I can fold in a fixup into the merge commit which brings together my clk
changes and your mips tree for you, don't worry. I assume you want to have
the CLK_SET_RATE_PARENT flag passed into clk_fixed_factor, right?

I get this when compiling:

drivers/clk/clk-ar933x.c: In function 'ar933x_ref_clk_init':
drivers/clk/clk-ar933x.c:108: warning: unused variable 'err'
drivers/clk/clk-ar933x.c:107: warning: unused variable 'clk'

I have a fix for this locally now. I'll have a look over the patches.
Should they be fine there's nothing to do for you (except checking the
result when I merged it)

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From s.hauer at pengutronix.de  Fri Mar 28 05:44:00 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 28 Mar 2014 10:44:00 +0100
Subject: [PATCH 7/9] MIPS: ath79: add tplink-mr3020 board support
In-Reply-To: <1395955604-12826-8-git-send-email-antonynpavlov@gmail.com>
References: <1395955604-12826-1-git-send-email-antonynpavlov@gmail.com>
 <1395955604-12826-8-git-send-email-antonynpavlov@gmail.com>
Message-ID: <20140328094400.GG17250@pengutronix.de>

On Fri, Mar 28, 2014 at 01:26:42AM +0400, Antony Pavlov wrote:
> This board support code can be used for TP-LINK WR703 too.
> 
> TP-LINK WR703 is very similar to TP-LINK MR3020, there are
> some non-essential differences:
> 
>   * WR703 is smaller and cheaper;
>   * WR703 has only one led, but MR3020 has five leds;
>   * MR3020 uses mini-USB connector, WR703 uses micro-USB connector.
> 
> See https://forum.openwrt.org/viewtopic.php?id=45159 for details.
> 
> Signed-off-by: Antony Pavlov <antonynpavlov at gmail.com>
> ---
>  arch/mips/Makefile                      |  1 +
>  arch/mips/boards/tplink-mr3020/Makefile |  1 +
>  arch/mips/boards/tplink-mr3020/board.c  | 27 +++++++++++++++++++++++++++
>  arch/mips/dts/tplink-mr3020.dts         | 18 ++++++++++++++++++
>  arch/mips/mach-ath79/Kconfig            |  8 ++++++++
>  5 files changed, 55 insertions(+)
> 
> diff --git a/arch/mips/Makefile b/arch/mips/Makefile
> index 5ca5fc9..b3bacf3 100644
> --- a/arch/mips/Makefile
> +++ b/arch/mips/Makefile
> @@ -79,6 +79,7 @@ machine-$(CONFIG_MACH_MIPS_AR231X)	:= ar231x
>  board-$(CONFIG_BOARD_NETGEAR_WG102)	:= netgear-wg102
>  
>  machine-$(CONFIG_MACH_MIPS_ATH79)	:= ath79
> +board-$(CONFIG_BOARD_TPLINK_MR3020)	:= tplink-mr3020
>  
>  machine-$(CONFIG_MACH_MIPS_BCM47XX)	:= bcm47xx
>  board-$(CONFIG_BOARD_DLINK_DIR320)	:= dlink-dir-320
> diff --git a/arch/mips/boards/tplink-mr3020/Makefile b/arch/mips/boards/tplink-mr3020/Makefile
> new file mode 100644
> index 0000000..dcfc293
> --- /dev/null
> +++ b/arch/mips/boards/tplink-mr3020/Makefile
> @@ -0,0 +1 @@
> +obj-y += board.o
> diff --git a/arch/mips/boards/tplink-mr3020/board.c b/arch/mips/boards/tplink-mr3020/board.c
> new file mode 100644
> index 0000000..318998c
> --- /dev/null
> +++ b/arch/mips/boards/tplink-mr3020/board.c
> @@ -0,0 +1,27 @@
> +/*
> + * Copyright (C) 2014 Antony Pavlov <antonynpavlov at gmail.com>
> + *
> + * This file is part of barebox.
> + * See file CREDITS for list of people who contributed to this project.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2
> + * as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + */
> +
> +#include <common.h>
> +#include <init.h>
> +
> +static int model_hostname_init(void)
> +{
> +	barebox_set_hostname("mr3020");
> +
> +	return 0;
> +}
> +postcore_initcall(model_hostname_init);
> diff --git a/arch/mips/dts/tplink-mr3020.dts b/arch/mips/dts/tplink-mr3020.dts
> new file mode 100644
> index 0000000..b9539c5
> --- /dev/null
> +++ b/arch/mips/dts/tplink-mr3020.dts
> @@ -0,0 +1,18 @@
> +/dts-v1/;
> +
> +#include <ar9331.dtsi>
> +
> +/ {
> +	model = "TP-LINK MR3020";
> +	compatible = "tplink,mr3020";
> +
> +	memory {
> +		reg = <0x00000000 0x2000000>;
> +	};
> +
> +	soc {
> +		serial0: serial at b8020000 {
> +			status = "okay";
> +		};
> +	};

This can be easier written as:

&serial0 {
	status = "okay";
};

With bigger board dts files this is much nicer since you don't have to
resemble the tree structure in your board dts.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From s.hauer at pengutronix.de  Fri Mar 28 05:53:49 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 28 Mar 2014 10:53:49 +0100
Subject: tegra: clk_fixed_factor
In-Reply-To: <20140328133144.83922cc5506a8d980d2cbd14@gmail.com>
References: <20140328133144.83922cc5506a8d980d2cbd14@gmail.com>
Message-ID: <20140328095349.GH17250@pengutronix.de>

On Fri, Mar 28, 2014 at 01:31:44PM +0400, Antony Pavlov wrote:
> Hi!
> 
> This latest commit in next breaks tegra build
> 
>   Author: Sascha Hauer <s.hauer at pengutronix.de>
>   Date:   Thu Mar 13 09:41:28 2014 +0100
> 
>       clk: clk-fixed-factor: pass flags to initializers
>      
>       Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
> 
> I can't check this trivial fix properly by myself as my tegra board is conserved:

Thanks for noting. I have just squashed it into the commit breaking it
(Not puseh yet)

Sascha

> 
> --- a/drivers/clk/tegra/clk-tegra20.c
> +++ b/drivers/clk/tegra/clk-tegra20.c
> @@ -62,7 +62,7 @@ static void tegra20_osc_clk_init(void)
>         clks[clk_32k] = clk_fixed("clk_32k", 32768);
>  
>         clks[pll_ref] = clk_fixed_factor("pll_ref", "clk_m", 1,
> -                                        get_pll_ref_div());
> +                                        get_pll_ref_div(), 0);
>  }
> 
> --?
> Best regards,
> ? Antony Pavlov
> 

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From antonynpavlov at gmail.com  Fri Mar 28 06:39:38 2014
From: antonynpavlov at gmail.com (Antony Pavlov)
Date: Fri, 28 Mar 2014 14:39:38 +0400
Subject: [PATCH 0/9] MIPS: add Atheros AR933x SoC & TP-LINK MR3020 board
 support
In-Reply-To: <20140328093844.GF17250@pengutronix.de>
References: <1395955604-12826-1-git-send-email-antonynpavlov@gmail.com>
 <20140328132811.ee85068f4bd2ee0f623c6be2@gmail.com>
 <20140328093844.GF17250@pengutronix.de>
Message-ID: <20140328143938.ad5b84aba01edb62beb60181@gmail.com>

On Fri, 28 Mar 2014 10:38:44 +0100
Sascha Hauer <s.hauer at pengutronix.de> wrote:

> On Fri, Mar 28, 2014 at 01:28:11PM +0400, Antony Pavlov wrote:
> > On Fri, 28 Mar 2014 01:26:35 +0400
> > Antony Pavlov <antonynpavlov at gmail.com> wrote:
> > 
> > Your latest clk-related changes break build of this patchseries.
> > 
> > I'll resend this series soon.
> 
> I can fold in a fixup into the merge commit which brings together my clk
> changes and your mips tree for you, don't worry. I assume you want to have
> the CLK_SET_RATE_PARENT flag passed into clk_fixed_factor, right?
> 
> I get this when compiling:
> 
> drivers/clk/clk-ar933x.c: In function 'ar933x_ref_clk_init':
> drivers/clk/clk-ar933x.c:108: warning: unused variable 'err'
> drivers/clk/clk-ar933x.c:107: warning: unused variable 'clk'

Agghhh.

I had used very old mips-linux-gcc 3.4.6 compiler most of time --- it does not show the warnings.

I have just checked with codesourcery mips-2013.11 --- it gives me the warnings.

> I have a fix for this locally now. I'll have a look over the patches.
> Should they be fine there's nothing to do for you (except checking the
> result when I merged it)

I have just checked next branch on my MR3020 board --- all works fine!

Thanks a lot for all!

--?
Best regards,
? Antony Pavlov


From antonynpavlov at gmail.com  Fri Mar 28 12:28:34 2014
From: antonynpavlov at gmail.com (Antony Pavlov)
Date: Fri, 28 Mar 2014 20:28:34 +0400
Subject: [PATCH] MIPS: rzx50: use short form for serial1 reference
Message-ID: <1396024114-15610-1-git-send-email-antonynpavlov@gmail.com>

Signed-off-by: Antony Pavlov <antonynpavlov at gmail.com>
---
 arch/mips/dts/rzx50.dts | 8 +++-----
 1 file changed, 3 insertions(+), 5 deletions(-)

diff --git a/arch/mips/dts/rzx50.dts b/arch/mips/dts/rzx50.dts
index 78103e3..360c1bf 100644
--- a/arch/mips/dts/rzx50.dts
+++ b/arch/mips/dts/rzx50.dts
@@ -9,10 +9,8 @@
 	memory {
 		reg = <0x00000000 0x4000000>;
 	};
+};
 
-	soc {
-		serial1: serial at b0031000 {
-			status = "okay";
-		};
-	};
+&serial1 {
+	status = "okay";
 };
-- 
1.9.0



From alex.aring at gmail.com  Sun Mar 30 20:12:11 2014
From: alex.aring at gmail.com (Alexander Aring)
Date: Mon, 31 Mar 2014 02:12:11 +0200
Subject: Can i access the barebox env from linux
In-Reply-To: <20140328095241.GB21559@omega.Speedport_W_921V_1_24_000>
References: <CA+dawz0DeA4+LWqamXp-tPDyWXW1JXfov-u2xdPBrSEsdFuZ3Q@mail.gmail.com>
 <20140326062619.GP17250@pengutronix.de>
 <20140326065734.GA18805@omega.Speedport_W_921V_1_24_000>
 <CA+dawz1a0EVA5OvDGZjpchV13R8J5+hKS8hVOtmmi2HFef5spQ@mail.gmail.com>
 <20140326113103.GA9427@omega.Speedport_W_921V_1_24_000>
 <20140326113300.GB9427@omega.Speedport_W_921V_1_24_000>
 <CA+dawz2HSTYcR4Lv_0Q_ECELh2i9kq6vnZTEdnD8e+qu4pyamA@mail.gmail.com>
 <20140328091854.GA20774@omega.Speedport_W_921V_1_24_000>
 <CA+dawz3gfhFv3mtAOjXVoooE5WqJb6sH1qbMmPw--OD-p_N4Qg@mail.gmail.com>
 <20140328095241.GB21559@omega.Speedport_W_921V_1_24_000>
Message-ID: <20140331001145.GB28141@omega.Speedport_W_921V_1_24_000>

Hi,

On Fri, Mar 28, 2014 at 10:52:41AM +0100, Alexander Aring wrote:
> On Fri, Mar 28, 2014 at 03:04:40PM +0530, Ashutosh Singh wrote:
> > ya i tried with that too please have a look over barebox log after reboot:
> > 
> > nand: ONFI param page 0 valid
> > nand: ONFI flash detected ...
> > nand: Manufacturer ID: 0x2c, Chip ID: 0xdc (Micron MT29F4G08ABADAH4),
> > page size: 2048, OOB size: 64
> > malloc space: 0x83ff4000 -> 0x87ff3fff (size 64 MiB)
> > err -74
> well, 74 is EBADMSG.
> 
> I run a 'grep -nr "EBADMSG" .' into the current barebox directory and it
> seems that the uncompress env functions doesn't return this errno. So
> maybe your enviroment is correct (I can't check it I need a hexdump for
> this).
> 
> 
> What I can see is:
> ./drivers/mtd/nand/nand_base.c:1464:		return -EBADMSG;
> ./drivers/mtd/nand/nand_base.c:1739:		return -EBADMSG;
> ./drivers/mtd/nand/nand_ecc.c:192:	return -EBADMSG;
> 
> 
> and especially "./drivers/mtd/nand/nand_ecc.c", try to enable more debug
> functionality in barebox "make menuconfig" there exist some option to
> enable set some debug level in "Debugging  --->".
> 
> Or maybe try to instrument the code there to see if it's really some ecc
> failure.
> 

today I tested it with nandsim but I can't use a real barebox to read
the environment.

I used nandwrite and nanddump afterwards. Maybe you can run a easy test,
too. Read the image back after you ran nandwrite and extract the image
wit bareboxenv. Then we know the env is successful written and there
exists some other problem between linux<->barebox.

... and please keep the mailinglist in cc.

- Alex



From s.hauer at pengutronix.de  Mon Mar 31 02:32:29 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Mon, 31 Mar 2014 08:32:29 +0200
Subject: [PATCH] MIPS: rzx50: use short form for serial1 reference
In-Reply-To: <1396024114-15610-1-git-send-email-antonynpavlov@gmail.com>
References: <1396024114-15610-1-git-send-email-antonynpavlov@gmail.com>
Message-ID: <20140331063229.GL17250@pengutronix.de>

On Fri, Mar 28, 2014 at 08:28:34PM +0400, Antony Pavlov wrote:
> Signed-off-by: Antony Pavlov <antonynpavlov at gmail.com>

Applied, thanks

Sascha

> ---
>  arch/mips/dts/rzx50.dts | 8 +++-----
>  1 file changed, 3 insertions(+), 5 deletions(-)
> 
> diff --git a/arch/mips/dts/rzx50.dts b/arch/mips/dts/rzx50.dts
> index 78103e3..360c1bf 100644
> --- a/arch/mips/dts/rzx50.dts
> +++ b/arch/mips/dts/rzx50.dts
> @@ -9,10 +9,8 @@
>  	memory {
>  		reg = <0x00000000 0x4000000>;
>  	};
> +};
>  
> -	soc {
> -		serial1: serial at b0031000 {
> -			status = "okay";
> -		};
> -	};
> +&serial1 {
> +	status = "okay";
>  };
> -- 
> 1.9.0
> 
> 
> _______________________________________________
> barebox mailing list
> barebox at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/barebox
> 

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From s.hauer at pengutronix.de  Mon Mar 31 02:33:24 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Mon, 31 Mar 2014 08:33:24 +0200
Subject: [PATCH] ARM: at91: add sama5d36 SoC support
In-Reply-To: <1395998575-25170-1-git-send-email-voice.shen@atmel.com>
References: <1395998575-25170-1-git-send-email-voice.shen@atmel.com>
Message-ID: <20140331063324.GM17250@pengutronix.de>

On Fri, Mar 28, 2014 at 05:22:55PM +0800, Bo Shen wrote:
> SAMA5D36 SoC is a sub type of SAMA5D3 which has two Ethernets
> 
> Signed-off-by: Bo Shen <voice.shen at atmel.com>

Applied, thanks

Sascha

> ---
>  arch/arm/mach-at91/include/mach/cpu.h | 5 ++++-
>  arch/arm/mach-at91/sama5d3.c          | 6 ++++--
>  arch/arm/mach-at91/setup.c            | 3 +++
>  3 files changed, 11 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/arm/mach-at91/include/mach/cpu.h b/arch/arm/mach-at91/include/mach/cpu.h
> index 7132489..0e213ce 100644
> --- a/arch/arm/mach-at91/include/mach/cpu.h
> +++ b/arch/arm/mach-at91/include/mach/cpu.h
> @@ -52,6 +52,7 @@
>  #define ARCH_EXID_SAMA5D33	0x00414300
>  #define ARCH_EXID_SAMA5D34	0x00414301
>  #define ARCH_EXID_SAMA5D35	0x00584300
> +#define ARCH_EXID_SAMA5D36	0x00004301
>  
>  #define ARCH_FAMILY_AT91X92	0x09200000
>  #define ARCH_FAMILY_AT91SAM9	0x01900000
> @@ -104,7 +105,7 @@ enum at91_soc_subtype {
>  
>  	/* SAMA5D3 */
>  	AT91_SOC_SAMA5D31, AT91_SOC_SAMA5D33, AT91_SOC_SAMA5D34,
> -	AT91_SOC_SAMA5D35,
> +	AT91_SOC_SAMA5D35, AT91_SOC_SAMA5D36,
>  
>  	/* Unknown subtype */
>  	AT91_SOC_SUBTYPE_NONE
> @@ -206,12 +207,14 @@ static inline int at91_soc_is_detected(void)
>  #define cpu_is_sama5d33()	(at91_soc_initdata.subtype == AT91_SOC_SAMA5D33)
>  #define cpu_is_sama5d34()	(at91_soc_initdata.subtype == AT91_SOC_SAMA5D34)
>  #define cpu_is_sama5d35()	(at91_soc_initdata.subtype == AT91_SOC_SAMA5D35)
> +#define cpu_is_sama5d36()	(at91_soc_initdata.subtype == AT91_SOC_SAMA5D36)
>  #else
>  #define cpu_is_sama5d3()	(0)
>  #define cpu_is_sama5d31()	(0)
>  #define cpu_is_sama5d33()	(0)
>  #define cpu_is_sama5d34()	(0)
>  #define cpu_is_sama5d35()	(0)
> +#define cpu_is_sama5d36()	(0)
>  #endif
>  
>  /*
> diff --git a/arch/arm/mach-at91/sama5d3.c b/arch/arm/mach-at91/sama5d3.c
> index 1bfae14..85efb2d 100644
> --- a/arch/arm/mach-at91/sama5d3.c
> +++ b/arch/arm/mach-at91/sama5d3.c
> @@ -348,11 +348,13 @@ static void __init sama5d3_register_clocks(void)
>  
>  	if ( cpu_is_sama5d33()
>  	|| cpu_is_sama5d34()
> -	|| cpu_is_sama5d35() )
> +	|| cpu_is_sama5d35()
> +	|| cpu_is_sama5d36())
>  		clk_register(&macb0_clk);
>  
>  	if ( cpu_is_sama5d31()
> -	|| cpu_is_sama5d35() )
> +	|| cpu_is_sama5d35()
> +	|| cpu_is_sama5d36())
>  		clk_register(&macb1_clk);
>  
>  	if (!cpu_is_sama5d35())
> diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
> index 65d0588..7a7de98 100644
> --- a/arch/arm/mach-at91/setup.c
> +++ b/arch/arm/mach-at91/setup.c
> @@ -162,6 +162,8 @@ static void __init soc_detect(u32 dbgu_base)
>  			break;
>  		case ARCH_EXID_SAMA5D35:
>  			at91_soc_initdata.subtype = AT91_SOC_SAMA5D35;
> +		case ARCH_EXID_SAMA5D36:
> +			at91_soc_initdata.subtype = AT91_SOC_SAMA5D36;
>  			break;
>  		}
>  	}
> @@ -205,6 +207,7 @@ static const char *soc_subtype_name[] = {
>  	[AT91_SOC_SAMA5D33]	= "sama5d33",
>  	[AT91_SOC_SAMA5D34]	= "sama5d34",
>  	[AT91_SOC_SAMA5D35]	= "sama5d35",
> +	[AT91_SOC_SAMA5D36]	= "sama5d36",
>  	[AT91_SOC_SUBTYPE_NONE]	= "Unknown"
>  };
>  
> -- 
> 1.8.5.2
> 
> 

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From s.hauer at pengutronix.de  Mon Mar 31 03:17:54 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Mon, 31 Mar 2014 09:17:54 +0200
Subject: [PATCH] of: Add support for "stdout-path" property
Message-ID: <1396250274-17827-1-git-send-email-s.hauer@pengutronix.de>

ePAPR 1.1 specifies the "stdout-path" property, but barebox currently
only handles the "linux,stdout-path" property. Add parsing for the new
property name.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 drivers/of/base.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/of/base.c b/drivers/of/base.c
index 104b6da..c440a69 100644
--- a/drivers/of/base.c
+++ b/drivers/of/base.c
@@ -1841,8 +1841,11 @@ int of_device_is_stdout_path(struct device_d *dev)
 	struct device_node *dn;
 	const char *name;
 
-	name = of_get_property(of_chosen, "linux,stdout-path", NULL);
-	if (name == NULL)
+	name = of_get_property(of_chosen, "stdout-path", NULL);
+	if (!name)
+		name = of_get_property(of_chosen, "linux,stdout-path", NULL);
+
+	if (!name)
 		return 0;
 
 	dn = of_find_node_by_path(name);
-- 
1.9.1



From s.hauer at pengutronix.de  Mon Mar 31 03:21:26 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Mon, 31 Mar 2014 09:21:26 +0200
Subject: [PATCH] netconsole: bail out when no connection is opened
Message-ID: <1396250486-7655-1-git-send-email-s.hauer@pengutronix.de>

When no connection is opened we should not call into
the networking stack. Otherwise it can happen that we
delay further execution until the network stack detected
a link (or timed out bringing the link up).

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 net/netconsole.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/net/netconsole.c b/net/netconsole.c
index 2ab19de..86a68e1 100644
--- a/net/netconsole.c
+++ b/net/netconsole.c
@@ -81,6 +81,9 @@ static int nc_getc(struct console_device *cdev)
 					struct nc_priv, cdev);
 	unsigned char c;
 
+	if (!priv->con)
+		return 0;
+
 	while (!kfifo_len(priv->fifo))
 		net_poll();
 
@@ -94,6 +97,9 @@ static int nc_tstc(struct console_device *cdev)
 	struct nc_priv *priv = container_of(cdev,
 					struct nc_priv, cdev);
 
+	if (!priv->con)
+		return 0;
+
 	if (priv->busy)
 		return kfifo_len(priv->fifo) ? 1 : 0;
 
-- 
1.9.1



From s.trumtrar at pengutronix.de  Mon Mar 31 04:18:50 2014
From: s.trumtrar at pengutronix.de (Steffen Trumtrar)
Date: Mon, 31 Mar 2014 10:18:50 +0200
Subject: [PATCH 1/2] ARM: socfpga: move iocsr from mach to sockit board folder
Message-ID: <1396253931-3669-1-git-send-email-s.trumtrar@pengutronix.de>

The current iocsr-config-cyclone5.c is actually board specific, although the
file name suggests otherwise.
As the file was generated for the SoCkit, move it there.

Signed-off-by: Steffen Trumtrar <s.trumtrar at pengutronix.de>
---
 arch/arm/boards/terasic-sockit/Makefile                                 | 1 +
 .../arm/{mach-socfpga => boards/terasic-sockit}/iocsr-config-cyclone5.c | 0
 arch/arm/mach-socfpga/Makefile                                          | 2 +-
 3 files changed, 2 insertions(+), 1 deletion(-)
 rename arch/arm/{mach-socfpga => boards/terasic-sockit}/iocsr-config-cyclone5.c (100%)

diff --git a/arch/arm/boards/terasic-sockit/Makefile b/arch/arm/boards/terasic-sockit/Makefile
index 8c927fe..b94f918 100644
--- a/arch/arm/boards/terasic-sockit/Makefile
+++ b/arch/arm/boards/terasic-sockit/Makefile
@@ -1,2 +1,3 @@
 obj-y += lowlevel.o board.o
+pbl-y += iocsr-config-cyclone5.o
 pbl-y += lowlevel.o
diff --git a/arch/arm/mach-socfpga/iocsr-config-cyclone5.c b/arch/arm/boards/terasic-sockit/iocsr-config-cyclone5.c
similarity index 100%
rename from arch/arm/mach-socfpga/iocsr-config-cyclone5.c
rename to arch/arm/boards/terasic-sockit/iocsr-config-cyclone5.c
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index d8bf067..dea0e07 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -1,4 +1,4 @@
 obj-y += generic.o nic301.o bootsource.o reset-manager.o
 pbl-y += init.o freeze-controller.o scan-manager.o system-manager.o
-pbl-y += clock-manager.o iocsr-config-cyclone5.o
+pbl-y += clock-manager.o
 obj-$(CONFIG_ARCH_SOCFPGA_XLOAD) += xload.o
-- 
1.9.1



From s.trumtrar at pengutronix.de  Mon Mar 31 04:18:51 2014
From: s.trumtrar at pengutronix.de (Steffen Trumtrar)
Date: Mon, 31 Mar 2014 10:18:51 +0200
Subject: [PATCH 2/2] ARM: socfpga: socrates: add iocsr config
In-Reply-To: <1396253931-3669-1-git-send-email-s.trumtrar@pengutronix.de>
References: <1396253931-3669-1-git-send-email-s.trumtrar@pengutronix.de>
Message-ID: <1396253931-3669-2-git-send-email-s.trumtrar@pengutronix.de>

Signed-off-by: Steffen Trumtrar <s.trumtrar at pengutronix.de>
---
 .../boards/ebv-socrates/iocsr_config_cyclone5.c    | 649 +++++++++++++++++++++
 1 file changed, 649 insertions(+)
 create mode 100644 arch/arm/boards/ebv-socrates/iocsr_config_cyclone5.c

diff --git a/arch/arm/boards/ebv-socrates/iocsr_config_cyclone5.c b/arch/arm/boards/ebv-socrates/iocsr_config_cyclone5.c
new file mode 100644
index 0000000..1761f4f
--- /dev/null
+++ b/arch/arm/boards/ebv-socrates/iocsr_config_cyclone5.c
@@ -0,0 +1,649 @@
+/* This file is generated by Preloader Generator */
+
+#include <common.h>
+#include <mach/scan-manager.h>
+
+const unsigned long iocsr_scan_chain0_table[((CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH / 32) + 1)] = {
+	0x00000000,
+	0x00000000,
+	0x0FF00000,
+	0xC0000000,
+	0x0000003F,
+	0x00008000,
+	0x00060180,
+	0x18060000,
+	0x18000000,
+	0x00018060,
+	0x00000000,
+	0x00004000,
+	0x000300C0,
+	0x0C030000,
+	0x0C000000,
+	0x00000030,
+	0x0000C030,
+	0x00002000,
+	0x00018060,
+	0x06018000,
+	0x06000000,
+	0x00000018,
+	0x00006018,
+	0x00001000,
+};
+
+const unsigned long iocsr_scan_chain1_table[((CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH / 32) + 1)] = {
+	0x000C0300,
+	0x300C0000,
+	0x300000C0,
+	0x000000C0,
+	0x000300C0,
+	0x00008000,
+	0x00060180,
+	0x18060000,
+	0x18000000,
+	0x00000060,
+	0x00018060,
+	0x00004000,
+	0x000300C0,
+	0x0C030000,
+	0x0C000000,
+	0x00000030,
+	0x0000C030,
+	0x00002000,
+	0x06018060,
+	0x06018000,
+	0x01FE0000,
+	0xF8000000,
+	0x00000007,
+	0x00001000,
+	0x0000C030,
+	0x0300C000,
+	0x03000000,
+	0x0000300C,
+	0x0000300C,
+	0x00000800,
+	0x00000000,
+	0x00000000,
+	0x01800000,
+	0x00000006,
+	0x00001806,
+	0x00000400,
+	0x00000000,
+	0x00C03000,
+	0x00000003,
+	0x00000000,
+	0x00000000,
+	0x00000200,
+	0x00601806,
+	0x00000000,
+	0x80600000,
+	0x80000601,
+	0x00000601,
+	0x00000100,
+	0x00300C03,
+	0xC0300C00,
+	0xC0300000,
+	0xC0000300,
+	0x000C0300,
+	0x00000080,
+};
+
+const unsigned long iocsr_scan_chain2_table[((CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH / 32) + 1)] = {
+	0x300C0300,
+	0x00000000,
+	0x0FF00000,
+	0x00000000,
+	0x0C0300C0,
+	0x00008000,
+	0x18060180,
+	0x18060000,
+	0x18000100,
+	0x00018060,
+	0x00018060,
+	0x00004000,
+	0x200700C0,
+	0x0C030000,
+	0x00000030,
+	0x00000000,
+	0x0300C030,
+	0x00002000,
+	0x10018060,
+	0x06018000,
+	0x06000000,
+	0x00010038,
+	0x00006018,
+	0x00001000,
+	0x0000C030,
+	0x00000000,
+	0x03000000,
+	0x0000800C,
+	0x00C0300C,
+	0x00000800,
+};
+
+const unsigned long iocsr_scan_chain3_table[((CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH / 32) + 1)] = {
+	0x0CC20D80,
+	0x8C3000FF,
+	0x0A804001,
+	0x07900000,
+	0x08020000,
+	0x00100000,
+	0x0A800000,
+	0x07900000,
+	0x08020000,
+	0x00100000,
+	0x20430000,
+	0x0C003001,
+	0x00C00481,
+	0x00000000,
+	0x00000021,
+	0x82000004,
+	0x05400000,
+	0x03C80000,
+	0x04010000,
+	0x00080000,
+	0x05400000,
+	0x03C80000,
+	0x05400000,
+	0x03C80000,
+	0x90218000,
+	0x86001800,
+	0x00600240,
+	0x80090218,
+	0x00000001,
+	0x40000002,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x4810C000,
+	0x43000C00,
+	0x00300120,
+	0xC004810C,
+	0x12043000,
+	0x20000300,
+	0x00040000,
+	0x50670000,
+	0x00000010,
+	0x24590000,
+	0x00001000,
+	0xA0000034,
+	0x0D000001,
+	0xA0680514,
+	0xCF034069,
+	0x1E781A03,
+	0x805140D0,
+	0x34069A06,
+	0x01A03CF0,
+	0x340D0000,
+	0x1860680D,
+	0x03CF0340,
+	0xD000001A,
+	0x0680D340,
+	0x10040000,
+	0x00200000,
+	0x10040000,
+	0x00200000,
+	0x15000000,
+	0x0F200000,
+	0x15000000,
+	0x0F200000,
+	0x01FE0000,
+	0x18000000,
+	0x01800902,
+	0x00240860,
+	0x007F8006,
+	0x00000000,
+	0x0A800001,
+	0x07900000,
+	0x0A800000,
+	0x07900000,
+	0x0A800000,
+	0x07900000,
+	0x08020000,
+	0x00100000,
+	0x20430000,
+	0x0C003001,
+	0x00C00481,
+	0x00000FF0,
+	0x4810C000,
+	0x80000C00,
+	0x05400000,
+	0x02480000,
+	0x04000000,
+	0x00080000,
+	0x05400000,
+	0x03C80000,
+	0x05400000,
+	0x03C80000,
+	0x90218000,
+	0x86001800,
+	0x00600240,
+	0x80090218,
+	0x24086001,
+	0x40000600,
+	0x02A00040,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x4810C000,
+	0x43000C00,
+	0x00300120,
+	0xC004810C,
+	0x12043000,
+	0x20000300,
+	0x00040000,
+	0x50670000,
+	0x00000010,
+	0x24590000,
+	0x00001000,
+	0xA0000034,
+	0x0D000001,
+	0x60680D34,
+	0xCF034018,
+	0x0E381A03,
+	0x80D340D0,
+	0x34018606,
+	0x01A00040,
+	0x340D0002,
+	0x1860680D,
+	0x03CF0340,
+	0xD01E781A,
+	0x06805140,
+	0x10040000,
+	0x00200000,
+	0x10040000,
+	0x00200000,
+	0x15000000,
+	0x0F200000,
+	0x15000000,
+	0x0F200000,
+	0x01FE0000,
+	0x18000000,
+	0x01800902,
+	0x00240860,
+	0x007F8006,
+	0x00000000,
+	0x99300001,
+	0x34343400,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0x00040100,
+	0x00000800,
+	0x00000000,
+	0x00001208,
+	0x00482000,
+	0x01000000,
+	0x00000000,
+	0x00410482,
+	0x0006A000,
+	0x0001B400,
+	0x00020000,
+	0x00000400,
+	0x0002A000,
+	0x0001E400,
+	0x5506A000,
+	0x00E1D400,
+	0x00000000,
+	0x2043090C,
+	0x00003001,
+	0x90400000,
+	0x00000000,
+	0x2020C243,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x00010040,
+	0x00000200,
+	0x00000000,
+	0x00000482,
+	0x00120800,
+	0x00002000,
+	0x80000000,
+	0x00104120,
+	0x00000200,
+	0xAC0D5F80,
+	0xFFFFFFFF,
+	0x14F3690D,
+	0x1A041414,
+	0x00D00000,
+	0x18864000,
+	0x49247A06,
+	0xF228A3D5,
+	0xF6D1451E,
+	0x0342E388,
+	0x821A0000,
+	0x0000D000,
+	0x028A0680,
+	0xD949247A,
+	0x1EF228A3,
+	0x88F6D145,
+	0x000352E3,
+	0x00080200,
+	0x00001000,
+	0x00080200,
+	0x00001000,
+	0x000A8000,
+	0x00075000,
+	0x541A8000,
+	0x03875001,
+	0x10000000,
+	0x00000000,
+	0x0080C000,
+	0x41000000,
+	0x00003FC2,
+	0x00820000,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0x00040100,
+	0x00000800,
+	0x00000000,
+	0x00001208,
+	0x00482000,
+	0x00008000,
+	0x00000000,
+	0x00410482,
+	0x0006A000,
+	0x0001B400,
+	0x00020000,
+	0x00000400,
+	0x00020080,
+	0x00000400,
+	0x5506A000,
+	0x00E1D400,
+	0x00000000,
+	0x0000090C,
+	0x00000010,
+	0x90400000,
+	0x00000000,
+	0x2020C243,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x00015000,
+	0x0000F200,
+	0x00000000,
+	0x00000482,
+	0x86120800,
+	0x00600240,
+	0x80000000,
+	0x00104120,
+	0x00000200,
+	0xAC0D5F80,
+	0xFFFFFFFF,
+	0x14F3690D,
+	0x1A041414,
+	0x00D00000,
+	0x18864000,
+	0x49247A06,
+	0xF3CF23D5,
+	0xF4D1451E,
+	0x034A9248,
+	0x821A00C3,
+	0x0000D000,
+	0x00000680,
+	0xD949247A,
+	0x1EF3CF23,
+	0x88F4D145,
+	0x000352E3,
+	0x00080200,
+	0x00001000,
+	0x00080200,
+	0x00001000,
+	0x000A8000,
+	0x00075000,
+	0x541A8000,
+	0x03875001,
+	0x10000000,
+	0x00000000,
+	0x0080C000,
+	0x41000000,
+	0x04000002,
+	0x00820000,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0x00040100,
+	0x00000800,
+	0x00000000,
+	0x00001208,
+	0x00482000,
+	0x00008000,
+	0x00000000,
+	0x00410482,
+	0x0006A000,
+	0x0001B400,
+	0x00020000,
+	0x00000400,
+	0x0002A000,
+	0x0001E400,
+	0x5506A000,
+	0x00E1D400,
+	0x00000000,
+	0x2043090C,
+	0x00003001,
+	0x90400000,
+	0x00000000,
+	0x2020C243,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x00010040,
+	0x00000200,
+	0x00000000,
+	0x00000482,
+	0x00120800,
+	0x00002000,
+	0x80000000,
+	0x00104120,
+	0x00000200,
+	0xAC0D5F80,
+	0xFFFFFFFF,
+	0x14F3690D,
+	0x1A041414,
+	0x00D00000,
+	0x18864000,
+	0x49247A06,
+	0xF228A3D9,
+	0xF4D1451E,
+	0x034A9248,
+	0x821A0000,
+	0x0000D000,
+	0x00000680,
+	0xD949247A,
+	0x1EF228A3,
+	0x88F4D145,
+	0x000352E3,
+	0x00080200,
+	0x00001000,
+	0x00080200,
+	0x00001000,
+	0x000A8000,
+	0x00075000,
+	0x541A8000,
+	0x03875001,
+	0x10000000,
+	0x00000000,
+	0x0080C000,
+	0x41000000,
+	0x04000002,
+	0x00820000,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0x00040100,
+	0x00000800,
+	0x00000000,
+	0x00001208,
+	0x00482000,
+	0x00008000,
+	0x00000000,
+	0x00410482,
+	0x0006A000,
+	0x0001B400,
+	0x00020000,
+	0x00000400,
+	0x00020080,
+	0x00000400,
+	0x5506A000,
+	0x00E1D400,
+	0x00000000,
+	0x0000090C,
+	0x00000010,
+	0x90400000,
+	0x00000000,
+	0x2020C243,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x00010040,
+	0x00000200,
+	0x00000000,
+	0x00000482,
+	0x00120800,
+	0x00400000,
+	0x80000000,
+	0x00104120,
+	0x00000200,
+	0xAC0D5F80,
+	0xFFFFFFFF,
+	0x14F1690D,
+	0x1A041414,
+	0x00D00000,
+	0x08864000,
+	0x49247A02,
+	0xF3CF23D9,
+	0xF4D1451E,
+	0x0342E388,
+	0x821A0000,
+	0x0000D000,
+	0x00000680,
+	0xD949247A,
+	0x1EF3CF23,
+	0x88F4DE79,
+	0x000342A2,
+	0x00080200,
+	0x00001000,
+	0x00080200,
+	0x00001000,
+	0x000A8000,
+	0x00075000,
+	0x541A8000,
+	0x03875001,
+	0x10000000,
+	0x00000000,
+	0x0080C000,
+	0x41000000,
+	0x04000002,
+	0x00820000,
+	0x00489800,
+	0x801A1A1A,
+	0x00000200,
+	0x80000004,
+	0x00000200,
+	0x80000004,
+	0x00000200,
+	0x80000004,
+	0x00000200,
+	0x00000004,
+	0x00040000,
+	0x10000000,
+	0x00000000,
+	0x00000040,
+	0x00010000,
+	0x40002000,
+	0x00000100,
+	0x40000002,
+	0x00000100,
+	0x40000002,
+	0x00000100,
+	0x40000002,
+	0x00000100,
+	0x00000002,
+	0x00020000,
+	0x08000000,
+	0x00000000,
+	0x00000020,
+	0x00008000,
+	0x20001000,
+	0x00000080,
+	0x20000001,
+	0x00000080,
+	0x20000001,
+	0x00000080,
+	0x20000001,
+	0x00000080,
+	0x00000001,
+	0x00010000,
+	0x04000000,
+	0x00FF0000,
+	0x00000000,
+	0x00004000,
+	0x00000800,
+	0xC0000001,
+	0x00041419,
+	0x40000000,
+	0x04000816,
+	0x000D0000,
+	0x00006800,
+	0x00000340,
+	0xD000001A,
+	0x06800000,
+	0x00340000,
+	0x0001A000,
+	0x00000D00,
+	0x40000068,
+	0x1A000003,
+	0x00D00000,
+	0x00068000,
+	0x00003400,
+	0x000001A0,
+	0x00000401,
+	0x00000008,
+	0x00000401,
+	0x00000008,
+	0x00000401,
+	0x00000008,
+	0x00000401,
+	0x80000008,
+	0x0000007F,
+	0x20000000,
+	0x00000000,
+	0xE0000080,
+	0x0000001F,
+	0x00004000,
+};
+
-- 
1.9.1



From s.hauer at pengutronix.de  Mon Mar 31 04:37:31 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Mon, 31 Mar 2014 10:37:31 +0200
Subject: [PATCH 2/2] ARM: i.MX6 Phytec phyFLEX: Add Nand update support
In-Reply-To: <1396255051-13989-1-git-send-email-s.hauer@pengutronix.de>
References: <1396255051-13989-1-git-send-email-s.hauer@pengutronix.de>
Message-ID: <1396255051-13989-2-git-send-email-s.hauer@pengutronix.de>

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/boards/phytec-phyflex-imx6/board.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/boards/phytec-phyflex-imx6/board.c b/arch/arm/boards/phytec-phyflex-imx6/board.c
index e9bd168..c90f378 100644
--- a/arch/arm/boards/phytec-phyflex-imx6/board.c
+++ b/arch/arm/boards/phytec-phyflex-imx6/board.c
@@ -21,6 +21,7 @@
 #include <gpio.h>
 #include <init.h>
 #include <of.h>
+#include <mach/bbu.h>
 
 #include <mach/imx6.h>
 
@@ -43,6 +44,8 @@ static int phytec_pfla02_init(void)
 
 	eth_phy_reset();
 
+	imx6_bbu_nand_register_handler("nand", BBU_HANDLER_FLAG_DEFAULT);
+
 	return 0;
 }
 device_initcall(phytec_pfla02_init);
-- 
1.9.1



From s.hauer at pengutronix.de  Mon Mar 31 04:37:30 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Mon, 31 Mar 2014 10:37:30 +0200
Subject: [PATCH 1/2] ARM: i.MX6: Add Nand boot bbu handler
Message-ID: <1396255051-13989-1-git-send-email-s.hauer@pengutronix.de>

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/mach-imx/Kconfig            |   6 +
 arch/arm/mach-imx/Makefile           |   1 +
 arch/arm/mach-imx/imx6-bbu-nand.c    | 497 +++++++++++++++++++++++++++++++++++
 arch/arm/mach-imx/include/mach/bbu.h |   6 +
 4 files changed, 510 insertions(+)
 create mode 100644 arch/arm/mach-imx/imx6-bbu-nand.c

diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index b7e7533..8d91e3e 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -109,6 +109,12 @@ config BAREBOX_UPDATE_IMX_EXTERNAL_NAND
 	depends on BAREBOX_UPDATE
 	default y
 
+config BAREBOX_UPDATE_IMX6_NAND
+	bool
+	depends on ARCH_IMX6
+	depends on BAREBOX_UPDATE
+	default y
+
 comment "Freescale i.MX System-on-Chip"
 
 config ARCH_IMX1
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index b3f00f9..03e5b10 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -20,4 +20,5 @@ obj-y += devices.o imx.o esdctl.o
 obj-y += boot.o
 obj-$(CONFIG_BAREBOX_UPDATE) += imx-bbu-internal.o
 obj-$(CONFIG_BAREBOX_UPDATE_IMX_EXTERNAL_NAND) += imx-bbu-external-nand.o
+obj-$(CONFIG_BAREBOX_UPDATE_IMX6_NAND) += imx6-bbu-nand.o
 pbl-y += esdctl.o
diff --git a/arch/arm/mach-imx/imx6-bbu-nand.c b/arch/arm/mach-imx/imx6-bbu-nand.c
new file mode 100644
index 0000000..2d07059
--- /dev/null
+++ b/arch/arm/mach-imx/imx6-bbu-nand.c
@@ -0,0 +1,497 @@
+/*
+ * Copyright (C) 2014 Sascha Hauer, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation.
+ *
+ */
+
+#define pr_fmt(fmt) "imx6-bbu-nand: " fmt
+
+#include <filetype.h>
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <fcntl.h>
+#include <ioctl.h>
+#include <sizes.h>
+#include <bbu.h>
+#include <fs.h>
+#include <mach/bbu.h>
+#include <linux/mtd/mtd-abi.h>
+#include <linux/mtd/mtd.h>
+#include <linux/stat.h>
+
+struct dbbt_block {
+	uint32_t Checksum;
+	uint32_t FingerPrint;
+	uint32_t Version;
+	uint32_t reserved;
+	uint32_t DBBTNumOfPages;
+};
+
+struct fcb_block {
+	uint32_t Checksum;		/* First fingerprint in first byte */
+	uint32_t FingerPrint;		/* 2nd fingerprint at byte 4 */
+	uint32_t Version;		/* 3rd fingerprint at byte 8 */
+	uint8_t DataSetup;
+	uint8_t DataHold;
+	uint8_t AddressSetup;
+	uint8_t DSAMPLE_TIME;
+	/* These are for application use only and not for ROM. */
+	uint8_t NandTimingState;
+	uint8_t REA;
+	uint8_t RLOH;
+	uint8_t RHOH;
+	uint32_t PageDataSize;		/* 2048 for 2K pages, 4096 for 4K pages */
+	uint32_t TotalPageSize;		/* 2112 for 2K pages, 4314 for 4K pages */
+	uint32_t SectorsPerBlock;	/* Number of 2K sections per block */
+	uint32_t NumberOfNANDs;		/* Total Number of NANDs - not used by ROM */
+	uint32_t TotalInternalDie;	/* Number of separate chips in this NAND */
+	uint32_t CellType;		/* MLC or SLC */
+	uint32_t EccBlockNEccType;	/* Type of ECC, can be one of BCH-0-20 */
+	uint32_t EccBlock0Size;		/* Number of bytes for Block0 - BCH */
+	uint32_t EccBlockNSize;		/* Block size in bytes for all blocks other than Block0 - BCH */
+	uint32_t EccBlock0EccType;	/* Ecc level for Block 0 - BCH */
+	uint32_t MetadataBytes;		/* Metadata size - BCH */
+	uint32_t NumEccBlocksPerPage;	/* Number of blocks per page for ROM use - BCH */
+	uint32_t EccBlockNEccLevelSDK;	/* Type of ECC, can be one of BCH-0-20 */
+	uint32_t EccBlock0SizeSDK;	/* Number of bytes for Block0 - BCH */
+	uint32_t EccBlockNSizeSDK;	/* Block size in bytes for all blocks other than Block0 - BCH */
+	uint32_t EccBlock0EccLevelSDK;	/* Ecc level for Block 0 - BCH */
+	uint32_t NumEccBlocksPerPageSDK;/* Number of blocks per page for SDK use - BCH */
+	uint32_t MetadataBytesSDK;	/* Metadata size - BCH */
+	uint32_t EraseThreshold;	/* To set into BCH_MODE register */
+	uint32_t BootPatch;		/* 0 for normal boot and 1 to load patch starting next to FCB */
+	uint32_t PatchSectors;		/* Size of patch in sectors */
+	uint32_t Firmware1_startingPage;/* Firmware image starts on this sector */
+	uint32_t Firmware2_startingPage;/* Secondary FW Image starting Sector */
+	uint32_t PagesInFirmware1;	/* Number of sectors in firmware image */
+	uint32_t PagesInFirmware2;	/* Number of sector in secondary FW image */
+	uint32_t DBBTSearchAreaStartAddress; /* Page address where dbbt search area begins */
+	uint32_t BadBlockMarkerByte;	/* Byte in page data that have manufacturer marked bad block marker, */
+					/* this will be swapped with metadata[0] to complete page data. */
+	uint32_t BadBlockMarkerStartBit;/* For BCH ECC sizes other than 8 and 16 the bad block marker does not */
+					/* start at 0th bit of BadBlockMarkerByte. This field is used to get to */
+					/* the start bit of bad block marker byte with in BadBlockMarkerByte */
+	uint32_t BBMarkerPhysicalOffset;/* FCB value that gives byte offset for bad block marker on physical NAND page */
+	uint32_t BCHType;
+
+	uint32_t TMTiming2_ReadLatency;
+	uint32_t TMTiming2_PreambleDelay;
+	uint32_t TMTiming2_CEDelay;
+	uint32_t TMTiming2_PostambleDelay;
+	uint32_t TMTiming2_CmdAddPause;
+	uint32_t TMTiming2_DataPause;
+	uint32_t TMSpeed;
+	uint32_t TMTiming1_BusyTimeout;
+
+	uint32_t DISBBM;	/* the flag to enable (1)/disable(0) bi swap */
+	uint32_t BBMarkerPhysicalOffsetInSpareData; /* The swap position of main area in spare area */
+};
+
+#define BF_VAL(v, bf)		(((v) & bf##_MASK) >> bf##_OFFSET)
+#define GETBIT(v,n)	(((v) >> (n)) & 0x1)
+
+static uint8_t calculate_parity_13_8(uint8_t d)
+{
+	uint8_t p = 0;
+
+	p |= (GETBIT(d, 6) ^ GETBIT(d, 5) ^ GETBIT(d, 3) ^ GETBIT(d, 2))		 << 0;
+	p |= (GETBIT(d, 7) ^ GETBIT(d, 5) ^ GETBIT(d, 4) ^ GETBIT(d, 2) ^ GETBIT(d, 1)) << 1;
+	p |= (GETBIT(d, 7) ^ GETBIT(d, 6) ^ GETBIT(d, 5) ^ GETBIT(d, 1) ^ GETBIT(d, 0)) << 2;
+	p |= (GETBIT(d, 7) ^ GETBIT(d, 4) ^ GETBIT(d, 3) ^ GETBIT(d, 0))		 << 3;
+	p |= (GETBIT(d, 6) ^ GETBIT(d, 4) ^ GETBIT(d, 3) ^ GETBIT(d, 2) ^ GETBIT(d, 1) ^ GETBIT(d, 0)) << 4;
+	return p;
+}
+
+static void encode_hamming_13_8(void *_src, void *_ecc, size_t size)
+{
+	int i;
+	uint8_t *src = _src;
+	uint8_t *ecc = _ecc;
+
+	for (i = 0; i < size; i++)
+		ecc[i] = calculate_parity_13_8(src[i]);
+}
+
+static uint32_t calc_chksum(void *buf, size_t size)
+{
+	u32 chksum = 0;
+	u8 *bp = buf;
+	size_t i;
+
+	for (i = 0; i < size; i++)
+		chksum += bp[i];
+
+	return ~chksum;
+}
+
+static __maybe_unused void dump_fcb(void *buf)
+{
+	struct fcb_block *fcb = buf;
+
+	pr_debug("Checksum:                   0x%08x\n", fcb->Checksum);
+	pr_debug("FingerPrint:                0x%08x\n", fcb->FingerPrint);
+	pr_debug("Version:                    0x%08x\n", fcb->Version);
+	pr_debug("DataSetup:                  0x%02x\n", fcb->DataSetup);
+	pr_debug("DataHold:                   0x%02x\n", fcb->DataHold);
+	pr_debug("AddressSetup:               0x%02x\n", fcb->AddressSetup);
+	pr_debug("DSAMPLE_TIME:               0x%02x\n", fcb->DSAMPLE_TIME);
+	pr_debug("NandTimingState:            0x%02x\n", fcb->NandTimingState);
+	pr_debug("REA:                        0x%02x\n", fcb->REA);
+	pr_debug("RLOH:                       0x%02x\n", fcb->RLOH);
+	pr_debug("RHOH:                       0x%02x\n", fcb->RHOH);
+	pr_debug("PageDataSize:               0x%08x\n", fcb->PageDataSize);
+	pr_debug("TotalPageSize:              0x%08x\n", fcb->TotalPageSize);
+	pr_debug("SectorsPerBlock:            0x%08x\n", fcb->SectorsPerBlock);
+	pr_debug("NumberOfNANDs:              0x%08x\n", fcb->NumberOfNANDs);
+	pr_debug("TotalInternalDie:           0x%08x\n", fcb->TotalInternalDie);
+	pr_debug("CellType:                   0x%08x\n", fcb->CellType);
+	pr_debug("EccBlockNEccType:           0x%08x\n", fcb->EccBlockNEccType);
+	pr_debug("EccBlock0Size:              0x%08x\n", fcb->EccBlock0Size);
+	pr_debug("EccBlockNSize:              0x%08x\n", fcb->EccBlockNSize);
+	pr_debug("EccBlock0EccType:           0x%08x\n", fcb->EccBlock0EccType);
+	pr_debug("MetadataBytes:              0x%08x\n", fcb->MetadataBytes);
+	pr_debug("NumEccBlocksPerPage:        0x%08x\n", fcb->NumEccBlocksPerPage);
+	pr_debug("EccBlockNEccLevelSDK:       0x%08x\n", fcb->EccBlockNEccLevelSDK);
+	pr_debug("EccBlock0SizeSDK:           0x%08x\n", fcb->EccBlock0SizeSDK);
+	pr_debug("EccBlockNSizeSDK:           0x%08x\n", fcb->EccBlockNSizeSDK);
+	pr_debug("EccBlock0EccLevelSDK:       0x%08x\n", fcb->EccBlock0EccLevelSDK);
+	pr_debug("NumEccBlocksPerPageSDK:     0x%08x\n", fcb->NumEccBlocksPerPageSDK);
+	pr_debug("MetadataBytesSDK:           0x%08x\n", fcb->MetadataBytesSDK);
+	pr_debug("EraseThreshold:             0x%08x\n", fcb->EraseThreshold);
+	pr_debug("BootPatch:                  0x%08x\n", fcb->BootPatch);
+	pr_debug("PatchSectors:               0x%08x\n", fcb->PatchSectors);
+	pr_debug("Firmware1_startingPage:     0x%08x\n", fcb->Firmware1_startingPage);
+	pr_debug("Firmware2_startingPage:     0x%08x\n", fcb->Firmware2_startingPage);
+	pr_debug("PagesInFirmware1:           0x%08x\n", fcb->PagesInFirmware1);
+	pr_debug("PagesInFirmware2:           0x%08x\n", fcb->PagesInFirmware2);
+	pr_debug("DBBTSearchAreaStartAddress: 0x%08x\n", fcb->DBBTSearchAreaStartAddress);
+	pr_debug("BadBlockMarkerByte:         0x%08x\n", fcb->BadBlockMarkerByte);
+	pr_debug("BadBlockMarkerStartBit:     0x%08x\n", fcb->BadBlockMarkerStartBit);
+	pr_debug("BBMarkerPhysicalOffset:     0x%08x\n", fcb->BBMarkerPhysicalOffset);
+	pr_debug("BCHType:                    0x%08x\n", fcb->BCHType);
+	pr_debug("TMTiming2_ReadLatency:      0x%08x\n", fcb->TMTiming2_ReadLatency);
+	pr_debug("TMTiming2_PreambleDelay:    0x%08x\n", fcb->TMTiming2_PreambleDelay);
+	pr_debug("TMTiming2_CEDelay:          0x%08x\n", fcb->TMTiming2_CEDelay);
+	pr_debug("TMTiming2_PostambleDelay:   0x%08x\n", fcb->TMTiming2_PostambleDelay);
+	pr_debug("TMTiming2_CmdAddPause:      0x%08x\n", fcb->TMTiming2_CmdAddPause);
+	pr_debug("TMTiming2_DataPause:        0x%08x\n", fcb->TMTiming2_DataPause);
+	pr_debug("TMSpeed:                    0x%08x\n", fcb->TMSpeed);
+	pr_debug("TMTiming1_BusyTimeout:      0x%08x\n", fcb->TMTiming1_BusyTimeout);
+	pr_debug("DISBBM:                     0x%08x\n", fcb->DISBBM);
+	pr_debug("BBMarkerPhysOfsInSpareData: 0x%08x\n", fcb->BBMarkerPhysicalOffsetInSpareData);
+}
+
+static __maybe_unused ssize_t raw_read_page(struct mtd_info *mtd, void *dst, loff_t offset)
+{
+	struct mtd_oob_ops ops;
+	ssize_t ret;
+
+	ops.mode = MTD_OPS_RAW;
+	ops.ooboffs = 0;
+	ops.datbuf = dst;
+	ops.len = mtd->writesize;
+	ops.oobbuf = dst + mtd->writesize;
+	ops.ooblen = mtd->oobsize;
+	ret = mtd_read_oob(mtd, offset, &ops);
+
+        return ret;
+}
+
+static ssize_t raw_write_page(struct mtd_info *mtd, void *buf, loff_t offset)
+{
+	struct mtd_oob_ops ops;
+	ssize_t ret;
+
+	ops.mode = MTD_OPS_RAW;
+	ops.ooboffs = 0;
+	ops.datbuf = buf;
+	ops.len = mtd->writesize;
+	ops.oobbuf = buf + mtd->writesize;
+	ops.ooblen = mtd->oobsize;
+	ret = mtd_write_oob(mtd, offset, &ops);
+
+        return ret;
+}
+
+static int fcb_create(struct fcb_block *fcb, struct mtd_info *mtd)
+{
+	fcb->FingerPrint = 0x20424346;
+	fcb->Version = 0x01000000;
+	fcb->PageDataSize = mtd->writesize;
+	fcb->TotalPageSize = mtd->writesize + mtd->oobsize;
+	fcb->SectorsPerBlock = mtd->erasesize / mtd->writesize;
+
+	if (mtd->writesize == 2048) {
+		fcb->EccBlock0EccType = 4;
+	} else if (mtd->writesize == 4096) {
+		if (mtd->oobsize == 218) {
+			fcb->EccBlock0EccType = 8;
+		} else if (mtd->oobsize == 128) {
+			fcb->EccBlock0EccType = 4;
+		} else {
+			pr_err("Illegal oobsize %d\n", mtd->oobsize);
+			return -EINVAL;
+		}
+	} else {
+		pr_err("Illegal writesize %d\n", mtd->writesize);
+		return -EINVAL;
+	}
+
+	fcb->EccBlockNEccType = fcb->EccBlock0EccType;
+
+	/* Also hardcoded in kobs-ng */
+	fcb->DataSetup = 80;
+	fcb->DataHold = 60;
+	fcb->AddressSetup = 25;
+	fcb->DSAMPLE_TIME = 6;
+	fcb->MetadataBytes = 0x0000000a;
+	fcb->EccBlock0Size = 0x00000200;
+	fcb->EccBlockNSize = 0x00000200;
+
+	fcb->NumEccBlocksPerPage = mtd->writesize / fcb->EccBlock0Size - 1;
+
+	/* DBBT search area starts at third block */
+	fcb->DBBTSearchAreaStartAddress = mtd->erasesize / mtd->writesize * 2;
+
+	if (mtd->writesize == 2048) {
+		fcb->BadBlockMarkerByte = 0x000007cf;
+	} else {
+		pr_err("BadBlockMarkerByte unknown for writesize %d\n", mtd->writesize);
+		return -EINVAL;
+	}
+
+	fcb->BBMarkerPhysicalOffset = mtd->writesize;
+
+	fcb->Checksum = calc_chksum((void *)fcb + 4, sizeof(*fcb) - 4);
+
+	return 0;
+}
+
+static int imx6_bbu_erase(struct mtd_info *mtd)
+{
+	uint64_t offset = 0;
+	int len = SZ_2M;
+	struct erase_info erase;
+	int ret;
+
+	while (len > 0) {
+		pr_debug("erasing at 0x%08llx\n", offset);
+		if (mtd_block_isbad(mtd, offset)) {
+			offset += mtd->erasesize;
+			pr_debug("erase skip block @ 0x%08llx\n", offset);
+			continue;
+		}
+
+		memset(&erase, 0, sizeof(erase));
+		erase.addr = offset;
+		erase.len = mtd->erasesize;
+
+		ret = mtd_erase(mtd, &erase);
+		if (ret)
+			return ret;
+
+		offset += mtd->erasesize;
+		len -= mtd->erasesize;
+	}
+
+	return 0;
+}
+
+static int imx6_bbu_write_firmware(struct mtd_info *mtd, int block, void *buf, size_t len)
+{
+	uint64_t offset = block * mtd->erasesize;
+	int ret;
+	size_t written;
+
+	while (len > 0) {
+		int now = min(len, mtd->erasesize);
+
+		pr_debug("writing %p at 0x%08llx, left 0x%08x\n",
+				buf, offset, len);
+
+		if (mtd_block_isbad(mtd, offset)) {
+			offset += mtd->erasesize;
+			block++;
+			pr_debug("write skip block @ 0x%08llx\n", offset);
+			continue;
+		}
+
+		ret = mtd_write(mtd, offset, now, &written, buf);
+		if (ret)
+			return ret;
+
+		offset += now;
+		len -= now;
+		buf += now;
+		block++;
+	}
+
+	return block;
+}
+
+static int dbbt_data_create(struct mtd_info *mtd, void *buf, int block_last)
+{
+	int n;
+	int n_bad_blocks = 0;
+	uint32_t *bb = buf + 0x8;
+	uint32_t *n_bad_blocksp = buf + 0x4;
+
+	for (n = 0; n <= block_last; n++) {
+		loff_t offset = n * mtd->erasesize;
+		if (mtd_block_isbad(mtd, offset)) {
+			n_bad_blocks++;
+			*bb = n;
+			bb++;
+		}
+	}
+
+	*n_bad_blocksp = n_bad_blocks;
+
+	return n_bad_blocks;
+}
+
+static int imx6_bbu_nand_update(struct bbu_handler *handler, struct bbu_data *data)
+{
+	struct cdev *bcb_cdev;
+	struct mtd_info *mtd;
+	int ret, block_fw1, block_fw2, block_last;
+	struct fcb_block *fcb;
+	struct dbbt_block *dbbt;
+	void *fcb_raw_page, *dbbt_page, *dbbt_data_page;
+	void *ecc;
+	int written;
+	void *fw;
+	unsigned fw_size;
+	int i;
+
+	if (file_detect_type(data->image, data->len) != filetype_arm_barebox &&
+			!bbu_force(data, "Not an ARM barebox image"))
+		return -EINVAL;
+
+	ret = bbu_confirm(data);
+	if (ret)
+		return ret;
+
+	bcb_cdev = cdev_by_name("nand0");
+	if (!bcb_cdev) {
+		pr_err("%s: No FCB device!\n", __func__);
+		return -ENODEV;
+	}
+
+	mtd = bcb_cdev->mtd;
+
+	fcb_raw_page = xzalloc(mtd->writesize + mtd->oobsize);
+
+	fcb = fcb_raw_page + 12;
+	ecc = fcb_raw_page + 512 + 12;
+
+	dbbt_page = xzalloc(mtd->writesize);
+	dbbt_data_page = xzalloc(mtd->writesize);
+	dbbt = dbbt_page;
+
+	/*
+	 * We have to write one additional page to make the ROM happy.
+	 * Maybe the PagesInFirmwarex fields are really the number of pages - 1.
+	 * kobs-ng has the same.
+	 */
+	fw_size = ALIGN(data->len + mtd->writesize, mtd->writesize);
+	fw = xzalloc(fw_size);
+	memcpy(fw, data->image, data->len);
+
+	block_fw1 = 4;
+
+	ret = imx6_bbu_erase(mtd);
+	if (ret)
+		goto out;
+
+	ret = imx6_bbu_write_firmware(mtd, block_fw1, fw, fw_size);
+	if (ret < 0)
+		goto out;
+
+	block_fw2 = ret;
+
+	ret = imx6_bbu_write_firmware(mtd, block_fw2, fw, fw_size);
+	if (ret < 0)
+		goto out;
+
+	block_last = ret;
+
+	fcb->Firmware1_startingPage = block_fw1 * mtd->erasesize / mtd->writesize;
+	fcb->Firmware2_startingPage = block_fw2 * mtd->erasesize / mtd->writesize;
+	fcb->PagesInFirmware1 = ALIGN(data->len, mtd->writesize) / mtd->writesize;
+	fcb->PagesInFirmware2 = fcb->PagesInFirmware1;
+
+	fcb_create(fcb, mtd);
+	encode_hamming_13_8(fcb, ecc, 512);
+	ret = raw_write_page(mtd, fcb_raw_page, 0);
+	if (ret)
+		goto out;
+
+	ret = raw_write_page(mtd, fcb_raw_page, mtd->erasesize);
+	if (ret)
+		goto out;
+
+	dbbt->Checksum = 0;
+	dbbt->FingerPrint = 0x54424244;
+	dbbt->Version = 0x01000000;
+
+	ret = dbbt_data_create(mtd, dbbt_data_page, block_last);
+	if (ret < 0)
+		goto out;
+
+	if (ret > 0)
+		dbbt->DBBTNumOfPages = 1;
+
+	for (i = 2; i < 4; i++) {
+		ret = mtd_write(mtd, mtd->erasesize * i, 2048, &written, dbbt_page);
+		if (ret)
+			goto out;
+
+		if (dbbt->DBBTNumOfPages > 0) {
+			ret = mtd_write(mtd, mtd->erasesize * i + mtd->writesize * 4,
+					2048, &written, dbbt_data_page);
+			if (ret)
+				goto out;
+		}
+	}
+
+out:
+	free(dbbt_page);
+	free(dbbt_data_page);
+	free(fcb_raw_page);
+	free(fw);
+
+	return ret;
+}
+
+int imx6_bbu_nand_register_handler(const char *name, unsigned long flags)
+{
+	struct bbu_handler *handler;
+	int ret;
+
+	handler = xzalloc(sizeof(*handler));
+	handler->devicefile = "/dev/nand0";
+	handler->name = name;
+	handler->flags = flags;
+	handler->handler = imx6_bbu_nand_update;
+
+	ret = bbu_register_handler(handler);
+	if (ret)
+		free(handler);
+
+	return ret;
+}
diff --git a/arch/arm/mach-imx/include/mach/bbu.h b/arch/arm/mach-imx/include/mach/bbu.h
index 3cd3b1e..1644d85 100644
--- a/arch/arm/mach-imx/include/mach/bbu.h
+++ b/arch/arm/mach-imx/include/mach/bbu.h
@@ -33,6 +33,8 @@ int imx6_bbu_internal_spi_i2c_register_handler(const char *name, char *devicefil
 		unsigned long flags, struct imx_dcd_v2_entry *dcd, int dcdsize,
 		unsigned long app_dest);
 
+int imx6_bbu_nand_register_handler(const char *name, unsigned long flags);
+
 #else
 
 static inline int imx51_bbu_internal_mmc_register_handler(const char *name, char *devicefile,
@@ -77,6 +79,10 @@ static inline int imx6_bbu_internal_spi_i2c_register_handler(const char *name, c
 	return -ENOSYS;
 }
 
+static inline int imx6_bbu_nand_register_handler(const char *name, unsigned long flags)
+{
+	return -ENOSYS;
+}
 #endif
 
 #if defined(CONFIG_BAREBOX_UPDATE_IMX_EXTERNAL_NAND)
-- 
1.9.1



From s.hauer at pengutronix.de  Mon Mar 31 04:42:09 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Mon, 31 Mar 2014 10:42:09 +0200
Subject: [PATCH] i.MX6: bbu: Barebox update support for NAND.
In-Reply-To: <20140313065458.GQ17250@pengutronix.de>
References: <1394610851-721-1-git-send-email-d.lavnikevich@sam-solutions.com>
 <20140313065458.GQ17250@pengutronix.de>
Message-ID: <20140331084209.GO17250@pengutronix.de>

On Thu, Mar 13, 2014 at 07:54:58AM +0100, Sascha Hauer wrote:
> Hi Dmitry,
> 
> On Wed, Mar 12, 2014 at 10:54:11AM +0300, Dmitry Lavnikevich wrote:
> > This patch implements updating barebox on i.MX6 NAND. In userspace
> > similar task is performed by freescale kobs-ng utility.
> > To use this bbu profile nand handler should be registered in board
> > code with 'imx6_bbu_internal_nand_register_handler' function.
> 
> I have the very same patch in the queue, it seems we have duplicated
> some work. As this version has some shortcomings I'll post my version as
> an alternative implementation. Also I'll try your version on a board I
> have here on which my version doesn't work (which is the reason I
> haven't posted my patch yet)

The NAND boot on our board finally works. It turned out to be a silly
bug in the DCD table. The DCD table turned off the GPMI clocks which
of course prevented the ROM from loading the rest of the image.

I just resent my version of this patch, but included the missing check
for a valid image and the confirmation question from your version.

Maybe you could give this a test on your board.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From hussein at unixcat.org  Mon Mar 31 09:04:18 2014
From: hussein at unixcat.org (Nur Hussein)
Date: Mon, 31 Mar 2014 21:04:18 +0800
Subject: Building and booting Barebox on Pandaboard
Message-ID: <20140331130418.GA3113@radagast>

Dear all,

I am using barebox-2014.03.0 to try to boot on a Pandaboard ES. I have followed the instructions in the docs:

http://wiki.barebox.org/doku.php?id=boards:omap

I could not however find a barebox.bin.ift file in the output, so I guessed and went with the barebox-flash-image linked file and named it MLO.

It did not work. The Pandaboard ES did not boot. 

Is the documentation outdated? Is there something else I should be doing?

-- 
Nur Hussein
http://unixcat.org


From s.hauer at pengutronix.de  Mon Mar 31 10:58:43 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Mon, 31 Mar 2014 16:58:43 +0200
Subject: [PATCH] ARM: Panda: Fix board selection in panda defconfig files
Message-ID: <1396277923-25059-1-git-send-email-s.hauer@pengutronix.de>

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/configs/panda_defconfig       | 4 +---
 arch/arm/configs/panda_xload_defconfig | 2 +-
 2 files changed, 2 insertions(+), 4 deletions(-)

diff --git a/arch/arm/configs/panda_defconfig b/arch/arm/configs/panda_defconfig
index 7be86ac..c42140a 100644
--- a/arch/arm/configs/panda_defconfig
+++ b/arch/arm/configs/panda_defconfig
@@ -1,5 +1,5 @@
 CONFIG_ARCH_OMAP=y
-CONFIG_ARCH_OMAP4=y
+CONFIG_MACH_PANDA=y
 CONFIG_THUMB2_BAREBOX=y
 CONFIG_CMD_ARM_MMUINFO=y
 CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
@@ -29,9 +29,7 @@ CONFIG_CMD_READLINE=y
 CONFIG_CMD_MENU=y
 CONFIG_CMD_MENU_MANAGEMENT=y
 CONFIG_CMD_TIME=y
-CONFIG_CMD_DIRNAME=y
 CONFIG_CMD_LN=y
-CONFIG_CMD_READLINK=y
 CONFIG_CMD_TFTP=y
 CONFIG_CMD_ECHO_E=y
 CONFIG_CMD_MEMINFO=y
diff --git a/arch/arm/configs/panda_xload_defconfig b/arch/arm/configs/panda_xload_defconfig
index 5cedcff..29a2afd 100644
--- a/arch/arm/configs/panda_xload_defconfig
+++ b/arch/arm/configs/panda_xload_defconfig
@@ -1,7 +1,7 @@
 CONFIG_ARCH_OMAP=y
-CONFIG_ARCH_OMAP4=y
 # CONFIG_OMAP_GPMC is not set
 CONFIG_OMAP_BUILD_IFT=y
+CONFIG_MACH_PANDA=y
 CONFIG_THUMB2_BAREBOX=y
 # CONFIG_CMD_ARM_CPUINFO is not set
 CONFIG_MMU=y
-- 
1.9.1



From s.hauer at pengutronix.de  Mon Mar 31 11:09:20 2014
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Mon, 31 Mar 2014 17:09:20 +0200
Subject: Building and booting Barebox on Pandaboard
In-Reply-To: <20140331130418.GA3113@radagast>
References: <20140331130418.GA3113@radagast>
Message-ID: <20140331150920.GP17250@pengutronix.de>

Hi,

On Mon, Mar 31, 2014 at 09:04:18PM +0800, Nur Hussein wrote:
> Dear all,
> 
> I am using barebox-2014.03.0 to try to boot on a Pandaboard ES. I have followed the instructions in the docs:
> 
> http://wiki.barebox.org/doku.php?id=boards:omap
> 
> I could not however find a barebox.bin.ift file in the output, so I guessed and went with the barebox-flash-image linked file and named it MLO.

Yes, right. barebox-flash-image is the correct file to use. I updated
this in the wiki.

> 
> It did not work. The Pandaboard ES did not boot.

Due to updates the panda_*defconfig configs currently do not build for
the panda board. Please either manually call a make menuconfig and set
the config back to panda:

System Type  --->
  OMAP Features  --->
    Select OMAP board (Texas Instrument's Panda Board)  --->

Or apply the patch I just sent to the list:

ARM: Panda: Fix board selection in panda defconfig files

I'm not 100% sure the ES variant is supported. What was the difference
between the ES and the regular board again? Does the ES have a omap4460
whereas the regular board has a omap4430? If yes then the ES should be
supported.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From hussein at unixcat.org  Mon Mar 31 11:14:59 2014
From: hussein at unixcat.org (Nur Hussein)
Date: Mon, 31 Mar 2014 23:14:59 +0800
Subject: Building and booting Barebox on Pandaboard
In-Reply-To: <20140331150920.GP17250@pengutronix.de>
References: <20140331130418.GA3113@radagast>
 <20140331150920.GP17250@pengutronix.de>
Message-ID: <20140331151459.GA9544@radagast>

Hello,

On Mon, Mar 31, 2014 at 05:09:20PM +0200, Sascha Hauer wrote:
> Due to updates the panda_*defconfig configs currently do not build for
> the panda board. Please either manually call a make menuconfig and set
> the config back to panda:
> 
> System Type  --->
>   OMAP Features  --->
>     Select OMAP board (Texas Instrument's Panda Board)  --->
> 
> Or apply the patch I just sent to the list:

Thanks for the heads up. I shall try it and see if it works.

> ARM: Panda: Fix board selection in panda defconfig files
> 
> I'm not 100% sure the ES variant is supported. What was the difference
> between the ES and the regular board again? Does the ES have a omap4460
> whereas the regular board has a omap4430? If yes then the ES should be
> supported.

Yes, this is indeed the case.

Thank you for the reply and the patch.

-- 
Nur Hussein
http://unixcat.org


