[PATCH 4/4] arm/cpu/lowlevel: invalidate i-cache before enabling
l.stach at pengutronix.de
Thu Dec 11 03:14:20 PST 2014
Am Donnerstag, den 11.12.2014, 10:15 +0100 schrieb Uwe Kleine-König:
> Architecturally the cache contents are undefined so it might well
> contain stale data at reset. So better be save than sorry.
> I verifyed that the added instructions are defined for both, ARMv6 and
> ARMv7, using the ARM Architecture Reference Manual, ARMv7-A and ARMv7-R
> edition (ARM DDI 0406C.c).
> Signed-off-by: Uwe Kleine-König <u.kleine-koenig at pengutronix.de>
> arch/arm/cpu/lowlevel.S | 14 +++++++++++++-
> 1 file changed, 13 insertions(+), 1 deletion(-)
> diff --git a/arch/arm/cpu/lowlevel.S b/arch/arm/cpu/lowlevel.S
> index dd0f75a8802a..af2b0a8ac93a 100644
> --- a/arch/arm/cpu/lowlevel.S
> +++ b/arch/arm/cpu/lowlevel.S
> @@ -11,7 +11,19 @@ ENTRY(arm_cpu_lowlevel_init)
> msr cpsr, r12
> #if __LINUX_ARM_ARCH__ >= 6
> + * Invalidate instruction cache and branch predictor. Even if the
> + * i-cache is off it might contain stale entries that are better
> + * discarded before enabling the cache.
> + */
> + /* ICIALLU: Invalidate all instruction caches to PoU */
> + mcr p15, 0, r12, c7, c5, 0
> + /* BPIALL: Invalidate all branch predictors */
> + mcr p15, 0, r12, c7, c5, 6
I don't think the above operation is needed as it is already implicitly
done in the ICIALLU op.
Citing the ARM ARM about ICIALLU/ICIALLUIS: "These instructions
invalidate the entire instruction cache or caches, and, if branch
predictors are architecturally-visible, all branch predictors."
Otherwise I think this series looks good. It makes the code more
readable and while the I-Cache _should_ be clean when the core comes out
of reset I can well see the use-case where we drop into barebox from an
So with the above fixed:
Reviewed-by: Lucas Stach <l.stach at pengutronix.de>
Pengutronix e.K. | Lucas Stach |
Industrial Linux Solutions | http://www.pengutronix.de/ |
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