[PATCH 2/4] arm/cpu/lowlevel: Use coprocessor instruction for ARMv7, too

[Uwe Kleine-König]

ARMv7 also supports the mcr syntax for the isb instructions, so use that
one to simplify the code a bit. The Linux kernel does the same, for
example in the decompressor's __armv7_mmu_cache_on function.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig at pengutronix.de>
---
 arch/arm/cpu/lowlevel.S | 14 ++++++++++----
 1 file changed, 10 insertions(+), 4 deletions(-)

diff --git a/arch/arm/cpu/lowlevel.S b/arch/arm/cpu/lowlevel.S
index 7cc14b954f1f..7c99ecaad9dd 100644
--- a/arch/arm/cpu/lowlevel.S
+++ b/arch/arm/cpu/lowlevel.S
@@ -11,10 +11,16 @@ ENTRY(arm_cpu_lowlevel_init)
 	orr	r12, r12, #0xd3
 	msr	cpsr, r12
 
-#if __LINUX_ARM_ARCH__ >= 7
-	isb
-#elif __LINUX_ARM_ARCH__ == 6
-	mcr	p15, 0, r12, c7, c5, 4
+#if __LINUX_ARM_ARCH__ >= 6
+	/*
+	 * Note that the ARM Architecture Reference Manual, ARMv7-A and ARMv7-R
+	 * edition (ARM DDI 0406C.c) doesn't define this instruction in the
+	 * ARMv6 part (D12.7.10). It only has: "Support of additional
+	 * operations is IMPLEMENTATION DEFINED".
+	 * But an earlier version of the ARMARM (ARM DDI 0100I) does define it
+	 * as "Flush prefetch buffer (PrefetchFlush)".
+	 */
+	mcr	p15, 0, r12, c7, c5, 4		/* ISB */
 #endif
 
 	/* disable MMU stuff and data/unified caches */
-- 
2.1.3