/dev/disk0 vs /dev/mmc0

[Lucas Stach]

Am Dienstag, den 08.10.2013, 16:49 +0200 schrieb David Jander:
[...]
> 
> For DRAM clock scaling, only the clock divider or PLL should ever be
> changed. Any other parameters should stay the same. If this has really been
> done, I'd like to see it...
> DRAM calibration settings have to do with signal propagation on the PCB. That
> has nothing to do with clock speeds or -settings.
> 
Take a look at the Tegra20 Colibri in the mainline kernel. The DT there
contains optimized timing register settings for every DRAM clock
frequency. Those are loaded into a shadow registerset in the
memory-controller that latches the settings into the live registers at
the same moment the clock divider is changed.

My understanding of the docs says a similar thing thing is possible on
i.MX6, although no one has done such a thing there up until now.

> Ok, now can we both please go back to work?

Absolutely.

Regards,
Lucas

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