[PATCH v2 3/5] tegra: add driver for the clock and reset module

[Sascha Hauer]

On Sun, Mar 10, 2013 at 11:41:44AM +0400, Antony Pavlov wrote:
> > +static void __iomem *car_base;
> > +
> > +enum tegra20_clks {
> > +       cpu, ac97 = 3, rtc, timer, uarta, gpio = 8, sdmmc2, i2s1 = 11, i2c1,
> > +       ndflash, sdmmc1, sdmmc4, twc, pwm, i2s2, epp, gr2d = 21, usbd, isp,
> > +       gr3d, ide, disp2, disp1, host1x, vcp, cache2 = 31, mem, ahbdma, apbdma,
> > +       kbc = 36, stat_mon, pmc, fuse, kfuse, sbc1, nor, spi, sbc2, xio, sbc3,
> > +       dvc, dsi, mipi = 50, hdmi, csi, tvdac, i2c2, uartc, emc = 57, usb2,
> > +       usb3, mpe, vde, bsea, bsev, speedo, uartd, uarte, i2c3, sbc4, sdmmc3,
> > +       pex, owr, afi, csite, pcie_xclk, avpucq = 75, la, irama = 84, iramb,
> > +       iramc, iramd, cram2, audio_2x, clk_d, csus = 92, cdev1, cdev2,
> > +       uartb = 96, vfir, spdif_in, spdif_out, vi, vi_sensor, tvo, cve,
> > +       osc, clk_32k, clk_m, sclk, cclk, hclk, pclk, blink, pll_a, pll_a_out0,
> > +       pll_c, pll_c_out1, pll_d, pll_d_out0, pll_e, pll_m, pll_m_out1,
> > +       pll_p, pll_p_out1, pll_p_out2, pll_p_out3, pll_p_out4, pll_u,
> > +       pll_x, audio, pll_ref, twd, clk_max,
> > +};
> > +
> Please remove unused constants or register appropriate clocks.

Maybe it makes sense to keep them. When they are in sync with the
devicetree it means we could derive clocks from the devicetree should
we ever want to. However, we could also do this later when we really
need it, so I have no objection in either direction.

Sascha

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