[PATCH] phyCORE-i.MX27: Keep frequency multiplier enabled to be able to do a warmstart

[Teresa Gamez]

Are there any reasons why this patch was not added to the barebox?
It works fine for us.

Teresa 

Am Donnerstag, den 25.11.2010, 17:52 +0100 schrieb Juergen Beisert:
> commit 7d25a0552dd3a4b65412ae1cbf8f9ca8a88b5d27
> Author: Juergen Beisert <jbe at pengutronix.de>
> Date:   Thu Nov 25 17:49:11 2010 +0100
> 
>     Keep frequency multiplier enabled to be able to do a warmstart
>     
>     The wachtdog's reset does only reset the ARM core, not the whole silicon.
>     But the PLLs seems to do some strange things: It seems they switch back to
>     the low frequency reference when the watchdog barks. But in the case the
>     frequency multiplier is off (not used due to 26 MHz reference usage) the
>     machine stops, because the PLLs are stopping due to the lack of a reference
>     frequency. As the power on reset will set the FPM_EN bit again, a power cycle
>     brings the machine back to life.
>     By keeping the frequency multiplier enabled, also a warmstart triggered by the
>     watchdog can restart the machine now.
>     
>     Signed-off-by: Juergen Beisert <jbe at pengutronix.de>
> 
> diff --git a/arch/arm/boards/pcm038/pll.h b/arch/arm/boards/pcm038/pll.h
> index 13a7989..15b94cf 100644
> --- a/arch/arm/boards/pcm038/pll.h
> +++ b/arch/arm/boards/pcm038/pll.h
> @@ -36,6 +36,7 @@
>  		CSCR_MCU_SEL | /* 26 MHz reference */ \
>  		CSCR_ARM_DIV(0) | /* CPU runs at MPLL/3 clock */ \
>  		CSCR_AHB_DIV(1) | /* AHB runs at MPLL/6 clock */ \
> +		CSCR_FPM_EN | \
>  		CSCR_SPEN |		\
>  		CSCR_MPEN)
>  
> @@ -51,6 +52,7 @@
>  		CSCR_ARM_SRC_MPLL | /* use main MPLL clock */ \
>  		CSCR_ARM_DIV(0) | /* CPU run at full MPLL clock */ \
>  		CSCR_AHB_DIV(1) | /* AHB runs at MPLL/6 clock */ \
> +		CSCR_FPM_EN | /* do not disable it! */ \
>  		CSCR_SPEN |		\
>  		CSCR_MPEN)
>  
>