[PATCH 6/8] omap36x: Perform basic clock initialization
Sanjeev Premi
premi at ti.com
Mon Jan 3 09:24:53 EST 2011
This patch adds the basic clock initizlization for OMAP36XX.
Portion of this patch is based on commit:
29587220909e639cda4fb5a35cb5bf33aba242b9
at http://arago-project.org/git/projects/?p=x-load-omap3.git
Signed-off-by: Sanjeev Premi <premi at ti.com>
---
arch/arm/mach-omap/omap3_clock.c | 32 ++++++++++++++++++++++++++------
1 files changed, 26 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mach-omap/omap3_clock.c b/arch/arm/mach-omap/omap3_clock.c
index 492e309..1668369 100644
--- a/arch/arm/mach-omap/omap3_clock.c
+++ b/arch/arm/mach-omap/omap3_clock.c
@@ -554,6 +554,7 @@ static void init_iva_dpll_36x(u32 cpu_rev, u32 clk_sel)
void prcm_init(void)
{
u32 osc_clk = 0, sys_clkin_sel = 0;
+ u32 cpu_type = get_cpu_type();
u32 cpu_rev = get_cpu_rev();
u32 clk_index;
@@ -565,8 +566,15 @@ void prcm_init(void)
/* set input crystal speed */
sr32(PRM_REG(CLKSEL), 0, 3, sys_clkin_sel);
- /* If the input clock is greater than 19.2M always divide/2 */
- if (sys_clkin_sel > 2) {
+ /*
+ * OMAP3430:
+ * If the input clock is greater than 19.2M always divide/2
+ * OMAP3630:
+ * DDR corruption was observed on exit from OFF mode, when
+ * sys clock is lower than 26M. As workaround, it is maintained
+ * at 26M.
+ */
+ if ((cpu_type != CPU_3630) && (sys_clkin_sel > 2)) {
/* input clock divider */
sr32(PRM_REG(CLKSRC_CTRL), 6, 2, 2);
clk_index = sys_clkin_sel / 2;
@@ -582,10 +590,22 @@ void prcm_init(void)
sr32(CM_REG(CLKEN_PLL_MPU), 0, 3, PLL_LOW_POWER_BYPASS);
wait_on_value((0x1 << 0), 0, CM_REG(IDLEST_PLL_MPU), LDELAY);
- init_core_dpll_34x(cpu_rev, clk_index);
- init_per_dpll_34x(cpu_rev, clk_index);
- init_mpu_dpll_34x(cpu_rev, clk_index);
- init_iva_dpll_34x(cpu_rev, clk_index);
+ if (cpu_type == CPU_3430) {
+ init_core_dpll_34x(cpu_rev, clk_index);
+ init_per_dpll_34x(cpu_rev, clk_index);
+ init_mpu_dpll_34x(cpu_rev, clk_index);
+ init_iva_dpll_34x(cpu_rev, clk_index);
+ }
+ else if (cpu_type == CPU_3630) {
+ init_core_dpll_36x(cpu_rev, clk_index);
+ init_per_dpll_36x(cpu_rev, clk_index);
+ init_mpu_dpll_36x(cpu_rev, clk_index);
+ init_iva_dpll_36x(cpu_rev, clk_index);
+ }
+ else {
+ /* Unknown CPU */
+ hang();
+ }
/*
* Clock configuration complete. Lock MPU PLL.
--
1.7.2.2
More information about the barebox
mailing list