[PATCH] ARM pcm043: New NOR Flash CS0 values

[Teresa Gámez]

Set new CS0 values for new NOR-Flashes (28F256P33BF).
These values also work with older flashes (28F256P33B).

Also removed unnecessary setup of CSO in the core_init call.

Signed-off-by: Teresa Gámez <t.gamez at phytec.de>
---
 arch/arm/boards/pcm043/pcm043.c |   10 +++-------
 1 files changed, 3 insertions(+), 7 deletions(-)

diff --git a/arch/arm/boards/pcm043/pcm043.c b/arch/arm/boards/pcm043/pcm043.c
index 966899a..fbe8cea 100644
--- a/arch/arm/boards/pcm043/pcm043.c
+++ b/arch/arm/boards/pcm043/pcm043.c
@@ -124,9 +124,9 @@ static int imx35_devices_init(void)
 	uint32_t reg;
 
 	/* CS0: Nor Flash */
-	writel(0x0000cf03, CSCR_U(0));
-	writel(0x10000d03, CSCR_L(0));
-	writel(0x00720900, CSCR_A(0));
+	writel(0x22C0CF00, CSCR_U(0));
+	writel(0x75000D01, CSCR_L(0));
+	writel(0x00000900, CSCR_A(0));
 
 	led_gpio_register(&led0);
 
@@ -277,10 +277,6 @@ static int pcm043_core_setup(void)
 	writel(0x0, IMX_MAX_BASE + 0xc00);	/* for M4 */
 	writel(0x0, IMX_MAX_BASE + 0xd00);	/* for M5 */
 
-	writel(0x0000DCF6, CSCR_U(0)); /* CS0: NOR Flash */
-	writel(0x444A4541, CSCR_L(0));
-	writel(0x44443302, CSCR_A(0));
-
 	/*
 	 * M3IF Control Register (M3IFCTL)
 	 * MRRP[0] = L2CC0 not on priority list (0 << 0)	= 0x00000000
-- 
1.7.0.4