uart interface issues (fixed)

[Oleksij Rempel]

Am 28.04.2013 16:17, schrieb Oleksij Rempel:
> Am 28.04.2013 13:38, schrieb Adrian Chadd:
>> .. is it triggering BREAK interrupts or something?
>
> I don't know, there is no serial output on this stage. JTAG may help if
> the protocol is some how similar to EJTAG. Are there any documentation
> about Xtensa dubug interface ;)?
> I will need to dig in it, but not this week.
>
>
>> That may be something that the boot ROM code interprets as a magical
>> "don't start" sequence or something.

So, this issue is fixed now.

ttl TX >------[2K]--------o RX pin on AR7010
                      |----[4K pull up]---< 3,3V

In attachment are pictures from my setup ;)

-- 
Regards,
Oleksij
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