[PATCH v5 5/6] wifi: ath11k: Add support for MHI bandwidth scaling
Krishna Chaitanya Chundru
krishna.chundru at oss.qualcomm.com
Tue Sep 1 22:30:51 PDT 2026
On 9/1/2026 8:15 PM, Neil Armstrong wrote:
> Hi,
>
> On 8/19/26 15:25, Krishna Chaitanya Chundru wrote:
>> From: Miaoqing Pan <quic_miaoqing at quicinc.com>
>>
>> Add support for MHI bandwidth scaling, which will reduce power consumption
>> if WLAN operates with lower bandwidth. This feature is only enabled for
>> QCA6390.
>>
>> Bandwidth scaling is initiated by the endpoint firmware based upon the
>> bandwidth requirements, if there is high bandwidth data endpoint requests
>> for higher data rates or if there is less bandwidth they request for lower
>> data rates to reduce power. Endpoint initiates this through MHI protocol.
>>
>> Tested-on: WCN6855 hw2.1 PCI
>> WLAN.HSP.1.1-04546-QCAHSPSWPL_V1_V2_SILICONZ_IOE-1
>
> Somehow unrelated, but I added this to the ath12k to test on an WCN785x and
> I just
> got a single event to set the speed to 5GT/s and no further event whatever
> the state
> of the Wireless link is.
>
> Is there anything required on the ath12k side to allow lowering the speed to
> 2.5GT/s ?
some wifi device has some limitation due to that they will stay in gen2 only.
- Krishna Chaitanya.
>
> Thanks,
> Neil
>
>>
>> Signed-off-by: Miaoqing Pan <quic_miaoqing at quicinc.com>
>> Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru at oss.qualcomm.com>
>> ---
>> drivers/net/wireless/ath/ath11k/mhi.c | 38
>> +++++++++++++++++++++++++++++++++++
>> 1 file changed, 38 insertions(+)
>>
>> diff --git a/drivers/net/wireless/ath/ath11k/mhi.c
>> b/drivers/net/wireless/ath/ath11k/mhi.c
>> index a6c9ff112c68..9bff4c4bca3b 100644
>> --- a/drivers/net/wireless/ath/ath11k/mhi.c
>> +++ b/drivers/net/wireless/ath/ath11k/mhi.c
>> @@ -20,6 +20,7 @@
>> #define MHI_TIMEOUT_DEFAULT_MS 20000
>> #define RDDM_DUMP_SIZE 0x420000
>> #define MHI_CB_INVALID 0xff
>> +#define MHI_BW_SCALE_CHAN_DB 126
>> static const struct mhi_channel_config ath11k_mhi_channels_qca6390[] = {
>> {
>> @@ -71,6 +72,17 @@ static struct mhi_event_config
>> ath11k_mhi_events_qca6390[] = {
>> .client_managed = false,
>> .offload_channel = false,
>> },
>> + {
>> + .num_elements = 8,
>> + .irq_moderation_ms = 0,
>> + .irq = 1,
>> + .mode = MHI_DB_BRST_DISABLE,
>> + .data_type = MHI_ER_BW_SCALE,
>> + .priority = 2,
>> + .hardware_event = false,
>> + .client_managed = false,
>> + .offload_channel = false,
>> + },
>> };
>> static const struct mhi_controller_config ath11k_mhi_config_qca6390 = {
>> @@ -311,6 +323,30 @@ static void ath11k_mhi_op_write_reg(struct
>> mhi_controller *mhi_cntrl,
>> writel(val, addr);
>> }
>> +static int ath11k_mhi_op_get_misc_doorbell(struct mhi_controller
>> *mhi_cntrl,
>> + enum mhi_er_data_type type)
>> +{
>> + if (type == MHI_ER_BW_SCALE)
>> + return MHI_BW_SCALE_CHAN_DB;
>> +
>> + return -EOPNOTSUPP;
>> +}
>> +
>> +static int ath11k_mhi_op_bw_scale(struct mhi_controller *mhi_cntrl,
>> + struct mhi_link_info *link_info)
>> +{
>> + enum pci_bus_speed speed =
>> pci_lnkctl2_bus_speed(link_info->target_link_speed);
>> + struct ath11k_base *ab = dev_get_drvdata(mhi_cntrl->cntrl_dev);
>> + struct pci_dev *pci_dev = to_pci_dev(ab->dev);
>> + struct pci_dev *pdev;
>> +
>> + pdev = pci_upstream_bridge(pci_dev);
>> + if (!pdev)
>> + return -ENODEV;
>> +
>> + return pcie_set_target_speed(pdev, speed, true);
>> +}
>> +
>> static int ath11k_mhi_read_addr_from_dt(struct mhi_controller *mhi_ctrl)
>> {
>> struct device_node *np;
>> @@ -387,6 +423,8 @@ int ath11k_mhi_register(struct ath11k_pci *ab_pci)
>> mhi_ctrl->status_cb = ath11k_mhi_op_status_cb;
>> mhi_ctrl->read_reg = ath11k_mhi_op_read_reg;
>> mhi_ctrl->write_reg = ath11k_mhi_op_write_reg;
>> + mhi_ctrl->bw_scale = ath11k_mhi_op_bw_scale;
>> + mhi_ctrl->get_misc_doorbell = ath11k_mhi_op_get_misc_doorbell;
>> switch (ab->hw_rev) {
>> case ATH11K_HW_QCN9074_HW10:
>>
>
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