From jjohnson at codeaurora.org  Mon May  3 18:24:54 2021
From: jjohnson at codeaurora.org (jjohnson at codeaurora.org)
Date: Mon, 03 May 2021 10:24:54 -0700
Subject: [PATCH v2 1/3] nl80211: Add support for beacon tx mode
In-Reply-To: <1619696874-30072-2-git-send-email-mkenna@codeaurora.org>
References: <1619696874-30072-1-git-send-email-mkenna@codeaurora.org>
 <1619696874-30072-2-git-send-email-mkenna@codeaurora.org>
Message-ID: <445ba573b519b9434d0e009eb9ff6f45@codeaurora.org>

On 2021-04-29 04:47, Maharaja Kennadyrajan wrote:
[..snip..]
> +/**
> + * enum nl80211_beacon_tx_mode - Beacon Tx Mode enum.
> + *      Used to configure beacon staggered mode or beacon burst mode.
> + */
> +enum nl80211_beacon_tx_mode {
> +	NL80211_BEACON_STAGGERED_MODE = 1,
> +	NL80211_BEACON_BURST_MODE = 2,
> +};
> +
[..snip..]
> @@ -5330,6 +5331,10 @@ static int nl80211_start_ap(struct sk_buff *skb,
> struct genl_info *info)
>  	params.dtim_period =
>  		nla_get_u32(info->attrs[NL80211_ATTR_DTIM_PERIOD]);
> 
> +	if (info->attrs[NL80211_ATTR_BEACON_TX_MODE])
> +		params.beacon_tx_mode =
> +
> nla_get_u32(info->attrs[NL80211_ATTR_BEACON_TX_MODE]);
> +

Note that in the case where NL80211_ATTR_BEACON_TX_MODE is not specified 
that
beacon_tx_mode will be zero, which is not a valid nl80211_beacon_tx_mode 
enumeration.

Should you renumber the nl80211_beacon_tx_mode enumerations so that the 
default
mode has a value of 0? Or add NL80211_BEACON_DEFAULT_MODE = 0 and allow 
the driver
to select a default mode?



From hemantk at codeaurora.org  Tue May  4 00:55:59 2021
From: hemantk at codeaurora.org (Hemant Kumar)
Date: Mon, 3 May 2021 16:55:59 -0700
Subject: [PATCH] mhi: add MHI_STATE_M2 to resume success criteria
In-Reply-To: <20210420035339.282963-1-bqiang@codeaurora.org>
References: <20210420035339.282963-1-bqiang@codeaurora.org>
Message-ID: <11a51914-141d-24b6-cffa-4eb093aaea7f@codeaurora.org>



On 4/19/21 8:53 PM, Baochen Qiang wrote:
> During system resume, mhi driver triggers M3->M0 transition and then waits
> for target device to enter M0 state. Once done, the device queues a state
> change event into ctrl event ring and notify mhi dirver by raising an
> interrupt, where a tasklet is scheduled to process this event. In most cases,
> the taklet is served timely and wait operation succeeds.
> 
> However, there are cases where CPU is busy and can not serve this tasklet
> for some time. Once delay goes long enough, the device moves itself to M1
> state and also interrupts mhi driver after inserting a new state change
> event to ctrl ring. Later CPU finally has time to process the ring, however
> there are two events in it now:
> 	1. for M3->M0 event, which is processed first as queued first,
> 	   tasklet handler updates device state to M0 and wakes up the task,
> 	   i.e., the mhi driver.
> 	2. for M0->M1 event, which is processed later, tasklet handler
> 	   triggers M1->M2 transition and updates device state to M2 directly,
> 	   then wakes up the mhi driver(if still sleeping on this wait queue).
> Note that although mhi driver has been woken up while processing the first
> event, it may still has no chance to run before the second event is processed.
> In other words, mhi driver has to keep waiting till timeout cause the M0 state
> has been missed.
> 
> kernel log here:
> ...
> Apr 15 01:45:14 test-NUC8i7HVK kernel: [ 4247.911251] mhi 0000:06:00.0: Entered with PM state: M3, MHI state: M3
> Apr 15 01:45:14 test-NUC8i7HVK kernel: [ 4247.917762] mhi 0000:06:00.0: State change event to state: M0
> Apr 15 01:45:14 test-NUC8i7HVK kernel: [ 4247.917767] mhi 0000:06:00.0: State change event to state: M1
> Apr 15 01:45:14 test-NUC8i7HVK kernel: [ 4338.788231] mhi 0000:06:00.0: Did not enter M0 state, MHI state: M2, PM state: M2
> ...
> 
> Fix this issue by simply adding M2 as a valid state for resume.
> 
> Tested-on: WCN6855 hw2.0 PCI WLAN.HSP.1.1-01720.1-QCAHSPSWPL_V1_V2_SILICONZ_LITE-1
> 
> Signed-off-by: Baochen Qiang <bqiang at codeaurora.org>

nice explanation of the issue!

Reviewed-by: Hemant Kumar <hemantk at codeaurora.org>

-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project


From robert.marko at sartura.hr  Tue May  4 17:35:30 2021
From: robert.marko at sartura.hr (Robert Marko)
Date: Tue, 4 May 2021 18:35:30 +0200
Subject: IPQ6018 issues
Message-ID: <CA+HBbNHYiULJ2T1Q3dmmXZSYb3gLajr2m86HTvCO-ud0GwkaZA@mail.gmail.com>

Hi,

I am trying to use ath11k on multiple IPQ6018 and IPQ6010 boards,
unfortunately, they will all fail like this:
>
> # echo c000000.wifi > /sys/bus/platform/drivers/ath11k/bind
> [   12.417214] ath11k c000000.wifi: event type: 0
> [   12.417557] ath11k c000000.wifi: qmi ignore invalid mem req type 3
> [   12.420605] ath11k c000000.wifi: event type: 2
> [   12.427191] ath11k c000000.wifi: event type: 3
> [   12.431312] ath11k c000000.wifi: chip_id 0x0 chip_family 0x4 board_id 0xff soc_id 0xffffffff
> [   12.435626] ath11k c000000.wifi: fw_version 0x240606c6 fw_build_timestamp 2021-02-12 03:17 fw_build_id QC_IMAGE_VERSION_STRING=WLAN.HK.2.4.0.1-01734-QCAHKSWPL_SILICONZ-1
> [   12.447560] ath11k c000000.wifi: event type: 4
> [   12.459215] ath11k c000000.wifi: ATH11K_QMI_EVENT_FW_READY
> [   12.463551] ath11k c000000.wifi: ath11k_core_qmi_firmware_ready
> [   12.469013] ath11k c000000.wifi: ath11k_core_qmi_firmware_ready start
> [   12.474900] ath11k c000000.wifi: ath11k_ce_init_pipes pass
> # [   12.491124] ath11k c000000.wifi: ath11k_crypto_mode: 0
>
> Format: Log Type - Time(microsec) - Message - Optional Info
> Log Type: B - Since Boot(Power On Reset),  D - Delta,  S - Statistic
> S - QC_IMAGE_VERSION_STRING=BOOT.XF.0.3-00098-IPQ60xxLZB-1
> S - IMAGE_VARIANT_STRING=IPQ6018LA
> S - OEM_IMAGE_VERSION_STRING=crm-ubuntu121
> S - Boot Interface: SPI
> S - Secure Boot: Off
> S - Boot Config @ 0x000a602c = 0x000002e1
> S - JTAG ID @ 0x000a607c = 0x0013a0e1
> S - OEM ID @ 0x000a6080 = 0x00000000
> S - Serial Number @ 0x000a4128 = 0xd92ca102
> S - OEM Config Row 0 @ 0x000a4188 = 0x0000000000000000
> S - OEM Config Row 1 @ 0x000a4190 = 0x0000000000000000
> S - Feature Config Row 0 @ 0x000a4130 = 0x0000000008000001
> S - Feature Config Row 1 @ 0x000a4138 = 0x02c3e83383000009
> S - PBL Patch Ver: 1
> S - I-cache: On
> S - D-cache: On
> B -      3413 - PBL, Start
> B -       592 - bootable_media_detect_entry, Start
> B -      4339 - bootable_media_detect_success, Start
> B -      4435 - elf_loader_entry, Start
> B -      4607 - auth_hash_seg_entry, Start
> B -     10854 - auth_hash_seg_exit, Start
> B -     11350 - elf_segs_hash_verify_entry, Start
> B -    357983 - elf_segs_hash_verify_exit, Start
> B -    362173 - auth_xbl_sec_hash_seg_entry, Start
> B -    362318 - auth_xbl_sec_hash_seg_exit, Start
> B -    368868 - xbl_sec_segs_hash_verify_entry, Start
> B -    368869 - xbl_sec_segs_hash_verify_exit, Start
> B -    369798 - PBL, End
> B -    296002 - SBL1, Start
> B -    435814 - GCC [RstStat:0x2, RstDbg:0x420100] WDog Stat : 0x4
> B -    438254 - clock_init, Start
> D -      3812 - clock_init, Delta
> B -    447862 - boot_flash_init, Start
> D -      8082 - boot_flash_init, Delta
> B -    458201 - sbl1_ddr_set_default_params, Start
> D -       274 - sbl1_ddr_set_default_params, Delta
> B -    464820 - boot_config_data_table_init, Start
> D -      1891 - boot_config_data_table_init, Delta - (575 Bytes)
> B -    473970 - CDT Version:2,Platform ID:8,Major ID:3,Minor ID:0,Subtype:0
> B -    479490 - Image Load, Start
> D -      6619 - OEM_MISC Image Loaded, Delta - (0 Bytes)
> B -    488823 - Image Load, Start
> D -      5063 - PMIC Image Loaded, Delta - (0 Bytes)
> B -    496692 - sbl1_ddr_set_params, Start
> B -    501694 - CPR configuration: 0x366
> B -    504897 - Pre_DDR_clock_init, Start
> D -       183 - Pre_DDR_clock_init, Delta
> D -         0 - sbl1_ddr_set_params, Delta


I added most of the prints to figure out where it dies.
If cold-boot calibration is enabled then it will die on the
ath11k_qmi_process_coldboot_calibration(), to be exact on the
>
> ret = ath11k_qmi_wlanfw_mode_send(ab, ATH11K_FIRMWARE_MODE_COLD_BOOT);


But, if cold-boot calibration is disabled then ti will fail in
ath11k_core_qmi_firmware_ready at or after ath11k_crypto_mode switch.

A big issue is that it will crash the board and it will get stuck in
SBL, only removing the power will help.

The hardware I tried on is:
* Wallys CP01-C1
* Wallys CP03-C1
* Alfa AP1800C-AX PRO

I also tried fw versions from 2.1.0.1 to 2.5.0.1-R2

Does anybody have an idea how to solve this?

-- 
Robert Marko
Staff Embedded Linux Engineer
Sartura Ltd.
Lendavska ulica 16a
10000 Zagreb, Croatia
Email: robert.marko at sartura.hr
Web: www.sartura.hr


From john at phrozen.org  Tue May  4 17:50:15 2021
From: john at phrozen.org (John Crispin)
Date: Tue, 4 May 2021 18:50:15 +0200
Subject: IPQ6018 issues
In-Reply-To: <CA+HBbNHYiULJ2T1Q3dmmXZSYb3gLajr2m86HTvCO-ud0GwkaZA@mail.gmail.com>
References: <CA+HBbNHYiULJ2T1Q3dmmXZSYb3gLajr2m86HTvCO-ud0GwkaZA@mail.gmail.com>
Message-ID: <724315d2-c542-617a-cfce-001c7e1b0f74@phrozen.org>


On 04.05.21 18:35, Robert Marko wrote:
> Hi,
>
> I am trying to use ath11k on multiple IPQ6018 and IPQ6010 boards,
> unfortunately, they will all fail like this:

I have observed the same on ipq807x. This crash happens when the driver 
does the first access to AHB memory if i recall correctly

 ??? John


>> # echo c000000.wifi > /sys/bus/platform/drivers/ath11k/bind
>> [   12.417214] ath11k c000000.wifi: event type: 0
>> [   12.417557] ath11k c000000.wifi: qmi ignore invalid mem req type 3
>> [   12.420605] ath11k c000000.wifi: event type: 2
>> [   12.427191] ath11k c000000.wifi: event type: 3
>> [   12.431312] ath11k c000000.wifi: chip_id 0x0 chip_family 0x4 board_id 0xff soc_id 0xffffffff
>> [   12.435626] ath11k c000000.wifi: fw_version 0x240606c6 fw_build_timestamp 2021-02-12 03:17 fw_build_id QC_IMAGE_VERSION_STRING=WLAN.HK.2.4.0.1-01734-QCAHKSWPL_SILICONZ-1
>> [   12.447560] ath11k c000000.wifi: event type: 4
>> [   12.459215] ath11k c000000.wifi: ATH11K_QMI_EVENT_FW_READY
>> [   12.463551] ath11k c000000.wifi: ath11k_core_qmi_firmware_ready
>> [   12.469013] ath11k c000000.wifi: ath11k_core_qmi_firmware_ready start
>> [   12.474900] ath11k c000000.wifi: ath11k_ce_init_pipes pass
>> # [   12.491124] ath11k c000000.wifi: ath11k_crypto_mode: 0
>>
>> Format: Log Type - Time(microsec) - Message - Optional Info
>> Log Type: B - Since Boot(Power On Reset),  D - Delta,  S - Statistic
>> S - QC_IMAGE_VERSION_STRING=BOOT.XF.0.3-00098-IPQ60xxLZB-1
>> S - IMAGE_VARIANT_STRING=IPQ6018LA
>> S - OEM_IMAGE_VERSION_STRING=crm-ubuntu121
>> S - Boot Interface: SPI
>> S - Secure Boot: Off
>> S - Boot Config @ 0x000a602c = 0x000002e1
>> S - JTAG ID @ 0x000a607c = 0x0013a0e1
>> S - OEM ID @ 0x000a6080 = 0x00000000
>> S - Serial Number @ 0x000a4128 = 0xd92ca102
>> S - OEM Config Row 0 @ 0x000a4188 = 0x0000000000000000
>> S - OEM Config Row 1 @ 0x000a4190 = 0x0000000000000000
>> S - Feature Config Row 0 @ 0x000a4130 = 0x0000000008000001
>> S - Feature Config Row 1 @ 0x000a4138 = 0x02c3e83383000009
>> S - PBL Patch Ver: 1
>> S - I-cache: On
>> S - D-cache: On
>> B -      3413 - PBL, Start
>> B -       592 - bootable_media_detect_entry, Start
>> B -      4339 - bootable_media_detect_success, Start
>> B -      4435 - elf_loader_entry, Start
>> B -      4607 - auth_hash_seg_entry, Start
>> B -     10854 - auth_hash_seg_exit, Start
>> B -     11350 - elf_segs_hash_verify_entry, Start
>> B -    357983 - elf_segs_hash_verify_exit, Start
>> B -    362173 - auth_xbl_sec_hash_seg_entry, Start
>> B -    362318 - auth_xbl_sec_hash_seg_exit, Start
>> B -    368868 - xbl_sec_segs_hash_verify_entry, Start
>> B -    368869 - xbl_sec_segs_hash_verify_exit, Start
>> B -    369798 - PBL, End
>> B -    296002 - SBL1, Start
>> B -    435814 - GCC [RstStat:0x2, RstDbg:0x420100] WDog Stat : 0x4
>> B -    438254 - clock_init, Start
>> D -      3812 - clock_init, Delta
>> B -    447862 - boot_flash_init, Start
>> D -      8082 - boot_flash_init, Delta
>> B -    458201 - sbl1_ddr_set_default_params, Start
>> D -       274 - sbl1_ddr_set_default_params, Delta
>> B -    464820 - boot_config_data_table_init, Start
>> D -      1891 - boot_config_data_table_init, Delta - (575 Bytes)
>> B -    473970 - CDT Version:2,Platform ID:8,Major ID:3,Minor ID:0,Subtype:0
>> B -    479490 - Image Load, Start
>> D -      6619 - OEM_MISC Image Loaded, Delta - (0 Bytes)
>> B -    488823 - Image Load, Start
>> D -      5063 - PMIC Image Loaded, Delta - (0 Bytes)
>> B -    496692 - sbl1_ddr_set_params, Start
>> B -    501694 - CPR configuration: 0x366
>> B -    504897 - Pre_DDR_clock_init, Start
>> D -       183 - Pre_DDR_clock_init, Delta
>> D -         0 - sbl1_ddr_set_params, Delta
>
> I added most of the prints to figure out where it dies.
> If cold-boot calibration is enabled then it will die on the
> ath11k_qmi_process_coldboot_calibration(), to be exact on the
>> ret = ath11k_qmi_wlanfw_mode_send(ab, ATH11K_FIRMWARE_MODE_COLD_BOOT);
>
> But, if cold-boot calibration is disabled then ti will fail in
> ath11k_core_qmi_firmware_ready at or after ath11k_crypto_mode switch.
>
> A big issue is that it will crash the board and it will get stuck in
> SBL, only removing the power will help.
>
> The hardware I tried on is:
> * Wallys CP01-C1
> * Wallys CP03-C1
> * Alfa AP1800C-AX PRO
>
> I also tried fw versions from 2.1.0.1 to 2.5.0.1-R2
>
> Does anybody have an idea how to solve this?
>


From quic_jhugo at quicinc.com  Tue May  4 18:22:28 2021
From: quic_jhugo at quicinc.com (Jeffrey Hugo)
Date: Tue, 4 May 2021 11:22:28 -0600
Subject: [PATCH v1 1/6] bus: mhi: core: Set BHI/BHIe offsets on power up
 preparation
In-Reply-To: <1618598825-18629-2-git-send-email-bbhatt@codeaurora.org>
References: <1618598825-18629-1-git-send-email-bbhatt@codeaurora.org>
 <1618598825-18629-2-git-send-email-bbhatt@codeaurora.org>
Message-ID: <5f0001da-bc1a-5649-ef72-1fbadd5b44ec@quicinc.com>

On 4/16/2021 12:47 PM, Bhaumik Bhatt wrote:
> Set the BHI and/or BHIe offsets in mhi_prepare_for_power_up(),
> rearrange the function, and remove the equivalent from
> mhi_async_power_up(). This helps consolidate multiple checks
> in different parts of the driver and can help MHI fail early on
> before power up begins if the offsets are not read correctly.
> 
> Signed-off-by: Bhaumik Bhatt <bbhatt at codeaurora.org>
> ---

Reviewed-by: Jeffrey Hugo <quic_jhugo at quicinc.com>



From quic_jhugo at quicinc.com  Tue May  4 18:26:08 2021
From: quic_jhugo at quicinc.com (Jeffrey Hugo)
Date: Tue, 4 May 2021 11:26:08 -0600
Subject: [PATCH v1 2/6] bus: mhi: core: Set BHI and BHIe pointers to NULL
 in clean-up
In-Reply-To: <1618598825-18629-3-git-send-email-bbhatt@codeaurora.org>
References: <1618598825-18629-1-git-send-email-bbhatt@codeaurora.org>
 <1618598825-18629-3-git-send-email-bbhatt@codeaurora.org>
Message-ID: <55df55c8-5799-e581-1dbb-8291243bf37d@quicinc.com>

On 4/16/2021 12:47 PM, Bhaumik Bhatt wrote:
> Set the BHI and BHIe pointers to NULL as part of clean-up. This
> makes sure that stale pointers are not accessed after powering
> MHI down.
> 
> Suggested-by: Hemant Kumar <hemantk at codeaurora.org>
> Signed-off-by: Bhaumik Bhatt <bbhatt at codeaurora.org>
> ---

Reviewed-by: Jeffrey Hugo <quic_jhugo at quicinc.com>


From quic_jhugo at quicinc.com  Tue May  4 18:28:26 2021
From: quic_jhugo at quicinc.com (Jeffrey Hugo)
Date: Tue, 4 May 2021 11:28:26 -0600
Subject: [PATCH v1 3/6] bus: mhi: Add MMIO region length to controller
 structure
In-Reply-To: <1618598825-18629-4-git-send-email-bbhatt@codeaurora.org>
References: <1618598825-18629-1-git-send-email-bbhatt@codeaurora.org>
 <1618598825-18629-4-git-send-email-bbhatt@codeaurora.org>
Message-ID: <83589a09-e1a0-4611-a844-0ea52ca036b9@quicinc.com>

On 4/16/2021 12:47 PM, Bhaumik Bhatt wrote:
> Make controller driver specify the MMIO register region length
> for range checking of BHI or BHIe space. This can help validate
> that offsets are in acceptable memory region or not and avoid any
> boot-up issues due to BHI or BHIe memory accesses.
> 
> Signed-off-by: Bhaumik Bhatt <bbhatt at codeaurora.org>
> ---
>   include/linux/mhi.h | 2 ++
>   1 file changed, 2 insertions(+)
> 
> diff --git a/include/linux/mhi.h b/include/linux/mhi.h
> index 944aa3a..ad53b24 100644
> --- a/include/linux/mhi.h
> +++ b/include/linux/mhi.h
> @@ -293,6 +293,7 @@ struct mhi_controller_config {
>    * @mhi_dev: MHI device instance for the controller
>    * @debugfs_dentry: MHI controller debugfs directory
>    * @regs: Base address of MHI MMIO register space (required)
> + * @reg_len: Length of the MHI MMIO region (required)
>    * @bhi: Points to base of MHI BHI register space
>    * @bhie: Points to base of MHI BHIe register space
>    * @wake_db: MHI WAKE doorbell register address
> @@ -375,6 +376,7 @@ struct mhi_controller {
>   	struct mhi_device *mhi_dev;
>   	struct dentry *debugfs_dentry;
>   	void __iomem *regs;
> +	size_t reg_len;

Didn't Mani make sure this struct was packed using pahole when things 
were first upstreamed?  Feels like sticking this in the middle of a 
bunch of void * entries will add some padding.  Am I wrong?

>   	void __iomem *bhi;
>   	void __iomem *bhie;
>   	void __iomem *wake_db;
> 



From quic_jhugo at quicinc.com  Tue May  4 18:30:59 2021
From: quic_jhugo at quicinc.com (Jeffrey Hugo)
Date: Tue, 4 May 2021 11:30:59 -0600
Subject: [PATCH v1 6/6] bus: mhi: core: Add range checks for BHI and BHIe
In-Reply-To: <1618598825-18629-7-git-send-email-bbhatt@codeaurora.org>
References: <1618598825-18629-1-git-send-email-bbhatt@codeaurora.org>
 <1618598825-18629-7-git-send-email-bbhatt@codeaurora.org>
Message-ID: <a5e8cd2e-2863-f88b-8344-021d90a68131@quicinc.com>

On 4/16/2021 12:47 PM, Bhaumik Bhatt wrote:
> When obtaining the BHI or BHIe offsets during the power up
> preparation phase, range checks are missing. These can help
> controller drivers avoid accessing any address outside of the
> MMIO region. Ensure that mhi_cntrl->reg_len is set before MHI
> registration as it is a required field and range checks will
> fail without it.
> 
> Signed-off-by: Bhaumik Bhatt <bbhatt at codeaurora.org>
> ---

Reviewed-by: Jeffrey Hugo <quic_jhugo at quicinc.com>



From bbhatt at codeaurora.org  Wed May  5 00:04:12 2021
From: bbhatt at codeaurora.org (Bhaumik Bhatt)
Date: Tue, 04 May 2021 16:04:12 -0700
Subject: [PATCH v1 3/6] bus: mhi: Add MMIO region length to controller
 structure
In-Reply-To: <83589a09-e1a0-4611-a844-0ea52ca036b9@quicinc.com>
References: <1618598825-18629-1-git-send-email-bbhatt@codeaurora.org>
 <1618598825-18629-4-git-send-email-bbhatt@codeaurora.org>
 <83589a09-e1a0-4611-a844-0ea52ca036b9@quicinc.com>
Message-ID: <928a29dca0d2b141d4e21b7878c1c42e@codeaurora.org>

Hi Jeff,

On 2021-05-04 10:28 AM, Jeffrey Hugo wrote:
> On 4/16/2021 12:47 PM, Bhaumik Bhatt wrote:
>> Make controller driver specify the MMIO register region length
>> for range checking of BHI or BHIe space. This can help validate
>> that offsets are in acceptable memory region or not and avoid any
>> boot-up issues due to BHI or BHIe memory accesses.
>> 
>> Signed-off-by: Bhaumik Bhatt <bbhatt at codeaurora.org>
>> ---
>>   include/linux/mhi.h | 2 ++
>>   1 file changed, 2 insertions(+)
>> 
>> diff --git a/include/linux/mhi.h b/include/linux/mhi.h
>> index 944aa3a..ad53b24 100644
>> --- a/include/linux/mhi.h
>> +++ b/include/linux/mhi.h
>> @@ -293,6 +293,7 @@ struct mhi_controller_config {
>>    * @mhi_dev: MHI device instance for the controller
>>    * @debugfs_dentry: MHI controller debugfs directory
>>    * @regs: Base address of MHI MMIO register space (required)
>> + * @reg_len: Length of the MHI MMIO region (required)
>>    * @bhi: Points to base of MHI BHI register space
>>    * @bhie: Points to base of MHI BHIe register space
>>    * @wake_db: MHI WAKE doorbell register address
>> @@ -375,6 +376,7 @@ struct mhi_controller {
>>   	struct mhi_device *mhi_dev;
>>   	struct dentry *debugfs_dentry;
>>   	void __iomem *regs;
>> +	size_t reg_len;
> 
> Didn't Mani make sure this struct was packed using pahole when things
> were first upstreamed?  Feels like sticking this in the middle of a
> bunch of void * entries will add some padding.  Am I wrong?
> 
OK. I missed out on this detail. I can move this size_t entry in v2.
>>   	void __iomem *bhi;
>>   	void __iomem *bhie;
>>   	void __iomem *wake_db;
>> 

Thanks,
Bhaumik
---
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora 
Forum,
a Linux Foundation Collaborative Project


From bbhatt at codeaurora.org  Wed May  5 00:37:55 2021
From: bbhatt at codeaurora.org (Bhaumik Bhatt)
Date: Tue,  4 May 2021 16:37:55 -0700
Subject: [PATCH v2 3/6] bus: mhi: Add MMIO region length to controller
 structure
In-Reply-To: <1620171478-35679-1-git-send-email-bbhatt@codeaurora.org>
References: <1620171478-35679-1-git-send-email-bbhatt@codeaurora.org>
Message-ID: <1620171478-35679-4-git-send-email-bbhatt@codeaurora.org>

Make controller driver specify the MMIO register region length
for range checking of BHI or BHIe space. This can help validate
that offsets are in acceptable memory region or not and avoid any
boot-up issues due to BHI or BHIe memory accesses.

Signed-off-by: Bhaumik Bhatt <bbhatt at codeaurora.org>
---
 include/linux/mhi.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/linux/mhi.h b/include/linux/mhi.h
index 944aa3a..f6901db 100644
--- a/include/linux/mhi.h
+++ b/include/linux/mhi.h
@@ -293,6 +293,7 @@ struct mhi_controller_config {
  * @mhi_dev: MHI device instance for the controller
  * @debugfs_dentry: MHI controller debugfs directory
  * @regs: Base address of MHI MMIO register space (required)
+ * @reg_len: Length of the MHI MMIO region (required)
  * @bhi: Points to base of MHI BHI register space
  * @bhie: Points to base of MHI BHIe register space
  * @wake_db: MHI WAKE doorbell register address
@@ -386,6 +387,7 @@ struct mhi_controller {
 	size_t rddm_size;
 	size_t sbl_size;
 	size_t seg_len;
+	size_t reg_len;
 	struct image_info *fbc_image;
 	struct image_info *rddm_image;
 	struct mhi_chan *mhi_chan;
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project



From bbhatt at codeaurora.org  Wed May  5 00:37:52 2021
From: bbhatt at codeaurora.org (Bhaumik Bhatt)
Date: Tue,  4 May 2021 16:37:52 -0700
Subject: [PATCH v2 0/6] BHI/BHIe improvements for MHI power purposes
Message-ID: <1620171478-35679-1-git-send-email-bbhatt@codeaurora.org>

This patch series improves the power up behavior by allowing MHI host driver to
set BHI and/or BHIe offsets early on in the preparation phase and fail pre-power
up if offsets are not found or not within a limited MMIO region. This also
allows MHI host to clean up the offsets in the unprepare after power down phase.

Going forward, controllers will be required to specify a reg_len field which
will be used to check whether the BHI/BHIe offsets are in range or not.

This series has been tested on X86_64 architecture with the PCI generic driver
as controller and an SDX55 device.

v2:
-Added reviewed-by tags
-Moved reg_len entry in mhi_controller structure to allow for a packed struct

Bhaumik Bhatt (6):
  bus: mhi: core: Set BHI/BHIe offsets on power up preparation
  bus: mhi: core: Set BHI and BHIe pointers to NULL in clean-up
  bus: mhi: Add MMIO region length to controller structure
  ath11k: set register access length for MHI driver
  bus: mhi: pci_generic: Set register access length for MHI driver
  bus: mhi: core: Add range checks for BHI and BHIe

 drivers/bus/mhi/core/init.c           | 58 +++++++++++++++++++++++------------
 drivers/bus/mhi/core/pm.c             | 28 +++--------------
 drivers/bus/mhi/pci_generic.c         |  1 +
 drivers/net/wireless/ath/ath11k/mhi.c |  1 +
 include/linux/mhi.h                   |  2 ++
 5 files changed, 47 insertions(+), 43 deletions(-)

-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project



From bbhatt at codeaurora.org  Wed May  5 00:37:53 2021
From: bbhatt at codeaurora.org (Bhaumik Bhatt)
Date: Tue,  4 May 2021 16:37:53 -0700
Subject: [PATCH v2 1/6] bus: mhi: core: Set BHI/BHIe offsets on power up
 preparation
In-Reply-To: <1620171478-35679-1-git-send-email-bbhatt@codeaurora.org>
References: <1620171478-35679-1-git-send-email-bbhatt@codeaurora.org>
Message-ID: <1620171478-35679-2-git-send-email-bbhatt@codeaurora.org>

Set the BHI and/or BHIe offsets in mhi_prepare_for_power_up(),
rearrange the function, and remove the equivalent from
mhi_async_power_up(). This helps consolidate multiple checks
in different parts of the driver and can help MHI fail early on
before power up begins if the offsets are not read correctly.

Signed-off-by: Bhaumik Bhatt <bbhatt at codeaurora.org>
Reviewed-by: Jeffrey Hugo <quic_jhugo at quicinc.com>
---
 drivers/bus/mhi/core/init.c | 42 +++++++++++++++++++++++-------------------
 drivers/bus/mhi/core/pm.c   | 28 ++++------------------------
 2 files changed, 27 insertions(+), 43 deletions(-)

diff --git a/drivers/bus/mhi/core/init.c b/drivers/bus/mhi/core/init.c
index c81b377..11c7a3d 100644
--- a/drivers/bus/mhi/core/init.c
+++ b/drivers/bus/mhi/core/init.c
@@ -1063,7 +1063,7 @@ EXPORT_SYMBOL_GPL(mhi_free_controller);
 int mhi_prepare_for_power_up(struct mhi_controller *mhi_cntrl)
 {
 	struct device *dev = &mhi_cntrl->mhi_dev->dev;
-	u32 bhie_off;
+	u32 bhi_off, bhie_off;
 	int ret;
 
 	mutex_lock(&mhi_cntrl->pm_mutex);
@@ -1072,29 +1072,36 @@ int mhi_prepare_for_power_up(struct mhi_controller *mhi_cntrl)
 	if (ret)
 		goto error_dev_ctxt;
 
-	/*
-	 * Allocate RDDM table if specified, this table is for debugging purpose
-	 */
-	if (mhi_cntrl->rddm_size) {
-		mhi_alloc_bhie_table(mhi_cntrl, &mhi_cntrl->rddm_image,
-				     mhi_cntrl->rddm_size);
+	ret = mhi_read_reg(mhi_cntrl, mhi_cntrl->regs, BHIOFF, &bhi_off);
+	if (ret) {
+		dev_err(dev, "Error getting BHI offset\n");
+		goto error_reg_offset;
+	}
+	mhi_cntrl->bhi = mhi_cntrl->regs + bhi_off;
 
-		/*
-		 * This controller supports RDDM, so we need to manually clear
-		 * BHIE RX registers since POR values are undefined.
-		 */
+	if (mhi_cntrl->fbc_download || mhi_cntrl->rddm_size) {
 		ret = mhi_read_reg(mhi_cntrl, mhi_cntrl->regs, BHIEOFF,
 				   &bhie_off);
 		if (ret) {
 			dev_err(dev, "Error getting BHIE offset\n");
-			goto bhie_error;
+			goto error_reg_offset;
 		}
-
 		mhi_cntrl->bhie = mhi_cntrl->regs + bhie_off;
+	}
+
+	if (mhi_cntrl->rddm_size) {
+		/*
+		 * This controller supports RDDM, so we need to manually clear
+		 * BHIE RX registers since POR values are undefined.
+		 */
 		memset_io(mhi_cntrl->bhie + BHIE_RXVECADDR_LOW_OFFS,
 			  0, BHIE_RXVECSTATUS_OFFS - BHIE_RXVECADDR_LOW_OFFS +
 			  4);
-
+		/*
+		 * Allocate RDDM table for debugging purpose if specified
+		 */
+		mhi_alloc_bhie_table(mhi_cntrl, &mhi_cntrl->rddm_image,
+				     mhi_cntrl->rddm_size);
 		if (mhi_cntrl->rddm_image)
 			mhi_rddm_prepare(mhi_cntrl, mhi_cntrl->rddm_image);
 	}
@@ -1103,11 +1110,8 @@ int mhi_prepare_for_power_up(struct mhi_controller *mhi_cntrl)
 
 	return 0;
 
-bhie_error:
-	if (mhi_cntrl->rddm_image) {
-		mhi_free_bhie_table(mhi_cntrl, mhi_cntrl->rddm_image);
-		mhi_cntrl->rddm_image = NULL;
-	}
+error_reg_offset:
+	mhi_deinit_dev_ctxt(mhi_cntrl);
 
 error_dev_ctxt:
 	mutex_unlock(&mhi_cntrl->pm_mutex);
diff --git a/drivers/bus/mhi/core/pm.c b/drivers/bus/mhi/core/pm.c
index e2e59a3..adf426c 100644
--- a/drivers/bus/mhi/core/pm.c
+++ b/drivers/bus/mhi/core/pm.c
@@ -1066,28 +1066,8 @@ int mhi_async_power_up(struct mhi_controller *mhi_cntrl)
 	if (ret)
 		goto error_setup_irq;
 
-	/* Setup BHI offset & INTVEC */
+	/* Setup BHI INTVEC */
 	write_lock_irq(&mhi_cntrl->pm_lock);
-	ret = mhi_read_reg(mhi_cntrl, mhi_cntrl->regs, BHIOFF, &val);
-	if (ret) {
-		write_unlock_irq(&mhi_cntrl->pm_lock);
-		goto error_bhi_offset;
-	}
-
-	mhi_cntrl->bhi = mhi_cntrl->regs + val;
-
-	/* Setup BHIE offset */
-	if (mhi_cntrl->fbc_download) {
-		ret = mhi_read_reg(mhi_cntrl, mhi_cntrl->regs, BHIEOFF, &val);
-		if (ret) {
-			write_unlock_irq(&mhi_cntrl->pm_lock);
-			dev_err(dev, "Error reading BHIE offset\n");
-			goto error_bhi_offset;
-		}
-
-		mhi_cntrl->bhie = mhi_cntrl->regs + val;
-	}
-
 	mhi_write_reg(mhi_cntrl, mhi_cntrl->bhi, BHI_INTVEC, 0);
 	mhi_cntrl->pm_state = MHI_PM_POR;
 	mhi_cntrl->ee = MHI_EE_MAX;
@@ -1098,7 +1078,7 @@ int mhi_async_power_up(struct mhi_controller *mhi_cntrl)
 	if (!MHI_IN_PBL(current_ee) && current_ee != MHI_EE_AMSS) {
 		dev_err(dev, "Not a valid EE for power on\n");
 		ret = -EIO;
-		goto error_bhi_offset;
+		goto error_async_power_up;
 	}
 
 	state = mhi_get_mhi_state(mhi_cntrl);
@@ -1117,7 +1097,7 @@ int mhi_async_power_up(struct mhi_controller *mhi_cntrl)
 		if (!ret) {
 			ret = -EIO;
 			dev_info(dev, "Failed to reset MHI due to syserr state\n");
-			goto error_bhi_offset;
+			goto error_async_power_up;
 		}
 
 		/*
@@ -1139,7 +1119,7 @@ int mhi_async_power_up(struct mhi_controller *mhi_cntrl)
 
 	return 0;
 
-error_bhi_offset:
+error_async_power_up:
 	mhi_deinit_free_irq(mhi_cntrl);
 
 error_setup_irq:
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project



From bbhatt at codeaurora.org  Wed May  5 00:37:58 2021
From: bbhatt at codeaurora.org (Bhaumik Bhatt)
Date: Tue,  4 May 2021 16:37:58 -0700
Subject: [PATCH v2 6/6] bus: mhi: core: Add range checks for BHI and BHIe
In-Reply-To: <1620171478-35679-1-git-send-email-bbhatt@codeaurora.org>
References: <1620171478-35679-1-git-send-email-bbhatt@codeaurora.org>
Message-ID: <1620171478-35679-7-git-send-email-bbhatt@codeaurora.org>

When obtaining the BHI or BHIe offsets during the power up
preparation phase, range checks are missing. These can help
controller drivers avoid accessing any address outside of the
MMIO region. Ensure that mhi_cntrl->reg_len is set before MHI
registration as it is a required field and range checks will
fail without it.

Signed-off-by: Bhaumik Bhatt <bbhatt at codeaurora.org>
Reviewed-by: Jeffrey Hugo <quic_jhugo at quicinc.com>
---
 drivers/bus/mhi/core/init.c | 15 ++++++++++++++-
 1 file changed, 14 insertions(+), 1 deletion(-)

diff --git a/drivers/bus/mhi/core/init.c b/drivers/bus/mhi/core/init.c
index 1cc2f22..86ad06e 100644
--- a/drivers/bus/mhi/core/init.c
+++ b/drivers/bus/mhi/core/init.c
@@ -885,7 +885,8 @@ int mhi_register_controller(struct mhi_controller *mhi_cntrl,
 	if (!mhi_cntrl || !mhi_cntrl->cntrl_dev || !mhi_cntrl->regs ||
 	    !mhi_cntrl->runtime_get || !mhi_cntrl->runtime_put ||
 	    !mhi_cntrl->status_cb || !mhi_cntrl->read_reg ||
-	    !mhi_cntrl->write_reg || !mhi_cntrl->nr_irqs || !mhi_cntrl->irq)
+	    !mhi_cntrl->write_reg || !mhi_cntrl->nr_irqs ||
+	    !mhi_cntrl->irq || !mhi_cntrl->reg_len)
 		return -EINVAL;
 
 	ret = parse_config(mhi_cntrl, config);
@@ -1077,6 +1078,12 @@ int mhi_prepare_for_power_up(struct mhi_controller *mhi_cntrl)
 		dev_err(dev, "Error getting BHI offset\n");
 		goto error_reg_offset;
 	}
+
+	if (bhi_off >= mhi_cntrl->reg_len) {
+		dev_err(dev, "BHI offset is out of range\n");
+		ret = -EINVAL;
+		goto error_reg_offset;
+	}
 	mhi_cntrl->bhi = mhi_cntrl->regs + bhi_off;
 
 	if (mhi_cntrl->fbc_download || mhi_cntrl->rddm_size) {
@@ -1086,6 +1093,12 @@ int mhi_prepare_for_power_up(struct mhi_controller *mhi_cntrl)
 			dev_err(dev, "Error getting BHIE offset\n");
 			goto error_reg_offset;
 		}
+
+		if (bhie_off >= mhi_cntrl->reg_len) {
+			dev_err(dev, "BHIe offset is out of range\n");
+			ret = -EINVAL;
+			goto error_reg_offset;
+		}
 		mhi_cntrl->bhie = mhi_cntrl->regs + bhie_off;
 	}
 
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project



From bbhatt at codeaurora.org  Wed May  5 00:37:56 2021
From: bbhatt at codeaurora.org (Bhaumik Bhatt)
Date: Tue,  4 May 2021 16:37:56 -0700
Subject: [PATCH v2 4/6] ath11k: set register access length for MHI driver
In-Reply-To: <1620171478-35679-1-git-send-email-bbhatt@codeaurora.org>
References: <1620171478-35679-1-git-send-email-bbhatt@codeaurora.org>
Message-ID: <1620171478-35679-5-git-send-email-bbhatt@codeaurora.org>

MHI driver requires register space length to add range checks and
prevent memory region accesses outside of that for MMIO space.
Set it before registering the MHI controller.

Signed-off-by: Bhaumik Bhatt <bbhatt at codeaurora.org>
---
 drivers/net/wireless/ath/ath11k/mhi.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/net/wireless/ath/ath11k/mhi.c b/drivers/net/wireless/ath/ath11k/mhi.c
index 09858e5..c0f013c 100644
--- a/drivers/net/wireless/ath/ath11k/mhi.c
+++ b/drivers/net/wireless/ath/ath11k/mhi.c
@@ -235,6 +235,7 @@ int ath11k_mhi_register(struct ath11k_pci *ab_pci)
 	mhi_ctrl->cntrl_dev = ab->dev;
 	mhi_ctrl->fw_image = ab_pci->amss_path;
 	mhi_ctrl->regs = ab->mem;
+	mhi_ctrl->reg_len = ab->mem_len;
 
 	ret = ath11k_mhi_get_msi(ab_pci);
 	if (ret) {
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project



From bbhatt at codeaurora.org  Wed May  5 00:37:54 2021
From: bbhatt at codeaurora.org (Bhaumik Bhatt)
Date: Tue,  4 May 2021 16:37:54 -0700
Subject: [PATCH v2 2/6] bus: mhi: core: Set BHI and BHIe pointers to NULL in
 clean-up
In-Reply-To: <1620171478-35679-1-git-send-email-bbhatt@codeaurora.org>
References: <1620171478-35679-1-git-send-email-bbhatt@codeaurora.org>
Message-ID: <1620171478-35679-3-git-send-email-bbhatt@codeaurora.org>

Set the BHI and BHIe pointers to NULL as part of clean-up. This
makes sure that stale pointers are not accessed after powering
MHI down.

Suggested-by: Hemant Kumar <hemantk at codeaurora.org>
Signed-off-by: Bhaumik Bhatt <bbhatt at codeaurora.org>
Reviewed-by: Jeffrey Hugo <quic_jhugo at quicinc.com>
---
 drivers/bus/mhi/core/init.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/bus/mhi/core/init.c b/drivers/bus/mhi/core/init.c
index 11c7a3d..1cc2f22 100644
--- a/drivers/bus/mhi/core/init.c
+++ b/drivers/bus/mhi/core/init.c
@@ -1132,6 +1132,9 @@ void mhi_unprepare_after_power_down(struct mhi_controller *mhi_cntrl)
 		mhi_cntrl->rddm_image = NULL;
 	}
 
+	mhi_cntrl->bhi = NULL;
+	mhi_cntrl->bhie = NULL;
+
 	mhi_deinit_dev_ctxt(mhi_cntrl);
 }
 EXPORT_SYMBOL_GPL(mhi_unprepare_after_power_down);
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project



From bbhatt at codeaurora.org  Wed May  5 00:37:57 2021
From: bbhatt at codeaurora.org (Bhaumik Bhatt)
Date: Tue,  4 May 2021 16:37:57 -0700
Subject: [PATCH v2 5/6] bus: mhi: pci_generic: Set register access length for
 MHI driver
In-Reply-To: <1620171478-35679-1-git-send-email-bbhatt@codeaurora.org>
References: <1620171478-35679-1-git-send-email-bbhatt@codeaurora.org>
Message-ID: <1620171478-35679-6-git-send-email-bbhatt@codeaurora.org>

MHI driver requires register space length to add range checks and
prevent memory region accesses outside of that for MMIO space.
Set it from the PCI generic controller driver before registering
the MHI controller.

Signed-off-by: Bhaumik Bhatt <bbhatt at codeaurora.org>
---
 drivers/bus/mhi/pci_generic.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/bus/mhi/pci_generic.c b/drivers/bus/mhi/pci_generic.c
index 7c810f0..fb7889f 100644
--- a/drivers/bus/mhi/pci_generic.c
+++ b/drivers/bus/mhi/pci_generic.c
@@ -463,6 +463,7 @@ static int mhi_pci_claim(struct mhi_controller *mhi_cntrl,
 		return err;
 	}
 	mhi_cntrl->regs = pcim_iomap_table(pdev)[bar_num];
+	mhi_cntrl->reg_len = pci_resource_len(pdev, bar_num);
 
 	err = pci_set_dma_mask(pdev, dma_mask);
 	if (err) {
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project



From mkenna at codeaurora.org  Wed May  5 08:18:03 2021
From: mkenna at codeaurora.org (Maharaja Kennadyrajan)
Date: Wed, 05 May 2021 12:48:03 +0530
Subject: [PATCH v2 1/3] nl80211: Add support for beacon tx mode
In-Reply-To: <445ba573b519b9434d0e009eb9ff6f45@codeaurora.org>
References: <1619696874-30072-1-git-send-email-mkenna@codeaurora.org>
 <1619696874-30072-2-git-send-email-mkenna@codeaurora.org>
 <445ba573b519b9434d0e009eb9ff6f45@codeaurora.org>
Message-ID: <cc2182041c5fc8f1c168a262e3a3263c@codeaurora.org>

On 2021-05-03 22:54, jjohnson at codeaurora.org wrote:
> On 2021-04-29 04:47, Maharaja Kennadyrajan wrote:
> [..snip..]
>> +/**
>> + * enum nl80211_beacon_tx_mode - Beacon Tx Mode enum.
>> + *      Used to configure beacon staggered mode or beacon burst mode.
>> + */
>> +enum nl80211_beacon_tx_mode {
>> +	NL80211_BEACON_STAGGERED_MODE = 1,
>> +	NL80211_BEACON_BURST_MODE = 2,
>> +};
>> +
> [..snip..]
>> @@ -5330,6 +5331,10 @@ static int nl80211_start_ap(struct sk_buff 
>> *skb,
>> struct genl_info *info)
>>  	params.dtim_period =
>>  		nla_get_u32(info->attrs[NL80211_ATTR_DTIM_PERIOD]);
>> 
>> +	if (info->attrs[NL80211_ATTR_BEACON_TX_MODE])
>> +		params.beacon_tx_mode =
>> +
>> nla_get_u32(info->attrs[NL80211_ATTR_BEACON_TX_MODE]);
>> +
> 
> Note that in the case where NL80211_ATTR_BEACON_TX_MODE is not 
> specified that
> beacon_tx_mode will be zero, which is not a valid
> nl80211_beacon_tx_mode enumeration.
> 
> Should you renumber the nl80211_beacon_tx_mode enumerations so that the 
> default
> mode has a value of 0? Or add NL80211_BEACON_DEFAULT_MODE = 0 and
> allow the driver
> to select a default mode?

[Maha]: Yes, it will select the default mode as STAGGERED mode when the 
user set
beacon_tx_mode as 0 in the hostapd conf file.
Also, it will select the default mode as STAGGERED mode when the user 
didn't add
beacon_tx_mode config in the hostapd conf file.
This is how it is handled here already.

Regards,
Maha


From jjohnson at codeaurora.org  Wed May  5 15:27:31 2021
From: jjohnson at codeaurora.org (jjohnson at codeaurora.org)
Date: Wed, 05 May 2021 07:27:31 -0700
Subject: [PATCH v2 1/3] nl80211: Add support for beacon tx mode
In-Reply-To: <cc2182041c5fc8f1c168a262e3a3263c@codeaurora.org>
References: <1619696874-30072-1-git-send-email-mkenna@codeaurora.org>
 <1619696874-30072-2-git-send-email-mkenna@codeaurora.org>
 <445ba573b519b9434d0e009eb9ff6f45@codeaurora.org>
 <cc2182041c5fc8f1c168a262e3a3263c@codeaurora.org>
Message-ID: <ce40ca27c3af5efd27a64415538d5b63@codeaurora.org>

On 2021-05-05 00:18, Maharaja Kennadyrajan wrote:
> On 2021-05-03 22:54, jjohnson at codeaurora.org wrote:
>> On 2021-04-29 04:47, Maharaja Kennadyrajan wrote:
>> [..snip..]
>>> +/**
>>> + * enum nl80211_beacon_tx_mode - Beacon Tx Mode enum.
>>> + *      Used to configure beacon staggered mode or beacon burst 
>>> mode.
>>> + */
>>> +enum nl80211_beacon_tx_mode {
>>> +	NL80211_BEACON_STAGGERED_MODE = 1,
>>> +	NL80211_BEACON_BURST_MODE = 2,
>>> +};
>>> +
>> [..snip..]
>>> @@ -5330,6 +5331,10 @@ static int nl80211_start_ap(struct sk_buff 
>>> *skb,
>>> struct genl_info *info)
>>>  	params.dtim_period =
>>>  		nla_get_u32(info->attrs[NL80211_ATTR_DTIM_PERIOD]);
>>> 
>>> +	if (info->attrs[NL80211_ATTR_BEACON_TX_MODE])
>>> +		params.beacon_tx_mode =
>>> +
>>> nla_get_u32(info->attrs[NL80211_ATTR_BEACON_TX_MODE]);
>>> +
>> 
>> Note that in the case where NL80211_ATTR_BEACON_TX_MODE is not 
>> specified that
>> beacon_tx_mode will be zero, which is not a valid
>> nl80211_beacon_tx_mode enumeration.
>> 
>> Should you renumber the nl80211_beacon_tx_mode enumerations so that 
>> the default
>> mode has a value of 0? Or add NL80211_BEACON_DEFAULT_MODE = 0 and
>> allow the driver
>> to select a default mode?
> 
> [Maha]: Yes, it will select the default mode as STAGGERED mode when the 
> user set
> beacon_tx_mode as 0 in the hostapd conf file.
> Also, it will select the default mode as STAGGERED mode when the user 
> didn't add
> beacon_tx_mode config in the hostapd conf file.
> This is how it is handled here already.

Regardless of how it is handled, I still assert that there is a
coding/logic error here since in the case the attribute is not
present you send an invalid enumeration (0) to the driver. I'm
suggesting to fix that logic/coding error either by renumbering
the existing enumerations or by adding a new enumeration so that
0 is a valid enumeration.



From quic_jhugo at quicinc.com  Wed May  5 15:37:32 2021
From: quic_jhugo at quicinc.com (Jeffrey Hugo)
Date: Wed, 5 May 2021 08:37:32 -0600
Subject: [PATCH v2 3/6] bus: mhi: Add MMIO region length to controller
 structure
In-Reply-To: <1620171478-35679-4-git-send-email-bbhatt@codeaurora.org>
References: <1620171478-35679-1-git-send-email-bbhatt@codeaurora.org>
 <1620171478-35679-4-git-send-email-bbhatt@codeaurora.org>
Message-ID: <ee188cdb-3edf-816a-c0b2-88a14fd037f3@quicinc.com>

On 5/4/2021 5:37 PM, Bhaumik Bhatt wrote:
> Make controller driver specify the MMIO register region length
> for range checking of BHI or BHIe space. This can help validate
> that offsets are in acceptable memory region or not and avoid any
> boot-up issues due to BHI or BHIe memory accesses.
> 
> Signed-off-by: Bhaumik Bhatt <bbhatt at codeaurora.org>
> ---
>   include/linux/mhi.h | 2 ++
>   1 file changed, 2 insertions(+)
> 
> diff --git a/include/linux/mhi.h b/include/linux/mhi.h
> index 944aa3a..f6901db 100644
> --- a/include/linux/mhi.h
> +++ b/include/linux/mhi.h
> @@ -293,6 +293,7 @@ struct mhi_controller_config {
>    * @mhi_dev: MHI device instance for the controller
>    * @debugfs_dentry: MHI controller debugfs directory
>    * @regs: Base address of MHI MMIO register space (required)
> + * @reg_len: Length of the MHI MMIO region (required)

I believe this should be moved so that it matches the ordering of the 
struct fields below.

With the adjustment, you can add my reviewed tag to this.

>    * @bhi: Points to base of MHI BHI register space
>    * @bhie: Points to base of MHI BHIe register space
>    * @wake_db: MHI WAKE doorbell register address
> @@ -386,6 +387,7 @@ struct mhi_controller {
>   	size_t rddm_size;
>   	size_t sbl_size;
>   	size_t seg_len;
> +	size_t reg_len;
>   	struct image_info *fbc_image;
>   	struct image_info *rddm_image;
>   	struct mhi_chan *mhi_chan;
> 



From sashal at kernel.org  Wed May  5 17:29:29 2021
From: sashal at kernel.org (Sasha Levin)
Date: Wed,  5 May 2021 12:29:29 -0400
Subject: [PATCH AUTOSEL 5.12 001/116] ath11k: fix thermal temperature read
Message-ID: <20210505163125.3460440-1-sashal@kernel.org>

From: Pradeep Kumar Chitrapu <pradeepc at codeaurora.org>

[ Upstream commit e3de5bb7ac1a4cb262f8768924fd3ef6182b10bb ]

Fix dangling pointer in thermal temperature event which causes
incorrect temperature read.

Tested-on: IPQ8074 AHB WLAN.HK.2.4.0.1-00041-QCAHKSWPL_SILICONZ-1

Signed-off-by: Pradeep Kumar Chitrapu <pradeepc at codeaurora.org>
Signed-off-by: Kalle Valo <kvalo at codeaurora.org>
Link: https://lore.kernel.org/r/20210218182708.8844-1-pradeepc at codeaurora.org
Signed-off-by: Sasha Levin <sashal at kernel.org>
---
 drivers/net/wireless/ath/ath11k/wmi.c | 53 +++++++++++----------------
 1 file changed, 21 insertions(+), 32 deletions(-)

diff --git a/drivers/net/wireless/ath/ath11k/wmi.c b/drivers/net/wireless/ath/ath11k/wmi.c
index cccfd3bd4d27..ca5cda890d58 100644
--- a/drivers/net/wireless/ath/ath11k/wmi.c
+++ b/drivers/net/wireless/ath/ath11k/wmi.c
@@ -5417,31 +5417,6 @@ int ath11k_wmi_pull_fw_stats(struct ath11k_base *ab, struct sk_buff *skb,
 	return 0;
 }
 
-static int
-ath11k_pull_pdev_temp_ev(struct ath11k_base *ab, u8 *evt_buf,
-			 u32 len, const struct wmi_pdev_temperature_event *ev)
-{
-	const void **tb;
-	int ret;
-
-	tb = ath11k_wmi_tlv_parse_alloc(ab, evt_buf, len, GFP_ATOMIC);
-	if (IS_ERR(tb)) {
-		ret = PTR_ERR(tb);
-		ath11k_warn(ab, "failed to parse tlv: %d\n", ret);
-		return ret;
-	}
-
-	ev = tb[WMI_TAG_PDEV_TEMPERATURE_EVENT];
-	if (!ev) {
-		ath11k_warn(ab, "failed to fetch pdev temp ev");
-		kfree(tb);
-		return -EPROTO;
-	}
-
-	kfree(tb);
-	return 0;
-}
-
 size_t ath11k_wmi_fw_stats_num_vdevs(struct list_head *head)
 {
 	struct ath11k_fw_stats_vdev *i;
@@ -6849,23 +6824,37 @@ ath11k_wmi_pdev_temperature_event(struct ath11k_base *ab,
 				  struct sk_buff *skb)
 {
 	struct ath11k *ar;
-	struct wmi_pdev_temperature_event ev = {0};
+	const void **tb;
+	const struct wmi_pdev_temperature_event *ev;
+	int ret;
+
+	tb = ath11k_wmi_tlv_parse_alloc(ab, skb->data, skb->len, GFP_ATOMIC);
+	if (IS_ERR(tb)) {
+		ret = PTR_ERR(tb);
+		ath11k_warn(ab, "failed to parse tlv: %d\n", ret);
+		return;
+	}
 
-	if (ath11k_pull_pdev_temp_ev(ab, skb->data, skb->len, &ev) != 0) {
-		ath11k_warn(ab, "failed to extract pdev temperature event");
+	ev = tb[WMI_TAG_PDEV_TEMPERATURE_EVENT];
+	if (!ev) {
+		ath11k_warn(ab, "failed to fetch pdev temp ev");
+		kfree(tb);
 		return;
 	}
 
 	ath11k_dbg(ab, ATH11K_DBG_WMI,
-		   "pdev temperature ev temp %d pdev_id %d\n", ev.temp, ev.pdev_id);
+		   "pdev temperature ev temp %d pdev_id %d\n", ev->temp, ev->pdev_id);
 
-	ar = ath11k_mac_get_ar_by_pdev_id(ab, ev.pdev_id);
+	ar = ath11k_mac_get_ar_by_pdev_id(ab, ev->pdev_id);
 	if (!ar) {
-		ath11k_warn(ab, "invalid pdev id in pdev temperature ev %d", ev.pdev_id);
+		ath11k_warn(ab, "invalid pdev id in pdev temperature ev %d", ev->pdev_id);
+		kfree(tb);
 		return;
 	}
 
-	ath11k_thermal_event_temperature(ar, ev.temp);
+	ath11k_thermal_event_temperature(ar, ev->temp);
+
+	kfree(tb);
 }
 
 static void ath11k_fils_discovery_event(struct ath11k_base *ab,
-- 
2.30.2



From sashal at kernel.org  Wed May  5 17:32:30 2021
From: sashal at kernel.org (Sasha Levin)
Date: Wed,  5 May 2021 12:32:30 -0400
Subject: [PATCH AUTOSEL 5.11 001/104] ath11k: fix thermal temperature read
Message-ID: <20210505163413.3461611-1-sashal@kernel.org>

From: Pradeep Kumar Chitrapu <pradeepc at codeaurora.org>

[ Upstream commit e3de5bb7ac1a4cb262f8768924fd3ef6182b10bb ]

Fix dangling pointer in thermal temperature event which causes
incorrect temperature read.

Tested-on: IPQ8074 AHB WLAN.HK.2.4.0.1-00041-QCAHKSWPL_SILICONZ-1

Signed-off-by: Pradeep Kumar Chitrapu <pradeepc at codeaurora.org>
Signed-off-by: Kalle Valo <kvalo at codeaurora.org>
Link: https://lore.kernel.org/r/20210218182708.8844-1-pradeepc at codeaurora.org
Signed-off-by: Sasha Levin <sashal at kernel.org>
---
 drivers/net/wireless/ath/ath11k/wmi.c | 53 +++++++++++----------------
 1 file changed, 21 insertions(+), 32 deletions(-)

diff --git a/drivers/net/wireless/ath/ath11k/wmi.c b/drivers/net/wireless/ath/ath11k/wmi.c
index 73869d445c5b..f457a089b63c 100644
--- a/drivers/net/wireless/ath/ath11k/wmi.c
+++ b/drivers/net/wireless/ath/ath11k/wmi.c
@@ -5190,31 +5190,6 @@ int ath11k_wmi_pull_fw_stats(struct ath11k_base *ab, struct sk_buff *skb,
 	return 0;
 }
 
-static int
-ath11k_pull_pdev_temp_ev(struct ath11k_base *ab, u8 *evt_buf,
-			 u32 len, const struct wmi_pdev_temperature_event *ev)
-{
-	const void **tb;
-	int ret;
-
-	tb = ath11k_wmi_tlv_parse_alloc(ab, evt_buf, len, GFP_ATOMIC);
-	if (IS_ERR(tb)) {
-		ret = PTR_ERR(tb);
-		ath11k_warn(ab, "failed to parse tlv: %d\n", ret);
-		return ret;
-	}
-
-	ev = tb[WMI_TAG_PDEV_TEMPERATURE_EVENT];
-	if (!ev) {
-		ath11k_warn(ab, "failed to fetch pdev temp ev");
-		kfree(tb);
-		return -EPROTO;
-	}
-
-	kfree(tb);
-	return 0;
-}
-
 size_t ath11k_wmi_fw_stats_num_vdevs(struct list_head *head)
 {
 	struct ath11k_fw_stats_vdev *i;
@@ -6622,23 +6597,37 @@ ath11k_wmi_pdev_temperature_event(struct ath11k_base *ab,
 				  struct sk_buff *skb)
 {
 	struct ath11k *ar;
-	struct wmi_pdev_temperature_event ev = {0};
+	const void **tb;
+	const struct wmi_pdev_temperature_event *ev;
+	int ret;
+
+	tb = ath11k_wmi_tlv_parse_alloc(ab, skb->data, skb->len, GFP_ATOMIC);
+	if (IS_ERR(tb)) {
+		ret = PTR_ERR(tb);
+		ath11k_warn(ab, "failed to parse tlv: %d\n", ret);
+		return;
+	}
 
-	if (ath11k_pull_pdev_temp_ev(ab, skb->data, skb->len, &ev) != 0) {
-		ath11k_warn(ab, "failed to extract pdev temperature event");
+	ev = tb[WMI_TAG_PDEV_TEMPERATURE_EVENT];
+	if (!ev) {
+		ath11k_warn(ab, "failed to fetch pdev temp ev");
+		kfree(tb);
 		return;
 	}
 
 	ath11k_dbg(ab, ATH11K_DBG_WMI,
-		   "pdev temperature ev temp %d pdev_id %d\n", ev.temp, ev.pdev_id);
+		   "pdev temperature ev temp %d pdev_id %d\n", ev->temp, ev->pdev_id);
 
-	ar = ath11k_mac_get_ar_by_pdev_id(ab, ev.pdev_id);
+	ar = ath11k_mac_get_ar_by_pdev_id(ab, ev->pdev_id);
 	if (!ar) {
-		ath11k_warn(ab, "invalid pdev id in pdev temperature ev %d", ev.pdev_id);
+		ath11k_warn(ab, "invalid pdev id in pdev temperature ev %d", ev->pdev_id);
+		kfree(tb);
 		return;
 	}
 
-	ath11k_thermal_event_temperature(ar, ev.temp);
+	ath11k_thermal_event_temperature(ar, ev->temp);
+
+	kfree(tb);
 }
 
 static void ath11k_fils_discovery_event(struct ath11k_base *ab,
-- 
2.30.2



From sashal at kernel.org  Wed May  5 17:35:24 2021
From: sashal at kernel.org (Sasha Levin)
Date: Wed,  5 May 2021 12:35:24 -0400
Subject: [PATCH AUTOSEL 5.10 01/85] ath11k: fix thermal temperature read
Message-ID: <20210505163648.3462507-1-sashal@kernel.org>

From: Pradeep Kumar Chitrapu <pradeepc at codeaurora.org>

[ Upstream commit e3de5bb7ac1a4cb262f8768924fd3ef6182b10bb ]

Fix dangling pointer in thermal temperature event which causes
incorrect temperature read.

Tested-on: IPQ8074 AHB WLAN.HK.2.4.0.1-00041-QCAHKSWPL_SILICONZ-1

Signed-off-by: Pradeep Kumar Chitrapu <pradeepc at codeaurora.org>
Signed-off-by: Kalle Valo <kvalo at codeaurora.org>
Link: https://lore.kernel.org/r/20210218182708.8844-1-pradeepc at codeaurora.org
Signed-off-by: Sasha Levin <sashal at kernel.org>
---
 drivers/net/wireless/ath/ath11k/wmi.c | 53 +++++++++++----------------
 1 file changed, 21 insertions(+), 32 deletions(-)

diff --git a/drivers/net/wireless/ath/ath11k/wmi.c b/drivers/net/wireless/ath/ath11k/wmi.c
index 173ab6ceed1f..eca86225a341 100644
--- a/drivers/net/wireless/ath/ath11k/wmi.c
+++ b/drivers/net/wireless/ath/ath11k/wmi.c
@@ -4986,31 +4986,6 @@ int ath11k_wmi_pull_fw_stats(struct ath11k_base *ab, struct sk_buff *skb,
 	return 0;
 }
 
-static int
-ath11k_pull_pdev_temp_ev(struct ath11k_base *ab, u8 *evt_buf,
-			 u32 len, const struct wmi_pdev_temperature_event *ev)
-{
-	const void **tb;
-	int ret;
-
-	tb = ath11k_wmi_tlv_parse_alloc(ab, evt_buf, len, GFP_ATOMIC);
-	if (IS_ERR(tb)) {
-		ret = PTR_ERR(tb);
-		ath11k_warn(ab, "failed to parse tlv: %d\n", ret);
-		return ret;
-	}
-
-	ev = tb[WMI_TAG_PDEV_TEMPERATURE_EVENT];
-	if (!ev) {
-		ath11k_warn(ab, "failed to fetch pdev temp ev");
-		kfree(tb);
-		return -EPROTO;
-	}
-
-	kfree(tb);
-	return 0;
-}
-
 size_t ath11k_wmi_fw_stats_num_vdevs(struct list_head *head)
 {
 	struct ath11k_fw_stats_vdev *i;
@@ -6390,23 +6365,37 @@ ath11k_wmi_pdev_temperature_event(struct ath11k_base *ab,
 				  struct sk_buff *skb)
 {
 	struct ath11k *ar;
-	struct wmi_pdev_temperature_event ev = {0};
+	const void **tb;
+	const struct wmi_pdev_temperature_event *ev;
+	int ret;
+
+	tb = ath11k_wmi_tlv_parse_alloc(ab, skb->data, skb->len, GFP_ATOMIC);
+	if (IS_ERR(tb)) {
+		ret = PTR_ERR(tb);
+		ath11k_warn(ab, "failed to parse tlv: %d\n", ret);
+		return;
+	}
 
-	if (ath11k_pull_pdev_temp_ev(ab, skb->data, skb->len, &ev) != 0) {
-		ath11k_warn(ab, "failed to extract pdev temperature event");
+	ev = tb[WMI_TAG_PDEV_TEMPERATURE_EVENT];
+	if (!ev) {
+		ath11k_warn(ab, "failed to fetch pdev temp ev");
+		kfree(tb);
 		return;
 	}
 
 	ath11k_dbg(ab, ATH11K_DBG_WMI,
-		   "pdev temperature ev temp %d pdev_id %d\n", ev.temp, ev.pdev_id);
+		   "pdev temperature ev temp %d pdev_id %d\n", ev->temp, ev->pdev_id);
 
-	ar = ath11k_mac_get_ar_by_pdev_id(ab, ev.pdev_id);
+	ar = ath11k_mac_get_ar_by_pdev_id(ab, ev->pdev_id);
 	if (!ar) {
-		ath11k_warn(ab, "invalid pdev id in pdev temperature ev %d", ev.pdev_id);
+		ath11k_warn(ab, "invalid pdev id in pdev temperature ev %d", ev->pdev_id);
+		kfree(tb);
 		return;
 	}
 
-	ath11k_thermal_event_temperature(ar, ev.temp);
+	ath11k_thermal_event_temperature(ar, ev->temp);
+
+	kfree(tb);
 }
 
 static void ath11k_wmi_tlv_op_rx(struct ath11k_base *ab, struct sk_buff *skb)
-- 
2.30.2



From bbhatt at codeaurora.org  Wed May  5 18:08:16 2021
From: bbhatt at codeaurora.org (Bhaumik Bhatt)
Date: Wed,  5 May 2021 10:08:16 -0700
Subject: [PATCH v3 1/6] bus: mhi: core: Set BHI/BHIe offsets on power up
 preparation
In-Reply-To: <1620234501-30461-1-git-send-email-bbhatt@codeaurora.org>
References: <1620234501-30461-1-git-send-email-bbhatt@codeaurora.org>
Message-ID: <1620234501-30461-2-git-send-email-bbhatt@codeaurora.org>

Set the BHI and/or BHIe offsets in mhi_prepare_for_power_up(),
rearrange the function, and remove the equivalent from
mhi_async_power_up(). This helps consolidate multiple checks
in different parts of the driver and can help MHI fail early on
before power up begins if the offsets are not read correctly.

Signed-off-by: Bhaumik Bhatt <bbhatt at codeaurora.org>
Reviewed-by: Jeffrey Hugo <quic_jhugo at quicinc.com>
---
 drivers/bus/mhi/core/init.c | 42 +++++++++++++++++++++++-------------------
 drivers/bus/mhi/core/pm.c   | 28 ++++------------------------
 2 files changed, 27 insertions(+), 43 deletions(-)

diff --git a/drivers/bus/mhi/core/init.c b/drivers/bus/mhi/core/init.c
index c81b377..11c7a3d 100644
--- a/drivers/bus/mhi/core/init.c
+++ b/drivers/bus/mhi/core/init.c
@@ -1063,7 +1063,7 @@ EXPORT_SYMBOL_GPL(mhi_free_controller);
 int mhi_prepare_for_power_up(struct mhi_controller *mhi_cntrl)
 {
 	struct device *dev = &mhi_cntrl->mhi_dev->dev;
-	u32 bhie_off;
+	u32 bhi_off, bhie_off;
 	int ret;
 
 	mutex_lock(&mhi_cntrl->pm_mutex);
@@ -1072,29 +1072,36 @@ int mhi_prepare_for_power_up(struct mhi_controller *mhi_cntrl)
 	if (ret)
 		goto error_dev_ctxt;
 
-	/*
-	 * Allocate RDDM table if specified, this table is for debugging purpose
-	 */
-	if (mhi_cntrl->rddm_size) {
-		mhi_alloc_bhie_table(mhi_cntrl, &mhi_cntrl->rddm_image,
-				     mhi_cntrl->rddm_size);
+	ret = mhi_read_reg(mhi_cntrl, mhi_cntrl->regs, BHIOFF, &bhi_off);
+	if (ret) {
+		dev_err(dev, "Error getting BHI offset\n");
+		goto error_reg_offset;
+	}
+	mhi_cntrl->bhi = mhi_cntrl->regs + bhi_off;
 
-		/*
-		 * This controller supports RDDM, so we need to manually clear
-		 * BHIE RX registers since POR values are undefined.
-		 */
+	if (mhi_cntrl->fbc_download || mhi_cntrl->rddm_size) {
 		ret = mhi_read_reg(mhi_cntrl, mhi_cntrl->regs, BHIEOFF,
 				   &bhie_off);
 		if (ret) {
 			dev_err(dev, "Error getting BHIE offset\n");
-			goto bhie_error;
+			goto error_reg_offset;
 		}
-
 		mhi_cntrl->bhie = mhi_cntrl->regs + bhie_off;
+	}
+
+	if (mhi_cntrl->rddm_size) {
+		/*
+		 * This controller supports RDDM, so we need to manually clear
+		 * BHIE RX registers since POR values are undefined.
+		 */
 		memset_io(mhi_cntrl->bhie + BHIE_RXVECADDR_LOW_OFFS,
 			  0, BHIE_RXVECSTATUS_OFFS - BHIE_RXVECADDR_LOW_OFFS +
 			  4);
-
+		/*
+		 * Allocate RDDM table for debugging purpose if specified
+		 */
+		mhi_alloc_bhie_table(mhi_cntrl, &mhi_cntrl->rddm_image,
+				     mhi_cntrl->rddm_size);
 		if (mhi_cntrl->rddm_image)
 			mhi_rddm_prepare(mhi_cntrl, mhi_cntrl->rddm_image);
 	}
@@ -1103,11 +1110,8 @@ int mhi_prepare_for_power_up(struct mhi_controller *mhi_cntrl)
 
 	return 0;
 
-bhie_error:
-	if (mhi_cntrl->rddm_image) {
-		mhi_free_bhie_table(mhi_cntrl, mhi_cntrl->rddm_image);
-		mhi_cntrl->rddm_image = NULL;
-	}
+error_reg_offset:
+	mhi_deinit_dev_ctxt(mhi_cntrl);
 
 error_dev_ctxt:
 	mutex_unlock(&mhi_cntrl->pm_mutex);
diff --git a/drivers/bus/mhi/core/pm.c b/drivers/bus/mhi/core/pm.c
index e2e59a3..adf426c 100644
--- a/drivers/bus/mhi/core/pm.c
+++ b/drivers/bus/mhi/core/pm.c
@@ -1066,28 +1066,8 @@ int mhi_async_power_up(struct mhi_controller *mhi_cntrl)
 	if (ret)
 		goto error_setup_irq;
 
-	/* Setup BHI offset & INTVEC */
+	/* Setup BHI INTVEC */
 	write_lock_irq(&mhi_cntrl->pm_lock);
-	ret = mhi_read_reg(mhi_cntrl, mhi_cntrl->regs, BHIOFF, &val);
-	if (ret) {
-		write_unlock_irq(&mhi_cntrl->pm_lock);
-		goto error_bhi_offset;
-	}
-
-	mhi_cntrl->bhi = mhi_cntrl->regs + val;
-
-	/* Setup BHIE offset */
-	if (mhi_cntrl->fbc_download) {
-		ret = mhi_read_reg(mhi_cntrl, mhi_cntrl->regs, BHIEOFF, &val);
-		if (ret) {
-			write_unlock_irq(&mhi_cntrl->pm_lock);
-			dev_err(dev, "Error reading BHIE offset\n");
-			goto error_bhi_offset;
-		}
-
-		mhi_cntrl->bhie = mhi_cntrl->regs + val;
-	}
-
 	mhi_write_reg(mhi_cntrl, mhi_cntrl->bhi, BHI_INTVEC, 0);
 	mhi_cntrl->pm_state = MHI_PM_POR;
 	mhi_cntrl->ee = MHI_EE_MAX;
@@ -1098,7 +1078,7 @@ int mhi_async_power_up(struct mhi_controller *mhi_cntrl)
 	if (!MHI_IN_PBL(current_ee) && current_ee != MHI_EE_AMSS) {
 		dev_err(dev, "Not a valid EE for power on\n");
 		ret = -EIO;
-		goto error_bhi_offset;
+		goto error_async_power_up;
 	}
 
 	state = mhi_get_mhi_state(mhi_cntrl);
@@ -1117,7 +1097,7 @@ int mhi_async_power_up(struct mhi_controller *mhi_cntrl)
 		if (!ret) {
 			ret = -EIO;
 			dev_info(dev, "Failed to reset MHI due to syserr state\n");
-			goto error_bhi_offset;
+			goto error_async_power_up;
 		}
 
 		/*
@@ -1139,7 +1119,7 @@ int mhi_async_power_up(struct mhi_controller *mhi_cntrl)
 
 	return 0;
 
-error_bhi_offset:
+error_async_power_up:
 	mhi_deinit_free_irq(mhi_cntrl);
 
 error_setup_irq:
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project



From bbhatt at codeaurora.org  Wed May  5 18:08:15 2021
From: bbhatt at codeaurora.org (Bhaumik Bhatt)
Date: Wed,  5 May 2021 10:08:15 -0700
Subject: [PATCH v3 0/6] BHI/BHIe improvements for MHI power purposes
Message-ID: <1620234501-30461-1-git-send-email-bbhatt@codeaurora.org>

This patch series improves the power up behavior by allowing MHI host driver to
set BHI and/or BHIe offsets early on in the preparation phase and fail pre-power
up if offsets are not found or not within a limited MMIO region. This also
allows MHI host to clean up the offsets in the unprepare after power down phase.

Going forward, controllers will be required to specify a reg_len field which
will be used to check whether the BHI/BHIe offsets are in range or not.

This series has been tested on X86_64 architecture with the PCI generic driver
as controller and an SDX55 device.

v3:
-Added reviewed-by tags
-Updated order of reg_len in mhi_controller structure documentation

v2:
-Added reviewed-by tags
-Moved reg_len entry in mhi_controller structure to allow for a packed struct

Bhaumik Bhatt (6):
  bus: mhi: core: Set BHI/BHIe offsets on power up preparation
  bus: mhi: core: Set BHI and BHIe pointers to NULL in clean-up
  bus: mhi: Add MMIO region length to controller structure
  ath11k: set register access length for MHI driver
  bus: mhi: pci_generic: Set register access length for MHI driver
  bus: mhi: core: Add range checks for BHI and BHIe

 drivers/bus/mhi/core/init.c           | 58 +++++++++++++++++++++++------------
 drivers/bus/mhi/core/pm.c             | 28 +++--------------
 drivers/bus/mhi/pci_generic.c         |  1 +
 drivers/net/wireless/ath/ath11k/mhi.c |  1 +
 include/linux/mhi.h                   |  2 ++
 5 files changed, 47 insertions(+), 43 deletions(-)

-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project



From bbhatt at codeaurora.org  Wed May  5 18:08:17 2021
From: bbhatt at codeaurora.org (Bhaumik Bhatt)
Date: Wed,  5 May 2021 10:08:17 -0700
Subject: [PATCH v3 2/6] bus: mhi: core: Set BHI and BHIe pointers to NULL in
 clean-up
In-Reply-To: <1620234501-30461-1-git-send-email-bbhatt@codeaurora.org>
References: <1620234501-30461-1-git-send-email-bbhatt@codeaurora.org>
Message-ID: <1620234501-30461-3-git-send-email-bbhatt@codeaurora.org>

Set the BHI and BHIe pointers to NULL as part of clean-up. This
makes sure that stale pointers are not accessed after powering
MHI down.

Suggested-by: Hemant Kumar <hemantk at codeaurora.org>
Signed-off-by: Bhaumik Bhatt <bbhatt at codeaurora.org>
Reviewed-by: Jeffrey Hugo <quic_jhugo at quicinc.com>
---
 drivers/bus/mhi/core/init.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/bus/mhi/core/init.c b/drivers/bus/mhi/core/init.c
index 11c7a3d..1cc2f22 100644
--- a/drivers/bus/mhi/core/init.c
+++ b/drivers/bus/mhi/core/init.c
@@ -1132,6 +1132,9 @@ void mhi_unprepare_after_power_down(struct mhi_controller *mhi_cntrl)
 		mhi_cntrl->rddm_image = NULL;
 	}
 
+	mhi_cntrl->bhi = NULL;
+	mhi_cntrl->bhie = NULL;
+
 	mhi_deinit_dev_ctxt(mhi_cntrl);
 }
 EXPORT_SYMBOL_GPL(mhi_unprepare_after_power_down);
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project



From bbhatt at codeaurora.org  Wed May  5 18:08:18 2021
From: bbhatt at codeaurora.org (Bhaumik Bhatt)
Date: Wed,  5 May 2021 10:08:18 -0700
Subject: [PATCH v3 3/6] bus: mhi: Add MMIO region length to controller
 structure
In-Reply-To: <1620234501-30461-1-git-send-email-bbhatt@codeaurora.org>
References: <1620234501-30461-1-git-send-email-bbhatt@codeaurora.org>
Message-ID: <1620234501-30461-4-git-send-email-bbhatt@codeaurora.org>

Make controller driver specify the MMIO register region length
for range checking of BHI or BHIe space. This can help validate
that offsets are in acceptable memory region or not and avoid any
boot-up issues due to BHI or BHIe memory accesses.

Signed-off-by: Bhaumik Bhatt <bbhatt at codeaurora.org>
Reviewed-by: Jeffrey Hugo <quic_jhugo at quicinc.com>
---
 include/linux/mhi.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/linux/mhi.h b/include/linux/mhi.h
index 944aa3a..9c347f5 100644
--- a/include/linux/mhi.h
+++ b/include/linux/mhi.h
@@ -303,6 +303,7 @@ struct mhi_controller_config {
  * @rddm_size: RAM dump size that host should allocate for debugging purpose
  * @sbl_size: SBL image size downloaded through BHIe (optional)
  * @seg_len: BHIe vector size (optional)
+ * @reg_len: Length of the MHI MMIO region (required)
  * @fbc_image: Points to firmware image buffer
  * @rddm_image: Points to RAM dump buffer
  * @mhi_chan: Points to the channel configuration table
@@ -386,6 +387,7 @@ struct mhi_controller {
 	size_t rddm_size;
 	size_t sbl_size;
 	size_t seg_len;
+	size_t reg_len;
 	struct image_info *fbc_image;
 	struct image_info *rddm_image;
 	struct mhi_chan *mhi_chan;
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project



From bbhatt at codeaurora.org  Wed May  5 18:08:20 2021
From: bbhatt at codeaurora.org (Bhaumik Bhatt)
Date: Wed,  5 May 2021 10:08:20 -0700
Subject: [PATCH v3 5/6] bus: mhi: pci_generic: Set register access length for
 MHI driver
In-Reply-To: <1620234501-30461-1-git-send-email-bbhatt@codeaurora.org>
References: <1620234501-30461-1-git-send-email-bbhatt@codeaurora.org>
Message-ID: <1620234501-30461-6-git-send-email-bbhatt@codeaurora.org>

MHI driver requires register space length to add range checks and
prevent memory region accesses outside of that for MMIO space.
Set it from the PCI generic controller driver before registering
the MHI controller.

Signed-off-by: Bhaumik Bhatt <bbhatt at codeaurora.org>
---
 drivers/bus/mhi/pci_generic.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/bus/mhi/pci_generic.c b/drivers/bus/mhi/pci_generic.c
index 7c810f0..fb7889f 100644
--- a/drivers/bus/mhi/pci_generic.c
+++ b/drivers/bus/mhi/pci_generic.c
@@ -463,6 +463,7 @@ static int mhi_pci_claim(struct mhi_controller *mhi_cntrl,
 		return err;
 	}
 	mhi_cntrl->regs = pcim_iomap_table(pdev)[bar_num];
+	mhi_cntrl->reg_len = pci_resource_len(pdev, bar_num);
 
 	err = pci_set_dma_mask(pdev, dma_mask);
 	if (err) {
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project



From bbhatt at codeaurora.org  Wed May  5 18:08:19 2021
From: bbhatt at codeaurora.org (Bhaumik Bhatt)
Date: Wed,  5 May 2021 10:08:19 -0700
Subject: [PATCH v3 4/6] ath11k: set register access length for MHI driver
In-Reply-To: <1620234501-30461-1-git-send-email-bbhatt@codeaurora.org>
References: <1620234501-30461-1-git-send-email-bbhatt@codeaurora.org>
Message-ID: <1620234501-30461-5-git-send-email-bbhatt@codeaurora.org>

MHI driver requires register space length to add range checks and
prevent memory region accesses outside of that for MMIO space.
Set it before registering the MHI controller.

Signed-off-by: Bhaumik Bhatt <bbhatt at codeaurora.org>
---
 drivers/net/wireless/ath/ath11k/mhi.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/net/wireless/ath/ath11k/mhi.c b/drivers/net/wireless/ath/ath11k/mhi.c
index 09858e5..c0f013c 100644
--- a/drivers/net/wireless/ath/ath11k/mhi.c
+++ b/drivers/net/wireless/ath/ath11k/mhi.c
@@ -235,6 +235,7 @@ int ath11k_mhi_register(struct ath11k_pci *ab_pci)
 	mhi_ctrl->cntrl_dev = ab->dev;
 	mhi_ctrl->fw_image = ab_pci->amss_path;
 	mhi_ctrl->regs = ab->mem;
+	mhi_ctrl->reg_len = ab->mem_len;
 
 	ret = ath11k_mhi_get_msi(ab_pci);
 	if (ret) {
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project



From bbhatt at codeaurora.org  Wed May  5 18:08:21 2021
From: bbhatt at codeaurora.org (Bhaumik Bhatt)
Date: Wed,  5 May 2021 10:08:21 -0700
Subject: [PATCH v3 6/6] bus: mhi: core: Add range checks for BHI and BHIe
In-Reply-To: <1620234501-30461-1-git-send-email-bbhatt@codeaurora.org>
References: <1620234501-30461-1-git-send-email-bbhatt@codeaurora.org>
Message-ID: <1620234501-30461-7-git-send-email-bbhatt@codeaurora.org>

When obtaining the BHI or BHIe offsets during the power up
preparation phase, range checks are missing. These can help
controller drivers avoid accessing any address outside of the
MMIO region. Ensure that mhi_cntrl->reg_len is set before MHI
registration as it is a required field and range checks will
fail without it.

Signed-off-by: Bhaumik Bhatt <bbhatt at codeaurora.org>
Reviewed-by: Jeffrey Hugo <quic_jhugo at quicinc.com>
---
 drivers/bus/mhi/core/init.c | 15 ++++++++++++++-
 1 file changed, 14 insertions(+), 1 deletion(-)

diff --git a/drivers/bus/mhi/core/init.c b/drivers/bus/mhi/core/init.c
index 1cc2f22..86ad06e 100644
--- a/drivers/bus/mhi/core/init.c
+++ b/drivers/bus/mhi/core/init.c
@@ -885,7 +885,8 @@ int mhi_register_controller(struct mhi_controller *mhi_cntrl,
 	if (!mhi_cntrl || !mhi_cntrl->cntrl_dev || !mhi_cntrl->regs ||
 	    !mhi_cntrl->runtime_get || !mhi_cntrl->runtime_put ||
 	    !mhi_cntrl->status_cb || !mhi_cntrl->read_reg ||
-	    !mhi_cntrl->write_reg || !mhi_cntrl->nr_irqs || !mhi_cntrl->irq)
+	    !mhi_cntrl->write_reg || !mhi_cntrl->nr_irqs ||
+	    !mhi_cntrl->irq || !mhi_cntrl->reg_len)
 		return -EINVAL;
 
 	ret = parse_config(mhi_cntrl, config);
@@ -1077,6 +1078,12 @@ int mhi_prepare_for_power_up(struct mhi_controller *mhi_cntrl)
 		dev_err(dev, "Error getting BHI offset\n");
 		goto error_reg_offset;
 	}
+
+	if (bhi_off >= mhi_cntrl->reg_len) {
+		dev_err(dev, "BHI offset is out of range\n");
+		ret = -EINVAL;
+		goto error_reg_offset;
+	}
 	mhi_cntrl->bhi = mhi_cntrl->regs + bhi_off;
 
 	if (mhi_cntrl->fbc_download || mhi_cntrl->rddm_size) {
@@ -1086,6 +1093,12 @@ int mhi_prepare_for_power_up(struct mhi_controller *mhi_cntrl)
 			dev_err(dev, "Error getting BHIE offset\n");
 			goto error_reg_offset;
 		}
+
+		if (bhie_off >= mhi_cntrl->reg_len) {
+			dev_err(dev, "BHIe offset is out of range\n");
+			ret = -EINVAL;
+			goto error_reg_offset;
+		}
 		mhi_cntrl->bhie = mhi_cntrl->regs + bhie_off;
 	}
 
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project



From hemantk at codeaurora.org  Thu May  6 01:12:14 2021
From: hemantk at codeaurora.org (Hemant Kumar)
Date: Wed, 5 May 2021 17:12:14 -0700
Subject: [PATCH v3 6/6] bus: mhi: core: Add range checks for BHI and BHIe
In-Reply-To: <1620234501-30461-7-git-send-email-bbhatt@codeaurora.org>
References: <1620234501-30461-1-git-send-email-bbhatt@codeaurora.org>
 <1620234501-30461-7-git-send-email-bbhatt@codeaurora.org>
Message-ID: <4eb740c7-d95f-8962-a06e-677404ebe84d@codeaurora.org>

Hi Bhaumik,

On 5/5/21 10:08 AM, Bhaumik Bhatt wrote:
> When obtaining the BHI or BHIe offsets during the power up
> preparation phase, range checks are missing. These can help
> controller drivers avoid accessing any address outside of the
> MMIO region. Ensure that mhi_cntrl->reg_len is set before MHI
> registration as it is a required field and range checks will
> fail without it.
> 
> Signed-off-by: Bhaumik Bhatt <bbhatt at codeaurora.org>
> Reviewed-by: Jeffrey Hugo <quic_jhugo at quicinc.com>
> ---
>   drivers/bus/mhi/core/init.c | 15 ++++++++++++++-
>   1 file changed, 14 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/bus/mhi/core/init.c b/drivers/bus/mhi/core/init.c
> index 1cc2f22..86ad06e 100644
> --- a/drivers/bus/mhi/core/init.c
> +++ b/drivers/bus/mhi/core/init.c
> @@ -885,7 +885,8 @@ int mhi_register_controller(struct mhi_controller *mhi_cntrl,
>   	if (!mhi_cntrl || !mhi_cntrl->cntrl_dev || !mhi_cntrl->regs ||
>   	    !mhi_cntrl->runtime_get || !mhi_cntrl->runtime_put ||
>   	    !mhi_cntrl->status_cb || !mhi_cntrl->read_reg ||
> -	    !mhi_cntrl->write_reg || !mhi_cntrl->nr_irqs || !mhi_cntrl->irq)
> +	    !mhi_cntrl->write_reg || !mhi_cntrl->nr_irqs ||
> +	    !mhi_cntrl->irq || !mhi_cntrl->reg_len)
>   		return -EINVAL;
>   
>   	ret = parse_config(mhi_cntrl, config);
> @@ -1077,6 +1078,12 @@ int mhi_prepare_for_power_up(struct mhi_controller *mhi_cntrl)
>   		dev_err(dev, "Error getting BHI offset\n");
>   		goto error_reg_offset;
>   	}
> +
> +	if (bhi_off >= mhi_cntrl->reg_len) {
> +		dev_err(dev, "BHI offset is out of range\n");
Does is make sense to also log bhi_off and/or reg_len values in error if 
it helps in debugging
> +		ret = -EINVAL;
> +		goto error_reg_offset;
> +	}
>   	mhi_cntrl->bhi = mhi_cntrl->regs + bhi_off;
>   
>   	if (mhi_cntrl->fbc_download || mhi_cntrl->rddm_size) {
> @@ -1086,6 +1093,12 @@ int mhi_prepare_for_power_up(struct mhi_controller *mhi_cntrl)
>   			dev_err(dev, "Error getting BHIE offset\n");
>   			goto error_reg_offset;
>   		}
> +
> +		if (bhie_off >= mhi_cntrl->reg_len) {
> +			dev_err(dev, "BHIe offset is out of range\n");
Same comment as above
> +			ret = -EINVAL;
> +			goto error_reg_offset;
> +		}
>   		mhi_cntrl->bhie = mhi_cntrl->regs + bhie_off;
>   	}
>   
> 

Thanks,
Hemant
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project


From hemantk at codeaurora.org  Thu May  6 01:14:17 2021
From: hemantk at codeaurora.org (Hemant Kumar)
Date: Wed, 5 May 2021 17:14:17 -0700
Subject: [PATCH v3 5/6] bus: mhi: pci_generic: Set register access length
 for MHI driver
In-Reply-To: <1620234501-30461-6-git-send-email-bbhatt@codeaurora.org>
References: <1620234501-30461-1-git-send-email-bbhatt@codeaurora.org>
 <1620234501-30461-6-git-send-email-bbhatt@codeaurora.org>
Message-ID: <eb0ead5a-94e6-d5c5-4450-04e4515b59b8@codeaurora.org>



On 5/5/21 10:08 AM, Bhaumik Bhatt wrote:
> MHI driver requires register space length to add range checks and
> prevent memory region accesses outside of that for MMIO space.
> Set it from the PCI generic controller driver before registering
> the MHI controller.
> 
> Signed-off-by: Bhaumik Bhatt <bbhatt at codeaurora.org>

Reviewed-by: Hemant Kumar <hemantk at codeaurora.org>

-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project


From hemantk at codeaurora.org  Thu May  6 01:15:08 2021
From: hemantk at codeaurora.org (Hemant Kumar)
Date: Wed, 5 May 2021 17:15:08 -0700
Subject: [PATCH v3 4/6] ath11k: set register access length for MHI driver
In-Reply-To: <1620234501-30461-5-git-send-email-bbhatt@codeaurora.org>
References: <1620234501-30461-1-git-send-email-bbhatt@codeaurora.org>
 <1620234501-30461-5-git-send-email-bbhatt@codeaurora.org>
Message-ID: <60e7a674-a5d1-e796-2911-a9680d0e26b2@codeaurora.org>



On 5/5/21 10:08 AM, Bhaumik Bhatt wrote:
> MHI driver requires register space length to add range checks and
> prevent memory region accesses outside of that for MMIO space.
> Set it before registering the MHI controller.
> 
> Signed-off-by: Bhaumik Bhatt <bbhatt at codeaurora.org>

Reviewed-by: Hemant Kumar <hemantk at codeaurora.org>

-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project


From hemantk at codeaurora.org  Thu May  6 01:16:07 2021
From: hemantk at codeaurora.org (Hemant Kumar)
Date: Wed, 5 May 2021 17:16:07 -0700
Subject: [PATCH v3 3/6] bus: mhi: Add MMIO region length to controller
 structure
In-Reply-To: <1620234501-30461-4-git-send-email-bbhatt@codeaurora.org>
References: <1620234501-30461-1-git-send-email-bbhatt@codeaurora.org>
 <1620234501-30461-4-git-send-email-bbhatt@codeaurora.org>
Message-ID: <1ed18dfe-19bc-440d-e524-0883768426b7@codeaurora.org>



On 5/5/21 10:08 AM, Bhaumik Bhatt wrote:
> Make controller driver specify the MMIO register region length
> for range checking of BHI or BHIe space. This can help validate
> that offsets are in acceptable memory region or not and avoid any
> boot-up issues due to BHI or BHIe memory accesses.
> 
> Signed-off-by: Bhaumik Bhatt <bbhatt at codeaurora.org>
> Reviewed-by: Jeffrey Hugo <quic_jhugo at quicinc.com>

Reviewed-by: Hemant Kumar <hemantk at codeaurora.org>
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project


From hemantk at codeaurora.org  Thu May  6 01:17:23 2021
From: hemantk at codeaurora.org (Hemant Kumar)
Date: Wed, 5 May 2021 17:17:23 -0700
Subject: [PATCH v3 2/6] bus: mhi: core: Set BHI and BHIe pointers to NULL
 in clean-up
In-Reply-To: <1620234501-30461-3-git-send-email-bbhatt@codeaurora.org>
References: <1620234501-30461-1-git-send-email-bbhatt@codeaurora.org>
 <1620234501-30461-3-git-send-email-bbhatt@codeaurora.org>
Message-ID: <747f0641-ebc1-7edf-35c1-0268c1134791@codeaurora.org>



On 5/5/21 10:08 AM, Bhaumik Bhatt wrote:
> Set the BHI and BHIe pointers to NULL as part of clean-up. This
> makes sure that stale pointers are not accessed after powering
> MHI down.
> 
> Suggested-by: Hemant Kumar <hemantk at codeaurora.org>
> Signed-off-by: Bhaumik Bhatt <bbhatt at codeaurora.org>
> Reviewed-by: Jeffrey Hugo <quic_jhugo at quicinc.com>

Reviewed-by: Hemant Kumar <hemantk at codeaurora.org>
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project


From hemantk at codeaurora.org  Thu May  6 01:25:26 2021
From: hemantk at codeaurora.org (Hemant Kumar)
Date: Wed, 5 May 2021 17:25:26 -0700
Subject: [PATCH v3 1/6] bus: mhi: core: Set BHI/BHIe offsets on power up
 preparation
In-Reply-To: <1620234501-30461-2-git-send-email-bbhatt@codeaurora.org>
References: <1620234501-30461-1-git-send-email-bbhatt@codeaurora.org>
 <1620234501-30461-2-git-send-email-bbhatt@codeaurora.org>
Message-ID: <d4371467-f9ea-a143-a1a0-3ce4bc86c6ed@codeaurora.org>



On 5/5/21 10:08 AM, Bhaumik Bhatt wrote:
> Set the BHI and/or BHIe offsets in mhi_prepare_for_power_up(),
> rearrange the function, and remove the equivalent from
> mhi_async_power_up(). This helps consolidate multiple checks
> in different parts of the driver and can help MHI fail early on
> before power up begins if the offsets are not read correctly.
> 
> Signed-off-by: Bhaumik Bhatt <bbhatt at codeaurora.org>
> Reviewed-by: Jeffrey Hugo <quic_jhugo at quicinc.com>

Reviewed-by: Hemant Kumar <hemantk at codeaurora.org>

-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project


From loic.poulain at linaro.org  Thu May  6 09:03:53 2021
From: loic.poulain at linaro.org (Loic Poulain)
Date: Thu, 6 May 2021 10:03:53 +0200
Subject: [PATCH v3 5/6] bus: mhi: pci_generic: Set register access length
 for MHI driver
In-Reply-To: <1620234501-30461-6-git-send-email-bbhatt@codeaurora.org>
References: <1620234501-30461-1-git-send-email-bbhatt@codeaurora.org>
 <1620234501-30461-6-git-send-email-bbhatt@codeaurora.org>
Message-ID: <CAMZdPi8_MKyF8imaOc+9MGz4ifOKX=UMA1CzHe3aPuXC2BEoOg@mail.gmail.com>

On Wed, 5 May 2021 at 19:08, Bhaumik Bhatt <bbhatt at codeaurora.org> wrote:
>
> MHI driver requires register space length to add range checks and
> prevent memory region accesses outside of that for MMIO space.
> Set it from the PCI generic controller driver before registering
> the MHI controller.
>
> Signed-off-by: Bhaumik Bhatt <bbhatt at codeaurora.org>

Reviewed-by: Loic Poulain <loic.poulain at linaro.org>


From tmariyap at codeaurora.org  Thu May  6 18:49:06 2021
From: tmariyap at codeaurora.org (Thiraviyam Mariyappan)
Date: Thu, 06 May 2021 23:19:06 +0530
Subject: [PATCHv2] mac80211: increment rx stats according to USES_RSS flag
In-Reply-To: <ec30381c062e3eb87abb724641a15331cfc3d11c.camel@sipsolutions.net>
References: <1613563010-1489-1-git-send-email-tmariyap@codeaurora.org>
 (sfid-20210217_125904_154301_738B3086)
 <c0aef41d2ecf09188de372fe4f7d6b1954e54e07.camel@sipsolutions.net>
 <1ee8d562986128767c037d20aedb96a5@codeaurora.org>
 <ec30381c062e3eb87abb724641a15331cfc3d11c.camel@sipsolutions.net>
Message-ID: <df6e33fe198e179f1c1f31ca6d55e995@codeaurora.org>

On 2021-04-23 13:28, Johannes Berg wrote:
> On Wed, 2021-04-21 at 22:18 +0530, Thiraviyam Mariyappan wrote:
>> In case of Mesh fast_rx is not applicable, but still USES_RSS can be
>> enabled from driver when parallel RX is supported by HW/Driver,
>> right??
> 
> Yes, I guess that's true.
> 
>> Hence checked for USES_RSS support to update per cpu stats.Please
>> correct me if the meaning of USES_RSS is misunderstood and it applies
>> only when fast_rx for a STA is enabled.
>> 
> 
> Well, actually using multi-queue is pointless or even 
> counter-productive
> when you don't have fast-RX, since then you'll run into a common lock,
> and doing much processing on multiple CPUs but under a common lock 
> might
> well be worse than doing it on a single CPU in the first place, since
> you'll bounce the lock around all the time.
> 
> However, you're right that the driver might generally advertise
> USES_RSS, but then not do it for mesh, but that throws off some
> statistics.
> 
> Something like this might then be a much better fix though?
Below fix good to me and working fine.
> 
> 
> diff --git a/net/mac80211/sta_info.c b/net/mac80211/sta_info.c
> index ec6973ee88ef..f87e883862d9 100644
> --- a/net/mac80211/sta_info.c
> +++ b/net/mac80211/sta_info.c
> @@ -2092,7 +2092,7 @@ sta_get_last_rx_stats(struct sta_info *sta)
>  	struct ieee80211_local *local = sta->local;
>  	int cpu;
> 
> -	if (!ieee80211_hw_check(&local->hw, USES_RSS))
> +	if (!sta->pcpu_rx_stats)
>  		return stats;
> 
>  	for_each_possible_cpu(cpu) {
> @@ -2192,9 +2192,7 @@ static void sta_set_tidstats(struct sta_info 
> *sta,
>  	int cpu;
> 
>  	if (!(tidstats->filled & BIT(NL80211_TID_STATS_RX_MSDU))) {
> -		if (!ieee80211_hw_check(&local->hw, USES_RSS))
> -			tidstats->rx_msdu +=
> -				sta_get_tidstats_msdu(&sta->rx_stats, tid);
> +		tidstats->rx_msdu += sta_get_tidstats_msdu(&sta->rx_stats, tid);
> 
>  		if (sta->pcpu_rx_stats) {
>  			for_each_possible_cpu(cpu) {
> @@ -2308,8 +2306,7 @@ void sta_set_sinfo(struct sta_info *sta, struct
> station_info *sinfo,
> 
>  	if (!(sinfo->filled & (BIT_ULL(NL80211_STA_INFO_RX_BYTES64) |
>  			       BIT_ULL(NL80211_STA_INFO_RX_BYTES)))) {
> -		if (!ieee80211_hw_check(&local->hw, USES_RSS))
> -			sinfo->rx_bytes += sta_get_stats_bytes(&sta->rx_stats);
> +		sinfo->rx_bytes += sta_get_stats_bytes(&sta->rx_stats);
> 
>  		if (sta->pcpu_rx_stats) {
>  			for_each_possible_cpu(cpu) {
> 
> 
> johannes


From bbhatt at qti.qualcomm.com  Thu May  6 20:32:19 2021
From: bbhatt at qti.qualcomm.com (Bhaumik Bhatt)
Date: Thu,  6 May 2021 12:32:19 -0700
Subject: [PATCH v4 0/6] BHI/BHIe improvements for MHI power purposes
Message-ID: <1620329545-32328-1-git-send-email-bbhatt@qti.qualcomm.com>

This patch series improves the power up behavior by allowing MHI host driver to
set BHI and/or BHIe offsets early on in the preparation phase and fail pre-power
up if offsets are not found or not within a limited MMIO region. This also
allows MHI host to clean up the offsets in the unprepare after power down phase.

Going forward, controllers will be required to specify a reg_len field which
will be used to check whether the BHI/BHIe offsets are in range or not.

This series has been tested on X86_64 architecture with the PCI generic driver
as controller and an SDX55 device.

v4:
-Added reviewed-by tags
-Updated range check patch to include BHI/e offsets in the error message

v3:
-Added reviewed-by tags
-Updated order of reg_len in mhi_controller structure documentation

v2:
-Added reviewed-by tags
-Moved reg_len entry in mhi_controller structure to allow for a packed struct

Bhaumik Bhatt (6):
  bus: mhi: core: Set BHI/BHIe offsets on power up preparation
  bus: mhi: core: Set BHI and BHIe pointers to NULL in clean-up
  bus: mhi: Add MMIO region length to controller structure
  ath11k: set register access length for MHI driver
  bus: mhi: pci_generic: Set register access length for MHI driver
  bus: mhi: core: Add range checks for BHI and BHIe

 drivers/bus/mhi/core/init.c           | 61 ++++++++++++++++++++++++-----------
 drivers/bus/mhi/core/pm.c             | 28 +++-------------
 drivers/bus/mhi/pci_generic.c         |  1 +
 drivers/net/wireless/ath/ath11k/mhi.c |  1 +
 include/linux/mhi.h                   |  2 ++
 5 files changed, 50 insertions(+), 43 deletions(-)

-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project



From bbhatt at qti.qualcomm.com  Thu May  6 20:32:20 2021
From: bbhatt at qti.qualcomm.com (Bhaumik Bhatt)
Date: Thu,  6 May 2021 12:32:20 -0700
Subject: [PATCH v4 1/6] bus: mhi: core: Set BHI/BHIe offsets on power up
 preparation
In-Reply-To: <1620329545-32328-1-git-send-email-bbhatt@qti.qualcomm.com>
References: <1620329545-32328-1-git-send-email-bbhatt@qti.qualcomm.com>
Message-ID: <1620329545-32328-2-git-send-email-bbhatt@qti.qualcomm.com>

From: Bhaumik Bhatt <bbhatt at codeaurora.org>

Set the BHI and/or BHIe offsets in mhi_prepare_for_power_up(),
rearrange the function, and remove the equivalent from
mhi_async_power_up(). This helps consolidate multiple checks
in different parts of the driver and can help MHI fail early on
before power up begins if the offsets are not read correctly.

Signed-off-by: Bhaumik Bhatt <bbhatt at codeaurora.org>
Reviewed-by: Jeffrey Hugo <quic_jhugo at quicinc.com>
Reviewed-by: Hemant Kumar <hemantk at codeaurora.org>
---
 drivers/bus/mhi/core/init.c | 42 +++++++++++++++++++++++-------------------
 drivers/bus/mhi/core/pm.c   | 28 ++++------------------------
 2 files changed, 27 insertions(+), 43 deletions(-)

diff --git a/drivers/bus/mhi/core/init.c b/drivers/bus/mhi/core/init.c
index c81b377..11c7a3d 100644
--- a/drivers/bus/mhi/core/init.c
+++ b/drivers/bus/mhi/core/init.c
@@ -1063,7 +1063,7 @@ EXPORT_SYMBOL_GPL(mhi_free_controller);
 int mhi_prepare_for_power_up(struct mhi_controller *mhi_cntrl)
 {
 	struct device *dev = &mhi_cntrl->mhi_dev->dev;
-	u32 bhie_off;
+	u32 bhi_off, bhie_off;
 	int ret;
 
 	mutex_lock(&mhi_cntrl->pm_mutex);
@@ -1072,29 +1072,36 @@ int mhi_prepare_for_power_up(struct mhi_controller *mhi_cntrl)
 	if (ret)
 		goto error_dev_ctxt;
 
-	/*
-	 * Allocate RDDM table if specified, this table is for debugging purpose
-	 */
-	if (mhi_cntrl->rddm_size) {
-		mhi_alloc_bhie_table(mhi_cntrl, &mhi_cntrl->rddm_image,
-				     mhi_cntrl->rddm_size);
+	ret = mhi_read_reg(mhi_cntrl, mhi_cntrl->regs, BHIOFF, &bhi_off);
+	if (ret) {
+		dev_err(dev, "Error getting BHI offset\n");
+		goto error_reg_offset;
+	}
+	mhi_cntrl->bhi = mhi_cntrl->regs + bhi_off;
 
-		/*
-		 * This controller supports RDDM, so we need to manually clear
-		 * BHIE RX registers since POR values are undefined.
-		 */
+	if (mhi_cntrl->fbc_download || mhi_cntrl->rddm_size) {
 		ret = mhi_read_reg(mhi_cntrl, mhi_cntrl->regs, BHIEOFF,
 				   &bhie_off);
 		if (ret) {
 			dev_err(dev, "Error getting BHIE offset\n");
-			goto bhie_error;
+			goto error_reg_offset;
 		}
-
 		mhi_cntrl->bhie = mhi_cntrl->regs + bhie_off;
+	}
+
+	if (mhi_cntrl->rddm_size) {
+		/*
+		 * This controller supports RDDM, so we need to manually clear
+		 * BHIE RX registers since POR values are undefined.
+		 */
 		memset_io(mhi_cntrl->bhie + BHIE_RXVECADDR_LOW_OFFS,
 			  0, BHIE_RXVECSTATUS_OFFS - BHIE_RXVECADDR_LOW_OFFS +
 			  4);
-
+		/*
+		 * Allocate RDDM table for debugging purpose if specified
+		 */
+		mhi_alloc_bhie_table(mhi_cntrl, &mhi_cntrl->rddm_image,
+				     mhi_cntrl->rddm_size);
 		if (mhi_cntrl->rddm_image)
 			mhi_rddm_prepare(mhi_cntrl, mhi_cntrl->rddm_image);
 	}
@@ -1103,11 +1110,8 @@ int mhi_prepare_for_power_up(struct mhi_controller *mhi_cntrl)
 
 	return 0;
 
-bhie_error:
-	if (mhi_cntrl->rddm_image) {
-		mhi_free_bhie_table(mhi_cntrl, mhi_cntrl->rddm_image);
-		mhi_cntrl->rddm_image = NULL;
-	}
+error_reg_offset:
+	mhi_deinit_dev_ctxt(mhi_cntrl);
 
 error_dev_ctxt:
 	mutex_unlock(&mhi_cntrl->pm_mutex);
diff --git a/drivers/bus/mhi/core/pm.c b/drivers/bus/mhi/core/pm.c
index e2e59a3..adf426c 100644
--- a/drivers/bus/mhi/core/pm.c
+++ b/drivers/bus/mhi/core/pm.c
@@ -1066,28 +1066,8 @@ int mhi_async_power_up(struct mhi_controller *mhi_cntrl)
 	if (ret)
 		goto error_setup_irq;
 
-	/* Setup BHI offset & INTVEC */
+	/* Setup BHI INTVEC */
 	write_lock_irq(&mhi_cntrl->pm_lock);
-	ret = mhi_read_reg(mhi_cntrl, mhi_cntrl->regs, BHIOFF, &val);
-	if (ret) {
-		write_unlock_irq(&mhi_cntrl->pm_lock);
-		goto error_bhi_offset;
-	}
-
-	mhi_cntrl->bhi = mhi_cntrl->regs + val;
-
-	/* Setup BHIE offset */
-	if (mhi_cntrl->fbc_download) {
-		ret = mhi_read_reg(mhi_cntrl, mhi_cntrl->regs, BHIEOFF, &val);
-		if (ret) {
-			write_unlock_irq(&mhi_cntrl->pm_lock);
-			dev_err(dev, "Error reading BHIE offset\n");
-			goto error_bhi_offset;
-		}
-
-		mhi_cntrl->bhie = mhi_cntrl->regs + val;
-	}
-
 	mhi_write_reg(mhi_cntrl, mhi_cntrl->bhi, BHI_INTVEC, 0);
 	mhi_cntrl->pm_state = MHI_PM_POR;
 	mhi_cntrl->ee = MHI_EE_MAX;
@@ -1098,7 +1078,7 @@ int mhi_async_power_up(struct mhi_controller *mhi_cntrl)
 	if (!MHI_IN_PBL(current_ee) && current_ee != MHI_EE_AMSS) {
 		dev_err(dev, "Not a valid EE for power on\n");
 		ret = -EIO;
-		goto error_bhi_offset;
+		goto error_async_power_up;
 	}
 
 	state = mhi_get_mhi_state(mhi_cntrl);
@@ -1117,7 +1097,7 @@ int mhi_async_power_up(struct mhi_controller *mhi_cntrl)
 		if (!ret) {
 			ret = -EIO;
 			dev_info(dev, "Failed to reset MHI due to syserr state\n");
-			goto error_bhi_offset;
+			goto error_async_power_up;
 		}
 
 		/*
@@ -1139,7 +1119,7 @@ int mhi_async_power_up(struct mhi_controller *mhi_cntrl)
 
 	return 0;
 
-error_bhi_offset:
+error_async_power_up:
 	mhi_deinit_free_irq(mhi_cntrl);
 
 error_setup_irq:
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project



From bbhatt at qti.qualcomm.com  Thu May  6 20:32:21 2021
From: bbhatt at qti.qualcomm.com (Bhaumik Bhatt)
Date: Thu,  6 May 2021 12:32:21 -0700
Subject: [PATCH v4 2/6] bus: mhi: core: Set BHI and BHIe pointers to NULL in
 clean-up
In-Reply-To: <1620329545-32328-1-git-send-email-bbhatt@qti.qualcomm.com>
References: <1620329545-32328-1-git-send-email-bbhatt@qti.qualcomm.com>
Message-ID: <1620329545-32328-3-git-send-email-bbhatt@qti.qualcomm.com>

From: Bhaumik Bhatt <bbhatt at codeaurora.org>

Set the BHI and BHIe pointers to NULL as part of clean-up. This
makes sure that stale pointers are not accessed after powering
MHI down.

Suggested-by: Hemant Kumar <hemantk at codeaurora.org>
Signed-off-by: Bhaumik Bhatt <bbhatt at codeaurora.org>
Reviewed-by: Jeffrey Hugo <quic_jhugo at quicinc.com>
Reviewed-by: Hemant Kumar <hemantk at codeaurora.org>
---
 drivers/bus/mhi/core/init.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/bus/mhi/core/init.c b/drivers/bus/mhi/core/init.c
index 11c7a3d..1cc2f22 100644
--- a/drivers/bus/mhi/core/init.c
+++ b/drivers/bus/mhi/core/init.c
@@ -1132,6 +1132,9 @@ void mhi_unprepare_after_power_down(struct mhi_controller *mhi_cntrl)
 		mhi_cntrl->rddm_image = NULL;
 	}
 
+	mhi_cntrl->bhi = NULL;
+	mhi_cntrl->bhie = NULL;
+
 	mhi_deinit_dev_ctxt(mhi_cntrl);
 }
 EXPORT_SYMBOL_GPL(mhi_unprepare_after_power_down);
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project



From bbhatt at qti.qualcomm.com  Thu May  6 20:32:24 2021
From: bbhatt at qti.qualcomm.com (Bhaumik Bhatt)
Date: Thu,  6 May 2021 12:32:24 -0700
Subject: [PATCH v4 5/6] bus: mhi: pci_generic: Set register access length for
 MHI driver
In-Reply-To: <1620329545-32328-1-git-send-email-bbhatt@qti.qualcomm.com>
References: <1620329545-32328-1-git-send-email-bbhatt@qti.qualcomm.com>
Message-ID: <1620329545-32328-6-git-send-email-bbhatt@qti.qualcomm.com>

From: Bhaumik Bhatt <bbhatt at codeaurora.org>

MHI driver requires register space length to add range checks and
prevent memory region accesses outside of that for MMIO space.
Set it from the PCI generic controller driver before registering
the MHI controller.

Signed-off-by: Bhaumik Bhatt <bbhatt at codeaurora.org>
Reviewed-by: Hemant Kumar <hemantk at codeaurora.org>
Reviewed-by: Loic Poulain <loic.poulain at linaro.org>
---
 drivers/bus/mhi/pci_generic.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/bus/mhi/pci_generic.c b/drivers/bus/mhi/pci_generic.c
index 7c810f0..fb7889f 100644
--- a/drivers/bus/mhi/pci_generic.c
+++ b/drivers/bus/mhi/pci_generic.c
@@ -463,6 +463,7 @@ static int mhi_pci_claim(struct mhi_controller *mhi_cntrl,
 		return err;
 	}
 	mhi_cntrl->regs = pcim_iomap_table(pdev)[bar_num];
+	mhi_cntrl->reg_len = pci_resource_len(pdev, bar_num);
 
 	err = pci_set_dma_mask(pdev, dma_mask);
 	if (err) {
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project



From bbhatt at qti.qualcomm.com  Thu May  6 20:32:23 2021
From: bbhatt at qti.qualcomm.com (Bhaumik Bhatt)
Date: Thu,  6 May 2021 12:32:23 -0700
Subject: [PATCH v4 4/6] ath11k: set register access length for MHI driver
In-Reply-To: <1620329545-32328-1-git-send-email-bbhatt@qti.qualcomm.com>
References: <1620329545-32328-1-git-send-email-bbhatt@qti.qualcomm.com>
Message-ID: <1620329545-32328-5-git-send-email-bbhatt@qti.qualcomm.com>

From: Bhaumik Bhatt <bbhatt at codeaurora.org>

MHI driver requires register space length to add range checks and
prevent memory region accesses outside of that for MMIO space.
Set it before registering the MHI controller.

Signed-off-by: Bhaumik Bhatt <bbhatt at codeaurora.org>
Reviewed-by: Hemant Kumar <hemantk at codeaurora.org>
---
 drivers/net/wireless/ath/ath11k/mhi.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/net/wireless/ath/ath11k/mhi.c b/drivers/net/wireless/ath/ath11k/mhi.c
index 09858e5..c0f013c 100644
--- a/drivers/net/wireless/ath/ath11k/mhi.c
+++ b/drivers/net/wireless/ath/ath11k/mhi.c
@@ -235,6 +235,7 @@ int ath11k_mhi_register(struct ath11k_pci *ab_pci)
 	mhi_ctrl->cntrl_dev = ab->dev;
 	mhi_ctrl->fw_image = ab_pci->amss_path;
 	mhi_ctrl->regs = ab->mem;
+	mhi_ctrl->reg_len = ab->mem_len;
 
 	ret = ath11k_mhi_get_msi(ab_pci);
 	if (ret) {
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project



From bbhatt at qti.qualcomm.com  Thu May  6 20:32:25 2021
From: bbhatt at qti.qualcomm.com (Bhaumik Bhatt)
Date: Thu,  6 May 2021 12:32:25 -0700
Subject: [PATCH v4 6/6] bus: mhi: core: Add range checks for BHI and BHIe
In-Reply-To: <1620329545-32328-1-git-send-email-bbhatt@qti.qualcomm.com>
References: <1620329545-32328-1-git-send-email-bbhatt@qti.qualcomm.com>
Message-ID: <1620329545-32328-7-git-send-email-bbhatt@qti.qualcomm.com>

From: Bhaumik Bhatt <bbhatt at codeaurora.org>

When obtaining the BHI or BHIe offsets during the power up
preparation phase, range checks are missing. These can help
controller drivers avoid accessing any address outside of the
MMIO region. Ensure that mhi_cntrl->reg_len is set before MHI
registration as it is a required field and range checks will
fail without it.

Signed-off-by: Bhaumik Bhatt <bbhatt at codeaurora.org>
Reviewed-by: Jeffrey Hugo <quic_jhugo at quicinc.com>
---
 drivers/bus/mhi/core/init.c | 18 +++++++++++++++++-
 1 file changed, 17 insertions(+), 1 deletion(-)

diff --git a/drivers/bus/mhi/core/init.c b/drivers/bus/mhi/core/init.c
index 1cc2f22..aeb1e3c 100644
--- a/drivers/bus/mhi/core/init.c
+++ b/drivers/bus/mhi/core/init.c
@@ -885,7 +885,8 @@ int mhi_register_controller(struct mhi_controller *mhi_cntrl,
 	if (!mhi_cntrl || !mhi_cntrl->cntrl_dev || !mhi_cntrl->regs ||
 	    !mhi_cntrl->runtime_get || !mhi_cntrl->runtime_put ||
 	    !mhi_cntrl->status_cb || !mhi_cntrl->read_reg ||
-	    !mhi_cntrl->write_reg || !mhi_cntrl->nr_irqs || !mhi_cntrl->irq)
+	    !mhi_cntrl->write_reg || !mhi_cntrl->nr_irqs ||
+	    !mhi_cntrl->irq || !mhi_cntrl->reg_len)
 		return -EINVAL;
 
 	ret = parse_config(mhi_cntrl, config);
@@ -1077,6 +1078,13 @@ int mhi_prepare_for_power_up(struct mhi_controller *mhi_cntrl)
 		dev_err(dev, "Error getting BHI offset\n");
 		goto error_reg_offset;
 	}
+
+	if (bhi_off >= mhi_cntrl->reg_len) {
+		dev_err(dev, "BHI offset: 0x%x is out of range: 0x%zx\n",
+			bhi_off, mhi_cntrl->reg_len);
+		ret = -EINVAL;
+		goto error_reg_offset;
+	}
 	mhi_cntrl->bhi = mhi_cntrl->regs + bhi_off;
 
 	if (mhi_cntrl->fbc_download || mhi_cntrl->rddm_size) {
@@ -1086,6 +1094,14 @@ int mhi_prepare_for_power_up(struct mhi_controller *mhi_cntrl)
 			dev_err(dev, "Error getting BHIE offset\n");
 			goto error_reg_offset;
 		}
+
+		if (bhie_off >= mhi_cntrl->reg_len) {
+			dev_err(dev,
+				"BHIe offset: 0x%x is out of range: 0x%zx\n",
+				bhie_off, mhi_cntrl->reg_len);
+			ret = -EINVAL;
+			goto error_reg_offset;
+		}
 		mhi_cntrl->bhie = mhi_cntrl->regs + bhie_off;
 	}
 
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project



From bbhatt at qti.qualcomm.com  Thu May  6 20:32:22 2021
From: bbhatt at qti.qualcomm.com (Bhaumik Bhatt)
Date: Thu,  6 May 2021 12:32:22 -0700
Subject: [PATCH v4 3/6] bus: mhi: Add MMIO region length to controller
 structure
In-Reply-To: <1620329545-32328-1-git-send-email-bbhatt@qti.qualcomm.com>
References: <1620329545-32328-1-git-send-email-bbhatt@qti.qualcomm.com>
Message-ID: <1620329545-32328-4-git-send-email-bbhatt@qti.qualcomm.com>

From: Bhaumik Bhatt <bbhatt at codeaurora.org>

Make controller driver specify the MMIO register region length
for range checking of BHI or BHIe space. This can help validate
that offsets are in acceptable memory region or not and avoid any
boot-up issues due to BHI or BHIe memory accesses.

Signed-off-by: Bhaumik Bhatt <bbhatt at codeaurora.org>
Reviewed-by: Jeffrey Hugo <quic_jhugo at quicinc.com>
Reviewed-by: Hemant Kumar <hemantk at codeaurora.org>
---
 include/linux/mhi.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/linux/mhi.h b/include/linux/mhi.h
index 944aa3a..9c347f5 100644
--- a/include/linux/mhi.h
+++ b/include/linux/mhi.h
@@ -303,6 +303,7 @@ struct mhi_controller_config {
  * @rddm_size: RAM dump size that host should allocate for debugging purpose
  * @sbl_size: SBL image size downloaded through BHIe (optional)
  * @seg_len: BHIe vector size (optional)
+ * @reg_len: Length of the MHI MMIO region (required)
  * @fbc_image: Points to firmware image buffer
  * @rddm_image: Points to RAM dump buffer
  * @mhi_chan: Points to the channel configuration table
@@ -386,6 +387,7 @@ struct mhi_controller {
 	size_t rddm_size;
 	size_t sbl_size;
 	size_t seg_len;
+	size_t reg_len;
 	struct image_info *fbc_image;
 	struct image_info *rddm_image;
 	struct mhi_chan *mhi_chan;
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project



From bbhatt at codeaurora.org  Thu May  6 20:51:44 2021
From: bbhatt at codeaurora.org (Bhaumik Bhatt)
Date: Thu,  6 May 2021 12:51:44 -0700
Subject: [PATCH v4 5/6] bus: mhi: pci_generic: Set register access length for
 MHI driver
In-Reply-To: <1620330705-40192-1-git-send-email-bbhatt@codeaurora.org>
References: <1620330705-40192-1-git-send-email-bbhatt@codeaurora.org>
Message-ID: <1620330705-40192-6-git-send-email-bbhatt@codeaurora.org>

MHI driver requires register space length to add range checks and
prevent memory region accesses outside of that for MMIO space.
Set it from the PCI generic controller driver before registering
the MHI controller.

Signed-off-by: Bhaumik Bhatt <bbhatt at codeaurora.org>
Reviewed-by: Hemant Kumar <hemantk at codeaurora.org>
Reviewed-by: Loic Poulain <loic.poulain at linaro.org>
---
 drivers/bus/mhi/pci_generic.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/bus/mhi/pci_generic.c b/drivers/bus/mhi/pci_generic.c
index 7c810f0..fb7889f 100644
--- a/drivers/bus/mhi/pci_generic.c
+++ b/drivers/bus/mhi/pci_generic.c
@@ -463,6 +463,7 @@ static int mhi_pci_claim(struct mhi_controller *mhi_cntrl,
 		return err;
 	}
 	mhi_cntrl->regs = pcim_iomap_table(pdev)[bar_num];
+	mhi_cntrl->reg_len = pci_resource_len(pdev, bar_num);
 
 	err = pci_set_dma_mask(pdev, dma_mask);
 	if (err) {
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project



From bbhatt at codeaurora.org  Thu May  6 20:51:40 2021
From: bbhatt at codeaurora.org (Bhaumik Bhatt)
Date: Thu,  6 May 2021 12:51:40 -0700
Subject: [PATCH v4 1/6] bus: mhi: core: Set BHI/BHIe offsets on power up
 preparation
In-Reply-To: <1620330705-40192-1-git-send-email-bbhatt@codeaurora.org>
References: <1620330705-40192-1-git-send-email-bbhatt@codeaurora.org>
Message-ID: <1620330705-40192-2-git-send-email-bbhatt@codeaurora.org>

Set the BHI and/or BHIe offsets in mhi_prepare_for_power_up(),
rearrange the function, and remove the equivalent from
mhi_async_power_up(). This helps consolidate multiple checks
in different parts of the driver and can help MHI fail early on
before power up begins if the offsets are not read correctly.

Signed-off-by: Bhaumik Bhatt <bbhatt at codeaurora.org>
Reviewed-by: Jeffrey Hugo <quic_jhugo at quicinc.com>
Reviewed-by: Hemant Kumar <hemantk at codeaurora.org>
---
 drivers/bus/mhi/core/init.c | 42 +++++++++++++++++++++++-------------------
 drivers/bus/mhi/core/pm.c   | 28 ++++------------------------
 2 files changed, 27 insertions(+), 43 deletions(-)

diff --git a/drivers/bus/mhi/core/init.c b/drivers/bus/mhi/core/init.c
index c81b377..11c7a3d 100644
--- a/drivers/bus/mhi/core/init.c
+++ b/drivers/bus/mhi/core/init.c
@@ -1063,7 +1063,7 @@ EXPORT_SYMBOL_GPL(mhi_free_controller);
 int mhi_prepare_for_power_up(struct mhi_controller *mhi_cntrl)
 {
 	struct device *dev = &mhi_cntrl->mhi_dev->dev;
-	u32 bhie_off;
+	u32 bhi_off, bhie_off;
 	int ret;
 
 	mutex_lock(&mhi_cntrl->pm_mutex);
@@ -1072,29 +1072,36 @@ int mhi_prepare_for_power_up(struct mhi_controller *mhi_cntrl)
 	if (ret)
 		goto error_dev_ctxt;
 
-	/*
-	 * Allocate RDDM table if specified, this table is for debugging purpose
-	 */
-	if (mhi_cntrl->rddm_size) {
-		mhi_alloc_bhie_table(mhi_cntrl, &mhi_cntrl->rddm_image,
-				     mhi_cntrl->rddm_size);
+	ret = mhi_read_reg(mhi_cntrl, mhi_cntrl->regs, BHIOFF, &bhi_off);
+	if (ret) {
+		dev_err(dev, "Error getting BHI offset\n");
+		goto error_reg_offset;
+	}
+	mhi_cntrl->bhi = mhi_cntrl->regs + bhi_off;
 
-		/*
-		 * This controller supports RDDM, so we need to manually clear
-		 * BHIE RX registers since POR values are undefined.
-		 */
+	if (mhi_cntrl->fbc_download || mhi_cntrl->rddm_size) {
 		ret = mhi_read_reg(mhi_cntrl, mhi_cntrl->regs, BHIEOFF,
 				   &bhie_off);
 		if (ret) {
 			dev_err(dev, "Error getting BHIE offset\n");
-			goto bhie_error;
+			goto error_reg_offset;
 		}
-
 		mhi_cntrl->bhie = mhi_cntrl->regs + bhie_off;
+	}
+
+	if (mhi_cntrl->rddm_size) {
+		/*
+		 * This controller supports RDDM, so we need to manually clear
+		 * BHIE RX registers since POR values are undefined.
+		 */
 		memset_io(mhi_cntrl->bhie + BHIE_RXVECADDR_LOW_OFFS,
 			  0, BHIE_RXVECSTATUS_OFFS - BHIE_RXVECADDR_LOW_OFFS +
 			  4);
-
+		/*
+		 * Allocate RDDM table for debugging purpose if specified
+		 */
+		mhi_alloc_bhie_table(mhi_cntrl, &mhi_cntrl->rddm_image,
+				     mhi_cntrl->rddm_size);
 		if (mhi_cntrl->rddm_image)
 			mhi_rddm_prepare(mhi_cntrl, mhi_cntrl->rddm_image);
 	}
@@ -1103,11 +1110,8 @@ int mhi_prepare_for_power_up(struct mhi_controller *mhi_cntrl)
 
 	return 0;
 
-bhie_error:
-	if (mhi_cntrl->rddm_image) {
-		mhi_free_bhie_table(mhi_cntrl, mhi_cntrl->rddm_image);
-		mhi_cntrl->rddm_image = NULL;
-	}
+error_reg_offset:
+	mhi_deinit_dev_ctxt(mhi_cntrl);
 
 error_dev_ctxt:
 	mutex_unlock(&mhi_cntrl->pm_mutex);
diff --git a/drivers/bus/mhi/core/pm.c b/drivers/bus/mhi/core/pm.c
index e2e59a3..adf426c 100644
--- a/drivers/bus/mhi/core/pm.c
+++ b/drivers/bus/mhi/core/pm.c
@@ -1066,28 +1066,8 @@ int mhi_async_power_up(struct mhi_controller *mhi_cntrl)
 	if (ret)
 		goto error_setup_irq;
 
-	/* Setup BHI offset & INTVEC */
+	/* Setup BHI INTVEC */
 	write_lock_irq(&mhi_cntrl->pm_lock);
-	ret = mhi_read_reg(mhi_cntrl, mhi_cntrl->regs, BHIOFF, &val);
-	if (ret) {
-		write_unlock_irq(&mhi_cntrl->pm_lock);
-		goto error_bhi_offset;
-	}
-
-	mhi_cntrl->bhi = mhi_cntrl->regs + val;
-
-	/* Setup BHIE offset */
-	if (mhi_cntrl->fbc_download) {
-		ret = mhi_read_reg(mhi_cntrl, mhi_cntrl->regs, BHIEOFF, &val);
-		if (ret) {
-			write_unlock_irq(&mhi_cntrl->pm_lock);
-			dev_err(dev, "Error reading BHIE offset\n");
-			goto error_bhi_offset;
-		}
-
-		mhi_cntrl->bhie = mhi_cntrl->regs + val;
-	}
-
 	mhi_write_reg(mhi_cntrl, mhi_cntrl->bhi, BHI_INTVEC, 0);
 	mhi_cntrl->pm_state = MHI_PM_POR;
 	mhi_cntrl->ee = MHI_EE_MAX;
@@ -1098,7 +1078,7 @@ int mhi_async_power_up(struct mhi_controller *mhi_cntrl)
 	if (!MHI_IN_PBL(current_ee) && current_ee != MHI_EE_AMSS) {
 		dev_err(dev, "Not a valid EE for power on\n");
 		ret = -EIO;
-		goto error_bhi_offset;
+		goto error_async_power_up;
 	}
 
 	state = mhi_get_mhi_state(mhi_cntrl);
@@ -1117,7 +1097,7 @@ int mhi_async_power_up(struct mhi_controller *mhi_cntrl)
 		if (!ret) {
 			ret = -EIO;
 			dev_info(dev, "Failed to reset MHI due to syserr state\n");
-			goto error_bhi_offset;
+			goto error_async_power_up;
 		}
 
 		/*
@@ -1139,7 +1119,7 @@ int mhi_async_power_up(struct mhi_controller *mhi_cntrl)
 
 	return 0;
 
-error_bhi_offset:
+error_async_power_up:
 	mhi_deinit_free_irq(mhi_cntrl);
 
 error_setup_irq:
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project



From bbhatt at codeaurora.org  Thu May  6 20:51:39 2021
From: bbhatt at codeaurora.org (Bhaumik Bhatt)
Date: Thu,  6 May 2021 12:51:39 -0700
Subject: [PATCH v4 0/6] BHI/BHIe improvements for MHI power purposes
Message-ID: <1620330705-40192-1-git-send-email-bbhatt@codeaurora.org>

This patch series improves the power up behavior by allowing MHI host driver to
set BHI and/or BHIe offsets early on in the preparation phase and fail pre-power
up if offsets are not found or not within a limited MMIO region. This also
allows MHI host to clean up the offsets in the unprepare after power down phase.

Going forward, controllers will be required to specify a reg_len field which
will be used to check whether the BHI/BHIe offsets are in range or not.

This series has been tested on X86_64 architecture with the PCI generic driver
as controller and an SDX55 device.

v4:
-Added reviewed-by tags
-Updated range check patch to include BHI/e offsets in the error message

v3:
-Added reviewed-by tags
-Updated order of reg_len in mhi_controller structure documentation

v2:
-Added reviewed-by tags
-Moved reg_len entry in mhi_controller structure to allow for a packed struct

Bhaumik Bhatt (6):
  bus: mhi: core: Set BHI/BHIe offsets on power up preparation
  bus: mhi: core: Set BHI and BHIe pointers to NULL in clean-up
  bus: mhi: Add MMIO region length to controller structure
  ath11k: set register access length for MHI driver
  bus: mhi: pci_generic: Set register access length for MHI driver
  bus: mhi: core: Add range checks for BHI and BHIe

 drivers/bus/mhi/core/init.c           | 61 ++++++++++++++++++++++++-----------
 drivers/bus/mhi/core/pm.c             | 28 +++-------------
 drivers/bus/mhi/pci_generic.c         |  1 +
 drivers/net/wireless/ath/ath11k/mhi.c |  1 +
 include/linux/mhi.h                   |  2 ++
 5 files changed, 50 insertions(+), 43 deletions(-)

-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project



From bbhatt at codeaurora.org  Thu May  6 20:51:43 2021
From: bbhatt at codeaurora.org (Bhaumik Bhatt)
Date: Thu,  6 May 2021 12:51:43 -0700
Subject: [PATCH v4 4/6] ath11k: set register access length for MHI driver
In-Reply-To: <1620330705-40192-1-git-send-email-bbhatt@codeaurora.org>
References: <1620330705-40192-1-git-send-email-bbhatt@codeaurora.org>
Message-ID: <1620330705-40192-5-git-send-email-bbhatt@codeaurora.org>

MHI driver requires register space length to add range checks and
prevent memory region accesses outside of that for MMIO space.
Set it before registering the MHI controller.

Signed-off-by: Bhaumik Bhatt <bbhatt at codeaurora.org>
Reviewed-by: Hemant Kumar <hemantk at codeaurora.org>
---
 drivers/net/wireless/ath/ath11k/mhi.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/net/wireless/ath/ath11k/mhi.c b/drivers/net/wireless/ath/ath11k/mhi.c
index 09858e5..c0f013c 100644
--- a/drivers/net/wireless/ath/ath11k/mhi.c
+++ b/drivers/net/wireless/ath/ath11k/mhi.c
@@ -235,6 +235,7 @@ int ath11k_mhi_register(struct ath11k_pci *ab_pci)
 	mhi_ctrl->cntrl_dev = ab->dev;
 	mhi_ctrl->fw_image = ab_pci->amss_path;
 	mhi_ctrl->regs = ab->mem;
+	mhi_ctrl->reg_len = ab->mem_len;
 
 	ret = ath11k_mhi_get_msi(ab_pci);
 	if (ret) {
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project



From bbhatt at codeaurora.org  Thu May  6 20:51:42 2021
From: bbhatt at codeaurora.org (Bhaumik Bhatt)
Date: Thu,  6 May 2021 12:51:42 -0700
Subject: [PATCH v4 3/6] bus: mhi: Add MMIO region length to controller
 structure
In-Reply-To: <1620330705-40192-1-git-send-email-bbhatt@codeaurora.org>
References: <1620330705-40192-1-git-send-email-bbhatt@codeaurora.org>
Message-ID: <1620330705-40192-4-git-send-email-bbhatt@codeaurora.org>

Make controller driver specify the MMIO register region length
for range checking of BHI or BHIe space. This can help validate
that offsets are in acceptable memory region or not and avoid any
boot-up issues due to BHI or BHIe memory accesses.

Signed-off-by: Bhaumik Bhatt <bbhatt at codeaurora.org>
Reviewed-by: Jeffrey Hugo <quic_jhugo at quicinc.com>
Reviewed-by: Hemant Kumar <hemantk at codeaurora.org>
---
 include/linux/mhi.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/linux/mhi.h b/include/linux/mhi.h
index 944aa3a..9c347f5 100644
--- a/include/linux/mhi.h
+++ b/include/linux/mhi.h
@@ -303,6 +303,7 @@ struct mhi_controller_config {
  * @rddm_size: RAM dump size that host should allocate for debugging purpose
  * @sbl_size: SBL image size downloaded through BHIe (optional)
  * @seg_len: BHIe vector size (optional)
+ * @reg_len: Length of the MHI MMIO region (required)
  * @fbc_image: Points to firmware image buffer
  * @rddm_image: Points to RAM dump buffer
  * @mhi_chan: Points to the channel configuration table
@@ -386,6 +387,7 @@ struct mhi_controller {
 	size_t rddm_size;
 	size_t sbl_size;
 	size_t seg_len;
+	size_t reg_len;
 	struct image_info *fbc_image;
 	struct image_info *rddm_image;
 	struct mhi_chan *mhi_chan;
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project



From bbhatt at codeaurora.org  Thu May  6 20:51:45 2021
From: bbhatt at codeaurora.org (Bhaumik Bhatt)
Date: Thu,  6 May 2021 12:51:45 -0700
Subject: [PATCH v4 6/6] bus: mhi: core: Add range checks for BHI and BHIe
In-Reply-To: <1620330705-40192-1-git-send-email-bbhatt@codeaurora.org>
References: <1620330705-40192-1-git-send-email-bbhatt@codeaurora.org>
Message-ID: <1620330705-40192-7-git-send-email-bbhatt@codeaurora.org>

When obtaining the BHI or BHIe offsets during the power up
preparation phase, range checks are missing. These can help
controller drivers avoid accessing any address outside of the
MMIO region. Ensure that mhi_cntrl->reg_len is set before MHI
registration as it is a required field and range checks will
fail without it.

Signed-off-by: Bhaumik Bhatt <bbhatt at codeaurora.org>
Reviewed-by: Jeffrey Hugo <quic_jhugo at quicinc.com>
---
 drivers/bus/mhi/core/init.c | 18 +++++++++++++++++-
 1 file changed, 17 insertions(+), 1 deletion(-)

diff --git a/drivers/bus/mhi/core/init.c b/drivers/bus/mhi/core/init.c
index 1cc2f22..aeb1e3c 100644
--- a/drivers/bus/mhi/core/init.c
+++ b/drivers/bus/mhi/core/init.c
@@ -885,7 +885,8 @@ int mhi_register_controller(struct mhi_controller *mhi_cntrl,
 	if (!mhi_cntrl || !mhi_cntrl->cntrl_dev || !mhi_cntrl->regs ||
 	    !mhi_cntrl->runtime_get || !mhi_cntrl->runtime_put ||
 	    !mhi_cntrl->status_cb || !mhi_cntrl->read_reg ||
-	    !mhi_cntrl->write_reg || !mhi_cntrl->nr_irqs || !mhi_cntrl->irq)
+	    !mhi_cntrl->write_reg || !mhi_cntrl->nr_irqs ||
+	    !mhi_cntrl->irq || !mhi_cntrl->reg_len)
 		return -EINVAL;
 
 	ret = parse_config(mhi_cntrl, config);
@@ -1077,6 +1078,13 @@ int mhi_prepare_for_power_up(struct mhi_controller *mhi_cntrl)
 		dev_err(dev, "Error getting BHI offset\n");
 		goto error_reg_offset;
 	}
+
+	if (bhi_off >= mhi_cntrl->reg_len) {
+		dev_err(dev, "BHI offset: 0x%x is out of range: 0x%zx\n",
+			bhi_off, mhi_cntrl->reg_len);
+		ret = -EINVAL;
+		goto error_reg_offset;
+	}
 	mhi_cntrl->bhi = mhi_cntrl->regs + bhi_off;
 
 	if (mhi_cntrl->fbc_download || mhi_cntrl->rddm_size) {
@@ -1086,6 +1094,14 @@ int mhi_prepare_for_power_up(struct mhi_controller *mhi_cntrl)
 			dev_err(dev, "Error getting BHIE offset\n");
 			goto error_reg_offset;
 		}
+
+		if (bhie_off >= mhi_cntrl->reg_len) {
+			dev_err(dev,
+				"BHIe offset: 0x%x is out of range: 0x%zx\n",
+				bhie_off, mhi_cntrl->reg_len);
+			ret = -EINVAL;
+			goto error_reg_offset;
+		}
 		mhi_cntrl->bhie = mhi_cntrl->regs + bhie_off;
 	}
 
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project



From bbhatt at codeaurora.org  Thu May  6 20:51:41 2021
From: bbhatt at codeaurora.org (Bhaumik Bhatt)
Date: Thu,  6 May 2021 12:51:41 -0700
Subject: [PATCH v4 2/6] bus: mhi: core: Set BHI and BHIe pointers to NULL in
 clean-up
In-Reply-To: <1620330705-40192-1-git-send-email-bbhatt@codeaurora.org>
References: <1620330705-40192-1-git-send-email-bbhatt@codeaurora.org>
Message-ID: <1620330705-40192-3-git-send-email-bbhatt@codeaurora.org>

Set the BHI and BHIe pointers to NULL as part of clean-up. This
makes sure that stale pointers are not accessed after powering
MHI down.

Suggested-by: Hemant Kumar <hemantk at codeaurora.org>
Signed-off-by: Bhaumik Bhatt <bbhatt at codeaurora.org>
Reviewed-by: Jeffrey Hugo <quic_jhugo at quicinc.com>
Reviewed-by: Hemant Kumar <hemantk at codeaurora.org>
---
 drivers/bus/mhi/core/init.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/bus/mhi/core/init.c b/drivers/bus/mhi/core/init.c
index 11c7a3d..1cc2f22 100644
--- a/drivers/bus/mhi/core/init.c
+++ b/drivers/bus/mhi/core/init.c
@@ -1132,6 +1132,9 @@ void mhi_unprepare_after_power_down(struct mhi_controller *mhi_cntrl)
 		mhi_cntrl->rddm_image = NULL;
 	}
 
+	mhi_cntrl->bhi = NULL;
+	mhi_cntrl->bhie = NULL;
+
 	mhi_deinit_dev_ctxt(mhi_cntrl);
 }
 EXPORT_SYMBOL_GPL(mhi_unprepare_after_power_down);
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project



From hemantk at codeaurora.org  Fri May  7 03:33:19 2021
From: hemantk at codeaurora.org (Hemant Kumar)
Date: Thu, 6 May 2021 19:33:19 -0700
Subject: [PATCH v4 6/6] bus: mhi: core: Add range checks for BHI and BHIe
In-Reply-To: <1620330705-40192-7-git-send-email-bbhatt@codeaurora.org>
References: <1620330705-40192-1-git-send-email-bbhatt@codeaurora.org>
 <1620330705-40192-7-git-send-email-bbhatt@codeaurora.org>
Message-ID: <860e3d9d-91dc-7fd6-68f6-e8f099cc4555@codeaurora.org>



On 5/6/21 12:51 PM, Bhaumik Bhatt wrote:
> When obtaining the BHI or BHIe offsets during the power up
> preparation phase, range checks are missing. These can help
> controller drivers avoid accessing any address outside of the
> MMIO region. Ensure that mhi_cntrl->reg_len is set before MHI
> registration as it is a required field and range checks will
> fail without it.
> 
> Signed-off-by: Bhaumik Bhatt <bbhatt at codeaurora.org>
> Reviewed-by: Jeffrey Hugo <quic_jhugo at quicinc.com>

Reviewed-by: Hemant Kumar <hemantk at codeaurora.org>

-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project


From bperumal at codeaurora.org  Fri May  7 06:02:55 2021
From: bperumal at codeaurora.org (Bhagavathi Perumal S)
Date: Fri, 07 May 2021 10:32:55 +0530
Subject: IPQ6018 issues
In-Reply-To: <CA+HBbNHYiULJ2T1Q3dmmXZSYb3gLajr2m86HTvCO-ud0GwkaZA@mail.gmail.com>
References: <CA+HBbNHYiULJ2T1Q3dmmXZSYb3gLajr2m86HTvCO-ud0GwkaZA@mail.gmail.com>
Message-ID: <6b7c79f0fd04c2d7752a181e5d0281f5@codeaurora.org>

On 2021-05-04 22:05, Robert Marko wrote:
> Hi,
> 
> I am trying to use ath11k on multiple IPQ6018 and IPQ6010 boards,
> unfortunately, they will all fail like this:
>> 
>> # echo c000000.wifi > /sys/bus/platform/drivers/ath11k/bind
>> [   12.417214] ath11k c000000.wifi: event type: 0
>> [   12.417557] ath11k c000000.wifi: qmi ignore invalid mem req type 3
>> [   12.420605] ath11k c000000.wifi: event type: 2
>> [   12.427191] ath11k c000000.wifi: event type: 3
>> [   12.431312] ath11k c000000.wifi: chip_id 0x0 chip_family 0x4 
>> board_id 0xff soc_id 0xffffffff
>> [   12.435626] ath11k c000000.wifi: fw_version 0x240606c6 
>> fw_build_timestamp 2021-02-12 03:17 fw_build_id 
>> QC_IMAGE_VERSION_STRING=WLAN.HK.2.4.0.1-01734-QCAHKSWPL_SILICONZ-1
>> [   12.447560] ath11k c000000.wifi: event type: 4
>> [   12.459215] ath11k c000000.wifi: ATH11K_QMI_EVENT_FW_READY
>> [   12.463551] ath11k c000000.wifi: ath11k_core_qmi_firmware_ready
>> [   12.469013] ath11k c000000.wifi: ath11k_core_qmi_firmware_ready 
>> start
>> [   12.474900] ath11k c000000.wifi: ath11k_ce_init_pipes pass
>> # [   12.491124] ath11k c000000.wifi: ath11k_crypto_mode: 0
>> 
>> Format: Log Type - Time(microsec) - Message - Optional Info
>> Log Type: B - Since Boot(Power On Reset),  D - Delta,  S - Statistic
>> S - QC_IMAGE_VERSION_STRING=BOOT.XF.0.3-00098-IPQ60xxLZB-1
>> S - IMAGE_VARIANT_STRING=IPQ6018LA
>> S - OEM_IMAGE_VERSION_STRING=crm-ubuntu121
>> S - Boot Interface: SPI
>> S - Secure Boot: Off
>> S - Boot Config @ 0x000a602c = 0x000002e1
>> S - JTAG ID @ 0x000a607c = 0x0013a0e1
>> S - OEM ID @ 0x000a6080 = 0x00000000
>> S - Serial Number @ 0x000a4128 = 0xd92ca102
>> S - OEM Config Row 0 @ 0x000a4188 = 0x0000000000000000
>> S - OEM Config Row 1 @ 0x000a4190 = 0x0000000000000000
>> S - Feature Config Row 0 @ 0x000a4130 = 0x0000000008000001
>> S - Feature Config Row 1 @ 0x000a4138 = 0x02c3e83383000009
>> S - PBL Patch Ver: 1
>> S - I-cache: On
>> S - D-cache: On
>> B -      3413 - PBL, Start
>> B -       592 - bootable_media_detect_entry, Start
>> B -      4339 - bootable_media_detect_success, Start
>> B -      4435 - elf_loader_entry, Start
>> B -      4607 - auth_hash_seg_entry, Start
>> B -     10854 - auth_hash_seg_exit, Start
>> B -     11350 - elf_segs_hash_verify_entry, Start
>> B -    357983 - elf_segs_hash_verify_exit, Start
>> B -    362173 - auth_xbl_sec_hash_seg_entry, Start
>> B -    362318 - auth_xbl_sec_hash_seg_exit, Start
>> B -    368868 - xbl_sec_segs_hash_verify_entry, Start
>> B -    368869 - xbl_sec_segs_hash_verify_exit, Start
>> B -    369798 - PBL, End
>> B -    296002 - SBL1, Start
>> B -    435814 - GCC [RstStat:0x2, RstDbg:0x420100] WDog Stat : 0x4
>> B -    438254 - clock_init, Start
>> D -      3812 - clock_init, Delta
>> B -    447862 - boot_flash_init, Start
>> D -      8082 - boot_flash_init, Delta
>> B -    458201 - sbl1_ddr_set_default_params, Start
>> D -       274 - sbl1_ddr_set_default_params, Delta
>> B -    464820 - boot_config_data_table_init, Start
>> D -      1891 - boot_config_data_table_init, Delta - (575 Bytes)
>> B -    473970 - CDT Version:2,Platform ID:8,Major ID:3,Minor 
>> ID:0,Subtype:0
>> B -    479490 - Image Load, Start
>> D -      6619 - OEM_MISC Image Loaded, Delta - (0 Bytes)
>> B -    488823 - Image Load, Start
>> D -      5063 - PMIC Image Loaded, Delta - (0 Bytes)
>> B -    496692 - sbl1_ddr_set_params, Start
>> B -    501694 - CPR configuration: 0x366
>> B -    504897 - Pre_DDR_clock_init, Start
>> D -       183 - Pre_DDR_clock_init, Delta
>> D -         0 - sbl1_ddr_set_params, Delta
> 
> 
> I added most of the prints to figure out where it dies.
> If cold-boot calibration is enabled then it will die on the
> ath11k_qmi_process_coldboot_calibration(), to be exact on the
>> 
>> ret = ath11k_qmi_wlanfw_mode_send(ab, ATH11K_FIRMWARE_MODE_COLD_BOOT);
> 
> 
> But, if cold-boot calibration is disabled then ti will fail in
> ath11k_core_qmi_firmware_ready at or after ath11k_crypto_mode switch.
> 
> A big issue is that it will crash the board and it will get stuck in
> SBL, only removing the power will help.
> 
> The hardware I tried on is:
> * Wallys CP01-C1
> * Wallys CP03-C1
> * Alfa AP1800C-AX PRO
> 
> I also tried fw versions from 2.1.0.1 to 2.5.0.1-R2
> 
> Does anybody have an idea how to solve this?
> 
> --
> Robert Marko
> Staff Embedded Linux Engineer
> Sartura Ltd.
> Lendavska ulica 16a
> 10000 Zagreb, Croatia
> Email: robert.marko at sartura.hr
> Web: www.sartura.hr

Hi, Please share full boot up log(enable below logs and include them as 
well), what is the image version you used and please share kernel 
version as well? and share us the codebase details as well?

ATH11K_DBG_QMI          = 0x00000040,
ATH11K_DBG_BOOT         = 0x00000020

eg:
echo 0x60 >/sys/module/ath11k/parameters/debug_mask

or modify below file and get during boot

$cat /etc/modules.d/ath11k
ath11k debug_mask=0x60
ath11k_ahb




From john at phrozen.org  Fri May  7 06:35:36 2021
From: john at phrozen.org (John Crispin)
Date: Fri, 7 May 2021 07:35:36 +0200
Subject: IPQ6018 issues
In-Reply-To: <6b7c79f0fd04c2d7752a181e5d0281f5@codeaurora.org>
References: <CA+HBbNHYiULJ2T1Q3dmmXZSYb3gLajr2m86HTvCO-ud0GwkaZA@mail.gmail.com>
 <6b7c79f0fd04c2d7752a181e5d0281f5@codeaurora.org>
Message-ID: <4b13c9a8-a673-83e0-2f44-5d9e463a25cc@phrozen.org>

Hi Bhagavathi,

please confirm whether QCA tests patches it sends upstream against the 
upstream kernel and not the forked v4.4 QSDK kernel.

 ??? John

On 07.05.21 07:02, Bhagavathi Perumal S wrote:
> On 2021-05-04 22:05, Robert Marko wrote:
>> Hi,
>>
>> I am trying to use ath11k on multiple IPQ6018 and IPQ6010 boards,
>> unfortunately, they will all fail like this:
>>>
>>> # echo c000000.wifi > /sys/bus/platform/drivers/ath11k/bind
>>> [?? 12.417214] ath11k c000000.wifi: event type: 0
>>> [?? 12.417557] ath11k c000000.wifi: qmi ignore invalid mem req type 3
>>> [?? 12.420605] ath11k c000000.wifi: event type: 2
>>> [?? 12.427191] ath11k c000000.wifi: event type: 3
>>> [?? 12.431312] ath11k c000000.wifi: chip_id 0x0 chip_family 0x4 
>>> board_id 0xff soc_id 0xffffffff
>>> [?? 12.435626] ath11k c000000.wifi: fw_version 0x240606c6 
>>> fw_build_timestamp 2021-02-12 03:17 fw_build_id 
>>> QC_IMAGE_VERSION_STRING=WLAN.HK.2.4.0.1-01734-QCAHKSWPL_SILICONZ-1
>>> [?? 12.447560] ath11k c000000.wifi: event type: 4
>>> [?? 12.459215] ath11k c000000.wifi: ATH11K_QMI_EVENT_FW_READY
>>> [?? 12.463551] ath11k c000000.wifi: ath11k_core_qmi_firmware_ready
>>> [?? 12.469013] ath11k c000000.wifi: ath11k_core_qmi_firmware_ready 
>>> start
>>> [?? 12.474900] ath11k c000000.wifi: ath11k_ce_init_pipes pass
>>> # [?? 12.491124] ath11k c000000.wifi: ath11k_crypto_mode: 0
>>>
>>> Format: Log Type - Time(microsec) - Message - Optional Info
>>> Log Type: B - Since Boot(Power On Reset),? D - Delta,? S - Statistic
>>> S - QC_IMAGE_VERSION_STRING=BOOT.XF.0.3-00098-IPQ60xxLZB-1
>>> S - IMAGE_VARIANT_STRING=IPQ6018LA
>>> S - OEM_IMAGE_VERSION_STRING=crm-ubuntu121
>>> S - Boot Interface: SPI
>>> S - Secure Boot: Off
>>> S - Boot Config @ 0x000a602c = 0x000002e1
>>> S - JTAG ID @ 0x000a607c = 0x0013a0e1
>>> S - OEM ID @ 0x000a6080 = 0x00000000
>>> S - Serial Number @ 0x000a4128 = 0xd92ca102
>>> S - OEM Config Row 0 @ 0x000a4188 = 0x0000000000000000
>>> S - OEM Config Row 1 @ 0x000a4190 = 0x0000000000000000
>>> S - Feature Config Row 0 @ 0x000a4130 = 0x0000000008000001
>>> S - Feature Config Row 1 @ 0x000a4138 = 0x02c3e83383000009
>>> S - PBL Patch Ver: 1
>>> S - I-cache: On
>>> S - D-cache: On
>>> B -????? 3413 - PBL, Start
>>> B -?????? 592 - bootable_media_detect_entry, Start
>>> B -????? 4339 - bootable_media_detect_success, Start
>>> B -????? 4435 - elf_loader_entry, Start
>>> B -????? 4607 - auth_hash_seg_entry, Start
>>> B -???? 10854 - auth_hash_seg_exit, Start
>>> B -???? 11350 - elf_segs_hash_verify_entry, Start
>>> B -??? 357983 - elf_segs_hash_verify_exit, Start
>>> B -??? 362173 - auth_xbl_sec_hash_seg_entry, Start
>>> B -??? 362318 - auth_xbl_sec_hash_seg_exit, Start
>>> B -??? 368868 - xbl_sec_segs_hash_verify_entry, Start
>>> B -??? 368869 - xbl_sec_segs_hash_verify_exit, Start
>>> B -??? 369798 - PBL, End
>>> B -??? 296002 - SBL1, Start
>>> B -??? 435814 - GCC [RstStat:0x2, RstDbg:0x420100] WDog Stat : 0x4
>>> B -??? 438254 - clock_init, Start
>>> D -????? 3812 - clock_init, Delta
>>> B -??? 447862 - boot_flash_init, Start
>>> D -????? 8082 - boot_flash_init, Delta
>>> B -??? 458201 - sbl1_ddr_set_default_params, Start
>>> D -?????? 274 - sbl1_ddr_set_default_params, Delta
>>> B -??? 464820 - boot_config_data_table_init, Start
>>> D -????? 1891 - boot_config_data_table_init, Delta - (575 Bytes)
>>> B -??? 473970 - CDT Version:2,Platform ID:8,Major ID:3,Minor 
>>> ID:0,Subtype:0
>>> B -??? 479490 - Image Load, Start
>>> D -????? 6619 - OEM_MISC Image Loaded, Delta - (0 Bytes)
>>> B -??? 488823 - Image Load, Start
>>> D -????? 5063 - PMIC Image Loaded, Delta - (0 Bytes)
>>> B -??? 496692 - sbl1_ddr_set_params, Start
>>> B -??? 501694 - CPR configuration: 0x366
>>> B -??? 504897 - Pre_DDR_clock_init, Start
>>> D -?????? 183 - Pre_DDR_clock_init, Delta
>>> D -???????? 0 - sbl1_ddr_set_params, Delta
>>
>>
>> I added most of the prints to figure out where it dies.
>> If cold-boot calibration is enabled then it will die on the
>> ath11k_qmi_process_coldboot_calibration(), to be exact on the
>>>
>>> ret = ath11k_qmi_wlanfw_mode_send(ab, ATH11K_FIRMWARE_MODE_COLD_BOOT);
>>
>>
>> But, if cold-boot calibration is disabled then ti will fail in
>> ath11k_core_qmi_firmware_ready at or after ath11k_crypto_mode switch.
>>
>> A big issue is that it will crash the board and it will get stuck in
>> SBL, only removing the power will help.
>>
>> The hardware I tried on is:
>> * Wallys CP01-C1
>> * Wallys CP03-C1
>> * Alfa AP1800C-AX PRO
>>
>> I also tried fw versions from 2.1.0.1 to 2.5.0.1-R2
>>
>> Does anybody have an idea how to solve this?
>>
>> -- 
>> Robert Marko
>> Staff Embedded Linux Engineer
>> Sartura Ltd.
>> Lendavska ulica 16a
>> 10000 Zagreb, Croatia
>> Email: robert.marko at sartura.hr
>> Web: www.sartura.hr
>
> Hi, Please share full boot up log(enable below logs and include them 
> as well), what is the image version you used and please share kernel 
> version as well? and share us the codebase details as well?
>
> ATH11K_DBG_QMI????????? = 0x00000040,
> ATH11K_DBG_BOOT???????? = 0x00000020
>
> eg:
> echo 0x60 >/sys/module/ath11k/parameters/debug_mask
>
> or modify below file and get during boot
>
> $cat /etc/modules.d/ath11k
> ath11k debug_mask=0x60
> ath11k_ahb
>
>
>


From robert.marko at sartura.hr  Fri May  7 11:38:24 2021
From: robert.marko at sartura.hr (Robert Marko)
Date: Fri, 7 May 2021 12:38:24 +0200
Subject: IPQ6018 issues
In-Reply-To: <4b13c9a8-a673-83e0-2f44-5d9e463a25cc@phrozen.org>
References: <CA+HBbNHYiULJ2T1Q3dmmXZSYb3gLajr2m86HTvCO-ud0GwkaZA@mail.gmail.com>
 <6b7c79f0fd04c2d7752a181e5d0281f5@codeaurora.org>
 <4b13c9a8-a673-83e0-2f44-5d9e463a25cc@phrozen.org>
Message-ID: <CA+HBbNHYzke1cB5WpWSazWnCxqsTQEKV3AApH7PiDj3aB-L0MQ@mail.gmail.com>

Hi,

I could not previously reply to my inquiry as for whatever reason I
did not receive the message to my email.

I have managed to get the ath11k mostly working on IPQ6018, the issue
was in the APPS PLL and the resets in the GCC driver
were not fully working and some were incorrect.

So, after backporting all of the downstream 5.4 changes to clock
drivers ath11k mostly works, however, if cold-boot calibration is
enabled it will then trigger the remoteproc WDT and crash and hang the
board as well.

However, I have not been able to get the radio working in 80 or 160MHz
mode, only 20MHz.

Trying 80Mhz will simply fail like this log:
https://gist.github.com/robimarko/b0d002a4cc5390a82a22eb47aa97684d

Hostapd 2.9 config used is:
root at localhost $ cat hostapd-ax.conf
logger_syslog=-1
logger_syslog_level=2
logger_stdout=-1
logger_stdout_level=2
ctrl_interface=/var/run/hostapd

interface=wlan0
bridge=br-lan
driver=nl80211
ssid=AXTest
country_code=US
ieee80211d=1
ieee80211h=1
hw_mode=a
channel=36
wmm_enabled=1
ieee80211n=0
ieee80211ac=1
ieee80211ax=1
he_oper_chwidth=1
he_oper_centr_freq_seg0_idx=42

Regards,
Robert


On Fri, May 7, 2021 at 7:35 AM John Crispin <john at phrozen.org> wrote:
>
> Hi Bhagavathi,
>
> please confirm whether QCA tests patches it sends upstream against the
> upstream kernel and not the forked v4.4 QSDK kernel.
>
>      John
>
> On 07.05.21 07:02, Bhagavathi Perumal S wrote:
> > On 2021-05-04 22:05, Robert Marko wrote:
> >> Hi,
> >>
> >> I am trying to use ath11k on multiple IPQ6018 and IPQ6010 boards,
> >> unfortunately, they will all fail like this:
> >>>
> >>> # echo c000000.wifi > /sys/bus/platform/drivers/ath11k/bind
> >>> [   12.417214] ath11k c000000.wifi: event type: 0
> >>> [   12.417557] ath11k c000000.wifi: qmi ignore invalid mem req type 3
> >>> [   12.420605] ath11k c000000.wifi: event type: 2
> >>> [   12.427191] ath11k c000000.wifi: event type: 3
> >>> [   12.431312] ath11k c000000.wifi: chip_id 0x0 chip_family 0x4
> >>> board_id 0xff soc_id 0xffffffff
> >>> [   12.435626] ath11k c000000.wifi: fw_version 0x240606c6
> >>> fw_build_timestamp 2021-02-12 03:17 fw_build_id
> >>> QC_IMAGE_VERSION_STRING=WLAN.HK.2.4.0.1-01734-QCAHKSWPL_SILICONZ-1
> >>> [   12.447560] ath11k c000000.wifi: event type: 4
> >>> [   12.459215] ath11k c000000.wifi: ATH11K_QMI_EVENT_FW_READY
> >>> [   12.463551] ath11k c000000.wifi: ath11k_core_qmi_firmware_ready
> >>> [   12.469013] ath11k c000000.wifi: ath11k_core_qmi_firmware_ready
> >>> start
> >>> [   12.474900] ath11k c000000.wifi: ath11k_ce_init_pipes pass
> >>> # [   12.491124] ath11k c000000.wifi: ath11k_crypto_mode: 0
> >>>
> >>> Format: Log Type - Time(microsec) - Message - Optional Info
> >>> Log Type: B - Since Boot(Power On Reset),  D - Delta,  S - Statistic
> >>> S - QC_IMAGE_VERSION_STRING=BOOT.XF.0.3-00098-IPQ60xxLZB-1
> >>> S - IMAGE_VARIANT_STRING=IPQ6018LA
> >>> S - OEM_IMAGE_VERSION_STRING=crm-ubuntu121
> >>> S - Boot Interface: SPI
> >>> S - Secure Boot: Off
> >>> S - Boot Config @ 0x000a602c = 0x000002e1
> >>> S - JTAG ID @ 0x000a607c = 0x0013a0e1
> >>> S - OEM ID @ 0x000a6080 = 0x00000000
> >>> S - Serial Number @ 0x000a4128 = 0xd92ca102
> >>> S - OEM Config Row 0 @ 0x000a4188 = 0x0000000000000000
> >>> S - OEM Config Row 1 @ 0x000a4190 = 0x0000000000000000
> >>> S - Feature Config Row 0 @ 0x000a4130 = 0x0000000008000001
> >>> S - Feature Config Row 1 @ 0x000a4138 = 0x02c3e83383000009
> >>> S - PBL Patch Ver: 1
> >>> S - I-cache: On
> >>> S - D-cache: On
> >>> B -      3413 - PBL, Start
> >>> B -       592 - bootable_media_detect_entry, Start
> >>> B -      4339 - bootable_media_detect_success, Start
> >>> B -      4435 - elf_loader_entry, Start
> >>> B -      4607 - auth_hash_seg_entry, Start
> >>> B -     10854 - auth_hash_seg_exit, Start
> >>> B -     11350 - elf_segs_hash_verify_entry, Start
> >>> B -    357983 - elf_segs_hash_verify_exit, Start
> >>> B -    362173 - auth_xbl_sec_hash_seg_entry, Start
> >>> B -    362318 - auth_xbl_sec_hash_seg_exit, Start
> >>> B -    368868 - xbl_sec_segs_hash_verify_entry, Start
> >>> B -    368869 - xbl_sec_segs_hash_verify_exit, Start
> >>> B -    369798 - PBL, End
> >>> B -    296002 - SBL1, Start
> >>> B -    435814 - GCC [RstStat:0x2, RstDbg:0x420100] WDog Stat : 0x4
> >>> B -    438254 - clock_init, Start
> >>> D -      3812 - clock_init, Delta
> >>> B -    447862 - boot_flash_init, Start
> >>> D -      8082 - boot_flash_init, Delta
> >>> B -    458201 - sbl1_ddr_set_default_params, Start
> >>> D -       274 - sbl1_ddr_set_default_params, Delta
> >>> B -    464820 - boot_config_data_table_init, Start
> >>> D -      1891 - boot_config_data_table_init, Delta - (575 Bytes)
> >>> B -    473970 - CDT Version:2,Platform ID:8,Major ID:3,Minor
> >>> ID:0,Subtype:0
> >>> B -    479490 - Image Load, Start
> >>> D -      6619 - OEM_MISC Image Loaded, Delta - (0 Bytes)
> >>> B -    488823 - Image Load, Start
> >>> D -      5063 - PMIC Image Loaded, Delta - (0 Bytes)
> >>> B -    496692 - sbl1_ddr_set_params, Start
> >>> B -    501694 - CPR configuration: 0x366
> >>> B -    504897 - Pre_DDR_clock_init, Start
> >>> D -       183 - Pre_DDR_clock_init, Delta
> >>> D -         0 - sbl1_ddr_set_params, Delta
> >>
> >>
> >> I added most of the prints to figure out where it dies.
> >> If cold-boot calibration is enabled then it will die on the
> >> ath11k_qmi_process_coldboot_calibration(), to be exact on the
> >>>
> >>> ret = ath11k_qmi_wlanfw_mode_send(ab, ATH11K_FIRMWARE_MODE_COLD_BOOT);
> >>
> >>
> >> But, if cold-boot calibration is disabled then ti will fail in
> >> ath11k_core_qmi_firmware_ready at or after ath11k_crypto_mode switch.
> >>
> >> A big issue is that it will crash the board and it will get stuck in
> >> SBL, only removing the power will help.
> >>
> >> The hardware I tried on is:
> >> * Wallys CP01-C1
> >> * Wallys CP03-C1
> >> * Alfa AP1800C-AX PRO
> >>
> >> I also tried fw versions from 2.1.0.1 to 2.5.0.1-R2
> >>
> >> Does anybody have an idea how to solve this?
> >>
> >> --
> >> Robert Marko
> >> Staff Embedded Linux Engineer
> >> Sartura Ltd.
> >> Lendavska ulica 16a
> >> 10000 Zagreb, Croatia
> >> Email: robert.marko at sartura.hr
> >> Web: www.sartura.hr
> >
> > Hi, Please share full boot up log(enable below logs and include them
> > as well), what is the image version you used and please share kernel
> > version as well? and share us the codebase details as well?
> >
> > ATH11K_DBG_QMI          = 0x00000040,
> > ATH11K_DBG_BOOT         = 0x00000020
> >
> > eg:
> > echo 0x60 >/sys/module/ath11k/parameters/debug_mask
> >
> > or modify below file and get during boot
> >
> > $cat /etc/modules.d/ath11k
> > ath11k debug_mask=0x60
> > ath11k_ahb
> >
> >
> >



-- 
Robert Marko
Staff Embedded Linux Engineer
Sartura Ltd.
Lendavska ulica 16a
10000 Zagreb, Croatia
Email: robert.marko at sartura.hr
Web: www.sartura.hr


From saggy00 at gmail.com  Mon May 10 12:59:15 2021
From: saggy00 at gmail.com (SaGGy00)
Date: Mon, 10 May 2021 13:59:15 +0200
Subject: Dell XPS 13 9310 MHI issue
Message-ID: <CAAzMHAgT3Xwfth_gu43bqKyTcpWvy+5abKfdicCKcLZBzZQ3fw@mail.gmail.com>

Hi everyone,

I am facing a problem with my Dell XPS 13 regarding the ath11k_pci module.

I have tried the following kernels:
ath11k-qca6390-bringup, ath-202104221406, archlinux's stock 5.12.1.

Wifi is working only for ath11k-qca6390-bringup and only when the
kernel is auto-loading the ath11k_pci/ath11k modules. For all three
kernels the wifi doesn't work when the modules are loaded manually
after booting the kernel. I tried to see what is going on and it seems
that the process fails because the MHI command to the PCI never
returns a response.

The debug output when loading ath11k_pci is given below:
[   37.680944] ath11k_pci 0000:72:00.0: BAR 0: assigned [mem
0xa2500000-0xa25fffff 64bit]
[   37.680970] ath11k_pci 0000:72:00.0: enabling device (0000 -> 0002)
[   37.681025] ath11k_pci 0000:72:00.0: boot pci_mem 0x00000000c2f3a455
[   37.681030] ath11k_pci 0000:72:00.0: pci tcsr_soc_hw_version major 2 minor 0
[   37.681257] ath11k_pci 0000:72:00.0: msi base data is 0
[   37.681258] ath11k_pci 0000:72:00.0: qca6390 hw2.0
[   37.681259] ath11k_pci 0000:72:00.0: Assign MSI to user: MHI,
num_vectors: 3, user_base_data: 0, base_vector: 0
[   37.681260] ath11k_pci 0000:72:00.0: Number of assigned MSI for MHI
is 3, base vector is 0
[   37.681329] ath11k_pci 0000:72:00.0: target_reg a3b034, shadow reg
0x8fc shadow_idx 0x0, ring_type 0, ring num 0
[   37.681330] ath11k_pci 0000:72:00.0: target_reg a3b03c, shadow reg
0x900 shadow_idx 0x1, ring_type 0, ring num 1
[   37.681331] ath11k_pci 0000:72:00.0: target_reg a3b044, shadow reg
0x904 shadow_idx 0x2, ring_type 0, ring num 2
[   37.681332] ath11k_pci 0000:72:00.0: target_reg a3b04c, shadow reg
0x908 shadow_idx 0x3, ring_type 0, ring num 3
[   37.681333] ath11k_pci 0000:72:00.0: target_reg a3b054, shadow reg
0x90c shadow_idx 0x4, ring_type 1, ring num 0
[   37.681334] ath11k_pci 0000:72:00.0: target_reg a3b028, shadow reg
0x910 shadow_idx 0x5, ring_type 2, ring num 0
[   37.681335] ath11k_pci 0000:72:00.0: target_reg a3b020, shadow reg
0x914 shadow_idx 0x6, ring_type 3, ring num 0
[   37.681335] ath11k_pci 0000:72:00.0: target_reg a3b06c, shadow reg
0x918 shadow_idx 0x7, ring_type 4, ring num 0
[   37.681336] ath11k_pci 0000:72:00.0: target_reg a46000, shadow reg
0x91c shadow_idx 0x8, ring_type 5, ring num 0
[   37.681337] ath11k_pci 0000:72:00.0: target_reg a46008, shadow reg
0x920 shadow_idx 0x9, ring_type 5, ring num 1
[   37.681338] ath11k_pci 0000:72:00.0: target_reg a46010, shadow reg
0x924 shadow_idx 0xa, ring_type 5, ring num 2
[   37.681338] ath11k_pci 0000:72:00.0: target_reg a46018, shadow reg
0x928 shadow_idx 0xb, ring_type 6, ring num 0
[   37.681339] ath11k_pci 0000:72:00.0: target_reg a46034, shadow reg
0x92c shadow_idx 0xc, ring_type 7, ring num 0
[   37.681347] ath11k_pci 0000:72:00.0: target_reg a370b0, shadow reg
0x930 shadow_idx 0xd, ring_type 11, ring num 0
[   37.681348] ath11k_pci 0000:72:00.0: target_reg a37018, shadow reg
0x934 shadow_idx 0xe, ring_type 12, ring num 0
[   37.681349] ath11k_pci 0000:72:00.0: target_reg a370c4, shadow reg
0x938 shadow_idx 0xf, ring_type 13, ring num 0
[   37.681349] ath11k_pci 0000:72:00.0: target_reg a370cc, shadow reg
0x93c shadow_idx 0x10, ring_type 13, ring num 1
[   37.681350] ath11k_pci 0000:72:00.0: target_reg a370d4, shadow reg
0x940 shadow_idx 0x11, ring_type 13, ring num 2
[   37.681351] ath11k_pci 0000:72:00.0: target_reg a370dc, shadow reg
0x944 shadow_idx 0x12, ring_type 13, ring num 3
[   37.681352] ath11k_pci 0000:72:00.0: target_reg a00400, shadow reg
0x948 shadow_idx 0x13, ring_type 8, ring num 0
[   37.681353] ath11k_pci 0000:72:00.0: target_reg a03400, shadow reg
0x94c shadow_idx 0x14, ring_type 9, ring num 1
[   37.681354] ath11k_pci 0000:72:00.0: target_reg a0340c, shadow reg
0x950 shadow_idx 0x15, ring_type 10, ring num 1
[   37.681355] ath11k_pci 0000:72:00.0: target_reg a05400, shadow reg
0x954 shadow_idx 0x16, ring_type 9, ring num 2
[   37.681356] ath11k_pci 0000:72:00.0: target_reg a0540c, shadow reg
0x958 shadow_idx 0x17, ring_type 10, ring num 2
[   37.681356] ath11k_pci 0000:72:00.0: target_reg a06400, shadow reg
0x95c shadow_idx 0x18, ring_type 8, ring num 3
[   37.681357] ath11k_pci 0000:72:00.0: target_reg a08400, shadow reg
0x960 shadow_idx 0x19, ring_type 8, ring num 4
[   37.681358] ath11k_pci 0000:72:00.0: target_reg a0b400, shadow reg
0x964 shadow_idx 0x1a, ring_type 9, ring num 5
[   37.681359] ath11k_pci 0000:72:00.0: target_reg a0b40c, shadow reg
0x968 shadow_idx 0x1b, ring_type 10, ring num 5
[   37.681360] ath11k_pci 0000:72:00.0: target_reg a0e400, shadow reg
0x96c shadow_idx 0x1c, ring_type 8, ring num 7
[   37.681360] ath11k_pci 0000:72:00.0: Assign MSI to user: CE,
num_vectors: 10, user_base_data: 3, base_vector: 3
[   37.681417] ath11k_pci 0000:72:00.0: Assign MSI to user: DP,
num_vectors: 18, user_base_data: 14, base_vector: 14
[   37.681419] ath11k_pci 0000:72:00.0: irq:192 group:0
[   37.681429] ath11k_pci 0000:72:00.0: irq:193 group:1
[   37.681438] ath11k_pci 0000:72:00.0: irq:194 group:2
[   37.681447] ath11k_pci 0000:72:00.0: irq:196 group:4
[   37.681457] ath11k_pci 0000:72:00.0: irq:197 group:5
[   37.681466] ath11k_pci 0000:72:00.0: irq:198 group:6
[   37.681475] ath11k_pci 0000:72:00.0: irq:199 group:7
[   37.681484] ath11k_pci 0000:72:00.0: irq:200 group:8
[   37.681494] ath11k_pci 0000:72:00.0: irq:201 group:9
[   37.681503] ath11k_pci 0000:72:00.0: irq:202 group:10
[   37.685504] NET: Registered protocol family 42
[   37.685694] ath11k_pci 0000:72:00.0: pci ltssm 0x111
[   37.685705] ath11k_pci 0000:72:00.0: pci pcie_hot_rst 0x10
[   37.710771] ath11k_pci 0000:72:00.0: MHISTATUS 0xff04
[   37.720790] ath11k_pci 0000:72:00.0: cookie:0x0
[   37.720802] ath11k_pci 0000:72:00.0: WLAON_WARM_SW_ENTRY 0x0
[   37.740817] ath11k_pci 0000:72:00.0: WLAON_WARM_SW_ENTRY 0x0
[   37.740829] ath11k_pci 0000:72:00.0: soc reset cause:0
[   37.740833] ath11k_pci 0000:72:00.0: pci link_ctl 0x0042 L0s 0 L1 1
[   37.740836] ath11k_pci 0000:72:00.0: setting mhi state: INIT(0)
[   37.740844] ath11k_pci 0000:72:00.0: setting mhi state: POWER_ON(2)
[   37.740846] mhi mhi0: Requested to power ON
[   37.741117] mhi mhi0: Power on setup success
[   37.741448] audit: type=1106 audit(1619127314.596:98): pid=1034
uid=1000 auid=1000 ses=4 msg='op=PAM:session_close
grantors=pam_limits,pam_unix,pam_permit acct="root"
exe="/usr/bin/sudo" hostname=? addr=? terminal=/dev/pts/0 res=success'
[   37.741481] audit: type=1104 audit(1619127314.596:99): pid=1034
uid=1000 auid=1000 ses=4 msg='op=PAM:setcred
grantors=pam_faillock,pam_permit,pam_env,pam_faillock acct="root"
exe="/usr/bin/sudo" hostname=? addr=? terminal=/dev/pts/0 res=success'
[   38.051572] mhi mhi0: Wait for device to enter SBL or Mission mode

I also tried the booting from the archlinux livecd and I noticed that
sometimes ath11k_pci is loaded properly, while other times is not.

Any help appreciated,
Thanasis Xigis


From bperumal at codeaurora.org  Tue May 11 17:13:47 2021
From: bperumal at codeaurora.org (Bhagavathi Perumal S)
Date: Tue, 11 May 2021 21:43:47 +0530
Subject: IPQ6018 issues
In-Reply-To: <CA+HBbNHYzke1cB5WpWSazWnCxqsTQEKV3AApH7PiDj3aB-L0MQ@mail.gmail.com>
References: <CA+HBbNHYiULJ2T1Q3dmmXZSYb3gLajr2m86HTvCO-ud0GwkaZA@mail.gmail.com>
 <6b7c79f0fd04c2d7752a181e5d0281f5@codeaurora.org>
 <4b13c9a8-a673-83e0-2f44-5d9e463a25cc@phrozen.org>
 <CA+HBbNHYzke1cB5WpWSazWnCxqsTQEKV3AApH7PiDj3aB-L0MQ@mail.gmail.com>
Message-ID: <77a17df97ac7817364b5ee3de7d48a95@codeaurora.org>

On 2021-05-07 16:08, Robert Marko wrote:
> Hi,
> 
> I could not previously reply to my inquiry as for whatever reason I
> did not receive the message to my email.
> 
> I have managed to get the ath11k mostly working on IPQ6018, the issue
> was in the APPS PLL and the resets in the GCC driver
> were not fully working and some were incorrect.
> 
> So, after backporting all of the downstream 5.4 changes to clock
> drivers ath11k mostly works, however, if cold-boot calibration is
> enabled it will then trigger the remoteproc WDT and crash and hang the
> board as well.
> 
> However, I have not been able to get the radio working in 80 or 160MHz
> mode, only 20MHz.
> 
> Trying 80Mhz will simply fail like this log:
> https://gist.github.com/robimarko/b0d002a4cc5390a82a22eb47aa97684d
> 
> Hostapd 2.9 config used is:
> root at localhost $ cat hostapd-ax.conf
> logger_syslog=-1
> logger_syslog_level=2
> logger_stdout=-1
> logger_stdout_level=2
> ctrl_interface=/var/run/hostapd
> 
> interface=wlan0
> bridge=br-lan
> driver=nl80211
> ssid=AXTest
> country_code=US
> ieee80211d=1
> ieee80211h=1
> hw_mode=a
> channel=36
> wmm_enabled=1
> ieee80211n=0

Please try with enabling ieee80211n and ht_capab. Have you tried with 
default configs?

> ieee80211ac=1
> ieee80211ax=1
> he_oper_chwidth=1
> he_oper_centr_freq_seg0_idx=42
> 
> Regards,
> Robert
> 
> 
> On Fri, May 7, 2021 at 7:35 AM John Crispin <john at phrozen.org> wrote:
>> 
>> Hi Bhagavathi,
>> 
>> please confirm whether QCA tests patches it sends upstream against the
>> upstream kernel and not the forked v4.4 QSDK kernel.
>> 
>>      John
>> 
>> On 07.05.21 07:02, Bhagavathi Perumal S wrote:
>> > On 2021-05-04 22:05, Robert Marko wrote:
>> >> Hi,
>> >>
>> >> I am trying to use ath11k on multiple IPQ6018 and IPQ6010 boards,
>> >> unfortunately, they will all fail like this:
>> >>>
>> >>> # echo c000000.wifi > /sys/bus/platform/drivers/ath11k/bind
>> >>> [   12.417214] ath11k c000000.wifi: event type: 0
>> >>> [   12.417557] ath11k c000000.wifi: qmi ignore invalid mem req type 3
>> >>> [   12.420605] ath11k c000000.wifi: event type: 2
>> >>> [   12.427191] ath11k c000000.wifi: event type: 3
>> >>> [   12.431312] ath11k c000000.wifi: chip_id 0x0 chip_family 0x4
>> >>> board_id 0xff soc_id 0xffffffff
>> >>> [   12.435626] ath11k c000000.wifi: fw_version 0x240606c6
>> >>> fw_build_timestamp 2021-02-12 03:17 fw_build_id
>> >>> QC_IMAGE_VERSION_STRING=WLAN.HK.2.4.0.1-01734-QCAHKSWPL_SILICONZ-1
>> >>> [   12.447560] ath11k c000000.wifi: event type: 4
>> >>> [   12.459215] ath11k c000000.wifi: ATH11K_QMI_EVENT_FW_READY
>> >>> [   12.463551] ath11k c000000.wifi: ath11k_core_qmi_firmware_ready
>> >>> [   12.469013] ath11k c000000.wifi: ath11k_core_qmi_firmware_ready
>> >>> start
>> >>> [   12.474900] ath11k c000000.wifi: ath11k_ce_init_pipes pass
>> >>> # [   12.491124] ath11k c000000.wifi: ath11k_crypto_mode: 0
>> >>>
>> >>> Format: Log Type - Time(microsec) - Message - Optional Info
>> >>> Log Type: B - Since Boot(Power On Reset),  D - Delta,  S - Statistic
>> >>> S - QC_IMAGE_VERSION_STRING=BOOT.XF.0.3-00098-IPQ60xxLZB-1
>> >>> S - IMAGE_VARIANT_STRING=IPQ6018LA
>> >>> S - OEM_IMAGE_VERSION_STRING=crm-ubuntu121
>> >>> S - Boot Interface: SPI
>> >>> S - Secure Boot: Off
>> >>> S - Boot Config @ 0x000a602c = 0x000002e1
>> >>> S - JTAG ID @ 0x000a607c = 0x0013a0e1
>> >>> S - OEM ID @ 0x000a6080 = 0x00000000
>> >>> S - Serial Number @ 0x000a4128 = 0xd92ca102
>> >>> S - OEM Config Row 0 @ 0x000a4188 = 0x0000000000000000
>> >>> S - OEM Config Row 1 @ 0x000a4190 = 0x0000000000000000
>> >>> S - Feature Config Row 0 @ 0x000a4130 = 0x0000000008000001
>> >>> S - Feature Config Row 1 @ 0x000a4138 = 0x02c3e83383000009
>> >>> S - PBL Patch Ver: 1
>> >>> S - I-cache: On
>> >>> S - D-cache: On
>> >>> B -      3413 - PBL, Start
>> >>> B -       592 - bootable_media_detect_entry, Start
>> >>> B -      4339 - bootable_media_detect_success, Start
>> >>> B -      4435 - elf_loader_entry, Start
>> >>> B -      4607 - auth_hash_seg_entry, Start
>> >>> B -     10854 - auth_hash_seg_exit, Start
>> >>> B -     11350 - elf_segs_hash_verify_entry, Start
>> >>> B -    357983 - elf_segs_hash_verify_exit, Start
>> >>> B -    362173 - auth_xbl_sec_hash_seg_entry, Start
>> >>> B -    362318 - auth_xbl_sec_hash_seg_exit, Start
>> >>> B -    368868 - xbl_sec_segs_hash_verify_entry, Start
>> >>> B -    368869 - xbl_sec_segs_hash_verify_exit, Start
>> >>> B -    369798 - PBL, End
>> >>> B -    296002 - SBL1, Start
>> >>> B -    435814 - GCC [RstStat:0x2, RstDbg:0x420100] WDog Stat : 0x4
>> >>> B -    438254 - clock_init, Start
>> >>> D -      3812 - clock_init, Delta
>> >>> B -    447862 - boot_flash_init, Start
>> >>> D -      8082 - boot_flash_init, Delta
>> >>> B -    458201 - sbl1_ddr_set_default_params, Start
>> >>> D -       274 - sbl1_ddr_set_default_params, Delta
>> >>> B -    464820 - boot_config_data_table_init, Start
>> >>> D -      1891 - boot_config_data_table_init, Delta - (575 Bytes)
>> >>> B -    473970 - CDT Version:2,Platform ID:8,Major ID:3,Minor
>> >>> ID:0,Subtype:0
>> >>> B -    479490 - Image Load, Start
>> >>> D -      6619 - OEM_MISC Image Loaded, Delta - (0 Bytes)
>> >>> B -    488823 - Image Load, Start
>> >>> D -      5063 - PMIC Image Loaded, Delta - (0 Bytes)
>> >>> B -    496692 - sbl1_ddr_set_params, Start
>> >>> B -    501694 - CPR configuration: 0x366
>> >>> B -    504897 - Pre_DDR_clock_init, Start
>> >>> D -       183 - Pre_DDR_clock_init, Delta
>> >>> D -         0 - sbl1_ddr_set_params, Delta
>> >>
>> >>
>> >> I added most of the prints to figure out where it dies.
>> >> If cold-boot calibration is enabled then it will die on the
>> >> ath11k_qmi_process_coldboot_calibration(), to be exact on the
>> >>>
>> >>> ret = ath11k_qmi_wlanfw_mode_send(ab, ATH11K_FIRMWARE_MODE_COLD_BOOT);
>> >>
>> >>
>> >> But, if cold-boot calibration is disabled then ti will fail in
>> >> ath11k_core_qmi_firmware_ready at or after ath11k_crypto_mode switch.
>> >>
>> >> A big issue is that it will crash the board and it will get stuck in
>> >> SBL, only removing the power will help.
>> >>
>> >> The hardware I tried on is:
>> >> * Wallys CP01-C1
>> >> * Wallys CP03-C1
>> >> * Alfa AP1800C-AX PRO
>> >>
>> >> I also tried fw versions from 2.1.0.1 to 2.5.0.1-R2
>> >>
>> >> Does anybody have an idea how to solve this?
>> >>
>> >> --
>> >> Robert Marko
>> >> Staff Embedded Linux Engineer
>> >> Sartura Ltd.
>> >> Lendavska ulica 16a
>> >> 10000 Zagreb, Croatia
>> >> Email: robert.marko at sartura.hr
>> >> Web: www.sartura.hr
>> >
>> > Hi, Please share full boot up log(enable below logs and include them
>> > as well), what is the image version you used and please share kernel
>> > version as well? and share us the codebase details as well?
>> >
>> > ATH11K_DBG_QMI          = 0x00000040,
>> > ATH11K_DBG_BOOT         = 0x00000020
>> >
>> > eg:
>> > echo 0x60 >/sys/module/ath11k/parameters/debug_mask
>> >
>> > or modify below file and get during boot
>> >
>> > $cat /etc/modules.d/ath11k
>> > ath11k debug_mask=0x60
>> > ath11k_ahb
>> >
>> >
>> >


From robert.marko at sartura.hr  Tue May 11 17:18:04 2021
From: robert.marko at sartura.hr (Robert Marko)
Date: Tue, 11 May 2021 18:18:04 +0200
Subject: IPQ6018 issues
In-Reply-To: <77a17df97ac7817364b5ee3de7d48a95@codeaurora.org>
References: <CA+HBbNHYiULJ2T1Q3dmmXZSYb3gLajr2m86HTvCO-ud0GwkaZA@mail.gmail.com>
 <6b7c79f0fd04c2d7752a181e5d0281f5@codeaurora.org>
 <4b13c9a8-a673-83e0-2f44-5d9e463a25cc@phrozen.org>
 <CA+HBbNHYzke1cB5WpWSazWnCxqsTQEKV3AApH7PiDj3aB-L0MQ@mail.gmail.com>
 <77a17df97ac7817364b5ee3de7d48a95@codeaurora.org>
Message-ID: <CA+HBbNEaTz9ZgXKv31qM-J1vtMochPZxhCFFTSxCSX7p8UxbyA@mail.gmail.com>

On Tue, May 11, 2021 at 6:14 PM Bhagavathi Perumal S
<bperumal at codeaurora.org> wrote:
>
> On 2021-05-07 16:08, Robert Marko wrote:
> > Hi,
> >
> > I could not previously reply to my inquiry as for whatever reason I
> > did not receive the message to my email.
> >
> > I have managed to get the ath11k mostly working on IPQ6018, the issue
> > was in the APPS PLL and the resets in the GCC driver
> > were not fully working and some were incorrect.
> >
> > So, after backporting all of the downstream 5.4 changes to clock
> > drivers ath11k mostly works, however, if cold-boot calibration is
> > enabled it will then trigger the remoteproc WDT and crash and hang the
> > board as well.
> >
> > However, I have not been able to get the radio working in 80 or 160MHz
> > mode, only 20MHz.
> >
> > Trying 80Mhz will simply fail like this log:
> > https://gist.github.com/robimarko/b0d002a4cc5390a82a22eb47aa97684d
> >
> > Hostapd 2.9 config used is:
> > root at localhost $ cat hostapd-ax.conf
> > logger_syslog=-1
> > logger_syslog_level=2
> > logger_stdout=-1
> > logger_stdout_level=2
> > ctrl_interface=/var/run/hostapd
> >
> > interface=wlan0
> > bridge=br-lan
> > driver=nl80211
> > ssid=AXTest
> > country_code=US
> > ieee80211d=1
> > ieee80211h=1
> > hw_mode=a
> > channel=36
> > wmm_enabled=1
> > ieee80211n=0
>
> Please try with enabling ieee80211n and ht_capab. Have you tried with
> default configs?

Yeah, after enabling ieee80211n and ht_capab as well as vht_capab it
will start in 80MHz as well.
I have further testing on hold as after getting SSDK and NSS-DP in
mainline it's really unstable and
remoteproc will crash after connecting a client.

With a USB to ethernet I could easily get 270Mbps on 40Mhz as that is
max that the USB adapter can do.
Regards
>
> > ieee80211ac=1
> > ieee80211ax=1
> > he_oper_chwidth=1
> > he_oper_centr_freq_seg0_idx=42
> >
> > Regards,
> > Robert
> >
> >
> > On Fri, May 7, 2021 at 7:35 AM John Crispin <john at phrozen.org> wrote:
> >>
> >> Hi Bhagavathi,
> >>
> >> please confirm whether QCA tests patches it sends upstream against the
> >> upstream kernel and not the forked v4.4 QSDK kernel.
> >>
> >>      John
> >>
> >> On 07.05.21 07:02, Bhagavathi Perumal S wrote:
> >> > On 2021-05-04 22:05, Robert Marko wrote:
> >> >> Hi,
> >> >>
> >> >> I am trying to use ath11k on multiple IPQ6018 and IPQ6010 boards,
> >> >> unfortunately, they will all fail like this:
> >> >>>
> >> >>> # echo c000000.wifi > /sys/bus/platform/drivers/ath11k/bind
> >> >>> [   12.417214] ath11k c000000.wifi: event type: 0
> >> >>> [   12.417557] ath11k c000000.wifi: qmi ignore invalid mem req type 3
> >> >>> [   12.420605] ath11k c000000.wifi: event type: 2
> >> >>> [   12.427191] ath11k c000000.wifi: event type: 3
> >> >>> [   12.431312] ath11k c000000.wifi: chip_id 0x0 chip_family 0x4
> >> >>> board_id 0xff soc_id 0xffffffff
> >> >>> [   12.435626] ath11k c000000.wifi: fw_version 0x240606c6
> >> >>> fw_build_timestamp 2021-02-12 03:17 fw_build_id
> >> >>> QC_IMAGE_VERSION_STRING=WLAN.HK.2.4.0.1-01734-QCAHKSWPL_SILICONZ-1
> >> >>> [   12.447560] ath11k c000000.wifi: event type: 4
> >> >>> [   12.459215] ath11k c000000.wifi: ATH11K_QMI_EVENT_FW_READY
> >> >>> [   12.463551] ath11k c000000.wifi: ath11k_core_qmi_firmware_ready
> >> >>> [   12.469013] ath11k c000000.wifi: ath11k_core_qmi_firmware_ready
> >> >>> start
> >> >>> [   12.474900] ath11k c000000.wifi: ath11k_ce_init_pipes pass
> >> >>> # [   12.491124] ath11k c000000.wifi: ath11k_crypto_mode: 0
> >> >>>
> >> >>> Format: Log Type - Time(microsec) - Message - Optional Info
> >> >>> Log Type: B - Since Boot(Power On Reset),  D - Delta,  S - Statistic
> >> >>> S - QC_IMAGE_VERSION_STRING=BOOT.XF.0.3-00098-IPQ60xxLZB-1
> >> >>> S - IMAGE_VARIANT_STRING=IPQ6018LA
> >> >>> S - OEM_IMAGE_VERSION_STRING=crm-ubuntu121
> >> >>> S - Boot Interface: SPI
> >> >>> S - Secure Boot: Off
> >> >>> S - Boot Config @ 0x000a602c = 0x000002e1
> >> >>> S - JTAG ID @ 0x000a607c = 0x0013a0e1
> >> >>> S - OEM ID @ 0x000a6080 = 0x00000000
> >> >>> S - Serial Number @ 0x000a4128 = 0xd92ca102
> >> >>> S - OEM Config Row 0 @ 0x000a4188 = 0x0000000000000000
> >> >>> S - OEM Config Row 1 @ 0x000a4190 = 0x0000000000000000
> >> >>> S - Feature Config Row 0 @ 0x000a4130 = 0x0000000008000001
> >> >>> S - Feature Config Row 1 @ 0x000a4138 = 0x02c3e83383000009
> >> >>> S - PBL Patch Ver: 1
> >> >>> S - I-cache: On
> >> >>> S - D-cache: On
> >> >>> B -      3413 - PBL, Start
> >> >>> B -       592 - bootable_media_detect_entry, Start
> >> >>> B -      4339 - bootable_media_detect_success, Start
> >> >>> B -      4435 - elf_loader_entry, Start
> >> >>> B -      4607 - auth_hash_seg_entry, Start
> >> >>> B -     10854 - auth_hash_seg_exit, Start
> >> >>> B -     11350 - elf_segs_hash_verify_entry, Start
> >> >>> B -    357983 - elf_segs_hash_verify_exit, Start
> >> >>> B -    362173 - auth_xbl_sec_hash_seg_entry, Start
> >> >>> B -    362318 - auth_xbl_sec_hash_seg_exit, Start
> >> >>> B -    368868 - xbl_sec_segs_hash_verify_entry, Start
> >> >>> B -    368869 - xbl_sec_segs_hash_verify_exit, Start
> >> >>> B -    369798 - PBL, End
> >> >>> B -    296002 - SBL1, Start
> >> >>> B -    435814 - GCC [RstStat:0x2, RstDbg:0x420100] WDog Stat : 0x4
> >> >>> B -    438254 - clock_init, Start
> >> >>> D -      3812 - clock_init, Delta
> >> >>> B -    447862 - boot_flash_init, Start
> >> >>> D -      8082 - boot_flash_init, Delta
> >> >>> B -    458201 - sbl1_ddr_set_default_params, Start
> >> >>> D -       274 - sbl1_ddr_set_default_params, Delta
> >> >>> B -    464820 - boot_config_data_table_init, Start
> >> >>> D -      1891 - boot_config_data_table_init, Delta - (575 Bytes)
> >> >>> B -    473970 - CDT Version:2,Platform ID:8,Major ID:3,Minor
> >> >>> ID:0,Subtype:0
> >> >>> B -    479490 - Image Load, Start
> >> >>> D -      6619 - OEM_MISC Image Loaded, Delta - (0 Bytes)
> >> >>> B -    488823 - Image Load, Start
> >> >>> D -      5063 - PMIC Image Loaded, Delta - (0 Bytes)
> >> >>> B -    496692 - sbl1_ddr_set_params, Start
> >> >>> B -    501694 - CPR configuration: 0x366
> >> >>> B -    504897 - Pre_DDR_clock_init, Start
> >> >>> D -       183 - Pre_DDR_clock_init, Delta
> >> >>> D -         0 - sbl1_ddr_set_params, Delta
> >> >>
> >> >>
> >> >> I added most of the prints to figure out where it dies.
> >> >> If cold-boot calibration is enabled then it will die on the
> >> >> ath11k_qmi_process_coldboot_calibration(), to be exact on the
> >> >>>
> >> >>> ret = ath11k_qmi_wlanfw_mode_send(ab, ATH11K_FIRMWARE_MODE_COLD_BOOT);
> >> >>
> >> >>
> >> >> But, if cold-boot calibration is disabled then ti will fail in
> >> >> ath11k_core_qmi_firmware_ready at or after ath11k_crypto_mode switch.
> >> >>
> >> >> A big issue is that it will crash the board and it will get stuck in
> >> >> SBL, only removing the power will help.
> >> >>
> >> >> The hardware I tried on is:
> >> >> * Wallys CP01-C1
> >> >> * Wallys CP03-C1
> >> >> * Alfa AP1800C-AX PRO
> >> >>
> >> >> I also tried fw versions from 2.1.0.1 to 2.5.0.1-R2
> >> >>
> >> >> Does anybody have an idea how to solve this?
> >> >>
> >> >> --
> >> >> Robert Marko
> >> >> Staff Embedded Linux Engineer
> >> >> Sartura Ltd.
> >> >> Lendavska ulica 16a
> >> >> 10000 Zagreb, Croatia
> >> >> Email: robert.marko at sartura.hr
> >> >> Web: www.sartura.hr
> >> >
> >> > Hi, Please share full boot up log(enable below logs and include them
> >> > as well), what is the image version you used and please share kernel
> >> > version as well? and share us the codebase details as well?
> >> >
> >> > ATH11K_DBG_QMI          = 0x00000040,
> >> > ATH11K_DBG_BOOT         = 0x00000020
> >> >
> >> > eg:
> >> > echo 0x60 >/sys/module/ath11k/parameters/debug_mask
> >> >
> >> > or modify below file and get during boot
> >> >
> >> > $cat /etc/modules.d/ath11k
> >> > ath11k debug_mask=0x60
> >> > ath11k_ahb
> >> >
> >> >
> >> >



-- 
Robert Marko
Staff Embedded Linux Engineer
Sartura Ltd.
Lendavska ulica 16a
10000 Zagreb, Croatia
Email: robert.marko at sartura.hr
Web: www.sartura.hr


From jouni at codeaurora.org  Tue May 11 17:22:07 2021
From: jouni at codeaurora.org (Jouni Malinen)
Date: Tue, 11 May 2021 19:22:07 +0300
Subject: [PATCH 0/7] ath11k: add support for WCN6855
Message-ID: <20210511162214.29475-1-jouni@codeaurora.org>

This patchset adds supports for WCN6855. WCN6855 is a PCI based
DBS device. It is very similar to QCA6390 overall but with below
differences:
 -WCN6855 has different registers, so new regs are
  defined and attached in hw params.
 -WCN6855 has different rx descriptor, so new descriptors
  are created and in addition, new hw ops are added.
 -REO configuration is also different for this target, so
  separate reo handling is added in hw ops.
 -WCN6855 does not have clock drift problem which is found
  on QCA6390, thus no need to configure some related registers.

Baochen Qiang (7):
  ath11k: add hw reg support for WCN6855
  ath11k: add dp support for WCN6855
  ath11k: setup REO for WCN6855
  ath11k: setup WBM_IDLE_LINK ring once again
  ath11k: add support to get peer id for WCN6855
  ath11k: add support for WCN6855
  ath11k: don't call ath11k_pci_set_l1ss for WCN6855

 drivers/net/wireless/ath/ath11k/core.c    |  44 +++
 drivers/net/wireless/ath/ath11k/core.h    |   1 +
 drivers/net/wireless/ath/ath11k/dp.c      |  16 +-
 drivers/net/wireless/ath/ath11k/hal.c     |  10 +
 drivers/net/wireless/ath/ath11k/hal.h     |   3 +-
 drivers/net/wireless/ath/ath11k/hal_rx.c  |  41 +--
 drivers/net/wireless/ath/ath11k/hal_rx.h  |   8 +
 drivers/net/wireless/ath/ath11k/hw.c      | 391 ++++++++++++++++++++++
 drivers/net/wireless/ath/ath11k/hw.h      |   5 +
 drivers/net/wireless/ath/ath11k/mhi.c     |   1 +
 drivers/net/wireless/ath/ath11k/pci.c     |  45 ++-
 drivers/net/wireless/ath/ath11k/rx_desc.h |  87 +++++
 12 files changed, 586 insertions(+), 66 deletions(-)

-- 
2.25.1



From jouni at codeaurora.org  Tue May 11 17:22:08 2021
From: jouni at codeaurora.org (Jouni Malinen)
Date: Tue, 11 May 2021 19:22:08 +0300
Subject: [PATCH 1/7] ath11k: add hw reg support for WCN6855
In-Reply-To: <20210511162214.29475-1-jouni@codeaurora.org>
References: <20210511162214.29475-1-jouni@codeaurora.org>
Message-ID: <20210511162214.29475-2-jouni@codeaurora.org>

From: Baochen Qiang <bqiang at codeaurora.org>

Reg address of WCN6855 is different from other devices,
so add separate reg definition for this target.

Tested-on: WCN6855 hw2.0 PCI WLAN.HSP.1.1-01720.1-QCAHSPSWPL_V1_V2_SILICONZ_LITE-1

Signed-off-by: Govind Singh <govinds at codeaurora.org>
Signed-off-by: Baochen Qiang <bqiang at codeaurora.org>
Signed-off-by: Jouni Malinen <jouni at codeaurora.org>
---
 drivers/net/wireless/ath/ath11k/hw.c | 71 ++++++++++++++++++++++++++++
 drivers/net/wireless/ath/ath11k/hw.h |  1 +
 2 files changed, 72 insertions(+)

diff --git a/drivers/net/wireless/ath/ath11k/hw.c b/drivers/net/wireless/ath/ath11k/hw.c
index 377ae8d5b58f..d9d7c4608052 100644
--- a/drivers/net/wireless/ath/ath11k/hw.c
+++ b/drivers/net/wireless/ath/ath11k/hw.c
@@ -1688,3 +1688,74 @@ const struct ath11k_hw_regs qcn9074_regs = {
 	.pcie_qserdes_sysclk_en_sel = 0x01e0e0a8,
 	.pcie_pcs_osc_dtct_config_base = 0x01e0f45c,
 };
+
+const struct ath11k_hw_regs wcn6855_regs = {
+	/* SW2TCL(x) R0 ring configuration address */
+	.hal_tcl1_ring_base_lsb = 0x00000690,
+	.hal_tcl1_ring_base_msb = 0x00000694,
+	.hal_tcl1_ring_id = 0x00000698,
+	.hal_tcl1_ring_misc = 0x000006a0,
+	.hal_tcl1_ring_tp_addr_lsb = 0x000006ac,
+	.hal_tcl1_ring_tp_addr_msb = 0x000006b0,
+	.hal_tcl1_ring_consumer_int_setup_ix0 = 0x000006c0,
+	.hal_tcl1_ring_consumer_int_setup_ix1 = 0x000006c4,
+	.hal_tcl1_ring_msi1_base_lsb = 0x000006d8,
+	.hal_tcl1_ring_msi1_base_msb = 0x000006dc,
+	.hal_tcl1_ring_msi1_data = 0x000006e0,
+	.hal_tcl2_ring_base_lsb = 0x000006e8,
+	.hal_tcl_ring_base_lsb = 0x00000798,
+
+	/* TCL STATUS ring address */
+	.hal_tcl_status_ring_base_lsb = 0x000008a0,
+
+	/* REO2SW(x) R0 ring configuration address */
+	.hal_reo1_ring_base_lsb = 0x00000244,
+	.hal_reo1_ring_base_msb = 0x00000248,
+	.hal_reo1_ring_id = 0x0000024c,
+	.hal_reo1_ring_misc = 0x00000254,
+	.hal_reo1_ring_hp_addr_lsb = 0x00000258,
+	.hal_reo1_ring_hp_addr_msb = 0x0000025c,
+	.hal_reo1_ring_producer_int_setup = 0x00000268,
+	.hal_reo1_ring_msi1_base_lsb = 0x0000028c,
+	.hal_reo1_ring_msi1_base_msb = 0x00000290,
+	.hal_reo1_ring_msi1_data = 0x00000294,
+	.hal_reo2_ring_base_lsb = 0x0000029c,
+	.hal_reo1_aging_thresh_ix_0 = 0x000005bc,
+	.hal_reo1_aging_thresh_ix_1 = 0x000005c0,
+	.hal_reo1_aging_thresh_ix_2 = 0x000005c4,
+	.hal_reo1_aging_thresh_ix_3 = 0x000005c8,
+
+	/* REO2SW(x) R2 ring pointers (head/tail) address */
+	.hal_reo1_ring_hp = 0x00003030,
+	.hal_reo1_ring_tp = 0x00003034,
+	.hal_reo2_ring_hp = 0x00003038,
+
+	/* REO2TCL R0 ring configuration address */
+	.hal_reo_tcl_ring_base_lsb = 0x00000454,
+	.hal_reo_tcl_ring_hp = 0x00003060,
+
+	/* REO status address */
+	.hal_reo_status_ring_base_lsb = 0x0000055c,
+	.hal_reo_status_hp = 0x00003078,
+
+	/* WCSS relative address */
+	.hal_seq_wcss_umac_ce0_src_reg = 0x1b80000,
+	.hal_seq_wcss_umac_ce0_dst_reg = 0x1b81000,
+	.hal_seq_wcss_umac_ce1_src_reg = 0x1b82000,
+	.hal_seq_wcss_umac_ce1_dst_reg = 0x1b83000,
+
+	/* WBM Idle address */
+	.hal_wbm_idle_link_ring_base_lsb = 0x00000870,
+	.hal_wbm_idle_link_ring_misc = 0x00000880,
+
+	/* SW2WBM release address */
+	.hal_wbm_release_ring_base_lsb = 0x000001e8,
+
+	/* WBM2SW release address */
+	.hal_wbm0_release_ring_base_lsb = 0x00000920,
+	.hal_wbm1_release_ring_base_lsb = 0x00000978,
+
+	/* PCIe base address */
+	.pcie_qserdes_sysclk_en_sel = 0x01e0c0ac,
+	.pcie_pcs_osc_dtct_config_base = 0x01e0c628,
+};
diff --git a/drivers/net/wireless/ath/ath11k/hw.h b/drivers/net/wireless/ath/ath11k/hw.h
index c81a6328361d..4e7261c0dca1 100644
--- a/drivers/net/wireless/ath/ath11k/hw.h
+++ b/drivers/net/wireless/ath/ath11k/hw.h
@@ -318,5 +318,6 @@ struct ath11k_hw_regs {
 extern const struct ath11k_hw_regs ipq8074_regs;
 extern const struct ath11k_hw_regs qca6390_regs;
 extern const struct ath11k_hw_regs qcn9074_regs;
+extern const struct ath11k_hw_regs wcn6855_regs;
 
 #endif
-- 
2.25.1



From jouni at codeaurora.org  Tue May 11 17:22:09 2021
From: jouni at codeaurora.org (Jouni Malinen)
Date: Tue, 11 May 2021 19:22:09 +0300
Subject: [PATCH 2/7] ath11k: add dp support for WCN6855
In-Reply-To: <20210511162214.29475-1-jouni@codeaurora.org>
References: <20210511162214.29475-1-jouni@codeaurora.org>
Message-ID: <20210511162214.29475-3-jouni@codeaurora.org>

From: Baochen Qiang <bqiang at codeaurora.org>

hal rx descriptor is different for WCN6855 and there are such a lot
of handlers processing this descriptor in data path. So add separate
handling for this target.

Tested-on: WCN6855 hw2.0 PCI WLAN.HSP.1.1-01720.1-QCAHSPSWPL_V1_V2_SILICONZ_LITE-1

Signed-off-by: Baochen Qiang <bqiang at codeaurora.org>
Signed-off-by: Jouni Malinen <jouni at codeaurora.org>
---
 drivers/net/wireless/ath/ath11k/hw.c      | 201 ++++++++++++++++++++++
 drivers/net/wireless/ath/ath11k/hw.h      |   1 +
 drivers/net/wireless/ath/ath11k/rx_desc.h |  87 ++++++++++
 3 files changed, 289 insertions(+)

diff --git a/drivers/net/wireless/ath/ath11k/hw.c b/drivers/net/wireless/ath/ath11k/hw.c
index d9d7c4608052..023047df954c 100644
--- a/drivers/net/wireless/ath/ath11k/hw.c
+++ b/drivers/net/wireless/ath/ath11k/hw.c
@@ -45,6 +45,13 @@ static void ath11k_hw_qcn9074_tx_mesh_enable(struct ath11k_base *ab,
 				     true);
 }
 
+static void ath11k_hw_wcn6855_tx_mesh_enable(struct ath11k_base *ab,
+					     struct hal_tcl_data_cmd *tcl_cmd)
+{
+	tcl_cmd->info3 |= FIELD_PREP(HAL_QCN9074_TCL_DATA_CMD_INFO3_MESH_ENABLE,
+				     true);
+}
+
 static void ath11k_init_wmi_config_qca6390(struct ath11k_base *ab,
 					   struct target_resource_config *config)
 {
@@ -489,6 +496,166 @@ static u8 *ath11k_hw_qcn9074_rx_desc_get_msdu_payload(struct hal_rx_desc *desc)
 	return &desc->u.qcn9074.msdu_payload[0];
 }
 
+static bool ath11k_hw_wcn6855_rx_desc_get_first_msdu(struct hal_rx_desc *desc)
+{
+	return !!FIELD_GET(RX_MSDU_END_INFO2_FIRST_MSDU_WCN6855,
+			   __le32_to_cpu(desc->u.wcn6855.msdu_end.info2));
+}
+
+static bool ath11k_hw_wcn6855_rx_desc_get_last_msdu(struct hal_rx_desc *desc)
+{
+	return !!FIELD_GET(RX_MSDU_END_INFO2_LAST_MSDU_WCN6855,
+			   __le32_to_cpu(desc->u.wcn6855.msdu_end.info2));
+}
+
+static u8 ath11k_hw_wcn6855_rx_desc_get_l3_pad_bytes(struct hal_rx_desc *desc)
+{
+	return FIELD_GET(RX_MSDU_END_INFO2_L3_HDR_PADDING,
+			 __le32_to_cpu(desc->u.wcn6855.msdu_end.info2));
+}
+
+static u8 *ath11k_hw_wcn6855_rx_desc_get_hdr_status(struct hal_rx_desc *desc)
+{
+	return desc->u.wcn6855.hdr_status;
+}
+
+static bool ath11k_hw_wcn6855_rx_desc_encrypt_valid(struct hal_rx_desc *desc)
+{
+	return __le32_to_cpu(desc->u.wcn6855.mpdu_start.info1) &
+	       RX_MPDU_START_INFO1_ENCRYPT_INFO_VALID;
+}
+
+static u32 ath11k_hw_wcn6855_rx_desc_get_encrypt_type(struct hal_rx_desc *desc)
+{
+	return FIELD_GET(RX_MPDU_START_INFO2_ENC_TYPE,
+			 __le32_to_cpu(desc->u.wcn6855.mpdu_start.info2));
+}
+
+static u8 ath11k_hw_wcn6855_rx_desc_get_decap_type(struct hal_rx_desc *desc)
+{
+	return FIELD_GET(RX_MSDU_START_INFO2_DECAP_FORMAT,
+			 __le32_to_cpu(desc->u.wcn6855.msdu_start.info2));
+}
+
+static u8 ath11k_hw_wcn6855_rx_desc_get_mesh_ctl(struct hal_rx_desc *desc)
+{
+	return FIELD_GET(RX_MSDU_START_INFO2_MESH_CTRL_PRESENT,
+			 __le32_to_cpu(desc->u.wcn6855.msdu_start.info2));
+}
+
+static bool ath11k_hw_wcn6855_rx_desc_get_mpdu_seq_ctl_vld(struct hal_rx_desc *desc)
+{
+	return !!FIELD_GET(RX_MPDU_START_INFO1_MPDU_SEQ_CTRL_VALID,
+			   __le32_to_cpu(desc->u.wcn6855.mpdu_start.info1));
+}
+
+static bool ath11k_hw_wcn6855_rx_desc_get_mpdu_fc_valid(struct hal_rx_desc *desc)
+{
+	return !!FIELD_GET(RX_MPDU_START_INFO1_MPDU_FCTRL_VALID,
+			   __le32_to_cpu(desc->u.wcn6855.mpdu_start.info1));
+}
+
+static u16 ath11k_hw_wcn6855_rx_desc_get_mpdu_start_seq_no(struct hal_rx_desc *desc)
+{
+	return FIELD_GET(RX_MPDU_START_INFO1_MPDU_SEQ_NUM,
+			 __le32_to_cpu(desc->u.wcn6855.mpdu_start.info1));
+}
+
+static u16 ath11k_hw_wcn6855_rx_desc_get_msdu_len(struct hal_rx_desc *desc)
+{
+	return FIELD_GET(RX_MSDU_START_INFO1_MSDU_LENGTH,
+			 __le32_to_cpu(desc->u.wcn6855.msdu_start.info1));
+}
+
+static u8 ath11k_hw_wcn6855_rx_desc_get_msdu_sgi(struct hal_rx_desc *desc)
+{
+	return FIELD_GET(RX_MSDU_START_INFO3_SGI,
+			 __le32_to_cpu(desc->u.wcn6855.msdu_start.info3));
+}
+
+static u8 ath11k_hw_wcn6855_rx_desc_get_msdu_rate_mcs(struct hal_rx_desc *desc)
+{
+	return FIELD_GET(RX_MSDU_START_INFO3_RATE_MCS,
+			 __le32_to_cpu(desc->u.wcn6855.msdu_start.info3));
+}
+
+static u8 ath11k_hw_wcn6855_rx_desc_get_msdu_rx_bw(struct hal_rx_desc *desc)
+{
+	return FIELD_GET(RX_MSDU_START_INFO3_RECV_BW,
+			 __le32_to_cpu(desc->u.wcn6855.msdu_start.info3));
+}
+
+static u32 ath11k_hw_wcn6855_rx_desc_get_msdu_freq(struct hal_rx_desc *desc)
+{
+	return __le32_to_cpu(desc->u.wcn6855.msdu_start.phy_meta_data);
+}
+
+static u8 ath11k_hw_wcn6855_rx_desc_get_msdu_pkt_type(struct hal_rx_desc *desc)
+{
+	return FIELD_GET(RX_MSDU_START_INFO3_PKT_TYPE,
+			 __le32_to_cpu(desc->u.wcn6855.msdu_start.info3));
+}
+
+static u8 ath11k_hw_wcn6855_rx_desc_get_msdu_nss(struct hal_rx_desc *desc)
+{
+	return FIELD_GET(RX_MSDU_START_INFO3_MIMO_SS_BITMAP,
+			 __le32_to_cpu(desc->u.wcn6855.msdu_start.info3));
+}
+
+static u8 ath11k_hw_wcn6855_rx_desc_get_mpdu_tid(struct hal_rx_desc *desc)
+{
+	return FIELD_GET(RX_MPDU_START_INFO2_TID_WCN6855,
+			 __le32_to_cpu(desc->u.wcn6855.mpdu_start.info2));
+}
+
+static u16 ath11k_hw_wcn6855_rx_desc_get_mpdu_peer_id(struct hal_rx_desc *desc)
+{
+	return __le16_to_cpu(desc->u.wcn6855.mpdu_start.sw_peer_id);
+}
+
+static void ath11k_hw_wcn6855_rx_desc_copy_attn_end(struct hal_rx_desc *fdesc,
+						    struct hal_rx_desc *ldesc)
+{
+	memcpy((u8 *)&fdesc->u.wcn6855.msdu_end, (u8 *)&ldesc->u.wcn6855.msdu_end,
+	       sizeof(struct rx_msdu_end_wcn6855));
+	memcpy((u8 *)&fdesc->u.wcn6855.attention, (u8 *)&ldesc->u.wcn6855.attention,
+	       sizeof(struct rx_attention));
+	memcpy((u8 *)&fdesc->u.wcn6855.mpdu_end, (u8 *)&ldesc->u.wcn6855.mpdu_end,
+	       sizeof(struct rx_mpdu_end));
+}
+
+static u32 ath11k_hw_wcn6855_rx_desc_get_mpdu_start_tag(struct hal_rx_desc *desc)
+{
+	return FIELD_GET(HAL_TLV_HDR_TAG,
+			 __le32_to_cpu(desc->u.wcn6855.mpdu_start_tag));
+}
+
+static u32 ath11k_hw_wcn6855_rx_desc_get_mpdu_ppdu_id(struct hal_rx_desc *desc)
+{
+	return __le16_to_cpu(desc->u.wcn6855.mpdu_start.phy_ppdu_id);
+}
+
+static void ath11k_hw_wcn6855_rx_desc_set_msdu_len(struct hal_rx_desc *desc, u16 len)
+{
+	u32 info = __le32_to_cpu(desc->u.wcn6855.msdu_start.info1);
+
+	info &= ~RX_MSDU_START_INFO1_MSDU_LENGTH;
+	info |= FIELD_PREP(RX_MSDU_START_INFO1_MSDU_LENGTH, len);
+
+	desc->u.wcn6855.msdu_start.info1 = __cpu_to_le32(info);
+}
+
+static
+struct rx_attention *ath11k_hw_wcn6855_rx_desc_get_attention(struct hal_rx_desc *desc)
+{
+	return &desc->u.wcn6855.attention;
+}
+
+static u8 *ath11k_hw_wcn6855_rx_desc_get_msdu_payload(struct hal_rx_desc *desc)
+{
+	return &desc->u.wcn6855.msdu_payload[0];
+}
+
 const struct ath11k_hw_ops ipq8074_ops = {
 	.get_hw_mac_from_pdev_id = ath11k_hw_ipq8074_mac_from_pdev_id,
 	.wmi_init_config = ath11k_init_wmi_config_ipq8074,
@@ -625,6 +792,40 @@ const struct ath11k_hw_ops qcn9074_ops = {
 	.rx_desc_get_msdu_payload = ath11k_hw_qcn9074_rx_desc_get_msdu_payload,
 };
 
+const struct ath11k_hw_ops wcn6855_ops = {
+	.get_hw_mac_from_pdev_id = ath11k_hw_ipq8074_mac_from_pdev_id,
+	.wmi_init_config = ath11k_init_wmi_config_qca6390,
+	.mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_qca6390,
+	.mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_qca6390,
+	.tx_mesh_enable = ath11k_hw_wcn6855_tx_mesh_enable,
+	.rx_desc_get_first_msdu = ath11k_hw_wcn6855_rx_desc_get_first_msdu,
+	.rx_desc_get_last_msdu = ath11k_hw_wcn6855_rx_desc_get_last_msdu,
+	.rx_desc_get_l3_pad_bytes = ath11k_hw_wcn6855_rx_desc_get_l3_pad_bytes,
+	.rx_desc_get_hdr_status = ath11k_hw_wcn6855_rx_desc_get_hdr_status,
+	.rx_desc_encrypt_valid = ath11k_hw_wcn6855_rx_desc_encrypt_valid,
+	.rx_desc_get_encrypt_type = ath11k_hw_wcn6855_rx_desc_get_encrypt_type,
+	.rx_desc_get_decap_type = ath11k_hw_wcn6855_rx_desc_get_decap_type,
+	.rx_desc_get_mesh_ctl = ath11k_hw_wcn6855_rx_desc_get_mesh_ctl,
+	.rx_desc_get_mpdu_seq_ctl_vld = ath11k_hw_wcn6855_rx_desc_get_mpdu_seq_ctl_vld,
+	.rx_desc_get_mpdu_fc_valid = ath11k_hw_wcn6855_rx_desc_get_mpdu_fc_valid,
+	.rx_desc_get_mpdu_start_seq_no = ath11k_hw_wcn6855_rx_desc_get_mpdu_start_seq_no,
+	.rx_desc_get_msdu_len = ath11k_hw_wcn6855_rx_desc_get_msdu_len,
+	.rx_desc_get_msdu_sgi = ath11k_hw_wcn6855_rx_desc_get_msdu_sgi,
+	.rx_desc_get_msdu_rate_mcs = ath11k_hw_wcn6855_rx_desc_get_msdu_rate_mcs,
+	.rx_desc_get_msdu_rx_bw = ath11k_hw_wcn6855_rx_desc_get_msdu_rx_bw,
+	.rx_desc_get_msdu_freq = ath11k_hw_wcn6855_rx_desc_get_msdu_freq,
+	.rx_desc_get_msdu_pkt_type = ath11k_hw_wcn6855_rx_desc_get_msdu_pkt_type,
+	.rx_desc_get_msdu_nss = ath11k_hw_wcn6855_rx_desc_get_msdu_nss,
+	.rx_desc_get_mpdu_tid = ath11k_hw_wcn6855_rx_desc_get_mpdu_tid,
+	.rx_desc_get_mpdu_peer_id = ath11k_hw_wcn6855_rx_desc_get_mpdu_peer_id,
+	.rx_desc_copy_attn_end_tlv = ath11k_hw_wcn6855_rx_desc_copy_attn_end,
+	.rx_desc_get_mpdu_start_tag = ath11k_hw_wcn6855_rx_desc_get_mpdu_start_tag,
+	.rx_desc_get_mpdu_ppdu_id = ath11k_hw_wcn6855_rx_desc_get_mpdu_ppdu_id,
+	.rx_desc_set_msdu_len = ath11k_hw_wcn6855_rx_desc_set_msdu_len,
+	.rx_desc_get_attention = ath11k_hw_wcn6855_rx_desc_get_attention,
+	.rx_desc_get_msdu_payload = ath11k_hw_wcn6855_rx_desc_get_msdu_payload,
+};
+
 #define ATH11K_TX_RING_MASK_0 0x1
 #define ATH11K_TX_RING_MASK_1 0x2
 #define ATH11K_TX_RING_MASK_2 0x4
diff --git a/drivers/net/wireless/ath/ath11k/hw.h b/drivers/net/wireless/ath/ath11k/hw.h
index 4e7261c0dca1..6e924f628f22 100644
--- a/drivers/net/wireless/ath/ath11k/hw.h
+++ b/drivers/net/wireless/ath/ath11k/hw.h
@@ -205,6 +205,7 @@ extern const struct ath11k_hw_ops ipq8074_ops;
 extern const struct ath11k_hw_ops ipq6018_ops;
 extern const struct ath11k_hw_ops qca6390_ops;
 extern const struct ath11k_hw_ops qcn9074_ops;
+extern const struct ath11k_hw_ops wcn6855_ops;
 
 extern const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_ipq8074;
 extern const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_qca6390;
diff --git a/drivers/net/wireless/ath/ath11k/rx_desc.h b/drivers/net/wireless/ath/ath11k/rx_desc.h
index 0cdb4a1f816e..79c50804d7dc 100644
--- a/drivers/net/wireless/ath/ath11k/rx_desc.h
+++ b/drivers/net/wireless/ath/ath11k/rx_desc.h
@@ -368,6 +368,7 @@ struct rx_attention {
 #define RX_MPDU_START_INFO2_BSSID_HIT		BIT(9)
 #define RX_MPDU_START_INFO2_BSSID_NUM		GENMASK(13, 10)
 #define RX_MPDU_START_INFO2_TID			GENMASK(17, 14)
+#define RX_MPDU_START_INFO2_TID_WCN6855		GENMASK(18, 15)
 
 #define RX_MPDU_START_INFO3_REO_DEST_IND		GENMASK(4, 0)
 #define RX_MPDU_START_INFO3_FLOW_ID_TOEPLITZ		BIT(7)
@@ -546,6 +547,31 @@ struct rx_mpdu_start_qcn9074 {
 	__le32 ht_ctrl;
 } __packed;
 
+struct rx_mpdu_start_wcn6855 {
+	__le32 info3;
+	__le32 reo_queue_desc_lo;
+	__le32 info4;
+	__le32 pn[4];
+	__le32 info2;
+	__le32 peer_meta_data;
+	__le16 info0;
+	__le16 phy_ppdu_id;
+	__le16 ast_index;
+	__le16 sw_peer_id;
+	__le32 info1;
+	__le32 info5;
+	__le32 info6;
+	__le16 frame_ctrl;
+	__le16 duration;
+	u8 addr1[ETH_ALEN];
+	u8 addr2[ETH_ALEN];
+	u8 addr3[ETH_ALEN];
+	__le16 seq_ctrl;
+	u8 addr4[ETH_ALEN];
+	__le16 qos_ctrl;
+	__le32 ht_ctrl;
+} __packed;
+
 /* rx_mpdu_start
  *
  * rxpcu_mpdu_filter_in_category
@@ -804,6 +830,20 @@ struct rx_msdu_start_qcn9074 {
 	__le16 vlan_stag_c1;
 } __packed;
 
+struct rx_msdu_start_wcn6855 {
+	__le16 info0;
+	__le16 phy_ppdu_id;
+	__le32 info1;
+	__le32 info2;
+	__le32 toeplitz_hash;
+	__le32 flow_id_toeplitz;
+	__le32 info3;
+	__le32 ppdu_start_timestamp;
+	__le32 phy_meta_data;
+	__le16 vlan_ctag_ci;
+	__le16 vlan_stag_ci;
+} __packed;
+
 /* rx_msdu_start
  *
  * rxpcu_mpdu_filter_in_category
@@ -988,7 +1028,9 @@ struct rx_msdu_start_qcn9074 {
 
 #define RX_MSDU_END_INFO2_REPORTED_MPDU_LEN	GENMASK(13, 0)
 #define RX_MSDU_END_INFO2_FIRST_MSDU		BIT(14)
+#define RX_MSDU_END_INFO2_FIRST_MSDU_WCN6855	BIT(28)
 #define RX_MSDU_END_INFO2_LAST_MSDU		BIT(15)
+#define RX_MSDU_END_INFO2_LAST_MSDU_WCN6855	BIT(29)
 #define RX_MSDU_END_INFO2_SA_IDX_TIMEOUT	BIT(16)
 #define RX_MSDU_END_INFO2_DA_IDX_TIMEOUT	BIT(17)
 #define RX_MSDU_END_INFO2_MSDU_LIMIT_ERR	BIT(18)
@@ -1037,6 +1079,31 @@ struct rx_msdu_end_ipq8074 {
 	__le16 sa_sw_peer_id;
 } __packed;
 
+struct rx_msdu_end_wcn6855 {
+	__le16 info0;
+	__le16 phy_ppdu_id;
+	__le16 ip_hdr_cksum;
+	__le16 reported_mpdu_len;
+	__le32 info1;
+	__le32 ext_wapi_pn[2];
+	__le32 info4;
+	__le32 ipv6_options_crc;
+	__le32 tcp_seq_num;
+	__le32 tcp_ack_num;
+	__le16 info3;
+	__le16 window_size;
+	__le32 info2;
+	__le16 sa_idx;
+	__le16 da_idx;
+	__le32 info5;
+	__le32 fse_metadata;
+	__le16 cce_metadata;
+	__le16 sa_sw_peer_id;
+	__le32 rule_indication[2];
+	__le32 info6;
+	__le32 info7;
+} __packed;
+
 #define RX_MSDU_END_MPDU_LENGTH_INFO		GENMASK(13, 0)
 
 #define RX_MSDU_END_INFO2_DA_OFFSET		GENMASK(5, 0)
@@ -1400,10 +1467,30 @@ struct hal_rx_desc_qcn9074 {
 	u8 msdu_payload[0];
 } __packed;
 
+struct hal_rx_desc_wcn6855 {
+	__le32 msdu_end_tag;
+	struct rx_msdu_end_wcn6855 msdu_end;
+	__le32 rx_attn_tag;
+	struct rx_attention attention;
+	__le32 msdu_start_tag;
+	struct rx_msdu_start_wcn6855 msdu_start;
+	u8 rx_padding0[HAL_RX_DESC_PADDING0_BYTES];
+	__le32 mpdu_start_tag;
+	struct rx_mpdu_start_wcn6855 mpdu_start;
+	__le32 mpdu_end_tag;
+	struct rx_mpdu_end mpdu_end;
+	u8 rx_padding1[HAL_RX_DESC_PADDING1_BYTES];
+	__le32 hdr_status_tag;
+	__le32 phy_ppdu_id;
+	u8 hdr_status[HAL_RX_DESC_HDR_STATUS_LEN];
+	u8 msdu_payload[0];
+} __packed;
+
 struct hal_rx_desc {
 	union {
 		struct hal_rx_desc_ipq8074 ipq8074;
 		struct hal_rx_desc_qcn9074 qcn9074;
+		struct hal_rx_desc_wcn6855 wcn6855;
 	} u;
 } __packed;
 
-- 
2.25.1



From jouni at codeaurora.org  Tue May 11 17:22:13 2021
From: jouni at codeaurora.org (Jouni Malinen)
Date: Tue, 11 May 2021 19:22:13 +0300
Subject: [PATCH 6/7] ath11k: add support for WCN6855
In-Reply-To: <20210511162214.29475-1-jouni@codeaurora.org>
References: <20210511162214.29475-1-jouni@codeaurora.org>
Message-ID: <20210511162214.29475-7-jouni@codeaurora.org>

From: Baochen Qiang <bqiang at codeaurora.org>

This patch is to add support for WCN6855. For station mode,
WCN6855 is able to connect to an AP, and ping works well.
For AP mode, hostapd is able to bringup an SAP interface with
WCN6855, a normal station can connect to this AP and
ping works well.

Tested-on: WCN6855 hw2.0 PCI WLAN.HSP.1.1-01720.1-QCAHSPSWPL_V1_V2_SILICONZ_LITE-1
Tested-on: QCA6390 hw2.0 PCI WLAN.HST.1.0.1-01740-QCAHSTSWPLZ_V2_TO_X86-1

Signed-off-by: Baochen Qiang <bqiang at codeaurora.org>
Signed-off-by: Jouni Malinen <jouni at codeaurora.org>
---
 drivers/net/wireless/ath/ath11k/core.c | 39 ++++++++++++++++++++++++
 drivers/net/wireless/ath/ath11k/core.h |  1 +
 drivers/net/wireless/ath/ath11k/mhi.c  |  1 +
 drivers/net/wireless/ath/ath11k/pci.c  | 42 ++++++++++++++++++++------
 4 files changed, 73 insertions(+), 10 deletions(-)

diff --git a/drivers/net/wireless/ath/ath11k/core.c b/drivers/net/wireless/ath/ath11k/core.c
index 77ce3347ab86..fd8941905fdb 100644
--- a/drivers/net/wireless/ath/ath11k/core.c
+++ b/drivers/net/wireless/ath/ath11k/core.c
@@ -187,6 +187,45 @@ static const struct ath11k_hw_params ath11k_hw_params[] = {
 		.supports_suspend = false,
 		.hal_desc_sz = sizeof(struct hal_rx_desc_qcn9074),
 	},
+	{
+		.name = "wcn6855 hw2.0",
+		.hw_rev = ATH11K_HW_WCN6855_HW20,
+		.fw = {
+			.dir = "WCN6855/hw2.0",
+			.board_size = 256 * 1024,
+			.cal_size = 256 * 1024,
+		},
+		.max_radios = 3,
+		.bdf_addr = 0x4B0C0000,
+		.hw_ops = &wcn6855_ops,
+		.ring_mask = &ath11k_hw_ring_mask_qca6390,
+		.internal_sleep_clock = true,
+		.regs = &wcn6855_regs,
+		.qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCA6390,
+		.host_ce_config = ath11k_host_ce_config_qca6390,
+		.ce_count = 9,
+		.target_ce_config = ath11k_target_ce_config_wlan_qca6390,
+		.target_ce_count = 9,
+		.svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390,
+		.svc_to_ce_map_len = 14,
+		.single_pdev_only = true,
+		.rxdma1_enable = false,
+		.num_rxmda_per_pdev = 2,
+		.rx_mac_buf_ring = true,
+		.vdev_start_delay = true,
+		.htt_peer_map_v2 = false,
+		.tcl_0_only = true,
+		.spectral_fft_sz = 0,
+
+		.interface_modes = BIT(NL80211_IFTYPE_STATION) |
+					BIT(NL80211_IFTYPE_AP),
+		.supports_monitor = false,
+		.supports_shadow_regs = true,
+		.idle_ps = true,
+		.cold_boot_calib = false,
+		.supports_suspend = true,
+		.hal_desc_sz = sizeof(struct hal_rx_desc_wcn6855),
+	},
 };
 
 int ath11k_core_suspend(struct ath11k_base *ab)
diff --git a/drivers/net/wireless/ath/ath11k/core.h b/drivers/net/wireless/ath/ath11k/core.h
index 55af982deca7..6bd3bc5cee2f 100644
--- a/drivers/net/wireless/ath/ath11k/core.h
+++ b/drivers/net/wireless/ath/ath11k/core.h
@@ -107,6 +107,7 @@ enum ath11k_hw_rev {
 	ATH11K_HW_QCA6390_HW20,
 	ATH11K_HW_IPQ6018_HW10,
 	ATH11K_HW_QCN9074_HW10,
+	ATH11K_HW_WCN6855_HW20,
 };
 
 enum ath11k_firmware_mode {
diff --git a/drivers/net/wireless/ath/ath11k/mhi.c b/drivers/net/wireless/ath/ath11k/mhi.c
index 27b394d115e2..75cc2d80fde8 100644
--- a/drivers/net/wireless/ath/ath11k/mhi.c
+++ b/drivers/net/wireless/ath/ath11k/mhi.c
@@ -354,6 +354,7 @@ int ath11k_mhi_register(struct ath11k_pci *ab_pci)
 		ath11k_mhi_config = &ath11k_mhi_config_qcn9074;
 		break;
 	case ATH11K_HW_QCA6390_HW20:
+	case ATH11K_HW_WCN6855_HW20:
 		ath11k_mhi_config = &ath11k_mhi_config_qca6390;
 		break;
 	default:
diff --git a/drivers/net/wireless/ath/ath11k/pci.c b/drivers/net/wireless/ath/ath11k/pci.c
index 0f31eb566fb6..d33b5d66b494 100644
--- a/drivers/net/wireless/ath/ath11k/pci.c
+++ b/drivers/net/wireless/ath/ath11k/pci.c
@@ -36,9 +36,11 @@
 
 #define QCA6390_DEVICE_ID		0x1101
 #define QCN9074_DEVICE_ID		0x1104
+#define WCN6855_DEVICE_ID		0x1103
 
 static const struct pci_device_id ath11k_pci_id_table[] = {
 	{ PCI_VDEVICE(QCOM, QCA6390_DEVICE_ID) },
+	{ PCI_VDEVICE(QCOM, WCN6855_DEVICE_ID) },
 	/* TODO: add QCN9074_DEVICE_ID) once firmware issues are resolved */
 	{0}
 };
@@ -1176,12 +1178,26 @@ static const struct ath11k_hif_ops ath11k_pci_hif_ops = {
 	.get_ce_msi_idx = ath11k_pci_get_ce_msi_idx,
 };
 
+static void ath11k_pci_read_hw_version(struct ath11k_base *ab, u32 *major, u32 *minor)
+{
+	u32 soc_hw_version;
+
+	soc_hw_version = ath11k_pci_read32(ab, TCSR_SOC_HW_VERSION);
+	*major = FIELD_GET(TCSR_SOC_HW_VERSION_MAJOR_MASK,
+			   soc_hw_version);
+	*minor = FIELD_GET(TCSR_SOC_HW_VERSION_MINOR_MASK,
+			   soc_hw_version);
+
+	ath11k_dbg(ab, ATH11K_DBG_PCI, "pci tcsr_soc_hw_version major %d minor %d\n",
+		   *major, *minor);
+}
+
 static int ath11k_pci_probe(struct pci_dev *pdev,
 			    const struct pci_device_id *pci_dev)
 {
 	struct ath11k_base *ab;
 	struct ath11k_pci *ab_pci;
-	u32 soc_hw_version, soc_hw_version_major, soc_hw_version_minor;
+	u32 soc_hw_version_major, soc_hw_version_minor;
 	int ret;
 
 	ab = ath11k_core_alloc(&pdev->dev, sizeof(*ab_pci), ATH11K_BUS_PCI,
@@ -1209,15 +1225,7 @@ static int ath11k_pci_probe(struct pci_dev *pdev,
 
 	switch (pci_dev->device) {
 	case QCA6390_DEVICE_ID:
-		soc_hw_version = ath11k_pci_read32(ab, TCSR_SOC_HW_VERSION);
-		soc_hw_version_major = FIELD_GET(TCSR_SOC_HW_VERSION_MAJOR_MASK,
-						 soc_hw_version);
-		soc_hw_version_minor = FIELD_GET(TCSR_SOC_HW_VERSION_MINOR_MASK,
-						 soc_hw_version);
-
-		ath11k_dbg(ab, ATH11K_DBG_PCI, "pci tcsr_soc_hw_version major %d minor %d\n",
-			   soc_hw_version_major, soc_hw_version_minor);
-
+		ath11k_pci_read_hw_version(ab, &soc_hw_version_major, &soc_hw_version_minor);
 		switch (soc_hw_version_major) {
 		case 2:
 			ab->hw_rev = ATH11K_HW_QCA6390_HW20;
@@ -1235,6 +1243,20 @@ static int ath11k_pci_probe(struct pci_dev *pdev,
 		ab->bus_params.static_window_map = true;
 		ab->hw_rev = ATH11K_HW_QCN9074_HW10;
 		break;
+	case WCN6855_DEVICE_ID:
+		ath11k_pci_read_hw_version(ab, &soc_hw_version_major, &soc_hw_version_minor);
+		switch (soc_hw_version_major) {
+		case 2:
+			ab->hw_rev = ATH11K_HW_WCN6855_HW20;
+			break;
+		default:
+			dev_err(&pdev->dev, "Unsupported WCN6855 SOC hardware version: %d %d\n",
+				soc_hw_version_major, soc_hw_version_minor);
+			ret = -EOPNOTSUPP;
+			goto err_pci_free_region;
+		}
+		ab_pci->msi_config = &ath11k_msi_config[0];
+		break;
 	default:
 		dev_err(&pdev->dev, "Unknown PCI device found: 0x%x\n",
 			pci_dev->device);
-- 
2.25.1



From jouni at codeaurora.org  Tue May 11 17:22:11 2021
From: jouni at codeaurora.org (Jouni Malinen)
Date: Tue, 11 May 2021 19:22:11 +0300
Subject: [PATCH 4/7] ath11k: setup WBM_IDLE_LINK ring once again
In-Reply-To: <20210511162214.29475-1-jouni@codeaurora.org>
References: <20210511162214.29475-1-jouni@codeaurora.org>
Message-ID: <20210511162214.29475-5-jouni@codeaurora.org>

From: Baochen Qiang <bqiang at codeaurora.org>

For WCN6855, WBM idle link ring needs a reinit.
Without this reinit, firmware crash might happen occasionally.
This is requested by the hw team.

Tested-on: WCN6855 hw2.0 PCI WLAN.HSP.1.1-01720.1-QCAHSPSWPL_V1_V2_SILICONZ_LITE-1
Tested-on: QCA6390 hw2.0 PCI WLAN.HST.1.0.1-01740-QCAHSTSWPLZ_V2_TO_X86-1

Signed-off-by: Baochen Qiang <bqiang at codeaurora.org>
Signed-off-by: Jouni Malinen <jouni at codeaurora.org>
---
 drivers/net/wireless/ath/ath11k/hal.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/net/wireless/ath/ath11k/hal.c b/drivers/net/wireless/ath/ath11k/hal.c
index 08e3c72d9237..eaa0edca5576 100644
--- a/drivers/net/wireless/ath/ath11k/hal.c
+++ b/drivers/net/wireless/ath/ath11k/hal.c
@@ -382,6 +382,16 @@ static void ath11k_hal_srng_src_hw_init(struct ath11k_base *ab,
 	val = FIELD_PREP(HAL_REO1_RING_ID_ENTRY_SIZE, srng->entry_size);
 	ath11k_hif_write32(ab, reg_base + HAL_TCL1_RING_ID_OFFSET(ab), val);
 
+	if (srng->ring_id == HAL_SRNG_RING_ID_WBM_IDLE_LINK) {
+		ath11k_hif_write32(ab, reg_base, (u32)srng->ring_base_paddr);
+		val = FIELD_PREP(HAL_TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB,
+				 ((u64)srng->ring_base_paddr >>
+				 HAL_ADDR_MSB_REG_SHIFT)) |
+			FIELD_PREP(HAL_TCL1_RING_BASE_MSB_RING_SIZE,
+				   (srng->entry_size * srng->num_entries));
+		ath11k_hif_write32(ab, reg_base + HAL_TCL1_RING_BASE_MSB_OFFSET(ab), val);
+	}
+
 	/* interrupt setup */
 	/* NOTE: IPQ8074 v2 requires the interrupt timer threshold in the
 	 * unit of 8 usecs instead of 1 usec (as required by v1).
-- 
2.25.1



From jouni at codeaurora.org  Tue May 11 17:22:14 2021
From: jouni at codeaurora.org (Jouni Malinen)
Date: Tue, 11 May 2021 19:22:14 +0300
Subject: [PATCH 7/7] ath11k: don't call ath11k_pci_set_l1ss for WCN6855
In-Reply-To: <20210511162214.29475-1-jouni@codeaurora.org>
References: <20210511162214.29475-1-jouni@codeaurora.org>
Message-ID: <20210511162214.29475-8-jouni@codeaurora.org>

From: Baochen Qiang <bqiang at codeaurora.org>

For QCA6390, one PCI related clock drifts sometimes, and it makes
PCI link difficult to quit L1ss. Current implementation fixed this
by configuring some related regs using ath11k_pci_fix_l1ss.

WCN6855 does not have this clock drift problem, so no need to set
these regs.

Tested-on: WCN6855 hw2.0 PCI WLAN.HSP.1.1-01720.1-QCAHSPSWPL_V1_V2_SILICONZ_LITE-1
Tested-on: QCA6390 hw2.0 PCI WLAN.HST.1.0.1-01740-QCAHSTSWPLZ_V2_TO_X86-1

Signed-off-by: Baochen Qiang <bqiang at codeaurora.org>
Signed-off-by: Jouni Malinen <jouni at codeaurora.org>
---
 drivers/net/wireless/ath/ath11k/core.c | 5 +++++
 drivers/net/wireless/ath/ath11k/hw.h   | 1 +
 drivers/net/wireless/ath/ath11k/pci.c  | 3 ++-
 3 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/net/wireless/ath/ath11k/core.c b/drivers/net/wireless/ath/ath11k/core.c
index fd8941905fdb..4a1051418f33 100644
--- a/drivers/net/wireless/ath/ath11k/core.c
+++ b/drivers/net/wireless/ath/ath11k/core.c
@@ -70,6 +70,7 @@ static const struct ath11k_hw_params ath11k_hw_params[] = {
 		.cold_boot_calib = true,
 		.supports_suspend = false,
 		.hal_desc_sz = sizeof(struct hal_rx_desc_ipq8074),
+		.fix_l1ss = true,
 	},
 	{
 		.hw_rev = ATH11K_HW_IPQ6018_HW10,
@@ -110,6 +111,7 @@ static const struct ath11k_hw_params ath11k_hw_params[] = {
 		.cold_boot_calib = true,
 		.supports_suspend = false,
 		.hal_desc_sz = sizeof(struct hal_rx_desc_ipq8074),
+		.fix_l1ss = true,
 	},
 	{
 		.name = "qca6390 hw2.0",
@@ -149,6 +151,7 @@ static const struct ath11k_hw_params ath11k_hw_params[] = {
 		.cold_boot_calib = false,
 		.supports_suspend = true,
 		.hal_desc_sz = sizeof(struct hal_rx_desc_ipq8074),
+		.fix_l1ss = true,
 	},
 	{
 		.name = "qcn9074 hw1.0",
@@ -186,6 +189,7 @@ static const struct ath11k_hw_params ath11k_hw_params[] = {
 		.cold_boot_calib = false,
 		.supports_suspend = false,
 		.hal_desc_sz = sizeof(struct hal_rx_desc_qcn9074),
+		.fix_l1ss = true,
 	},
 	{
 		.name = "wcn6855 hw2.0",
@@ -225,6 +229,7 @@ static const struct ath11k_hw_params ath11k_hw_params[] = {
 		.cold_boot_calib = false,
 		.supports_suspend = true,
 		.hal_desc_sz = sizeof(struct hal_rx_desc_wcn6855),
+		.fix_l1ss = false,
 	},
 };
 
diff --git a/drivers/net/wireless/ath/ath11k/hw.h b/drivers/net/wireless/ath/ath11k/hw.h
index be62f0c2e25e..62f5978b3005 100644
--- a/drivers/net/wireless/ath/ath11k/hw.h
+++ b/drivers/net/wireless/ath/ath11k/hw.h
@@ -162,6 +162,7 @@ struct ath11k_hw_params {
 	bool cold_boot_calib;
 	bool supports_suspend;
 	u32 hal_desc_sz;
+	bool fix_l1ss;
 };
 
 struct ath11k_hw_ops {
diff --git a/drivers/net/wireless/ath/ath11k/pci.c b/drivers/net/wireless/ath/ath11k/pci.c
index d33b5d66b494..9fe42194f488 100644
--- a/drivers/net/wireless/ath/ath11k/pci.c
+++ b/drivers/net/wireless/ath/ath11k/pci.c
@@ -434,7 +434,8 @@ static void ath11k_pci_sw_reset(struct ath11k_base *ab, bool power_on)
 		ath11k_pci_enable_ltssm(ab);
 		ath11k_pci_clear_all_intrs(ab);
 		ath11k_pci_set_wlaon_pwr_ctrl(ab);
-		ath11k_pci_fix_l1ss(ab);
+		if (ab->hw_params.fix_l1ss)
+			ath11k_pci_fix_l1ss(ab);
 	}
 
 	ath11k_mhi_clear_vector(ab);
-- 
2.25.1



From jouni at codeaurora.org  Tue May 11 17:22:12 2021
From: jouni at codeaurora.org (Jouni Malinen)
Date: Tue, 11 May 2021 19:22:12 +0300
Subject: [PATCH 5/7] ath11k: add support to get peer id for WCN6855
In-Reply-To: <20210511162214.29475-1-jouni@codeaurora.org>
References: <20210511162214.29475-1-jouni@codeaurora.org>
Message-ID: <20210511162214.29475-6-jouni@codeaurora.org>

From: Baochen Qiang <bqiang at codeaurora.org>

For WCN6855, the layout of hal rx mpdu info is different, so need to
handle this target differently when getting peer id.

Tested-on: WCN6855 hw2.0 PCI WLAN.HSP.1.1-01720.1-QCAHSPSWPL_V1_V2_SILICONZ_LITE-1
Tested-on: QCA6390 hw2.0 PCI WLAN.HST.1.0.1-01740-QCAHSTSWPLZ_V2_TO_X86-1

Signed-off-by: Baochen Qiang <bqiang at codeaurora.org>
Signed-off-by: Jouni Malinen <jouni at codeaurora.org>
---
 drivers/net/wireless/ath/ath11k/hal_rx.c |  5 +----
 drivers/net/wireless/ath/ath11k/hal_rx.h |  8 +++++++
 drivers/net/wireless/ath/ath11k/hw.c     | 28 ++++++++++++++++++++++++
 drivers/net/wireless/ath/ath11k/hw.h     |  1 +
 4 files changed, 38 insertions(+), 4 deletions(-)

diff --git a/drivers/net/wireless/ath/ath11k/hal_rx.c b/drivers/net/wireless/ath/ath11k/hal_rx.c
index b479d93bee32..95d77468e87e 100644
--- a/drivers/net/wireless/ath/ath11k/hal_rx.c
+++ b/drivers/net/wireless/ath/ath11k/hal_rx.c
@@ -1092,12 +1092,9 @@ ath11k_hal_rx_parse_mon_status_tlv(struct ath11k_base *ab,
 		break;
 	}
 	case HAL_RX_MPDU_START: {
-		struct hal_rx_mpdu_info *mpdu_info =
-			(struct hal_rx_mpdu_info *)tlv_data;
 		u16 peer_id;
 
-		peer_id = FIELD_GET(HAL_RX_MPDU_INFO_INFO0_PEERID,
-				    __le32_to_cpu(mpdu_info->info0));
+		peer_id = ab->hw_params.hw_ops->mpdu_info_get_peerid(tlv_data);
 		if (peer_id)
 			ppdu_info->peer_id = peer_id;
 		break;
diff --git a/drivers/net/wireless/ath/ath11k/hal_rx.h b/drivers/net/wireless/ath/ath11k/hal_rx.h
index d464a270c049..0f1f04b812b9 100644
--- a/drivers/net/wireless/ath/ath11k/hal_rx.h
+++ b/drivers/net/wireless/ath/ath11k/hal_rx.h
@@ -254,12 +254,20 @@ struct hal_rx_phyrx_rssi_legacy_info {
 } __packed;
 
 #define HAL_RX_MPDU_INFO_INFO0_PEERID	GENMASK(31, 16)
+#define HAL_RX_MPDU_INFO_INFO0_PEERID_WCN6855	GENMASK(15, 0)
+
 struct hal_rx_mpdu_info {
 	__le32 rsvd0;
 	__le32 info0;
 	__le32 rsvd1[21];
 } __packed;
 
+struct hal_rx_mpdu_info_wcn6855 {
+	__le32 rsvd0[8];
+	__le32 info0;
+	__le32 rsvd1[14];
+} __packed;
+
 #define HAL_RX_PPDU_END_DURATION	GENMASK(23, 0)
 struct hal_rx_ppdu_end_duration {
 	__le32 rsvd0[9];
diff --git a/drivers/net/wireless/ath/ath11k/hw.c b/drivers/net/wireless/ath/ath11k/hw.c
index 01207b50a454..d9596903b0a5 100644
--- a/drivers/net/wireless/ath/ath11k/hw.c
+++ b/drivers/net/wireless/ath/ath11k/hw.c
@@ -742,6 +742,29 @@ static void ath11k_hw_wcn6855_reo_setup(struct ath11k_base *ab)
 			   ring_hash_map);
 }
 
+static u16 ath11k_hw_ipq8074_mpdu_info_get_peerid(u8 *tlv_data)
+{
+	u16 peer_id = 0;
+	struct hal_rx_mpdu_info *mpdu_info =
+		(struct hal_rx_mpdu_info *)tlv_data;
+
+	peer_id = FIELD_GET(HAL_RX_MPDU_INFO_INFO0_PEERID,
+			    __le32_to_cpu(mpdu_info->info0));
+
+	return peer_id;
+}
+
+static u16 ath11k_hw_wcn6855_mpdu_info_get_peerid(u8 *tlv_data)
+{
+	u16 peer_id = 0;
+	struct hal_rx_mpdu_info_wcn6855 *mpdu_info =
+		(struct hal_rx_mpdu_info_wcn6855 *)tlv_data;
+
+	peer_id = FIELD_GET(HAL_RX_MPDU_INFO_INFO0_PEERID_WCN6855,
+			    __le32_to_cpu(mpdu_info->info0));
+	return peer_id;
+}
+
 const struct ath11k_hw_ops ipq8074_ops = {
 	.get_hw_mac_from_pdev_id = ath11k_hw_ipq8074_mac_from_pdev_id,
 	.wmi_init_config = ath11k_init_wmi_config_ipq8074,
@@ -775,6 +798,7 @@ const struct ath11k_hw_ops ipq8074_ops = {
 	.rx_desc_get_attention = ath11k_hw_ipq8074_rx_desc_get_attention,
 	.rx_desc_get_msdu_payload = ath11k_hw_ipq8074_rx_desc_get_msdu_payload,
 	.reo_setup = ath11k_hw_ipq8074_reo_setup,
+	.mpdu_info_get_peerid = ath11k_hw_ipq8074_mpdu_info_get_peerid,
 };
 
 const struct ath11k_hw_ops ipq6018_ops = {
@@ -810,6 +834,7 @@ const struct ath11k_hw_ops ipq6018_ops = {
 	.rx_desc_get_attention = ath11k_hw_ipq8074_rx_desc_get_attention,
 	.rx_desc_get_msdu_payload = ath11k_hw_ipq8074_rx_desc_get_msdu_payload,
 	.reo_setup = ath11k_hw_ipq8074_reo_setup,
+	.mpdu_info_get_peerid = ath11k_hw_ipq8074_mpdu_info_get_peerid,
 };
 
 const struct ath11k_hw_ops qca6390_ops = {
@@ -845,6 +870,7 @@ const struct ath11k_hw_ops qca6390_ops = {
 	.rx_desc_get_attention = ath11k_hw_ipq8074_rx_desc_get_attention,
 	.rx_desc_get_msdu_payload = ath11k_hw_ipq8074_rx_desc_get_msdu_payload,
 	.reo_setup = ath11k_hw_ipq8074_reo_setup,
+	.mpdu_info_get_peerid = ath11k_hw_ipq8074_mpdu_info_get_peerid,
 };
 
 const struct ath11k_hw_ops qcn9074_ops = {
@@ -880,6 +906,7 @@ const struct ath11k_hw_ops qcn9074_ops = {
 	.rx_desc_get_attention = ath11k_hw_qcn9074_rx_desc_get_attention,
 	.rx_desc_get_msdu_payload = ath11k_hw_qcn9074_rx_desc_get_msdu_payload,
 	.reo_setup = ath11k_hw_ipq8074_reo_setup,
+	.mpdu_info_get_peerid = ath11k_hw_ipq8074_mpdu_info_get_peerid,
 };
 
 const struct ath11k_hw_ops wcn6855_ops = {
@@ -915,6 +942,7 @@ const struct ath11k_hw_ops wcn6855_ops = {
 	.rx_desc_get_attention = ath11k_hw_wcn6855_rx_desc_get_attention,
 	.rx_desc_get_msdu_payload = ath11k_hw_wcn6855_rx_desc_get_msdu_payload,
 	.reo_setup = ath11k_hw_wcn6855_reo_setup,
+	.mpdu_info_get_peerid = ath11k_hw_wcn6855_mpdu_info_get_peerid,
 };
 
 #define ATH11K_TX_RING_MASK_0 0x1
diff --git a/drivers/net/wireless/ath/ath11k/hw.h b/drivers/net/wireless/ath/ath11k/hw.h
index afe3b3c71695..be62f0c2e25e 100644
--- a/drivers/net/wireless/ath/ath11k/hw.h
+++ b/drivers/net/wireless/ath/ath11k/hw.h
@@ -200,6 +200,7 @@ struct ath11k_hw_ops {
 	struct rx_attention *(*rx_desc_get_attention)(struct hal_rx_desc *desc);
 	u8 *(*rx_desc_get_msdu_payload)(struct hal_rx_desc *desc);
 	void (*reo_setup)(struct ath11k_base *ab);
+	u16 (*mpdu_info_get_peerid)(u8 *tlv_data);
 };
 
 extern const struct ath11k_hw_ops ipq8074_ops;
-- 
2.25.1



From jouni at codeaurora.org  Tue May 11 17:22:10 2021
From: jouni at codeaurora.org (Jouni Malinen)
Date: Tue, 11 May 2021 19:22:10 +0300
Subject: [PATCH 3/7] ath11k: setup REO for WCN6855
In-Reply-To: <20210511162214.29475-1-jouni@codeaurora.org>
References: <20210511162214.29475-1-jouni@codeaurora.org>
Message-ID: <20210511162214.29475-4-jouni@codeaurora.org>

From: Baochen Qiang <bqiang at codeaurora.org>

WCN6855 needs a different reo configuration, so add separate handling
for this target in ath11k_hw_ops.

Tested-on: WCN6855 hw2.0 PCI WLAN.HSP.1.1-01720.1-QCAHSPSWPL_V1_V2_SILICONZ_LITE-1
Tested-on: QCA6390 hw2.0 PCI WLAN.HST.1.0.1-01740-QCAHSTSWPLZ_V2_TO_X86-1

Signed-off-by: Baochen Qiang <bqiang at codeaurora.org>
Signed-off-by: Jouni Malinen <jouni at codeaurora.org>
---
 drivers/net/wireless/ath/ath11k/dp.c     | 16 +----
 drivers/net/wireless/ath/ath11k/hal.h    |  3 +-
 drivers/net/wireless/ath/ath11k/hal_rx.c | 36 ----------
 drivers/net/wireless/ath/ath11k/hw.c     | 91 ++++++++++++++++++++++++
 drivers/net/wireless/ath/ath11k/hw.h     |  1 +
 5 files changed, 96 insertions(+), 51 deletions(-)

diff --git a/drivers/net/wireless/ath/ath11k/dp.c b/drivers/net/wireless/ath/ath11k/dp.c
index 04f6c4e0658b..b0c8f6290099 100644
--- a/drivers/net/wireless/ath/ath11k/dp.c
+++ b/drivers/net/wireless/ath/ath11k/dp.c
@@ -342,7 +342,6 @@ static int ath11k_dp_srng_common_setup(struct ath11k_base *ab)
 	struct ath11k_dp *dp = &ab->dp;
 	struct hal_srng *srng;
 	int i, ret;
-	u32 ring_hash_map;
 
 	ret = ath11k_dp_srng_setup(ab, &dp->wbm_desc_rel_ring,
 				   HAL_SW2WBM_RELEASE, 0, 0,
@@ -439,20 +438,9 @@ static int ath11k_dp_srng_common_setup(struct ath11k_base *ab)
 	}
 
 	/* When hash based routing of rx packet is enabled, 32 entries to map
-	 * the hash values to the ring will be configured. Each hash entry uses
-	 * three bits to map to a particular ring. The ring mapping will be
-	 * 0:TCL, 1:SW1, 2:SW2, 3:SW3, 4:SW4, 5:Release, 6:FW and 7:Not used.
+	 * the hash values to the ring will be configured.
 	 */
-	ring_hash_map = HAL_HASH_ROUTING_RING_SW1 << 0 |
-			HAL_HASH_ROUTING_RING_SW2 << 3 |
-			HAL_HASH_ROUTING_RING_SW3 << 6 |
-			HAL_HASH_ROUTING_RING_SW4 << 9 |
-			HAL_HASH_ROUTING_RING_SW1 << 12 |
-			HAL_HASH_ROUTING_RING_SW2 << 15 |
-			HAL_HASH_ROUTING_RING_SW3 << 18 |
-			HAL_HASH_ROUTING_RING_SW4 << 21;
-
-	ath11k_hal_reo_hw_setup(ab, ring_hash_map);
+	ab->hw_params.hw_ops->reo_setup(ab);
 
 	return 0;
 
diff --git a/drivers/net/wireless/ath/ath11k/hal.h b/drivers/net/wireless/ath/ath11k/hal.h
index 91d1428b8b94..35ed3a14e200 100644
--- a/drivers/net/wireless/ath/ath11k/hal.h
+++ b/drivers/net/wireless/ath/ath11k/hal.h
@@ -120,6 +120,7 @@ struct ath11k_base;
 #define HAL_REO1_DEST_RING_CTRL_IX_1		0x00000008
 #define HAL_REO1_DEST_RING_CTRL_IX_2		0x0000000c
 #define HAL_REO1_DEST_RING_CTRL_IX_3		0x00000010
+#define HAL_REO1_MISC_CTL			0x00000630
 #define HAL_REO1_RING_BASE_LSB(ab)		ab->hw_params.regs->hal_reo1_ring_base_lsb
 #define HAL_REO1_RING_BASE_MSB(ab)		ab->hw_params.regs->hal_reo1_ring_base_msb
 #define HAL_REO1_RING_ID(ab)			ab->hw_params.regs->hal_reo1_ring_id
@@ -280,6 +281,7 @@ struct ath11k_base;
 #define HAL_REO1_GEN_ENABLE_FRAG_DST_RING		GENMASK(25, 23)
 #define HAL_REO1_GEN_ENABLE_AGING_LIST_ENABLE		BIT(2)
 #define HAL_REO1_GEN_ENABLE_AGING_FLUSH_ENABLE		BIT(3)
+#define HAL_REO1_MISC_CTL_FRAGMENT_DST_RING		GENMASK(20, 17)
 
 /* CE ring bit field mask and shift */
 #define HAL_CE_DST_R0_DEST_CTRL_MAX_LEN			GENMASK(15, 0)
@@ -906,7 +908,6 @@ void ath11k_hal_reo_qdesc_setup(void *vaddr, int tid, u32 ba_window_size,
 				u32 start_seq, enum hal_pn_type type);
 void ath11k_hal_reo_init_cmd_ring(struct ath11k_base *ab,
 				  struct hal_srng *srng);
-void ath11k_hal_reo_hw_setup(struct ath11k_base *ab, u32 ring_hash_map);
 void ath11k_hal_setup_link_idle_list(struct ath11k_base *ab,
 				     struct hal_wbm_idle_scatter_list *sbuf,
 				     u32 nsbufs, u32 tot_link_desc,
diff --git a/drivers/net/wireless/ath/ath11k/hal_rx.c b/drivers/net/wireless/ath/ath11k/hal_rx.c
index fac2396edf32..b479d93bee32 100644
--- a/drivers/net/wireless/ath/ath11k/hal_rx.c
+++ b/drivers/net/wireless/ath/ath11k/hal_rx.c
@@ -801,42 +801,6 @@ void ath11k_hal_reo_init_cmd_ring(struct ath11k_base *ab,
 	}
 }
 
-void ath11k_hal_reo_hw_setup(struct ath11k_base *ab, u32 ring_hash_map)
-{
-	u32 reo_base = HAL_SEQ_WCSS_UMAC_REO_REG;
-	u32 val;
-
-	val = ath11k_hif_read32(ab, reo_base + HAL_REO1_GEN_ENABLE);
-
-	val &= ~HAL_REO1_GEN_ENABLE_FRAG_DST_RING;
-	val |= FIELD_PREP(HAL_REO1_GEN_ENABLE_FRAG_DST_RING,
-			  HAL_SRNG_RING_ID_REO2SW1) |
-	       FIELD_PREP(HAL_REO1_GEN_ENABLE_AGING_LIST_ENABLE, 1) |
-	       FIELD_PREP(HAL_REO1_GEN_ENABLE_AGING_FLUSH_ENABLE, 1);
-	ath11k_hif_write32(ab, reo_base + HAL_REO1_GEN_ENABLE, val);
-
-	ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_0(ab),
-			   HAL_DEFAULT_REO_TIMEOUT_USEC);
-	ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_1(ab),
-			   HAL_DEFAULT_REO_TIMEOUT_USEC);
-	ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_2(ab),
-			   HAL_DEFAULT_REO_TIMEOUT_USEC);
-	ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_3(ab),
-			   HAL_DEFAULT_REO_TIMEOUT_USEC);
-
-	ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_0,
-			   FIELD_PREP(HAL_REO_DEST_RING_CTRL_HASH_RING_MAP,
-				      ring_hash_map));
-	ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_1,
-			   FIELD_PREP(HAL_REO_DEST_RING_CTRL_HASH_RING_MAP,
-				      ring_hash_map));
-	ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_2,
-			   FIELD_PREP(HAL_REO_DEST_RING_CTRL_HASH_RING_MAP,
-				      ring_hash_map));
-	ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_3,
-			   FIELD_PREP(HAL_REO_DEST_RING_CTRL_HASH_RING_MAP,
-				      ring_hash_map));
-}
 
 static enum hal_rx_mon_status
 ath11k_hal_rx_parse_mon_status_tlv(struct ath11k_base *ab,
diff --git a/drivers/net/wireless/ath/ath11k/hw.c b/drivers/net/wireless/ath/ath11k/hw.c
index 023047df954c..01207b50a454 100644
--- a/drivers/net/wireless/ath/ath11k/hw.c
+++ b/drivers/net/wireless/ath/ath11k/hw.c
@@ -10,6 +10,7 @@
 #include "hw.h"
 #include "core.h"
 #include "ce.h"
+#include "hif.h"
 
 /* Map from pdev index to hw mac index */
 static u8 ath11k_hw_ipq8074_mac_from_pdev_id(int pdev_idx)
@@ -98,6 +99,52 @@ static void ath11k_init_wmi_config_qca6390(struct ath11k_base *ab,
 	config->num_keep_alive_pattern = 0;
 }
 
+static void ath11k_hw_ipq8074_reo_setup(struct ath11k_base *ab)
+{
+	u32 reo_base = HAL_SEQ_WCSS_UMAC_REO_REG;
+	u32 val;
+	/* Each hash entry uses three bits to map to a particular ring. */
+	u32 ring_hash_map = HAL_HASH_ROUTING_RING_SW1 << 0 |
+		HAL_HASH_ROUTING_RING_SW2 << 3 |
+		HAL_HASH_ROUTING_RING_SW3 << 6 |
+		HAL_HASH_ROUTING_RING_SW4 << 9 |
+		HAL_HASH_ROUTING_RING_SW1 << 12 |
+		HAL_HASH_ROUTING_RING_SW2 << 15 |
+		HAL_HASH_ROUTING_RING_SW3 << 18 |
+		HAL_HASH_ROUTING_RING_SW4 << 21;
+
+	val = ath11k_hif_read32(ab, reo_base + HAL_REO1_GEN_ENABLE);
+
+	val &= ~HAL_REO1_GEN_ENABLE_FRAG_DST_RING;
+	val |= FIELD_PREP(HAL_REO1_GEN_ENABLE_FRAG_DST_RING,
+			HAL_SRNG_RING_ID_REO2SW1) |
+		FIELD_PREP(HAL_REO1_GEN_ENABLE_AGING_LIST_ENABLE, 1) |
+		FIELD_PREP(HAL_REO1_GEN_ENABLE_AGING_FLUSH_ENABLE, 1);
+	ath11k_hif_write32(ab, reo_base + HAL_REO1_GEN_ENABLE, val);
+
+	ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_0(ab),
+			   HAL_DEFAULT_REO_TIMEOUT_USEC);
+	ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_1(ab),
+			   HAL_DEFAULT_REO_TIMEOUT_USEC);
+	ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_2(ab),
+			   HAL_DEFAULT_REO_TIMEOUT_USEC);
+	ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_3(ab),
+			   HAL_DEFAULT_REO_TIMEOUT_USEC);
+
+	ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_0,
+			   FIELD_PREP(HAL_REO_DEST_RING_CTRL_HASH_RING_MAP,
+				      ring_hash_map));
+	ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_1,
+			   FIELD_PREP(HAL_REO_DEST_RING_CTRL_HASH_RING_MAP,
+				      ring_hash_map));
+	ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_2,
+			   FIELD_PREP(HAL_REO_DEST_RING_CTRL_HASH_RING_MAP,
+				      ring_hash_map));
+	ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_3,
+			   FIELD_PREP(HAL_REO_DEST_RING_CTRL_HASH_RING_MAP,
+				      ring_hash_map));
+}
+
 static void ath11k_init_wmi_config_ipq8074(struct ath11k_base *ab,
 					   struct target_resource_config *config)
 {
@@ -656,6 +703,45 @@ static u8 *ath11k_hw_wcn6855_rx_desc_get_msdu_payload(struct hal_rx_desc *desc)
 	return &desc->u.wcn6855.msdu_payload[0];
 }
 
+static void ath11k_hw_wcn6855_reo_setup(struct ath11k_base *ab)
+{
+	u32 reo_base = HAL_SEQ_WCSS_UMAC_REO_REG;
+	u32 val;
+	/* Each hash entry uses four bits to map to a particular ring. */
+	u32 ring_hash_map = HAL_HASH_ROUTING_RING_SW1 << 0 |
+		HAL_HASH_ROUTING_RING_SW2 << 4 |
+		HAL_HASH_ROUTING_RING_SW3 << 8 |
+		HAL_HASH_ROUTING_RING_SW4 << 12 |
+		HAL_HASH_ROUTING_RING_SW1 << 16 |
+		HAL_HASH_ROUTING_RING_SW2 << 20 |
+		HAL_HASH_ROUTING_RING_SW3 << 24 |
+		HAL_HASH_ROUTING_RING_SW4 << 28;
+
+	val = ath11k_hif_read32(ab, reo_base + HAL_REO1_GEN_ENABLE);
+	val |= FIELD_PREP(HAL_REO1_GEN_ENABLE_AGING_LIST_ENABLE, 1) |
+		FIELD_PREP(HAL_REO1_GEN_ENABLE_AGING_FLUSH_ENABLE, 1);
+	ath11k_hif_write32(ab, reo_base + HAL_REO1_GEN_ENABLE, val);
+
+	val = ath11k_hif_read32(ab, reo_base + HAL_REO1_MISC_CTL);
+	val &= ~HAL_REO1_MISC_CTL_FRAGMENT_DST_RING;
+	val |= FIELD_PREP(HAL_REO1_MISC_CTL_FRAGMENT_DST_RING, HAL_SRNG_RING_ID_REO2SW1);
+	ath11k_hif_write32(ab, reo_base + HAL_REO1_MISC_CTL, val);
+
+	ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_0(ab),
+			   HAL_DEFAULT_REO_TIMEOUT_USEC);
+	ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_1(ab),
+			   HAL_DEFAULT_REO_TIMEOUT_USEC);
+	ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_2(ab),
+			   HAL_DEFAULT_REO_TIMEOUT_USEC);
+	ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_3(ab),
+			   HAL_DEFAULT_REO_TIMEOUT_USEC);
+
+	ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_2,
+			   ring_hash_map);
+	ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_3,
+			   ring_hash_map);
+}
+
 const struct ath11k_hw_ops ipq8074_ops = {
 	.get_hw_mac_from_pdev_id = ath11k_hw_ipq8074_mac_from_pdev_id,
 	.wmi_init_config = ath11k_init_wmi_config_ipq8074,
@@ -688,6 +774,7 @@ const struct ath11k_hw_ops ipq8074_ops = {
 	.rx_desc_set_msdu_len = ath11k_hw_ipq8074_rx_desc_set_msdu_len,
 	.rx_desc_get_attention = ath11k_hw_ipq8074_rx_desc_get_attention,
 	.rx_desc_get_msdu_payload = ath11k_hw_ipq8074_rx_desc_get_msdu_payload,
+	.reo_setup = ath11k_hw_ipq8074_reo_setup,
 };
 
 const struct ath11k_hw_ops ipq6018_ops = {
@@ -722,6 +809,7 @@ const struct ath11k_hw_ops ipq6018_ops = {
 	.rx_desc_set_msdu_len = ath11k_hw_ipq8074_rx_desc_set_msdu_len,
 	.rx_desc_get_attention = ath11k_hw_ipq8074_rx_desc_get_attention,
 	.rx_desc_get_msdu_payload = ath11k_hw_ipq8074_rx_desc_get_msdu_payload,
+	.reo_setup = ath11k_hw_ipq8074_reo_setup,
 };
 
 const struct ath11k_hw_ops qca6390_ops = {
@@ -756,6 +844,7 @@ const struct ath11k_hw_ops qca6390_ops = {
 	.rx_desc_set_msdu_len = ath11k_hw_ipq8074_rx_desc_set_msdu_len,
 	.rx_desc_get_attention = ath11k_hw_ipq8074_rx_desc_get_attention,
 	.rx_desc_get_msdu_payload = ath11k_hw_ipq8074_rx_desc_get_msdu_payload,
+	.reo_setup = ath11k_hw_ipq8074_reo_setup,
 };
 
 const struct ath11k_hw_ops qcn9074_ops = {
@@ -790,6 +879,7 @@ const struct ath11k_hw_ops qcn9074_ops = {
 	.rx_desc_set_msdu_len = ath11k_hw_qcn9074_rx_desc_set_msdu_len,
 	.rx_desc_get_attention = ath11k_hw_qcn9074_rx_desc_get_attention,
 	.rx_desc_get_msdu_payload = ath11k_hw_qcn9074_rx_desc_get_msdu_payload,
+	.reo_setup = ath11k_hw_ipq8074_reo_setup,
 };
 
 const struct ath11k_hw_ops wcn6855_ops = {
@@ -824,6 +914,7 @@ const struct ath11k_hw_ops wcn6855_ops = {
 	.rx_desc_set_msdu_len = ath11k_hw_wcn6855_rx_desc_set_msdu_len,
 	.rx_desc_get_attention = ath11k_hw_wcn6855_rx_desc_get_attention,
 	.rx_desc_get_msdu_payload = ath11k_hw_wcn6855_rx_desc_get_msdu_payload,
+	.reo_setup = ath11k_hw_wcn6855_reo_setup,
 };
 
 #define ATH11K_TX_RING_MASK_0 0x1
diff --git a/drivers/net/wireless/ath/ath11k/hw.h b/drivers/net/wireless/ath/ath11k/hw.h
index 6e924f628f22..afe3b3c71695 100644
--- a/drivers/net/wireless/ath/ath11k/hw.h
+++ b/drivers/net/wireless/ath/ath11k/hw.h
@@ -199,6 +199,7 @@ struct ath11k_hw_ops {
 	void (*rx_desc_set_msdu_len)(struct hal_rx_desc *desc, u16 len);
 	struct rx_attention *(*rx_desc_get_attention)(struct hal_rx_desc *desc);
 	u8 *(*rx_desc_get_msdu_payload)(struct hal_rx_desc *desc);
+	void (*reo_setup)(struct ath11k_base *ab);
 };
 
 extern const struct ath11k_hw_ops ipq8074_ops;
-- 
2.25.1



From kernel at gecius.de  Tue May 11 14:02:52 2021
From: kernel at gecius.de (Jens Gecius)
Date: Tue, 11 May 2021 15:02:52 +0200
Subject: qca/hci issues with Bluetooth on Dell XPS 13/AX500 (9310)
Message-ID: <d078b4bb-0cd5-ee9f-5d5d-6a95b3fe2ed9@gecius.de>

Dear all,

there was an earlier (March 30 "issues with QCA6390 on Dell XPS 13") 
report of the same/similar problem (just realized today).

As that reporter, I have a Dell XPS 13 dev edition/Ubuntu (working). My 
9310 has the AX500 Killer Wifi. Wifi is working fine, but Bluetooth 
always gives me a crash (I blacklisted BT required modules to later 
trigger the oops myself or run without). The crash renders the 
suspend/resume capabilities inoperable, the hci_uart module is not 
removeable.

I tried to get differences of the Dell supplied Ubuntu-OEM 5.6 kernel to 
current mainline, but my grey matter is unable to digest that 
information and supply helpful hints.
/lib/firmware-files were the same on Ubuntu and Fedora (it recently got 
updated on my Fedora 34 - crash unchanged).

Full dmesg output of module loading attached.

Intentionally, I did a suspend-resume cycle first for your kind 
information and then loaded the BT modules. The crash also occurs if I 
load the hci_uart directly after system startup.

That is unchanged since receiving the notebook in April, even with 
earlier firmware version. I am on the latest Fedora kernel, now 
5.11.18-300.fc34.x86_64. BIOS is latest 2.2.0.

The trace says, that qca_read_soc_version is causing the crash during 
qca_uart_setup in btqca. Is that correct?

And - maybe I'm on the wrong list here (BT / ath11k) anyway, please let 
me know if so. :-)

If I can support, please let me know. Thank you very much.

Best
 ?Jens

-------------- next part --------------
[    0.000000] Linux version 5.11.18-300.fc34.x86_64 (mockbuild at bkernel01.iad2.fedoraproject.org) (gcc (GCC) 11.1.1 20210428 (Red Hat 11.1.1-1), GNU ld version 2.35.1-41.fc34) #1 SMP Mon May 3 15:10:32 UTC 2021
[    0.000000] Command line: BOOT_IMAGE=(hd0,gpt4)/boot/vmlinuz-5.11.18-300.fc34.x86_64 root=UUID=ab42b613-710e-41e0-be16-15407806f5df ro rhgb quiet
[    0.000000] x86/split lock detection: warning about user-space split_locks
[    0.000000] x86/fpu: Supporting XSAVE feature 0x001: 'x87 floating point registers'
[    0.000000] x86/fpu: Supporting XSAVE feature 0x002: 'SSE registers'
[    0.000000] x86/fpu: Supporting XSAVE feature 0x004: 'AVX registers'
[    0.000000] x86/fpu: Supporting XSAVE feature 0x020: 'AVX-512 opmask'
[    0.000000] x86/fpu: Supporting XSAVE feature 0x040: 'AVX-512 Hi256'
[    0.000000] x86/fpu: Supporting XSAVE feature 0x080: 'AVX-512 ZMM_Hi256'
[    0.000000] x86/fpu: Supporting XSAVE feature 0x200: 'Protection Keys User registers'
[    0.000000] x86/fpu: xstate_offset[2]:  576, xstate_sizes[2]:  256
[    0.000000] x86/fpu: xstate_offset[5]:  832, xstate_sizes[5]:   64
[    0.000000] x86/fpu: xstate_offset[6]:  896, xstate_sizes[6]:  512
[    0.000000] x86/fpu: xstate_offset[7]: 1408, xstate_sizes[7]: 1024
[    0.000000] x86/fpu: xstate_offset[9]: 2432, xstate_sizes[9]:    8
[    0.000000] x86/fpu: Enabled xstate features 0x2e7, context size is 2440 bytes, using 'compacted' format.
[    0.000000] BIOS-provided physical RAM map:
[    0.000000] BIOS-e820: [mem 0x0000000000000000-0x000000000009efff] usable
[    0.000000] BIOS-e820: [mem 0x000000000009f000-0x00000000000fffff] reserved
[    0.000000] BIOS-e820: [mem 0x0000000000100000-0x000000005e72afff] usable
[    0.000000] BIOS-e820: [mem 0x000000005e72b000-0x0000000062510fff] reserved
[    0.000000] BIOS-e820: [mem 0x0000000062511000-0x0000000062d71fff] ACPI NVS
[    0.000000] BIOS-e820: [mem 0x0000000062d72000-0x0000000062ffefff] ACPI data
[    0.000000] BIOS-e820: [mem 0x0000000062fff000-0x0000000062ffffff] usable
[    0.000000] BIOS-e820: [mem 0x0000000063000000-0x0000000066ffffff] reserved
[    0.000000] BIOS-e820: [mem 0x0000000067600000-0x00000000677fffff] reserved
[    0.000000] BIOS-e820: [mem 0x0000000068000000-0x00000000707fffff] reserved
[    0.000000] BIOS-e820: [mem 0x00000000c0000000-0x00000000cfffffff] reserved
[    0.000000] BIOS-e820: [mem 0x00000000fed20000-0x00000000fed7ffff] reserved
[    0.000000] BIOS-e820: [mem 0x00000000ff000000-0x00000000ffffffff] reserved
[    0.000000] BIOS-e820: [mem 0x0000000100000000-0x000000088f7fffff] usable
[    0.000000] NX (Execute Disable) protection: active
[    0.000000] efi: EFI v2.70 by Dell
[    0.000000] efi: ACPI=0x62ffe000 ACPI 2.0=0x62ffe014 SMBIOS=0x5edd7000 TPMFinalLog=0x62cd8000 ESRT=0x5eccc298 MEMATTR=0x59d4f018 MOKvar=0x59d58000 RNG=0x5ed11f18 TPMEventLog=0x59d47018 
[    0.000000] efi: seeding entropy pool
[    0.000000] secureboot: Secure boot disabled
[    0.000000] SMBIOS 3.2 present.
[    0.000000] DMI: Dell Inc. XPS 13 9310/0MRT12, BIOS 2.2.0 04/06/2021
[    0.000000] tsc: Detected 3000.000 MHz processor
[    0.000000] tsc: Detected 2995.200 MHz TSC
[    0.000005] e820: update [mem 0x00000000-0x00000fff] usable ==> reserved
[    0.000007] e820: remove [mem 0x000a0000-0x000fffff] usable
[    0.000010] last_pfn = 0x88f800 max_arch_pfn = 0x400000000
[    0.000012] MTRR default type: write-back
[    0.000013] MTRR fixed ranges enabled:
[    0.000014]   00000-9FFFF write-back
[    0.000015]   A0000-BFFFF uncachable
[    0.000015]   C0000-FFFFF write-protect
[    0.000016] MTRR variable ranges enabled:
[    0.000016]   0 base 0080000000 mask 7F80000000 uncachable
[    0.000018]   1 base 0070000000 mask 7FF0000000 uncachable
[    0.000018]   2 base 006C000000 mask 7FFC000000 uncachable
[    0.000019]   3 base 2000000000 mask 6000000000 uncachable
[    0.000020]   4 base 1000000000 mask 7000000000 uncachable
[    0.000020]   5 base 4000000000 mask 4000000000 uncachable
[    0.000021]   6 disabled
[    0.000021]   7 disabled
[    0.000022]   8 disabled
[    0.000022]   9 disabled
[    0.000141] x86/PAT: Configuration [0-7]: WB  WC  UC- UC  WB  WP  UC- WT  
[    0.001007] last_pfn = 0x63000 max_arch_pfn = 0x400000000
[    0.007268] esrt: Reserving ESRT space from 0x000000005eccc298 to 0x000000005eccc320.
[    0.007273] e820: update [mem 0x59d58000-0x59d58fff] usable ==> reserved
[    0.007287] Using GB pages for direct mapping
[    0.007438] secureboot: Secure boot disabled
[    0.007439] RAMDISK: [mem 0x529aa000-0x546bbfff]
[    0.007441] ACPI: Early table checksum verification disabled
[    0.007443] ACPI: RSDP 0x0000000062FFE014 000024 (v02 DELL  )
[    0.007446] ACPI: XSDT 0x0000000062F78188 0000FC (v01 DELL   Dell Inc 00000002      01000013)
[    0.007451] ACPI: FACP 0x0000000062FF5000 000114 (v06 DELL   Dell Inc 00000002      01000013)
[    0.007454] ACPI: DSDT 0x0000000062F97000 05A2BC (v02 DELL   Dell Inc 00000002      01000013)
[    0.007456] ACPI: FACS 0x0000000062D1B000 000040
[    0.007458] ACPI: SSDT 0x0000000062FFA000 0024D0 (v02 CpuRef CpuSsdt  00003000 INTL 20191018)
[    0.007460] ACPI: SSDT 0x0000000062FF6000 0038FA (v02 DptfTb DptfTabl 00001000 INTL 20191018)
[    0.007462] ACPI: HPET 0x0000000062FF4000 000038 (v01 DELL   Dell Inc 00000002      01000013)
[    0.007464] ACPI: APIC 0x0000000062FF3000 00012C (v04 DELL   Dell Inc 00000002      01000013)
[    0.007465] ACPI: MCFG 0x0000000062FF2000 00003C (v01 DELL   Dell Inc 00000002      01000013)
[    0.007467] ACPI: SSDT 0x0000000062F96000 000D01 (v02 DELL   DellRtd3 00001000 INTL 20191018)
[    0.007469] ACPI: NHLT 0x0000000062F94000 001B54 (v00 DELL   Dell Inc 00000002      01000013)
[    0.007471] ACPI: SSDT 0x0000000062F91000 002CCD (v02 SaSsdt SaSsdt   00003000 INTL 20191018)
[    0.007473] ACPI: SSDT 0x0000000062F8F000 0012AA (v02 INTEL  IgfxSsdt 00003000 INTL 20191018)
[    0.007475] ACPI: SSDT 0x0000000062F83000 00B192 (v02 INTEL  TcssSsdt 00001000 INTL 20191018)
[    0.007476] ACPI: SSDT 0x0000000062F82000 000CD2 (v02 DELL   UsbCTabl 00001000 INTL 20191018)
[    0.007478] ACPI: LPIT 0x0000000062F81000 0000CC (v01 DELL   Dell Inc 00000002      01000013)
[    0.007480] ACPI: SSDT 0x0000000062F80000 000B75 (v02 DELL   PtidDevc 00001000 INTL 20191018)
[    0.007482] ACPI: SSDT 0x0000000062F7F000 00012A (v02 DELL   TbtTypeC 00000000 INTL 20191018)
[    0.007484] ACPI: DBGP 0x0000000062F7E000 000034 (v01 DELL   Dell Inc 00000002      01000013)
[    0.007485] ACPI: DBG2 0x0000000062F7D000 000054 (v00 DELL   Dell Inc 00000002      01000013)
[    0.007487] ACPI: SLIC 0x0000000062F7C000 000176 (v03 DELL   CBX3     06222004 MSFT 00010013)
[    0.007489] ACPI: BOOT 0x0000000062F7B000 000028 (v01 DELL   CBX3     00000002      01000013)
[    0.007491] ACPI: SSDT 0x0000000062F7A000 00060E (v02 DELL   Tpm2Tabl 00001000 INTL 20191018)
[    0.007493] ACPI: TPM2 0x0000000062F79000 00004C (v04 DELL   Dell Inc 00000002      01000013)
[    0.007495] ACPI: DMAR 0x0000000062FFD000 0000B8 (v02 INTEL  Dell Inc 00000002      01000013)
[    0.007496] ACPI: SSDT 0x0000000062F77000 000841 (v02 DELL   xh_Dell_ 00000000 INTL 20191018)
[    0.007498] ACPI: SSDT 0x0000000062F76000 000144 (v02 Intel  ADebTabl 00001000 INTL 20191018)
[    0.007500] ACPI: PTDT 0x0000000062F75000 000D44 (v00 DELL   Dell Inc 00000005 MSFT 0100000D)
[    0.007502] ACPI: BGRT 0x0000000062F74000 000038 (v01 DELL   Dell Inc 00000002      01000013)
[    0.007504] ACPI: FPDT 0x0000000062F73000 000034 (v01 DELL   Dell Inc 00000002      01000013)
[    0.007505] ACPI: Reserving FACP table memory at [mem 0x62ff5000-0x62ff5113]
[    0.007506] ACPI: Reserving DSDT table memory at [mem 0x62f97000-0x62ff12bb]
[    0.007507] ACPI: Reserving FACS table memory at [mem 0x62d1b000-0x62d1b03f]
[    0.007507] ACPI: Reserving SSDT table memory at [mem 0x62ffa000-0x62ffc4cf]
[    0.007508] ACPI: Reserving SSDT table memory at [mem 0x62ff6000-0x62ff98f9]
[    0.007508] ACPI: Reserving HPET table memory at [mem 0x62ff4000-0x62ff4037]
[    0.007509] ACPI: Reserving APIC table memory at [mem 0x62ff3000-0x62ff312b]
[    0.007509] ACPI: Reserving MCFG table memory at [mem 0x62ff2000-0x62ff203b]
[    0.007510] ACPI: Reserving SSDT table memory at [mem 0x62f96000-0x62f96d00]
[    0.007511] ACPI: Reserving NHLT table memory at [mem 0x62f94000-0x62f95b53]
[    0.007511] ACPI: Reserving SSDT table memory at [mem 0x62f91000-0x62f93ccc]
[    0.007512] ACPI: Reserving SSDT table memory at [mem 0x62f8f000-0x62f902a9]
[    0.007512] ACPI: Reserving SSDT table memory at [mem 0x62f83000-0x62f8e191]
[    0.007513] ACPI: Reserving SSDT table memory at [mem 0x62f82000-0x62f82cd1]
[    0.007513] ACPI: Reserving LPIT table memory at [mem 0x62f81000-0x62f810cb]
[    0.007514] ACPI: Reserving SSDT table memory at [mem 0x62f80000-0x62f80b74]
[    0.007514] ACPI: Reserving SSDT table memory at [mem 0x62f7f000-0x62f7f129]
[    0.007515] ACPI: Reserving DBGP table memory at [mem 0x62f7e000-0x62f7e033]
[    0.007515] ACPI: Reserving DBG2 table memory at [mem 0x62f7d000-0x62f7d053]
[    0.007516] ACPI: Reserving SLIC table memory at [mem 0x62f7c000-0x62f7c175]
[    0.007516] ACPI: Reserving BOOT table memory at [mem 0x62f7b000-0x62f7b027]
[    0.007517] ACPI: Reserving SSDT table memory at [mem 0x62f7a000-0x62f7a60d]
[    0.007518] ACPI: Reserving TPM2 table memory at [mem 0x62f79000-0x62f7904b]
[    0.007518] ACPI: Reserving DMAR table memory at [mem 0x62ffd000-0x62ffd0b7]
[    0.007519] ACPI: Reserving SSDT table memory at [mem 0x62f77000-0x62f77840]
[    0.007519] ACPI: Reserving SSDT table memory at [mem 0x62f76000-0x62f76143]
[    0.007520] ACPI: Reserving PTDT table memory at [mem 0x62f75000-0x62f75d43]
[    0.007521] ACPI: Reserving BGRT table memory at [mem 0x62f74000-0x62f74037]
[    0.007521] ACPI: Reserving FPDT table memory at [mem 0x62f73000-0x62f73033]
[    0.007537] ACPI: Local APIC address 0xfee00000
[    0.007792] No NUMA configuration found
[    0.007792] Faking a node at [mem 0x0000000000000000-0x000000088f7fffff]
[    0.007798] NODE_DATA(0) allocated [mem 0x88f7d5000-0x88f7fffff]
[    0.048271] Zone ranges:
[    0.048272]   DMA      [mem 0x0000000000001000-0x0000000000ffffff]
[    0.048273]   DMA32    [mem 0x0000000001000000-0x00000000ffffffff]
[    0.048274]   Normal   [mem 0x0000000100000000-0x000000088f7fffff]
[    0.048275]   Device   empty
[    0.048276] Movable zone start for each node
[    0.048277] Early memory node ranges
[    0.048277]   node   0: [mem 0x0000000000001000-0x000000000009efff]
[    0.048278]   node   0: [mem 0x0000000000100000-0x000000005e72afff]
[    0.048279]   node   0: [mem 0x0000000062fff000-0x0000000062ffffff]
[    0.048280]   node   0: [mem 0x0000000100000000-0x000000088f7fffff]
[    0.048282] Initmem setup node 0 [mem 0x0000000000001000-0x000000088f7fffff]
[    0.048283] On node 0 totalpages: 8314570
[    0.048284]   DMA zone: 64 pages used for memmap
[    0.048284]   DMA zone: 24 pages reserved
[    0.048285]   DMA zone: 3998 pages, LIFO batch:0
[    0.048494]   DMA zone: 28770 pages in unavailable ranges
[    0.048495]   DMA32 zone: 5981 pages used for memmap
[    0.048496]   DMA32 zone: 382764 pages, LIFO batch:63
[    0.050573]   DMA32 zone: 39124 pages in unavailable ranges
[    0.050574]   Normal zone: 123872 pages used for memmap
[    0.050575]   Normal zone: 7927808 pages, LIFO batch:63
[    0.089745]   Normal zone: 2048 pages in unavailable ranges
[    0.089766] Reserving Intel graphics memory at [mem 0x6c800000-0x707fffff]
[    0.090504] ACPI: PM-Timer IO Port: 0x1808
[    0.090505] ACPI: Local APIC address 0xfee00000
[    0.090511] ACPI: LAPIC_NMI (acpi_id[0x01] high edge lint[0x1])
[    0.090512] ACPI: LAPIC_NMI (acpi_id[0x02] high edge lint[0x1])
[    0.090512] ACPI: LAPIC_NMI (acpi_id[0x03] high edge lint[0x1])
[    0.090513] ACPI: LAPIC_NMI (acpi_id[0x04] high edge lint[0x1])
[    0.090513] ACPI: LAPIC_NMI (acpi_id[0x05] high edge lint[0x1])
[    0.090513] ACPI: LAPIC_NMI (acpi_id[0x06] high edge lint[0x1])
[    0.090514] ACPI: LAPIC_NMI (acpi_id[0x07] high edge lint[0x1])
[    0.090514] ACPI: LAPIC_NMI (acpi_id[0x08] high edge lint[0x1])
[    0.090515] ACPI: LAPIC_NMI (acpi_id[0x09] high edge lint[0x1])
[    0.090515] ACPI: LAPIC_NMI (acpi_id[0x0a] high edge lint[0x1])
[    0.090516] ACPI: LAPIC_NMI (acpi_id[0x0b] high edge lint[0x1])
[    0.090516] ACPI: LAPIC_NMI (acpi_id[0x0c] high edge lint[0x1])
[    0.090516] ACPI: LAPIC_NMI (acpi_id[0x0d] high edge lint[0x1])
[    0.090517] ACPI: LAPIC_NMI (acpi_id[0x0e] high edge lint[0x1])
[    0.090517] ACPI: LAPIC_NMI (acpi_id[0x0f] high edge lint[0x1])
[    0.090518] ACPI: LAPIC_NMI (acpi_id[0x10] high edge lint[0x1])
[    0.090552] IOAPIC[0]: apic_id 2, version 32, address 0xfec00000, GSI 0-119
[    0.090554] ACPI: INT_SRC_OVR (bus 0 bus_irq 0 global_irq 2 dfl dfl)
[    0.090555] ACPI: INT_SRC_OVR (bus 0 bus_irq 9 global_irq 9 high level)
[    0.090556] ACPI: IRQ0 used by override.
[    0.090557] ACPI: IRQ9 used by override.
[    0.090558] Using ACPI (MADT) for SMP configuration information
[    0.090559] ACPI: HPET id: 0x8086a201 base: 0xfed00000
[    0.090564] e820: update [mem 0x59d61000-0x59d7efff] usable ==> reserved
[    0.090569] TSC deadline timer available
[    0.090570] smpboot: Allowing 8 CPUs, 0 hotplug CPUs
[    0.090579] PM: hibernation: Registered nosave memory: [mem 0x00000000-0x00000fff]
[    0.090581] PM: hibernation: Registered nosave memory: [mem 0x0009f000-0x000fffff]
[    0.090582] PM: hibernation: Registered nosave memory: [mem 0x59d58000-0x59d58fff]
[    0.090583] PM: hibernation: Registered nosave memory: [mem 0x59d61000-0x59d7efff]
[    0.090584] PM: hibernation: Registered nosave memory: [mem 0x5e72b000-0x62510fff]
[    0.090584] PM: hibernation: Registered nosave memory: [mem 0x62511000-0x62d71fff]
[    0.090585] PM: hibernation: Registered nosave memory: [mem 0x62d72000-0x62ffefff]
[    0.090585] PM: hibernation: Registered nosave memory: [mem 0x63000000-0x66ffffff]
[    0.090586] PM: hibernation: Registered nosave memory: [mem 0x67000000-0x675fffff]
[    0.090586] PM: hibernation: Registered nosave memory: [mem 0x67600000-0x677fffff]
[    0.090587] PM: hibernation: Registered nosave memory: [mem 0x67800000-0x67ffffff]
[    0.090587] PM: hibernation: Registered nosave memory: [mem 0x68000000-0x707fffff]
[    0.090587] PM: hibernation: Registered nosave memory: [mem 0x70800000-0xbfffffff]
[    0.090588] PM: hibernation: Registered nosave memory: [mem 0xc0000000-0xcfffffff]
[    0.090588] PM: hibernation: Registered nosave memory: [mem 0xd0000000-0xfed1ffff]
[    0.090589] PM: hibernation: Registered nosave memory: [mem 0xfed20000-0xfed7ffff]
[    0.090589] PM: hibernation: Registered nosave memory: [mem 0xfed80000-0xfeffffff]
[    0.090590] PM: hibernation: Registered nosave memory: [mem 0xff000000-0xffffffff]
[    0.090590] [mem 0x70800000-0xbfffffff] available for PCI devices
[    0.090591] Booting paravirtualized kernel on bare hardware
[    0.090593] clocksource: refined-jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 1910969940391419 ns
[    0.093780] setup_percpu: NR_CPUS:8192 nr_cpumask_bits:8 nr_cpu_ids:8 nr_node_ids:1
[    0.093888] percpu: Embedded 54 pages/cpu s184320 r8192 d28672 u262144
[    0.093892] pcpu-alloc: s184320 r8192 d28672 u262144 alloc=1*2097152
[    0.093893] pcpu-alloc: [0] 0 1 2 3 4 5 6 7 
[    0.093909] Built 1 zonelists, mobility grouping on.  Total pages: 8184629
[    0.093910] Policy zone: Normal
[    0.093911] Kernel command line: BOOT_IMAGE=(hd0,gpt4)/boot/vmlinuz-5.11.18-300.fc34.x86_64 root=UUID=ab42b613-710e-41e0-be16-15407806f5df ro rhgb quiet
[    0.094746] Dentry cache hash table entries: 4194304 (order: 13, 33554432 bytes, linear)
[    0.095149] Inode-cache hash table entries: 2097152 (order: 12, 16777216 bytes, linear)
[    0.095197] mem auto-init: stack:off, heap alloc:off, heap free:off
[    0.144541] Memory: 32435920K/33258280K available (14345K kernel code, 3471K rwdata, 9740K rodata, 2540K init, 5512K bss, 822100K reserved, 0K cma-reserved)
[    0.144544] random: get_random_u64 called from __kmem_cache_create+0x2e/0x560 with crng_init=0
[    0.144626] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
[    0.144635] ftrace: allocating 45648 entries in 179 pages
[    0.154495] ftrace: allocated 179 pages with 5 groups
[    0.154558] rcu: Hierarchical RCU implementation.
[    0.154559] rcu: 	RCU restricting CPUs from NR_CPUS=8192 to nr_cpu_ids=8.
[    0.154559] 	Trampoline variant of Tasks RCU enabled.
[    0.154560] 	Rude variant of Tasks RCU enabled.
[    0.154560] 	Tracing variant of Tasks RCU enabled.
[    0.154560] rcu: RCU calculated value of scheduler-enlistment delay is 100 jiffies.
[    0.154561] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
[    0.156440] NR_IRQS: 524544, nr_irqs: 2048, preallocated irqs: 16
[    0.156897] random: crng done (trusting CPU's manufacturer)
[    0.156916] Console: colour dummy device 80x25
[    0.156926] printk: console [tty0] enabled
[    0.156941] ACPI: Core revision 20201113
[    0.157258] clocksource: hpet: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 99544814920 ns
[    0.157367] APIC: Switch to symmetric I/O mode setup
[    0.157369] DMAR: Host address width 39
[    0.157370] DMAR: DRHD base: 0x000000fed90000 flags: 0x0
[    0.157373] DMAR: dmar0: reg_base_addr fed90000 ver 4:0 cap 1c0000c40660462 ecap 69e2ff0505e
[    0.157375] DMAR: DRHD base: 0x000000fed84000 flags: 0x0
[    0.157379] DMAR: dmar1: reg_base_addr fed84000 ver 1:0 cap d2008c40660462 ecap f050da
[    0.157381] DMAR: DRHD base: 0x000000fed86000 flags: 0x0
[    0.157384] DMAR: dmar2: reg_base_addr fed86000 ver 1:0 cap d2008c40660462 ecap f050da
[    0.157385] DMAR: DRHD base: 0x000000fed91000 flags: 0x1
[    0.157389] DMAR: dmar3: reg_base_addr fed91000 ver 1:0 cap d2008c40660462 ecap f050da
[    0.157390] DMAR: RMRR base: 0x0000006c000000 end: 0x000000707fffff
[    0.157393] DMAR-IR: IOAPIC id 2 under DRHD base  0xfed91000 IOMMU 3
[    0.157393] DMAR-IR: HPET id 0 under DRHD base 0xfed91000
[    0.157394] DMAR-IR: Queued invalidation will be enabled to support x2apic and Intr-remapping.
[    0.159678] DMAR-IR: Enabled IRQ remapping in x2apic mode
[    0.159680] x2apic enabled
[    0.159711] Switched APIC routing to cluster x2apic.
[    0.164573] ..TIMER: vector=0x30 apic1=0 pin1=2 apic2=-1 pin2=-1
[    0.169317] clocksource: tsc-early: mask: 0xffffffffffffffff max_cycles: 0x2b2c8ec87c7, max_idle_ns: 440795278598 ns
[    0.169322] Calibrating delay loop (skipped), value calculated using timer frequency.. 5990.40 BogoMIPS (lpj=2995200)
[    0.169324] pid_max: default: 32768 minimum: 301
[    0.171336] LSM: Security Framework initializing
[    0.171344] Yama: becoming mindful.
[    0.171349] SELinux:  Initializing.
[    0.171444] Mount-cache hash table entries: 65536 (order: 7, 524288 bytes, linear)
[    0.171503] Mountpoint-cache hash table entries: 65536 (order: 7, 524288 bytes, linear)
[    0.171703] x86/tme: enabled by BIOS
[    0.171703] x86/mktme: No known encryption algorithm is supported: 0x0
[    0.171704] x86/mktme: disabled by BIOS
[    0.171706] x86/cpu: User Mode Instruction Prevention (UMIP) activated
[    0.171737] mce: CPU0: Thermal monitoring enabled (TM1)
[    0.171807] process: using mwait in idle threads
[    0.171808] Last level iTLB entries: 4KB 0, 2MB 0, 4MB 0
[    0.171809] Last level dTLB entries: 4KB 0, 2MB 0, 4MB 0, 1GB 0
[    0.171812] Spectre V1 : Mitigation: usercopy/swapgs barriers and __user pointer sanitization
[    0.171814] Spectre V2 : Mitigation: Enhanced IBRS
[    0.171814] Spectre V2 : Spectre v2 / SpectreRSB mitigation: Filling RSB on context switch
[    0.171815] Spectre V2 : mitigation: Enabling conditional Indirect Branch Prediction Barrier
[    0.171816] Speculative Store Bypass: Mitigation: Speculative Store Bypass disabled via prctl and seccomp
[    0.172070] Freeing SMP alternatives memory: 44K
[    0.174388] smpboot: Estimated ratio of average max frequency by base frequency (times 1024): 1467
[    0.174409] smpboot: CPU0: 11th Gen Intel(R) Core(TM) i7-1185G7 @ 3.00GHz (family: 0x6, model: 0x8c, stepping: 0x1)
[    0.174522] Performance Events: PEBS fmt4+-baseline,  AnyThread deprecated, Icelake events, 32-deep LBR, full-width counters, Intel PMU driver.
[    0.174540] ... version:                5
[    0.174540] ... bit width:              48
[    0.174541] ... generic registers:      8
[    0.174541] ... value mask:             0000ffffffffffff
[    0.174542] ... max period:             00007fffffffffff
[    0.174543] ... fixed-purpose events:   4
[    0.174543] ... event mask:             0001000f000000ff
[    0.174612] rcu: Hierarchical SRCU implementation.
[    0.175149] NMI watchdog: Enabled. Permanently consumes one hw-PMU counter.
[    0.175206] smp: Bringing up secondary CPUs ...
[    0.175264] x86: Booting SMP configuration:
[    0.175264] .... node  #0, CPUs:      #1 #2 #3 #4 #5 #6 #7
[    0.182379] smp: Brought up 1 node, 8 CPUs
[    0.182379] smpboot: Max logical packages: 1
[    0.182379] smpboot: Total of 8 processors activated (47923.20 BogoMIPS)
[    0.184600] devtmpfs: initialized
[    0.184600] x86/mm: Memory block size: 128MB
[    0.185904] PM: Registering ACPI NVS region [mem 0x62511000-0x62d71fff] (8785920 bytes)
[    0.185904] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 1911260446275000 ns
[    0.185904] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
[    0.185904] pinctrl core: initialized pinctrl subsystem
[    0.186323] PM: RTC time: 12:17:04, date: 2021-05-11
[    0.186428] NET: Registered protocol family 16
[    0.186499] DMA: preallocated 4096 KiB GFP_KERNEL pool for atomic allocations
[    0.186507] DMA: preallocated 4096 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
[    0.186515] DMA: preallocated 4096 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
[    0.186524] thermal_sys: Registered thermal governor 'fair_share'
[    0.186524] thermal_sys: Registered thermal governor 'bang_bang'
[    0.186524] thermal_sys: Registered thermal governor 'step_wise'
[    0.186524] thermal_sys: Registered thermal governor 'user_space'
[    0.186524] cpuidle: using governor menu
[    0.186524] Simple Boot Flag at 0x47 set to 0x80
[    0.186524] ACPI: bus type PCI registered
[    0.186524] acpiphp: ACPI Hot Plug PCI Controller Driver version: 0.5
[    0.186524] PCI: MMCONFIG for domain 0000 [bus 00-ff] at [mem 0xc0000000-0xcfffffff] (base 0xc0000000)
[    0.186524] PCI: MMCONFIG at [mem 0xc0000000-0xcfffffff] reserved in E820
[    0.186524] PCI: Using configuration type 1 for base access
[    0.186794] ENERGY_PERF_BIAS: Set to 'normal', was 'performance'
[    0.188061] Kprobes globally optimized
[    0.188066] HugeTLB registered 1.00 GiB page size, pre-allocated 0 pages
[    0.188066] HugeTLB registered 2.00 MiB page size, pre-allocated 0 pages
[    0.281468] cryptd: max_cpu_qlen set to 1000
[    0.283327] alg: No test for 842 (842-generic)
[    0.283328] alg: No test for 842 (842-scomp)
[    0.284441] raid6: skip pq benchmark and using algorithm avx512x4
[    0.284441] raid6: using avx512x2 recovery algorithm
[    0.284441] ACPI: Added _OSI(Module Device)
[    0.284441] ACPI: Added _OSI(Processor Device)
[    0.284441] ACPI: Added _OSI(3.0 _SCP Extensions)
[    0.284441] ACPI: Added _OSI(Processor Aggregator Device)
[    0.284441] ACPI: Added _OSI(Linux-Dell-Video)
[    0.284441] ACPI: Added _OSI(Linux-Lenovo-NV-HDMI-Audio)
[    0.284441] ACPI: Added _OSI(Linux-HPI-Hybrid-Graphics)
[    0.334711] ACPI: 13 ACPI AML tables successfully acquired and loaded
[    0.347566] ACPI: Dynamic OEM Table Load:
[    0.347573] ACPI: SSDT 0xFFFF88A781521400 0001CB (v02 PmRef  Cpu0Psd  00003000 INTL 20191018)
[    0.348390] ACPI: \_SB_.PR00: _OSC native thermal LVT Acked
[    0.349909] ACPI: Dynamic OEM Table Load:
[    0.349914] ACPI: SSDT 0xFFFF88A78152BC00 000394 (v02 PmRef  Cpu0Cst  00003001 INTL 20191018)
[    0.350883] ACPI: Dynamic OEM Table Load:
[    0.350888] ACPI: SSDT 0xFFFF88A781D7C800 000689 (v02 PmRef  Cpu0Ist  00003000 INTL 20191018)
[    0.351867] ACPI: Dynamic OEM Table Load:
[    0.351870] ACPI: SSDT 0xFFFF88A781529400 000266 (v02 PmRef  Cpu0Hwp  00003000 INTL 20191018)
[    0.352872] ACPI: Dynamic OEM Table Load:
[    0.352877] ACPI: SSDT 0xFFFF88A781679000 0008E7 (v02 PmRef  ApIst    00003000 INTL 20191018)
[    0.353889] ACPI: Dynamic OEM Table Load:
[    0.353893] ACPI: SSDT 0xFFFF88A781D7E800 00048A (v02 PmRef  ApHwp    00003000 INTL 20191018)
[    0.354880] ACPI: Dynamic OEM Table Load:
[    0.354884] ACPI: SSDT 0xFFFF88A781D7F000 0004D4 (v02 PmRef  ApPsd    00003000 INTL 20191018)
[    0.355807] ACPI: Dynamic OEM Table Load:
[    0.355811] ACPI: SSDT 0xFFFF88A781D7F800 00048A (v02 PmRef  ApCst    00003000 INTL 20191018)
[    0.359756] ACPI: EC: EC started
[    0.359757] ACPI: EC: interrupt blocked
[    0.362044] ACPI: EC: EC_CMD/EC_SC=0x934, EC_DATA=0x930
[    0.362045] ACPI: \_SB_.PC00.LPCB.ECDV: Boot DSDT EC used to handle transactions
[    0.362046] ACPI: Interpreter enabled
[    0.362098] ACPI: (supports S0 S4 S5)
[    0.362099] ACPI: Using IOAPIC for interrupt routing
[    0.362136] PCI: Using host bridge windows from ACPI; if necessary, use "pci=nocrs" and report a bug
[    0.363493] ACPI: Enabled 8 GPEs in block 00 to 7F
[    0.369320] ACPI: Power Resource [WRST] (on)
[    0.369320] ACPI: Power Resource [DRST] (on)
[    0.373909] ACPI: Power Resource [V0PR] (on)
[    0.374002] ACPI: Power Resource [V1PR] (on)
[    0.374090] ACPI: Power Resource [V2PR] (on)
[    0.377274] ACPI: Power Resource [WRST] (on)
[    0.379641] ACPI: Power Resource [TBT0] (on)
[    0.379670] ACPI: Power Resource [TBT1] (on)
[    0.379696] ACPI: Power Resource [D3C] (on)
[    0.601320] ACPI: Power Resource [PIN] (off)
[    0.601320] ACPI: PCI Root Bridge [PC00] (domain 0000 [bus 00-fe])
[    0.601320] acpi PNP0A08:00: _OSC: OS supports [ExtendedConfig ASPM ClockPM Segments MSI EDR HPX-Type3]
[    0.603097] acpi PNP0A08:00: _OSC: platform does not support [AER]
[    0.605967] acpi PNP0A08:00: _OSC: OS now controls [PCIeHotplug SHPCHotplug PME PCIeCapability LTR DPC]
[    0.608602] PCI host bridge to bus 0000:00
[    0.608603] pci_bus 0000:00: root bus resource [io  0x0000-0x0cf7 window]
[    0.608605] pci_bus 0000:00: root bus resource [io  0x0d00-0xffff window]
[    0.608605] pci_bus 0000:00: root bus resource [mem 0x000a0000-0x000bffff window]
[    0.608606] pci_bus 0000:00: root bus resource [mem 0x70800000-0xbfffffff window]
[    0.608607] pci_bus 0000:00: root bus resource [mem 0x4000000000-0x7fffffffff window]
[    0.608608] pci_bus 0000:00: root bus resource [bus 00-fe]
[    0.608632] pci 0000:00:00.0: [8086:9a14] type 00 class 0x060000
[    0.609620] pci 0000:00:02.0: [8086:9a49] type 00 class 0x030000
[    0.609628] pci 0000:00:02.0: reg 0x10: [mem 0x6052000000-0x6052ffffff 64bit]
[    0.609633] pci 0000:00:02.0: reg 0x18: [mem 0x4000000000-0x400fffffff 64bit pref]
[    0.609636] pci 0000:00:02.0: reg 0x20: [io  0x3000-0x303f]
[    0.609650] pci 0000:00:02.0: BAR 2: assigned to efifb
[    0.609651] pci 0000:00:02.0: DMAR: Skip IOMMU disabling for graphics
[    0.609675] pci 0000:00:02.0: reg 0x344: [mem 0x00000000-0x00ffffff 64bit]
[    0.609676] pci 0000:00:02.0: VF(n) BAR0 space: [mem 0x00000000-0x06ffffff 64bit] (contains BAR0 for 7 VFs)
[    0.609680] pci 0000:00:02.0: reg 0x34c: [mem 0x00000000-0x1fffffff 64bit pref]
[    0.609681] pci 0000:00:02.0: VF(n) BAR2 space: [mem 0x00000000-0xdfffffff 64bit pref] (contains BAR2 for 7 VFs)
[    0.610482] pci 0000:00:04.0: [8086:9a03] type 00 class 0x118000
[    0.610497] pci 0000:00:04.0: reg 0x10: [mem 0x6053180000-0x605319ffff 64bit]
[    0.611413] pci 0000:00:06.0: [8086:9a09] type 01 class 0x060400
[    0.611491] pci 0000:00:06.0: PME# supported from D0 D3hot D3cold
[    0.611521] pci 0000:00:06.0: PTM enabled (root), 4ns granularity
[    0.612407] pci 0000:00:07.0: [8086:9a23] type 01 class 0x060400
[    0.613261] pci 0000:00:07.0: PME# supported from D0 D3hot D3cold
[    0.613282] pci 0000:00:07.0: DPC: RP PIO log size 0 is invalid
[    0.613467] pci 0000:00:07.2: [8086:9a27] type 01 class 0x060400
[    0.614359] pci 0000:00:07.2: PME# supported from D0 D3hot D3cold
[    0.614379] pci 0000:00:07.2: DPC: RP PIO log size 0 is invalid
[    0.614570] pci 0000:00:0a.0: [8086:9a0d] type 00 class 0x118000
[    0.614577] pci 0000:00:0a.0: reg 0x10: [mem 0x60531d0000-0x60531d7fff 64bit]
[    0.614597] pci 0000:00:0a.0: enabling Extended Tags
[    0.615398] pci 0000:00:0d.0: [8086:9a13] type 00 class 0x0c0330
[    0.615410] pci 0000:00:0d.0: reg 0x10: [mem 0x60531c0000-0x60531cffff 64bit]
[    0.615463] pci 0000:00:0d.0: PME# supported from D3hot D3cold
[    0.616350] pci 0000:00:0d.2: [8086:9a1b] type 00 class 0x0c0340
[    0.616361] pci 0000:00:0d.2: reg 0x10: [mem 0x6053140000-0x605317ffff 64bit]
[    0.616368] pci 0000:00:0d.2: reg 0x18: [mem 0x60531e9000-0x60531e9fff 64bit]
[    0.616404] pci 0000:00:0d.2: supports D1 D2
[    0.616404] pci 0000:00:0d.2: PME# supported from D0 D1 D2 D3hot D3cold
[    0.617270] pci 0000:00:0d.3: [8086:9a1d] type 00 class 0x0c0340
[    0.617281] pci 0000:00:0d.3: reg 0x10: [mem 0x6053100000-0x605313ffff 64bit]
[    0.617289] pci 0000:00:0d.3: reg 0x18: [mem 0x60531e8000-0x60531e8fff 64bit]
[    0.617325] pci 0000:00:0d.3: supports D1 D2
[    0.617325] pci 0000:00:0d.3: PME# supported from D0 D1 D2 D3hot D3cold
[    0.618152] pci 0000:00:12.0: [8086:a0fc] type 00 class 0x070000
[    0.618173] pci 0000:00:12.0: reg 0x10: [mem 0x60531b0000-0x60531bffff 64bit]
[    0.618244] pci 0000:00:12.0: PME# supported from D0 D3hot
[    0.619164] pci 0000:00:14.0: [8086:a0ed] type 00 class 0x0c0330
[    0.619185] pci 0000:00:14.0: reg 0x10: [mem 0x60531a0000-0x60531affff 64bit]
[    0.619273] pci 0000:00:14.0: PME# supported from D3hot D3cold
[    0.620220] pci 0000:00:14.2: [8086:a0ef] type 00 class 0x050000
[    0.620240] pci 0000:00:14.2: reg 0x10: [mem 0x60531dc000-0x60531dffff 64bit]
[    0.620253] pci 0000:00:14.2: reg 0x18: [mem 0x60531e7000-0x60531e7fff 64bit]
[    0.621224] pci 0000:00:15.0: [8086:a0e8] type 00 class 0x0c8000
[    0.621255] pci 0000:00:15.0: reg 0x10: [mem 0x00000000-0x00000fff 64bit]
[    0.622288] pci 0000:00:15.1: [8086:a0e9] type 00 class 0x0c8000
[    0.622315] pci 0000:00:15.1: reg 0x10: [mem 0x00000000-0x00000fff 64bit]
[    0.623376] pci 0000:00:16.0: [8086:a0e0] type 00 class 0x078000
[    0.623398] pci 0000:00:16.0: reg 0x10: [mem 0x60531e4000-0x60531e4fff 64bit]
[    0.623484] pci 0000:00:16.0: PME# supported from D3hot
[    0.624521] pci 0000:00:19.0: [8086:a0c5] type 00 class 0x0c8000
[    0.624551] pci 0000:00:19.0: reg 0x10: [mem 0x00000000-0x00000fff 64bit]
[    0.625522] pci 0000:00:19.1: [8086:a0c6] type 00 class 0x0c8000
[    0.625551] pci 0000:00:19.1: reg 0x10: [mem 0x00000000-0x00000fff 64bit]
[    0.626620] pci 0000:00:1c.0: [8086:a0b8] type 01 class 0x060400
[    0.626724] pci 0000:00:1c.0: PME# supported from D0 D3hot D3cold
[    0.626757] pci 0000:00:1c.0: PTM enabled (root), 4ns granularity
[    0.627735] pci 0000:00:1d.0: [8086:a0b3] type 01 class 0x060400
[    0.627834] pci 0000:00:1d.0: PME# supported from D0 D3hot D3cold
[    0.627871] pci 0000:00:1d.0: PTM enabled (root), 4ns granularity
[    0.628862] pci 0000:00:1e.0: [8086:a0a8] type 00 class 0x078000
[    0.628890] pci 0000:00:1e.0: reg 0x10: [mem 0x00000000-0x00000fff 64bit]
[    0.629966] pci 0000:00:1f.0: [8086:a082] type 00 class 0x060100
[    0.630983] pci 0000:00:1f.3: [8086:a0c8] type 00 class 0x040100
[    0.631025] pci 0000:00:1f.3: reg 0x10: [mem 0x60531d8000-0x60531dbfff 64bit]
[    0.631080] pci 0000:00:1f.3: reg 0x20: [mem 0x6053000000-0x60530fffff 64bit]
[    0.631187] pci 0000:00:1f.3: PME# supported from D3hot D3cold
[    0.632099] pci 0000:00:1f.4: [8086:a0a3] type 00 class 0x0c0500
[    0.632121] pci 0000:00:1f.4: reg 0x10: [mem 0x60531e0000-0x60531e00ff 64bit]
[    0.632144] pci 0000:00:1f.4: reg 0x20: [io  0xefa0-0xefbf]
[    0.633020] pci 0000:00:1f.5: [8086:a0a4] type 00 class 0x0c8000
[    0.633039] pci 0000:00:1f.5: reg 0x10: [mem 0xfe010000-0xfe010fff]
[    0.634242] pci 0000:01:00.0: [1179:011a] type 00 class 0x010802
[    0.634258] pci 0000:01:00.0: reg 0x10: [mem 0xa2600000-0xa2603fff 64bit]
[    0.634429] pci 0000:00:06.0: PCI bridge to [bus 01]
[    0.634432] pci 0000:00:06.0:   bridge window [mem 0xa2600000-0xa26fffff]
[    0.634463] pci 0000:00:07.0: PCI bridge to [bus 02-39]
[    0.634467] pci 0000:00:07.0:   bridge window [mem 0x8c000000-0xa23fffff]
[    0.634470] pci 0000:00:07.0:   bridge window [mem 0x6000000000-0x6021ffffff 64bit pref]
[    0.634503] pci 0000:00:07.2: PCI bridge to [bus 3a-71]
[    0.634506] pci 0000:00:07.2:   bridge window [mem 0x74000000-0x8a3fffff]
[    0.634510] pci 0000:00:07.2:   bridge window [mem 0x6030000000-0x6051ffffff 64bit pref]
[    0.634574] pci 0000:72:00.0: [17cb:1101] type 00 class 0x028000
[    0.634597] pci 0000:72:00.0: reg 0x10: [mem 0xa2500000-0xa25fffff 64bit]
[    0.634738] pci 0000:72:00.0: PME# supported from D0 D3hot D3cold
[    0.634813] pci 0000:72:00.0: 4.000 Gb/s available PCIe bandwidth, limited by 5.0 GT/s PCIe x1 link at 0000:00:1c.0 (capable of 7.876 Gb/s with 8.0 GT/s PCIe x1 link)
[    0.634903] pci 0000:00:1c.0: PCI bridge to [bus 72]
[    0.634908] pci 0000:00:1c.0:   bridge window [mem 0xa2500000-0xa25fffff]
[    0.634981] pci 0000:73:00.0: [10ec:5260] type 00 class 0xff0000
[    0.634999] pci 0000:73:00.0: reg 0x10: [mem 0xa2400000-0xa2400fff]
[    0.635138] pci 0000:73:00.0: supports D1 D2
[    0.635139] pci 0000:73:00.0: PME# supported from D1 D2 D3hot D3cold
[    0.635280] pci 0000:00:1d.0: PCI bridge to [bus 73]
[    0.635285] pci 0000:00:1d.0:   bridge window [mem 0xa2400000-0xa24fffff]
[    0.660840] ACPI: EC: interrupt unblocked
[    0.660841] ACPI: EC: event unblocked
[    0.660850] ACPI: EC: EC_CMD/EC_SC=0x934, EC_DATA=0x930
[    0.660850] ACPI: EC: GPE=0x6e
[    0.660851] ACPI: \_SB_.PC00.LPCB.ECDV: Boot DSDT EC initialization complete
[    0.660853] ACPI: \_SB_.PC00.LPCB.ECDV: EC: Used to handle transactions and events
[    0.661333] iommu: Default domain type: Translated 
[    0.661356] pci 0000:00:02.0: vgaarb: setting as boot VGA device
[    0.661356] pci 0000:00:02.0: vgaarb: VGA device added: decodes=io+mem,owns=io+mem,locks=none
[    0.661356] pci 0000:00:02.0: vgaarb: bridge control possible
[    0.661356] vgaarb: loaded
[    0.661392] SCSI subsystem initialized
[    0.661397] libata version 3.00 loaded.
[    0.661397] ACPI: bus type USB registered
[    0.661397] usbcore: registered new interface driver usbfs
[    0.661397] usbcore: registered new interface driver hub
[    0.661397] usbcore: registered new device driver usb
[    0.661397] pps_core: LinuxPPS API ver. 1 registered
[    0.661397] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti at linux.it>
[    0.661397] PTP clock support registered
[    0.661399] EDAC MC: Ver: 3.0.0
[    0.661468] Registered efivars operations
[    0.661468] NetLabel: Initializing
[    0.661468] NetLabel:  domain hash size = 128
[    0.661468] NetLabel:  protocols = UNLABELED CIPSOv4 CALIPSO
[    0.661469] NetLabel:  unlabeled traffic allowed by default
[    0.661472] PCI: Using ACPI for IRQ routing
[    0.677507] PCI: pci_cache_line_size set to 64 bytes
[    0.677681] pci 0000:00:1f.5: can't claim BAR 0 [mem 0xfe010000-0xfe010fff]: no compatible bridge window
[    0.677811] e820: reserve RAM buffer [mem 0x0009f000-0x0009ffff]
[    0.677813] e820: reserve RAM buffer [mem 0x59d58000-0x5bffffff]
[    0.677813] e820: reserve RAM buffer [mem 0x59d61000-0x5bffffff]
[    0.677814] e820: reserve RAM buffer [mem 0x5e72b000-0x5fffffff]
[    0.677815] e820: reserve RAM buffer [mem 0x63000000-0x63ffffff]
[    0.677815] e820: reserve RAM buffer [mem 0x88f800000-0x88fffffff]
[    0.678358] hpet0: at MMIO 0xfed00000, IRQs 2, 8, 0, 0, 0, 0, 0, 0
[    0.678363] hpet0: 8 comparators, 64-bit 19.200000 MHz counter
[    0.680355] clocksource: Switched to clocksource tsc-early
[    0.687719] VFS: Disk quotas dquot_6.6.0
[    0.687730] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
[    0.687770] pnp: PnP ACPI init
[    0.687955] system 00:00: [io  0x0680-0x069f] has been reserved
[    0.687957] system 00:00: [io  0x164e-0x164f] has been reserved
[    0.687961] system 00:00: Plug and Play ACPI device, IDs PNP0c02 (active)
[    0.687981] pnp 00:01: Plug and Play ACPI device, IDs PNP0b00 (active)
[    0.688054] system 00:02: [io  0x1854-0x1857] has been reserved
[    0.688056] system 00:02: Plug and Play ACPI device, IDs INT3f0d PNP0c02 (active)
[    0.688120] pnp 00:03: Plug and Play ACPI device, IDs PNP0303 (active)
[    0.688131] pnp 00:04: Plug and Play ACPI device, IDs DLL0991 PNP0f13 (active)
[    0.688906] pnp 00:05: disabling [mem 0xc0000000-0xcfffffff] because it overlaps 0000:00:02.0 BAR 9 [mem 0x00000000-0xdfffffff 64bit pref]
[    0.688934] system 00:05: [mem 0xfedc0000-0xfedc7fff] has been reserved
[    0.688936] system 00:05: [mem 0xfeda0000-0xfeda0fff] has been reserved
[    0.688937] system 00:05: [mem 0xfeda1000-0xfeda1fff] has been reserved
[    0.688939] system 00:05: [mem 0xfed20000-0xfed7ffff] could not be reserved
[    0.688941] system 00:05: [mem 0xfed90000-0xfed93fff] could not be reserved
[    0.688943] system 00:05: [mem 0xfed45000-0xfed8ffff] could not be reserved
[    0.688945] system 00:05: [mem 0xfee00000-0xfeefffff] has been reserved
[    0.688949] system 00:05: Plug and Play ACPI device, IDs PNP0c02 (active)
[    0.689896] system 00:06: [io  0x1800-0x18fe] could not be reserved
[    0.689898] system 00:06: [mem 0xfe000000-0xfe01ffff] has been reserved
[    0.689899] system 00:06: [mem 0xfe04c000-0xfe04ffff] has been reserved
[    0.689901] system 00:06: [mem 0xfe050000-0xfe0affff] has been reserved
[    0.689902] system 00:06: [mem 0xfe0d0000-0xfe0fffff] has been reserved
[    0.689904] system 00:06: [mem 0xfe200000-0xfe7fffff] has been reserved
[    0.689905] system 00:06: [mem 0xff000000-0xffffffff] has been reserved
[    0.689907] system 00:06: [mem 0xfd000000-0xfd68ffff] has been reserved
[    0.689909] system 00:06: [mem 0xfd6b0000-0xfd6cffff] has been reserved
[    0.689910] system 00:06: [mem 0xfd6f0000-0xfdffffff] has been reserved
[    0.689913] system 00:06: Plug and Play ACPI device, IDs PNP0c02 (active)
[    0.690198] system 00:07: [io  0x2000-0x20fe] has been reserved
[    0.690200] system 00:07: Plug and Play ACPI device, IDs PNP0c02 (active)
[    0.690385] system 00:08: Plug and Play ACPI device, IDs PNP0c02 (active)
[    0.693567] pnp: PnP ACPI: found 9 devices
[    0.698971] clocksource: acpi_pm: mask: 0xffffff max_cycles: 0xffffff, max_idle_ns: 2085701024 ns
[    0.699012] NET: Registered protocol family 2
[    0.699172] tcp_listen_portaddr_hash hash table entries: 16384 (order: 6, 262144 bytes, linear)
[    0.699280] TCP established hash table entries: 262144 (order: 9, 2097152 bytes, linear)
[    0.699833] TCP bind hash table entries: 65536 (order: 8, 1048576 bytes, linear)
[    0.700122] TCP: Hash tables configured (established 262144 bind 65536)
[    0.700252] MPTCP token hash table entries: 32768 (order: 7, 786432 bytes, linear)
[    0.700323] UDP hash table entries: 16384 (order: 7, 524288 bytes, linear)
[    0.700513] UDP-Lite hash table entries: 16384 (order: 7, 524288 bytes, linear)
[    0.700730] NET: Registered protocol family 1
[    0.700741] NET: Registered protocol family 44
[    0.700745] pci 0000:00:07.0: bridge window [io  0x1000-0x0fff] to [bus 02-39] add_size 1000
[    0.700747] pci 0000:00:07.2: bridge window [io  0x1000-0x0fff] to [bus 3a-71] add_size 1000
[    0.700755] pci 0000:00:02.0: BAR 9: assigned [mem 0x4020000000-0x40ffffffff 64bit pref]
[    0.700758] pci 0000:00:02.0: BAR 7: assigned [mem 0x4010000000-0x4016ffffff 64bit]
[    0.700760] pci 0000:00:07.0: BAR 13: assigned [io  0x4000-0x4fff]
[    0.700761] pci 0000:00:07.2: BAR 13: assigned [io  0x5000-0x5fff]
[    0.700762] pci 0000:00:15.0: BAR 0: assigned [mem 0x4017000000-0x4017000fff 64bit]
[    0.700820] pci 0000:00:15.1: BAR 0: assigned [mem 0x4017001000-0x4017001fff 64bit]
[    0.700883] pci 0000:00:19.0: BAR 0: assigned [mem 0x4017002000-0x4017002fff 64bit]
[    0.700899] pci 0000:00:19.1: BAR 0: assigned [mem 0x4017003000-0x4017003fff 64bit]
[    0.700914] pci 0000:00:1e.0: BAR 0: assigned [mem 0x4017004000-0x4017004fff 64bit]
[    0.700928] pci 0000:00:1f.5: BAR 0: assigned [mem 0x70800000-0x70800fff]
[    0.700939] pci 0000:00:06.0: PCI bridge to [bus 01]
[    0.700942] pci 0000:00:06.0:   bridge window [mem 0xa2600000-0xa26fffff]
[    0.700946] pci 0000:00:07.0: PCI bridge to [bus 02-39]
[    0.700948] pci 0000:00:07.0:   bridge window [io  0x4000-0x4fff]
[    0.700951] pci 0000:00:07.0:   bridge window [mem 0x8c000000-0xa23fffff]
[    0.700953] pci 0000:00:07.0:   bridge window [mem 0x6000000000-0x6021ffffff 64bit pref]
[    0.700957] pci 0000:00:07.2: PCI bridge to [bus 3a-71]
[    0.700958] pci 0000:00:07.2:   bridge window [io  0x5000-0x5fff]
[    0.700961] pci 0000:00:07.2:   bridge window [mem 0x74000000-0x8a3fffff]
[    0.700963] pci 0000:00:07.2:   bridge window [mem 0x6030000000-0x6051ffffff 64bit pref]
[    0.700967] pci 0000:00:1c.0: PCI bridge to [bus 72]
[    0.700972] pci 0000:00:1c.0:   bridge window [mem 0xa2500000-0xa25fffff]
[    0.700979] pci 0000:00:1d.0: PCI bridge to [bus 73]
[    0.700982] pci 0000:00:1d.0:   bridge window [mem 0xa2400000-0xa24fffff]
[    0.700989] pci_bus 0000:00: resource 4 [io  0x0000-0x0cf7 window]
[    0.700990] pci_bus 0000:00: resource 5 [io  0x0d00-0xffff window]
[    0.700991] pci_bus 0000:00: resource 6 [mem 0x000a0000-0x000bffff window]
[    0.700992] pci_bus 0000:00: resource 7 [mem 0x70800000-0xbfffffff window]
[    0.700992] pci_bus 0000:00: resource 8 [mem 0x4000000000-0x7fffffffff window]
[    0.700993] pci_bus 0000:01: resource 1 [mem 0xa2600000-0xa26fffff]
[    0.700994] pci_bus 0000:02: resource 0 [io  0x4000-0x4fff]
[    0.700995] pci_bus 0000:02: resource 1 [mem 0x8c000000-0xa23fffff]
[    0.700996] pci_bus 0000:02: resource 2 [mem 0x6000000000-0x6021ffffff 64bit pref]
[    0.700996] pci_bus 0000:3a: resource 0 [io  0x5000-0x5fff]
[    0.700997] pci_bus 0000:3a: resource 1 [mem 0x74000000-0x8a3fffff]
[    0.700998] pci_bus 0000:3a: resource 2 [mem 0x6030000000-0x6051ffffff 64bit pref]
[    0.700999] pci_bus 0000:72: resource 1 [mem 0xa2500000-0xa25fffff]
[    0.701000] pci_bus 0000:73: resource 1 [mem 0xa2400000-0xa24fffff]
[    0.701101] pci 0000:00:02.0: Video device with shadowed ROM at [mem 0x000c0000-0x000dffff]
[    0.701543] PCI: CLS 0 bytes, default 64
[    0.701570] Trying to unpack rootfs image as initramfs...
[    0.979816] Freeing initrd memory: 29768K
[    0.979854] PCI-DMA: Using software bounce buffering for IO (SWIOTLB)
[    0.979854] software IO TLB: mapped [mem 0x000000004e9aa000-0x00000000529aa000] (64MB)
[    0.979877] clocksource: tsc: mask: 0xffffffffffffffff max_cycles: 0x2b2c8ec87c7, max_idle_ns: 440795278598 ns
[    0.979910] clocksource: Switched to clocksource tsc
[    0.980544] Initialise system trusted keyrings
[    0.980553] Key type blacklist registered
[    0.980583] workingset: timestamp_bits=36 max_order=23 bucket_order=0
[    0.981351] zbud: loaded
[    0.981666] integrity: Platform Keyring initialized
[    0.988903] NET: Registered protocol family 38
[    0.988905] xor: automatically using best checksumming function   avx       
[    0.988906] Key type asymmetric registered
[    0.988907] Asymmetric key parser 'x509' registered
[    0.988911] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 245)
[    0.988952] io scheduler mq-deadline registered
[    0.988953] io scheduler kyber registered
[    0.988968] io scheduler bfq registered
[    0.989051] atomic64_test: passed for x86-64 platform with CX8 and with SSE
[    0.989260] pcieport 0000:00:06.0: PME: Signaling with IRQ 124
[    0.989456] pcieport 0000:00:07.0: PME: Signaling with IRQ 125
[    0.989470] pcieport 0000:00:07.0: pciehp: Slot #0 AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug+ Surprise+ Interlock- NoCompl+ IbPresDis- LLActRep+
[    0.989728] pcieport 0000:00:07.2: PME: Signaling with IRQ 126
[    0.989741] pcieport 0000:00:07.2: pciehp: Slot #0 AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug+ Surprise+ Interlock- NoCompl+ IbPresDis- LLActRep+
[    0.989956] pcieport 0000:00:1c.0: PME: Signaling with IRQ 127
[    0.990151] pcieport 0000:00:1d.0: PME: Signaling with IRQ 128
[    0.990242] shpchp: Standard Hot Plug PCI Controller Driver version: 0.4
[    0.990258] efifb: probing for efifb
[    0.990276] efifb: Ignoring BGRT: unexpected or invalid BMP data
[    0.990277] efifb: framebuffer at 0x4000000000, using 9000k, total 9000k
[    0.990278] efifb: mode is 1920x1200x32, linelength=7680, pages=1
[    0.990279] efifb: scrolling: redraw
[    0.990280] efifb: Truecolor: size=8:8:8:8, shift=24:16:8:0
[    0.990350] fbcon: Deferring console take-over
[    0.990351] fb0: EFI VGA frame buffer device
[    0.990356] intel_idle: MWAIT substates: 0x11121020
[    0.990507] Monitor-Mwait will be used to enter C-1 state
[    0.990527] Monitor-Mwait will be used to enter C-2 state
[    0.990532] Monitor-Mwait will be used to enter C-3 state
[    0.990535] ACPI: \_SB_.PR00: Found 3 idle states
[    0.990537] intel_idle: v0.5.1 model 0x8C
[    0.990777] intel_idle: Local APIC timer is reliable in all C-states
[    0.992369] ACPI: AC Adapter [AC] (off-line)
[    0.992407] input: Lid Switch as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0C0D:00/input/input0
[    0.992426] ACPI: Lid Switch [LID0]
[    0.992437] input: Power Button as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0C0C:00/input/input1
[    0.992447] ACPI: Power Button [PBTN]
[    0.992533] smpboot: Estimated ratio of average max frequency by base frequency (times 1024): 1467
[    0.993869] Serial: 8250/16550 driver, 32 ports, IRQ sharing enabled
[    0.994690] serial 0000:00:12.0: enabling device (0000 -> 0002)
[    0.995380] Non-volatile memory driver v1.3
[    0.995394] Linux agpgart interface v0.103
[    0.996993] tpm_tis STM0125:00: 2.0 TPM (device-id 0x0, rev-id 78)
[    1.016186] battery: ACPI: Battery Slot [BAT0] (battery present)
[    1.019484] intel-lpss 0000:00:15.0: enabling device (0000 -> 0002)
[    1.042714] intel-lpss 0000:00:15.1: enabling device (0000 -> 0002)
[    1.064606] intel-lpss 0000:00:19.0: enabling device (0000 -> 0002)
[    1.086401] intel-lpss 0000:00:19.1: enabling device (0000 -> 0002)
[    1.108602] intel-lpss 0000:00:1e.0: enabling device (0000 -> 0002)
[    1.109152] dw-apb-uart.4: ttyS4 at MMIO 0x4017004000 (irq = 16, base_baud = 6250000) is a 16550A
[    1.112092] serial serial0: tty port ttyS4 registered
[    1.112595] libphy: Fixed MDIO Bus: probed
[    1.112652] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
[    1.112654] ehci-pci: EHCI PCI platform driver
[    1.112659] ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver
[    1.112660] ohci-pci: OHCI PCI platform driver
[    1.112664] uhci_hcd: USB Universal Host Controller Interface driver
[    1.112696] xhci_hcd 0000:00:0d.0: xHCI Host Controller
[    1.112713] xhci_hcd 0000:00:0d.0: new USB bus registered, assigned bus number 1
[    1.113774] xhci_hcd 0000:00:0d.0: hcc params 0x20007fc1 hci version 0x120 quirks 0x0000000200009810
[    1.113910] usb usb1: New USB device found, idVendor=1d6b, idProduct=0002, bcdDevice= 5.11
[    1.113911] usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[    1.113912] usb usb1: Product: xHCI Host Controller
[    1.113913] usb usb1: Manufacturer: Linux 5.11.18-300.fc34.x86_64 xhci-hcd
[    1.113914] usb usb1: SerialNumber: 0000:00:0d.0
[    1.114002] hub 1-0:1.0: USB hub found
[    1.114009] hub 1-0:1.0: 1 port detected
[    1.114101] xhci_hcd 0000:00:0d.0: xHCI Host Controller
[    1.114114] xhci_hcd 0000:00:0d.0: new USB bus registered, assigned bus number 2
[    1.114115] xhci_hcd 0000:00:0d.0: Host supports USB 3.1 Enhanced SuperSpeed
[    1.114137] usb usb2: New USB device found, idVendor=1d6b, idProduct=0003, bcdDevice= 5.11
[    1.114139] usb usb2: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[    1.114139] usb usb2: Product: xHCI Host Controller
[    1.114140] usb usb2: Manufacturer: Linux 5.11.18-300.fc34.x86_64 xhci-hcd
[    1.114141] usb usb2: SerialNumber: 0000:00:0d.0
[    1.114178] hub 2-0:1.0: USB hub found
[    1.114185] hub 2-0:1.0: 4 ports detected
[    1.114967] xhci_hcd 0000:00:14.0: xHCI Host Controller
[    1.115003] xhci_hcd 0000:00:14.0: new USB bus registered, assigned bus number 3
[    1.116476] xhci_hcd 0000:00:14.0: hcc params 0x20007fc1 hci version 0x120 quirks 0x0000000000009810
[    1.116668] usb usb3: New USB device found, idVendor=1d6b, idProduct=0002, bcdDevice= 5.11
[    1.116669] usb usb3: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[    1.116670] usb usb3: Product: xHCI Host Controller
[    1.116670] usb usb3: Manufacturer: Linux 5.11.18-300.fc34.x86_64 xhci-hcd
[    1.116671] usb usb3: SerialNumber: 0000:00:14.0
[    1.116738] hub 3-0:1.0: USB hub found
[    1.116757] hub 3-0:1.0: 12 ports detected
[    1.117295] xhci_hcd 0000:00:14.0: xHCI Host Controller
[    1.117327] xhci_hcd 0000:00:14.0: new USB bus registered, assigned bus number 4
[    1.117329] xhci_hcd 0000:00:14.0: Host supports USB 3.1 Enhanced SuperSpeed
[    1.117355] usb usb4: New USB device found, idVendor=1d6b, idProduct=0003, bcdDevice= 5.11
[    1.117356] usb usb4: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[    1.117357] usb usb4: Product: xHCI Host Controller
[    1.117358] usb usb4: Manufacturer: Linux 5.11.18-300.fc34.x86_64 xhci-hcd
[    1.117358] usb usb4: SerialNumber: 0000:00:14.0
[    1.117398] hub 4-0:1.0: USB hub found
[    1.117410] hub 4-0:1.0: 4 ports detected
[    1.117493] usb: port power management may be unreliable
[    1.117633] usbcore: registered new interface driver usbserial_generic
[    1.117635] usbserial: USB Serial support registered for generic
[    1.117658] i8042: PNP: PS/2 Controller [PNP0303:PS2K,PNP0f13:PS2M] at 0x60,0x64 irq 1,12
[    1.117982] i8042: Warning: Keylock active
[    1.120184] serio: i8042 KBD port at 0x60,0x64 irq 1
[    1.120186] serio: i8042 AUX port at 0x60,0x64 irq 12
[    1.120342] mousedev: PS/2 mouse device common for all mice
[    1.120479] rtc_cmos 00:01: RTC can wake from S4
[    1.121390] rtc_cmos 00:01: registered as rtc0
[    1.121666] rtc_cmos 00:01: setting system clock to 2021-05-11T12:17:05 UTC (1620735425)
[    1.121701] rtc_cmos 00:01: alarms up to one month, y3k, 242 bytes nvram
[    1.121744] device-mapper: uevent: version 1.0.3
[    1.121859] device-mapper: ioctl: 4.43.0-ioctl (2020-10-01) initialised: dm-devel at redhat.com
[    1.121917] intel_pstate: Intel P-state driver initializing
[    1.122212] input: AT Translated Set 2 keyboard as /devices/platform/i8042/serio0/input/input2
[    1.122554] intel_pstate: HWP enabled
[    1.122756] hid: raw HID events driver (C) Jiri Kosina
[    1.122780] usbcore: registered new interface driver usbhid
[    1.122781] usbhid: USB HID core driver
[    1.122855] intel_pmc_core INT33A1:00:  initialized
[    1.122919] drop_monitor: Initializing network drop monitor service
[    1.122973] Initializing XFRM netlink socket
[    1.123053] NET: Registered protocol family 10
[    1.125748] Segment Routing with IPv6
[    1.125749] RPL Segment Routing with IPv6
[    1.125762] mip6: Mobile IPv6
[    1.125763] NET: Registered protocol family 17
[    1.126749] microcode: sig=0x806c1, pf=0x80, revision=0x86
[    1.126778] microcode: Microcode Update Driver: v2.2.
[    1.126846] resctrl: L2 allocation detected
[    1.126847] resctrl: L2DATA allocation detected
[    1.126848] resctrl: L2CODE allocation detected
[    1.126850] IPI shorthand broadcast: enabled
[    1.126854] AVX2 version of gcm_enc/dec engaged.
[    1.126855] AES CTR mode by8 optimization enabled
[    1.137817] sched_clock: Marking stable (1133297306, 4509748)->(1147858648, -10051594)
[    1.137919] registered taskstats version 1
[    1.137930] Loading compiled-in X.509 certificates
[    1.138485] Loaded X.509 cert 'Fedora kernel signing key: 9d24c105418ec9559d89b9ccc2c02c132cb9c636'
[    1.138553] zswap: loaded using pool lzo/zbud
[    1.138628] Key type ._fscrypt registered
[    1.138629] Key type .fscrypt registered
[    1.138629] Key type fscrypt-provisioning registered
[    1.138768] Btrfs loaded, crc32c=crc32c-generic, zoned=yes
[    1.140566] Key type encrypted registered
[    1.140616] integrity: Loading X.509 certificate: UEFI:db
[    1.140634] integrity: Loaded X.509 cert 'Dell Inc.: Dell Bios DB Key: 637fa7a9f74471b406de0511557071fd41dd5487'
[    1.140635] integrity: Loading X.509 certificate: UEFI:db
[    1.140649] integrity: Loaded X.509 cert 'Dell Inc.: Dell Bios FW Aux Authority 2018: dd4df7c3f5ce7e5a77847915abc37b031f6b10bd'
[    1.140650] integrity: Loading X.509 certificate: UEFI:db
[    1.140666] integrity: Loaded X.509 cert 'Microsoft Windows Production PCA 2011: a92902398e16c49778cd90f99e4f9ae17c55af53'
[    1.140667] integrity: Loading X.509 certificate: UEFI:db
[    1.140683] integrity: Loaded X.509 cert 'Microsoft Corporation UEFI CA 2011: 13adbf4309bd82709c8cd54f316ed522988a1bd4'
[    1.140933] integrity: Loading X.509 certificate: UEFI:MokListRT (MOKvar table)
[    1.161609] integrity: Loaded X.509 cert 'Fedora Secure Boot CA: fde32599c2d61db1bf5807335d7b20e4cd963b42'
[    1.161619] ima: Allocated hash algorithm: sha256
[    1.179930] ima: No architecture policies found
[    1.179943] evm: Initialising EVM extended attributes:
[    1.179943] evm: security.selinux
[    1.179944] evm: security.ima
[    1.179945] evm: security.capability
[    1.179946] evm: HMAC attrs: 0x1
[    1.181697] PM:   Magic number: 5:810:278
[    1.181738] tty tty15: hash matches
[    1.181823] memory memory144: hash matches
[    1.181895] RAS: Correctable Errors collector initialized.
[    1.190292] Freeing unused decrypted memory: 2036K
[    1.190795] Freeing unused kernel image (initmem) memory: 2540K
[    1.197471] Write protecting the kernel read-only data: 26624k
[    1.198142] Freeing unused kernel image (text/rodata gap) memory: 2036K
[    1.198420] Freeing unused kernel image (rodata/data gap) memory: 500K
[    1.206161] x86/mm: Checked W+X mappings: passed, no W+X pages found.
[    1.206166] rodata_test: all tests were successful
[    1.206172] Run /init as init process
[    1.206173]   with arguments:
[    1.206174]     /init
[    1.206175]     rhgb
[    1.206176]   with environment:
[    1.206176]     HOME=/
[    1.206177]     TERM=linux
[    1.206177]     BOOT_IMAGE=(hd0,gpt4)/boot/vmlinuz-5.11.18-300.fc34.x86_64
[    1.218232] systemd[1]: systemd v248-2.fc34 running in system mode. (+PAM +AUDIT +SELINUX -APPARMOR +IMA +SMACK +SECCOMP +GCRYPT +GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 +PWQUALITY +P11KIT +QRENCODE +BZIP2 +LZ4 +XZ +ZLIB +ZSTD +XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
[    1.229478] systemd[1]: Detected architecture x86-64.
[    1.229480] systemd[1]: Running in initial RAM disk.
[    1.229504] systemd[1]: Hostname set to <dellpow>.
[    1.272781] systemd[1]: Queued start job for default target Initrd Default Target.
[    1.272881] systemd[1]: Reached target Local File Systems.
[    1.272927] systemd[1]: Reached target Slices.
[    1.272937] systemd[1]: Reached target Swap.
[    1.272944] systemd[1]: Reached target Timers.
[    1.273025] systemd[1]: Listening on Journal Audit Socket.
[    1.273066] systemd[1]: Listening on Journal Socket (/dev/log).
[    1.273106] systemd[1]: Listening on Journal Socket.
[    1.273150] systemd[1]: Listening on udev Control Socket.
[    1.273178] systemd[1]: Listening on udev Kernel Socket.
[    1.273185] systemd[1]: Reached target Sockets.
[    1.274170] systemd[1]: Starting Create list of static device nodes for the current kernel...
[    1.274198] systemd[1]: Condition check resulted in Memstrack Anylazing Service being skipped.
[    1.275004] systemd[1]: Starting Journal Service...
[    1.275594] systemd[1]: Starting Load Kernel Modules...
[    1.276072] systemd[1]: Starting Setup Virtual Console...
[    1.276490] systemd[1]: Finished Create list of static device nodes for the current kernel.
[    1.277013] systemd[1]: Starting Create Static Device Nodes in /dev...
[    1.280854] systemd[1]: Finished Create Static Device Nodes in /dev.
[    1.293495] fuse: init (API version 7.33)
[    1.294313] systemd[1]: Finished Load Kernel Modules.
[    1.294917] systemd[1]: Starting Apply Kernel Variables...
[    1.297870] systemd[1]: Started Journal Service.
[    1.436461] usb 3-3: new full-speed USB device number 2 using xhci_hcd
[    1.490937] acpi PNP0C14:01: duplicate WMI GUID 05901221-D566-11D1-B2F0-00A0C9062910 (first instance was on PNP0C14:00)
[    1.491007] wmi_bus wmi_bus-PNP0C14:02: WQBC data block query control method not found
[    1.491009] acpi PNP0C14:02: duplicate WMI GUID 05901221-D566-11D1-B2F0-00A0C9062910 (first instance was on PNP0C14:00)
[    1.493512] acpi PNP0C14:03: duplicate WMI GUID 05901221-D566-11D1-B2F0-00A0C9062910 (first instance was on PNP0C14:00)
[    1.495273] acpi PNP0C14:04: duplicate WMI GUID 05901221-D566-11D1-B2F0-00A0C9062910 (first instance was on PNP0C14:00)
[    1.495341] acpi PNP0C14:05: duplicate WMI GUID 05901221-D566-11D1-B2F0-00A0C9062910 (first instance was on PNP0C14:00)
[    1.495388] acpi PNP0C14:06: duplicate WMI GUID 05901221-D566-11D1-B2F0-00A0C9062910 (first instance was on PNP0C14:00)
[    1.495422] acpi PNP0C14:07: duplicate WMI GUID 05901221-D566-11D1-B2F0-00A0C9062910 (first instance was on PNP0C14:00)
[    1.497855] i2c_hid i2c-DLL0945:00: supply vdd not found, using dummy regulator
[    1.497881] i2c_hid i2c-DLL0945:00: supply vddl not found, using dummy regulator
[    1.509653] rtsx_pci 0000:73:00.0: enabling device (0000 -> 0002)
[    1.557064] nvme nvme0: pci function 0000:01:00.0
[    1.565342] usb 3-3: New USB device found, idVendor=27c6, idProduct=533c, bcdDevice= 1.00
[    1.565345] usb 3-3: New USB device strings: Mfr=1, Product=2, SerialNumber=0
[    1.565347] usb 3-3: Product: FingerPrint
[    1.565348] usb 3-3: Manufacturer: Goodix
[    1.566219] nvme nvme0: 8/0/0 default/read/poll queues
[    1.568099]  nvme0n1: p1 p2 p3 p4
[    1.647726] input: DLL0945:00 06CB:CDE6 Mouse as /devices/pci0000:00/0000:00:15.1/i2c_designware.1/i2c-1/i2c-DLL0945:00/0018:06CB:CDE6.0001/input/input5
[    1.647857] input: DLL0945:00 06CB:CDE6 Touchpad as /devices/pci0000:00/0000:00:15.1/i2c_designware.1/i2c-1/i2c-DLL0945:00/0018:06CB:CDE6.0001/input/input6
[    1.647962] hid-generic 0018:06CB:CDE6.0001: input,hidraw0: I2C HID v1.00 Mouse [DLL0945:00 06CB:CDE6] on i2c-DLL0945:00
[    1.658171] BTRFS: device label dellpow-fedora devid 1 transid 177058 /dev/nvme0n1p4 scanned by systemd-udevd (338)
[    1.679361] usb 3-6: new high-speed USB device number 3 using xhci_hcd
[    1.696249] checking generic (4000000000 8ca000) vs hw (6052000000 1000000)
[    1.696251] checking generic (4000000000 8ca000) vs hw (4000000000 10000000)
[    1.696252] fb0: switching to inteldrmfb from EFI VGA
[    1.696344] i915 0000:00:02.0: vgaarb: deactivate vga console
[    1.698032] i915 0000:00:02.0: vgaarb: changed VGA decodes: olddecodes=io+mem,decodes=io+mem:owns=io+mem
[    1.699194] i915 0000:00:02.0: [drm] Finished loading DMC firmware i915/tgl_dmc_ver2_08.bin (v2.8)
[    1.714996] i915 0000:00:02.0: [drm] Panel advertises DPCD backlight support, but VBT disagrees. If your backlight controls don't work try booting with i915.enable_dpcd_backlight=1. If your machine needs this, please file a _new_ bug report on drm/i915, see https://gitlab.freedesktop.org/drm/intel/-/wikis/How-to-file-i915-bugs for details.
[    1.751682] input: DLL0945:00 06CB:CDE6 Mouse as /devices/pci0000:00/0000:00:15.1/i2c_designware.1/i2c-1/i2c-DLL0945:00/0018:06CB:CDE6.0001/input/input8
[    1.751842] input: DLL0945:00 06CB:CDE6 Touchpad as /devices/pci0000:00/0000:00:15.1/i2c_designware.1/i2c-1/i2c-DLL0945:00/0018:06CB:CDE6.0001/input/input9
[    1.751880] hid-multitouch 0018:06CB:CDE6.0001: input,hidraw0: I2C HID v1.00 Mouse [DLL0945:00 06CB:CDE6] on i2c-DLL0945:00
[    1.821820] usb 3-6: New USB device found, idVendor=0c45, idProduct=672a, bcdDevice= 5.29
[    1.821830] usb 3-6: New USB device strings: Mfr=2, Product=1, SerialNumber=0
[    1.821832] usb 3-6: Product: Integrated_Webcam_HD
[    1.821835] usb 3-6: Manufacturer: CN03GGY48LG0011GB25TA00
[    2.177599] ish-hid {33AECD58-B679-4E54-9BD9-A04D34F0C226}: [hid-ish]: enum_devices_done OK, num_hid_devices=1
[    2.178945] hid-generic 001F:8087:0AC2.0002: hidraw1: <UNKNOWN> HID v2.00 Device [hid-ishtp 8087:0AC2] on 
[    2.859424] [drm] Initialized i915 1.6.0 20201103 for 0000:00:02.0 on minor 0
[    2.863356] ACPI: Video Device [GFX0] (multi-head: yes  rom: no  post: no)
[    2.864588] input: Video Bus as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0A08:00/LNXVIDEO:00/input/input11
[    2.866813] fbcon: i915drmfb (fb0) is primary device
[    2.866817] fbcon: Deferring console take-over
[    2.866822] i915 0000:00:02.0: [drm] fb0: i915drmfb frame buffer device
[    2.924309] BTRFS info (device nvme0n1p4): disk space caching is enabled
[    2.924312] BTRFS info (device nvme0n1p4): has skinny extents
[    2.936942] BTRFS info (device nvme0n1p4): enabling ssd optimizations
[    3.114523] systemd-journald[238]: Received SIGTERM from PID 1 (systemd).
[    3.225641] SELinux:  policy capability network_peer_controls=1
[    3.225644] SELinux:  policy capability open_perms=1
[    3.225645] SELinux:  policy capability extended_socket_class=1
[    3.225645] SELinux:  policy capability always_check_network=0
[    3.225646] SELinux:  policy capability cgroup_seclabel=1
[    3.225646] SELinux:  policy capability nnp_nosuid_transition=1
[    3.225646] SELinux:  policy capability genfs_seclabel_symlinks=0
[    3.248142] systemd[1]: Successfully loaded SELinux policy in 59.328ms.
[    3.278741] systemd[1]: Relabelled /dev, /dev/shm, /run, /sys/fs/cgroup in 14.143ms.
[    3.282324] systemd[1]: systemd v248-2.fc34 running in system mode. (+PAM +AUDIT +SELINUX -APPARMOR +IMA +SMACK +SECCOMP +GCRYPT +GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 +PWQUALITY +P11KIT +QRENCODE +BZIP2 +LZ4 +XZ +ZLIB +ZSTD +XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
[    3.294528] systemd[1]: Detected architecture x86-64.
[    3.323647] systemd-sysv-generator[515]: SysV service '/etc/rc.d/init.d/livesys' lacks a native systemd unit file. Automatically generating a unit file for compatibility. Please update package to include a native systemd unit file, in order to make it more safe and robust.
[    3.323689] systemd-sysv-generator[515]: SysV service '/etc/rc.d/init.d/livesys-late' lacks a native systemd unit file. Automatically generating a unit file for compatibility. Please update package to include a native systemd unit file, in order to make it more safe and robust.
[    3.332909] zram: Added device: zram0
[    3.405692] systemd[1]: /usr/lib/systemd/system/alsa-restore.service:15: Standard output type syslog is obsolete, automatically updating to journal. Please update your unit file, and consider removing the setting altogether.
[    3.448886] systemd[1]: initrd-switch-root.service: Deactivated successfully.
[    3.449009] systemd[1]: Stopped Switch Root.
[    3.449303] systemd[1]: systemd-journald.service: Scheduled restart job, restart counter is at 1.
[    3.449517] systemd[1]: Created slice Virtual Machine and Container Slice.
[    3.449694] systemd[1]: Created slice system-getty.slice.
[    3.449850] systemd[1]: Created slice system-modprobe.slice.
[    3.449995] systemd[1]: Created slice system-openvpn\x2dclient.slice.
[    3.450121] systemd[1]: Created slice system-sshd\x2dkeygen.slice.
[    3.450243] systemd[1]: Created slice system-systemd\x2dfsck.slice.
[    3.450380] systemd[1]: Created slice system-systemd\x2dzram\x2dsetup.slice.
[    3.450522] systemd[1]: Created slice User and Session Slice.
[    3.450541] systemd[1]: Condition check resulted in Dispatch Password Requests to Console Directory Watch being skipped.
[    3.450609] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
[    3.450865] systemd[1]: Set up automount Arbitrary Executable File Formats File System Automount Point.
[    3.450893] systemd[1]: Reached target Local Encrypted Volumes.
[    3.450909] systemd[1]: Reached target Login Prompts.
[    3.450928] systemd[1]: Stopped target Switch Root.
[    3.450942] systemd[1]: Stopped target Initrd File Systems.
[    3.450953] systemd[1]: Stopped target Initrd Root File System.
[    3.450991] systemd[1]: Reached target Slices.
[    3.451014] systemd[1]: Reached target Local Verity Integrity Protected Volumes.
[    3.451258] systemd[1]: Listening on Device-mapper event daemon FIFOs.
[    3.451802] systemd[1]: Listening on LVM2 poll daemon socket.
[    3.451890] systemd[1]: Listening on multipathd control socket.
[    3.455173] systemd[1]: Listening on RPCbind Server Activation Socket.
[    3.455208] systemd[1]: Reached target RPC Port Mapper.
[    3.456167] systemd[1]: Listening on Process Core Dump Socket.
[    3.456256] systemd[1]: Listening on initctl Compatibility Named Pipe.
[    3.457196] systemd[1]: Listening on udev Control Socket.
[    3.457592] systemd[1]: Listening on udev Kernel Socket.
[    3.457869] systemd[1]: Listening on User Database Manager Socket.
[    3.458554] systemd[1]: Mounting Huge Pages File System...
[    3.459372] systemd[1]: Mounting POSIX Message Queue File System...
[    3.460170] systemd[1]: Mounting Kernel Debug File System...
[    3.461086] systemd[1]: Mounting Kernel Trace File System...
[    3.461236] systemd[1]: Condition check resulted in Kernel Module supporting RPCSEC_GSS being skipped.
[    3.461977] systemd[1]: Starting Create list of static device nodes for the current kernel...
[    3.462918] systemd[1]: Starting Monitoring of LVM2 mirrors, snapshots etc. using dmeventd or progress polling...
[    3.463865] systemd[1]: Starting Load Kernel Module configfs...
[    3.464597] systemd[1]: Starting Load Kernel Module drm...
[    3.465334] systemd[1]: Starting Load Kernel Module fuse...
[    3.466121] systemd[1]: Starting Preprocess NFS configuration convertion...
[    3.466392] systemd[1]: plymouth-switch-root.service: Deactivated successfully.
[    3.466550] systemd[1]: Stopped Plymouth switch root service.
[    3.466800] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
[    3.466919] systemd[1]: systemd-fsck-root.service: Deactivated successfully.
[    3.467047] systemd[1]: Stopped File System Check on Root Device.
[    3.467145] systemd[1]: Stopped Journal Service.
[    3.468420] systemd[1]: Starting Journal Service...
[    3.469269] systemd[1]: Starting Load Kernel Modules...
[    3.470119] systemd[1]: Starting Remount Root and Kernel File Systems...
[    3.470193] systemd[1]: Condition check resulted in Repartition Root Disk being skipped.
[    3.471008] systemd[1]: Starting Coldplug All udev Devices...
[    3.471866] systemd[1]: sysroot.mount: Deactivated successfully.
[    3.472891] systemd[1]: Mounted Huge Pages File System.
[    3.473051] systemd[1]: Mounted POSIX Message Queue File System.
[    3.473133] systemd[1]: Mounted Kernel Debug File System.
[    3.473196] systemd[1]: Mounted Kernel Trace File System.
[    3.473560] systemd[1]: Finished Create list of static device nodes for the current kernel.
[    3.473806] systemd[1]: modprobe at configfs.service: Deactivated successfully.
[    3.474000] systemd[1]: Finished Load Kernel Module configfs.
[    3.474268] systemd[1]: modprobe at drm.service: Deactivated successfully.
[    3.474486] systemd[1]: Finished Load Kernel Module drm.
[    3.474844] systemd[1]: modprobe at fuse.service: Deactivated successfully.
[    3.475031] systemd[1]: Finished Load Kernel Module fuse.
[    3.475407] systemd[1]: nfs-convert.service: Deactivated successfully.
[    3.475581] systemd[1]: Finished Preprocess NFS configuration convertion.
[    3.475946] systemd[1]: Finished Load Kernel Modules.
[    3.476828] BTRFS info (device nvme0n1p4): use zstd compression, level 3
[    3.476833] BTRFS info (device nvme0n1p4): turning on async discard
[    3.476835] BTRFS info (device nvme0n1p4): disk space caching is enabled
[    3.477456] systemd[1]: Mounting FUSE Control File System...
[    3.478476] systemd[1]: Mounting Kernel Configuration File System...
[    3.479258] systemd[1]: Starting Apply Kernel Variables...
[    3.480570] systemd[1]: Started Journal Service.
[    3.488341] systemd-journald[540]: Received client request to flush runtime journal.
[    3.623512] input: Intel HID events as /devices/platform/INTC1051:00/input/input12
[    3.623954] intel-hid INTC1051:00: platform supports 5 button array
[    3.623989] input: Intel HID 5 button array as /devices/platform/INTC1051:00/input/input13
[    3.807616] intel-pmt 0000:00:0a.0: Watcher not supported
[    3.807623] intel-pmt 0000:00:0a.0: Crashlog not supported
[    3.820157] proc_thermal 0000:00:04.0: enabling device (0000 -> 0002)
[    3.823979] proc_thermal 0000:00:04.0: Creating sysfs group for PROC_THERMAL_PCI
[    3.824020] intel_rapl_common: Found RAPL domain package
[    3.898656] idma64 idma64.0: Found Intel integrated DMA 64-bit
[    3.911563] idma64 idma64.1: Found Intel integrated DMA 64-bit
[    3.923499] idma64 idma64.2: Found Intel integrated DMA 64-bit
[    3.936468] idma64 idma64.3: Found Intel integrated DMA 64-bit
[    3.949430] idma64 idma64.4: Found Intel integrated DMA 64-bit
[    3.975105] i801_smbus 0000:00:1f.4: enabling device (0000 -> 0003)
[    3.975308] i801_smbus 0000:00:1f.4: SPD Write Disable is set
[    3.975380] i801_smbus 0000:00:1f.4: SMBus using PCI interrupt
[    4.010343] dcdbas dcdbas: Dell Systems Management Base Driver (version 5.6.0-3.4)
[    4.019004] input: PC Speaker as /devices/platform/pcspkr/input/input14
[    4.019043] input: Dell WMI hotkeys as /devices/platform/PNP0C14:02/wmi_bus/wmi_bus-PNP0C14:02/9DBB5994-A997-11DA-B012-B622A1EF5492/input/input15
[    4.025381] cfg80211: Loading compiled-in X.509 certificates for regulatory database
[    4.025881] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
[    4.056051] resource sanity check: requesting [mem 0xfedc0000-0xfedcdfff], which spans more than pnp 00:05 [mem 0xfedc0000-0xfedc7fff]
[    4.056057] caller tgl_uncore_imc_freerunning_init_box+0xa7/0xd0 [intel_uncore] mapping multiple BARs
[    4.165285] i2c i2c-18: 8/8 memory slots populated (from DMI)
[    4.165291] i2c i2c-18: Systems with more than 4 memory slots not supported yet, not instantiating SPD
[    4.215589] ath11k_pci 0000:72:00.0: WARNING: ath11k PCI support is experimental!
[    4.215665] ath11k_pci 0000:72:00.0: BAR 0: assigned [mem 0xa2500000-0xa25fffff 64bit]
[    4.215688] ath11k_pci 0000:72:00.0: enabling device (0000 -> 0002)
[    4.251399] NET: Registered protocol family 42
[    4.260919] snd_hda_intel 0000:00:1f.3: DSP detected with PCI class/subclass/prog-if info 0x040100
[    4.260946] snd_hda_intel 0000:00:1f.3: Digital mics found on Skylake+ platform, using SOF driver
[    4.288843] sof-audio-pci 0000:00:1f.3: DSP detected with PCI class/subclass/prog-if info 0x040100
[    4.288859] sof-audio-pci 0000:00:1f.3: Digital mics found on Skylake+ platform, using SOF driver
[    4.288878] sof-audio-pci 0000:00:1f.3: enabling device (0000 -> 0002)
[    4.289078] sof-audio-pci 0000:00:1f.3: DSP detected with PCI class/subclass/prog-if 0x040100
[    4.289190] sof-audio-pci 0000:00:1f.3: bound 0000:00:02.0 (ops i915_audio_component_bind_ops [i915])
[    4.295484] sof-audio-pci 0000:00:1f.3: use msi interrupt mode
[    4.306934] mhi mhi0: Requested to power ON
[    4.307073] mhi mhi0: Power on setup success
[    4.384125] zram0: detected capacity change from 0 to 16777216
[    4.451721] Adding 8388604k swap on /dev/zram0.  Priority:100 extents:1 across:8388604k SSFS
[    4.456456] intel_rapl_msr: PL4 support detected.
[    4.459923] intel_rapl_common: Found RAPL domain package
[    4.459928] intel_rapl_common: Found RAPL domain core
[    4.459930] intel_rapl_common: Found RAPL domain uncore
[    4.459932] intel_rapl_common: Found RAPL domain psys
[    4.477228] iTCO_vendor_support: vendor-support=0
[    4.503662] sof-audio-pci 0000:00:1f.3: hda codecs found, mask 5
[    4.503666] sof-audio-pci 0000:00:1f.3: using HDA machine driver skl_hda_dsp_generic now
[    4.503669] sof-audio-pci 0000:00:1f.3: DMICs detected in NHLT tables: 2
[    4.505310] iTCO_wdt iTCO_wdt: Found a Intel PCH TCO device (Version=6, TCOBASE=0x0400)
[    4.505647] iTCO_wdt iTCO_wdt: initialized. heartbeat=30 sec (nowayout=0)
[    4.608480] sof-audio-pci 0000:00:1f.3: Firmware info: version 1:6:1-53680
[    4.608485] sof-audio-pci 0000:00:1f.3: Firmware: ABI 3:17:0 Kernel ABI 3:18:0
[    4.632887] sof-audio-pci 0000:00:1f.3: Topology: ABI 3:17:0 Kernel ABI 3:18:0
[    4.651832] sof-audio-pci 0000:00:1f.3: ASoC: Parent card not yet available, widget card binding deferred
[    4.670788] snd_hda_codec_realtek ehdaudio0D0: autoconfig for ALC289: line_outs=1 (0x17/0x0/0x0/0x0/0x0) type:speaker
[    4.670794] snd_hda_codec_realtek ehdaudio0D0:    speaker_outs=0 (0x0/0x0/0x0/0x0/0x0)
[    4.670796] snd_hda_codec_realtek ehdaudio0D0:    hp_outs=1 (0x21/0x0/0x0/0x0/0x0)
[    4.670798] snd_hda_codec_realtek ehdaudio0D0:    mono: mono_out=0x0
[    4.670799] snd_hda_codec_realtek ehdaudio0D0:    inputs:
[    4.670799] snd_hda_codec_realtek ehdaudio0D0:      Headset Mic=0x19
[    4.670801] snd_hda_codec_realtek ehdaudio0D0:      Headphone Mic=0x1b
[    4.714384] snd_hda_codec_realtek ehdaudio0D0: ASoC: sink widget AIF1TX overwritten
[    4.714392] snd_hda_codec_realtek ehdaudio0D0: ASoC: source widget AIF1RX overwritten
[    4.714539] skl_hda_dsp_generic skl_hda_dsp_generic: ASoC: sink widget hifi3 overwritten
[    4.714543] skl_hda_dsp_generic skl_hda_dsp_generic: ASoC: sink widget hifi2 overwritten
[    4.714547] skl_hda_dsp_generic skl_hda_dsp_generic: ASoC: sink widget hifi1 overwritten
[    4.714551] skl_hda_dsp_generic skl_hda_dsp_generic: ASoC: source widget Codec Output Pin1 overwritten
[    4.714555] skl_hda_dsp_generic skl_hda_dsp_generic: ASoC: sink widget Codec Input Pin1 overwritten
[    4.714560] skl_hda_dsp_generic skl_hda_dsp_generic: ASoC: sink widget Analog Codec Playback overwritten
[    4.714564] skl_hda_dsp_generic skl_hda_dsp_generic: ASoC: sink widget Digital Codec Playback overwritten
[    4.714568] skl_hda_dsp_generic skl_hda_dsp_generic: ASoC: sink widget Alt Analog Codec Playback overwritten
[    4.714574] skl_hda_dsp_generic skl_hda_dsp_generic: ASoC: source widget Analog Codec Capture overwritten
[    4.714579] skl_hda_dsp_generic skl_hda_dsp_generic: ASoC: source widget Digital Codec Capture overwritten
[    4.714583] skl_hda_dsp_generic skl_hda_dsp_generic: ASoC: source widget Alt Analog Codec Capture overwritten
[    4.714589] skl_hda_dsp_generic skl_hda_dsp_generic: hda_dsp_hdmi_build_controls: no PCM in topology for HDMI converter 3

[    4.714591] skl_hda_dsp_generic skl_hda_dsp_generic: hda_dsp_hdmi_build_controls: no PCM in topology for HDMI converter 4

[    4.714592] skl_hda_dsp_generic skl_hda_dsp_generic: hda_dsp_hdmi_build_controls: no PCM in topology for HDMI converter 5

[    4.714594] skl_hda_dsp_generic skl_hda_dsp_generic: hda_dsp_hdmi_build_controls: no PCM in topology for HDMI converter 6

[    4.714595] skl_hda_dsp_generic skl_hda_dsp_generic: hda_dsp_hdmi_build_controls: no PCM in topology for HDMI converter 7

[    4.714596] skl_hda_dsp_generic skl_hda_dsp_generic: hda_dsp_hdmi_build_controls: no PCM in topology for HDMI converter 8

[    4.729882] input: sof-hda-dsp Headphone Mic as /devices/pci0000:00/0000:00:1f.3/skl_hda_dsp_generic/sound/card0/input16
[    4.730053] input: sof-hda-dsp HDMI/DP,pcm=3 as /devices/pci0000:00/0000:00:1f.3/skl_hda_dsp_generic/sound/card0/input17
[    4.730084] input: sof-hda-dsp HDMI/DP,pcm=4 as /devices/pci0000:00/0000:00:1f.3/skl_hda_dsp_generic/sound/card0/input18
[    4.730113] input: sof-hda-dsp HDMI/DP,pcm=5 as /devices/pci0000:00/0000:00:1f.3/skl_hda_dsp_generic/sound/card0/input19
[    4.837110] ath11k_pci 0000:72:00.0: chip_id 0x0 chip_family 0xb board_id 0xff soc_id 0xffffffff
[    4.837117] ath11k_pci 0000:72:00.0: fw_version 0x101c06cc fw_build_timestamp 2020-06-24 19:50 fw_build_id 
[    4.996981] mc: Linux media interface: v0.10
[    5.013743] videodev: Linux video capture interface: v2.00
[    5.022963] ath11k_pci 0000:72:00.0 wlp114s0: renamed from wlan0
[    5.267539] uvcvideo: Found UVC 1.00 device Integrated_Webcam_HD (0c45:672a)
[    5.277778] input: Integrated_Webcam_HD: Integrate as /devices/pci0000:00/0000:00:14.0/usb3/3-6/3-6:1.0/input/input20
[    5.278810] uvcvideo: Found UVC 1.00 device Integrated_Webcam_HD (0c45:672a)
[    5.287079] input: Integrated_Webcam_HD: Integrate as /devices/pci0000:00/0000:00:14.0/usb3/3-6/3-6:1.2/input/input21
[    5.287123] usbcore: registered new interface driver uvcvideo
[    5.287125] USB Video Class driver (1.1.1)
[    5.457330] psmouse serio1: synaptics: Unable to query device: -5
[    7.031591] RPC: Registered named UNIX socket transport module.
[    7.031595] RPC: Registered udp transport module.
[    7.031596] RPC: Registered tcp transport module.
[    7.031597] RPC: Registered tcp NFSv4.1 backchannel transport module.
[   11.057559] input: PS/2 Synaptics TouchPad as /devices/platform/i8042/serio1/input/input4
[   11.265510] psmouse serio1: Failed to enable mouse on isa0060/serio1
[   15.950433] wlp114s0: authenticate with 5c:49:79:3a:xx:xx
[   16.174940] wlp114s0: send auth to 5c:49:79:3a:xx:xx (try 1/3)
[   16.487250] wlp114s0: authenticate with 5c:49:79:3a:xx:xx
[   16.487261] wlp114s0: send auth to 5c:49:79:3a:xx:xx (try 1/3)
[   16.615193] wlp114s0: authenticated
[   16.616430] wlp114s0: associate with 5c:49:79:3a:xx:xx (try 1/3)
[   16.621802] wlp114s0: RX AssocResp from 5c:49:79:3a:xx:xx (capab=0x1511 status=0 aid=2)
[   16.621828] wlp114s0: AP has invalid WMM params (AIFSN=0 for ACI 0), will use 2
[   16.621831] wlp114s0: AP has invalid WMM params (CWmin/max=0/0 for ACI 0), using defaults
[   16.634190] wlp114s0: associated
[   16.704327] wlp114s0: Limiting TX power to 23 (23 - 0) dBm as advertised by 5c:49:79:3a:xx:xx
[   16.994182] IPv6: ADDRCONF(NETDEV_CHANGE): wlp114s0: link becomes ready
[   17.299718] bridge: filtering via arp/ip/ip6tables is no longer available by default. Update your scripts to load br_netfilter if you need this.
[   18.525112] tun: Universal TUN/TAP device driver, 1.6
[   18.919959] rfkill: input handler disabled
[   23.269096] rfkill: input handler enabled
[   24.857299] rfkill: input handler disabled
[   27.410824] FS-Cache: Loaded
[   27.461091] FS-Cache: Netfs 'nfs' registered for caching
[   27.466434] Key type dns_resolver registered
[   27.666076] NFS: Registering the id_resolver key type
[   27.666098] Key type id_resolver registered
[   27.666099] Key type id_legacy registered
[  126.931261] wlp114s0: deauthenticating from 5c:49:79:3a:xx:xx by local choice (Reason: 3=DEAUTH_LEAVING)
[  128.177122] PM: suspend entry (s2idle)
[  128.190671] Filesystems sync: 0.013 seconds
[  128.272778] Freezing user space processes ... (elapsed 0.002 seconds) done.
[  128.275708] OOM killer disabled.
[  128.275709] Freezing remaining freezable tasks ... (elapsed 0.000 seconds) done.
[  128.276586] printk: Suspending console(s) (use no_console_suspend to debug)
[  128.505612] psmouse serio1: Failed to disable mouse on isa0060/serio1
[  129.499987] mhi mhi0: Allowing M3 transition
[  129.499995] mhi mhi0: Wait for M3 completion
[  129.502981] PM: suspend devices took 1.226 seconds
[  129.559728] ACPI: EC: interrupt blocked
[  149.011167] ACPI: EC: interrupt unblocked
[  149.291395] mhi mhi0: Entered with PM state: M3, MHI state: M3
[  149.531202] PM: resume devices took 0.241 seconds
[  149.531229] OOM killer enabled.
[  149.531231] Restarting tasks ... done.
[  149.609249] PM: suspend exit
[  153.569181] wlp114s0: authenticate with 5c:49:79:3a:xx:xx
[  153.678269] wlp114s0: send auth to 5c:49:79:3a:xx:xx (try 1/3)
[  153.991606] wlp114s0: authenticate with 5c:49:79:3a:xx:xx
[  153.991614] wlp114s0: send auth to 5c:49:79:3a:xx:xx (try 1/3)
[  154.120237] wlp114s0: authenticated
[  154.121324] wlp114s0: associate with 5c:49:79:3a:xx:xx (try 1/3)
[  154.126598] wlp114s0: RX AssocResp from 5c:49:79:3a:xx:xx (capab=0x1511 status=0 aid=2)
[  154.126623] wlp114s0: AP has invalid WMM params (AIFSN=0 for ACI 0), will use 2
[  154.126625] wlp114s0: AP has invalid WMM params (CWmin/max=0/0 for ACI 0), using defaults
[  154.137969] wlp114s0: associated 
[  154.229025] wlp114s0: Limiting TX power to 23 (23 - 0) dBm as advertised by 5c:49:79:3a:xx:xx
[  154.364381] IPv6: ADDRCONF(NETDEV_CHANGE): wlp114s0: link becomes ready
[  283.583052] Bluetooth: Core ver 2.22
[  283.583102] NET: Registered protocol family 31
[  283.583104] Bluetooth: HCI device and connection manager initialized
[  283.583109] Bluetooth: HCI socket layer initialized
[  283.583112] Bluetooth: L2CAP socket layer initialized
[  283.583117] Bluetooth: SCO socket layer initialized
[  290.377223] Bluetooth: HCI UART driver ver 2.3
[  290.377230] Bluetooth: HCI UART protocol H4 registered
[  290.377232] Bluetooth: HCI UART protocol BCSP registered
[  290.377267] Bluetooth: HCI UART protocol LL registered
[  290.377269] Bluetooth: HCI UART protocol ATH3K registered
[  290.377285] Bluetooth: HCI UART protocol Three-wire (H5) registered
[  290.377393] Bluetooth: HCI UART protocol Intel registered
[  290.377479] Bluetooth: HCI UART protocol Broadcom registered
[  290.377498] Bluetooth: HCI UART protocol QCA registered
[  290.377500] Bluetooth: HCI UART protocol AG6XX registered
[  290.377516] Bluetooth: HCI UART protocol Marvell registered
[  290.389557] hci_uart_qca serial0-0: failed to acquire enable gpio
[  290.390031] Bluetooth: hci0: setting up ROME/QCA6390
[  290.394119] Bluetooth: hci0: Frame reassembly failed (-84)
[  290.696125] Bluetooth: hci0: QCA Product ID   :0x00000010
[  290.696136] Bluetooth: hci0: QCA SOC Version  :0x400a0200
[  290.696138] Bluetooth: hci0: QCA ROM Version  :0x00000200
[  290.696140] Bluetooth: hci0: QCA Patch Version:0x00000d2b
[  290.696145] Bluetooth: hci0: QCA controller version 0x02000200
[  290.696148] Bluetooth: hci0: QCA Downloading qca/htbtfw20.tlv
[  291.604463] Bluetooth: hci0: QCA Downloading qca/htnv20.bin
[  291.606778] BUG: unable to handle page fault for address: ffffa672809f3047
[  291.606787] #PF: supervisor write access in kernel mode
[  291.606791] #PF: error_code(0x0003) - permissions violation
[  291.606795] PGD 100000067 P4D 100000067 PUD 1001cc067 PMD 1016d5067 PTE 80000002ca996161
[  291.606805] Oops: 0003 [#1] SMP NOPTI
[  291.606811] CPU: 0 PID: 3928 Comm: kworker/u17:3 Not tainted 5.11.18-300.fc34.x86_64 #1
[  291.606818] Hardware name: Dell Inc. XPS 13 9310/0MRT12, BIOS 2.2.0 04/06/2021
[  291.606822] Workqueue: hci0 hci_power_on [bluetooth]
[  291.606867] RIP: 0010:qca_download_firmware+0x231/0x490 [btqca]
[  291.606875] Code: 1b 75 04 80 48 0c 01 0f b7 c1 8d 54 02 0c 41 39 d7 0f 8e 99 fe ff ff 48 63 c2 4c 01 e8 0f b7 30 0f b7 48 02 66 83 fe 11 75 d3 <80> 48 0c 80 41 83 fc 03 7e 6f 44 88 70 0d eb cd 41 0f b6 45 0e 48
[  291.606880] RSP: 0018:ffffa67285c4bc60 EFLAGS: 00010246
[  291.606885] RAX: ffffa672809f303b RBX: 0000000000000005 RCX: 0000000000000006
[  291.606889] RDX: 0000000000000037 RSI: 0000000000000011 RDI: ffff88a80498bd20
[  291.606892] RBP: ffff88a804a2e000 R08: ffff88a9398126c0 R09: ffff88a80498bd20
[  291.606895] R10: 0000000000194e1f R11: 0000000000000000 R12: 0000000000000005
[  291.606897] R13: ffffa672809f3004 R14: 000000000000000e R15: 00000000000016a9
[  291.606901] FS:  0000000000000000(0000) GS:ffff88aeef600000(0000) knlGS:0000000000000000
[  291.606905] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
[  291.606909] CR2: ffffa672809f3047 CR3: 0000000448a10004 CR4: 0000000000770ef0
[  291.606912] PKRU: 55555554x
[  291.606914] Call Trace:
[  291.606924]  qca_uart_setup+0x277/0x5a0 [btqca]
[  291.606931]  ? qca_read_soc_version+0x136/0x220 [btqca]
[  291.606939]  qca_setup+0x52e/0xb40 [hci_uart]
[  291.606963]  hci_dev_do_open+0x1d0/0x740 [bluetooth]
[  291.606996]  ? __switch_to_asm+0x42/0x70
[  291.607006]  ? __switch_to+0x18e/0x460
[  291.607015]  hci_power_on+0x3f/0x200 [bluetooth]
[  291.607047]  ? __schedule+0x2ba/0x900
[  291.607057]  process_one_work+0x1ec/0x380
[  291.607065]  worker_thread+0x53/0x3e0
[  291.607069]  ? process_one_work+0x380/0x380
[  291.607073]  kthread+0x11b/0x140
[  291.607080]  ? kthread_associate_blkcg+0xa0/0xa0
[  291.607086]  ret_from_fork+0x1f/0x30
[  291.607094] Modules linked in: hci_uart btqca btrtl btbcm btintel bluetooth ecdh_generic ecc rpcsec_gss_krb5 auth_rpcgss nfsv4 dns_resolver nfs lockd grace nfs_ssc fscache uinput snd_seq_dummy snd_hrtimer tun xt_CHECKSUM xt_MASQUERADE xt_conntrack ipt_REJECT nf_nat_tftp nf_conntrack_tftp bridge stp llc cmac ccm michael_mic nft_objref nf_conntrack_netbios_ns nf_conntrack_broadcast nft_fib_inet nft_fib_ipv4 nft_fib_ipv6 nft_fib nft_reject_inet nf_reject_ipv4 nf_reject_ipv6 nft_reject nft_ct nft_chain_nat ip6table_nat ip6table_mangle ip6table_raw ip6table_security iptable_nat nf_nat nf_conntrack nf_defrag_ipv6 nf_defrag_ipv4 iptable_mangle iptable_raw iptable_security ip_set nf_tables nfnetlink ip6table_filter ip6_tables iptable_filter sunrpc vfat fat uvcvideo videobuf2_vmalloc videobuf2_memops videobuf2_v4l2 videobuf2_common videodev mc qrtr_mhi snd_soc_skl_hda_dsp snd_soc_hdac_hdmi iTCO_wdt snd_soc_dmic snd_hda_codec_hdmi intel_pmc_bxt dell_laptop snd_hda_codec_realtek
[  291.607206]  iTCO_vendor_support intel_pmt_telemetry intel_rapl_msr intel_pmt_class x86_pkg_temp_thermal dell_smm_hwmon snd_hda_codec_generic intel_powerclamp snd_sof_pci snd_sof_intel_hda_common snd_sof_intel_hda snd_sof_intel_byt snd_sof_intel_ipc snd_sof snd_sof_xtensa_dsp snd_soc_hdac_hda snd_hda_ext_core snd_soc_acpi_intel_match snd_soc_acpi ledtrig_audio snd_hda_intel snd_intel_dspcfg soundwire_intel coretemp qrtr soundwire_generic_allocation ns kvm_intel ath11k_pci snd_soc_core ath11k kvm snd_compress snd_pcm_dmaengine soundwire_cadence snd_hda_codec qmi_helpers mac80211 snd_hda_core irqbypass intel_cstate ac97_bus intel_uncore snd_hwdep snd_seq snd_seq_device snd_pcm pcspkr dell_wmi cfg80211 dell_smbios dcdbas snd_timer dell_wmi_sysman wmi_bmof dell_wmi_descriptor snd i2c_i801 i2c_smbus soundcore rfkill mhi libarc4 joydev hid_sensor_als idma64 hid_sensor_trigger hid_sensor_iio_common industrialio_triggered_buffer kfifo_buf industrialio thunderbolt processor_thermal_device
[  291.607320]  processor_thermal_rfim processor_thermal_mbox processor_thermal_rapl intel_rapl_common intel_pmt intel_soc_dts_iosf ucsi_acpi typec_ucsi typec int3403_thermal int340x_thermal_zone acpi_tad int3400_thermal intel_hid acpi_thermal_rel sparse_keymap acpi_pad zram ip_tables hid_sensor_hub intel_ishtp_loader intel_ishtp_hid i915 hid_multitouch i2c_algo_bit drm_kms_helper cec rtsx_pci_sdmmc mmc_core nvme drm crct10dif_pclmul crc32_pclmul crc32c_intel ghash_clmulni_intel intel_ish_ipc rtsx_pci nvme_core serio_raw intel_ishtp wmi i2c_hid video pinctrl_tigerlake fuse ecryptfs
[  291.607393] CR2: ffffa672809f3047
[  291.607397] ---[ end trace 4a3d0c97b7782da0 ]---
[  291.607401] RIP: 0010:qca_download_firmware+0x231/0x490 [btqca]
[  291.607408] Code: 1b 75 04 80 48 0c 01 0f b7 c1 8d 54 02 0c 41 39 d7 0f 8e 99 fe ff ff 48 63 c2 4c 01 e8 0f b7 30 0f b7 48 02 66 83 fe 11 75 d3 <80> 48 0c 80 41 83 fc 03 7e 6f 44 88 70 0d eb cd 41 0f b6 45 0e 48
[  291.607412] RSP: 0018:ffffa67285c4bc60 EFLAGS: 00010246
[  291.607416] RAX: ffffa672809f303b RBX: 0000000000000005 RCX: 0000000000000006
[  291.607419] RDX: 0000000000000037 RSI: 0000000000000011 RDI: ffff88a80498bd20
[  291.607422] RBP: ffff88a804a2e000 R08: ffff88a9398126c0 R09: ffff88a80498bd20
[  291.607425] R10: 0000000000194e1f R11: 0000000000000000 R12: 0000000000000005
[  291.607428] R13: ffffa672809f3004 R14: 000000000000000e R15: 00000000000016a9
[  291.607431] FS:  0000000000000000(0000) GS:ffff88aeef600000(0000) knlGS:0000000000000000
[  291.607434] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
[  291.607437] CR2: ffffa672809f3047 CR3: 0000000448a10004 CR4: 0000000000770ef0
[  291.607441] PKRU: 55555554

From wgong at codeaurora.org  Mon May 17 21:19:23 2021
From: wgong at codeaurora.org (Wen Gong)
Date: Mon, 17 May 2021 16:19:23 -0400
Subject: [PATCH 0/9] cfg80211/mac80211: Add support for 6GHZ STA for various
 modes : LPI, SP and VLP
Message-ID: <20210517201932.8860-1-wgong@codeaurora.org>

It introduced some new concept:
power type of AP(STANDARD_POWER_AP, INDOOR_AP, VERY_LOW_POWER_AP)
power type of STATION(DEFAULT_CLIENT, SUBORDINATE_CLIENT)
power spectral density(psd)

This patchset for cfg80211/mac80211 is to add the definition of new
concept of 6G and add basic parse of IE(transmit power envelope
element) in beacon and save power spectral density(psd) reported
by lower-driver for 6G channel, the info will be passed to lower
driver when connecting to 6G AP.

Wen Gong (9):
  cfg80211: add power type definition for 6G Hz
  mac80211: add definition of regulatory info in 6G Hz operation
    information
  mac80211: add parse regulatory info in 6G Hz operation information
  cfg80211: add definition for 6G power spectral density(psd)
  cfg80211: save power spectral density(psd) of regulatory rule
  mac80211: add definition for transmit power envelope element
  mac80211: add parse transmit power envelope element
  mac80211: add transmit power envelope element and power constraint in
    bss_conf
  mac80211: save transmit power envelope element and power constraint

 include/linux/ieee80211.h    | 35 ++++++++++++++++++++++++++++++++++-
 include/net/cfg80211.h       |  7 +++++++
 include/net/mac80211.h       |  6 ++++++
 include/net/regulatory.h     |  1 +
 include/uapi/linux/nl80211.h | 32 ++++++++++++++++++++++++++++++++
 net/mac80211/ieee80211_i.h   |  3 +++
 net/mac80211/mlme.c          | 21 +++++++++++++++++++++
 net/mac80211/util.c          | 18 ++++++++++++++++++
 net/wireless/reg.c           | 14 ++++++++++++++
 9 files changed, 136 insertions(+), 1 deletion(-)

-- 
2.31.1



From wgong at codeaurora.org  Mon May 17 21:19:24 2021
From: wgong at codeaurora.org (Wen Gong)
Date: Mon, 17 May 2021 16:19:24 -0400
Subject: [PATCH 1/9] cfg80211: add power type definition for 6G Hz
In-Reply-To: <20210517201932.8860-1-wgong@codeaurora.org>
References: <20210517201932.8860-1-wgong@codeaurora.org>
Message-ID: <20210517201932.8860-2-wgong@codeaurora.org>

6GHz regulatory domains introduces different modes for 6GHz AP
operations Low Power Indoor(LPI), Standard Power(SP) and Very Low
Power(VLP). 6GHz STAs could be operated as either Regular or
Subordinate clients. This patch is define the flags for power type
of AP and STATION mode.

Signed-off-by: Wen Gong <wgong at codeaurora.org>
---
 include/net/cfg80211.h       |  2 ++
 include/uapi/linux/nl80211.h | 30 ++++++++++++++++++++++++++++++
 2 files changed, 32 insertions(+)

diff --git a/include/net/cfg80211.h b/include/net/cfg80211.h
index 911fae42b0c0..13d92c643794 100644
--- a/include/net/cfg80211.h
+++ b/include/net/cfg80211.h
@@ -675,6 +675,7 @@ struct key_params {
  *	chan will define the primary channel and all other
  *	parameters are ignored.
  * @freq1_offset: offset from @center_freq1, in KHz
+ * @power_type: power type of BSS for 6G
  */
 struct cfg80211_chan_def {
 	struct ieee80211_channel *chan;
@@ -683,6 +684,7 @@ struct cfg80211_chan_def {
 	u32 center_freq2;
 	struct ieee80211_edmg edmg;
 	u16 freq1_offset;
+	enum nl80211_ap_reg_power power_type;
 };
 
 /*
diff --git a/include/uapi/linux/nl80211.h b/include/uapi/linux/nl80211.h
index ac78da99fccd..9f8e9e49a16a 100644
--- a/include/uapi/linux/nl80211.h
+++ b/include/uapi/linux/nl80211.h
@@ -4085,6 +4085,36 @@ enum nl80211_dfs_regions {
 	NL80211_DFS_JP		= 3,
 };
 
+/**
+ * enum nl80211_ap_reg_power - regulatory power for a Access Point
+ *
+ * @NL80211_REG_UNSET_AP: Access Point has no regulatory power mode
+ * @NL80211_REG_LPI: Indoor Access Point
+ * @NL80211_REG_SP: Standard power Access Point
+ * @NL80211_REG_VLP: Very low power Access Point
+ */
+enum nl80211_ap_reg_power {
+	NL80211_REG_UNSET_AP,
+	NL80211_REG_LPI_AP,
+	NL80211_REG_SP_AP,
+	NL80211_REG_VLP_AP,
+	NL80211_REG_MAX_AP_TYPE = 3,
+};
+
+/**
+ * enum nl80211_client_reg_power - regulatory power for a client
+ *
+ * @NL80211_REG_UNSET_CLIENT: Client has no regulatory power mode
+ * @NL80211_REG_DEFAULT_CLIENT: Default Client
+ * @NL80211_REG_SUBORDINATE_CLIENT: Subordinate Client
+ */
+enum nl80211_client_reg_power {
+	NL80211_REG_UNSET_CLIENT,
+	NL80211_REG_DEFAULT_CLIENT,
+	NL80211_REG_SUBORDINATE_CLIENT,
+	NL80211_REG_MAX_CLIENT_TYPE = 2,
+};
+
 /**
  * enum nl80211_user_reg_hint_type - type of user regulatory hint
  *
-- 
2.31.1



From wgong at codeaurora.org  Mon May 17 21:19:25 2021
From: wgong at codeaurora.org (Wen Gong)
Date: Mon, 17 May 2021 16:19:25 -0400
Subject: [PATCH 2/9] mac80211: add definition of regulatory info in 6G Hz
 operation information
In-Reply-To: <20210517201932.8860-1-wgong@codeaurora.org>
References: <20210517201932.8860-1-wgong@codeaurora.org>
Message-ID: <20210517201932.8860-3-wgong@codeaurora.org>

IEEE P802.11ax?/D8.0 added regulatory info subfield in HE operation
element, this patch is to add it in mac80211 definition.

Signed-off-by: Wen Gong <wgong at codeaurora.org>
---
 include/linux/ieee80211.h | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/include/linux/ieee80211.h b/include/linux/ieee80211.h
index 3d8cf579745d..894a2c4d7cb7 100644
--- a/include/linux/ieee80211.h
+++ b/include/linux/ieee80211.h
@@ -2266,6 +2266,9 @@ ieee80211_he_ppe_size(u8 ppe_thres_hdr, const u8 *phy_cap_info)
 #define IEEE80211_HE_OPERATION_PARTIAL_BSS_COLOR		0x40000000
 #define IEEE80211_HE_OPERATION_BSS_COLOR_DISABLED		0x80000000
 
+#define IEEE80211_6GHZ_CTRL_REG_LPI_AP	0
+#define IEEE80211_6GHZ_CTRL_REG_SP_AP	1
+
 /**
  * ieee80211_he_6ghz_oper - HE 6 GHz operation Information field
  * @primary: primary channel
@@ -2282,6 +2285,7 @@ struct ieee80211_he_6ghz_oper {
 #define		IEEE80211_HE_6GHZ_OPER_CTRL_CHANWIDTH_80MHZ	2
 #define		IEEE80211_HE_6GHZ_OPER_CTRL_CHANWIDTH_160MHZ	3
 #define IEEE80211_HE_6GHZ_OPER_CTRL_DUP_BEACON	0x4
+#define IEEE80211_HE_6GHZ_OPER_CTRL_REG_INFO	0x38
 	u8 control;
 	u8 ccfs0;
 	u8 ccfs1;
-- 
2.31.1



From wgong at codeaurora.org  Mon May 17 21:19:27 2021
From: wgong at codeaurora.org (Wen Gong)
Date: Mon, 17 May 2021 16:19:27 -0400
Subject: [PATCH 4/9] cfg80211: add definition for 6G power spectral
 density(psd)
In-Reply-To: <20210517201932.8860-1-wgong@codeaurora.org>
References: <20210517201932.8860-1-wgong@codeaurora.org>
Message-ID: <20210517201932.8860-5-wgong@codeaurora.org>

6GHz regulatory domains introduces power spectral density(psd). This
patch is define the flags for psd.

Signed-off-by: Wen Gong <wgong at codeaurora.org>
---
 include/net/cfg80211.h       | 5 +++++
 include/net/regulatory.h     | 1 +
 include/uapi/linux/nl80211.h | 2 ++
 3 files changed, 8 insertions(+)

diff --git a/include/net/cfg80211.h b/include/net/cfg80211.h
index 13d92c643794..2f1769412fd6 100644
--- a/include/net/cfg80211.h
+++ b/include/net/cfg80211.h
@@ -107,6 +107,8 @@ struct wiphy;
  *	on this channel.
  * @IEEE80211_CHAN_16MHZ: 16 MHz bandwidth is permitted
  *	on this channel.
+ * @IEEE80211_CHAN_PSD: power spectral density (in dBm)
+ *	on this channel.
  *
  */
 enum ieee80211_channel_flags {
@@ -129,6 +131,7 @@ enum ieee80211_channel_flags {
 	IEEE80211_CHAN_4MHZ		= 1<<16,
 	IEEE80211_CHAN_8MHZ		= 1<<17,
 	IEEE80211_CHAN_16MHZ		= 1<<18,
+	IEEE80211_CHAN_PSD		= 1<<19,
 };
 
 #define IEEE80211_CHAN_NO_HT40 \
@@ -162,6 +165,7 @@ enum ieee80211_channel_flags {
  *	on this channel.
  * @dfs_state_entered: timestamp (jiffies) when the dfs state was entered.
  * @dfs_cac_ms: DFS CAC time in milliseconds, this is valid for DFS channels.
+ * @psd: power spectral density (in dBm)
  */
 struct ieee80211_channel {
 	enum nl80211_band band;
@@ -178,6 +182,7 @@ struct ieee80211_channel {
 	enum nl80211_dfs_state dfs_state;
 	unsigned long dfs_state_entered;
 	unsigned int dfs_cac_ms;
+	s8 psd;
 };
 
 /**
diff --git a/include/net/regulatory.h b/include/net/regulatory.h
index 47f06f6f5a67..ed20004fb6a9 100644
--- a/include/net/regulatory.h
+++ b/include/net/regulatory.h
@@ -221,6 +221,7 @@ struct ieee80211_reg_rule {
 	u32 flags;
 	u32 dfs_cac_ms;
 	bool has_wmm;
+	s8 psd;
 };
 
 struct ieee80211_regdomain {
diff --git a/include/uapi/linux/nl80211.h b/include/uapi/linux/nl80211.h
index 9f8e9e49a16a..b843ba0afad2 100644
--- a/include/uapi/linux/nl80211.h
+++ b/include/uapi/linux/nl80211.h
@@ -4040,6 +4040,7 @@ enum nl80211_sched_scan_match_attr {
  * @NL80211_RRF_NO_80MHZ: 80MHz operation not allowed
  * @NL80211_RRF_NO_160MHZ: 160MHz operation not allowed
  * @NL80211_RRF_NO_HE: HE operation not allowed
+ * @NL80211_RRF_PSD: channels has power spectral density value
  */
 enum nl80211_reg_rule_flags {
 	NL80211_RRF_NO_OFDM		= 1<<0,
@@ -4058,6 +4059,7 @@ enum nl80211_reg_rule_flags {
 	NL80211_RRF_NO_80MHZ		= 1<<15,
 	NL80211_RRF_NO_160MHZ		= 1<<16,
 	NL80211_RRF_NO_HE		= 1<<17,
+	NL80211_RRF_PSD		= 1<<18,
 };
 
 #define NL80211_RRF_PASSIVE_SCAN	NL80211_RRF_NO_IR
-- 
2.31.1



From wgong at codeaurora.org  Mon May 17 21:19:31 2021
From: wgong at codeaurora.org (Wen Gong)
Date: Mon, 17 May 2021 16:19:31 -0400
Subject: [PATCH 8/9] mac80211: add transmit power envelope element and power
 constraint in bss_conf
In-Reply-To: <20210517201932.8860-1-wgong@codeaurora.org>
References: <20210517201932.8860-1-wgong@codeaurora.org>
Message-ID: <20210517201932.8860-9-wgong@codeaurora.org>

This patch is to add definition of transmit power envelope element and
power constraint in struct ieee80211_bss_conf for 6GHz.

Signed-off-by: Wen Gong <wgong at codeaurora.org>
---
 include/net/mac80211.h | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/include/net/mac80211.h b/include/net/mac80211.h
index 2d1d629e5d14..1e9d3650fbc4 100644
--- a/include/net/mac80211.h
+++ b/include/net/mac80211.h
@@ -631,6 +631,9 @@ struct ieee80211_fils_discovery {
  * @s1g: BSS is S1G BSS (affects Association Request format).
  * @beacon_tx_rate: The configured beacon transmit rate that needs to be passed
  *	to driver when rate control is offloaded to firmware.
+ * @tx_pwr_env: transmit power envelope array of BSS.
+ * @tx_pwr_env_num: number of @tx_pwr_env.
+ * @pwr_reduction: power constraint of BSS.
  */
 struct ieee80211_bss_conf {
 	const u8 *bssid;
@@ -700,6 +703,9 @@ struct ieee80211_bss_conf {
 	u32 unsol_bcast_probe_resp_interval;
 	bool s1g;
 	struct cfg80211_bitrate_mask beacon_tx_rate;
+	struct ieee80211_tx_pwr_env tx_pwr_env[IEEE80211_TPE_MAX_IE_COUNT];
+	u8 tx_pwr_env_num;
+	u8 pwr_reduction;
 };
 
 /**
-- 
2.31.1



From wgong at codeaurora.org  Mon May 17 21:19:32 2021
From: wgong at codeaurora.org (Wen Gong)
Date: Mon, 17 May 2021 16:19:32 -0400
Subject: [PATCH 9/9] mac80211: save transmit power envelope element and power
 constraint
In-Reply-To: <20210517201932.8860-1-wgong@codeaurora.org>
References: <20210517201932.8860-1-wgong@codeaurora.org>
Message-ID: <20210517201932.8860-10-wgong@codeaurora.org>

This patch is to save the transmit power envelope element and power
constraint in struct ieee80211_bss_conf for 6GHz.

Signed-off-by: Wen Gong <wgong at codeaurora.org>
---
 net/mac80211/mlme.c | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/net/mac80211/mlme.c b/net/mac80211/mlme.c
index 2e33a1263518..5b02d78bd934 100644
--- a/net/mac80211/mlme.c
+++ b/net/mac80211/mlme.c
@@ -5076,6 +5076,27 @@ static int ieee80211_prep_channel(struct ieee80211_sub_if_data *sdata,
 		else
 			he_oper = NULL;
 
+		if (is_6ghz) {
+			struct ieee802_11_elems elems;
+			struct ieee80211_bss_conf *bss_conf;
+			u8 i, n;
+
+			ieee802_11_parse_elems(ies->data, ies->len, false, &elems,
+					       NULL, NULL);
+			bss_conf = &sdata->vif.bss_conf;
+			bss_conf->pwr_reduction = 0;
+			if (elems.pwr_constr_elem)
+				bss_conf->pwr_reduction = *elems.pwr_constr_elem;
+
+			memset(bss_conf->tx_pwr_env, 0, sizeof(bss_conf->tx_pwr_env));
+			bss_conf->tx_pwr_env_num = elems.tx_pwr_env_num;
+			n = min_t(u8, elems.tx_pwr_env_num,
+				  ARRAY_SIZE(elems.tx_pwr_env));
+			for (i = 0; i < n; i++)
+				memcpy(&bss_conf->tx_pwr_env[i], elems.tx_pwr_env[i],
+				       elems.tx_pwr_env_len[i]);
+		}
+
 		if (!ieee80211_verify_sta_he_mcs_support(sband, he_oper))
 			ifmgd->flags |= IEEE80211_STA_DISABLE_HE;
 	}
-- 
2.31.1



From wgong at codeaurora.org  Mon May 17 21:19:28 2021
From: wgong at codeaurora.org (Wen Gong)
Date: Mon, 17 May 2021 16:19:28 -0400
Subject: [PATCH 5/9] cfg80211: save power spectral density(psd) of regulatory
 rule
In-Reply-To: <20210517201932.8860-1-wgong@codeaurora.org>
References: <20210517201932.8860-1-wgong@codeaurora.org>
Message-ID: <20210517201932.8860-6-wgong@codeaurora.org>

The power spectral density(psd) of regulatory rule should be take
effect to the channels. This patch is to save the values to the
channel which has psd value.

Signed-off-by: Wen Gong <wgong at codeaurora.org>
---
 net/wireless/reg.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/net/wireless/reg.c b/net/wireless/reg.c
index 21536c48deec..270be66a8d3f 100644
--- a/net/wireless/reg.c
+++ b/net/wireless/reg.c
@@ -1583,6 +1583,8 @@ static u32 map_regdom_flags(u32 rd_flags)
 		channel_flags |= IEEE80211_CHAN_NO_160MHZ;
 	if (rd_flags & NL80211_RRF_NO_HE)
 		channel_flags |= IEEE80211_CHAN_NO_HE;
+	if (rd_flags & NL80211_RRF_PSD)
+		channel_flags |= IEEE80211_CHAN_PSD;
 	return channel_flags;
 }
 
@@ -1787,6 +1789,9 @@ static void handle_channel_single_rule(struct wiphy *wiphy,
 				chan->dfs_cac_ms = reg_rule->dfs_cac_ms;
 		}
 
+		if (chan->flags & IEEE80211_CHAN_PSD)
+			chan->psd = reg_rule->psd;
+
 		return;
 	}
 
@@ -1807,6 +1812,9 @@ static void handle_channel_single_rule(struct wiphy *wiphy,
 			chan->dfs_cac_ms = IEEE80211_DFS_MIN_CAC_TIME_MS;
 	}
 
+	if (chan->flags & IEEE80211_CHAN_PSD)
+		chan->psd = reg_rule->psd;
+
 	if (chan->orig_mpwr) {
 		/*
 		 * Devices that use REGULATORY_COUNTRY_IE_FOLLOW_POWER
@@ -1876,6 +1884,9 @@ static void handle_channel_adjacent_rules(struct wiphy *wiphy,
 							 rrule2->dfs_cac_ms);
 		}
 
+		if (chan->flags & IEEE80211_CHAN_PSD)
+			chan->psd = min_t(s8, rrule1->psd, rrule1->psd);
+
 		return;
 	}
 
@@ -2533,6 +2544,9 @@ static void handle_channel_custom(struct wiphy *wiphy,
 			chan->dfs_cac_ms = IEEE80211_DFS_MIN_CAC_TIME_MS;
 	}
 
+	if (chan->flags & IEEE80211_CHAN_PSD)
+		chan->psd = reg_rule->psd;
+
 	chan->max_power = chan->max_reg_power;
 }
 
-- 
2.31.1



From wgong at codeaurora.org  Mon May 17 21:19:29 2021
From: wgong at codeaurora.org (Wen Gong)
Date: Mon, 17 May 2021 16:19:29 -0400
Subject: [PATCH 6/9] mac80211: add definition for transmit power envelope
 element
In-Reply-To: <20210517201932.8860-1-wgong@codeaurora.org>
References: <20210517201932.8860-1-wgong@codeaurora.org>
Message-ID: <20210517201932.8860-7-wgong@codeaurora.org>

IEEE P802.11ax?/D8.0 have some change for  transmit power envelope
element. This patch to add the definition of it.

Signed-off-by: Wen Gong <wgong at codeaurora.org>
---
 include/linux/ieee80211.h | 31 ++++++++++++++++++++++++++++++-
 1 file changed, 30 insertions(+), 1 deletion(-)

diff --git a/include/linux/ieee80211.h b/include/linux/ieee80211.h
index 894a2c4d7cb7..a39b5fc1dffc 100644
--- a/include/linux/ieee80211.h
+++ b/include/linux/ieee80211.h
@@ -2292,6 +2292,35 @@ struct ieee80211_he_6ghz_oper {
 	u8 minrate;
 } __packed;
 
+#define IEEE80211_TPE_MAX_IE_COUNT	8
+#define IEEE80211_TPE_MAX_POWER_COUNT	8
+
+/* transmit power interpretation type of transmit power envelope element*/
+enum ieee80211_tx_power_intrpt_type {
+	IEEE80211_TPE_LOCAL_EIRP,
+	IEEE80211_TPE_LOCAL_EIRP_PSD,
+	IEEE80211_TPE_REG_CLIENT_EIRP,
+	IEEE80211_TPE_REG_CLIENT_EIRP_PSD,
+};
+
+/**
+ * struct ieee80211_tx_pwr_env
+ *
+ * This structure represents the "Transmit Power Envelope element"
+ */
+struct ieee80211_tx_pwr_env {
+	u8 tx_power_info;
+	s8 tx_power[IEEE80211_TPE_MAX_POWER_COUNT];
+} __packed;
+
+#define TX_PWR_ENV_INFO_COUNT	GENMASK(2, 0)
+#define TX_PWR_ENV_INFO_INTERPRET	GENMASK(5, 3)
+#define TX_PWR_ENV_INFO_CATEGORY	GENMASK(7, 6)
+
+#define GET_TX_PWR_ENV_COUNT(fv) FIELD_GET(TX_PWR_ENV_INFO_COUNT, fv)
+#define GET_TX_PWR_ENV_INTERPRET(fv) FIELD_GET(TX_PWR_ENV_INFO_INTERPRET, fv)
+#define GET_TX_PWR_ENV_CATEGORY(fv) FIELD_GET(TX_PWR_ENV_INFO_CATEGORY, fv)
+
 /*
  * ieee80211_he_oper_size - calculate 802.11ax HE Operations IE size
  * @he_oper_ie: byte data of the He Operations IE, stating from the byte
@@ -2873,7 +2902,7 @@ enum ieee80211_eid {
 	WLAN_EID_VHT_OPERATION = 192,
 	WLAN_EID_EXTENDED_BSS_LOAD = 193,
 	WLAN_EID_WIDE_BW_CHANNEL_SWITCH = 194,
-	WLAN_EID_VHT_TX_POWER_ENVELOPE = 195,
+	WLAN_EID_TX_POWER_ENVELOPE = 195,
 	WLAN_EID_CHANNEL_SWITCH_WRAPPER = 196,
 	WLAN_EID_AID = 197,
 	WLAN_EID_QUIET_CHANNEL = 198,
-- 
2.31.1



From wgong at codeaurora.org  Mon May 17 21:19:26 2021
From: wgong at codeaurora.org (Wen Gong)
Date: Mon, 17 May 2021 16:19:26 -0400
Subject: [PATCH 3/9] mac80211: add parse regulatory info in 6G Hz operation
 information
In-Reply-To: <20210517201932.8860-1-wgong@codeaurora.org>
References: <20210517201932.8860-1-wgong@codeaurora.org>
Message-ID: <20210517201932.8860-4-wgong@codeaurora.org>

This patch is to convert the regulatory info subfield in HE operation
element to power type and save in struct cfg80211_chan_def.

Signed-off-by: Wen Gong <wgong at codeaurora.org>
---
 net/mac80211/util.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/net/mac80211/util.c b/net/mac80211/util.c
index f080fcf60e45..f58136e844a7 100644
--- a/net/mac80211/util.c
+++ b/net/mac80211/util.c
@@ -3405,6 +3405,16 @@ bool ieee80211_chandef_he_6ghz_oper(struct ieee80211_sub_if_data *sdata,
 					      NL80211_BAND_6GHZ);
 	he_chandef.chan = ieee80211_get_channel(sdata->local->hw.wiphy, freq);
 
+	switch (u8_get_bits(he_6ghz_oper->control,
+			    IEEE80211_HE_6GHZ_OPER_CTRL_REG_INFO)) {
+	case IEEE80211_6GHZ_CTRL_REG_LPI_AP:
+		he_chandef.power_type = NL80211_REG_LPI_AP;
+		break;
+	case IEEE80211_6GHZ_CTRL_REG_SP_AP:
+		he_chandef.power_type = NL80211_REG_SP_AP;
+		break;
+	}
+
 	switch (u8_get_bits(he_6ghz_oper->control,
 			    IEEE80211_HE_6GHZ_OPER_CTRL_CHANWIDTH)) {
 	case IEEE80211_HE_6GHZ_OPER_CTRL_CHANWIDTH_20MHZ:
-- 
2.31.1



From wgong at codeaurora.org  Mon May 17 21:19:30 2021
From: wgong at codeaurora.org (Wen Gong)
Date: Mon, 17 May 2021 16:19:30 -0400
Subject: [PATCH 7/9] mac80211: add parse transmit power envelope element
In-Reply-To: <20210517201932.8860-1-wgong@codeaurora.org>
References: <20210517201932.8860-1-wgong@codeaurora.org>
Message-ID: <20210517201932.8860-8-wgong@codeaurora.org>

This patch is to add the transmit power envelope element parse in
_ieee802_11_parse_elems_crc(), it maybe have more than one transmit
power envelope element in a beacon.

Signed-off-by: Wen Gong <wgong at codeaurora.org>
---
 net/mac80211/ieee80211_i.h | 3 +++
 net/mac80211/util.c        | 8 ++++++++
 2 files changed, 11 insertions(+)

diff --git a/net/mac80211/ieee80211_i.h b/net/mac80211/ieee80211_i.h
index ecda126a7026..22220e8dfdc7 100644
--- a/net/mac80211/ieee80211_i.h
+++ b/net/mac80211/ieee80211_i.h
@@ -1507,6 +1507,7 @@ struct ieee802_11_elems {
 	const struct ieee80211_he_spr *he_spr;
 	const struct ieee80211_mu_edca_param_set *mu_edca_param_set;
 	const struct ieee80211_he_6ghz_capa *he_6ghz_capa;
+	const struct ieee80211_tx_pwr_env *tx_pwr_env[IEEE80211_TPE_MAX_IE_COUNT];
 	const u8 *uora_element;
 	const u8 *mesh_id;
 	const u8 *peering;
@@ -1557,6 +1558,8 @@ struct ieee802_11_elems {
 	u8 perr_len;
 	u8 country_elem_len;
 	u8 bssid_index_len;
+	u8 tx_pwr_env_len[IEEE80211_TPE_MAX_IE_COUNT];
+	u8 tx_pwr_env_num;
 
 	/* whether a parse error occurred while retrieving these elements */
 	bool parse_error;
diff --git a/net/mac80211/util.c b/net/mac80211/util.c
index f58136e844a7..585d2eeb4470 100644
--- a/net/mac80211/util.c
+++ b/net/mac80211/util.c
@@ -1344,6 +1344,14 @@ _ieee802_11_parse_elems_crc(const u8 *start, size_t len, bool action,
 			elems->rsnx = pos;
 			elems->rsnx_len = elen;
 			break;
+		case WLAN_EID_TX_POWER_ENVELOPE:
+			if (elems->tx_pwr_env_num >= ARRAY_SIZE(elems->tx_pwr_env))
+				break;
+
+			elems->tx_pwr_env[elems->tx_pwr_env_num] = (void *)pos;
+			elems->tx_pwr_env_len[elems->tx_pwr_env_num] = elen;
+			elems->tx_pwr_env_num++;
+			break;
 		case WLAN_EID_EXTENSION:
 			ieee80211_parse_extension_element(calc_crc ?
 								&crc : NULL,
-- 
2.31.1



From wgong at codeaurora.org  Wed May 19 05:14:56 2021
From: wgong at codeaurora.org (Wen Gong)
Date: Wed, 19 May 2021 12:14:56 +0800
Subject: ath11k: qca6390 firmware crashes while connecting to 160 MHz
 channel
In-Reply-To: <871rcz9m9j.fsf@codeaurora.org>
References: <87blew3e4q.fsf@codeaurora.org> <87blew3e4q.fsf@codeaurora.org>
 <054ddea6-639e-c21e-d404-d551c65128df@justinmp.com>
 <920c8cc9-21fb-b7aa-4b49-be7656fb14b5@justinmp.com>
 <f776233a-0ed6-1ebc-3d68-be4a88514736@justinmp.com>
 <874kkfozhp.fsf@codeaurora.org>
 <a170a87b-072d-dc8e-6833-231e0df5b23c@justinmp.com>
 <875z2yuafn.fsf_-_@codeaurora.org>
 <5fd39674-d513-c28e-5469-693d96e804c0@justinmp.com>
 <87k0rdste7.fsf@codeaurora.org>
 <ed6c2f2b-3f47-007f-9bdd-135514121aa5@justinmp.com>
 <af78423479f82ae460541ee3ab737121@codeaurora.org>
 <87czwj9umb.fsf@codeaurora.org>
 <ae28fa90b517a293d0a61278ceb834db@codeaurora.org>
 <871rcz9m9j.fsf@codeaurora.org>
Message-ID: <27c2bb587c61c7577aec462420e14986@codeaurora.org>

On 2021-03-01 18:55, Kalle Valo wrote:
> Wen Gong <wgong at codeaurora.org> writes:
> 
>> On 2021-03-01 15:54, Kalle Valo wrote:
>>> Wen Gong <wgong at codeaurora.org> writes:
>>> 
>>>> On 2021-02-14 02:36, Justin Mazzola Paluska wrote:
>>>>> On 2/12/21 1:16 AM, Kalle Valo wrote:
>>>>>> Justin Mazzola Paluska <jmp at justinmp.com> writes:
>>>>>> 
>>>>>>> On 2/11/21 6:10 AM, Kalle Valo wrote:
>>>>>>>> (changing the title to find this easier)
>>>>>>>> 
>>>>>>>> Justin Mazzola Paluska <jmp at justinmp.com> writes:
>>>>>>>> 
>>>>>>>>> On 12/21/20 12:11 PM, Kalle Valo wrote:
>>>>>>>>>>> My router supports 160 MHz channels in the 5 GHz bands [1].? 
>>>>>>>>>>> I
>>>>>>>>>>> switched the router to advertising 80 MHz channels and the
>>>>>>>>>>> card could
>>>>>>>>>>> connect.
>>>>>>>>>> Thanks for the detailed debugging, this should help us
>>>>>>>>>> reproducing the
>>>>>>>>>> problem. What's the exact openwrt version you are using?
>>>>>>>>> The OpenWRT version is:
>>>>>>>>> 
>>>>>>>>> OpenWrt 19.07.5 r11257-5090152ae3 / LuCI openwrt-19.07 branch
>>>>>>>>> git-20.341.57626-51f55b5
>>>>>>>>> 
>>>>>>>>> (This is the latest stable release.)
>>>>>>>> Thanks. I got a report that this might be due to commit
>>>>>>>> 3579994476b6
>>>>>>>> ("wireless: fix wrong 160/80+80 MHz setting"). Can you try
>>>>>>>> reverting the
>>>>>>>> commit just to confirm we are seeing the same issue?
>>>>>>> I will try over the weekend.? Shall I still use the
>>>>>>> ath11k-qca6390-bringup branch or something else?? (I'm still
>>>>>>> running
>>>>>>> the ath11k-qca6390-bringup branch on my laptop).
>>>>>> Yes, use the same branch. Least amount of changes that way.
>>>>> 
>>>>> I reverted 3579994476b6 and re-enabled 160 MHz channels on my
>>>>> router.?
>>>>> I was able to connect to my router using the 5 GHz band at 80 MHz 
>>>>> (as
>>>>> expected).
>>>>> 
>>>>> It seems that reverting 3579994476b6 fixed the firmware crash with
>>>>> 160
>>>>> MHz channels!
>>>>> 
>>>>> I'll leave my router in 160 MHz mode for a while to see if there 
>>>>> are
>>>>> any problems that crop up over time.
>>>> 
>>>> Does anyone trying revert this patch(3579994476b6 wireless: fix 
>>>> wrong
>>>> 160/80+80 MHz setting) upstream?
>>> 
>>> Yes, Justin reports above that he reverted commit 3579994476b6 and 
>>> the
>>> firmware did not crash after that.
>> 
>> I know that. Has someone sent patch to revert it in public?
> 
> I don't recall seeing any reverts for this.
Does the qca6390 firmware crashes issue fixed now in upstream?
I see this patch(3579994476b6 wireless: fix wrong 160/80+80 MHz setting) 
not revert in upstream.


From wgong at codeaurora.org  Wed May 19 08:23:08 2021
From: wgong at codeaurora.org (Wen Gong)
Date: Wed, 19 May 2021 15:23:08 +0800
Subject: [PATCH] wireless: fix wrong 160/80+80 MHz setting
In-Reply-To: <20200826143139.25976-1-shay.bar@celeno.com>
References: <20200826143139.25976-1-shay.bar@celeno.com>
Message-ID: <dbf4ca6dc2b49b55d7272e4d8eba94db@codeaurora.org>

On 2020-08-26 22:31, Shay Bar wrote:
> Fix cfg80211_chandef_usable():
> consider IEEE80211_VHT_CAP_EXT_NSS_BW when verifying 160/80+80 MHz.
> 
> Based on:
> "Table 9-272 ? Setting of the Supported Channel Width Set subfield and
> Extended NSS BW
> Support subfield at a STA transmitting the VHT Capabilities Information 
> field"
> From "Draft P802.11REVmd_D3.0.pdf"
> 
> Signed-off-by: Aviad Brikman <aviad.brikman at celeno.com>
> Signed-off-by: Shay Bar <shay.bar at celeno.com>
> ---
>  net/wireless/chan.c | 15 ++++++++++++---
>  1 file changed, 12 insertions(+), 3 deletions(-)
> 
> diff --git a/net/wireless/chan.c b/net/wireless/chan.c
> index 90f0f82cd9ca..a51d11d3be33 100644
> --- a/net/wireless/chan.c
> +++ b/net/wireless/chan.c
> @@ -912,6 +912,7 @@ bool cfg80211_chandef_usable(struct wiphy *wiphy,
>         struct ieee80211_sta_vht_cap *vht_cap;
>         struct ieee80211_edmg *edmg_cap;
>         u32 width, control_freq, cap;
> +       bool support_80_80 = false;
> 
>         if (WARN_ON(!cfg80211_chandef_valid(chandef)))
>                 return false;
> @@ -979,9 +980,16 @@ bool cfg80211_chandef_usable(struct wiphy *wiphy,
>                         return false;
>                 break;
>         case NL80211_CHAN_WIDTH_80P80:
> -               cap = vht_cap->cap & 
> IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_MASK;
> +               cap = vht_cap->cap;
> +               support_80_80 =
> +                       ((cap &
> +                         
> IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160_80PLUS80MHZ) ||
> +                       (cap & IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ 
> &&
> +                        cap & IEEE80211_VHT_CAP_EXT_NSS_BW_MASK) ||
> +                       ((cap & IEEE80211_VHT_CAP_EXT_NSS_BW_MASK) >>
> +                                   IEEE80211_VHT_CAP_EXT_NSS_BW_SHIFT 
> > 1));
>                 if (chandef->chan->band != NL80211_BAND_6GHZ &&
> -                   cap != 
> IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160_80PLUS80MHZ)
> +                   !support_80_80)
>                         return false;
>                 /* fall through */
>         case NL80211_CHAN_WIDTH_80:
> @@ -1001,7 +1009,8 @@ bool cfg80211_chandef_usable(struct wiphy *wiphy,
>                         return false;
>                 cap = vht_cap->cap & 
> IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_MASK;
>                 if (cap != IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ &&
> -                   cap != 
> IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160_80PLUS80MHZ)
> +                   cap != 
> IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160_80PLUS80MHZ &&
> +                   !(vht_cap->cap & 
> IEEE80211_VHT_CAP_EXT_NSS_BW_MASK))
>                         return false;
in Table 9-251?Supported VHT-MCS and NSS Set subfields, it has Subfield 
VHT Extended
NSS BW Capable, its Definition is:
Indicates whether the STA is capable of
interpreting the Extended NSS BW
Support subfield of the VHT Capabilities
Information field

so it should check the Subfield VHT Extended NSS BW Capable in 
vht_cap->vht_mcs firstly, if
it is 0, then not allowed to check IEEE80211_VHT_CAP_EXT_NSS_BW_MASK of 
vht_cap->cap.
please correct me if wrong.

>                 break;
>         default:
> --
> 2.17.1
> 
> ________________________________
> The information transmitted is intended only for the person or entity
> to which it is addressed and may contain confidential and/or
> privileged material. Any retransmission, dissemination, copying or
> other use of, or taking of any action in reliance upon this
> information is prohibited. If you received this in error, please
> contact the sender and delete the material from any computer. Nothing
> contained herein shall be deemed as a representation, warranty or a
> commitment by Celeno. No warranties are expressed or implied,
> including, but not limited to, any implied warranties of
> non-infringement, merchantability and fitness for a particular
> purpose.
> ________________________________


From wgong at codeaurora.org  Thu May 20 04:40:21 2021
From: wgong at codeaurora.org (Wen Gong)
Date: Wed, 19 May 2021 23:40:21 -0400
Subject: [PATCH] wireless: add check of field VHT Extended NSS BW Capable for
 160/80+80 MHz setting
Message-ID: <20210520034021.14690-1-wgong@codeaurora.org>

Table 9-251?Supported VHT-MCS and NSS Set subfields, it has subfield VHT Extended
NSS BW Capable, its definition is:
Indicates whether the STA is capable of interpreting the Extended NSS BW
Support subfield of the VHT Capabilities Information field.

This patch is to add check for the subfield.

Signed-off-by: Wen Gong <wgong at codeaurora.org>
---
 net/wireless/chan.c | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/net/wireless/chan.c b/net/wireless/chan.c
index 285b8076054b..f7f86bd75cc0 100644
--- a/net/wireless/chan.c
+++ b/net/wireless/chan.c
@@ -942,7 +942,7 @@ bool cfg80211_chandef_usable(struct wiphy *wiphy,
 	struct ieee80211_sta_vht_cap *vht_cap;
 	struct ieee80211_edmg *edmg_cap;
 	u32 width, control_freq, cap;
-	bool support_80_80 = false;
+	bool ext_nss_cap, support_80_80 = false;
 
 	if (WARN_ON(!cfg80211_chandef_valid(chandef)))
 		return false;
@@ -950,6 +950,7 @@ bool cfg80211_chandef_usable(struct wiphy *wiphy,
 	ht_cap = &wiphy->bands[chandef->chan->band]->ht_cap;
 	vht_cap = &wiphy->bands[chandef->chan->band]->vht_cap;
 	edmg_cap = &wiphy->bands[chandef->chan->band]->edmg_cap;
+	ext_nss_cap = vht_cap->vht_mcs.tx_highest & IEEE80211_VHT_EXT_NSS_BW_CAPABLE;
 
 	if (edmg_cap->channels &&
 	    !cfg80211_edmg_usable(wiphy,
@@ -1015,7 +1016,8 @@ bool cfg80211_chandef_usable(struct wiphy *wiphy,
 			(cap & IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160_80PLUS80MHZ) ||
 			(cap & IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ &&
 			 cap & IEEE80211_VHT_CAP_EXT_NSS_BW_MASK) ||
-			u32_get_bits(cap, IEEE80211_VHT_CAP_EXT_NSS_BW_MASK) > 1;
+			(ext_nss_cap &&
+			 u32_get_bits(cap, IEEE80211_VHT_CAP_EXT_NSS_BW_MASK) > 1);
 		if (chandef->chan->band != NL80211_BAND_6GHZ && !support_80_80)
 			return false;
 		fallthrough;
@@ -1037,7 +1039,7 @@ bool cfg80211_chandef_usable(struct wiphy *wiphy,
 		cap = vht_cap->cap & IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_MASK;
 		if (cap != IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ &&
 		    cap != IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160_80PLUS80MHZ &&
-		    !(vht_cap->cap & IEEE80211_VHT_CAP_EXT_NSS_BW_MASK))
+		    !(ext_nss_cap && vht_cap->cap & IEEE80211_VHT_CAP_EXT_NSS_BW_MASK))
 			return false;
 		break;
 	default:
-- 
2.31.1



From kvalo at codeaurora.org  Thu May 20 10:47:53 2021
From: kvalo at codeaurora.org (Kalle Valo)
Date: Thu, 20 May 2021 12:47:53 +0300
Subject: [regressions] ath11k: v5.12.3 mhi regression
Message-ID: <87v97dhh2u.fsf@codeaurora.org>

Hi,

I got several reports that this mhi commit broke ath11k in v5.12.3:

commit 29b9829718c5e9bd68fc1c652f5e0ba9b9a64fed
Author: Bhaumik Bhatt <bbhatt at codeaurora.org>
Date:   Wed Feb 24 15:23:04 2021 -0800

    bus: mhi: core: Process execution environment changes serially
    
    [ Upstream commit ef2126c4e2ea2b92f543fae00a2a0332e4573c48 ]

Here are the reports:

https://bugzilla.kernel.org/show_bug.cgi?id=213055

https://bugzilla.kernel.org/show_bug.cgi?id=212187

https://bugs.archlinux.org/task/70849?project=1&string=linux

Interestingly v5.13-rc1 seems to work fine, at least for me, though I
have not tested v5.12.3 myself. Can someone revert this commit in the
stable release so that people get their wifi working again, please?

-- 
https://patchwork.kernel.org/project/linux-wireless/list/

https://wireless.wiki.kernel.org/en/developers/documentation/submittingpatches


From gregkh at linuxfoundation.org  Thu May 20 11:02:40 2021
From: gregkh at linuxfoundation.org (Greg KH)
Date: Thu, 20 May 2021 12:02:40 +0200
Subject: [regressions] ath11k: v5.12.3 mhi regression
In-Reply-To: <87v97dhh2u.fsf@codeaurora.org>
References: <87v97dhh2u.fsf@codeaurora.org>
Message-ID: <YKYzwBJNTy4Czd1A@kroah.com>

On Thu, May 20, 2021 at 12:47:53PM +0300, Kalle Valo wrote:
> Hi,
> 
> I got several reports that this mhi commit broke ath11k in v5.12.3:
> 
> commit 29b9829718c5e9bd68fc1c652f5e0ba9b9a64fed
> Author: Bhaumik Bhatt <bbhatt at codeaurora.org>
> Date:   Wed Feb 24 15:23:04 2021 -0800
> 
>     bus: mhi: core: Process execution environment changes serially
>     
>     [ Upstream commit ef2126c4e2ea2b92f543fae00a2a0332e4573c48 ]
> 
> Here are the reports:
> 
> https://bugzilla.kernel.org/show_bug.cgi?id=213055
> 
> https://bugzilla.kernel.org/show_bug.cgi?id=212187
> 
> https://bugs.archlinux.org/task/70849?project=1&string=linux
> 
> Interestingly v5.13-rc1 seems to work fine, at least for me, though I
> have not tested v5.12.3 myself. Can someone revert this commit in the
> stable release so that people get their wifi working again, please?

How does the mhi bus code relate to a ath11k driver?  What bus is that
on?

This seems odd...

greg k-h


From manivannan.sadhasivam at linaro.org  Thu May 20 11:43:13 2021
From: manivannan.sadhasivam at linaro.org (Manivannan Sadhasivam)
Date: Thu, 20 May 2021 16:13:13 +0530
Subject: [regressions] ath11k: v5.12.3 mhi regression
In-Reply-To: <YKYzwBJNTy4Czd1A@kroah.com>
References: <87v97dhh2u.fsf@codeaurora.org>
 <YKYzwBJNTy4Czd1A@kroah.com>
Message-ID: <20210520104313.GA128703@thinkpad>

On Thu, May 20, 2021 at 12:02:40PM +0200, Greg KH wrote:
> On Thu, May 20, 2021 at 12:47:53PM +0300, Kalle Valo wrote:
> > Hi,
> > 
> > I got several reports that this mhi commit broke ath11k in v5.12.3:
> > 
> > commit 29b9829718c5e9bd68fc1c652f5e0ba9b9a64fed
> > Author: Bhaumik Bhatt <bbhatt at codeaurora.org>
> > Date:   Wed Feb 24 15:23:04 2021 -0800
> > 
> >     bus: mhi: core: Process execution environment changes serially
> >     
> >     [ Upstream commit ef2126c4e2ea2b92f543fae00a2a0332e4573c48 ]
> > 
> > Here are the reports:
> > 
> > https://bugzilla.kernel.org/show_bug.cgi?id=213055
> > 
> > https://bugzilla.kernel.org/show_bug.cgi?id=212187
> > 
> > https://bugs.archlinux.org/task/70849?project=1&string=linux
> > 
> > Interestingly v5.13-rc1 seems to work fine, at least for me, though I
> > have not tested v5.12.3 myself. Can someone revert this commit in the
> > stable release so that people get their wifi working again, please?
> 
> How does the mhi bus code relate to a ath11k driver?  What bus is that
> on?
> 

MHI is the transport used by the ath11k driver to work with the WLAN devices
over PCIe.

Regarding the bug, I'd suggest to wait for Bhaumik (the author of 29b9829718c5)
to comment on the possible commit which needs backporting from mainline.

Thanks,
Mani

> This seems odd...
> 
> greg k-h


From kvalo at codeaurora.org  Thu May 20 13:36:00 2021
From: kvalo at codeaurora.org (Kalle Valo)
Date: Thu, 20 May 2021 15:36:00 +0300
Subject: [regressions] ath11k: v5.12.3 mhi regression
In-Reply-To: <20210520104313.GA128703@thinkpad> (Manivannan Sadhasivam's
 message of "Thu, 20 May 2021 16:13:13 +0530")
References: <87v97dhh2u.fsf@codeaurora.org> <YKYzwBJNTy4Czd1A@kroah.com>
 <20210520104313.GA128703@thinkpad>
Message-ID: <87r1i1h9an.fsf@codeaurora.org>

Manivannan Sadhasivam <manivannan.sadhasivam at linaro.org> writes:

> On Thu, May 20, 2021 at 12:02:40PM +0200, Greg KH wrote:
>> On Thu, May 20, 2021 at 12:47:53PM +0300, Kalle Valo wrote:
>> > Hi,
>> > 
>> > I got several reports that this mhi commit broke ath11k in v5.12.3:
>> > 
>> > commit 29b9829718c5e9bd68fc1c652f5e0ba9b9a64fed
>> > Author: Bhaumik Bhatt <bbhatt at codeaurora.org>
>> > Date:   Wed Feb 24 15:23:04 2021 -0800
>> > 
>> >     bus: mhi: core: Process execution environment changes serially
>> >     
>> >     [ Upstream commit ef2126c4e2ea2b92f543fae00a2a0332e4573c48 ]
>> > 
>> > Here are the reports:
>> > 
>> > https://bugzilla.kernel.org/show_bug.cgi?id=213055
>> > 
>> > https://bugzilla.kernel.org/show_bug.cgi?id=212187
>> > 
>> > https://bugs.archlinux.org/task/70849?project=1&string=linux
>> > 
>> > Interestingly v5.13-rc1 seems to work fine, at least for me, though I
>> > have not tested v5.12.3 myself. Can someone revert this commit in the
>> > stable release so that people get their wifi working again, please?
>> 
>> How does the mhi bus code relate to a ath11k driver?  What bus is that
>> on?
>> 
>
> MHI is the transport used by the ath11k driver to work with the WLAN devices
> over PCIe.
>
> Regarding the bug, I'd suggest to wait for Bhaumik (the author of 29b9829718c5)
> to comment on the possible commit which needs backporting from mainline.

Ok, but if a quick fix is not available I think we should just revert
this in the stable releases. I also got a report that v5.11.21 is
broken:

https://bugzilla.kernel.org/show_bug.cgi?id=213055#c11

-- 
https://patchwork.kernel.org/project/linux-wireless/list/

https://wireless.wiki.kernel.org/en/developers/documentation/submittingpatches


From bbhatt at codeaurora.org  Thu May 20 18:38:12 2021
From: bbhatt at codeaurora.org (Bhaumik Bhatt)
Date: Thu, 20 May 2021 10:38:12 -0700
Subject: [regressions] ath11k: v5.12.3 mhi regression
In-Reply-To: <87r1i1h9an.fsf@codeaurora.org>
References: <87v97dhh2u.fsf@codeaurora.org> <YKYzwBJNTy4Czd1A@kroah.com>
 <20210520104313.GA128703@thinkpad> <87r1i1h9an.fsf@codeaurora.org>
Message-ID: <3e8bac3b02e3549a55b7c9b78b699965@codeaurora.org>

On 2021-05-20 05:36 AM, Kalle Valo wrote:
> Manivannan Sadhasivam <manivannan.sadhasivam at linaro.org> writes:
> 
>> On Thu, May 20, 2021 at 12:02:40PM +0200, Greg KH wrote:
>>> On Thu, May 20, 2021 at 12:47:53PM +0300, Kalle Valo wrote:
>>> > Hi,
>>> >
>>> > I got several reports that this mhi commit broke ath11k in v5.12.3:
>>> >
>>> > commit 29b9829718c5e9bd68fc1c652f5e0ba9b9a64fed
>>> > Author: Bhaumik Bhatt <bbhatt at codeaurora.org>
>>> > Date:   Wed Feb 24 15:23:04 2021 -0800
>>> >
>>> >     bus: mhi: core: Process execution environment changes serially
>>> >
>>> >     [ Upstream commit ef2126c4e2ea2b92f543fae00a2a0332e4573c48 ]
>>> >
>>> > Here are the reports:
>>> >
>>> > https://bugzilla.kernel.org/show_bug.cgi?id=213055
>>> >
>>> > https://bugzilla.kernel.org/show_bug.cgi?id=212187
>>> >
>>> > https://bugs.archlinux.org/task/70849?project=1&string=linux
>>> >
>>> > Interestingly v5.13-rc1 seems to work fine, at least for me, though I
>>> > have not tested v5.12.3 myself. Can someone revert this commit in the
>>> > stable release so that people get their wifi working again, please?
>>> 
>>> How does the mhi bus code relate to a ath11k driver?  What bus is 
>>> that
>>> on?
>>> 
>> 
>> MHI is the transport used by the ath11k driver to work with the WLAN 
>> devices
>> over PCIe.
>> 
>> Regarding the bug, I'd suggest to wait for Bhaumik (the author of 
>> 29b9829718c5)
>> to comment on the possible commit which needs backporting from 
>> mainline.
> 
> Ok, but if a quick fix is not available I think we should just revert
> this in the stable releases. I also got a report that v5.11.21 is
> broken:
> 
> https://bugzilla.kernel.org/show_bug.cgi?id=213055#c11

Please pick [1] as the dependency to [ Upstream commit 
ef2126c4e2ea2b92f543fae00a2a0332e4573c48 ].

That is missing in older kernels and did not get backported.
This explains why 5.13.x works.

Thanks,
Bhaumik
---
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora 
Forum,
a Linux Foundation Collaborative Project

[1] 
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/bus/mhi/core?h=v5.13-rc2&id=4884362f6977fc05cbec736625665241c0e0732f


From gregkh at linuxfoundation.org  Thu May 20 18:58:49 2021
From: gregkh at linuxfoundation.org (Greg KH)
Date: Thu, 20 May 2021 19:58:49 +0200
Subject: [regressions] ath11k: v5.12.3 mhi regression
In-Reply-To: <3e8bac3b02e3549a55b7c9b78b699965@codeaurora.org>
References: <87v97dhh2u.fsf@codeaurora.org> <YKYzwBJNTy4Czd1A@kroah.com>
 <20210520104313.GA128703@thinkpad> <87r1i1h9an.fsf@codeaurora.org>
 <3e8bac3b02e3549a55b7c9b78b699965@codeaurora.org>
Message-ID: <YKajWVPUSTzNVVm8@kroah.com>

On Thu, May 20, 2021 at 10:38:12AM -0700, Bhaumik Bhatt wrote:
> On 2021-05-20 05:36 AM, Kalle Valo wrote:
> > Manivannan Sadhasivam <manivannan.sadhasivam at linaro.org> writes:
> > 
> > > On Thu, May 20, 2021 at 12:02:40PM +0200, Greg KH wrote:
> > > > On Thu, May 20, 2021 at 12:47:53PM +0300, Kalle Valo wrote:
> > > > > Hi,
> > > > >
> > > > > I got several reports that this mhi commit broke ath11k in v5.12.3:
> > > > >
> > > > > commit 29b9829718c5e9bd68fc1c652f5e0ba9b9a64fed
> > > > > Author: Bhaumik Bhatt <bbhatt at codeaurora.org>
> > > > > Date:   Wed Feb 24 15:23:04 2021 -0800
> > > > >
> > > > >     bus: mhi: core: Process execution environment changes serially
> > > > >
> > > > >     [ Upstream commit ef2126c4e2ea2b92f543fae00a2a0332e4573c48 ]
> > > > >
> > > > > Here are the reports:
> > > > >
> > > > > https://bugzilla.kernel.org/show_bug.cgi?id=213055
> > > > >
> > > > > https://bugzilla.kernel.org/show_bug.cgi?id=212187
> > > > >
> > > > > https://bugs.archlinux.org/task/70849?project=1&string=linux
> > > > >
> > > > > Interestingly v5.13-rc1 seems to work fine, at least for me, though I
> > > > > have not tested v5.12.3 myself. Can someone revert this commit in the
> > > > > stable release so that people get their wifi working again, please?
> > > > 
> > > > How does the mhi bus code relate to a ath11k driver?  What bus
> > > > is that
> > > > on?
> > > > 
> > > 
> > > MHI is the transport used by the ath11k driver to work with the WLAN
> > > devices
> > > over PCIe.
> > > 
> > > Regarding the bug, I'd suggest to wait for Bhaumik (the author of
> > > 29b9829718c5)
> > > to comment on the possible commit which needs backporting from
> > > mainline.
> > 
> > Ok, but if a quick fix is not available I think we should just revert
> > this in the stable releases. I also got a report that v5.11.21 is
> > broken:
> > 
> > https://bugzilla.kernel.org/show_bug.cgi?id=213055#c11
> 
> Please pick [1] as the dependency to [ Upstream commit
> ef2126c4e2ea2b92f543fae00a2a0332e4573c48 ].

what is [1]???

What commit do I need to backport, a commit id would be nice...

thanks,

greg k-h


From bbhatt at codeaurora.org  Thu May 20 19:04:05 2021
From: bbhatt at codeaurora.org (Bhaumik Bhatt)
Date: Thu, 20 May 2021 11:04:05 -0700
Subject: [regressions] ath11k: v5.12.3 mhi regression
In-Reply-To: <YKajWVPUSTzNVVm8@kroah.com>
References: <87v97dhh2u.fsf@codeaurora.org> <YKYzwBJNTy4Czd1A@kroah.com>
 <20210520104313.GA128703@thinkpad> <87r1i1h9an.fsf@codeaurora.org>
 <3e8bac3b02e3549a55b7c9b78b699965@codeaurora.org>
 <YKajWVPUSTzNVVm8@kroah.com>
Message-ID: <608474b9b9feae5bd0616ad16d6d6bbd@codeaurora.org>

On 2021-05-20 10:58 AM, Greg KH wrote:
> On Thu, May 20, 2021 at 10:38:12AM -0700, Bhaumik Bhatt wrote:
>> On 2021-05-20 05:36 AM, Kalle Valo wrote:
>> > Manivannan Sadhasivam <manivannan.sadhasivam at linaro.org> writes:
>> >
>> > > On Thu, May 20, 2021 at 12:02:40PM +0200, Greg KH wrote:
>> > > > On Thu, May 20, 2021 at 12:47:53PM +0300, Kalle Valo wrote:
>> > > > > Hi,
>> > > > >
>> > > > > I got several reports that this mhi commit broke ath11k in v5.12.3:
>> > > > >
>> > > > > commit 29b9829718c5e9bd68fc1c652f5e0ba9b9a64fed
>> > > > > Author: Bhaumik Bhatt <bbhatt at codeaurora.org>
>> > > > > Date:   Wed Feb 24 15:23:04 2021 -0800
>> > > > >
>> > > > >     bus: mhi: core: Process execution environment changes serially
>> > > > >
>> > > > >     [ Upstream commit ef2126c4e2ea2b92f543fae00a2a0332e4573c48 ]
>> > > > >
>> > > > > Here are the reports:
>> > > > >
>> > > > > https://bugzilla.kernel.org/show_bug.cgi?id=213055
>> > > > >
>> > > > > https://bugzilla.kernel.org/show_bug.cgi?id=212187
>> > > > >
>> > > > > https://bugs.archlinux.org/task/70849?project=1&string=linux
>> > > > >
>> > > > > Interestingly v5.13-rc1 seems to work fine, at least for me, though I
>> > > > > have not tested v5.12.3 myself. Can someone revert this commit in the
>> > > > > stable release so that people get their wifi working again, please?
>> > > >
>> > > > How does the mhi bus code relate to a ath11k driver?  What bus
>> > > > is that
>> > > > on?
>> > > >
>> > >
>> > > MHI is the transport used by the ath11k driver to work with the WLAN
>> > > devices
>> > > over PCIe.
>> > >
>> > > Regarding the bug, I'd suggest to wait for Bhaumik (the author of
>> > > 29b9829718c5)
>> > > to comment on the possible commit which needs backporting from
>> > > mainline.
>> >
>> > Ok, but if a quick fix is not available I think we should just revert
>> > this in the stable releases. I also got a report that v5.11.21 is
>> > broken:
>> >
>> > https://bugzilla.kernel.org/show_bug.cgi?id=213055#c11
>> 
>> Please pick [1] as the dependency to [ Upstream commit
>> ef2126c4e2ea2b92f543fae00a2a0332e4573c48 ].
> 
> what is [1]???
> 
> What commit do I need to backport, a commit id would be nice...
> 
> thanks,
> 
> greg k-h
Sure Greg. Commit id is: 4884362f6977fc05cbec736625665241c0e0732f

Title of patch:
bus: mhi: core: Download AMSS image from appropriate function

It was supposed to be a link but not sure why it's not seen.

Thanks,
Bhaumik
---
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora 
Forum,
a Linux Foundation Collaborative Project


From gregkh at linuxfoundation.org  Thu May 20 19:17:31 2021
From: gregkh at linuxfoundation.org (Greg KH)
Date: Thu, 20 May 2021 20:17:31 +0200
Subject: [regressions] ath11k: v5.12.3 mhi regression
In-Reply-To: <608474b9b9feae5bd0616ad16d6d6bbd@codeaurora.org>
References: <87v97dhh2u.fsf@codeaurora.org> <YKYzwBJNTy4Czd1A@kroah.com>
 <20210520104313.GA128703@thinkpad> <87r1i1h9an.fsf@codeaurora.org>
 <3e8bac3b02e3549a55b7c9b78b699965@codeaurora.org>
 <YKajWVPUSTzNVVm8@kroah.com>
 <608474b9b9feae5bd0616ad16d6d6bbd@codeaurora.org>
Message-ID: <YKanuzzvDhztYxm/@kroah.com>

On Thu, May 20, 2021 at 11:04:05AM -0700, Bhaumik Bhatt wrote:
> On 2021-05-20 10:58 AM, Greg KH wrote:
> > On Thu, May 20, 2021 at 10:38:12AM -0700, Bhaumik Bhatt wrote:
> > > On 2021-05-20 05:36 AM, Kalle Valo wrote:
> > > > Manivannan Sadhasivam <manivannan.sadhasivam at linaro.org> writes:
> > > >
> > > > > On Thu, May 20, 2021 at 12:02:40PM +0200, Greg KH wrote:
> > > > > > On Thu, May 20, 2021 at 12:47:53PM +0300, Kalle Valo wrote:
> > > > > > > Hi,
> > > > > > >
> > > > > > > I got several reports that this mhi commit broke ath11k in v5.12.3:
> > > > > > >
> > > > > > > commit 29b9829718c5e9bd68fc1c652f5e0ba9b9a64fed
> > > > > > > Author: Bhaumik Bhatt <bbhatt at codeaurora.org>
> > > > > > > Date:   Wed Feb 24 15:23:04 2021 -0800
> > > > > > >
> > > > > > >     bus: mhi: core: Process execution environment changes serially
> > > > > > >
> > > > > > >     [ Upstream commit ef2126c4e2ea2b92f543fae00a2a0332e4573c48 ]
> > > > > > >
> > > > > > > Here are the reports:
> > > > > > >
> > > > > > > https://bugzilla.kernel.org/show_bug.cgi?id=213055
> > > > > > >
> > > > > > > https://bugzilla.kernel.org/show_bug.cgi?id=212187
> > > > > > >
> > > > > > > https://bugs.archlinux.org/task/70849?project=1&string=linux
> > > > > > >
> > > > > > > Interestingly v5.13-rc1 seems to work fine, at least for me, though I
> > > > > > > have not tested v5.12.3 myself. Can someone revert this commit in the
> > > > > > > stable release so that people get their wifi working again, please?
> > > > > >
> > > > > > How does the mhi bus code relate to a ath11k driver?  What bus
> > > > > > is that
> > > > > > on?
> > > > > >
> > > > >
> > > > > MHI is the transport used by the ath11k driver to work with the WLAN
> > > > > devices
> > > > > over PCIe.
> > > > >
> > > > > Regarding the bug, I'd suggest to wait for Bhaumik (the author of
> > > > > 29b9829718c5)
> > > > > to comment on the possible commit which needs backporting from
> > > > > mainline.
> > > >
> > > > Ok, but if a quick fix is not available I think we should just revert
> > > > this in the stable releases. I also got a report that v5.11.21 is
> > > > broken:
> > > >
> > > > https://bugzilla.kernel.org/show_bug.cgi?id=213055#c11
> > > 
> > > Please pick [1] as the dependency to [ Upstream commit
> > > ef2126c4e2ea2b92f543fae00a2a0332e4573c48 ].
> > 
> > what is [1]???
> > 
> > What commit do I need to backport, a commit id would be nice...
> > 
> > thanks,
> > 
> > greg k-h
> Sure Greg. Commit id is: 4884362f6977fc05cbec736625665241c0e0732f
> 
> Title of patch:
> bus: mhi: core: Download AMSS image from appropriate function
> 
> It was supposed to be a link but not sure why it's not seen.

Text email doesn't have links :)

Anyway, thanks, now queued up.

Also note, it's nice to write kernel commit ids as 4884362f6977 ("bus:
mhi: core: Download AMSS image from appropriate function") which is the
preferred way to reference them in a emails and commit logs.

thanks,

greg k-h


From arend.vanspriel at broadcom.com  Thu May 20 20:21:13 2021
From: arend.vanspriel at broadcom.com (Arend van Spriel)
Date: Thu, 20 May 2021 21:21:13 +0200
Subject: [PATCH] wireless: add check of field VHT Extended NSS BW Capable
 for 160/80+80 MHz setting
In-Reply-To: <20210520034021.14690-1-wgong@codeaurora.org>
References: <20210520034021.14690-1-wgong@codeaurora.org>
Message-ID: <fe1b7675-23ba-a86e-90db-de5803231e21@broadcom.com>

On 5/20/2021 5:40 AM, Wen Gong wrote:
> Table 9-251?Supported VHT-MCS and NSS Set subfields, it has subfield VHT Extended
> NSS BW Capable, its definition is:
> Indicates whether the STA is capable of interpreting the Extended NSS BW
> Support subfield of the VHT Capabilities Information field.
> 
> This patch is to add check for the subfield.

Almost looks good to me, but...

> Signed-off-by: Wen Gong <wgong at codeaurora.org>
> ---
>   net/wireless/chan.c | 8 +++++---
>   1 file changed, 5 insertions(+), 3 deletions(-)
> 
> diff --git a/net/wireless/chan.c b/net/wireless/chan.c
> index 285b8076054b..f7f86bd75cc0 100644
> --- a/net/wireless/chan.c
> +++ b/net/wireless/chan.c

[...]

> @@ -1037,7 +1039,7 @@ bool cfg80211_chandef_usable(struct wiphy *wiphy,
>   		cap = vht_cap->cap & IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_MASK;
>   		if (cap != IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ &&
>   		    cap != IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160_80PLUS80MHZ &&
> -		    !(vht_cap->cap & IEEE80211_VHT_CAP_EXT_NSS_BW_MASK))
> +		    !(ext_nss_cap && vht_cap->cap & IEEE80211_VHT_CAP_EXT_NSS_BW_MASK))

you should not mix logical and binary operators so add braces around the 
binary operation here.

Regards,
Arend

>   			return false;
>   		break;
>   	default:
> 


From wgong at codeaurora.org  Fri May 21 03:18:09 2021
From: wgong at codeaurora.org (Wen Gong)
Date: Thu, 20 May 2021 22:18:09 -0400
Subject: [PATCH v2] wireless: add check of field VHT Extended NSS BW Capable
 for 160/80+80 MHz setting
Message-ID: <20210521021809.23986-1-wgong@codeaurora.org>

Table 9-251?Supported VHT-MCS and NSS Set subfields, it has subfield VHT Extended
NSS BW Capable, its definition is:
Indicates whether the STA is capable of interpreting the Extended NSS BW
Support subfield of the VHT Capabilities Information field.

This patch is to add check for the subfield.

Signed-off-by: Wen Gong <wgong at codeaurora.org>
---
v2: change code style
 net/wireless/chan.c | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/net/wireless/chan.c b/net/wireless/chan.c
index 285b8076054b..e29562659ae5 100644
--- a/net/wireless/chan.c
+++ b/net/wireless/chan.c
@@ -942,7 +942,7 @@ bool cfg80211_chandef_usable(struct wiphy *wiphy,
 	struct ieee80211_sta_vht_cap *vht_cap;
 	struct ieee80211_edmg *edmg_cap;
 	u32 width, control_freq, cap;
-	bool support_80_80 = false;
+	bool ext_nss_cap, support_80_80 = false;
 
 	if (WARN_ON(!cfg80211_chandef_valid(chandef)))
 		return false;
@@ -950,6 +950,7 @@ bool cfg80211_chandef_usable(struct wiphy *wiphy,
 	ht_cap = &wiphy->bands[chandef->chan->band]->ht_cap;
 	vht_cap = &wiphy->bands[chandef->chan->band]->vht_cap;
 	edmg_cap = &wiphy->bands[chandef->chan->band]->edmg_cap;
+	ext_nss_cap = vht_cap->vht_mcs.tx_highest & IEEE80211_VHT_EXT_NSS_BW_CAPABLE;
 
 	if (edmg_cap->channels &&
 	    !cfg80211_edmg_usable(wiphy,
@@ -1015,7 +1016,8 @@ bool cfg80211_chandef_usable(struct wiphy *wiphy,
 			(cap & IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160_80PLUS80MHZ) ||
 			(cap & IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ &&
 			 cap & IEEE80211_VHT_CAP_EXT_NSS_BW_MASK) ||
-			u32_get_bits(cap, IEEE80211_VHT_CAP_EXT_NSS_BW_MASK) > 1;
+			(ext_nss_cap &&
+			 u32_get_bits(cap, IEEE80211_VHT_CAP_EXT_NSS_BW_MASK) > 1);
 		if (chandef->chan->band != NL80211_BAND_6GHZ && !support_80_80)
 			return false;
 		fallthrough;
@@ -1037,7 +1039,7 @@ bool cfg80211_chandef_usable(struct wiphy *wiphy,
 		cap = vht_cap->cap & IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_MASK;
 		if (cap != IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ &&
 		    cap != IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160_80PLUS80MHZ &&
-		    !(vht_cap->cap & IEEE80211_VHT_CAP_EXT_NSS_BW_MASK))
+		    !(ext_nss_cap && (vht_cap->cap & IEEE80211_VHT_CAP_EXT_NSS_BW_MASK)))
 			return false;
 		break;
 	default:
-- 
2.31.1



From wgong at codeaurora.org  Fri May 21 03:21:33 2021
From: wgong at codeaurora.org (Wen Gong)
Date: Fri, 21 May 2021 10:21:33 +0800
Subject: [PATCH] wireless: add check of field VHT Extended NSS BW Capable
 for 160/80+80 MHz setting
In-Reply-To: <fe1b7675-23ba-a86e-90db-de5803231e21@broadcom.com>
References: <20210520034021.14690-1-wgong@codeaurora.org>
 <fe1b7675-23ba-a86e-90db-de5803231e21@broadcom.com>
Message-ID: <2f580f80af0ec9b17068d80d42e666b9@codeaurora.org>

On 2021-05-21 03:21, Arend van Spriel wrote:
> On 5/20/2021 5:40 AM, Wen Gong wrote:
>> Table 9-251?Supported VHT-MCS and NSS Set subfields, it has subfield 
>> VHT Extended
>> NSS BW Capable, its definition is:
>> Indicates whether the STA is capable of interpreting the Extended NSS 
>> BW
>> Support subfield of the VHT Capabilities Information field.
>> 
>> This patch is to add check for the subfield.
> 
> Almost looks good to me, but...
> 
>> Signed-off-by: Wen Gong <wgong at codeaurora.org>
>> ---
>>   net/wireless/chan.c | 8 +++++---
>>   1 file changed, 5 insertions(+), 3 deletions(-)
>> 
>> diff --git a/net/wireless/chan.c b/net/wireless/chan.c
>> index 285b8076054b..f7f86bd75cc0 100644
>> --- a/net/wireless/chan.c
>> +++ b/net/wireless/chan.c
> 
> [...]
> 
>> @@ -1037,7 +1039,7 @@ bool cfg80211_chandef_usable(struct wiphy 
>> *wiphy,
>>   		cap = vht_cap->cap & IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_MASK;
>>   		if (cap != IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ &&
>>   		    cap != IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160_80PLUS80MHZ &&
>> -		    !(vht_cap->cap & IEEE80211_VHT_CAP_EXT_NSS_BW_MASK))
>> +		    !(ext_nss_cap && vht_cap->cap & 
>> IEEE80211_VHT_CAP_EXT_NSS_BW_MASK))
> 
> you should not mix logical and binary operators so add braces around
> the binary operation here.
priority of & is higher than &&, so it not need to add braces here.
however, i have sent patch v2 which added the braces.
https://lore.kernel.org/linux-wireless/20210521021809.23986-1-wgong at codeaurora.org/T/#u
> 
> Regards,
> Arend
> 
>>   			return false;
>>   		break;
>>   	default:
>> 


From manivannan.sadhasivam at linaro.org  Fri May 21 13:45:30 2021
From: manivannan.sadhasivam at linaro.org (Manivannan Sadhasivam)
Date: Fri, 21 May 2021 18:15:30 +0530
Subject: [PATCH] mhi: add MHI_STATE_M2 to resume success criteria
In-Reply-To: <20210420035339.282963-1-bqiang@codeaurora.org>
References: <20210420035339.282963-1-bqiang@codeaurora.org>
Message-ID: <20210521124530.GF70095@thinkpad>

Hi,

The patch subject should be,

"bus: mhi: Wait for M2 state during system resume"

We follow "bus: mhi:" prefix for all MHI patches. Also, the subject should
clearly portray what the patch is intend to do.

On Tue, Apr 20, 2021 at 11:53:39AM +0800, Baochen Qiang wrote:
> During system resume, mhi driver triggers M3->M0 transition and then waits

s/mhi driver/MHI host

> for target device to enter M0 state. Once done, the device queues a state
> change event into ctrl event ring and notify mhi dirver by raising an

s/notify/notifies and s/mhi dirver/MHI host. MHI driver is somewhat confusing
since we have the MHI device driver (QRTR etc...) as well. So just use MHI host
everywhere.

> interrupt, where a tasklet is scheduled to process this event. In most cases,
> the taklet is served timely and wait operation succeeds.
> 

s/taklet/tasklet

> However, there are cases where CPU is busy and can not serve this tasklet

a/can not/cannot

> for some time. Once delay goes long enough, the device moves itself to M1
> state and also interrupts mhi driver after inserting a new state change
> event to ctrl ring. Later CPU finally has time to process the ring, however
> there are two events in it now:
> 	1. for M3->M0 event, which is processed first as queued first,
> 	   tasklet handler updates device state to M0 and wakes up the task,
> 	   i.e., the mhi driver.
> 	2. for M0->M1 event, which is processed later, tasklet handler
> 	   triggers M1->M2 transition and updates device state to M2 directly,
> 	   then wakes up the mhi driver(if still sleeping on this wait queue).
> Note that although mhi driver has been woken up while processing the first
> event, it may still has no chance to run before the second event is processed.
> In other words, mhi driver has to keep waiting till timeout cause the M0 state
> has been missed.
> 
> kernel log here:
> ...
> Apr 15 01:45:14 test-NUC8i7HVK kernel: [ 4247.911251] mhi 0000:06:00.0: Entered with PM state: M3, MHI state: M3
> Apr 15 01:45:14 test-NUC8i7HVK kernel: [ 4247.917762] mhi 0000:06:00.0: State change event to state: M0
> Apr 15 01:45:14 test-NUC8i7HVK kernel: [ 4247.917767] mhi 0000:06:00.0: State change event to state: M1
> Apr 15 01:45:14 test-NUC8i7HVK kernel: [ 4338.788231] mhi 0000:06:00.0: Did not enter M0 state, MHI state: M2, PM state: M2
> ...
> 
> Fix this issue by simply adding M2 as a valid state for resume.
> 
> Tested-on: WCN6855 hw2.0 PCI WLAN.HSP.1.1-01720.1-QCAHSPSWPL_V1_V2_SILICONZ_LITE-1
> 
> Signed-off-by: Baochen Qiang <bqiang at codeaurora.org>

Could you please add a fixes tag as well? And this patch should be backported to
stable kernels also, so please CC stable at vger.kernel.org.

Thanks,
Mani

> ---
>  drivers/bus/mhi/core/pm.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/bus/mhi/core/pm.c b/drivers/bus/mhi/core/pm.c
> index ce73cfa63cb3..ca5f2feed9d5 100644
> --- a/drivers/bus/mhi/core/pm.c
> +++ b/drivers/bus/mhi/core/pm.c
> @@ -900,6 +900,7 @@ int mhi_pm_resume(struct mhi_controller *mhi_cntrl)
>  
>  	ret = wait_event_timeout(mhi_cntrl->state_event,
>  				 mhi_cntrl->dev_state == MHI_STATE_M0 ||
> +				 mhi_cntrl->dev_state == MHI_STATE_M2 ||
>  				 MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state),
>  				 msecs_to_jiffies(mhi_cntrl->timeout_ms));
>  
> -- 
> 2.25.1
> 


From manivannan.sadhasivam at linaro.org  Fri May 21 14:36:04 2021
From: manivannan.sadhasivam at linaro.org (Manivannan Sadhasivam)
Date: Fri, 21 May 2021 19:06:04 +0530
Subject: [PATCH v4 1/6] bus: mhi: core: Set BHI/BHIe offsets on power up
 preparation
In-Reply-To: <1620330705-40192-2-git-send-email-bbhatt@codeaurora.org>
References: <1620330705-40192-1-git-send-email-bbhatt@codeaurora.org>
 <1620330705-40192-2-git-send-email-bbhatt@codeaurora.org>
Message-ID: <20210521133604.GI70095@thinkpad>

On Thu, May 06, 2021 at 12:51:40PM -0700, Bhaumik Bhatt wrote:
> Set the BHI and/or BHIe offsets in mhi_prepare_for_power_up(),
> rearrange the function, and remove the equivalent from
> mhi_async_power_up(). This helps consolidate multiple checks
> in different parts of the driver and can help MHI fail early on
> before power up begins if the offsets are not read correctly.
> 
> Signed-off-by: Bhaumik Bhatt <bbhatt at codeaurora.org>
> Reviewed-by: Jeffrey Hugo <quic_jhugo at quicinc.com>
> Reviewed-by: Hemant Kumar <hemantk at codeaurora.org>

Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam at linaro.org>

Thanks,
Mani

> ---
>  drivers/bus/mhi/core/init.c | 42 +++++++++++++++++++++++-------------------
>  drivers/bus/mhi/core/pm.c   | 28 ++++------------------------
>  2 files changed, 27 insertions(+), 43 deletions(-)
> 
> diff --git a/drivers/bus/mhi/core/init.c b/drivers/bus/mhi/core/init.c
> index c81b377..11c7a3d 100644
> --- a/drivers/bus/mhi/core/init.c
> +++ b/drivers/bus/mhi/core/init.c
> @@ -1063,7 +1063,7 @@ EXPORT_SYMBOL_GPL(mhi_free_controller);
>  int mhi_prepare_for_power_up(struct mhi_controller *mhi_cntrl)
>  {
>  	struct device *dev = &mhi_cntrl->mhi_dev->dev;
> -	u32 bhie_off;
> +	u32 bhi_off, bhie_off;
>  	int ret;
>  
>  	mutex_lock(&mhi_cntrl->pm_mutex);
> @@ -1072,29 +1072,36 @@ int mhi_prepare_for_power_up(struct mhi_controller *mhi_cntrl)
>  	if (ret)
>  		goto error_dev_ctxt;
>  
> -	/*
> -	 * Allocate RDDM table if specified, this table is for debugging purpose
> -	 */
> -	if (mhi_cntrl->rddm_size) {
> -		mhi_alloc_bhie_table(mhi_cntrl, &mhi_cntrl->rddm_image,
> -				     mhi_cntrl->rddm_size);
> +	ret = mhi_read_reg(mhi_cntrl, mhi_cntrl->regs, BHIOFF, &bhi_off);
> +	if (ret) {
> +		dev_err(dev, "Error getting BHI offset\n");
> +		goto error_reg_offset;
> +	}
> +	mhi_cntrl->bhi = mhi_cntrl->regs + bhi_off;
>  
> -		/*
> -		 * This controller supports RDDM, so we need to manually clear
> -		 * BHIE RX registers since POR values are undefined.
> -		 */
> +	if (mhi_cntrl->fbc_download || mhi_cntrl->rddm_size) {
>  		ret = mhi_read_reg(mhi_cntrl, mhi_cntrl->regs, BHIEOFF,
>  				   &bhie_off);
>  		if (ret) {
>  			dev_err(dev, "Error getting BHIE offset\n");
> -			goto bhie_error;
> +			goto error_reg_offset;
>  		}
> -
>  		mhi_cntrl->bhie = mhi_cntrl->regs + bhie_off;
> +	}
> +
> +	if (mhi_cntrl->rddm_size) {
> +		/*
> +		 * This controller supports RDDM, so we need to manually clear
> +		 * BHIE RX registers since POR values are undefined.
> +		 */
>  		memset_io(mhi_cntrl->bhie + BHIE_RXVECADDR_LOW_OFFS,
>  			  0, BHIE_RXVECSTATUS_OFFS - BHIE_RXVECADDR_LOW_OFFS +
>  			  4);
> -
> +		/*
> +		 * Allocate RDDM table for debugging purpose if specified
> +		 */
> +		mhi_alloc_bhie_table(mhi_cntrl, &mhi_cntrl->rddm_image,
> +				     mhi_cntrl->rddm_size);
>  		if (mhi_cntrl->rddm_image)
>  			mhi_rddm_prepare(mhi_cntrl, mhi_cntrl->rddm_image);
>  	}
> @@ -1103,11 +1110,8 @@ int mhi_prepare_for_power_up(struct mhi_controller *mhi_cntrl)
>  
>  	return 0;
>  
> -bhie_error:
> -	if (mhi_cntrl->rddm_image) {
> -		mhi_free_bhie_table(mhi_cntrl, mhi_cntrl->rddm_image);
> -		mhi_cntrl->rddm_image = NULL;
> -	}
> +error_reg_offset:
> +	mhi_deinit_dev_ctxt(mhi_cntrl);
>  
>  error_dev_ctxt:
>  	mutex_unlock(&mhi_cntrl->pm_mutex);
> diff --git a/drivers/bus/mhi/core/pm.c b/drivers/bus/mhi/core/pm.c
> index e2e59a3..adf426c 100644
> --- a/drivers/bus/mhi/core/pm.c
> +++ b/drivers/bus/mhi/core/pm.c
> @@ -1066,28 +1066,8 @@ int mhi_async_power_up(struct mhi_controller *mhi_cntrl)
>  	if (ret)
>  		goto error_setup_irq;
>  
> -	/* Setup BHI offset & INTVEC */
> +	/* Setup BHI INTVEC */
>  	write_lock_irq(&mhi_cntrl->pm_lock);
> -	ret = mhi_read_reg(mhi_cntrl, mhi_cntrl->regs, BHIOFF, &val);
> -	if (ret) {
> -		write_unlock_irq(&mhi_cntrl->pm_lock);
> -		goto error_bhi_offset;
> -	}
> -
> -	mhi_cntrl->bhi = mhi_cntrl->regs + val;
> -
> -	/* Setup BHIE offset */
> -	if (mhi_cntrl->fbc_download) {
> -		ret = mhi_read_reg(mhi_cntrl, mhi_cntrl->regs, BHIEOFF, &val);
> -		if (ret) {
> -			write_unlock_irq(&mhi_cntrl->pm_lock);
> -			dev_err(dev, "Error reading BHIE offset\n");
> -			goto error_bhi_offset;
> -		}
> -
> -		mhi_cntrl->bhie = mhi_cntrl->regs + val;
> -	}
> -
>  	mhi_write_reg(mhi_cntrl, mhi_cntrl->bhi, BHI_INTVEC, 0);
>  	mhi_cntrl->pm_state = MHI_PM_POR;
>  	mhi_cntrl->ee = MHI_EE_MAX;
> @@ -1098,7 +1078,7 @@ int mhi_async_power_up(struct mhi_controller *mhi_cntrl)
>  	if (!MHI_IN_PBL(current_ee) && current_ee != MHI_EE_AMSS) {
>  		dev_err(dev, "Not a valid EE for power on\n");
>  		ret = -EIO;
> -		goto error_bhi_offset;
> +		goto error_async_power_up;
>  	}
>  
>  	state = mhi_get_mhi_state(mhi_cntrl);
> @@ -1117,7 +1097,7 @@ int mhi_async_power_up(struct mhi_controller *mhi_cntrl)
>  		if (!ret) {
>  			ret = -EIO;
>  			dev_info(dev, "Failed to reset MHI due to syserr state\n");
> -			goto error_bhi_offset;
> +			goto error_async_power_up;
>  		}
>  
>  		/*
> @@ -1139,7 +1119,7 @@ int mhi_async_power_up(struct mhi_controller *mhi_cntrl)
>  
>  	return 0;
>  
> -error_bhi_offset:
> +error_async_power_up:
>  	mhi_deinit_free_irq(mhi_cntrl);
>  
>  error_setup_irq:
> -- 
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
> 


From manivannan.sadhasivam at linaro.org  Fri May 21 14:37:28 2021
From: manivannan.sadhasivam at linaro.org (Manivannan Sadhasivam)
Date: Fri, 21 May 2021 19:07:28 +0530
Subject: [PATCH v4 2/6] bus: mhi: core: Set BHI and BHIe pointers to NULL
 in clean-up
In-Reply-To: <1620330705-40192-3-git-send-email-bbhatt@codeaurora.org>
References: <1620330705-40192-1-git-send-email-bbhatt@codeaurora.org>
 <1620330705-40192-3-git-send-email-bbhatt@codeaurora.org>
Message-ID: <20210521133728.GJ70095@thinkpad>

On Thu, May 06, 2021 at 12:51:41PM -0700, Bhaumik Bhatt wrote:
> Set the BHI and BHIe pointers to NULL as part of clean-up. This
> makes sure that stale pointers are not accessed after powering
> MHI down.
> 
> Suggested-by: Hemant Kumar <hemantk at codeaurora.org>
> Signed-off-by: Bhaumik Bhatt <bbhatt at codeaurora.org>
> Reviewed-by: Jeffrey Hugo <quic_jhugo at quicinc.com>
> Reviewed-by: Hemant Kumar <hemantk at codeaurora.org>

Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam at linaro.org>

Thanks,
Mani

> ---
>  drivers/bus/mhi/core/init.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/bus/mhi/core/init.c b/drivers/bus/mhi/core/init.c
> index 11c7a3d..1cc2f22 100644
> --- a/drivers/bus/mhi/core/init.c
> +++ b/drivers/bus/mhi/core/init.c
> @@ -1132,6 +1132,9 @@ void mhi_unprepare_after_power_down(struct mhi_controller *mhi_cntrl)
>  		mhi_cntrl->rddm_image = NULL;
>  	}
>  
> +	mhi_cntrl->bhi = NULL;
> +	mhi_cntrl->bhie = NULL;
> +
>  	mhi_deinit_dev_ctxt(mhi_cntrl);
>  }
>  EXPORT_SYMBOL_GPL(mhi_unprepare_after_power_down);
> -- 
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
> 


From manivannan.sadhasivam at linaro.org  Fri May 21 14:38:12 2021
From: manivannan.sadhasivam at linaro.org (Manivannan Sadhasivam)
Date: Fri, 21 May 2021 19:08:12 +0530
Subject: [PATCH v4 3/6] bus: mhi: Add MMIO region length to controller
 structure
In-Reply-To: <1620330705-40192-4-git-send-email-bbhatt@codeaurora.org>
References: <1620330705-40192-1-git-send-email-bbhatt@codeaurora.org>
 <1620330705-40192-4-git-send-email-bbhatt@codeaurora.org>
Message-ID: <20210521133812.GK70095@thinkpad>

On Thu, May 06, 2021 at 12:51:42PM -0700, Bhaumik Bhatt wrote:
> Make controller driver specify the MMIO register region length
> for range checking of BHI or BHIe space. This can help validate
> that offsets are in acceptable memory region or not and avoid any
> boot-up issues due to BHI or BHIe memory accesses.
> 
> Signed-off-by: Bhaumik Bhatt <bbhatt at codeaurora.org>
> Reviewed-by: Jeffrey Hugo <quic_jhugo at quicinc.com>
> Reviewed-by: Hemant Kumar <hemantk at codeaurora.org>

Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam at linaro.org>

Thanks,
Mani

> ---
>  include/linux/mhi.h | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/include/linux/mhi.h b/include/linux/mhi.h
> index 944aa3a..9c347f5 100644
> --- a/include/linux/mhi.h
> +++ b/include/linux/mhi.h
> @@ -303,6 +303,7 @@ struct mhi_controller_config {
>   * @rddm_size: RAM dump size that host should allocate for debugging purpose
>   * @sbl_size: SBL image size downloaded through BHIe (optional)
>   * @seg_len: BHIe vector size (optional)
> + * @reg_len: Length of the MHI MMIO region (required)
>   * @fbc_image: Points to firmware image buffer
>   * @rddm_image: Points to RAM dump buffer
>   * @mhi_chan: Points to the channel configuration table
> @@ -386,6 +387,7 @@ struct mhi_controller {
>  	size_t rddm_size;
>  	size_t sbl_size;
>  	size_t seg_len;
> +	size_t reg_len;
>  	struct image_info *fbc_image;
>  	struct image_info *rddm_image;
>  	struct mhi_chan *mhi_chan;
> -- 
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
> 


From manivannan.sadhasivam at linaro.org  Fri May 21 14:51:52 2021
From: manivannan.sadhasivam at linaro.org (Manivannan Sadhasivam)
Date: Fri, 21 May 2021 19:21:52 +0530
Subject: [PATCH v4 4/6] ath11k: set register access length for MHI driver
In-Reply-To: <1620330705-40192-5-git-send-email-bbhatt@codeaurora.org>
References: <1620330705-40192-1-git-send-email-bbhatt@codeaurora.org>
 <1620330705-40192-5-git-send-email-bbhatt@codeaurora.org>
Message-ID: <20210521135152.GL70095@thinkpad>

On Thu, May 06, 2021 at 12:51:43PM -0700, Bhaumik Bhatt wrote:
> MHI driver requires register space length to add range checks and
> prevent memory region accesses outside of that for MMIO space.
> Set it before registering the MHI controller.
> 
> Signed-off-by: Bhaumik Bhatt <bbhatt at codeaurora.org>
> Reviewed-by: Hemant Kumar <hemantk at codeaurora.org>

Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam at linaro.org>

Kalle, should we do immutable branch for this patch or I can pick it up via MHI
tree (if there are no other patches expected from ath11k for this controller)?

Thanks,
Mani

> ---
>  drivers/net/wireless/ath/ath11k/mhi.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/net/wireless/ath/ath11k/mhi.c b/drivers/net/wireless/ath/ath11k/mhi.c
> index 09858e5..c0f013c 100644
> --- a/drivers/net/wireless/ath/ath11k/mhi.c
> +++ b/drivers/net/wireless/ath/ath11k/mhi.c
> @@ -235,6 +235,7 @@ int ath11k_mhi_register(struct ath11k_pci *ab_pci)
>  	mhi_ctrl->cntrl_dev = ab->dev;
>  	mhi_ctrl->fw_image = ab_pci->amss_path;
>  	mhi_ctrl->regs = ab->mem;
> +	mhi_ctrl->reg_len = ab->mem_len;
>  
>  	ret = ath11k_mhi_get_msi(ab_pci);
>  	if (ret) {
> -- 
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
> 


From manivannan.sadhasivam at linaro.org  Fri May 21 14:52:18 2021
From: manivannan.sadhasivam at linaro.org (Manivannan Sadhasivam)
Date: Fri, 21 May 2021 19:22:18 +0530
Subject: [PATCH v4 5/6] bus: mhi: pci_generic: Set register access length
 for MHI driver
In-Reply-To: <1620330705-40192-6-git-send-email-bbhatt@codeaurora.org>
References: <1620330705-40192-1-git-send-email-bbhatt@codeaurora.org>
 <1620330705-40192-6-git-send-email-bbhatt@codeaurora.org>
Message-ID: <20210521135218.GM70095@thinkpad>

On Thu, May 06, 2021 at 12:51:44PM -0700, Bhaumik Bhatt wrote:
> MHI driver requires register space length to add range checks and
> prevent memory region accesses outside of that for MMIO space.
> Set it from the PCI generic controller driver before registering
> the MHI controller.
> 
> Signed-off-by: Bhaumik Bhatt <bbhatt at codeaurora.org>
> Reviewed-by: Hemant Kumar <hemantk at codeaurora.org>
> Reviewed-by: Loic Poulain <loic.poulain at linaro.org>

Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam at linaro.org>

Thanks,
Mani

> ---
>  drivers/bus/mhi/pci_generic.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/bus/mhi/pci_generic.c b/drivers/bus/mhi/pci_generic.c
> index 7c810f0..fb7889f 100644
> --- a/drivers/bus/mhi/pci_generic.c
> +++ b/drivers/bus/mhi/pci_generic.c
> @@ -463,6 +463,7 @@ static int mhi_pci_claim(struct mhi_controller *mhi_cntrl,
>  		return err;
>  	}
>  	mhi_cntrl->regs = pcim_iomap_table(pdev)[bar_num];
> +	mhi_cntrl->reg_len = pci_resource_len(pdev, bar_num);
>  
>  	err = pci_set_dma_mask(pdev, dma_mask);
>  	if (err) {
> -- 
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
> 


From manivannan.sadhasivam at linaro.org  Fri May 21 14:54:37 2021
From: manivannan.sadhasivam at linaro.org (Manivannan Sadhasivam)
Date: Fri, 21 May 2021 19:24:37 +0530
Subject: [PATCH v4 6/6] bus: mhi: core: Add range checks for BHI and BHIe
In-Reply-To: <1620330705-40192-7-git-send-email-bbhatt@codeaurora.org>
References: <1620330705-40192-1-git-send-email-bbhatt@codeaurora.org>
 <1620330705-40192-7-git-send-email-bbhatt@codeaurora.org>
Message-ID: <20210521135437.GN70095@thinkpad>

On Thu, May 06, 2021 at 12:51:45PM -0700, Bhaumik Bhatt wrote:
> When obtaining the BHI or BHIe offsets during the power up
> preparation phase, range checks are missing. These can help
> controller drivers avoid accessing any address outside of the
> MMIO region. Ensure that mhi_cntrl->reg_len is set before MHI
> registration as it is a required field and range checks will
> fail without it.
> 
> Signed-off-by: Bhaumik Bhatt <bbhatt at codeaurora.org>
> Reviewed-by: Jeffrey Hugo <quic_jhugo at quicinc.com>

Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam at linaro.org>

Thanks,
Mani

> ---
>  drivers/bus/mhi/core/init.c | 18 +++++++++++++++++-
>  1 file changed, 17 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/bus/mhi/core/init.c b/drivers/bus/mhi/core/init.c
> index 1cc2f22..aeb1e3c 100644
> --- a/drivers/bus/mhi/core/init.c
> +++ b/drivers/bus/mhi/core/init.c
> @@ -885,7 +885,8 @@ int mhi_register_controller(struct mhi_controller *mhi_cntrl,
>  	if (!mhi_cntrl || !mhi_cntrl->cntrl_dev || !mhi_cntrl->regs ||
>  	    !mhi_cntrl->runtime_get || !mhi_cntrl->runtime_put ||
>  	    !mhi_cntrl->status_cb || !mhi_cntrl->read_reg ||
> -	    !mhi_cntrl->write_reg || !mhi_cntrl->nr_irqs || !mhi_cntrl->irq)
> +	    !mhi_cntrl->write_reg || !mhi_cntrl->nr_irqs ||
> +	    !mhi_cntrl->irq || !mhi_cntrl->reg_len)
>  		return -EINVAL;
>  
>  	ret = parse_config(mhi_cntrl, config);
> @@ -1077,6 +1078,13 @@ int mhi_prepare_for_power_up(struct mhi_controller *mhi_cntrl)
>  		dev_err(dev, "Error getting BHI offset\n");
>  		goto error_reg_offset;
>  	}
> +
> +	if (bhi_off >= mhi_cntrl->reg_len) {
> +		dev_err(dev, "BHI offset: 0x%x is out of range: 0x%zx\n",
> +			bhi_off, mhi_cntrl->reg_len);
> +		ret = -EINVAL;
> +		goto error_reg_offset;
> +	}
>  	mhi_cntrl->bhi = mhi_cntrl->regs + bhi_off;
>  
>  	if (mhi_cntrl->fbc_download || mhi_cntrl->rddm_size) {
> @@ -1086,6 +1094,14 @@ int mhi_prepare_for_power_up(struct mhi_controller *mhi_cntrl)
>  			dev_err(dev, "Error getting BHIE offset\n");
>  			goto error_reg_offset;
>  		}
> +
> +		if (bhie_off >= mhi_cntrl->reg_len) {
> +			dev_err(dev,
> +				"BHIe offset: 0x%x is out of range: 0x%zx\n",
> +				bhie_off, mhi_cntrl->reg_len);
> +			ret = -EINVAL;
> +			goto error_reg_offset;
> +		}
>  		mhi_cntrl->bhie = mhi_cntrl->regs + bhie_off;
>  	}
>  
> -- 
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
> 


From christophe.jaillet at wanadoo.fr  Sat May 22 10:50:54 2021
From: christophe.jaillet at wanadoo.fr (Christophe JAILLET)
Date: Sat, 22 May 2021 11:50:54 +0200
Subject: [PATCH] ath11k: Fix an error handling path in
 'ath11k_core_fetch_board_data_api_n()'
Message-ID: <e959eb544f3cb04258507d8e25a6f12eab126bde.1621676864.git.christophe.jaillet@wanadoo.fr>

All error paths but this one 'goto err' in order to release some
resources.
Fix this.

Fixes: d5c65159f289 ("ath11k: driver for Qualcomm IEEE 802.11ax devices")
Signed-off-by: Christophe JAILLET <christophe.jaillet at wanadoo.fr>
---
 drivers/net/wireless/ath/ath11k/core.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/net/wireless/ath/ath11k/core.c b/drivers/net/wireless/ath/ath11k/core.c
index 77ce3347ab86..595e83fe0990 100644
--- a/drivers/net/wireless/ath/ath11k/core.c
+++ b/drivers/net/wireless/ath/ath11k/core.c
@@ -488,7 +488,8 @@ static int ath11k_core_fetch_board_data_api_n(struct ath11k_base *ab,
 		if (len < ALIGN(ie_len, 4)) {
 			ath11k_err(ab, "invalid length for board ie_id %d ie_len %zu len %zu\n",
 				   ie_id, ie_len, len);
-			return -EINVAL;
+			ret = -EINVAL;
+			goto err;
 		}
 
 		switch (ie_id) {
-- 
2.30.2



From manivannan.sadhasivam at linaro.org  Mon May 24 01:43:18 2021
From: manivannan.sadhasivam at linaro.org (Manivannan Sadhasivam)
Date: Mon, 24 May 2021 14:13:18 +0530
Subject: [PATCH v2] bus: mhi: Wait for M2 state during system resume
In-Reply-To: <YKtPXWrTb6Qj+E9l@kroah.com>
References: <20210524040312.14409-1-bqiang@codeaurora.org>
 <YKtPXWrTb6Qj+E9l@kroah.com>
Message-ID: <20210524084318.GA27389@work>

On Mon, May 24, 2021 at 09:01:49AM +0200, Greg KH wrote:
> On Mon, May 24, 2021 at 12:03:12PM +0800, Baochen Qiang wrote:
> > During system resume, MHI host triggers M3->M0 transition and then waits
> > for target device to enter M0 state. Once done, the device queues a state
> > change event into ctrl event ring and notifies MHI host by raising an
> > interrupt, where a tasklet is scheduled to process this event. In most cases,
> > the tasklet is served timely and wait operation succeeds.
> > 
> > However, there are cases where CPU is busy and cannot serve this tasklet
> > for some time. Once delay goes long enough, the device moves itself to M1
> > state and also interrupts MHI host after inserting a new state change
> > event to ctrl ring. Later CPU finally has time to process the ring, however
> > there are two events in it now:
> > 	1. for M3->M0 event, which is processed first as queued first,
> > 	   tasklet handler updates device state to M0 and wakes up the task,
> > 	   i.e., the MHI host.
> > 	2. for M0->M1 event, which is processed later, tasklet handler
> > 	   triggers M1->M2 transition and updates device state to M2 directly,
> > 	   then wakes up the MHI host(if still sleeping on this wait queue).
> > Note that although MHI host has been woken up while processing the first
> > event, it may still has no chance to run before the second event is processed.
> > In other words, MHI host has to keep waiting till timeout cause the M0 state
> > has been missed.
> > 
> > kernel log here:
> > ...
> > Apr 15 01:45:14 test-NUC8i7HVK kernel: [ 4247.911251] mhi 0000:06:00.0: Entered with PM state: M3, MHI state: M3
> > Apr 15 01:45:14 test-NUC8i7HVK kernel: [ 4247.917762] mhi 0000:06:00.0: State change event to state: M0
> > Apr 15 01:45:14 test-NUC8i7HVK kernel: [ 4247.917767] mhi 0000:06:00.0: State change event to state: M1
> > Apr 15 01:45:14 test-NUC8i7HVK kernel: [ 4338.788231] mhi 0000:06:00.0: Did not enter M0 state, MHI state: M2, PM state: M2
> > ...
> > 
> > Fix this issue by simply adding M2 as a valid state for resume.
> > 
> > Tested-on: WCN6855 hw2.0 PCI WLAN.HSP.1.1-01720.1-QCAHSPSWPL_V1_V2_SILICONZ_LITE-1
> > 
> > Fixes: 0c6b20a1d720 ("bus: mhi: core: Add support for MHI suspend and resume")
> > Signed-off-by: Baochen Qiang <bqiang at codeaurora.org>
> > Reviewed-by: Hemant Kumar <hemantk at codeaurora.org>
> > ---
> >  drivers/bus/mhi/core/pm.c | 1 +
> >  1 file changed, 1 insertion(+)
> 
> <formletter>
> 
> This is not the correct way to submit patches for inclusion in the
> stable kernel tree.  Please read:
>     https://www.kernel.org/doc/html/latest/process/stable-kernel-rules.html
> for how to do this properly.
> 

I've applied this patch to mhi tree with tag "Cc: stable at vger.kernel.org".

Thanks,
Mani

> </formletter>


From bqiang at codeaurora.org  Sun May 23 20:14:58 2021
From: bqiang at codeaurora.org (bqiang at codeaurora.org)
Date: Mon, 24 May 2021 11:14:58 +0800
Subject: [PATCH] mhi: add MHI_STATE_M2 to resume success criteria
In-Reply-To: <20210521124530.GF70095@thinkpad>
References: <20210420035339.282963-1-bqiang@codeaurora.org>
 <20210521124530.GF70095@thinkpad>
Message-ID: <480583c9b392c315c30795c54afd69f8@codeaurora.org>

On 2021-05-21 20:45, Manivannan Sadhasivam wrote:
> Hi,
> 
> The patch subject should be,
> 
> "bus: mhi: Wait for M2 state during system resume"
> 
> We follow "bus: mhi:" prefix for all MHI patches. Also, the subject 
> should
> clearly portray what the patch is intend to do.
> 
> On Tue, Apr 20, 2021 at 11:53:39AM +0800, Baochen Qiang wrote:
>> During system resume, mhi driver triggers M3->M0 transition and then 
>> waits
> 
> s/mhi driver/MHI host
> 
>> for target device to enter M0 state. Once done, the device queues a 
>> state
>> change event into ctrl event ring and notify mhi dirver by raising an
> 
> s/notify/notifies and s/mhi dirver/MHI host. MHI driver is somewhat 
> confusing
> since we have the MHI device driver (QRTR etc...) as well. So just use 
> MHI host
> everywhere.
> 
>> interrupt, where a tasklet is scheduled to process this event. In most 
>> cases,
>> the taklet is served timely and wait operation succeeds.
>> 
> 
> s/taklet/tasklet
> 
>> However, there are cases where CPU is busy and can not serve this 
>> tasklet
> 
> a/can not/cannot
> 
>> for some time. Once delay goes long enough, the device moves itself to 
>> M1
>> state and also interrupts mhi driver after inserting a new state 
>> change
>> event to ctrl ring. Later CPU finally has time to process the ring, 
>> however
>> there are two events in it now:
>> 	1. for M3->M0 event, which is processed first as queued first,
>> 	   tasklet handler updates device state to M0 and wakes up the task,
>> 	   i.e., the mhi driver.
>> 	2. for M0->M1 event, which is processed later, tasklet handler
>> 	   triggers M1->M2 transition and updates device state to M2 
>> directly,
>> 	   then wakes up the mhi driver(if still sleeping on this wait 
>> queue).
>> Note that although mhi driver has been woken up while processing the 
>> first
>> event, it may still has no chance to run before the second event is 
>> processed.
>> In other words, mhi driver has to keep waiting till timeout cause the 
>> M0 state
>> has been missed.
>> 
>> kernel log here:
>> ...
>> Apr 15 01:45:14 test-NUC8i7HVK kernel: [ 4247.911251] mhi 
>> 0000:06:00.0: Entered with PM state: M3, MHI state: M3
>> Apr 15 01:45:14 test-NUC8i7HVK kernel: [ 4247.917762] mhi 
>> 0000:06:00.0: State change event to state: M0
>> Apr 15 01:45:14 test-NUC8i7HVK kernel: [ 4247.917767] mhi 
>> 0000:06:00.0: State change event to state: M1
>> Apr 15 01:45:14 test-NUC8i7HVK kernel: [ 4338.788231] mhi 
>> 0000:06:00.0: Did not enter M0 state, MHI state: M2, PM state: M2
>> ...
>> 
>> Fix this issue by simply adding M2 as a valid state for resume.
>> 
>> Tested-on: WCN6855 hw2.0 PCI 
>> WLAN.HSP.1.1-01720.1-QCAHSPSWPL_V1_V2_SILICONZ_LITE-1
>> 
>> Signed-off-by: Baochen Qiang <bqiang at codeaurora.org>
> 
> Could you please add a fixes tag as well? And this patch should be 
> backported to
> stable kernels also, so please CC stable at vger.kernel.org.
> 
> Thanks,
> Mani
> 

Thanks Mani.
Will address them and send as V2.

>> ---
>>  drivers/bus/mhi/core/pm.c | 1 +
>>  1 file changed, 1 insertion(+)
>> 
>> diff --git a/drivers/bus/mhi/core/pm.c b/drivers/bus/mhi/core/pm.c
>> index ce73cfa63cb3..ca5f2feed9d5 100644
>> --- a/drivers/bus/mhi/core/pm.c
>> +++ b/drivers/bus/mhi/core/pm.c
>> @@ -900,6 +900,7 @@ int mhi_pm_resume(struct mhi_controller 
>> *mhi_cntrl)
>> 
>>  	ret = wait_event_timeout(mhi_cntrl->state_event,
>>  				 mhi_cntrl->dev_state == MHI_STATE_M0 ||
>> +				 mhi_cntrl->dev_state == MHI_STATE_M2 ||
>>  				 MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state),
>>  				 msecs_to_jiffies(mhi_cntrl->timeout_ms));
>> 
>> --
>> 2.25.1
>> 


From manivannan.sadhasivam at linaro.org  Sun May 23 21:58:55 2021
From: manivannan.sadhasivam at linaro.org (Manivannan Sadhasivam)
Date: Mon, 24 May 2021 10:28:55 +0530
Subject: [PATCH v2] bus: mhi: Wait for M2 state during system resume
In-Reply-To: <20210524043740.GC8823@work>
References: <20210524040312.14409-1-bqiang@codeaurora.org>
 <20210524043740.GC8823@work>
Message-ID: <20210524045855.GF8823@work>

On Mon, May 24, 2021 at 10:07:40AM +0530, Manivannan Sadhasivam wrote:
> On Mon, May 24, 2021 at 12:03:12PM +0800, Baochen Qiang wrote:
> > During system resume, MHI host triggers M3->M0 transition and then waits
> > for target device to enter M0 state. Once done, the device queues a state
> > change event into ctrl event ring and notifies MHI host by raising an
> > interrupt, where a tasklet is scheduled to process this event. In most cases,
> > the tasklet is served timely and wait operation succeeds.
> > 
> > However, there are cases where CPU is busy and cannot serve this tasklet
> > for some time. Once delay goes long enough, the device moves itself to M1
> > state and also interrupts MHI host after inserting a new state change
> > event to ctrl ring. Later CPU finally has time to process the ring, however
> > there are two events in it now:
> > 	1. for M3->M0 event, which is processed first as queued first,
> > 	   tasklet handler updates device state to M0 and wakes up the task,
> > 	   i.e., the MHI host.
> > 	2. for M0->M1 event, which is processed later, tasklet handler
> > 	   triggers M1->M2 transition and updates device state to M2 directly,
> > 	   then wakes up the MHI host(if still sleeping on this wait queue).
> > Note that although MHI host has been woken up while processing the first
> > event, it may still has no chance to run before the second event is processed.
> > In other words, MHI host has to keep waiting till timeout cause the M0 state
> > has been missed.
> > 
> > kernel log here:
> > ...
> > Apr 15 01:45:14 test-NUC8i7HVK kernel: [ 4247.911251] mhi 0000:06:00.0: Entered with PM state: M3, MHI state: M3
> > Apr 15 01:45:14 test-NUC8i7HVK kernel: [ 4247.917762] mhi 0000:06:00.0: State change event to state: M0
> > Apr 15 01:45:14 test-NUC8i7HVK kernel: [ 4247.917767] mhi 0000:06:00.0: State change event to state: M1
> > Apr 15 01:45:14 test-NUC8i7HVK kernel: [ 4338.788231] mhi 0000:06:00.0: Did not enter M0 state, MHI state: M2, PM state: M2
> > ...
> > 
> > Fix this issue by simply adding M2 as a valid state for resume.
> > 
> > Tested-on: WCN6855 hw2.0 PCI WLAN.HSP.1.1-01720.1-QCAHSPSWPL_V1_V2_SILICONZ_LITE-1
> > 
> > Fixes: 0c6b20a1d720 ("bus: mhi: core: Add support for MHI suspend and resume")
> > Signed-off-by: Baochen Qiang <bqiang at codeaurora.org>
> > Reviewed-by: Hemant Kumar <hemantk at codeaurora.org>
> 
> Applied to mhi-fixes!
> 

Sorry this has been applied to mhi-next!

Thanks,
Mani

> Thanks,
> Mani
> 
> > ---
> >  drivers/bus/mhi/core/pm.c | 1 +
> >  1 file changed, 1 insertion(+)
> > 
> > diff --git a/drivers/bus/mhi/core/pm.c b/drivers/bus/mhi/core/pm.c
> > index e2e59a341fef..59b009a3ee9b 100644
> > --- a/drivers/bus/mhi/core/pm.c
> > +++ b/drivers/bus/mhi/core/pm.c
> > @@ -934,6 +934,7 @@ int mhi_pm_resume(struct mhi_controller *mhi_cntrl)
> >  
> >  	ret = wait_event_timeout(mhi_cntrl->state_event,
> >  				 mhi_cntrl->dev_state == MHI_STATE_M0 ||
> > +				 mhi_cntrl->dev_state == MHI_STATE_M2 ||
> >  				 MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state),
> >  				 msecs_to_jiffies(mhi_cntrl->timeout_ms));
> >  
> > -- 
> > 2.25.1
> > 


From bqiang at codeaurora.org  Sun May 23 21:03:12 2021
From: bqiang at codeaurora.org (Baochen Qiang)
Date: Mon, 24 May 2021 12:03:12 +0800
Subject: [PATCH v2] bus: mhi: Wait for M2 state during system resume
Message-ID: <20210524040312.14409-1-bqiang@codeaurora.org>

During system resume, MHI host triggers M3->M0 transition and then waits
for target device to enter M0 state. Once done, the device queues a state
change event into ctrl event ring and notifies MHI host by raising an
interrupt, where a tasklet is scheduled to process this event. In most cases,
the tasklet is served timely and wait operation succeeds.

However, there are cases where CPU is busy and cannot serve this tasklet
for some time. Once delay goes long enough, the device moves itself to M1
state and also interrupts MHI host after inserting a new state change
event to ctrl ring. Later CPU finally has time to process the ring, however
there are two events in it now:
	1. for M3->M0 event, which is processed first as queued first,
	   tasklet handler updates device state to M0 and wakes up the task,
	   i.e., the MHI host.
	2. for M0->M1 event, which is processed later, tasklet handler
	   triggers M1->M2 transition and updates device state to M2 directly,
	   then wakes up the MHI host(if still sleeping on this wait queue).
Note that although MHI host has been woken up while processing the first
event, it may still has no chance to run before the second event is processed.
In other words, MHI host has to keep waiting till timeout cause the M0 state
has been missed.

kernel log here:
...
Apr 15 01:45:14 test-NUC8i7HVK kernel: [ 4247.911251] mhi 0000:06:00.0: Entered with PM state: M3, MHI state: M3
Apr 15 01:45:14 test-NUC8i7HVK kernel: [ 4247.917762] mhi 0000:06:00.0: State change event to state: M0
Apr 15 01:45:14 test-NUC8i7HVK kernel: [ 4247.917767] mhi 0000:06:00.0: State change event to state: M1
Apr 15 01:45:14 test-NUC8i7HVK kernel: [ 4338.788231] mhi 0000:06:00.0: Did not enter M0 state, MHI state: M2, PM state: M2
...

Fix this issue by simply adding M2 as a valid state for resume.

Tested-on: WCN6855 hw2.0 PCI WLAN.HSP.1.1-01720.1-QCAHSPSWPL_V1_V2_SILICONZ_LITE-1

Fixes: 0c6b20a1d720 ("bus: mhi: core: Add support for MHI suspend and resume")
Signed-off-by: Baochen Qiang <bqiang at codeaurora.org>
Reviewed-by: Hemant Kumar <hemantk at codeaurora.org>
---
 drivers/bus/mhi/core/pm.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/bus/mhi/core/pm.c b/drivers/bus/mhi/core/pm.c
index e2e59a341fef..59b009a3ee9b 100644
--- a/drivers/bus/mhi/core/pm.c
+++ b/drivers/bus/mhi/core/pm.c
@@ -934,6 +934,7 @@ int mhi_pm_resume(struct mhi_controller *mhi_cntrl)
 
 	ret = wait_event_timeout(mhi_cntrl->state_event,
 				 mhi_cntrl->dev_state == MHI_STATE_M0 ||
+				 mhi_cntrl->dev_state == MHI_STATE_M2 ||
 				 MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state),
 				 msecs_to_jiffies(mhi_cntrl->timeout_ms));
 
-- 
2.25.1



From kvalo at codeaurora.org  Sun May 23 22:56:14 2021
From: kvalo at codeaurora.org (Kalle Valo)
Date: Mon, 24 May 2021 08:56:14 +0300
Subject: [regressions] ath11k: v5.12.3 mhi regression
In-Reply-To: <YKanuzzvDhztYxm/@kroah.com> (Greg KH's message of "Thu, 20 May
 2021 20:17:31 +0200")
References: <87v97dhh2u.fsf@codeaurora.org> <YKYzwBJNTy4Czd1A@kroah.com>
 <20210520104313.GA128703@thinkpad> <87r1i1h9an.fsf@codeaurora.org>
 <3e8bac3b02e3549a55b7c9b78b699965@codeaurora.org>
 <YKajWVPUSTzNVVm8@kroah.com>
 <608474b9b9feae5bd0616ad16d6d6bbd@codeaurora.org>
 <YKanuzzvDhztYxm/@kroah.com>
Message-ID: <87eedwhdz5.fsf@codeaurora.org>

Greg KH <gregkh at linuxfoundation.org> writes:

> On Thu, May 20, 2021 at 11:04:05AM -0700, Bhaumik Bhatt wrote:
>> On 2021-05-20 10:58 AM, Greg KH wrote:
>> > On Thu, May 20, 2021 at 10:38:12AM -0700, Bhaumik Bhatt wrote:
>> > > On 2021-05-20 05:36 AM, Kalle Valo wrote:
>> > > > Manivannan Sadhasivam <manivannan.sadhasivam at linaro.org> writes:
>> > > >
>> > > > > On Thu, May 20, 2021 at 12:02:40PM +0200, Greg KH wrote:
>> > > > > > On Thu, May 20, 2021 at 12:47:53PM +0300, Kalle Valo wrote:
>> > > > > > > Hi,
>> > > > > > >
>> > > > > > > I got several reports that this mhi commit broke ath11k in v5.12.3:
>> > > > > > >
>> > > > > > > commit 29b9829718c5e9bd68fc1c652f5e0ba9b9a64fed
>> > > > > > > Author: Bhaumik Bhatt <bbhatt at codeaurora.org>
>> > > > > > > Date:   Wed Feb 24 15:23:04 2021 -0800
>> > > > > > >
>> > > > > > >     bus: mhi: core: Process execution environment changes serially
>> > > > > > >
>> > > > > > >     [ Upstream commit ef2126c4e2ea2b92f543fae00a2a0332e4573c48 ]
>> > > > > > >
>> > > > > > > Here are the reports:
>> > > > > > >
>> > > > > > > https://bugzilla.kernel.org/show_bug.cgi?id=213055
>> > > > > > >
>> > > > > > > https://bugzilla.kernel.org/show_bug.cgi?id=212187
>> > > > > > >
>> > > > > > > https://bugs.archlinux.org/task/70849?project=1&string=linux
>> > > > > > >
>> > > > > > > Interestingly v5.13-rc1 seems to work fine, at least for me, though I
>> > > > > > > have not tested v5.12.3 myself. Can someone revert this commit in the
>> > > > > > > stable release so that people get their wifi working again, please?
>> > > > > >
>> > > > > > How does the mhi bus code relate to a ath11k driver?  What bus
>> > > > > > is that
>> > > > > > on?
>> > > > > >
>> > > > >
>> > > > > MHI is the transport used by the ath11k driver to work with the WLAN
>> > > > > devices
>> > > > > over PCIe.
>> > > > >
>> > > > > Regarding the bug, I'd suggest to wait for Bhaumik (the author of
>> > > > > 29b9829718c5)
>> > > > > to comment on the possible commit which needs backporting from
>> > > > > mainline.
>> > > >
>> > > > Ok, but if a quick fix is not available I think we should just revert
>> > > > this in the stable releases. I also got a report that v5.11.21 is
>> > > > broken:
>> > > >
>> > > > https://bugzilla.kernel.org/show_bug.cgi?id=213055#c11
>> > > 
>> > > Please pick [1] as the dependency to [ Upstream commit
>> > > ef2126c4e2ea2b92f543fae00a2a0332e4573c48 ].
>> > 
>> > what is [1]???
>> > 
>> > What commit do I need to backport, a commit id would be nice...
>> > 
>> > thanks,
>> > 
>> > greg k-h
>> Sure Greg. Commit id is: 4884362f6977fc05cbec736625665241c0e0732f
>> 
>> Title of patch:
>> bus: mhi: core: Download AMSS image from appropriate function
>> 
>> It was supposed to be a link but not sure why it's not seen.
>
> Text email doesn't have links :)
>
> Anyway, thanks, now queued up.

I'm now getting confirmations that this issue is fixed in v5.12.6.
Thanks for the quick fix and the quick new release!

-- 
https://patchwork.kernel.org/project/linux-wireless/list/

https://wireless.wiki.kernel.org/en/developers/documentation/submittingpatches


From kvalo at codeaurora.org  Sun May 23 22:35:47 2021
From: kvalo at codeaurora.org (Kalle Valo)
Date: Mon, 24 May 2021 05:35:47 +0000 (UTC)
Subject: [PATCH] ath10k/ath11k: fix spelling mistake "requed" -> "requeued"
In-Reply-To: <20210423134133.339751-1-colin.king@canonical.com>
References: <20210423134133.339751-1-colin.king@canonical.com>
Message-ID: <20210524053547.6F488C43217@smtp.codeaurora.org>

Colin King <colin.king at canonical.com> wrote:

> There are multiple occurrances of the misspelling of requeued in
> the drivers with symbol names and debug text. Fix these.
> 
> Signed-off-by: Colin Ian King <colin.king at canonical.com>
> Signed-off-by: Kalle Valo <kvalo at codeaurora.org>

Patch applied to ath-next branch of ath.git, thanks.

17818dfa8f2e ath10k/ath11k: fix spelling mistake "requed" -> "requeued"

-- 
https://patchwork.kernel.org/project/linux-wireless/patch/20210423134133.339751-1-colin.king at canonical.com/

https://wireless.wiki.kernel.org/en/developers/documentation/submittingpatches



From gregkh at linuxfoundation.org  Mon May 24 00:01:49 2021
From: gregkh at linuxfoundation.org (Greg KH)
Date: Mon, 24 May 2021 09:01:49 +0200
Subject: [PATCH v2] bus: mhi: Wait for M2 state during system resume
In-Reply-To: <20210524040312.14409-1-bqiang@codeaurora.org>
References: <20210524040312.14409-1-bqiang@codeaurora.org>
Message-ID: <YKtPXWrTb6Qj+E9l@kroah.com>

On Mon, May 24, 2021 at 12:03:12PM +0800, Baochen Qiang wrote:
> During system resume, MHI host triggers M3->M0 transition and then waits
> for target device to enter M0 state. Once done, the device queues a state
> change event into ctrl event ring and notifies MHI host by raising an
> interrupt, where a tasklet is scheduled to process this event. In most cases,
> the tasklet is served timely and wait operation succeeds.
> 
> However, there are cases where CPU is busy and cannot serve this tasklet
> for some time. Once delay goes long enough, the device moves itself to M1
> state and also interrupts MHI host after inserting a new state change
> event to ctrl ring. Later CPU finally has time to process the ring, however
> there are two events in it now:
> 	1. for M3->M0 event, which is processed first as queued first,
> 	   tasklet handler updates device state to M0 and wakes up the task,
> 	   i.e., the MHI host.
> 	2. for M0->M1 event, which is processed later, tasklet handler
> 	   triggers M1->M2 transition and updates device state to M2 directly,
> 	   then wakes up the MHI host(if still sleeping on this wait queue).
> Note that although MHI host has been woken up while processing the first
> event, it may still has no chance to run before the second event is processed.
> In other words, MHI host has to keep waiting till timeout cause the M0 state
> has been missed.
> 
> kernel log here:
> ...
> Apr 15 01:45:14 test-NUC8i7HVK kernel: [ 4247.911251] mhi 0000:06:00.0: Entered with PM state: M3, MHI state: M3
> Apr 15 01:45:14 test-NUC8i7HVK kernel: [ 4247.917762] mhi 0000:06:00.0: State change event to state: M0
> Apr 15 01:45:14 test-NUC8i7HVK kernel: [ 4247.917767] mhi 0000:06:00.0: State change event to state: M1
> Apr 15 01:45:14 test-NUC8i7HVK kernel: [ 4338.788231] mhi 0000:06:00.0: Did not enter M0 state, MHI state: M2, PM state: M2
> ...
> 
> Fix this issue by simply adding M2 as a valid state for resume.
> 
> Tested-on: WCN6855 hw2.0 PCI WLAN.HSP.1.1-01720.1-QCAHSPSWPL_V1_V2_SILICONZ_LITE-1
> 
> Fixes: 0c6b20a1d720 ("bus: mhi: core: Add support for MHI suspend and resume")
> Signed-off-by: Baochen Qiang <bqiang at codeaurora.org>
> Reviewed-by: Hemant Kumar <hemantk at codeaurora.org>
> ---
>  drivers/bus/mhi/core/pm.c | 1 +
>  1 file changed, 1 insertion(+)

<formletter>

This is not the correct way to submit patches for inclusion in the
stable kernel tree.  Please read:
    https://www.kernel.org/doc/html/latest/process/stable-kernel-rules.html
for how to do this properly.

</formletter>


From manivannan.sadhasivam at linaro.org  Sun May 23 21:37:40 2021
From: manivannan.sadhasivam at linaro.org (Manivannan Sadhasivam)
Date: Mon, 24 May 2021 10:07:40 +0530
Subject: [PATCH v2] bus: mhi: Wait for M2 state during system resume
In-Reply-To: <20210524040312.14409-1-bqiang@codeaurora.org>
References: <20210524040312.14409-1-bqiang@codeaurora.org>
Message-ID: <20210524043740.GC8823@work>

On Mon, May 24, 2021 at 12:03:12PM +0800, Baochen Qiang wrote:
> During system resume, MHI host triggers M3->M0 transition and then waits
> for target device to enter M0 state. Once done, the device queues a state
> change event into ctrl event ring and notifies MHI host by raising an
> interrupt, where a tasklet is scheduled to process this event. In most cases,
> the tasklet is served timely and wait operation succeeds.
> 
> However, there are cases where CPU is busy and cannot serve this tasklet
> for some time. Once delay goes long enough, the device moves itself to M1
> state and also interrupts MHI host after inserting a new state change
> event to ctrl ring. Later CPU finally has time to process the ring, however
> there are two events in it now:
> 	1. for M3->M0 event, which is processed first as queued first,
> 	   tasklet handler updates device state to M0 and wakes up the task,
> 	   i.e., the MHI host.
> 	2. for M0->M1 event, which is processed later, tasklet handler
> 	   triggers M1->M2 transition and updates device state to M2 directly,
> 	   then wakes up the MHI host(if still sleeping on this wait queue).
> Note that although MHI host has been woken up while processing the first
> event, it may still has no chance to run before the second event is processed.
> In other words, MHI host has to keep waiting till timeout cause the M0 state
> has been missed.
> 
> kernel log here:
> ...
> Apr 15 01:45:14 test-NUC8i7HVK kernel: [ 4247.911251] mhi 0000:06:00.0: Entered with PM state: M3, MHI state: M3
> Apr 15 01:45:14 test-NUC8i7HVK kernel: [ 4247.917762] mhi 0000:06:00.0: State change event to state: M0
> Apr 15 01:45:14 test-NUC8i7HVK kernel: [ 4247.917767] mhi 0000:06:00.0: State change event to state: M1
> Apr 15 01:45:14 test-NUC8i7HVK kernel: [ 4338.788231] mhi 0000:06:00.0: Did not enter M0 state, MHI state: M2, PM state: M2
> ...
> 
> Fix this issue by simply adding M2 as a valid state for resume.
> 
> Tested-on: WCN6855 hw2.0 PCI WLAN.HSP.1.1-01720.1-QCAHSPSWPL_V1_V2_SILICONZ_LITE-1
> 
> Fixes: 0c6b20a1d720 ("bus: mhi: core: Add support for MHI suspend and resume")
> Signed-off-by: Baochen Qiang <bqiang at codeaurora.org>
> Reviewed-by: Hemant Kumar <hemantk at codeaurora.org>

Applied to mhi-fixes!

Thanks,
Mani

> ---
>  drivers/bus/mhi/core/pm.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/bus/mhi/core/pm.c b/drivers/bus/mhi/core/pm.c
> index e2e59a341fef..59b009a3ee9b 100644
> --- a/drivers/bus/mhi/core/pm.c
> +++ b/drivers/bus/mhi/core/pm.c
> @@ -934,6 +934,7 @@ int mhi_pm_resume(struct mhi_controller *mhi_cntrl)
>  
>  	ret = wait_event_timeout(mhi_cntrl->state_event,
>  				 mhi_cntrl->dev_state == MHI_STATE_M0 ||
> +				 mhi_cntrl->dev_state == MHI_STATE_M2 ||
>  				 MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state),
>  				 msecs_to_jiffies(mhi_cntrl->timeout_ms));
>  
> -- 
> 2.25.1
> 


From wgong at codeaurora.org  Sun May 23 20:36:24 2021
From: wgong at codeaurora.org (Wen Gong)
Date: Sun, 23 May 2021 23:36:24 -0400
Subject: [PATCH v3] wireless: add check of field VHT Extended NSS BW Capable
 for 160/80+80 MHz setting
Message-ID: <20210524033624.16993-1-wgong@codeaurora.org>

Table 9-251?Supported VHT-MCS and NSS Set subfields, it has subfield VHT Extended
NSS BW Capable, its definition is:
Indicates whether the STA is capable of interpreting the Extended NSS BW
Support subfield of the VHT Capabilities Information field.

This patch is to add check for the subfield.

Signed-off-by: Wen Gong <wgong at codeaurora.org>
---
v3: add __le16_to_cpu for __le16 tx_highest
v2: change code style
 net/wireless/chan.c | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/net/wireless/chan.c b/net/wireless/chan.c
index 285b8076054b..a2d11c801585 100644
--- a/net/wireless/chan.c
+++ b/net/wireless/chan.c
@@ -942,7 +942,7 @@ bool cfg80211_chandef_usable(struct wiphy *wiphy,
 	struct ieee80211_sta_vht_cap *vht_cap;
 	struct ieee80211_edmg *edmg_cap;
 	u32 width, control_freq, cap;
-	bool support_80_80 = false;
+	bool ext_nss_cap, support_80_80 = false;
 
 	if (WARN_ON(!cfg80211_chandef_valid(chandef)))
 		return false;
@@ -950,6 +950,7 @@ bool cfg80211_chandef_usable(struct wiphy *wiphy,
 	ht_cap = &wiphy->bands[chandef->chan->band]->ht_cap;
 	vht_cap = &wiphy->bands[chandef->chan->band]->vht_cap;
 	edmg_cap = &wiphy->bands[chandef->chan->band]->edmg_cap;
+	ext_nss_cap = __le16_to_cpu(vht_cap->vht_mcs.tx_highest) & IEEE80211_VHT_EXT_NSS_BW_CAPABLE;
 
 	if (edmg_cap->channels &&
 	    !cfg80211_edmg_usable(wiphy,
@@ -1015,7 +1016,8 @@ bool cfg80211_chandef_usable(struct wiphy *wiphy,
 			(cap & IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160_80PLUS80MHZ) ||
 			(cap & IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ &&
 			 cap & IEEE80211_VHT_CAP_EXT_NSS_BW_MASK) ||
-			u32_get_bits(cap, IEEE80211_VHT_CAP_EXT_NSS_BW_MASK) > 1;
+			(ext_nss_cap &&
+			 u32_get_bits(cap, IEEE80211_VHT_CAP_EXT_NSS_BW_MASK) > 1);
 		if (chandef->chan->band != NL80211_BAND_6GHZ && !support_80_80)
 			return false;
 		fallthrough;
@@ -1037,7 +1039,7 @@ bool cfg80211_chandef_usable(struct wiphy *wiphy,
 		cap = vht_cap->cap & IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_MASK;
 		if (cap != IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ &&
 		    cap != IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160_80PLUS80MHZ &&
-		    !(vht_cap->cap & IEEE80211_VHT_CAP_EXT_NSS_BW_MASK))
+		    !(ext_nss_cap && (vht_cap->cap & IEEE80211_VHT_CAP_EXT_NSS_BW_MASK)))
 			return false;
 		break;
 	default:
-- 
2.31.1



From manivannan.sadhasivam at linaro.org  Sun May 23 21:15:14 2021
From: manivannan.sadhasivam at linaro.org (Manivannan Sadhasivam)
Date: Mon, 24 May 2021 09:45:14 +0530
Subject: [PATCH v2] bus: mhi: Wait for M2 state during system resume
In-Reply-To: <20210524040312.14409-1-bqiang@codeaurora.org>
References: <20210524040312.14409-1-bqiang@codeaurora.org>
Message-ID: <20210524041514.GA8823@work>

On Mon, May 24, 2021 at 12:03:12PM +0800, Baochen Qiang wrote:
> During system resume, MHI host triggers M3->M0 transition and then waits
> for target device to enter M0 state. Once done, the device queues a state
> change event into ctrl event ring and notifies MHI host by raising an
> interrupt, where a tasklet is scheduled to process this event. In most cases,
> the tasklet is served timely and wait operation succeeds.
> 
> However, there are cases where CPU is busy and cannot serve this tasklet
> for some time. Once delay goes long enough, the device moves itself to M1
> state and also interrupts MHI host after inserting a new state change
> event to ctrl ring. Later CPU finally has time to process the ring, however
> there are two events in it now:
> 	1. for M3->M0 event, which is processed first as queued first,
> 	   tasklet handler updates device state to M0 and wakes up the task,
> 	   i.e., the MHI host.
> 	2. for M0->M1 event, which is processed later, tasklet handler
> 	   triggers M1->M2 transition and updates device state to M2 directly,
> 	   then wakes up the MHI host(if still sleeping on this wait queue).
> Note that although MHI host has been woken up while processing the first
> event, it may still has no chance to run before the second event is processed.
> In other words, MHI host has to keep waiting till timeout cause the M0 state
> has been missed.
> 
> kernel log here:
> ...
> Apr 15 01:45:14 test-NUC8i7HVK kernel: [ 4247.911251] mhi 0000:06:00.0: Entered with PM state: M3, MHI state: M3
> Apr 15 01:45:14 test-NUC8i7HVK kernel: [ 4247.917762] mhi 0000:06:00.0: State change event to state: M0
> Apr 15 01:45:14 test-NUC8i7HVK kernel: [ 4247.917767] mhi 0000:06:00.0: State change event to state: M1
> Apr 15 01:45:14 test-NUC8i7HVK kernel: [ 4338.788231] mhi 0000:06:00.0: Did not enter M0 state, MHI state: M2, PM state: M2
> ...
> 
> Fix this issue by simply adding M2 as a valid state for resume.
> 
> Tested-on: WCN6855 hw2.0 PCI WLAN.HSP.1.1-01720.1-QCAHSPSWPL_V1_V2_SILICONZ_LITE-1
> 
> Fixes: 0c6b20a1d720 ("bus: mhi: core: Add support for MHI suspend and resume")
> Signed-off-by: Baochen Qiang <bqiang at codeaurora.org>
> Reviewed-by: Hemant Kumar <hemantk at codeaurora.org>

Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam at linaro.org>

Thanks,
Mani

> ---
>  drivers/bus/mhi/core/pm.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/bus/mhi/core/pm.c b/drivers/bus/mhi/core/pm.c
> index e2e59a341fef..59b009a3ee9b 100644
> --- a/drivers/bus/mhi/core/pm.c
> +++ b/drivers/bus/mhi/core/pm.c
> @@ -934,6 +934,7 @@ int mhi_pm_resume(struct mhi_controller *mhi_cntrl)
>  
>  	ret = wait_event_timeout(mhi_cntrl->state_event,
>  				 mhi_cntrl->dev_state == MHI_STATE_M0 ||
> +				 mhi_cntrl->dev_state == MHI_STATE_M2 ||
>  				 MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state),
>  				 msecs_to_jiffies(mhi_cntrl->timeout_ms));
>  
> -- 
> 2.25.1
> 


From wgong at codeaurora.org  Tue May 25 03:04:37 2021
From: wgong at codeaurora.org (Wen Gong)
Date: Tue, 25 May 2021 18:04:37 +0800
Subject: [PATCH 0/9] cfg80211/mac80211: Add support for 6GHZ STA for
 various modes : LPI, SP and VLP
In-Reply-To: <20210517201932.8860-1-wgong@codeaurora.org>
References: <20210517201932.8860-1-wgong@codeaurora.org>
Message-ID: <6add42222bd66655fe76ce62676bd105@codeaurora.org>

On 2021-05-18 04:19, Wen Gong wrote:
> It introduced some new concept:
> power type of AP(STANDARD_POWER_AP, INDOOR_AP, VERY_LOW_POWER_AP)
> power type of STATION(DEFAULT_CLIENT, SUBORDINATE_CLIENT)
> power spectral density(psd)
> 
> This patchset for cfg80211/mac80211 is to add the definition of new
> concept of 6G and add basic parse of IE(transmit power envelope
> element) in beacon and save power spectral density(psd) reported
> by lower-driver for 6G channel, the info will be passed to lower
> driver when connecting to 6G AP.
> 
> Wen Gong (9):
>   cfg80211: add power type definition for 6G Hz
>   mac80211: add definition of regulatory info in 6G Hz operation
>     information
>   mac80211: add parse regulatory info in 6G Hz operation information
>   cfg80211: add definition for 6G power spectral density(psd)
>   cfg80211: save power spectral density(psd) of regulatory rule
>   mac80211: add definition for transmit power envelope element
>   mac80211: add parse transmit power envelope element
>   mac80211: add transmit power envelope element and power constraint in
>     bss_conf
>   mac80211: save transmit power envelope element and power constraint
> 
...
Nobody have comments?


From sven at narfation.org  Tue May 25 06:30:28 2021
From: sven at narfation.org (Sven Eckelmann)
Date: Tue, 25 May 2021 15:30:28 +0200
Subject: [PATCH] ath11k: send beacon template after vdev_start/restart during
 csa
Message-ID: <20210525133028.2805615-1-sven@narfation.org>

From: Seevalamuthu Mariappan <seevalam at codeaurora.org>

Firmware has added assert if beacon template is received after
vdev_down. Firmware expects beacon template after vdev_start
and before vdev_up. This change is needed to support MBSSID EMA
cases in firmware.

Hence, Change the sequence in ath11k as expected from firmware.
This new change is not causing any issues with older
firmware.

Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.5.0.1.r3-00011-QCAHKSWPL_SILICONZ-1
Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.5.0.1.r4-00008-QCAHKSWPL_SILICONZ-1

Fixes: d5c65159f289 ("ath11k: driver for Qualcomm IEEE 802.11ax devices")
Signed-off-by: Seevalamuthu Mariappan <seevalam at codeaurora.org>
[sven at narfation.org: added tested-on/fixes information]
Signed-off-by: Sven Eckelmann <sven at narfation.org>
---
Patch from
https://source.codeaurora.org/quic/cc-qrdk/oss/system/feeds/wlan-open/tree/mac80211/patches/303-ath11k-send-beacon-template-after-vdev_start-restart.patch?h=NHSS.QSDK.11.4.0.5.r5

There are a lot more fixes which should have been submitted to upstream by
the actual developer

 drivers/net/wireless/ath/ath11k/mac.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/net/wireless/ath/ath11k/mac.c b/drivers/net/wireless/ath/ath11k/mac.c
index 9d0ff150ec30..eb52332dbe3f 100644
--- a/drivers/net/wireless/ath/ath11k/mac.c
+++ b/drivers/net/wireless/ath/ath11k/mac.c
@@ -5379,11 +5379,6 @@ ath11k_mac_update_vif_chan(struct ath11k *ar,
 		if (WARN_ON(!arvif->is_up))
 			continue;
 
-		ret = ath11k_mac_setup_bcn_tmpl(arvif);
-		if (ret)
-			ath11k_warn(ab, "failed to update bcn tmpl during csa: %d\n",
-				    ret);
-
 		ret = ath11k_mac_vdev_restart(arvif, &vifs[i].new_ctx->def);
 		if (ret) {
 			ath11k_warn(ab, "failed to restart vdev %d: %d\n",
@@ -5391,6 +5386,11 @@ ath11k_mac_update_vif_chan(struct ath11k *ar,
 			continue;
 		}
 
+		ret = ath11k_mac_setup_bcn_tmpl(arvif);
+		if (ret)
+			ath11k_warn(ab, "failed to update bcn tmpl during csa: %d\n",
+				    ret);
+
 		ret = ath11k_wmi_vdev_up(arvif->ar, arvif->vdev_id, arvif->aid,
 					 arvif->bssid);
 		if (ret) {
-- 
2.30.2



From mkenna at codeaurora.org  Wed May 26 07:13:40 2021
From: mkenna at codeaurora.org (Maharaja Kennadyrajan)
Date: Wed, 26 May 2021 19:43:40 +0530
Subject: [PATCH v2 0/3] Add support to configure beacon tx mode
In-Reply-To: <4581459.tLtf2NohVe@ripper>
References: <1619696874-30072-1-git-send-email-mkenna@codeaurora.org>
 <4581459.tLtf2NohVe@ripper>
Message-ID: <4038b2868605da158392bd4c65d10c66@codeaurora.org>

On 2021-04-30 12:45, Sven Eckelmann wrote:
> On Thursday, 29 April 2021 13:47:51 CEST Maharaja Kennadyrajan wrote:
> [...]
>> Beacons can be sent out in burst(continuously in a single shot
>> one after another) or staggered (equally spread out over beacon
>> interval) mode.
>> 
>> V2:
>> 	Addressed Johannes's comment on v1 patch.
>> 	Updated the commit log.
> 
> Still it is advertised as vif setting but the code itself shows that it 
> is a
> phy setting (as you would expect). Or is it a potential feature for a 
> device
> to send some beacons staggered and some beacons as burst?

[Maha]: No, it won't allow to send some beacons in staggered and some 
beacons in burst
mode. It will send either staggered or burst mode at a time in a device.

> Kind regards,
> 	Sven


From lkp at intel.com  Sat May 22 11:36:31 2021
From: lkp at intel.com (kernel test robot)
Date: Sun, 23 May 2021 02:36:31 +0800
Subject: [PATCH v2] wireless: add check of field VHT Extended NSS BW
 Capable for 160/80+80 MHz setting
In-Reply-To: <20210521021809.23986-1-wgong@codeaurora.org>
References: <20210521021809.23986-1-wgong@codeaurora.org>
Message-ID: <202105230249.n4ifN4Wm-lkp@intel.com>

Hi Wen,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on mac80211-next/master]
[also build test WARNING on mac80211/master v5.13-rc2 next-20210521]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:    https://github.com/0day-ci/linux/commits/Wen-Gong/wireless-add-check-of-field-VHT-Extended-NSS-BW-Capable-for-160-80-80-MHz-setting/20210522-224810
base:   https://git.kernel.org/pub/scm/linux/kernel/git/jberg/mac80211-next.git master
config: i386-randconfig-s001-20210522 (attached as .config)
compiler: gcc-9 (Debian 9.3.0-22) 9.3.0
reproduce:
        # apt-get install sparse
        # sparse version: v0.6.3-341-g8af24329-dirty
        # https://github.com/0day-ci/linux/commit/ed41c78effa1b66bb3d00e368b92940e5ffadb57
        git remote add linux-review https://github.com/0day-ci/linux
        git fetch --no-tags linux-review Wen-Gong/wireless-add-check-of-field-VHT-Extended-NSS-BW-Capable-for-160-80-80-MHz-setting/20210522-224810
        git checkout ed41c78effa1b66bb3d00e368b92940e5ffadb57
        # save the attached .config to linux build tree
        make W=1 C=1 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__' W=1 ARCH=i386 

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp at intel.com>


sparse warnings: (new ones prefixed by >>)
>> net/wireless/chan.c:953:39: sparse: sparse: restricted __le16 degrades to integer

vim +953 net/wireless/chan.c

   936	
   937	bool cfg80211_chandef_usable(struct wiphy *wiphy,
   938				     const struct cfg80211_chan_def *chandef,
   939				     u32 prohibited_flags)
   940	{
   941		struct ieee80211_sta_ht_cap *ht_cap;
   942		struct ieee80211_sta_vht_cap *vht_cap;
   943		struct ieee80211_edmg *edmg_cap;
   944		u32 width, control_freq, cap;
   945		bool ext_nss_cap, support_80_80 = false;
   946	
   947		if (WARN_ON(!cfg80211_chandef_valid(chandef)))
   948			return false;
   949	
   950		ht_cap = &wiphy->bands[chandef->chan->band]->ht_cap;
   951		vht_cap = &wiphy->bands[chandef->chan->band]->vht_cap;
   952		edmg_cap = &wiphy->bands[chandef->chan->band]->edmg_cap;
 > 953		ext_nss_cap = vht_cap->vht_mcs.tx_highest & IEEE80211_VHT_EXT_NSS_BW_CAPABLE;
   954	
   955		if (edmg_cap->channels &&
   956		    !cfg80211_edmg_usable(wiphy,
   957					  chandef->edmg.channels,
   958					  chandef->edmg.bw_config,
   959					  chandef->chan->hw_value,
   960					  edmg_cap))
   961			return false;
   962	
   963		control_freq = chandef->chan->center_freq;
   964	
   965		switch (chandef->width) {
   966		case NL80211_CHAN_WIDTH_1:
   967			width = 1;
   968			break;
   969		case NL80211_CHAN_WIDTH_2:
   970			width = 2;
   971			break;
   972		case NL80211_CHAN_WIDTH_4:
   973			width = 4;
   974			break;
   975		case NL80211_CHAN_WIDTH_8:
   976			width = 8;
   977			break;
   978		case NL80211_CHAN_WIDTH_16:
   979			width = 16;
   980			break;
   981		case NL80211_CHAN_WIDTH_5:
   982			width = 5;
   983			break;
   984		case NL80211_CHAN_WIDTH_10:
   985			prohibited_flags |= IEEE80211_CHAN_NO_10MHZ;
   986			width = 10;
   987			break;
   988		case NL80211_CHAN_WIDTH_20:
   989			if (!ht_cap->ht_supported &&
   990			    chandef->chan->band != NL80211_BAND_6GHZ)
   991				return false;
   992			fallthrough;
   993		case NL80211_CHAN_WIDTH_20_NOHT:
   994			prohibited_flags |= IEEE80211_CHAN_NO_20MHZ;
   995			width = 20;
   996			break;
   997		case NL80211_CHAN_WIDTH_40:
   998			width = 40;
   999			if (chandef->chan->band == NL80211_BAND_6GHZ)
  1000				break;
  1001			if (!ht_cap->ht_supported)
  1002				return false;
  1003			if (!(ht_cap->cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40) ||
  1004			    ht_cap->cap & IEEE80211_HT_CAP_40MHZ_INTOLERANT)
  1005				return false;
  1006			if (chandef->center_freq1 < control_freq &&
  1007			    chandef->chan->flags & IEEE80211_CHAN_NO_HT40MINUS)
  1008				return false;
  1009			if (chandef->center_freq1 > control_freq &&
  1010			    chandef->chan->flags & IEEE80211_CHAN_NO_HT40PLUS)
  1011				return false;
  1012			break;
  1013		case NL80211_CHAN_WIDTH_80P80:
  1014			cap = vht_cap->cap;
  1015			support_80_80 =
  1016				(cap & IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160_80PLUS80MHZ) ||
  1017				(cap & IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ &&
  1018				 cap & IEEE80211_VHT_CAP_EXT_NSS_BW_MASK) ||
  1019				(ext_nss_cap &&
  1020				 u32_get_bits(cap, IEEE80211_VHT_CAP_EXT_NSS_BW_MASK) > 1);
  1021			if (chandef->chan->band != NL80211_BAND_6GHZ && !support_80_80)
  1022				return false;
  1023			fallthrough;
  1024		case NL80211_CHAN_WIDTH_80:
  1025			prohibited_flags |= IEEE80211_CHAN_NO_80MHZ;
  1026			width = 80;
  1027			if (chandef->chan->band == NL80211_BAND_6GHZ)
  1028				break;
  1029			if (!vht_cap->vht_supported)
  1030				return false;
  1031			break;
  1032		case NL80211_CHAN_WIDTH_160:
  1033			prohibited_flags |= IEEE80211_CHAN_NO_160MHZ;
  1034			width = 160;
  1035			if (chandef->chan->band == NL80211_BAND_6GHZ)
  1036				break;
  1037			if (!vht_cap->vht_supported)
  1038				return false;
  1039			cap = vht_cap->cap & IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_MASK;
  1040			if (cap != IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ &&
  1041			    cap != IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160_80PLUS80MHZ &&
  1042			    !(ext_nss_cap && (vht_cap->cap & IEEE80211_VHT_CAP_EXT_NSS_BW_MASK)))
  1043				return false;
  1044			break;
  1045		default:
  1046			WARN_ON_ONCE(1);
  1047			return false;
  1048		}
  1049	
  1050		/*
  1051		 * TODO: What if there are only certain 80/160/80+80 MHz channels
  1052		 *	 allowed by the driver, or only certain combinations?
  1053		 *	 For 40 MHz the driver can set the NO_HT40 flags, but for
  1054		 *	 80/160 MHz and in particular 80+80 MHz this isn't really
  1055		 *	 feasible and we only have NO_80MHZ/NO_160MHZ so far but
  1056		 *	 no way to cover 80+80 MHz or more complex restrictions.
  1057		 *	 Note that such restrictions also need to be advertised to
  1058		 *	 userspace, for example for P2P channel selection.
  1059		 */
  1060	
  1061		if (width > 20)
  1062			prohibited_flags |= IEEE80211_CHAN_NO_OFDM;
  1063	
  1064		/* 5 and 10 MHz are only defined for the OFDM PHY */
  1065		if (width < 20)
  1066			prohibited_flags |= IEEE80211_CHAN_NO_OFDM;
  1067	
  1068	
  1069		if (!cfg80211_secondary_chans_ok(wiphy,
  1070						 ieee80211_chandef_to_khz(chandef),
  1071						 width, prohibited_flags))
  1072			return false;
  1073	
  1074		if (!chandef->center_freq2)
  1075			return true;
  1076		return cfg80211_secondary_chans_ok(wiphy,
  1077						   MHZ_TO_KHZ(chandef->center_freq2),
  1078						   width, prohibited_flags);
  1079	}
  1080	EXPORT_SYMBOL(cfg80211_chandef_usable);
  1081	

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all at lists.01.org
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From wgong at codeaurora.org  Sun May 30 20:04:33 2021
From: wgong at codeaurora.org (Wen Gong)
Date: Mon, 31 May 2021 11:04:33 +0800
Subject: [PATCH v2] wireless: add check of field VHT Extended NSS BW
 Capable for 160/80+80 MHz setting
In-Reply-To: <202105230249.n4ifN4Wm-lkp@intel.com>
References: <20210521021809.23986-1-wgong@codeaurora.org>
 <202105230249.n4ifN4Wm-lkp@intel.com>
Message-ID: <6dedc959bd3b7515a7e151ea4dae2964@codeaurora.org>

On 2021-05-23 02:36, kernel test robot wrote:
> Hi Wen,
> 
> Thank you for the patch! Perhaps something to improve:
> 
> [auto build test WARNING on mac80211-next/master]
> [also build test WARNING on mac80211/master v5.13-rc2 next-20210521]
> [If your patch is applied to the wrong git tree, kindly drop us a note.
> And when submitting patch, we suggest to use '--base' as documented in
> https://git-scm.com/docs/git-format-patch]
> 
> url:
> https://github.com/0day-ci/linux/commits/Wen-Gong/wireless-add-check-of-field-VHT-Extended-NSS-BW-Capable-for-160-80-80-MHz-setting/20210522-224810
> base:
> https://git.kernel.org/pub/scm/linux/kernel/git/jberg/mac80211-next.git
> master
> config: i386-randconfig-s001-20210522 (attached as .config)
> compiler: gcc-9 (Debian 9.3.0-22) 9.3.0
> reproduce:
>         # apt-get install sparse
>         # sparse version: v0.6.3-341-g8af24329-dirty
>         #
> https://github.com/0day-ci/linux/commit/ed41c78effa1b66bb3d00e368b92940e5ffadb57
>         git remote add linux-review https://github.com/0day-ci/linux
>         git fetch --no-tags linux-review
> Wen-Gong/wireless-add-check-of-field-VHT-Extended-NSS-BW-Capable-for-160-80-80-MHz-setting/20210522-224810
>         git checkout ed41c78effa1b66bb3d00e368b92940e5ffadb57
>         # save the attached .config to linux build tree
>         make W=1 C=1 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__' W=1 
> ARCH=i386
> 
> If you fix the issue, kindly add following tag as appropriate
> Reported-by: kernel test robot <lkp at intel.com>
> 
> 
> sparse warnings: (new ones prefixed by >>)
>>> net/wireless/chan.c:953:39: sparse: sparse: restricted __le16 
>>> degrades to integer
> 

please use new patch: "[PATCH v3] wireless: add check of field VHT 
Extended NSS BW Capable for 160/80+80 MHz setting"

...


From kvalo at codeaurora.org  Mon May 31 08:09:15 2021
From: kvalo at codeaurora.org (Kalle Valo)
Date: Mon, 31 May 2021 15:09:15 +0000 (UTC)
Subject: [PATCH 1/7] ath11k: add hw reg support for WCN6855
In-Reply-To: <20210511162214.29475-2-jouni@codeaurora.org>
References: <20210511162214.29475-2-jouni@codeaurora.org>
Message-ID: <20210531150915.535F1C433D3@smtp.codeaurora.org>

Jouni Malinen <jouni at codeaurora.org> wrote:

> Reg address of WCN6855 is different from other devices,
> so add separate reg definition for this target.
> 
> Tested-on: WCN6855 hw2.0 PCI WLAN.HSP.1.1-01720.1-QCAHSPSWPL_V1_V2_SILICONZ_LITE-1
> 
> Signed-off-by: Govind Singh <govinds at codeaurora.org>
> Signed-off-by: Baochen Qiang <bqiang at codeaurora.org>
> Signed-off-by: Jouni Malinen <jouni at codeaurora.org>
> Signed-off-by: Kalle Valo <kvalo at codeaurora.org>

This patchset had some warnings from ath11k-check:

drivers/net/wireless/ath/ath11k/pci.c:1229: line length of 93 exceeds 90 columns
drivers/net/wireless/ath/ath11k/pci.c:1248: line length of 93 exceeds 90 columns
drivers/net/wireless/ath/ath11k/hal_rx.c:804: Please don't use multiple blank lines

I fixed them in the pending branch.

-- 
https://patchwork.kernel.org/project/linux-wireless/patch/20210511162214.29475-2-jouni at codeaurora.org/

https://wireless.wiki.kernel.org/en/developers/documentation/submittingpatches



