[PATCH V2] ath10k: Delay device access after cold reset

Kalle Valo kvalo at qca.qualcomm.com
Fri Jul 24 00:44:02 PDT 2015

Vasanthakumar Thiagarajan <vthiagar at qti.qualcomm.com> writes:

> It is observed that during cold reset pcie access right
> after a write operation to SOC_GLOBAL_RESET_ADDRESS causes
> Data Bus Error and system hard lockup. The reason
> for bus error is that pcie needs some time to get
> back to stable state for any transaction during cold reset. Add
> delay of 20 msecs after write of SOC_GLOBAL_RESET_ADDRESS
> to fix this issue. This patch is tested on QCA988X. This is
> also tested on QCA99X0 which is WIP.
> Signed-off-by: Vasanthakumar Thiagarajan <vthiagar at qti.qualcomm.com>

Thanks, applied.

Kalle Valo

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