[PATCH] ath10k: Delay device access after cold reset

Kalle Valo kvalo at qca.qualcomm.com
Fri Jul 10 01:48:51 PDT 2015

Vasanthakumar Thiagarajan <vthiagar at qti.qualcomm.com> writes:

> It is observed that during cold reset pcie access right
> after a write operation to SOC_GLOBAL_RESET_ADDRESS causes
> Data Bus Error and system hard lockup. The reason
> for bus error is that pcie needs some time to get
> back to stable state for any transaction during cold reset. Add
> delay of 20 msecs after write of SOC_GLOBAL_RESET_ADDRESS
> to fix this issue.
> Signed-off-by: Vasanthakumar Thiagarajan <vthiagar at qti.qualcomm.com>

On what devices did you test this? That should be documented in the
commit log.

Kalle Valo

More information about the ath10k mailing list