[PATCH 1/2] ath10k: improve warm reset reliability

[Michal Kazior]

On 15 May 2014 12:48, Kalle Valo <kvalo at qca.qualcomm.com> wrote:
> Michal Kazior <michal.kazior at tieto.com> writes:
>
>> Warm reset is now able to recover after device
>> crashes which required a cold reset before.
>>
>> This should greatly reduce chances of getting data
>> bus errors or host system freezes due to buggy
>> cold reset on some chips.
>>
>> Signed-off-by: Michal Kazior <michal.kazior at tieto.com>
>
> Awesome! This is very much needed. I just have a cosmetic comment:
>
>> +/* this function effectively clears target memory controller assert line */
>> +static void ath10k_pci_warm_reset_si0(struct ath10k *ar)
>> +{
>> +     u32 val;
>> +
>> +     val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS +
>> +                             SOC_RESET_CONTROL_ADDRESS);
>> +     ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + SOC_RESET_CONTROL_ADDRESS,
>> +                        val | SOC_RESET_CONTROL_SI0_RST_MASK);
>> +     val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS +
>> +                             SOC_RESET_CONTROL_ADDRESS);
>
> We do have the ath10k_pci_soc_ functions for accessing SOC registers, I
> would prefer to use those here. I now modified your patch with the diff
> below. Is that ok to you?

Ah, yeah. I totally forgot about these functions (again).


> --- a/drivers/net/wireless/ath/ath10k/pci.c
> +++ b/drivers/net/wireless/ath/ath10k/pci.c
> @@ -1807,20 +1807,18 @@ static void ath10k_pci_warm_reset_si0(struct ath10k *ar)
>  {
>         u32 val;
>
> -       val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS +
> -                               SOC_RESET_CONTROL_ADDRESS);
> -       ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + SOC_RESET_CONTROL_ADDRESS,
> -                          val | SOC_RESET_CONTROL_SI0_RST_MASK);
> -       val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS +
> -                               SOC_RESET_CONTROL_ADDRESS);
> +       val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS);
> +       ath10k_pci_soc_write32(ar, SOC_RESET_CONTROL_ADDRESS,
> +                              val | SOC_RESET_CONTROL_SI0_RST_MASK);
> +       val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS);
> +
>         msleep(10);
>
> -       val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS +
> -                               SOC_RESET_CONTROL_ADDRESS);
> -       ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + SOC_RESET_CONTROL_ADDRESS,
> -                          val & ~SOC_RESET_CONTROL_SI0_RST_MASK);
> -       val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS +
> -                               SOC_RESET_CONTROL_ADDRESS);
> +       val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS);
> +       ath10k_pci_soc_write32(ar, SOC_RESET_CONTROL_ADDRESS,
> +                              val & ~SOC_RESET_CONTROL_SI0_RST_MASK);
> +       val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS);
> +
>         msleep(10);
>  }

Looks good to me :-)


> Full patch here:
>
> https://github.com/kvalo/ath/commit/7b52054308a371d479a9e686e1d8411d19a90fd7

You probably mean:

https://github.com/kvalo/ath/commit/136ef8110cba61752eee5ef6bd7ce170b15cf491


Michał